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linux: update 3.0 to 3.0.12
[openwrt.git] / target / linux / generic / patches-2.6.38 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -1192,10 +1192,10 @@ void ssb_device_enable(struct ssb_device
4 }
5 EXPORT_SYMBOL(ssb_device_enable);
6
7 -/* Wait for a bit in a register to get set or unset.
8 +/* Wait for bitmask in a register to get set or cleared.
9 * timeout is in units of ten-microseconds */
10 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
11 - int timeout, int set)
12 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
13 + int timeout, int set)
14 {
15 int i;
16 u32 val;
17 @@ -1203,7 +1203,7 @@ static int ssb_wait_bit(struct ssb_devic
18 for (i = 0; i < timeout; i++) {
19 val = ssb_read32(dev, reg);
20 if (set) {
21 - if (val & bitmask)
22 + if ((val & bitmask) == bitmask)
23 return 0;
24 } else {
25 if (!(val & bitmask))
26 @@ -1220,20 +1220,38 @@ static int ssb_wait_bit(struct ssb_devic
27
28 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
29 {
30 - u32 reject;
31 + u32 reject, val;
32
33 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
34 return;
35
36 reject = ssb_tmslow_reject_bitmask(dev);
37 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
38 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
39 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
40 - ssb_write32(dev, SSB_TMSLOW,
41 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
42 - reject | SSB_TMSLOW_RESET |
43 - core_specific_flags);
44 - ssb_flush_tmslow(dev);
45 +
46 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
47 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
48 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
49 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
50 +
51 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
52 + val = ssb_read32(dev, SSB_IMSTATE);
53 + val |= SSB_IMSTATE_REJECT;
54 + ssb_write32(dev, SSB_IMSTATE, val);
55 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
56 + 0);
57 + }
58 +
59 + ssb_write32(dev, SSB_TMSLOW,
60 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
61 + reject | SSB_TMSLOW_RESET |
62 + core_specific_flags);
63 + ssb_flush_tmslow(dev);
64 +
65 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
66 + val = ssb_read32(dev, SSB_IMSTATE);
67 + val &= ~SSB_IMSTATE_REJECT;
68 + ssb_write32(dev, SSB_IMSTATE, val);
69 + }
70 + }
71
72 ssb_write32(dev, SSB_TMSLOW,
73 reject | SSB_TMSLOW_RESET |
74 --- a/drivers/ssb/pci.c
75 +++ b/drivers/ssb/pci.c
76 @@ -468,10 +468,14 @@ static void sprom_extract_r45(struct ssb
77 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
78 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
79 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
80 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
81 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
82 } else {
83 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
84 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
85 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
86 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
87 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
88 }
89 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
90 SSB_SPROM4_ANTAVAIL_A_SHIFT);
91 @@ -641,7 +645,7 @@ static int sprom_extract(struct ssb_bus
92 break;
93 default:
94 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
95 - " revision %d detected. Will extract"
96 + " revision %d detected. Will extract"
97 " v1\n", out->revision);
98 out->revision = 1;
99 sprom_extract_r123(out, in);
100 --- a/include/linux/ssb/ssb_regs.h
101 +++ b/include/linux/ssb/ssb_regs.h
102 @@ -85,6 +85,8 @@
103 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
104 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
105 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
106 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
107 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
108 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
109 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
110 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
111 @@ -97,7 +99,6 @@
112 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
113 #define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
114 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
115 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
116 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
117 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
118 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
119 @@ -268,6 +269,8 @@
120 /* SPROM Revision 4 */
121 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
122 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
123 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
124 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
125 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
126 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
127 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
128 @@ -358,6 +361,8 @@
129 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
130 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
131 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
132 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
133 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
134 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
135 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
136 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
137 diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
138 index 7c031fd..06d15b6 100644
139 --- a/drivers/ssb/driver_chipcommon.c
140 +++ b/drivers/ssb/driver_chipcommon.c
141 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
142 if (!ccdev)
143 return;
144 bus = ccdev->bus;
145 +
146 + /* We support SLOW only on 6..9 */
147 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
148 + mode = SSB_CLKMODE_DYNAMIC;
149 +
150 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
151 + return; /* PMU controls clockmode, separated function needed */
152 + SSB_WARN_ON(ccdev->id.revision >= 20);
153 +
154 /* chipcommon cores prior to rev6 don't support dynamic clock control */
155 if (ccdev->id.revision < 6)
156 return;
157 - /* chipcommon cores rev10 are a whole new ball game */
158 +
159 + /* ChipCommon cores rev10+ need testing */
160 if (ccdev->id.revision >= 10)
161 return;
162 +
163 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
164 return;
165
166 switch (mode) {
167 - case SSB_CLKMODE_SLOW:
168 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
169 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
170 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
171 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
172 break;
173 case SSB_CLKMODE_FAST:
174 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
175 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
176 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
177 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
178 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
179 + if (ccdev->id.revision < 10) {
180 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
181 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
182 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
183 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
184 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
185 + } else {
186 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
187 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
188 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
189 + /* udelay(150); TODO: not available in early init */
190 + }
191 break;
192 case SSB_CLKMODE_DYNAMIC:
193 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
194 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
195 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
196 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
197 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
198 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
199 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
200 -
201 - /* for dynamic control, we have to release our xtal_pu "force on" */
202 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
203 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
204 + if (ccdev->id.revision < 10) {
205 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
206 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
207 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
208 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
209 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
210 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
211 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
212 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
213 +
214 + /* For dynamic control, we have to release our xtal_pu
215 + * "force on" */
216 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
217 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
218 + } else {
219 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
220 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
221 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
222 + }
223 break;
224 default:
225 SSB_WARN_ON(1);
226 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
227 if (cc->dev->id.revision >= 11)
228 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
229 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
230 +
231 + if (cc->dev->id.revision >= 20) {
232 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
233 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
234 + }
235 +
236 ssb_pmu_init(cc);
237 chipco_powercontrol_init(cc);
238 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
239 diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
240 index 5732bb2..a7aef47 100644
241 --- a/drivers/ssb/driver_chipcommon_pmu.c
242 +++ b/drivers/ssb/driver_chipcommon_pmu.c
243 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
244 u32 min_msk = 0, max_msk = 0;
245 unsigned int i;
246 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
247 - unsigned int updown_tab_size;
248 + unsigned int updown_tab_size = 0;
249 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
250 - unsigned int depend_tab_size;
251 + unsigned int depend_tab_size = 0;
252
253 switch (bus->chip_id) {
254 case 0x4312:
255 + min_msk = 0xCBB;
256 + break;
257 case 0x4322:
258 /* We keep the default settings:
259 * min_msk = 0xCBB
260 diff --git a/drivers/ssb/driver_gige.c b/drivers/ssb/driver_gige.c
261 index 5ba92a2..d758909 100644
262 --- a/drivers/ssb/driver_gige.c
263 +++ b/drivers/ssb/driver_gige.c
264 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige *dev,
265 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
266 }
267
268 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
269 - int reg, int size, u32 *val)
270 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
271 + unsigned int devfn, int reg,
272 + int size, u32 *val)
273 {
274 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
275 unsigned long flags;
276 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
277 return PCIBIOS_SUCCESSFUL;
278 }
279
280 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
281 - int reg, int size, u32 val)
282 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
283 + unsigned int devfn, int reg,
284 + int size, u32 val)
285 {
286 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
287 unsigned long flags;
288 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
289 return PCIBIOS_SUCCESSFUL;
290 }
291
292 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
293 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
294 + const struct ssb_device_id *id)
295 {
296 struct ssb_gige *dev;
297 u32 base, tmslow, tmshigh;
298 diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
299 index 0e8d352..11d85bf 100644
300 --- a/drivers/ssb/driver_pcicore.c
301 +++ b/drivers/ssb/driver_pcicore.c
302 @@ -15,6 +15,11 @@
303
304 #include "ssb_private.h"
305
306 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
307 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
308 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
309 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
310 + u8 address, u16 data);
311
312 static inline
313 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
314 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
315 return ssb_mips_irq(extpci_core->dev) + 2;
316 }
317
318 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
319 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
320 {
321 u32 val;
322
323 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
324 register_pci_controller(&ssb_pcicore_controller);
325 }
326
327 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
328 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
329 {
330 struct ssb_bus *bus = pc->dev->bus;
331 u16 chipid_top;
332 @@ -403,25 +408,133 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
333 }
334 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
335
336 +/**************************************************
337 + * Workarounds.
338 + **************************************************/
339 +
340 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
341 +{
342 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
343 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
344 + tmp &= ~0xF000;
345 + tmp |= (pc->dev->core_index << 12);
346 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
347 + }
348 +}
349 +
350 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
351 +{
352 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
353 +}
354 +
355 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
356 +{
357 + const u8 serdes_pll_device = 0x1D;
358 + const u8 serdes_rx_device = 0x1F;
359 + u16 tmp;
360 +
361 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
362 + ssb_pcicore_polarity_workaround(pc));
363 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
364 + if (tmp & 0x4000)
365 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
366 +}
367 +
368 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
369 +{
370 + struct ssb_device *pdev = pc->dev;
371 + struct ssb_bus *bus = pdev->bus;
372 + u32 tmp;
373 +
374 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
375 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
376 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
377 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
378 +
379 + if (pdev->id.revision < 5) {
380 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
381 + tmp &= ~SSB_IMCFGLO_SERTO;
382 + tmp |= 2;
383 + tmp &= ~SSB_IMCFGLO_REQTO;
384 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
385 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
386 + ssb_commit_settings(bus);
387 + } else if (pdev->id.revision >= 11) {
388 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
389 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
390 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
391 + }
392 +}
393 +
394 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
395 +{
396 + u32 tmp;
397 + u8 rev = pc->dev->id.revision;
398 +
399 + if (rev == 0 || rev == 1) {
400 + /* TLP Workaround register. */
401 + tmp = ssb_pcie_read(pc, 0x4);
402 + tmp |= 0x8;
403 + ssb_pcie_write(pc, 0x4, tmp);
404 + }
405 + if (rev == 1) {
406 + /* DLLP Link Control register. */
407 + tmp = ssb_pcie_read(pc, 0x100);
408 + tmp |= 0x40;
409 + ssb_pcie_write(pc, 0x100, tmp);
410 + }
411 +
412 + if (rev == 0) {
413 + const u8 serdes_rx_device = 0x1F;
414 +
415 + ssb_pcie_mdio_write(pc, serdes_rx_device,
416 + 2 /* Timer */, 0x8128);
417 + ssb_pcie_mdio_write(pc, serdes_rx_device,
418 + 6 /* CDR */, 0x0100);
419 + ssb_pcie_mdio_write(pc, serdes_rx_device,
420 + 7 /* CDR BW */, 0x1466);
421 + } else if (rev == 3 || rev == 4 || rev == 5) {
422 + /* TODO: DLLP Power Management Threshold */
423 + ssb_pcicore_serdes_workaround(pc);
424 + /* TODO: ASPM */
425 + } else if (rev == 7) {
426 + /* TODO: No PLL down */
427 + }
428 +
429 + if (rev >= 6) {
430 + /* Miscellaneous Configuration Fixup */
431 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
432 + if (!(tmp & 0x8000))
433 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
434 + tmp | 0x8000);
435 + }
436 +}
437
438 /**************************************************
439 * Generic and Clientmode operation code.
440 **************************************************/
441
442 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
443 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
444 {
445 + ssb_pcicore_fix_sprom_core_index(pc);
446 +
447 /* Disable PCI interrupts. */
448 ssb_write32(pc->dev, SSB_INTVEC, 0);
449 +
450 + /* Additional PCIe always once-executed workarounds */
451 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
452 + ssb_pcicore_serdes_workaround(pc);
453 + /* TODO: ASPM */
454 + /* TODO: Clock Request Update */
455 + }
456 }
457
458 -void ssb_pcicore_init(struct ssb_pcicore *pc)
459 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
460 {
461 struct ssb_device *dev = pc->dev;
462 - struct ssb_bus *bus;
463
464 if (!dev)
465 return;
466 - bus = dev->bus;
467 if (!ssb_device_is_enabled(dev))
468 ssb_device_enable(dev, 0);
469
470 @@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
471 pcicore_write32(pc, 0x134, data);
472 }
473
474 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
475 - u8 address, u16 data)
476 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
477 +{
478 + const u16 mdio_control = 0x128;
479 + const u16 mdio_data = 0x12C;
480 + u32 v;
481 + int i;
482 +
483 + v = (1 << 30); /* Start of Transaction */
484 + v |= (1 << 28); /* Write Transaction */
485 + v |= (1 << 17); /* Turnaround */
486 + v |= (0x1F << 18);
487 + v |= (phy << 4);
488 + pcicore_write32(pc, mdio_data, v);
489 +
490 + udelay(10);
491 + for (i = 0; i < 200; i++) {
492 + v = pcicore_read32(pc, mdio_control);
493 + if (v & 0x100 /* Trans complete */)
494 + break;
495 + msleep(1);
496 + }
497 +}
498 +
499 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
500 {
501 const u16 mdio_control = 0x128;
502 const u16 mdio_data = 0x12C;
503 + int max_retries = 10;
504 + u16 ret = 0;
505 u32 v;
506 int i;
507
508 @@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
509 v |= 0x2; /* MDIO Clock Divisor */
510 pcicore_write32(pc, mdio_control, v);
511
512 + if (pc->dev->id.revision >= 10) {
513 + max_retries = 200;
514 + ssb_pcie_mdio_set_phy(pc, device);
515 + }
516 +
517 v = (1 << 30); /* Start of Transaction */
518 - v |= (1 << 28); /* Write Transaction */
519 + v |= (1 << 29); /* Read Transaction */
520 v |= (1 << 17); /* Turnaround */
521 - v |= (u32)device << 22;
522 + if (pc->dev->id.revision < 10)
523 + v |= (u32)device << 22;
524 v |= (u32)address << 18;
525 - v |= data;
526 pcicore_write32(pc, mdio_data, v);
527 /* Wait for the device to complete the transaction */
528 udelay(10);
529 - for (i = 0; i < 10; i++) {
530 + for (i = 0; i < max_retries; i++) {
531 v = pcicore_read32(pc, mdio_control);
532 - if (v & 0x100 /* Trans complete */)
533 + if (v & 0x100 /* Trans complete */) {
534 + udelay(10);
535 + ret = pcicore_read32(pc, mdio_data);
536 break;
537 + }
538 msleep(1);
539 }
540 pcicore_write32(pc, mdio_control, 0);
541 + return ret;
542 }
543
544 -static void ssb_broadcast_value(struct ssb_device *dev,
545 - u32 address, u32 data)
546 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
547 + u8 address, u16 data)
548 {
549 - /* This is used for both, PCI and ChipCommon core, so be careful. */
550 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
551 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
552 -
553 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
554 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
555 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
556 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
557 -}
558 + const u16 mdio_control = 0x128;
559 + const u16 mdio_data = 0x12C;
560 + int max_retries = 10;
561 + u32 v;
562 + int i;
563
564 -static void ssb_commit_settings(struct ssb_bus *bus)
565 -{
566 - struct ssb_device *dev;
567 + v = 0x80; /* Enable Preamble Sequence */
568 + v |= 0x2; /* MDIO Clock Divisor */
569 + pcicore_write32(pc, mdio_control, v);
570
571 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
572 - if (WARN_ON(!dev))
573 - return;
574 - /* This forces an update of the cached registers. */
575 - ssb_broadcast_value(dev, 0xFD8, 0);
576 + if (pc->dev->id.revision >= 10) {
577 + max_retries = 200;
578 + ssb_pcie_mdio_set_phy(pc, device);
579 + }
580 +
581 + v = (1 << 30); /* Start of Transaction */
582 + v |= (1 << 28); /* Write Transaction */
583 + v |= (1 << 17); /* Turnaround */
584 + if (pc->dev->id.revision < 10)
585 + v |= (u32)device << 22;
586 + v |= (u32)address << 18;
587 + v |= data;
588 + pcicore_write32(pc, mdio_data, v);
589 + /* Wait for the device to complete the transaction */
590 + udelay(10);
591 + for (i = 0; i < max_retries; i++) {
592 + v = pcicore_read32(pc, mdio_control);
593 + if (v & 0x100 /* Trans complete */)
594 + break;
595 + msleep(1);
596 + }
597 + pcicore_write32(pc, mdio_control, 0);
598 }
599
600 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
601 @@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
602 if (pc->setup_done)
603 goto out;
604 if (pdev->id.coreid == SSB_DEV_PCI) {
605 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
606 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
607 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
608 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
609 -
610 - if (pdev->id.revision < 5) {
611 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
612 - tmp &= ~SSB_IMCFGLO_SERTO;
613 - tmp |= 2;
614 - tmp &= ~SSB_IMCFGLO_REQTO;
615 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
616 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
617 - ssb_commit_settings(bus);
618 - } else if (pdev->id.revision >= 11) {
619 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
620 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
621 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
622 - }
623 + ssb_pcicore_pci_setup_workarounds(pc);
624 } else {
625 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
626 - //TODO: Better make defines for all these magic PCIE values.
627 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
628 - /* TLP Workaround register. */
629 - tmp = ssb_pcie_read(pc, 0x4);
630 - tmp |= 0x8;
631 - ssb_pcie_write(pc, 0x4, tmp);
632 - }
633 - if (pdev->id.revision == 0) {
634 - const u8 serdes_rx_device = 0x1F;
635 -
636 - ssb_pcie_mdio_write(pc, serdes_rx_device,
637 - 2 /* Timer */, 0x8128);
638 - ssb_pcie_mdio_write(pc, serdes_rx_device,
639 - 6 /* CDR */, 0x0100);
640 - ssb_pcie_mdio_write(pc, serdes_rx_device,
641 - 7 /* CDR BW */, 0x1466);
642 - } else if (pdev->id.revision == 1) {
643 - /* DLLP Link Control register. */
644 - tmp = ssb_pcie_read(pc, 0x100);
645 - tmp |= 0x40;
646 - ssb_pcie_write(pc, 0x100, tmp);
647 - }
648 + ssb_pcicore_pcie_setup_workarounds(pc);
649 }
650 pc->setup_done = 1;
651 out:
652 diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
653 index e05ba6e..6ec6e09 100644
654 --- a/drivers/ssb/main.c
655 +++ b/drivers/ssb/main.c
656 @@ -557,7 +557,7 @@ error:
657 }
658
659 /* Needs ssb_buses_lock() */
660 -static int ssb_attach_queued_buses(void)
661 +static int __devinit ssb_attach_queued_buses(void)
662 {
663 struct ssb_bus *bus, *n;
664 int err = 0;
665 @@ -768,9 +768,9 @@ out:
666 return err;
667 }
668
669 -static int ssb_bus_register(struct ssb_bus *bus,
670 - ssb_invariants_func_t get_invariants,
671 - unsigned long baseaddr)
672 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
673 + ssb_invariants_func_t get_invariants,
674 + unsigned long baseaddr)
675 {
676 int err;
677
678 @@ -851,8 +851,8 @@ err_disable_xtal:
679 }
680
681 #ifdef CONFIG_SSB_PCIHOST
682 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
683 - struct pci_dev *host_pci)
684 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
685 + struct pci_dev *host_pci)
686 {
687 int err;
688
689 @@ -875,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
690 #endif /* CONFIG_SSB_PCIHOST */
691
692 #ifdef CONFIG_SSB_PCMCIAHOST
693 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
694 - struct pcmcia_device *pcmcia_dev,
695 - unsigned long baseaddr)
696 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
697 + struct pcmcia_device *pcmcia_dev,
698 + unsigned long baseaddr)
699 {
700 int err;
701
702 @@ -897,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
703 #endif /* CONFIG_SSB_PCMCIAHOST */
704
705 #ifdef CONFIG_SSB_SDIOHOST
706 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
707 - unsigned int quirks)
708 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
709 + struct sdio_func *func,
710 + unsigned int quirks)
711 {
712 int err;
713
714 @@ -918,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
715 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
716 #endif /* CONFIG_SSB_PCMCIAHOST */
717
718 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
719 - unsigned long baseaddr,
720 - ssb_invariants_func_t get_invariants)
721 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
722 + unsigned long baseaddr,
723 + ssb_invariants_func_t get_invariants)
724 {
725 int err;
726
727 @@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
728 switch (plltype) {
729 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
730 if (m & SSB_CHIPCO_CLK_T6_MMASK)
731 - return SSB_CHIPCO_CLK_T6_M0;
732 - return SSB_CHIPCO_CLK_T6_M1;
733 + return SSB_CHIPCO_CLK_T6_M1;
734 + return SSB_CHIPCO_CLK_T6_M0;
735 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
736 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
737 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
738 @@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
739 {
740 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
741
742 - /* The REJECT bit changed position in TMSLOW between
743 - * Backplane revisions. */
744 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
745 switch (rev) {
746 case SSB_IDLOW_SSBREV_22:
747 - return SSB_TMSLOW_REJECT_22;
748 + case SSB_IDLOW_SSBREV_24:
749 + case SSB_IDLOW_SSBREV_26:
750 + return SSB_TMSLOW_REJECT;
751 case SSB_IDLOW_SSBREV_23:
752 return SSB_TMSLOW_REJECT_23;
753 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
754 - case SSB_IDLOW_SSBREV_25: /* same here */
755 - case SSB_IDLOW_SSBREV_26: /* same here */
756 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
757 case SSB_IDLOW_SSBREV_27: /* same here */
758 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
759 + return SSB_TMSLOW_REJECT; /* this is a guess */
760 default:
761 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
762 WARN_ON(1);
763 }
764 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
765 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
766 }
767
768 int ssb_device_is_enabled(struct ssb_device *dev)
769 @@ -1266,7 +1266,10 @@ u32 ssb_dma_translation(struct ssb_device *dev)
770 case SSB_BUSTYPE_SSB:
771 return 0;
772 case SSB_BUSTYPE_PCI:
773 - return SSB_PCI_DMA;
774 + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
775 + return SSB_PCIE_DMA_H32;
776 + else
777 + return SSB_PCI_DMA;
778 default:
779 __ssb_dma_not_implemented(dev);
780 }
781 @@ -1309,20 +1312,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
782
783 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
784 {
785 - struct ssb_chipcommon *cc;
786 int err;
787 enum ssb_clkmode mode;
788
789 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
790 if (err)
791 goto error;
792 - cc = &bus->chipco;
793 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
794 - ssb_chipco_set_clockmode(cc, mode);
795
796 #ifdef CONFIG_SSB_DEBUG
797 bus->powered_up = 1;
798 #endif
799 +
800 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
801 + ssb_chipco_set_clockmode(&bus->chipco, mode);
802 +
803 return 0;
804 error:
805 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
806 @@ -1330,6 +1333,37 @@ error:
807 }
808 EXPORT_SYMBOL(ssb_bus_powerup);
809
810 +static void ssb_broadcast_value(struct ssb_device *dev,
811 + u32 address, u32 data)
812 +{
813 +#ifdef CONFIG_SSB_DRIVER_PCICORE
814 + /* This is used for both, PCI and ChipCommon core, so be careful. */
815 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
816 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
817 +#endif
818 +
819 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
820 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
821 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
822 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
823 +}
824 +
825 +void ssb_commit_settings(struct ssb_bus *bus)
826 +{
827 + struct ssb_device *dev;
828 +
829 +#ifdef CONFIG_SSB_DRIVER_PCICORE
830 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
831 +#else
832 + dev = bus->chipco.dev;
833 +#endif
834 + if (WARN_ON(!dev))
835 + return;
836 + /* This forces an update of the cached registers. */
837 + ssb_broadcast_value(dev, 0xFD8, 0);
838 +}
839 +EXPORT_SYMBOL(ssb_commit_settings);
840 +
841 u32 ssb_admatch_base(u32 adm)
842 {
843 u32 base = 0;
844 diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
845 index a467b20..a00b35f 100644
846 --- a/drivers/ssb/pci.c
847 +++ b/drivers/ssb/pci.c
848 @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
849 static int ssb_pci_sprom_get(struct ssb_bus *bus,
850 struct ssb_sprom *sprom)
851 {
852 - const struct ssb_sprom *fallback;
853 int err;
854 u16 *buf;
855
856 @@ -670,7 +669,7 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
857 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
858 return -ENODEV;
859 }
860 - if (bus->chipco.dev) { /* can be unavailible! */
861 + if (bus->chipco.dev) { /* can be unavailable! */
862 /*
863 * get SPROM offset: SSB_SPROM_BASE1 except for
864 * chipcommon rev >= 31 or chip ID is 0x4312 and
865 @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
866 if (err) {
867 /* All CRC attempts failed.
868 * Maybe there is no SPROM on the device?
869 - * If we have a fallback, use that. */
870 - fallback = ssb_get_fallback_sprom();
871 - if (fallback) {
872 - memcpy(sprom, fallback, sizeof(*sprom));
873 + * Now we ask the arch code if there is some sprom
874 + * available for this device in some other storage */
875 + err = ssb_fill_sprom_with_fallback(bus, sprom);
876 + if (err) {
877 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
878 + " fallback SPROM failed (err %d)\n",
879 + err);
880 + } else {
881 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
882 + " revision %d provided by"
883 + " platform.\n", sprom->revision);
884 err = 0;
885 goto out_free;
886 }
887 @@ -728,12 +734,9 @@ out_free:
888 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
889 struct ssb_boardinfo *bi)
890 {
891 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
892 - &bi->vendor);
893 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
894 - &bi->type);
895 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
896 - &bi->rev);
897 + bi->vendor = bus->host_pci->subsystem_vendor;
898 + bi->type = bus->host_pci->subsystem_device;
899 + bi->rev = bus->host_pci->revision;
900 }
901
902 int ssb_pci_get_invariants(struct ssb_bus *bus,
903 diff --git a/drivers/ssb/pcihost_wrapper.c b/drivers/ssb/pcihost_wrapper.c
904 index f6c8c81..d7a9813 100644
905 --- a/drivers/ssb/pcihost_wrapper.c
906 +++ b/drivers/ssb/pcihost_wrapper.c
907 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci_dev *dev)
908 # define ssb_pcihost_resume NULL
909 #endif /* CONFIG_PM */
910
911 -static int ssb_pcihost_probe(struct pci_dev *dev,
912 - const struct pci_device_id *id)
913 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
914 + const struct pci_device_id *id)
915 {
916 struct ssb_bus *ssb;
917 int err = -ENOMEM;
918 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pci_dev *dev)
919 pci_set_drvdata(dev, NULL);
920 }
921
922 -int ssb_pcihost_register(struct pci_driver *driver)
923 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
924 {
925 driver->probe = ssb_pcihost_probe;
926 driver->remove = ssb_pcihost_remove;
927 diff --git a/drivers/ssb/scan.c b/drivers/ssb/scan.c
928 index 29884c0..8047f9a 100644
929 --- a/drivers/ssb/scan.c
930 +++ b/drivers/ssb/scan.c
931 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cores(struct ssb_bus *bus)
932 #ifdef CONFIG_SSB_PCIHOST
933 if (bus->bustype == SSB_BUSTYPE_PCI) {
934 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
935 - bus->host_pci->device == 0x4324)
936 + ((bus->host_pci->device == 0x4313) ||
937 + (bus->host_pci->device == 0x431A) ||
938 + (bus->host_pci->device == 0x4321) ||
939 + (bus->host_pci->device == 0x4324)))
940 return 1;
941 }
942 #endif /* CONFIG_SSB_PCIHOST */
943 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
944 } else {
945 if (bus->bustype == SSB_BUSTYPE_PCI) {
946 bus->chip_id = pcidev_to_chipid(bus->host_pci);
947 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
948 - &bus->chip_rev);
949 + bus->chip_rev = bus->host_pci->revision;
950 bus->chip_package = 0;
951 } else {
952 bus->chip_id = 0x4710;
953 diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
954 index 4f7cc8d..45ff0e3 100644
955 --- a/drivers/ssb/sprom.c
956 +++ b/drivers/ssb/sprom.c
957 @@ -17,7 +17,7 @@
958 #include <linux/slab.h>
959
960
961 -static const struct ssb_sprom *fallback_sprom;
962 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
963
964
965 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
966 @@ -145,36 +145,43 @@ out:
967 }
968
969 /**
970 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
971 + * ssb_arch_register_fallback_sprom - Registers a method providing a
972 + * fallback SPROM if no SPROM is found.
973 *
974 - * @sprom: The SPROM data structure to register.
975 + * @sprom_callback: The callback function.
976 *
977 - * With this function the architecture implementation may register a fallback
978 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
979 - * where no valid SPROM can be found in the shadow registers.
980 + * With this function the architecture implementation may register a
981 + * callback handler which fills the SPROM data structure. The fallback is
982 + * only used for PCI based SSB devices, where no valid SPROM can be found
983 + * in the shadow registers.
984 *
985 - * This function is useful for weird architectures that have a half-assed SSB device
986 - * hardwired to their PCI bus.
987 + * This function is useful for weird architectures that have a half-assed
988 + * SSB device hardwired to their PCI bus.
989 *
990 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
991 - * don't use this fallback.
992 - * Architectures must provide the SPROM for native SSB devices anyway,
993 - * so the fallback also isn't used for native devices.
994 + * Note that it does only work with PCI attached SSB devices. PCMCIA
995 + * devices currently don't use this fallback.
996 + * Architectures must provide the SPROM for native SSB devices anyway, so
997 + * the fallback also isn't used for native devices.
998 *
999 - * This function is available for architecture code, only. So it is not exported.
1000 + * This function is available for architecture code, only. So it is not
1001 + * exported.
1002 */
1003 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1004 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1005 + struct ssb_sprom *out))
1006 {
1007 - if (fallback_sprom)
1008 + if (get_fallback_sprom)
1009 return -EEXIST;
1010 - fallback_sprom = sprom;
1011 + get_fallback_sprom = sprom_callback;
1012
1013 return 0;
1014 }
1015
1016 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1017 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1018 {
1019 - return fallback_sprom;
1020 + if (!get_fallback_sprom)
1021 + return -ENOENT;
1022 +
1023 + return get_fallback_sprom(bus, out);
1024 }
1025
1026 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1027 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_bus *bus)
1028 /* this routine differs from specs as we do not access SPROM directly
1029 on PCMCIA */
1030 if (bus->bustype == SSB_BUSTYPE_PCI &&
1031 - bus->chipco.dev && /* can be unavailible! */
1032 + bus->chipco.dev && /* can be unavailable! */
1033 bus->chipco.dev->id.revision >= 31)
1034 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1035
1036 diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
1037 index 0331139..7765301 100644
1038 --- a/drivers/ssb/ssb_private.h
1039 +++ b/drivers/ssb/ssb_private.h
1040 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus,
1041 const char *buf, size_t count,
1042 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1043 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1044 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1045 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1046 + struct ssb_sprom *out);
1047
1048
1049 /* core.c */
1050 diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
1051 index 9659eff..8623217 100644
1052 --- a/include/linux/ssb/ssb.h
1053 +++ b/include/linux/ssb/ssb.h
1054 @@ -27,6 +27,8 @@ struct ssb_sprom {
1055 u8 et1mdcport; /* MDIO for enet1 */
1056 u8 board_rev; /* Board revision number from SPROM. */
1057 u8 country_code; /* Country Code */
1058 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1059 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1060 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1061 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1062 u16 pa0b0;
1063 @@ -99,7 +101,7 @@ struct ssb_sprom {
1064 struct ssb_boardinfo {
1065 u16 vendor;
1066 u16 type;
1067 - u16 rev;
1068 + u8 rev;
1069 };
1070
1071
1072 @@ -308,7 +310,7 @@ struct ssb_bus {
1073
1074 /* ID information about the Chip. */
1075 u16 chip_id;
1076 - u16 chip_rev;
1077 + u8 chip_rev;
1078 u16 sprom_offset;
1079 u16 sprom_size; /* number of words in sprom */
1080 u8 chip_package;
1081 @@ -404,7 +406,9 @@ extern bool ssb_is_sprom_available(struct ssb_bus *bus);
1082
1083 /* Set a fallback SPROM.
1084 * See kdoc at the function definition for complete documentation. */
1085 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1086 +extern int ssb_arch_register_fallback_sprom(
1087 + int (*sprom_callback)(struct ssb_bus *bus,
1088 + struct ssb_sprom *out));
1089
1090 /* Suspend a SSB bus.
1091 * Call this from the parent bus suspend routine. */
1092 @@ -518,6 +522,7 @@ extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
1093 * Otherwise static always-on powercontrol will be used. */
1094 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1095
1096 +extern void ssb_commit_settings(struct ssb_bus *bus);
1097
1098 /* Various helper functions */
1099 extern u32 ssb_admatch_base(u32 adm);
1100 diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
1101 index 2cdf249..a08d693 100644
1102 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1103 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1104 @@ -123,6 +123,8 @@
1105 #define SSB_CHIPCO_FLASHDATA 0x0048
1106 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1107 #define SSB_CHIPCO_BCAST_DATA 0x0054
1108 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1109 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1110 #define SSB_CHIPCO_GPIOIN 0x0060
1111 #define SSB_CHIPCO_GPIOOUT 0x0064
1112 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1113 @@ -131,6 +133,9 @@
1114 #define SSB_CHIPCO_GPIOIRQ 0x0074
1115 #define SSB_CHIPCO_WATCHDOG 0x0080
1116 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1117 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1118 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1119 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1120 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1121 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1122 #define SSB_CHIPCO_CLOCK_N 0x0090
1123 @@ -189,8 +194,10 @@
1124 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1125 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1126 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1127 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1128 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1129 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1130 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1131 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1132 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1133 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1134 #define SSB_CHIPCO_UART0_DATA 0x0300
1135 #define SSB_CHIPCO_UART0_IMR 0x0304
1136 diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
1137 index 402955a..efbf459 100644
1138 --- a/include/linux/ssb/ssb_regs.h
1139 +++ b/include/linux/ssb/ssb_regs.h
1140 @@ -97,7 +97,7 @@
1141 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1142 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
1143 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
1144 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
1145 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
1146 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
1147 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
1148 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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