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finally fix the v1 hardware bug :)
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 003-bcm47xx_cache_fixes.patch
1 diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
2 --- linux.old/arch/mips/kernel/entry.S 2005-07-04 23:39:26.000000000 +0200
3 +++ linux.dev/arch/mips/kernel/entry.S 2005-07-05 14:33:14.000000000 +0200
4 @@ -100,6 +100,10 @@
5 * and R4400 SC and MC versions.
6 */
7 NESTED(except_vec3_generic, 0, sp)
8 +#ifdef CONFIG_BCM4710
9 + nop
10 + nop
11 +#endif
12 #if R5432_CP0_INTERRUPT_WAR
13 mfc0 k0, CP0_INDEX
14 #endif
15 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16 --- linux.old/arch/mips/mm/c-r4k.c 2005-07-04 23:39:26.000000000 +0200
17 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-07-05 15:11:49.000000000 +0200
18 @@ -14,6 +14,12 @@
19 #include <linux/mm.h>
20 #include <linux/bitops.h>
21
22 +#ifdef CONFIG_BCM4710
23 +#include "../bcm947xx/include/typedefs.h"
24 +#include "../bcm947xx/include/sbconfig.h"
25 +#include <asm/paccess.h>
26 +#endif
27 +
28 #include <asm/bcache.h>
29 #include <asm/bootinfo.h>
30 #include <asm/cacheops.h>
31 @@ -40,6 +46,7 @@
32 .bc_inv = (void *)no_sc_noop
33 };
34
35 +static int bcm4710 = 0;
36 struct bcache_ops *bcops = &no_sc_ops;
37
38 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
39 @@ -64,8 +71,10 @@
40 static inline void r4k_blast_dcache_page_setup(void)
41 {
42 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
43 -
44 - if (dc_lsize == 16)
45 +
46 + if (bcm4710)
47 + r4k_blast_dcache_page = blast_dcache_page;
48 + else if (dc_lsize == 16)
49 r4k_blast_dcache_page = blast_dcache16_page;
50 else if (dc_lsize == 32)
51 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
52 @@ -77,7 +86,9 @@
53 {
54 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
55
56 - if (dc_lsize == 16)
57 + if (bcm4710)
58 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
59 + else if (dc_lsize == 16)
60 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
61 else if (dc_lsize == 32)
62 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
63 @@ -89,7 +100,9 @@
64 {
65 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
66
67 - if (dc_lsize == 16)
68 + if (bcm4710)
69 + r4k_blast_dcache = blast_dcache;
70 + else if (dc_lsize == 16)
71 r4k_blast_dcache = blast_dcache16;
72 else if (dc_lsize == 32)
73 r4k_blast_dcache = blast_dcache32;
74 @@ -266,6 +279,7 @@
75 r4k_blast_dcache();
76 r4k_blast_icache();
77
78 + if (!bcm4710)
79 switch (current_cpu_data.cputype) {
80 case CPU_R4000SC:
81 case CPU_R4000MC:
82 @@ -304,10 +318,10 @@
83 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
84 * only flush the primary caches but R10000 and R12000 behave sane ...
85 */
86 - if (current_cpu_data.cputype == CPU_R4000SC ||
87 + if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
88 current_cpu_data.cputype == CPU_R4000MC ||
89 current_cpu_data.cputype == CPU_R4400SC ||
90 - current_cpu_data.cputype == CPU_R4400MC)
91 + current_cpu_data.cputype == CPU_R4400MC))
92 r4k_blast_scache();
93 }
94
95 @@ -383,12 +397,15 @@
96 unsigned long ic_lsize = current_cpu_data.icache.linesz;
97 unsigned long addr, aend;
98
99 + addr = start & ~(dc_lsize - 1);
100 + aend = (end - 1) & ~(dc_lsize - 1);
101 +
102 if (!cpu_has_ic_fills_f_dc) {
103 if (end - start > dcache_size)
104 r4k_blast_dcache();
105 else {
106 - addr = start & ~(dc_lsize - 1);
107 - aend = (end - 1) & ~(dc_lsize - 1);
108 + BCM4710_PROTECTED_FILL_TLB(addr);
109 + BCM4710_PROTECTED_FILL_TLB(aend);
110
111 while (1) {
112 /* Hit_Writeback_Inv_D */
113 @@ -403,8 +420,6 @@
114 if (end - start > icache_size)
115 r4k_blast_icache();
116 else {
117 - addr = start & ~(ic_lsize - 1);
118 - aend = (end - 1) & ~(ic_lsize - 1);
119 while (1) {
120 /* Hit_Invalidate_I */
121 protected_flush_icache_line(addr);
122 @@ -443,7 +458,8 @@
123 if (cpu_has_subset_pcaches) {
124 unsigned long addr = (unsigned long) page_address(page);
125
126 - r4k_blast_scache_page(addr);
127 + if (!bcm4710)
128 + r4k_blast_scache_page(addr);
129 ClearPageDcacheDirty(page);
130
131 return;
132 @@ -451,6 +467,7 @@
133
134 if (!cpu_has_ic_fills_f_dc) {
135 unsigned long addr = (unsigned long) page_address(page);
136 +
137 r4k_blast_dcache_page(addr);
138 ClearPageDcacheDirty(page);
139 }
140 @@ -477,7 +494,7 @@
141 /* Catch bad driver code */
142 BUG_ON(size == 0);
143
144 - if (cpu_has_subset_pcaches) {
145 + if (!bcm4710 && cpu_has_subset_pcaches) {
146 unsigned long sc_lsize = current_cpu_data.scache.linesz;
147
148 if (size >= scache_size) {
149 @@ -509,6 +526,8 @@
150 R4600_HIT_CACHEOP_WAR_IMPL;
151 a = addr & ~(dc_lsize - 1);
152 end = (addr + size - 1) & ~(dc_lsize - 1);
153 + BCM4710_FILL_TLB(a);
154 + BCM4710_FILL_TLB(end);
155 while (1) {
156 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
157 if (a == end)
158 @@ -527,7 +546,7 @@
159 /* Catch bad driver code */
160 BUG_ON(size == 0);
161
162 - if (cpu_has_subset_pcaches) {
163 + if (!bcm4710 && (cpu_has_subset_pcaches)) {
164 unsigned long sc_lsize = current_cpu_data.scache.linesz;
165
166 if (size >= scache_size) {
167 @@ -554,6 +573,8 @@
168 R4600_HIT_CACHEOP_WAR_IMPL;
169 a = addr & ~(dc_lsize - 1);
170 end = (addr + size - 1) & ~(dc_lsize - 1);
171 + BCM4710_FILL_TLB(a);
172 + BCM4710_FILL_TLB(end);
173 while (1) {
174 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
175 if (a == end)
176 @@ -577,6 +598,8 @@
177 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
178
179 R4600_HIT_CACHEOP_WAR_IMPL;
180 + BCM4710_PROTECTED_FILL_TLB(addr);
181 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
182 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
183 protected_flush_icache_line(addr & ~(ic_lsize - 1));
184 if (MIPS4K_ICACHE_REFILL_WAR) {
185 @@ -986,10 +1009,12 @@
186 case CPU_R4000MC:
187 case CPU_R4400SC:
188 case CPU_R4400MC:
189 - probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
190 - sc_present = probe_scache_kseg1(config);
191 - if (sc_present)
192 - c->options |= MIPS_CPU_CACHE_CDEX_S;
193 + if (!bcm4710) {
194 + probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
195 + sc_present = probe_scache_kseg1(config);
196 + if (sc_present)
197 + c->options |= MIPS_CPU_CACHE_CDEX_S;
198 + }
199 break;
200
201 case CPU_R10000:
202 @@ -1041,6 +1066,19 @@
203 static inline void coherency_setup(void)
204 {
205 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
206 +
207 +#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
208 + if (BCM330X(current_cpu_data.processor_id)) {
209 + uint32 cm;
210 +
211 + cm = read_c0_diag();
212 + /* Enable icache */
213 + cm |= (1 << 31);
214 + /* Enable dcache */
215 + cm |= (1 << 30);
216 + write_c0_diag(cm);
217 + }
218 +#endif
219
220 /*
221 * c0_status.cu=0 specifies that updates by the sc instruction use
222 @@ -1062,6 +1100,42 @@
223
224 }
225
226 +#ifdef CONFIG_BCM4704
227 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
228 +{
229 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
230 + int i;
231 + for (i = 0; i < nbytes; i += ic_lsize)
232 + fill_icache_line((addr + i));
233 +}
234 +
235 +/*
236 + * This must be run from the cache on 4704A0
237 + * so there are no mips core BIU ops in progress
238 + * when the PFC is enabled.
239 + */
240 +#define PFC_CR0 0xff400000 /* control reg 0 */
241 +#define PFC_CR1 0xff400004 /* control reg 1 */
242 +static void __init enable_pfc(u32 mode)
243 +{
244 + /* write range */
245 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
246 +
247 + /* enable */
248 + *(volatile u32 *)PFC_CR0 = mode;
249 +}
250 +
251 +void check_enable_mips_pfc(int val)
252 +{
253 + /* enable prefetch cache */
254 + if (BCM330X(current_cpu_data.processor_id)
255 + && (read_c0_diag() & (1 << 29))) {
256 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
257 + enable_pfc(val);
258 + }
259 +}
260 +#endif
261 +
262 void __init ld_mmu_r4xx0(void)
263 {
264 extern void build_clear_page(void);
265 @@ -1073,6 +1147,11 @@
266 memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
267 memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
268
269 + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0)
270 + bcm4710 = 1;
271 + else
272 + bcm4710 = 0;
273 +
274 probe_pcache();
275 setup_scache();
276
277 @@ -1117,47 +1196,9 @@
278
279 build_clear_page();
280 build_copy_page();
281 -}
282 -
283 -#ifdef CONFIG_BCM4704
284 -static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
285 -{
286 - unsigned long ic_lsize = current_cpu_data.icache.linesz;
287 - int i;
288 - for (i = 0; i < nbytes; i += ic_lsize)
289 - fill_icache_line((addr + i));
290 -}
291 -
292 -/*
293 - * This must be run from the cache on 4704A0
294 - * so there are no mips core BIU ops in progress
295 - * when the PFC is enabled.
296 - */
297 -#define PFC_CR0 0xff400000 /* control reg 0 */
298 -#define PFC_CR1 0xff400004 /* control reg 1 */
299 -static void __init enable_pfc(u32 mode)
300 -{
301 - /* write range */
302 - *(volatile u32 *)PFC_CR1 = 0xffff0000;
303 -
304 - /* enable */
305 - *(volatile u32 *)PFC_CR0 = mode;
306 -}
307 -#endif
308 -
309 -
310 -void check_enable_mips_pfc(int val)
311 -{
312 -
313 +
314 #ifdef CONFIG_BCM4704
315 - struct cpuinfo_mips *c = &current_cpu_data;
316 -
317 - /* enable prefetch cache */
318 - if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
319 - && (read_c0_diag() & (1 << 29))) {
320 - mips32_icache_fill((unsigned long) &enable_pfc, 64);
321 - enable_pfc(val);
322 - }
323 + check_enable_mips_pfc(0x15);
324 #endif
325 }
326
327 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
328 --- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-04 23:39:26.000000000 +0200
329 +++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-05 14:33:14.000000000 +0200
330 @@ -38,6 +38,7 @@
331 old_ctx = read_c0_entryhi();
332 write_c0_entrylo0(0);
333 write_c0_entrylo1(0);
334 + BARRIER;
335
336 entry = read_c0_wired();
337
338 @@ -47,6 +48,7 @@
339 write_c0_index(entry);
340 mtc0_tlbw_hazard();
341 tlb_write_indexed();
342 + BARRIER;
343 entry++;
344 }
345 tlbw_use_hazard();
346 @@ -98,6 +100,7 @@
347 write_c0_entryhi(KSEG0 + idx*0x2000);
348 mtc0_tlbw_hazard();
349 tlb_write_indexed();
350 + BARRIER;
351 }
352 tlbw_use_hazard();
353 write_c0_entryhi(oldpid);
354 @@ -136,6 +139,7 @@
355 tlbw_use_hazard();
356
357 finish:
358 + BARRIER;
359 write_c0_entryhi(oldpid);
360 local_irq_restore(flags);
361 }
362 @@ -204,6 +208,7 @@
363 pmdp = pmd_offset(pgdp, address);
364 idx = read_c0_index();
365 ptep = pte_offset(pmdp, address);
366 + BARRIER;
367 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
368 write_c0_entrylo0(ptep->pte_high);
369 ptep++;
370 @@ -220,6 +225,7 @@
371 tlb_write_indexed();
372 tlbw_use_hazard();
373 write_c0_entryhi(pid);
374 + BARRIER;
375 local_irq_restore(flags);
376 }
377
378 @@ -317,6 +323,7 @@
379 }
380
381 write_c0_index(temp_tlb_entry);
382 + BARRIER;
383 write_c0_pagemask(pagemask);
384 write_c0_entryhi(entryhi);
385 write_c0_entrylo0(entrylo0);
386 diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
387 --- linux.old/arch/mips/mm/tlbex-mips32.S 2005-07-04 23:39:26.000000000 +0200
388 +++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-07-05 14:33:14.000000000 +0200
389 @@ -90,6 +90,9 @@
390 .set noat
391 LEAF(except_vec0_r4000)
392 .set mips3
393 +#ifdef CONFIG_BCM4704
394 + nop
395 +#endif
396 #ifdef CONFIG_SMP
397 mfc0 k1, CP0_CONTEXT
398 la k0, pgd_current
399 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
400 --- linux.old/include/asm-mips/r4kcache.h 2005-07-04 23:39:26.000000000 +0200
401 +++ linux.dev/include/asm-mips/r4kcache.h 2005-07-05 15:13:56.000000000 +0200
402 @@ -15,6 +15,18 @@
403 #include <asm/asm.h>
404 #include <asm/cacheops.h>
405
406 +#ifdef CONFIG_BCM4710
407 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
408 +
409 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
410 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
411 +#else
412 +#define BCM4710_DUMMY_RREG()
413 +
414 +#define BCM4710_FILL_TLB(addr)
415 +#define BCM4710_PROTECTED_FILL_TLB(addr)
416 +#endif
417 +
418 #define cache_op(op,addr) \
419 __asm__ __volatile__( \
420 " .set noreorder \n" \
421 @@ -32,6 +44,7 @@
422
423 static inline void flush_dcache_line_indexed(unsigned long addr)
424 {
425 + BCM4710_DUMMY_RREG();
426 cache_op(Index_Writeback_Inv_D, addr);
427 }
428
429 @@ -47,6 +60,7 @@
430
431 static inline void flush_dcache_line(unsigned long addr)
432 {
433 + BCM4710_DUMMY_RREG();
434 cache_op(Hit_Writeback_Inv_D, addr);
435 }
436
437 @@ -91,6 +105,7 @@
438 */
439 static inline void protected_writeback_dcache_line(unsigned long addr)
440 {
441 + BCM4710_DUMMY_RREG();
442 __asm__ __volatile__(
443 ".set noreorder\n\t"
444 ".set mips3\n"
445 @@ -138,6 +153,59 @@
446 : "r" (base), \
447 "i" (op));
448
449 +#define cache_unroll(base,op) \
450 + __asm__ __volatile__(" \
451 + .set noreorder; \
452 + .set mips3; \
453 + cache %1, (%0); \
454 + .set mips0; \
455 + .set reorder" \
456 + : \
457 + : "r" (base), \
458 + "i" (op));
459 +
460 +
461 +static inline void blast_dcache(void)
462 +{
463 + unsigned long start = KSEG0;
464 + unsigned long end = start + current_cpu_data.dcache.waysize;
465 +
466 + while(start < end) {
467 + BCM4710_DUMMY_RREG();
468 + cache_unroll(start,Index_Writeback_Inv_D);
469 + start += current_cpu_data.dcache.linesz;
470 + }
471 +}
472 +
473 +static inline void blast_dcache_page(unsigned long page)
474 +{
475 + unsigned long start = page;
476 + unsigned long end = start + PAGE_SIZE;
477 +
478 + BCM4710_FILL_TLB(start);
479 + do {
480 + BCM4710_DUMMY_RREG();
481 + cache_unroll(start,Hit_Writeback_Inv_D);
482 + start += current_cpu_data.dcache.linesz;
483 + } while (start < end);
484 +}
485 +
486 +static inline void blast_dcache_page_indexed(unsigned long page)
487 +{
488 + unsigned long start = page;
489 + unsigned long end = start + PAGE_SIZE;
490 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
491 + unsigned long ws_end = current_cpu_data.dcache.ways <<
492 + current_cpu_data.dcache.waybit;
493 + unsigned long ws, addr;
494 +
495 + for (ws = 0; ws < ws_end; ws += ws_inc)
496 + for (addr = start; addr < end; addr += start += current_cpu_data.dcache.linesz) {
497 + BCM4710_DUMMY_RREG();
498 + cache_unroll(addr,Index_Writeback_Inv_D);
499 + }
500 +}
501 +
502 static inline void blast_dcache16(void)
503 {
504 unsigned long start = KSEG0;
505 @@ -148,8 +216,9 @@
506 unsigned long ws, addr;
507
508 for (ws = 0; ws < ws_end; ws += ws_inc)
509 - for (addr = start; addr < end; addr += 0x200)
510 + for (addr = start; addr < end; addr += 0x200) {
511 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
512 + }
513 }
514
515 static inline void blast_dcache16_page(unsigned long page)
516 @@ -173,8 +242,9 @@
517 unsigned long ws, addr;
518
519 for (ws = 0; ws < ws_end; ws += ws_inc)
520 - for (addr = start; addr < end; addr += 0x200)
521 + for (addr = start; addr < end; addr += 0x200) {
522 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
523 + }
524 }
525
526 static inline void blast_icache16(void)
527 @@ -196,6 +266,7 @@
528 unsigned long start = page;
529 unsigned long end = start + PAGE_SIZE;
530
531 + BCM4710_FILL_TLB(start);
532 do {
533 cache16_unroll32(start,Hit_Invalidate_I);
534 start += 0x200;
535 @@ -281,6 +352,7 @@
536 : "r" (base), \
537 "i" (op));
538
539 +
540 static inline void blast_dcache32(void)
541 {
542 unsigned long start = KSEG0;
543 @@ -291,8 +363,9 @@
544 unsigned long ws, addr;
545
546 for (ws = 0; ws < ws_end; ws += ws_inc)
547 - for (addr = start; addr < end; addr += 0x400)
548 + for (addr = start; addr < end; addr += 0x400) {
549 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
550 + }
551 }
552
553 static inline void blast_dcache32_page(unsigned long page)
554 @@ -316,8 +389,9 @@
555 unsigned long ws, addr;
556
557 for (ws = 0; ws < ws_end; ws += ws_inc)
558 - for (addr = start; addr < end; addr += 0x400)
559 + for (addr = start; addr < end; addr += 0x400) {
560 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
561 + }
562 }
563
564 static inline void blast_icache32(void)
565 @@ -339,6 +413,7 @@
566 unsigned long start = page;
567 unsigned long end = start + PAGE_SIZE;
568
569 + BCM4710_FILL_TLB(start);
570 do {
571 cache32_unroll32(start,Hit_Invalidate_I);
572 start += 0x400;
573 @@ -443,6 +518,7 @@
574 unsigned long start = page;
575 unsigned long end = start + PAGE_SIZE;
576
577 + BCM4710_FILL_TLB(start);
578 do {
579 cache64_unroll32(start,Hit_Invalidate_I);
580 start += 0x800;
581 diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
582 --- linux.old/include/asm-mips/stackframe.h 2005-07-04 23:39:26.000000000 +0200
583 +++ linux.dev/include/asm-mips/stackframe.h 2005-07-05 14:33:14.000000000 +0200
584 @@ -172,6 +172,46 @@
585 rfe; \
586 .set pop
587
588 +#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
589 +
590 +#define RESTORE_SOME \
591 + .set push; \
592 + .set reorder; \
593 + mfc0 t0, CP0_STATUS; \
594 + .set pop; \
595 + ori t0, 0x1f; \
596 + xori t0, 0x1f; \
597 + mtc0 t0, CP0_STATUS; \
598 + li v1, 0xff00; \
599 + and t0, v1; \
600 + lw v0, PT_STATUS(sp); \
601 + nor v1, $0, v1; \
602 + and v0, v1; \
603 + or v0, t0; \
604 + ori v1, v0, ST0_IE; \
605 + xori v1, v1, ST0_IE; \
606 + mtc0 v1, CP0_STATUS; \
607 + mtc0 v0, CP0_STATUS; \
608 + lw v1, PT_EPC(sp); \
609 + mtc0 v1, CP0_EPC; \
610 + lw $31, PT_R31(sp); \
611 + lw $28, PT_R28(sp); \
612 + lw $25, PT_R25(sp); \
613 + lw $7, PT_R7(sp); \
614 + lw $6, PT_R6(sp); \
615 + lw $5, PT_R5(sp); \
616 + lw $4, PT_R4(sp); \
617 + lw $3, PT_R3(sp); \
618 + lw $2, PT_R2(sp)
619 +
620 +#define RESTORE_SP_AND_RET \
621 + lw sp, PT_R29(sp); \
622 + nop; \
623 + nop; \
624 + .set mips3; \
625 + eret; \
626 + .set mips0
627 +
628 #else
629
630 #define RESTORE_SOME \
Personal OpenWRT clone
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