projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[atheros] enable mtu & mac config options
[openwrt.git] / target / linux / atheros / patches-2.6.34 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -371,6 +371,12 @@ config AX88796_93CX6
4 help
5 Select this if your platform comes with an external 93CX6 eeprom.
6
7 +config AR231X_ETHERNET
8 + tristate "AR231x Ethernet support"
9 + depends on ATHEROS_AR231X
10 + help
11 + Support for the AR231x/531x ethernet controller
12 +
13 config MACE
14 tristate "MACE (Power Mac ethernet) support"
15 depends on PPC_PMAC && PPC32
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -221,6 +221,7 @@ obj-$(CONFIG_EQUALIZER) += eql.o
19 obj-$(CONFIG_KORINA) += korina.o
20 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
21 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
22 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
23 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
24 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
25 obj-$(CONFIG_DECLANCE) += declance.o
26 --- /dev/null
27 +++ b/drivers/net/ar231x.c
28 @@ -0,0 +1,1266 @@
29 +/*
30 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
31 + *
32 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
33 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + *
36 + * Thanks to Atheros for providing hardware and documentation
37 + * enabling me to write this driver.
38 + *
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License as published by
41 + * the Free Software Foundation; either version 2 of the License, or
42 + * (at your option) any later version.
43 + *
44 + * Additional credits:
45 + * This code is taken from John Taylor's Sibyte driver and then
46 + * modified for the AR2313.
47 + */
48 +
49 +#include <linux/module.h>
50 +#include <linux/version.h>
51 +#include <linux/types.h>
52 +#include <linux/errno.h>
53 +#include <linux/ioport.h>
54 +#include <linux/pci.h>
55 +#include <linux/netdevice.h>
56 +#include <linux/etherdevice.h>
57 +#include <linux/skbuff.h>
58 +#include <linux/init.h>
59 +#include <linux/delay.h>
60 +#include <linux/mm.h>
61 +#include <linux/highmem.h>
62 +#include <linux/sockios.h>
63 +#include <linux/pkt_sched.h>
64 +#include <linux/mii.h>
65 +#include <linux/phy.h>
66 +#include <linux/ethtool.h>
67 +#include <linux/ctype.h>
68 +#include <linux/platform_device.h>
69 +
70 +#include <net/sock.h>
71 +#include <net/ip.h>
72 +
73 +#include <asm/system.h>
74 +#include <asm/io.h>
75 +#include <asm/irq.h>
76 +#include <asm/byteorder.h>
77 +#include <asm/uaccess.h>
78 +#include <asm/bootinfo.h>
79 +
80 +#define AR2313_MTU 1692
81 +#define AR2313_PRIOS 1
82 +#define AR2313_QUEUES (2*AR2313_PRIOS)
83 +#define AR2313_DESCR_ENTRIES 64
84 +
85 +
86 +#ifndef min
87 +#define min(a,b) (((a)<(b))?(a):(b))
88 +#endif
89 +
90 +#ifndef SMP_CACHE_BYTES
91 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
92 +#endif
93 +
94 +#define AR2313_MBOX_SET_BIT 0x8
95 +
96 +#include "ar231x.h"
97 +
98 +/*
99 + * New interrupt handler strategy:
100 + *
101 + * An old interrupt handler worked using the traditional method of
102 + * replacing an skbuff with a new one when a packet arrives. However
103 + * the rx rings do not need to contain a static number of buffer
104 + * descriptors, thus it makes sense to move the memory allocation out
105 + * of the main interrupt handler and do it in a bottom half handler
106 + * and only allocate new buffers when the number of buffers in the
107 + * ring is below a certain threshold. In order to avoid starving the
108 + * NIC under heavy load it is however necessary to force allocation
109 + * when hitting a minimum threshold. The strategy for alloction is as
110 + * follows:
111 + *
112 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
113 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
114 + * the buffers in the interrupt handler
115 + * RX_RING_THRES - maximum number of buffers in the rx ring
116 + *
117 + * One advantagous side effect of this allocation approach is that the
118 + * entire rx processing can be done without holding any spin lock
119 + * since the rx rings and registers are totally independent of the tx
120 + * ring and its registers. This of course includes the kmalloc's of
121 + * new skb's. Thus start_xmit can run in parallel with rx processing
122 + * and the memory allocation on SMP systems.
123 + *
124 + * Note that running the skb reallocation in a bottom half opens up
125 + * another can of races which needs to be handled properly. In
126 + * particular it can happen that the interrupt handler tries to run
127 + * the reallocation while the bottom half is either running on another
128 + * CPU or was interrupted on the same CPU. To get around this the
129 + * driver uses bitops to prevent the reallocation routines from being
130 + * reentered.
131 + *
132 + * TX handling can also be done without holding any spin lock, wheee
133 + * this is fun! since tx_csm is only written to by the interrupt
134 + * handler.
135 + */
136 +
137 +/*
138 + * Threshold values for RX buffer allocation - the low water marks for
139 + * when to start refilling the rings are set to 75% of the ring
140 + * sizes. It seems to make sense to refill the rings entirely from the
141 + * intrrupt handler once it gets below the panic threshold, that way
142 + * we don't risk that the refilling is moved to another CPU when the
143 + * one running the interrupt handler just got the slab code hot in its
144 + * cache.
145 + */
146 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
147 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
148 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
149 +#define CRC_LEN 4
150 +#define RX_OFFSET 2
151 +
152 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
153 +#define VLAN_HDR 4
154 +#else
155 +#define VLAN_HDR 0
156 +#endif
157 +
158 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
159 +
160 +#ifdef MODULE
161 +MODULE_LICENSE("GPL");
162 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
163 +MODULE_DESCRIPTION("AR231x Ethernet driver");
164 +#endif
165 +
166 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
167 +
168 +// prototypes
169 +static void ar231x_halt(struct net_device *dev);
170 +static void rx_tasklet_func(unsigned long data);
171 +static void rx_tasklet_cleanup(struct net_device *dev);
172 +static void ar231x_multicast_list(struct net_device *dev);
173 +
174 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
175 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
176 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
177 +static int ar231x_mdiobus_probe (struct net_device *dev);
178 +static void ar231x_adjust_link(struct net_device *dev);
179 +
180 +#ifndef ERR
181 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
182 +#endif
183 +
184 +static const struct net_device_ops ar231x_ops = {
185 + .ndo_open = ar231x_open,
186 + .ndo_stop = ar231x_close,
187 + .ndo_start_xmit = ar231x_start_xmit,
188 + .ndo_set_multicast_list = ar231x_multicast_list,
189 + .ndo_do_ioctl = ar231x_ioctl,
190 + .ndo_change_mtu = eth_change_mtu,
191 + .ndo_validate_addr = eth_validate_addr,
192 + .ndo_set_mac_address = eth_mac_addr,
193 +};
194 +
195 +int __init ar231x_probe(struct platform_device *pdev)
196 +{
197 + struct net_device *dev;
198 + struct ar231x_private *sp;
199 + struct resource *res;
200 + unsigned long ar_eth_base;
201 + char buf[64];
202 +
203 + dev = alloc_etherdev(sizeof(struct ar231x_private));
204 +
205 + if (dev == NULL) {
206 + printk(KERN_ERR
207 + "ar231x: Unable to allocate net_device structure!\n");
208 + return -ENOMEM;
209 + }
210 +
211 + platform_set_drvdata(pdev, dev);
212 +
213 + sp = netdev_priv(dev);
214 + sp->dev = dev;
215 + sp->cfg = pdev->dev.platform_data;
216 +
217 + sprintf(buf, "eth%d_membase", pdev->id);
218 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
219 + if (!res)
220 + return -ENODEV;
221 +
222 + sp->link = 0;
223 + ar_eth_base = res->start;
224 +
225 + sprintf(buf, "eth%d_irq", pdev->id);
226 + dev->irq = platform_get_irq_byname(pdev, buf);
227 +
228 + spin_lock_init(&sp->lock);
229 +
230 + dev->features |= NETIF_F_HIGHDMA;
231 + dev->netdev_ops = &ar231x_ops;
232 +
233 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
234 + tasklet_disable(&sp->rx_tasklet);
235 +
236 + sp->eth_regs =
237 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
238 + if (!sp->eth_regs) {
239 + printk("Can't remap eth registers\n");
240 + return (-ENXIO);
241 + }
242 +
243 + /*
244 + * When there's only one MAC, PHY regs are typically on ENET0,
245 + * even though the MAC might be on ENET1.
246 + * Needto remap PHY regs separately in this case
247 + */
248 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
249 + sp->phy_regs = sp->eth_regs;
250 + else {
251 + sp->phy_regs =
252 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
253 + sizeof(*sp->phy_regs));
254 + if (!sp->phy_regs) {
255 + printk("Can't remap phy registers\n");
256 + return (-ENXIO);
257 + }
258 + }
259 +
260 + sp->dma_regs =
261 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
262 + sizeof(*sp->dma_regs));
263 + dev->base_addr = (unsigned int) sp->dma_regs;
264 + if (!sp->dma_regs) {
265 + printk("Can't remap DMA registers\n");
266 + return (-ENXIO);
267 + }
268 +
269 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
270 + if (!sp->int_regs) {
271 + printk("Can't remap INTERRUPT registers\n");
272 + return (-ENXIO);
273 + }
274 +
275 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
276 + sp->name[sizeof(sp->name) - 1] = '\0';
277 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
278 +
279 + if (ar231x_init(dev)) {
280 + /*
281 + * ar231x_init() calls ar231x_init_cleanup() on error.
282 + */
283 + kfree(dev);
284 + return -ENODEV;
285 + }
286 +
287 + if (register_netdev(dev)) {
288 + printk("%s: register_netdev failed\n", __func__);
289 + return -1;
290 + }
291 +
292 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
293 + dev->name, sp->name,
294 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
295 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
296 +
297 + sp->mii_bus = mdiobus_alloc();
298 + if (sp->mii_bus == NULL)
299 + return -1;
300 +
301 + sp->mii_bus->priv = dev;
302 + sp->mii_bus->read = ar231x_mdiobus_read;
303 + sp->mii_bus->write = ar231x_mdiobus_write;
304 + sp->mii_bus->reset = ar231x_mdiobus_reset;
305 + sp->mii_bus->name = "ar231x_eth_mii";
306 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
307 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
308 + *sp->mii_bus->irq = PHY_POLL;
309 +
310 + mdiobus_register(sp->mii_bus);
311 +
312 + if (ar231x_mdiobus_probe(dev) != 0) {
313 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
314 + rx_tasklet_cleanup(dev);
315 + ar231x_init_cleanup(dev);
316 + unregister_netdev(dev);
317 + kfree(dev);
318 + return -ENODEV;
319 + }
320 +
321 + /* start link poll timer */
322 + ar231x_setup_timer(dev);
323 +
324 + return 0;
325 +}
326 +
327 +
328 +static void ar231x_multicast_list(struct net_device *dev)
329 +{
330 + struct ar231x_private *sp = netdev_priv(dev);
331 + unsigned int filter;
332 +
333 + filter = sp->eth_regs->mac_control;
334 +
335 + if (dev->flags & IFF_PROMISC)
336 + filter |= MAC_CONTROL_PR;
337 + else
338 + filter &= ~MAC_CONTROL_PR;
339 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
340 + filter |= MAC_CONTROL_PM;
341 + else
342 + filter &= ~MAC_CONTROL_PM;
343 +
344 + sp->eth_regs->mac_control = filter;
345 +}
346 +
347 +static void rx_tasklet_cleanup(struct net_device *dev)
348 +{
349 + struct ar231x_private *sp = netdev_priv(dev);
350 +
351 + /*
352 + * Tasklet may be scheduled. Need to get it removed from the list
353 + * since we're about to free the struct.
354 + */
355 +
356 + sp->unloading = 1;
357 + tasklet_enable(&sp->rx_tasklet);
358 + tasklet_kill(&sp->rx_tasklet);
359 +}
360 +
361 +static int __devexit ar231x_remove(struct platform_device *pdev)
362 +{
363 + struct net_device *dev = platform_get_drvdata(pdev);
364 + struct ar231x_private *sp = netdev_priv(dev);
365 + rx_tasklet_cleanup(dev);
366 + ar231x_init_cleanup(dev);
367 + unregister_netdev(dev);
368 + mdiobus_unregister(sp->mii_bus);
369 + mdiobus_free(sp->mii_bus);
370 + kfree(dev);
371 + return 0;
372 +}
373 +
374 +
375 +/*
376 + * Restart the AR2313 ethernet controller.
377 + */
378 +static int ar231x_restart(struct net_device *dev)
379 +{
380 + /* disable interrupts */
381 + disable_irq(dev->irq);
382 +
383 + /* stop mac */
384 + ar231x_halt(dev);
385 +
386 + /* initialize */
387 + ar231x_init(dev);
388 +
389 + /* enable interrupts */
390 + enable_irq(dev->irq);
391 +
392 + return 0;
393 +}
394 +
395 +static struct platform_driver ar231x_driver = {
396 + .driver.name = "ar231x-eth",
397 + .probe = ar231x_probe,
398 + .remove = __devexit_p(ar231x_remove),
399 +};
400 +
401 +int __init ar231x_module_init(void)
402 +{
403 + return platform_driver_register(&ar231x_driver);
404 +}
405 +
406 +void __exit ar231x_module_cleanup(void)
407 +{
408 + platform_driver_unregister(&ar231x_driver);
409 +}
410 +
411 +module_init(ar231x_module_init);
412 +module_exit(ar231x_module_cleanup);
413 +
414 +
415 +static void ar231x_free_descriptors(struct net_device *dev)
416 +{
417 + struct ar231x_private *sp = netdev_priv(dev);
418 + if (sp->rx_ring != NULL) {
419 + kfree((void *) KSEG0ADDR(sp->rx_ring));
420 + sp->rx_ring = NULL;
421 + sp->tx_ring = NULL;
422 + }
423 +}
424 +
425 +
426 +static int ar231x_allocate_descriptors(struct net_device *dev)
427 +{
428 + struct ar231x_private *sp = netdev_priv(dev);
429 + int size;
430 + int j;
431 + ar231x_descr_t *space;
432 +
433 + if (sp->rx_ring != NULL) {
434 + printk("%s: already done.\n", __FUNCTION__);
435 + return 0;
436 + }
437 +
438 + size =
439 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
440 + space = kmalloc(size, GFP_KERNEL);
441 + if (space == NULL)
442 + return 1;
443 +
444 + /* invalidate caches */
445 + dma_cache_inv((unsigned int) space, size);
446 +
447 + /* now convert pointer to KSEG1 */
448 + space = (ar231x_descr_t *) KSEG1ADDR(space);
449 +
450 + memset((void *) space, 0, size);
451 +
452 + sp->rx_ring = space;
453 + space += AR2313_DESCR_ENTRIES;
454 +
455 + sp->tx_ring = space;
456 + space += AR2313_DESCR_ENTRIES;
457 +
458 + /* Initialize the transmit Descriptors */
459 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
460 + ar231x_descr_t *td = &sp->tx_ring[j];
461 + td->status = 0;
462 + td->devcs = DMA_TX1_CHAINED;
463 + td->addr = 0;
464 + td->descr =
465 + virt_to_phys(&sp->
466 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
467 + }
468 +
469 + return 0;
470 +}
471 +
472 +
473 +/*
474 + * Generic cleanup handling data allocated during init. Used when the
475 + * module is unloaded or if an error occurs during initialization
476 + */
477 +static void ar231x_init_cleanup(struct net_device *dev)
478 +{
479 + struct ar231x_private *sp = netdev_priv(dev);
480 + struct sk_buff *skb;
481 + int j;
482 +
483 + ar231x_free_descriptors(dev);
484 +
485 + if (sp->eth_regs)
486 + iounmap((void *) sp->eth_regs);
487 + if (sp->dma_regs)
488 + iounmap((void *) sp->dma_regs);
489 +
490 + if (sp->rx_skb) {
491 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
492 + skb = sp->rx_skb[j];
493 + if (skb) {
494 + sp->rx_skb[j] = NULL;
495 + dev_kfree_skb(skb);
496 + }
497 + }
498 + kfree(sp->rx_skb);
499 + sp->rx_skb = NULL;
500 + }
501 +
502 + if (sp->tx_skb) {
503 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
504 + skb = sp->tx_skb[j];
505 + if (skb) {
506 + sp->tx_skb[j] = NULL;
507 + dev_kfree_skb(skb);
508 + }
509 + }
510 + kfree(sp->tx_skb);
511 + sp->tx_skb = NULL;
512 + }
513 +}
514 +
515 +static int ar231x_setup_timer(struct net_device *dev)
516 +{
517 + struct ar231x_private *sp = netdev_priv(dev);
518 +
519 + init_timer(&sp->link_timer);
520 +
521 + sp->link_timer.function = ar231x_link_timer_fn;
522 + sp->link_timer.data = (int) dev;
523 + sp->link_timer.expires = jiffies + HZ;
524 +
525 + add_timer(&sp->link_timer);
526 + return 0;
527 +
528 +}
529 +
530 +static void ar231x_link_timer_fn(unsigned long data)
531 +{
532 + struct net_device *dev = (struct net_device *) data;
533 + struct ar231x_private *sp = netdev_priv(dev);
534 +
535 + // see if the link status changed
536 + // This was needed to make sure we set the PHY to the
537 + // autonegotiated value of half or full duplex.
538 + ar231x_check_link(dev);
539 +
540 + // Loop faster when we don't have link.
541 + // This was needed to speed up the AP bootstrap time.
542 + if (sp->link == 0) {
543 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
544 + } else {
545 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
546 + }
547 +}
548 +
549 +static void ar231x_check_link(struct net_device *dev)
550 +{
551 + struct ar231x_private *sp = netdev_priv(dev);
552 + u16 phyData;
553 +
554 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
555 + if (sp->phyData != phyData) {
556 + if (phyData & BMSR_LSTATUS) {
557 + /* link is present, ready link partner ability to deterine
558 + duplexity */
559 + int duplex = 0;
560 + u16 reg;
561 +
562 + sp->link = 1;
563 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
564 + if (reg & BMCR_ANENABLE) {
565 + /* auto neg enabled */
566 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
567 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
568 + } else {
569 + /* no auto neg, just read duplex config */
570 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
571 + }
572 +
573 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
574 + dev->name, (duplex) ? "full" : "half");
575 +
576 + if (duplex) {
577 + /* full duplex */
578 + sp->eth_regs->mac_control =
579 + ((sp->eth_regs->
580 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
581 + } else {
582 + /* half duplex */
583 + sp->eth_regs->mac_control =
584 + ((sp->eth_regs->
585 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
586 + }
587 + } else {
588 + /* no link */
589 + sp->link = 0;
590 + }
591 + sp->phyData = phyData;
592 + }
593 +}
594 +
595 +static int ar231x_reset_reg(struct net_device *dev)
596 +{
597 + struct ar231x_private *sp = netdev_priv(dev);
598 + unsigned int ethsal, ethsah;
599 + unsigned int flags;
600 +
601 + *sp->int_regs |= sp->cfg->reset_mac;
602 + mdelay(10);
603 + *sp->int_regs &= ~sp->cfg->reset_mac;
604 + mdelay(10);
605 + *sp->int_regs |= sp->cfg->reset_phy;
606 + mdelay(10);
607 + *sp->int_regs &= ~sp->cfg->reset_phy;
608 + mdelay(10);
609 +
610 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
611 + mdelay(10);
612 + sp->dma_regs->bus_mode =
613 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
614 +
615 + /* enable interrupts */
616 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
617 + DMA_STATUS_NIS |
618 + DMA_STATUS_RI |
619 + DMA_STATUS_TI | DMA_STATUS_FBE);
620 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
621 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
622 + sp->dma_regs->control =
623 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
624 +
625 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
626 + sp->eth_regs->vlan_tag = (0x8100);
627 +
628 + /* Enable Ethernet Interface */
629 + flags = (MAC_CONTROL_TE | /* transmit enable */
630 + MAC_CONTROL_PM | /* pass mcast */
631 + MAC_CONTROL_F | /* full duplex */
632 + MAC_CONTROL_HBD); /* heart beat disabled */
633 +
634 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
635 + flags |= MAC_CONTROL_PR;
636 + }
637 + sp->eth_regs->mac_control = flags;
638 +
639 + /* Set all Ethernet station address registers to their initial values */
640 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
641 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
642 +
643 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
644 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
645 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
646 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
647 +
648 + sp->eth_regs->mac_addr[0] = ethsah;
649 + sp->eth_regs->mac_addr[1] = ethsal;
650 +
651 + mdelay(10);
652 +
653 + return (0);
654 +}
655 +
656 +
657 +static int ar231x_init(struct net_device *dev)
658 +{
659 + struct ar231x_private *sp = netdev_priv(dev);
660 + int ecode = 0;
661 +
662 + /*
663 + * Allocate descriptors
664 + */
665 + if (ar231x_allocate_descriptors(dev)) {
666 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
667 + dev->name, __FUNCTION__);
668 + ecode = -EAGAIN;
669 + goto init_error;
670 + }
671 +
672 + /*
673 + * Get the memory for the skb rings.
674 + */
675 + if (sp->rx_skb == NULL) {
676 + sp->rx_skb =
677 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
678 + GFP_KERNEL);
679 + if (!(sp->rx_skb)) {
680 + printk("%s: %s: rx_skb kmalloc failed\n",
681 + dev->name, __FUNCTION__);
682 + ecode = -EAGAIN;
683 + goto init_error;
684 + }
685 + }
686 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
687 +
688 + if (sp->tx_skb == NULL) {
689 + sp->tx_skb =
690 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
691 + GFP_KERNEL);
692 + if (!(sp->tx_skb)) {
693 + printk("%s: %s: tx_skb kmalloc failed\n",
694 + dev->name, __FUNCTION__);
695 + ecode = -EAGAIN;
696 + goto init_error;
697 + }
698 + }
699 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
700 +
701 + /*
702 + * Set tx_csm before we start receiving interrupts, otherwise
703 + * the interrupt handler might think it is supposed to process
704 + * tx ints before we are up and running, which may cause a null
705 + * pointer access in the int handler.
706 + */
707 + sp->rx_skbprd = 0;
708 + sp->cur_rx = 0;
709 + sp->tx_prd = 0;
710 + sp->tx_csm = 0;
711 +
712 + /*
713 + * Zero the stats before starting the interface
714 + */
715 + memset(&dev->stats, 0, sizeof(dev->stats));
716 +
717 + /*
718 + * We load the ring here as there seem to be no way to tell the
719 + * firmware to wipe the ring without re-initializing it.
720 + */
721 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
722 +
723 + /*
724 + * Init hardware
725 + */
726 + ar231x_reset_reg(dev);
727 +
728 + /*
729 + * Get the IRQ
730 + */
731 + ecode =
732 + request_irq(dev->irq, &ar231x_interrupt,
733 + IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
734 + dev->name, dev);
735 + if (ecode) {
736 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
737 + dev->name, __FUNCTION__, dev->irq);
738 + goto init_error;
739 + }
740 +
741 +
742 + tasklet_enable(&sp->rx_tasklet);
743 +
744 + return 0;
745 +
746 + init_error:
747 + ar231x_init_cleanup(dev);
748 + return ecode;
749 +}
750 +
751 +/*
752 + * Load the rx ring.
753 + *
754 + * Loading rings is safe without holding the spin lock since this is
755 + * done only before the device is enabled, thus no interrupts are
756 + * generated and by the interrupt handler/tasklet handler.
757 + */
758 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
759 +{
760 +
761 + struct ar231x_private *sp = netdev_priv(dev);
762 + short i, idx;
763 +
764 + idx = sp->rx_skbprd;
765 +
766 + for (i = 0; i < nr_bufs; i++) {
767 + struct sk_buff *skb;
768 + ar231x_descr_t *rd;
769 +
770 + if (sp->rx_skb[idx])
771 + break;
772 +
773 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
774 + if (!skb) {
775 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
776 + __FUNCTION__);
777 + break;
778 + }
779 +
780 + /*
781 + * Make sure IP header starts on a fresh cache line.
782 + */
783 + skb->dev = dev;
784 + skb_reserve(skb, RX_OFFSET);
785 + sp->rx_skb[idx] = skb;
786 +
787 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
788 +
789 + /* initialize dma descriptor */
790 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
791 + DMA_RX1_CHAINED);
792 + rd->addr = virt_to_phys(skb->data);
793 + rd->descr =
794 + virt_to_phys(&sp->
795 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
796 + rd->status = DMA_RX_OWN;
797 +
798 + idx = DSC_NEXT(idx);
799 + }
800 +
801 + if (i)
802 + sp->rx_skbprd = idx;
803 +
804 + return;
805 +}
806 +
807 +#define AR2313_MAX_PKTS_PER_CALL 64
808 +
809 +static int ar231x_rx_int(struct net_device *dev)
810 +{
811 + struct ar231x_private *sp = netdev_priv(dev);
812 + struct sk_buff *skb, *skb_new;
813 + ar231x_descr_t *rxdesc;
814 + unsigned int status;
815 + u32 idx;
816 + int pkts = 0;
817 + int rval;
818 +
819 + idx = sp->cur_rx;
820 +
821 + /* process at most the entire ring and then wait for another interrupt
822 + */
823 + while (1) {
824 +
825 + rxdesc = &sp->rx_ring[idx];
826 + status = rxdesc->status;
827 + if (status & DMA_RX_OWN) {
828 + /* SiByte owns descriptor or descr not yet filled in */
829 + rval = 0;
830 + break;
831 + }
832 +
833 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
834 + rval = 1;
835 + break;
836 + }
837 +
838 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
839 + dev->stats.rx_errors++;
840 + dev->stats.rx_dropped++;
841 +
842 + /* add statistics counters */
843 + if (status & DMA_RX_ERR_CRC)
844 + dev->stats.rx_crc_errors++;
845 + if (status & DMA_RX_ERR_COL)
846 + dev->stats.rx_over_errors++;
847 + if (status & DMA_RX_ERR_LENGTH)
848 + dev->stats.rx_length_errors++;
849 + if (status & DMA_RX_ERR_RUNT)
850 + dev->stats.rx_over_errors++;
851 + if (status & DMA_RX_ERR_DESC)
852 + dev->stats.rx_over_errors++;
853 +
854 + } else {
855 + /* alloc new buffer. */
856 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
857 + if (skb_new != NULL) {
858 +
859 + skb = sp->rx_skb[idx];
860 + /* set skb */
861 + skb_put(skb,
862 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
863 +
864 + dev->stats.rx_bytes += skb->len;
865 + skb->protocol = eth_type_trans(skb, dev);
866 + /* pass the packet to upper layers */
867 + netif_rx(skb);
868 +
869 + skb_new->dev = dev;
870 + /* 16 bit align */
871 + skb_reserve(skb_new, RX_OFFSET);
872 + /* reset descriptor's curr_addr */
873 + rxdesc->addr = virt_to_phys(skb_new->data);
874 +
875 + dev->stats.rx_packets++;
876 + sp->rx_skb[idx] = skb_new;
877 + } else {
878 + dev->stats.rx_dropped++;
879 + }
880 + }
881 +
882 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
883 + DMA_RX1_CHAINED);
884 + rxdesc->status = DMA_RX_OWN;
885 +
886 + idx = DSC_NEXT(idx);
887 + }
888 +
889 + sp->cur_rx = idx;
890 +
891 + return rval;
892 +}
893 +
894 +
895 +static void ar231x_tx_int(struct net_device *dev)
896 +{
897 + struct ar231x_private *sp = netdev_priv(dev);
898 + u32 idx;
899 + struct sk_buff *skb;
900 + ar231x_descr_t *txdesc;
901 + unsigned int status = 0;
902 +
903 + idx = sp->tx_csm;
904 +
905 + while (idx != sp->tx_prd) {
906 + txdesc = &sp->tx_ring[idx];
907 +
908 + if ((status = txdesc->status) & DMA_TX_OWN) {
909 + /* ar231x dma still owns descr */
910 + break;
911 + }
912 + /* done with this descriptor */
913 + dma_unmap_single(NULL, txdesc->addr,
914 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
915 + DMA_TO_DEVICE);
916 + txdesc->status = 0;
917 +
918 + if (status & DMA_TX_ERROR) {
919 + dev->stats.tx_errors++;
920 + dev->stats.tx_dropped++;
921 + if (status & DMA_TX_ERR_UNDER)
922 + dev->stats.tx_fifo_errors++;
923 + if (status & DMA_TX_ERR_HB)
924 + dev->stats.tx_heartbeat_errors++;
925 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
926 + dev->stats.tx_carrier_errors++;
927 + if (status & (DMA_TX_ERR_LATE |
928 + DMA_TX_ERR_COL |
929 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
930 + dev->stats.tx_aborted_errors++;
931 + } else {
932 + /* transmit OK */
933 + dev->stats.tx_packets++;
934 + }
935 +
936 + skb = sp->tx_skb[idx];
937 + sp->tx_skb[idx] = NULL;
938 + idx = DSC_NEXT(idx);
939 + dev->stats.tx_bytes += skb->len;
940 + dev_kfree_skb_irq(skb);
941 + }
942 +
943 + sp->tx_csm = idx;
944 +
945 + return;
946 +}
947 +
948 +
949 +static void rx_tasklet_func(unsigned long data)
950 +{
951 + struct net_device *dev = (struct net_device *) data;
952 + struct ar231x_private *sp = netdev_priv(dev);
953 +
954 + if (sp->unloading) {
955 + return;
956 + }
957 +
958 + if (ar231x_rx_int(dev)) {
959 + tasklet_hi_schedule(&sp->rx_tasklet);
960 + } else {
961 + unsigned long flags;
962 + spin_lock_irqsave(&sp->lock, flags);
963 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
964 + spin_unlock_irqrestore(&sp->lock, flags);
965 + }
966 +}
967 +
968 +static void rx_schedule(struct net_device *dev)
969 +{
970 + struct ar231x_private *sp = netdev_priv(dev);
971 +
972 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
973 +
974 + tasklet_hi_schedule(&sp->rx_tasklet);
975 +}
976 +
977 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
978 +{
979 + struct net_device *dev = (struct net_device *) dev_id;
980 + struct ar231x_private *sp = netdev_priv(dev);
981 + unsigned int status, enabled;
982 +
983 + /* clear interrupt */
984 + /*
985 + * Don't clear RI bit if currently disabled.
986 + */
987 + status = sp->dma_regs->status;
988 + enabled = sp->dma_regs->intr_ena;
989 + sp->dma_regs->status = status & enabled;
990 +
991 + if (status & DMA_STATUS_NIS) {
992 + /* normal status */
993 + /*
994 + * Don't schedule rx processing if interrupt
995 + * is already disabled.
996 + */
997 + if (status & enabled & DMA_STATUS_RI) {
998 + /* receive interrupt */
999 + rx_schedule(dev);
1000 + }
1001 + if (status & DMA_STATUS_TI) {
1002 + /* transmit interrupt */
1003 + ar231x_tx_int(dev);
1004 + }
1005 + }
1006 +
1007 + /* abnormal status */
1008 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1009 + ar231x_restart(dev);
1010 + }
1011 + return IRQ_HANDLED;
1012 +}
1013 +
1014 +
1015 +static int ar231x_open(struct net_device *dev)
1016 +{
1017 + struct ar231x_private *sp = netdev_priv(dev);
1018 + unsigned int ethsal, ethsah;
1019 +
1020 + /* reset the hardware, in case the MAC address changed */
1021 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1022 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1023 +
1024 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1025 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1026 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1027 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1028 +
1029 + sp->eth_regs->mac_addr[0] = ethsah;
1030 + sp->eth_regs->mac_addr[1] = ethsal;
1031 +
1032 + mdelay(10);
1033 +
1034 + dev->mtu = 1500;
1035 + netif_start_queue(dev);
1036 +
1037 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1038 +
1039 + return 0;
1040 +}
1041 +
1042 +static void ar231x_halt(struct net_device *dev)
1043 +{
1044 + struct ar231x_private *sp = netdev_priv(dev);
1045 + int j;
1046 +
1047 + tasklet_disable(&sp->rx_tasklet);
1048 +
1049 + /* kill the MAC */
1050 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1051 + MAC_CONTROL_TE); /* disable Transmits */
1052 + /* stop dma */
1053 + sp->dma_regs->control = 0;
1054 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1055 +
1056 + /* place phy and MAC in reset */
1057 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1058 +
1059 + /* free buffers on tx ring */
1060 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1061 + struct sk_buff *skb;
1062 + ar231x_descr_t *txdesc;
1063 +
1064 + txdesc = &sp->tx_ring[j];
1065 + txdesc->descr = 0;
1066 +
1067 + skb = sp->tx_skb[j];
1068 + if (skb) {
1069 + dev_kfree_skb(skb);
1070 + sp->tx_skb[j] = NULL;
1071 + }
1072 + }
1073 +}
1074 +
1075 +/*
1076 + * close should do nothing. Here's why. It's called when
1077 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1078 + * the irq is gone forever ! When bond0 is made 'up' again,
1079 + * the ar231x_open () does not call request_irq (). Worse,
1080 + * the call to ar231x_halt() generates a WDOG reset due to
1081 + * the write to 'sp->int_regs' and the box reboots.
1082 + * Commenting this out is good since it allows the
1083 + * system to resume when bond0 is made up again.
1084 + */
1085 +static int ar231x_close(struct net_device *dev)
1086 +{
1087 +#if 0
1088 + /*
1089 + * Disable interrupts
1090 + */
1091 + disable_irq(dev->irq);
1092 +
1093 + /*
1094 + * Without (or before) releasing irq and stopping hardware, this
1095 + * is an absolute non-sense, by the way. It will be reset instantly
1096 + * by the first irq.
1097 + */
1098 + netif_stop_queue(dev);
1099 +
1100 + /* stop the MAC and DMA engines */
1101 + ar231x_halt(dev);
1102 +
1103 + /* release the interrupt */
1104 + free_irq(dev->irq, dev);
1105 +
1106 +#endif
1107 + return 0;
1108 +}
1109 +
1110 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1111 +{
1112 + struct ar231x_private *sp = netdev_priv(dev);
1113 + ar231x_descr_t *td;
1114 + u32 idx;
1115 +
1116 + idx = sp->tx_prd;
1117 + td = &sp->tx_ring[idx];
1118 +
1119 + if (td->status & DMA_TX_OWN) {
1120 + /* free skbuf and lie to the caller that we sent it out */
1121 + dev->stats.tx_dropped++;
1122 + dev_kfree_skb(skb);
1123 +
1124 + /* restart transmitter in case locked */
1125 + sp->dma_regs->xmt_poll = 0;
1126 + return 0;
1127 + }
1128 +
1129 + /* Setup the transmit descriptor. */
1130 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1131 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1132 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1133 + td->status = DMA_TX_OWN;
1134 +
1135 + /* kick transmitter last */
1136 + sp->dma_regs->xmt_poll = 0;
1137 +
1138 + sp->tx_skb[idx] = skb;
1139 + idx = DSC_NEXT(idx);
1140 + sp->tx_prd = idx;
1141 +
1142 + return 0;
1143 +}
1144 +
1145 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1146 +{
1147 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1148 + struct ar231x_private *sp = netdev_priv(dev);
1149 + int ret;
1150 +
1151 + switch (cmd) {
1152 +
1153 + case SIOCETHTOOL:
1154 + spin_lock_irq(&sp->lock);
1155 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1156 + spin_unlock_irq(&sp->lock);
1157 + return ret;
1158 +
1159 + case SIOCSIFHWADDR:
1160 + if (copy_from_user
1161 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1162 + return -EFAULT;
1163 + return 0;
1164 +
1165 + case SIOCGIFHWADDR:
1166 + if (copy_to_user
1167 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1168 + return -EFAULT;
1169 + return 0;
1170 +
1171 + case SIOCGMIIPHY:
1172 + case SIOCGMIIREG:
1173 + case SIOCSMIIREG:
1174 + return phy_mii_ioctl(sp->phy_dev, data, cmd);
1175 +
1176 + default:
1177 + break;
1178 + }
1179 +
1180 + return -EOPNOTSUPP;
1181 +}
1182 +
1183 +static void ar231x_adjust_link(struct net_device *dev)
1184 +{
1185 + struct ar231x_private *sp = netdev_priv(dev);
1186 + unsigned int mc;
1187 +
1188 + if (!sp->phy_dev->link)
1189 + return;
1190 +
1191 + if (sp->phy_dev->duplex != sp->oldduplex) {
1192 + mc = readl(&sp->eth_regs->mac_control);
1193 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1194 + if (sp->phy_dev->duplex)
1195 + mc |= MAC_CONTROL_F;
1196 + else
1197 + mc |= MAC_CONTROL_DRO;
1198 + writel(mc, &sp->eth_regs->mac_control);
1199 + sp->oldduplex = sp->phy_dev->duplex;
1200 + }
1201 +}
1202 +
1203 +#define MII_ADDR(phy, reg) \
1204 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1205 +
1206 +static int
1207 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1208 +{
1209 + struct net_device *const dev = bus->priv;
1210 + struct ar231x_private *sp = netdev_priv(dev);
1211 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1212 +
1213 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1214 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1215 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1216 +}
1217 +
1218 +static int
1219 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1220 + u16 value)
1221 +{
1222 + struct net_device *const dev = bus->priv;
1223 + struct ar231x_private *sp = netdev_priv(dev);
1224 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1225 +
1226 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1227 + ethernet->mii_data = value << MII_DATA_SHIFT;
1228 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1229 +
1230 + return 0;
1231 +}
1232 +
1233 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1234 +{
1235 + struct net_device *const dev = bus->priv;
1236 +
1237 + ar231x_reset_reg(dev);
1238 +
1239 + return 0;
1240 +}
1241 +
1242 +static int ar231x_mdiobus_probe (struct net_device *dev)
1243 +{
1244 + struct ar231x_private *const sp = netdev_priv(dev);
1245 + struct phy_device *phydev = NULL;
1246 + int phy_addr;
1247 +
1248 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1249 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1250 + if (sp->mii_bus->phy_map[phy_addr]) {
1251 + phydev = sp->mii_bus->phy_map[phy_addr];
1252 + sp->phy = phy_addr;
1253 + break; /* break out with first one found */
1254 + }
1255 +
1256 + if (!phydev) {
1257 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1258 + return -1;
1259 + }
1260 +
1261 + /* now we are supposed to have a proper phydev, to attach to... */
1262 + BUG_ON(!phydev);
1263 + BUG_ON(phydev->attached_dev);
1264 +
1265 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1266 + PHY_INTERFACE_MODE_MII);
1267 +
1268 + if (IS_ERR(phydev)) {
1269 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1270 + return PTR_ERR(phydev);
1271 + }
1272 +
1273 + /* mask with MAC supported features */
1274 + phydev->supported &= (SUPPORTED_10baseT_Half
1275 + | SUPPORTED_10baseT_Full
1276 + | SUPPORTED_100baseT_Half
1277 + | SUPPORTED_100baseT_Full
1278 + | SUPPORTED_Autoneg
1279 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1280 + | SUPPORTED_MII
1281 + | SUPPORTED_TP);
1282 +
1283 + phydev->advertising = phydev->supported;
1284 +
1285 + sp->oldduplex = -1;
1286 + sp->phy_dev = phydev;
1287 +
1288 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1289 + "(mii_bus:phy_addr=%s)\n",
1290 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1291 +
1292 + return 0;
1293 +}
1294 +
1295 --- /dev/null
1296 +++ b/drivers/net/ar231x.h
1297 @@ -0,0 +1,302 @@
1298 +/*
1299 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1300 + *
1301 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1302 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1303 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1304 + *
1305 + * Thanks to Atheros for providing hardware and documentation
1306 + * enabling me to write this driver.
1307 + *
1308 + * This program is free software; you can redistribute it and/or modify
1309 + * it under the terms of the GNU General Public License as published by
1310 + * the Free Software Foundation; either version 2 of the License, or
1311 + * (at your option) any later version.
1312 + */
1313 +
1314 +#ifndef _AR2313_H_
1315 +#define _AR2313_H_
1316 +
1317 +#include <generated/autoconf.h>
1318 +#include <linux/bitops.h>
1319 +#include <asm/bootinfo.h>
1320 +#include <ar231x_platform.h>
1321 +
1322 +/*
1323 + * probe link timer - 5 secs
1324 + */
1325 +#define LINK_TIMER (5*HZ)
1326 +
1327 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1328 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1329 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1330 +
1331 +#define AR2313_TX_TIMEOUT (HZ/4)
1332 +
1333 +/*
1334 + * Rings
1335 + */
1336 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1337 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1338 +
1339 +#define AR2313_MBGET 2
1340 +#define AR2313_MBSET 3
1341 +#define AR2313_PCI_RECONFIG 4
1342 +#define AR2313_PCI_DUMP 5
1343 +#define AR2313_TEST_PANIC 6
1344 +#define AR2313_TEST_NULLPTR 7
1345 +#define AR2313_READ_DATA 8
1346 +#define AR2313_WRITE_DATA 9
1347 +#define AR2313_GET_VERSION 10
1348 +#define AR2313_TEST_HANG 11
1349 +#define AR2313_SYNC 12
1350 +
1351 +#define DMA_RX_ERR_CRC BIT(1)
1352 +#define DMA_RX_ERR_DRIB BIT(2)
1353 +#define DMA_RX_ERR_MII BIT(3)
1354 +#define DMA_RX_EV2 BIT(5)
1355 +#define DMA_RX_ERR_COL BIT(6)
1356 +#define DMA_RX_LONG BIT(7)
1357 +#define DMA_RX_LS BIT(8) /* last descriptor */
1358 +#define DMA_RX_FS BIT(9) /* first descriptor */
1359 +#define DMA_RX_MF BIT(10) /* multicast frame */
1360 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1361 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1362 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1363 +#define DMA_RX_ERROR BIT(15) /* error summary */
1364 +#define DMA_RX_LEN_MASK 0x3fff0000
1365 +#define DMA_RX_LEN_SHIFT 16
1366 +#define DMA_RX_FILT BIT(30)
1367 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1368 +
1369 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1370 +#define DMA_RX1_BSIZE_SHIFT 0
1371 +#define DMA_RX1_CHAINED BIT(24)
1372 +#define DMA_RX1_RER BIT(25)
1373 +
1374 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1375 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1376 +#define DMA_TX_COL_MASK 0x78
1377 +#define DMA_TX_COL_SHIFT 3
1378 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1379 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1380 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1381 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1382 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1383 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1384 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1385 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1386 +
1387 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1388 +#define DMA_TX1_BSIZE_SHIFT 0
1389 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1390 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1391 +#define DMA_TX1_FS BIT(29) /* first segment */
1392 +#define DMA_TX1_LS BIT(30) /* last segment */
1393 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1394 +
1395 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1396 +
1397 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1398 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1399 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1400 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1401 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1402 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1403 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1404 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1405 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1406 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1407 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1408 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1409 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1410 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1411 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1412 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1413 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1414 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1415 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1416 +
1417 +#define MII_ADDR_BUSY BIT(0)
1418 +#define MII_ADDR_WRITE BIT(1)
1419 +#define MII_ADDR_REG_SHIFT 6
1420 +#define MII_ADDR_PHY_SHIFT 11
1421 +#define MII_DATA_SHIFT 0
1422 +
1423 +#define FLOW_CONTROL_FCE BIT(1)
1424 +
1425 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1426 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1427 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1428 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1429 +
1430 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1431 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1432 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1433 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1434 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1435 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1436 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1437 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1438 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1439 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1440 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1441 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1442 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1443 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1444 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1445 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1446 +
1447 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1448 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1449 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1450 +
1451 +
1452 +typedef struct {
1453 + volatile unsigned int status; // OWN, Device control and status.
1454 + volatile unsigned int devcs; // pkt Control bits + Length
1455 + volatile unsigned int addr; // Current Address.
1456 + volatile unsigned int descr; // Next descriptor in chain.
1457 +} ar231x_descr_t;
1458 +
1459 +
1460 +
1461 +//
1462 +// New Combo structure for Both Eth0 AND eth1
1463 +//
1464 +typedef struct {
1465 + volatile unsigned int mac_control; /* 0x00 */
1466 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1467 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1468 + volatile unsigned int mii_addr; /* 0x14 */
1469 + volatile unsigned int mii_data; /* 0x18 */
1470 + volatile unsigned int flow_control; /* 0x1c */
1471 + volatile unsigned int vlan_tag; /* 0x20 */
1472 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1473 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1474 +
1475 +} ETHERNET_STRUCT;
1476 +
1477 +/********************************************************************
1478 + * Interrupt controller
1479 + ********************************************************************/
1480 +
1481 +typedef struct {
1482 + volatile unsigned int wdog_control; /* 0x08 */
1483 + volatile unsigned int wdog_timer; /* 0x0c */
1484 + volatile unsigned int misc_status; /* 0x10 */
1485 + volatile unsigned int misc_mask; /* 0x14 */
1486 + volatile unsigned int global_status; /* 0x18 */
1487 + volatile unsigned int reserved; /* 0x1c */
1488 + volatile unsigned int reset_control; /* 0x20 */
1489 +} INTERRUPT;
1490 +
1491 +/********************************************************************
1492 + * DMA controller
1493 + ********************************************************************/
1494 +typedef struct {
1495 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1496 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1497 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1498 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1499 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1500 + volatile unsigned int status; /* 0x14 (CSR5) */
1501 + volatile unsigned int control; /* 0x18 (CSR6) */
1502 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1503 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1504 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1505 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1506 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1507 +} DMA;
1508 +
1509 +/*
1510 + * Struct private for the Sibyte.
1511 + *
1512 + * Elements are grouped so variables used by the tx handling goes
1513 + * together, and will go into the same cache lines etc. in order to
1514 + * avoid cache line contention between the rx and tx handling on SMP.
1515 + *
1516 + * Frequently accessed variables are put at the beginning of the
1517 + * struct to help the compiler generate better/shorter code.
1518 + */
1519 +struct ar231x_private {
1520 + struct net_device *dev;
1521 + int version;
1522 + u32 mb[2];
1523 +
1524 + volatile ETHERNET_STRUCT *phy_regs;
1525 + volatile ETHERNET_STRUCT *eth_regs;
1526 + volatile DMA *dma_regs;
1527 + volatile u32 *int_regs;
1528 + struct ar231x_eth *cfg;
1529 +
1530 + spinlock_t lock; /* Serialise access to device */
1531 +
1532 + /*
1533 + * RX and TX descriptors, must be adjacent
1534 + */
1535 + ar231x_descr_t *rx_ring;
1536 + ar231x_descr_t *tx_ring;
1537 +
1538 +
1539 + struct sk_buff **rx_skb;
1540 + struct sk_buff **tx_skb;
1541 +
1542 + /*
1543 + * RX elements
1544 + */
1545 + u32 rx_skbprd;
1546 + u32 cur_rx;
1547 +
1548 + /*
1549 + * TX elements
1550 + */
1551 + u32 tx_prd;
1552 + u32 tx_csm;
1553 +
1554 + /*
1555 + * Misc elements
1556 + */
1557 + char name[48];
1558 + struct {
1559 + u32 address;
1560 + u32 length;
1561 + char *mapping;
1562 + } desc;
1563 +
1564 +
1565 + struct timer_list link_timer;
1566 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1567 + unsigned short mac;
1568 + unsigned short link; /* 0 - link down, 1 - link up */
1569 + u16 phyData;
1570 +
1571 + struct tasklet_struct rx_tasklet;
1572 + int unloading;
1573 +
1574 + struct phy_device *phy_dev;
1575 + struct mii_bus *mii_bus;
1576 + int oldduplex;
1577 +};
1578 +
1579 +
1580 +/*
1581 + * Prototypes
1582 + */
1583 +static int ar231x_init(struct net_device *dev);
1584 +#ifdef TX_TIMEOUT
1585 +static void ar231x_tx_timeout(struct net_device *dev);
1586 +#endif
1587 +static int ar231x_restart(struct net_device *dev);
1588 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1589 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1590 +static int ar231x_open(struct net_device *dev);
1591 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1592 +static int ar231x_close(struct net_device *dev);
1593 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1594 + int cmd);
1595 +static void ar231x_init_cleanup(struct net_device *dev);
1596 +static int ar231x_setup_timer(struct net_device *dev);
1597 +static void ar231x_link_timer_fn(unsigned long data);
1598 +static void ar231x_check_link(struct net_device *dev);
1599 +#endif /* _AR2313_H_ */
Personal OpenWRT clone
This page took 0.109799 seconds and 5 git commands to generate.