target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c

   1 /*
   2  * Ralink RT3662/RT3883 SoC specific setup
   3  *
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mach-ralink/common.h>
  18 #include <asm/mach-ralink/ramips_gpio.h>
  19 #include <asm/mach-ralink/rt3883.h>
  20 #include <asm/mach-ralink/rt3883_regs.h>
  21
  22 void __iomem * rt3883_sysc_base;
  23 void __iomem * rt3883_memc_base;
  24
  25 void __init ramips_soc_prom_init(void)
  26 {
  27         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
  28         u32 n0;
  29         u32 n1;
  30         u32 id;
  31
  32         n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
  33         n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
  34         id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
  35
  36         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  37                 "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u",
  38                 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
  39                 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
  40                 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
  41                 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
  42                 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
  43                 (id & RT3883_REVID_ECO_ID_MASK));
  44 }
  45
  46 static struct ramips_gpio_chip rt3883_gpio_chips[] = {
  47         {
  48                 .chip = {
  49                         .label                  = "RT3883-GPIO0",
  50                         .base                   = 0,
  51                         .ngpio                  = 24,
  52                 },
  53                 .regs = {
  54                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  55                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  56                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  57                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  58                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  59                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  60                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  61                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  62                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  63                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  64                 },
  65                 .map_base       = RT3883_PIO_BASE,
  66                 .map_size       = RT3883_PIO_SIZE,
  67         },
  68         {
  69                 .chip = {
  70                         .label                  = "RT3883-GPIO1",
  71                         .base                   = 24,
  72                         .ngpio                  = 16,
  73                 },
  74                 .regs = {
  75                         [RAMIPS_GPIO_REG_INT]   = 0x38,
  76                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
  77                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
  78                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
  79                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
  80                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
  81                         [RAMIPS_GPIO_REG_POL]   = 0x50,
  82                         [RAMIPS_GPIO_REG_SET]   = 0x54,
  83                         [RAMIPS_GPIO_REG_RESET] = 0x58,
  84                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
  85                 },
  86                 .map_base       = RT3883_PIO_BASE,
  87                 .map_size       = RT3883_PIO_SIZE,
  88         },
  89         {
  90                 .chip = {
  91                         .label                  = "RT3883-GPIO2",
  92                         .base                   = 40,
  93                         .ngpio                  = 32,
  94                 },
  95                 .regs = {
  96                         [RAMIPS_GPIO_REG_INT]   = 0x60,
  97                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
  98                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
  99                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 100                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 101                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 102                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 103                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 104                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 105                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 106                 },
 107                 .map_base       = RT3883_PIO_BASE,
 108                 .map_size       = RT3883_PIO_SIZE,
 109         },
 110         {
 111                 .chip = {
 112                         .label                  = "RT3883-GPIO3",
 113                         .base                   = 72,
 114                         .ngpio                  = 24,
 115                 },
 116                 .regs = {
 117                         [RAMIPS_GPIO_REG_INT]   = 0x88,
 118                         [RAMIPS_GPIO_REG_EDGE]  = 0x8c,
 119                         [RAMIPS_GPIO_REG_RENA]  = 0x90,
 120                         [RAMIPS_GPIO_REG_FENA]  = 0x94,
 121                         [RAMIPS_GPIO_REG_DATA]  = 0x98,
 122                         [RAMIPS_GPIO_REG_DIR]   = 0x9c,
 123                         [RAMIPS_GPIO_REG_POL]   = 0xa0,
 124                         [RAMIPS_GPIO_REG_SET]   = 0xa4,
 125                         [RAMIPS_GPIO_REG_RESET] = 0xa8,
 126                         [RAMIPS_GPIO_REG_TOGGLE] = 0xac,
 127                 },
 128                 .map_base       = RT3883_PIO_BASE,
 129                 .map_size       = RT3883_PIO_SIZE,
 130         },
 131 };
 132
 133 static struct ramips_gpio_data rt3883_gpio_data = {
 134         .chips = rt3883_gpio_chips,
 135         .num_chips = ARRAY_SIZE(rt3883_gpio_chips),
 136 };
 137
 138 static void rt3883_gpio_reserve(int first, int last)
 139 {
 140         for (; first <= last; first++)
 141                 gpio_request(first, "reserved");
 142 }
 143
 144 void __init rt3883_gpio_init(u32 mode)
 145 {
 146         u32 t;
 147
 148         rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE);
 149
 150         ramips_gpio_init(&rt3883_gpio_data);
 151         if ((mode & RT3883_GPIO_MODE_I2C) == 0)
 152                 rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK);
 153
 154         if ((mode & RT3883_GPIO_MODE_SPI) == 0)
 155                 rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_CLK);
 156
 157         t = mode >> RT3883_GPIO_MODE_UART0_SHIFT;
 158         t &= RT3883_GPIO_MODE_UART0_MASK;
 159         switch (t) {
 160         case RT3883_GPIO_MODE_UARTF:
 161         case RT3883_GPIO_MODE_PCM_UARTF:
 162         case RT3883_GPIO_MODE_PCM_I2S:
 163         case RT3883_GPIO_MODE_I2S_UARTF:
 164                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14);
 165                 break;
 166         case RT3883_GPIO_MODE_PCM_GPIO:
 167                 rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14);
 168                 break;
 169         case RT3883_GPIO_MODE_GPIO_UARTF:
 170         case RT3883_GPIO_MODE_GPIO_I2S:
 171                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10);
 172                 break;
 173         }
 174
 175         if ((mode & RT3883_GPIO_MODE_UART1) == 0)
 176                 rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD,
 177                                     RT3883_GPIO_UART1_RXD);
 178
 179         if ((mode & RT3883_GPIO_MODE_JTAG) == 0)
 180                 rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO,
 181                                     RT3883_GPIO_JTAG_TCLK);
 182
 183         if ((mode & RT3883_GPIO_MODE_MDIO) == 0)
 184                 rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC,
 185                                     RT3883_GPIO_MDIO_MDIO);
 186
 187         if ((mode & RT3883_GPIO_MODE_GE1) == 0)
 188                 rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0,
 189                                     RT3883_GPIO_GE1_RXCLK);
 190
 191         if ((mode & RT3883_GPIO_MODE_GE2) == 0)
 192                 rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0,
 193                                     RT3883_GPIO_GE2_RXCLK);
 194
 195         t = mode >> RT3883_GPIO_MODE_PCI_SHIFT;
 196         t &= RT3883_GPIO_MODE_PCI_MASK;
 197         if (t != RT3883_GPIO_MODE_PCI_GPIO)
 198                 rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0,
 199                                     RT3883_GPIO_PCI_AD31);
 200
 201         t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT;
 202         t &= RT3883_GPIO_MODE_LNA_A_MASK;
 203         if (t != RT3883_GPIO_MODE_LNA_A_GPIO)
 204                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0,
 205                                     RT3883_GPIO_LNA_PE_A2);
 206
 207         t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT;
 208         t &= RT3883_GPIO_MODE_LNA_G_MASK;
 209         if (t != RT3883_GPIO_MODE_LNA_G_GPIO)
 210                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0,
 211                                     RT3883_GPIO_LNA_PE_G2);
 212 }