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target/linux: refresh 2.6.32 patches
[openwrt.git] / target / linux / generic-2.6 / patches-2.6.33 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
4 {
5 if (!cc->dev)
6 return; /* We don't have a ChipCommon */
7 + if (cc->dev->id.revision >= 11)
8 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
9 ssb_pmu_init(cc);
10 chipco_powercontrol_init(cc);
11 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
12 @@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
13 {
14 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
15 }
16 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
17
18 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
19 {
20 --- a/drivers/ssb/driver_chipcommon_pmu.c
21 +++ b/drivers/ssb/driver_chipcommon_pmu.c
22 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
23 case 0x5354:
24 ssb_pmu0_pllinit_r0(cc, crystalfreq);
25 break;
26 + case 0x4322:
27 + if (cc->pmu.rev == 2) {
28 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
29 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
30 + }
31 + break;
32 default:
33 ssb_printk(KERN_ERR PFX
34 "ERROR: PLL init unknown for device %04X\n",
35 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
36
37 switch (bus->chip_id) {
38 case 0x4312:
39 + case 0x4322:
40 /* We keep the default settings:
41 * min_msk = 0xCBB
42 * max_msk = 0x7FFFF
43 --- a/drivers/ssb/driver_mipscore.c
44 +++ b/drivers/ssb/driver_mipscore.c
45 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
46 set_irq(dev, irq++);
47 }
48 break;
49 - /* fallthrough */
50 case SSB_DEV_PCI:
51 case SSB_DEV_ETHERNET:
52 case SSB_DEV_ETHERNET_GBIT:
53 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
54 set_irq(dev, irq++);
55 break;
56 }
57 + /* fallthrough */
58 + case SSB_DEV_EXTIF:
59 + set_irq(dev, 0);
60 + break;
61 }
62 }
63 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
64 --- a/drivers/ssb/driver_pcicore.c
65 +++ b/drivers/ssb/driver_pcicore.c
66 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
67 .pci_ops = &ssb_pcicore_pciops,
68 .io_resource = &ssb_pcicore_io_resource,
69 .mem_resource = &ssb_pcicore_mem_resource,
70 - .mem_offset = 0x24000000,
71 };
72
73 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
74 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
75 -
76 /* This function is called when doing a pci_enable_device().
77 * We must first check if the device is a device on the PCI-core bridge. */
78 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
79 {
80 - struct resource *res;
81 - int pos, size;
82 - u32 *base;
83 -
84 if (d->bus->ops != &ssb_pcicore_pciops) {
85 /* This is not a device on the PCI-core bridge. */
86 return -ENODEV;
87 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
88 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
89 pci_name(d));
90
91 - /* Fix up resource bases */
92 - for (pos = 0; pos < 6; pos++) {
93 - res = &d->resource[pos];
94 - if (res->flags & IORESOURCE_IO)
95 - base = &ssb_pcicore_pcibus_iobase;
96 - else
97 - base = &ssb_pcicore_pcibus_membase;
98 - res->flags |= IORESOURCE_PCI_FIXED;
99 - if (res->end) {
100 - size = res->end - res->start + 1;
101 - if (*base & (size - 1))
102 - *base = (*base + size) & ~(size - 1);
103 - res->start = *base;
104 - res->end = res->start + size - 1;
105 - *base += size;
106 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
107 - }
108 - /* Fix up PCI bridge BAR0 only */
109 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
110 - break;
111 - }
112 /* Fix up interrupt lines */
113 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
114 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
115 --- a/drivers/ssb/main.c
116 +++ b/drivers/ssb/main.c
117 @@ -833,6 +833,9 @@ int ssb_bus_pcibus_register(struct ssb_b
118 if (!err) {
119 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
120 "PCI device %s\n", dev_name(&host_pci->dev));
121 + } else {
122 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
123 + " of SSB with error %d\n", err);
124 }
125
126 return err;
127 --- a/drivers/ssb/pci.c
128 +++ b/drivers/ssb/pci.c
129 @@ -167,7 +167,7 @@ err_pci:
130 }
131
132 /* Get the word-offset for a SSB_SPROM_XXX define. */
133 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
134 +#define SPOFF(offset) ((offset) / sizeof(u16))
135 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
136 #define SPEX16(_outvar, _offset, _mask, _shift) \
137 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
138 @@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus
139 int i;
140
141 for (i = 0; i < bus->sprom_size; i++)
142 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
143 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
144
145 return 0;
146 }
147 @@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
148 ssb_printk("75%%");
149 else if (i % 2)
150 ssb_printk(".");
151 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
152 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
153 mmiowb();
154 msleep(20);
155 }
156 @@ -620,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
157 int err = -ENOMEM;
158 u16 *buf;
159
160 + if (!ssb_is_sprom_available(bus)) {
161 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
162 + return -ENODEV;
163 + }
164 +
165 + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
166 + SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
167 +
168 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
169 if (!buf)
170 goto out;
171 --- a/drivers/ssb/sprom.c
172 +++ b/drivers/ssb/sprom.c
173 @@ -175,3 +175,17 @@ const struct ssb_sprom *ssb_get_fallback
174 {
175 return fallback_sprom;
176 }
177 +
178 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
179 +bool ssb_is_sprom_available(struct ssb_bus *bus)
180 +{
181 + /* status register only exists on chipcomon rev >= 11 and we need check
182 + for >= 31 only */
183 + /* this routine differs from specs as we do not access SPROM directly
184 + on PCMCIA */
185 + if (bus->bustype == SSB_BUSTYPE_PCI &&
186 + bus->chipco.dev->id.revision >= 31)
187 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
188 +
189 + return true;
190 +}
191 --- a/drivers/ssb/ssb_private.h
192 +++ b/drivers/ssb/ssb_private.h
193 @@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f
194 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
195 extern int __init b43_pci_ssb_bridge_init(void);
196 extern void __exit b43_pci_ssb_bridge_exit(void);
197 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
198 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
199 static inline int b43_pci_ssb_bridge_init(void)
200 {
201 return 0;
202 @@ -204,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
203 static inline void b43_pci_ssb_bridge_exit(void)
204 {
205 }
206 -#endif /* CONFIG_SSB_PCIHOST */
207 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
208
209 #endif /* LINUX_SSB_PRIVATE_H_ */
210 --- a/include/linux/ssb/ssb.h
211 +++ b/include/linux/ssb/ssb.h
212 @@ -305,6 +305,7 @@ struct ssb_bus {
213 /* ID information about the Chip. */
214 u16 chip_id;
215 u16 chip_rev;
216 + u16 sprom_offset;
217 u16 sprom_size; /* number of words in sprom */
218 u8 chip_package;
219
220 @@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
221
222 extern void ssb_bus_unregister(struct ssb_bus *bus);
223
224 +/* Does the device have an SPROM? */
225 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
226 +
227 /* Set a fallback SPROM.
228 * See kdoc at the function definition for complete documentation. */
229 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
230 --- a/include/linux/ssb/ssb_driver_chipcommon.h
231 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
232 @@ -53,6 +53,7 @@
233 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
234 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
235 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
236 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
237 #define SSB_CHIPCO_CORECTL 0x0008
238 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
239 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
240 @@ -385,6 +386,7 @@
241
242
243 /** Chip specific Chip-Status register contents. */
244 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
245 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
246 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
247 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
248 @@ -398,6 +400,18 @@
249 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
250 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
251
252 +/** Macros to determine SPROM presence based on Chip-Status register. */
253 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
254 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
255 + SSB_CHIPCO_CHST_4325_OTP_SEL)
256 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
257 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
258 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
259 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
260 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
261 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
262 + SSB_CHIPCO_CHST_4325_OTP_SEL))
263 +
264
265
266 /** Clockcontrol masks and values **/
267 @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
268 struct ssb_chipcommon {
269 struct ssb_device *dev;
270 u32 capabilities;
271 + u32 status;
272 /* Fast Powerup Delay constant */
273 u16 fast_pwrup_delay;
274 struct ssb_chipcommon_pmu pmu;
275 --- a/include/linux/ssb/ssb_regs.h
276 +++ b/include/linux/ssb/ssb_regs.h
277 @@ -170,26 +170,27 @@
278 #define SSB_SPROMSIZE_WORDS_R4 220
279 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
280 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
281 -#define SSB_SPROM_BASE 0x1000
282 -#define SSB_SPROM_REVISION 0x107E
283 +#define SSB_SPROM_BASE1 0x1000
284 +#define SSB_SPROM_BASE31 0x0800
285 +#define SSB_SPROM_REVISION 0x007E
286 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
287 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
288 #define SSB_SPROM_REVISION_CRC_SHIFT 8
289
290 /* SPROM Revision 1 */
291 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
292 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
293 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
294 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
295 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
296 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
297 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
298 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
299 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
300 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
301 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
302 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
303 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
304 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
305 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
306 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
307 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
308 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
309 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
310 -#define SSB_SPROM1_BINF 0x105C /* Board info */
311 +#define SSB_SPROM1_BINF 0x005C /* Board info */
312 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
313 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
314 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
315 @@ -197,63 +198,63 @@
316 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
317 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
318 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
319 -#define SSB_SPROM1_PA0B0 0x105E
320 -#define SSB_SPROM1_PA0B1 0x1060
321 -#define SSB_SPROM1_PA0B2 0x1062
322 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
323 +#define SSB_SPROM1_PA0B0 0x005E
324 +#define SSB_SPROM1_PA0B1 0x0060
325 +#define SSB_SPROM1_PA0B2 0x0062
326 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
327 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
328 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
329 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
330 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
331 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
332 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
333 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
334 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
335 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
336 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
337 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
338 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
339 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
340 -#define SSB_SPROM1_PA1B0 0x106A
341 -#define SSB_SPROM1_PA1B1 0x106C
342 -#define SSB_SPROM1_PA1B2 0x106E
343 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
344 +#define SSB_SPROM1_PA1B0 0x006A
345 +#define SSB_SPROM1_PA1B1 0x006C
346 +#define SSB_SPROM1_PA1B2 0x006E
347 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
348 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
349 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
350 #define SSB_SPROM1_ITSSI_A_SHIFT 8
351 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
352 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
353 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
354 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
355 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
356 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
357 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
358 #define SSB_SPROM1_AGAIN_A_SHIFT 8
359
360 /* SPROM Revision 2 (inherits from rev 1) */
361 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
362 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
363 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
364 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
365 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
366 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
367 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
368 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
369 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
370 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
371 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
372 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
373 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
374 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
375 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
376 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
377 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
378 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
379 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
380 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
381 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
382 #define SSB_SPROM2_OPO_VALUE 0x00FF
383 #define SSB_SPROM2_OPO_UNUSED 0xFF00
384 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
385 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
386
387 /* SPROM Revision 3 (inherits most data from rev 2) */
388 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
389 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
390 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
391 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
392 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
393 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
394 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
395 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
396 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
397 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
398 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
399 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
400 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
401 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
402 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
403 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
404 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
405 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
406 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
407 @@ -264,100 +265,100 @@
408 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
409
410 /* SPROM Revision 4 */
411 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
412 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
413 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
414 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
415 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
416 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
417 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
418 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
419 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
420 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
421 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
422 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
423 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
424 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
425 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
426 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
427 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
428 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
429 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
430 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
431 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
432 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
433 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
434 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
435 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
436 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
437 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
438 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
439 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
440 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
441 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
442 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
443 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
444 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
445 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
446 #define SSB_SPROM4_AGAIN0_SHIFT 0
447 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
448 #define SSB_SPROM4_AGAIN1_SHIFT 8
449 -#define SSB_SPROM4_AGAIN23 0x1060
450 +#define SSB_SPROM4_AGAIN23 0x0060
451 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
452 #define SSB_SPROM4_AGAIN2_SHIFT 0
453 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
454 #define SSB_SPROM4_AGAIN3_SHIFT 8
455 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
456 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
457 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
458 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
459 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
460 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
461 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
462 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
463 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
464 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
465 #define SSB_SPROM4_ITSSI_A_SHIFT 8
466 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
467 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
468 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
469 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
470 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
471 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
472 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
473 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
474 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
475 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
476 -#define SSB_SPROM4_PA0B2 0x1086
477 -#define SSB_SPROM4_PA1B0 0x108E
478 -#define SSB_SPROM4_PA1B1 0x1090
479 -#define SSB_SPROM4_PA1B2 0x1092
480 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
481 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
482 +#define SSB_SPROM4_PA0B2 0x0086
483 +#define SSB_SPROM4_PA1B0 0x008E
484 +#define SSB_SPROM4_PA1B1 0x0090
485 +#define SSB_SPROM4_PA1B2 0x0092
486
487 /* SPROM Revision 5 (inherits most data from rev 4) */
488 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
489 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
490 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
491 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
492 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
493 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
494 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
495 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
496 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
497 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
498 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
499 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
500 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
501 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
502 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
503 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
504 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
505 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
506
507 /* SPROM Revision 8 */
508 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
509 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
510 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
511 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
512 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
513 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
514 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
515 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
516 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
517 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
518 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
519 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
520 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
521 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
522 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
523 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
524 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
525 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
526 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
527 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
528 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
529 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
530 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
531 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
532 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
533 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
534 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
535 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
536 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
537 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
538 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
539 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
540 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
541 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
542 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
543 #define SSB_SPROM8_AGAIN0_SHIFT 0
544 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
545 #define SSB_SPROM8_AGAIN1_SHIFT 8
546 -#define SSB_SPROM8_AGAIN23 0x10A0
547 +#define SSB_SPROM8_AGAIN23 0x00A0
548 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
549 #define SSB_SPROM8_AGAIN2_SHIFT 0
550 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
551 #define SSB_SPROM8_AGAIN3_SHIFT 8
552 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
553 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
554 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
555 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
556 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
557 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
558 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
559 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
560 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
561 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
562 #define SSB_SPROM8_RSSISMF2G 0x000F
563 #define SSB_SPROM8_RSSISMC2G 0x00F0
564 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
565 @@ -365,7 +366,7 @@
566 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
567 #define SSB_SPROM8_BXA2G 0x1800
568 #define SSB_SPROM8_BXA2G_SHIFT 11
569 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
570 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
571 #define SSB_SPROM8_RSSISMF5G 0x000F
572 #define SSB_SPROM8_RSSISMC5G 0x00F0
573 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
574 @@ -373,47 +374,47 @@
575 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
576 #define SSB_SPROM8_BXA5G 0x1800
577 #define SSB_SPROM8_BXA5G_SHIFT 11
578 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
579 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
580 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
581 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
582 #define SSB_SPROM8_TRI5G_SHIFT 8
583 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
584 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
585 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
586 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
587 #define SSB_SPROM8_TRI5GH_SHIFT 8
588 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
589 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
590 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
591 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
592 #define SSB_SPROM8_RXPO5G_SHIFT 8
593 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
594 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
595 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
596 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
597 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
598 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
599 -#define SSB_SPROM8_PA0B1 0x10C4
600 -#define SSB_SPROM8_PA0B2 0x10C6
601 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
602 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
603 +#define SSB_SPROM8_PA0B1 0x00C4
604 +#define SSB_SPROM8_PA0B2 0x00C6
605 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
606 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
607 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
608 #define SSB_SPROM8_ITSSI_A_SHIFT 8
609 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
610 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
611 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
612 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
613 #define SSB_SPROM8_MAXP_AL_SHIFT 8
614 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
615 -#define SSB_SPROM8_PA1B1 0x10CE
616 -#define SSB_SPROM8_PA1B2 0x10D0
617 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
618 -#define SSB_SPROM8_PA1LOB1 0x10D4
619 -#define SSB_SPROM8_PA1LOB2 0x10D6
620 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
621 -#define SSB_SPROM8_PA1HIB1 0x10DA
622 -#define SSB_SPROM8_PA1HIB2 0x10DC
623 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
624 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
625 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
626 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
627 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
628 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
629 +#define SSB_SPROM8_PA1B1 0x00CE
630 +#define SSB_SPROM8_PA1B2 0x00D0
631 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
632 +#define SSB_SPROM8_PA1LOB1 0x00D4
633 +#define SSB_SPROM8_PA1LOB2 0x00D6
634 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
635 +#define SSB_SPROM8_PA1HIB1 0x00DA
636 +#define SSB_SPROM8_PA1HIB2 0x00DC
637 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
638 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
639 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
640 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
641 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
642
643 /* Values for SSB_SPROM1_BINF_CCODE */
644 enum {
Personal OpenWRT clone
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