[uml] update README after r18624
[openwrt.git] / target / linux / brcm-2.4 / patches / 012-aec62xx.patch
1 --- a/drivers/ide/pci/aec62xx.c
2 +++ b/drivers/ide/pci/aec62xx.c
3 @@ -3,6 +3,8 @@
4 *
5 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
6 *
7 + * With Broadcom 4780 patches
8 + *
9 */
10
11 #include <linux/module.h>
12 @@ -329,7 +331,11 @@ static int aec62xx_config_drive_xfer_rat
13 ide_hwif_t *hwif = HWIF(drive);
14 struct hd_driveid *id = drive->id;
15
16 +#ifndef CONFIG_BCM947XX
17 if ((id->capability & 1) && drive->autodma) {
18 +#else
19 + if (1) {
20 +#endif
21 /* Consult the list of known "bad" drives */
22 if (hwif->ide_dma_bad_drive(drive))
23 goto fast_ata_pio;
24 @@ -414,10 +420,60 @@ static unsigned int __init init_chipset_
25 {
26 int bus_speed = system_bus_clock();
27
28 +#ifndef CONFIG_BCM947XX
29 if (dev->resource[PCI_ROM_RESOURCE].start) {
30 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
31 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
32 }
33 +#else
34 + if (dev->resource[PCI_ROM_RESOURCE].start) {
35 + pci_write_config_dword(dev, PCI_ROM_ADDRESS,
36 + dev->resource[PCI_ROM_RESOURCE].
37 + start | PCI_ROM_ADDRESS_ENABLE);
38 + } else {
39 + pci_write_config_dword(dev, PCI_ROM_ADDRESS,
40 + dev->resource[PCI_ROM_RESOURCE].
41 + start);
42 + }
43 +
44 + /* Set IDE controller parameters manually - FIXME: replace magic values */
45 + {
46 + byte setting;
47 +
48 + pci_write_config_word(dev, PCI_COMMAND, 0x0007);
49 + //pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A);
50 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13);
51 +
52 + pci_write_config_byte(dev, 0x40, 0x31);
53 + pci_write_config_byte(dev, 0x41, 0x31);
54 + pci_write_config_byte(dev, 0x42, 0x31);
55 + pci_write_config_byte(dev, 0x43, 0x31);
56 + // Set IDE Command Speed
57 + pci_write_config_byte(dev, 0x48, 0x31);
58 +
59 + // Disable WriteSubSysID & PIOROM
60 + pci_read_config_byte(dev, 0x49, &setting);
61 + setting &= 0x07;
62 + pci_write_config_byte(dev, 0x49, setting);
63 +
64 + // Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80
65 + pci_read_config_byte(dev, 0x4A, &setting);
66 + //setting = (setting & 0xFE) | 0xA8;
67 + setting = (setting & 0xFE) | 0xD8;
68 + setting = (setting & 0xF7);
69 + pci_write_config_byte(dev, 0x4A, setting);
70 +
71 + //pci_write_config_byte(dev, 0x4B, 0x20);
72 + pci_write_config_byte(dev, 0x4B, 0x2C);
73 + //pci_write_config_byte(dev, 0x4B, 0x0C);
74 +
75 + // Set PreRead count: 512 byte
76 + pci_write_config_byte(dev, 0x4C, 0);
77 + pci_write_config_word(dev, 0x4D, 0x0002);
78 + pci_write_config_byte(dev, 0x54, 0);
79 + pci_write_config_word(dev, 0x55, 0x0002);
80 + }
81 +#endif
82
83 #if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
84 aec_devs[n_aec_devs++] = dev;
85 @@ -500,6 +556,7 @@ static void __init init_setup_aec62xx (s
86
87 static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
88 {
89 +#ifndef CONFIG_BCM947XX /* Causes OOPS on BCM4780 */
90 unsigned long bar4reg = pci_resource_start(dev, 4);
91
92 if (inb(bar4reg+2) & 0x10) {
93 @@ -512,6 +569,7 @@ static void __init init_setup_aec6x80 (s
94 strcpy(d->name, "AEC6280R");
95 }
96
97 +#endif
98 ide_setup_pci_device(dev, d);
99 }
100
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