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kernel: update bcma and ssb to version master-2011-12-16 from wireless-testing
[openwrt.git] / target / linux / generic / patches-2.6.36 / 941-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -384,6 +385,35 @@ static int ssb_device_uevent(struct devi
21 ssb_dev->id.revision);
22 }
23
24 +#define ssb_config_attr(attrib, field, format_string) \
25 +static ssize_t \
26 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
27 +{ \
28 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
29 +}
30 +
31 +ssb_config_attr(core_num, core_index, "%u\n")
32 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
33 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
34 +ssb_config_attr(revision, id.revision, "%u\n")
35 +ssb_config_attr(irq, irq, "%u\n")
36 +static ssize_t
37 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
38 +{
39 + return sprintf(buf, "%s\n",
40 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
41 +}
42 +
43 +static struct device_attribute ssb_device_attrs[] = {
44 + __ATTR_RO(name),
45 + __ATTR_RO(core_num),
46 + __ATTR_RO(coreid),
47 + __ATTR_RO(vendor),
48 + __ATTR_RO(revision),
49 + __ATTR_RO(irq),
50 + __ATTR_NULL,
51 +};
52 +
53 static struct bus_type ssb_bustype = {
54 .name = "ssb",
55 .match = ssb_bus_match,
56 @@ -393,6 +423,7 @@ static struct bus_type ssb_bustype = {
57 .suspend = ssb_device_suspend,
58 .resume = ssb_device_resume,
59 .uevent = ssb_device_uevent,
60 + .dev_attrs = ssb_device_attrs,
61 };
62
63 static void ssb_buses_lock(void)
64 @@ -528,7 +559,7 @@ error:
65 }
66
67 /* Needs ssb_buses_lock() */
68 -static int ssb_attach_queued_buses(void)
69 +static int __devinit ssb_attach_queued_buses(void)
70 {
71 struct ssb_bus *bus, *n;
72 int err = 0;
73 @@ -739,9 +770,9 @@ out:
74 return err;
75 }
76
77 -static int ssb_bus_register(struct ssb_bus *bus,
78 - ssb_invariants_func_t get_invariants,
79 - unsigned long baseaddr)
80 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
81 + ssb_invariants_func_t get_invariants,
82 + unsigned long baseaddr)
83 {
84 int err;
85
86 @@ -822,8 +853,8 @@ err_disable_xtal:
87 }
88
89 #ifdef CONFIG_SSB_PCIHOST
90 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
91 - struct pci_dev *host_pci)
92 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
93 + struct pci_dev *host_pci)
94 {
95 int err;
96
97 @@ -846,9 +877,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
98 #endif /* CONFIG_SSB_PCIHOST */
99
100 #ifdef CONFIG_SSB_PCMCIAHOST
101 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
102 - struct pcmcia_device *pcmcia_dev,
103 - unsigned long baseaddr)
104 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
105 + struct pcmcia_device *pcmcia_dev,
106 + unsigned long baseaddr)
107 {
108 int err;
109
110 @@ -868,8 +899,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
111 #endif /* CONFIG_SSB_PCMCIAHOST */
112
113 #ifdef CONFIG_SSB_SDIOHOST
114 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
115 - unsigned int quirks)
116 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
117 + struct sdio_func *func,
118 + unsigned int quirks)
119 {
120 int err;
121
122 @@ -889,9 +921,9 @@ int ssb_bus_sdiobus_register(struct ssb_
123 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
124 #endif /* CONFIG_SSB_PCMCIAHOST */
125
126 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
127 - unsigned long baseaddr,
128 - ssb_invariants_func_t get_invariants)
129 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
130 + unsigned long baseaddr,
131 + ssb_invariants_func_t get_invariants)
132 {
133 int err;
134
135 @@ -972,8 +1004,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
136 switch (plltype) {
137 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
138 if (m & SSB_CHIPCO_CLK_T6_MMASK)
139 - return SSB_CHIPCO_CLK_T6_M0;
140 - return SSB_CHIPCO_CLK_T6_M1;
141 + return SSB_CHIPCO_CLK_T6_M1;
142 + return SSB_CHIPCO_CLK_T6_M0;
143 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
144 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
145 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
146 @@ -1088,23 +1120,22 @@ static u32 ssb_tmslow_reject_bitmask(str
147 {
148 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
149
150 - /* The REJECT bit changed position in TMSLOW between
151 - * Backplane revisions. */
152 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
153 switch (rev) {
154 case SSB_IDLOW_SSBREV_22:
155 - return SSB_TMSLOW_REJECT_22;
156 + case SSB_IDLOW_SSBREV_24:
157 + case SSB_IDLOW_SSBREV_26:
158 + return SSB_TMSLOW_REJECT;
159 case SSB_IDLOW_SSBREV_23:
160 return SSB_TMSLOW_REJECT_23;
161 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
162 - case SSB_IDLOW_SSBREV_25: /* same here */
163 - case SSB_IDLOW_SSBREV_26: /* same here */
164 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
165 case SSB_IDLOW_SSBREV_27: /* same here */
166 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
167 + return SSB_TMSLOW_REJECT; /* this is a guess */
168 default:
169 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
170 WARN_ON(1);
171 }
172 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
173 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
174 }
175
176 int ssb_device_is_enabled(struct ssb_device *dev)
177 @@ -1163,10 +1194,10 @@ void ssb_device_enable(struct ssb_device
178 }
179 EXPORT_SYMBOL(ssb_device_enable);
180
181 -/* Wait for a bit in a register to get set or unset.
182 +/* Wait for bitmask in a register to get set or cleared.
183 * timeout is in units of ten-microseconds */
184 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
185 - int timeout, int set)
186 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
187 + int timeout, int set)
188 {
189 int i;
190 u32 val;
191 @@ -1174,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic
192 for (i = 0; i < timeout; i++) {
193 val = ssb_read32(dev, reg);
194 if (set) {
195 - if (val & bitmask)
196 + if ((val & bitmask) == bitmask)
197 return 0;
198 } else {
199 if (!(val & bitmask))
200 @@ -1191,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic
201
202 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
203 {
204 - u32 reject;
205 + u32 reject, val;
206
207 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
208 return;
209
210 reject = ssb_tmslow_reject_bitmask(dev);
211 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
212 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
213 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
214 - ssb_write32(dev, SSB_TMSLOW,
215 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
216 - reject | SSB_TMSLOW_RESET |
217 - core_specific_flags);
218 - ssb_flush_tmslow(dev);
219 +
220 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
221 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
222 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
223 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
224 +
225 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
226 + val = ssb_read32(dev, SSB_IMSTATE);
227 + val |= SSB_IMSTATE_REJECT;
228 + ssb_write32(dev, SSB_IMSTATE, val);
229 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
230 + 0);
231 + }
232 +
233 + ssb_write32(dev, SSB_TMSLOW,
234 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
235 + reject | SSB_TMSLOW_RESET |
236 + core_specific_flags);
237 + ssb_flush_tmslow(dev);
238 +
239 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
240 + val = ssb_read32(dev, SSB_IMSTATE);
241 + val &= ~SSB_IMSTATE_REJECT;
242 + ssb_write32(dev, SSB_IMSTATE, val);
243 + }
244 + }
245
246 ssb_write32(dev, SSB_TMSLOW,
247 reject | SSB_TMSLOW_RESET |
248 @@ -1213,13 +1262,34 @@ void ssb_device_disable(struct ssb_devic
249 }
250 EXPORT_SYMBOL(ssb_device_disable);
251
252 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
253 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
254 +{
255 + u16 chip_id = dev->bus->chip_id;
256 +
257 + if (dev->id.coreid == SSB_DEV_80211) {
258 + return (chip_id == 0x4322 || chip_id == 43221 ||
259 + chip_id == 43231 || chip_id == 43222);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 u32 ssb_dma_translation(struct ssb_device *dev)
266 {
267 switch (dev->bus->bustype) {
268 case SSB_BUSTYPE_SSB:
269 return 0;
270 case SSB_BUSTYPE_PCI:
271 - return SSB_PCI_DMA;
272 + if (pci_is_pcie(dev->bus->host_pci) &&
273 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
274 + return SSB_PCIE_DMA_H32;
275 + } else {
276 + if (ssb_dma_translation_special_bit(dev))
277 + return SSB_PCIE_DMA_H32;
278 + else
279 + return SSB_PCI_DMA;
280 + }
281 default:
282 __ssb_dma_not_implemented(dev);
283 }
284 @@ -1262,20 +1332,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
285
286 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
287 {
288 - struct ssb_chipcommon *cc;
289 int err;
290 enum ssb_clkmode mode;
291
292 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
293 if (err)
294 goto error;
295 - cc = &bus->chipco;
296 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
297 - ssb_chipco_set_clockmode(cc, mode);
298
299 #ifdef CONFIG_SSB_DEBUG
300 bus->powered_up = 1;
301 #endif
302 +
303 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
304 + ssb_chipco_set_clockmode(&bus->chipco, mode);
305 +
306 return 0;
307 error:
308 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
309 @@ -1283,6 +1353,37 @@ error:
310 }
311 EXPORT_SYMBOL(ssb_bus_powerup);
312
313 +static void ssb_broadcast_value(struct ssb_device *dev,
314 + u32 address, u32 data)
315 +{
316 +#ifdef CONFIG_SSB_DRIVER_PCICORE
317 + /* This is used for both, PCI and ChipCommon core, so be careful. */
318 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
319 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
320 +#endif
321 +
322 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
323 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
324 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
325 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
326 +}
327 +
328 +void ssb_commit_settings(struct ssb_bus *bus)
329 +{
330 + struct ssb_device *dev;
331 +
332 +#ifdef CONFIG_SSB_DRIVER_PCICORE
333 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
334 +#else
335 + dev = bus->chipco.dev;
336 +#endif
337 + if (WARN_ON(!dev))
338 + return;
339 + /* This forces an update of the cached registers. */
340 + ssb_broadcast_value(dev, 0xFD8, 0);
341 +}
342 +EXPORT_SYMBOL(ssb_commit_settings);
343 +
344 u32 ssb_admatch_base(u32 adm)
345 {
346 u32 base = 0;
347 --- a/drivers/ssb/pci.c
348 +++ b/drivers/ssb/pci.c
349 @@ -1,7 +1,7 @@
350 /*
351 * Sonics Silicon Backplane PCI-Hostbus related functions.
352 *
353 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
354 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
355 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
356 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
357 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
358 @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
359 out->antenna_gain.ghz5.a3 = gain;
360 }
361
362 +/* Revs 4 5 and 8 have partially shared layout */
363 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
364 +{
365 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
366 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
367 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
368 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
369 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
370 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
371 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
372 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
373 +
374 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
375 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
376 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
377 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
378 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
379 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
380 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
381 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
382 +
383 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
384 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
385 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
386 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
387 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
388 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
389 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
390 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
391 +
392 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
393 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
394 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
395 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
396 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
397 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
398 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
399 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
400 +}
401 +
402 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
403 {
404 int i;
405 @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
406 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
407 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
408 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
409 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
410 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
411 } else {
412 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
413 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
414 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
415 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
416 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
417 }
418 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
419 SSB_SPROM4_ANTAVAIL_A_SHIFT);
420 @@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
421 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
422 sizeof(out->antenna_gain.ghz5));
423
424 + sprom_extract_r458(out, in);
425 +
426 /* TODO - get remaining rev 4 stuff needed */
427 }
428
429 @@ -561,6 +607,31 @@ static void sprom_extract_r8(struct ssb_
430 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
431 sizeof(out->antenna_gain.ghz5));
432
433 + /* Extract FEM info */
434 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
435 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
436 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
437 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
438 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
439 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
440 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
441 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
442 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
443 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
444 +
445 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
446 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
447 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
448 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
449 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
450 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
451 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
452 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
453 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
454 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
455 +
456 + sprom_extract_r458(out, in);
457 +
458 /* TODO - get remaining rev 8 stuff needed */
459 }
460
461 @@ -573,37 +644,34 @@ static int sprom_extract(struct ssb_bus
462 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
463 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
464 memset(out->et1mac, 0xFF, 6);
465 +
466 if ((bus->chip_id & 0xFF00) == 0x4400) {
467 /* Workaround: The BCM44XX chip has a stupid revision
468 * number stored in the SPROM.
469 * Always extract r1. */
470 out->revision = 1;
471 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
472 + }
473 +
474 + switch (out->revision) {
475 + case 1:
476 + case 2:
477 + case 3:
478 sprom_extract_r123(out, in);
479 - } else if (bus->chip_id == 0x4321) {
480 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
481 - out->revision = 4;
482 + break;
483 + case 4:
484 + case 5:
485 sprom_extract_r45(out, in);
486 - } else {
487 - switch (out->revision) {
488 - case 1:
489 - case 2:
490 - case 3:
491 - sprom_extract_r123(out, in);
492 - break;
493 - case 4:
494 - case 5:
495 - sprom_extract_r45(out, in);
496 - break;
497 - case 8:
498 - sprom_extract_r8(out, in);
499 - break;
500 - default:
501 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
502 - " revision %d detected. Will extract"
503 - " v1\n", out->revision);
504 - out->revision = 1;
505 - sprom_extract_r123(out, in);
506 - }
507 + break;
508 + case 8:
509 + sprom_extract_r8(out, in);
510 + break;
511 + default:
512 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
513 + " revision %d detected. Will extract"
514 + " v1\n", out->revision);
515 + out->revision = 1;
516 + sprom_extract_r123(out, in);
517 }
518
519 if (out->boardflags_lo == 0xFFFF)
520 @@ -617,15 +685,14 @@ static int sprom_extract(struct ssb_bus
521 static int ssb_pci_sprom_get(struct ssb_bus *bus,
522 struct ssb_sprom *sprom)
523 {
524 - const struct ssb_sprom *fallback;
525 - int err = -ENOMEM;
526 + int err;
527 u16 *buf;
528
529 if (!ssb_is_sprom_available(bus)) {
530 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
531 return -ENODEV;
532 }
533 - if (bus->chipco.dev) { /* can be unavailible! */
534 + if (bus->chipco.dev) { /* can be unavailable! */
535 /*
536 * get SPROM offset: SSB_SPROM_BASE1 except for
537 * chipcommon rev >= 31 or chip ID is 0x4312 and
538 @@ -645,7 +712,7 @@ static int ssb_pci_sprom_get(struct ssb_
539
540 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
541 if (!buf)
542 - goto out;
543 + return -ENOMEM;
544 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
545 sprom_do_read(bus, buf);
546 err = sprom_check_crc(buf, bus->sprom_size);
547 @@ -655,17 +722,24 @@ static int ssb_pci_sprom_get(struct ssb_
548 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
549 GFP_KERNEL);
550 if (!buf)
551 - goto out;
552 + return -ENOMEM;
553 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
554 sprom_do_read(bus, buf);
555 err = sprom_check_crc(buf, bus->sprom_size);
556 if (err) {
557 /* All CRC attempts failed.
558 * Maybe there is no SPROM on the device?
559 - * If we have a fallback, use that. */
560 - fallback = ssb_get_fallback_sprom();
561 - if (fallback) {
562 - memcpy(sprom, fallback, sizeof(*sprom));
563 + * Now we ask the arch code if there is some sprom
564 + * available for this device in some other storage */
565 + err = ssb_fill_sprom_with_fallback(bus, sprom);
566 + if (err) {
567 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
568 + " fallback SPROM failed (err %d)\n",
569 + err);
570 + } else {
571 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
572 + " revision %d provided by"
573 + " platform.\n", sprom->revision);
574 err = 0;
575 goto out_free;
576 }
577 @@ -677,19 +751,15 @@ static int ssb_pci_sprom_get(struct ssb_
578
579 out_free:
580 kfree(buf);
581 -out:
582 return err;
583 }
584
585 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
586 struct ssb_boardinfo *bi)
587 {
588 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
589 - &bi->vendor);
590 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
591 - &bi->type);
592 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
593 - &bi->rev);
594 + bi->vendor = bus->host_pci->subsystem_vendor;
595 + bi->type = bus->host_pci->subsystem_device;
596 + bi->rev = bus->host_pci->revision;
597 }
598
599 int ssb_pci_get_invariants(struct ssb_bus *bus,
600 --- a/drivers/ssb/pcihost_wrapper.c
601 +++ b/drivers/ssb/pcihost_wrapper.c
602 @@ -6,7 +6,7 @@
603 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
604 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
605 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
606 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
607 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
608 *
609 * Licensed under the GNU/GPL. See COPYING for details.
610 */
611 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
612 # define ssb_pcihost_resume NULL
613 #endif /* CONFIG_PM */
614
615 -static int ssb_pcihost_probe(struct pci_dev *dev,
616 - const struct pci_device_id *id)
617 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
618 + const struct pci_device_id *id)
619 {
620 struct ssb_bus *ssb;
621 int err = -ENOMEM;
622 const char *name;
623 + u32 val;
624
625 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
626 if (!ssb)
627 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
628 goto err_pci_disable;
629 pci_set_master(dev);
630
631 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
632 + * PCI Tx retries from interfering with C3 CPU state */
633 + pci_read_config_dword(dev, 0x40, &val);
634 + if ((val & 0x0000ff00) != 0)
635 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
636 +
637 err = ssb_bus_pcibus_register(ssb, dev);
638 if (err)
639 goto err_pci_release_regions;
640 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
641 pci_set_drvdata(dev, NULL);
642 }
643
644 -int ssb_pcihost_register(struct pci_driver *driver)
645 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
646 {
647 driver->probe = ssb_pcihost_probe;
648 driver->remove = ssb_pcihost_remove;
649 --- a/drivers/ssb/scan.c
650 +++ b/drivers/ssb/scan.c
651 @@ -2,7 +2,7 @@
652 * Sonics Silicon Backplane
653 * Bus scanning
654 *
655 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
656 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
657 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
658 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
659 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
660 @@ -259,7 +259,10 @@ static int we_support_multiple_80211_cor
661 #ifdef CONFIG_SSB_PCIHOST
662 if (bus->bustype == SSB_BUSTYPE_PCI) {
663 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
664 - bus->host_pci->device == 0x4324)
665 + ((bus->host_pci->device == 0x4313) ||
666 + (bus->host_pci->device == 0x431A) ||
667 + (bus->host_pci->device == 0x4321) ||
668 + (bus->host_pci->device == 0x4324)))
669 return 1;
670 }
671 #endif /* CONFIG_SSB_PCIHOST */
672 @@ -308,8 +311,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
673 } else {
674 if (bus->bustype == SSB_BUSTYPE_PCI) {
675 bus->chip_id = pcidev_to_chipid(bus->host_pci);
676 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
677 - &bus->chip_rev);
678 + bus->chip_rev = bus->host_pci->revision;
679 bus->chip_package = 0;
680 } else {
681 bus->chip_id = 0x4710;
682 @@ -406,10 +408,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
683 /* Ignore PCI cores on PCI-E cards.
684 * Ignore PCI-E cores on PCI cards. */
685 if (dev->id.coreid == SSB_DEV_PCI) {
686 - if (bus->host_pci->is_pcie)
687 + if (pci_is_pcie(bus->host_pci))
688 continue;
689 } else {
690 - if (!bus->host_pci->is_pcie)
691 + if (!pci_is_pcie(bus->host_pci))
692 continue;
693 }
694 }
695 @@ -421,6 +423,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
696 bus->pcicore.dev = dev;
697 #endif /* CONFIG_SSB_DRIVER_PCICORE */
698 break;
699 + case SSB_DEV_ETHERNET:
700 + if (bus->bustype == SSB_BUSTYPE_PCI) {
701 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
702 + (bus->host_pci->device & 0xFF00) == 0x4300) {
703 + /* This is a dangling ethernet core on a
704 + * wireless device. Ignore it. */
705 + continue;
706 + }
707 + }
708 + break;
709 default:
710 break;
711 }
712 --- a/include/linux/ssb/ssb.h
713 +++ b/include/linux/ssb/ssb.h
714 @@ -25,8 +25,10 @@ struct ssb_sprom {
715 u8 et1phyaddr; /* MII address for enet1 */
716 u8 et0mdcport; /* MDIO for enet0 */
717 u8 et1mdcport; /* MDIO for enet1 */
718 - u8 board_rev; /* Board revision number from SPROM. */
719 + u16 board_rev; /* Board revision number from SPROM. */
720 u8 country_code; /* Country Code */
721 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
722 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
723 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
724 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
725 u16 pa0b0;
726 @@ -55,6 +57,10 @@ struct ssb_sprom {
727 u8 tri5gl; /* 5.2GHz TX isolation */
728 u8 tri5g; /* 5.3GHz TX isolation */
729 u8 tri5gh; /* 5.8GHz TX isolation */
730 + u8 txpid2g[4]; /* 2GHz TX power index */
731 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
732 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
733 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
734 u8 rxpo2g; /* 2GHz RX power offset */
735 u8 rxpo5g; /* 5GHz RX power offset */
736 u8 rssisav2g; /* 2GHz RSSI params */
737 @@ -88,6 +94,15 @@ struct ssb_sprom {
738 } ghz5; /* 5GHz band */
739 } antenna_gain;
740
741 + struct {
742 + struct {
743 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
744 + } ghz2;
745 + struct {
746 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
747 + } ghz5;
748 + } fem;
749 +
750 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
751 };
752
753 @@ -95,7 +110,7 @@ struct ssb_sprom {
754 struct ssb_boardinfo {
755 u16 vendor;
756 u16 type;
757 - u16 rev;
758 + u8 rev;
759 };
760
761
762 @@ -225,10 +240,9 @@ struct ssb_driver {
763 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
764
765 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
766 -static inline int ssb_driver_register(struct ssb_driver *drv)
767 -{
768 - return __ssb_driver_register(drv, THIS_MODULE);
769 -}
770 +#define ssb_driver_register(drv) \
771 + __ssb_driver_register(drv, THIS_MODULE)
772 +
773 extern void ssb_driver_unregister(struct ssb_driver *drv);
774
775
776 @@ -304,7 +318,7 @@ struct ssb_bus {
777
778 /* ID information about the Chip. */
779 u16 chip_id;
780 - u16 chip_rev;
781 + u8 chip_rev;
782 u16 sprom_offset;
783 u16 sprom_size; /* number of words in sprom */
784 u8 chip_package;
785 @@ -400,7 +414,9 @@ extern bool ssb_is_sprom_available(struc
786
787 /* Set a fallback SPROM.
788 * See kdoc at the function definition for complete documentation. */
789 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
790 +extern int ssb_arch_register_fallback_sprom(
791 + int (*sprom_callback)(struct ssb_bus *bus,
792 + struct ssb_sprom *out));
793
794 /* Suspend a SSB bus.
795 * Call this from the parent bus suspend routine. */
796 @@ -514,6 +530,7 @@ extern int ssb_bus_may_powerdown(struct
797 * Otherwise static always-on powercontrol will be used. */
798 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
799
800 +extern void ssb_commit_settings(struct ssb_bus *bus);
801
802 /* Various helper functions */
803 extern u32 ssb_admatch_base(u32 adm);
804 --- a/include/linux/ssb/ssb_driver_gige.h
805 +++ b/include/linux/ssb/ssb_driver_gige.h
806 @@ -96,16 +96,21 @@ static inline bool ssb_gige_must_flush_p
807 return 0;
808 }
809
810 -extern char * nvram_get(const char *name);
811 +#ifdef CONFIG_BCM47XX
812 +#include <asm/mach-bcm47xx/nvram.h>
813 /* Get the device MAC address */
814 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
815 {
816 -#ifdef CONFIG_BCM47XX
817 - char *res = nvram_get("et0macaddr");
818 - if (res)
819 - memcpy(macaddr, res, 6);
820 -#endif
821 + char buf[20];
822 + if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
823 + return;
824 + nvram_parse_macaddr(buf, macaddr);
825 }
826 +#else
827 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
828 +{
829 +}
830 +#endif
831
832 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
833 struct pci_dev *pdev);
834 --- a/include/linux/ssb/ssb_regs.h
835 +++ b/include/linux/ssb/ssb_regs.h
836 @@ -85,6 +85,8 @@
837 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
838 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
839 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
840 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
841 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
842 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
843 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
844 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
845 @@ -95,7 +97,7 @@
846 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
847 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
848 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
849 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
850 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
851 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
852 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
853 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
854 @@ -267,6 +269,8 @@
855 /* SPROM Revision 4 */
856 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
857 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
858 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
859 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
860 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
861 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
862 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
863 @@ -298,6 +302,46 @@
864 #define SSB_SPROM4_AGAIN2_SHIFT 0
865 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
866 #define SSB_SPROM4_AGAIN3_SHIFT 8
867 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
868 +#define SSB_SPROM4_TXPID2G0 0x00FF
869 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
870 +#define SSB_SPROM4_TXPID2G1 0xFF00
871 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
872 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
873 +#define SSB_SPROM4_TXPID2G2 0x00FF
874 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
875 +#define SSB_SPROM4_TXPID2G3 0xFF00
876 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
877 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
878 +#define SSB_SPROM4_TXPID5G0 0x00FF
879 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
880 +#define SSB_SPROM4_TXPID5G1 0xFF00
881 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
882 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
883 +#define SSB_SPROM4_TXPID5G2 0x00FF
884 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
885 +#define SSB_SPROM4_TXPID5G3 0xFF00
886 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
887 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
888 +#define SSB_SPROM4_TXPID5GL0 0x00FF
889 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
890 +#define SSB_SPROM4_TXPID5GL1 0xFF00
891 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
892 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
893 +#define SSB_SPROM4_TXPID5GL2 0x00FF
894 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
895 +#define SSB_SPROM4_TXPID5GL3 0xFF00
896 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
897 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
898 +#define SSB_SPROM4_TXPID5GH0 0x00FF
899 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
900 +#define SSB_SPROM4_TXPID5GH1 0xFF00
901 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
902 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
903 +#define SSB_SPROM4_TXPID5GH2 0x00FF
904 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
905 +#define SSB_SPROM4_TXPID5GH3 0xFF00
906 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
907 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
908 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
909 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
910 @@ -317,6 +361,8 @@
911 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
912 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
913 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
914 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
915 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
916 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
917 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
918 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
919 @@ -386,6 +432,23 @@
920 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
921 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
922 #define SSB_SPROM8_RXPO5G_SHIFT 8
923 +#define SSB_SPROM8_FEM2G 0x00AE
924 +#define SSB_SPROM8_FEM5G 0x00B0
925 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
926 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
927 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
928 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
929 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
930 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
931 +#define SSB_SROM8_FEM_TR_ISO 0x0700
932 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
933 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
934 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
935 +#define SSB_SPROM8_THERMAL 0x00B2
936 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
937 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
938 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
939 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
940 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
941 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
942 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
943 @@ -416,6 +479,46 @@
944 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
945 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
946
947 +/* Values for boardflags_lo read from SPROM */
948 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
949 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
950 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
951 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
952 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
953 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
954 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
955 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
956 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
957 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
958 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
959 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
960 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
961 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
962 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
963 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
964 +
965 +/* Values for boardflags_hi read from SPROM */
966 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
967 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
968 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
969 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
970 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
971 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
972 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
973 +
974 +/* Values for boardflags2_lo read from SPROM */
975 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
976 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
977 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
978 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
979 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
980 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
981 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
982 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
983 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
984 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
985 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
986 +
987 /* Values for SSB_SPROM1_BINF_CCODE */
988 enum {
989 SSB_SPROM1CCODE_WORLD = 0,
990 --- a/drivers/ssb/driver_chipcommon.c
991 +++ b/drivers/ssb/driver_chipcommon.c
992 @@ -3,7 +3,7 @@
993 * Broadcom ChipCommon core driver
994 *
995 * Copyright 2005, Broadcom Corporation
996 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
997 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
998 *
999 * Licensed under the GNU/GPL. See COPYING for details.
1000 */
1001 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
1002 if (!ccdev)
1003 return;
1004 bus = ccdev->bus;
1005 +
1006 + /* We support SLOW only on 6..9 */
1007 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
1008 + mode = SSB_CLKMODE_DYNAMIC;
1009 +
1010 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
1011 + return; /* PMU controls clockmode, separated function needed */
1012 + SSB_WARN_ON(ccdev->id.revision >= 20);
1013 +
1014 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1015 if (ccdev->id.revision < 6)
1016 return;
1017 - /* chipcommon cores rev10 are a whole new ball game */
1018 +
1019 + /* ChipCommon cores rev10+ need testing */
1020 if (ccdev->id.revision >= 10)
1021 return;
1022 +
1023 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
1024 return;
1025
1026 switch (mode) {
1027 - case SSB_CLKMODE_SLOW:
1028 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
1029 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1030 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1031 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1032 break;
1033 case SSB_CLKMODE_FAST:
1034 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1035 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1036 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1037 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1038 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1039 + if (ccdev->id.revision < 10) {
1040 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
1041 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1042 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1043 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
1044 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1045 + } else {
1046 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1047 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
1048 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1049 + /* udelay(150); TODO: not available in early init */
1050 + }
1051 break;
1052 case SSB_CLKMODE_DYNAMIC:
1053 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1054 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1055 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1056 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1057 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1058 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1059 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1060 -
1061 - /* for dynamic control, we have to release our xtal_pu "force on" */
1062 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1063 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1064 + if (ccdev->id.revision < 10) {
1065 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
1066 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
1067 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
1068 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1069 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
1070 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
1071 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
1072 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
1073 +
1074 + /* For dynamic control, we have to release our xtal_pu
1075 + * "force on" */
1076 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
1077 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
1078 + } else {
1079 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
1080 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
1081 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
1082 + }
1083 break;
1084 default:
1085 SSB_WARN_ON(1);
1086 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
1087 if (cc->dev->id.revision >= 11)
1088 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1089 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
1090 +
1091 + if (cc->dev->id.revision >= 20) {
1092 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
1093 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
1094 + }
1095 +
1096 ssb_pmu_init(cc);
1097 chipco_powercontrol_init(cc);
1098 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1099 --- a/drivers/ssb/driver_chipcommon_pmu.c
1100 +++ b/drivers/ssb/driver_chipcommon_pmu.c
1101 @@ -2,7 +2,7 @@
1102 * Sonics Silicon Backplane
1103 * Broadcom ChipCommon Power Management Unit driver
1104 *
1105 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
1106 + * Copyright 2009, Michael Buesch <m@bues.ch>
1107 * Copyright 2007, Broadcom Corporation
1108 *
1109 * Licensed under the GNU/GPL. See COPYING for details.
1110 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
1111 u32 min_msk = 0, max_msk = 0;
1112 unsigned int i;
1113 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
1114 - unsigned int updown_tab_size;
1115 + unsigned int updown_tab_size = 0;
1116 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
1117 - unsigned int depend_tab_size;
1118 + unsigned int depend_tab_size = 0;
1119
1120 switch (bus->chip_id) {
1121 case 0x4312:
1122 + min_msk = 0xCBB;
1123 + break;
1124 case 0x4322:
1125 /* We keep the default settings:
1126 * min_msk = 0xCBB
1127 --- a/drivers/ssb/driver_gige.c
1128 +++ b/drivers/ssb/driver_gige.c
1129 @@ -3,7 +3,7 @@
1130 * Broadcom Gigabit Ethernet core driver
1131 *
1132 * Copyright 2008, Broadcom Corporation
1133 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
1134 + * Copyright 2008, Michael Buesch <m@bues.ch>
1135 *
1136 * Licensed under the GNU/GPL. See COPYING for details.
1137 */
1138 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
1139 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
1140 }
1141
1142 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
1143 - int reg, int size, u32 *val)
1144 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
1145 + unsigned int devfn, int reg,
1146 + int size, u32 *val)
1147 {
1148 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1149 unsigned long flags;
1150 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
1151 return PCIBIOS_SUCCESSFUL;
1152 }
1153
1154 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
1155 - int reg, int size, u32 val)
1156 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
1157 + unsigned int devfn, int reg,
1158 + int size, u32 val)
1159 {
1160 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
1161 unsigned long flags;
1162 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
1163 return PCIBIOS_SUCCESSFUL;
1164 }
1165
1166 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
1167 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
1168 + const struct ssb_device_id *id)
1169 {
1170 struct ssb_gige *dev;
1171 u32 base, tmslow, tmshigh;
1172 --- a/drivers/ssb/driver_pcicore.c
1173 +++ b/drivers/ssb/driver_pcicore.c
1174 @@ -3,7 +3,7 @@
1175 * Broadcom PCI-core driver
1176 *
1177 * Copyright 2005, Broadcom Corporation
1178 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1179 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1180 *
1181 * Licensed under the GNU/GPL. See COPYING for details.
1182 */
1183 @@ -15,6 +15,11 @@
1184
1185 #include "ssb_private.h"
1186
1187 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
1188 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
1189 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
1190 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1191 + u8 address, u16 data);
1192
1193 static inline
1194 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
1195 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
1196 return ssb_mips_irq(extpci_core->dev) + 2;
1197 }
1198
1199 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1200 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1201 {
1202 u32 val;
1203
1204 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
1205 register_pci_controller(&ssb_pcicore_controller);
1206 }
1207
1208 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1209 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1210 {
1211 struct ssb_bus *bus = pc->dev->bus;
1212 u16 chipid_top;
1213 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
1214 }
1215 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
1216
1217 +/**************************************************
1218 + * Workarounds.
1219 + **************************************************/
1220 +
1221 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
1222 +{
1223 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
1224 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
1225 + tmp &= ~0xF000;
1226 + tmp |= (pc->dev->core_index << 12);
1227 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
1228 + }
1229 +}
1230 +
1231 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1232 +{
1233 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1234 +}
1235 +
1236 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1237 +{
1238 + const u8 serdes_pll_device = 0x1D;
1239 + const u8 serdes_rx_device = 0x1F;
1240 + u16 tmp;
1241 +
1242 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1243 + ssb_pcicore_polarity_workaround(pc));
1244 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1245 + if (tmp & 0x4000)
1246 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1247 +}
1248 +
1249 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1250 +{
1251 + struct ssb_device *pdev = pc->dev;
1252 + struct ssb_bus *bus = pdev->bus;
1253 + u32 tmp;
1254 +
1255 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1256 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1257 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1258 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1259 +
1260 + if (pdev->id.revision < 5) {
1261 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1262 + tmp &= ~SSB_IMCFGLO_SERTO;
1263 + tmp |= 2;
1264 + tmp &= ~SSB_IMCFGLO_REQTO;
1265 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1266 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1267 + ssb_commit_settings(bus);
1268 + } else if (pdev->id.revision >= 11) {
1269 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1270 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1271 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1272 + }
1273 +}
1274 +
1275 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1276 +{
1277 + u32 tmp;
1278 + u8 rev = pc->dev->id.revision;
1279 +
1280 + if (rev == 0 || rev == 1) {
1281 + /* TLP Workaround register. */
1282 + tmp = ssb_pcie_read(pc, 0x4);
1283 + tmp |= 0x8;
1284 + ssb_pcie_write(pc, 0x4, tmp);
1285 + }
1286 + if (rev == 1) {
1287 + /* DLLP Link Control register. */
1288 + tmp = ssb_pcie_read(pc, 0x100);
1289 + tmp |= 0x40;
1290 + ssb_pcie_write(pc, 0x100, tmp);
1291 + }
1292 +
1293 + if (rev == 0) {
1294 + const u8 serdes_rx_device = 0x1F;
1295 +
1296 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1297 + 2 /* Timer */, 0x8128);
1298 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1299 + 6 /* CDR */, 0x0100);
1300 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1301 + 7 /* CDR BW */, 0x1466);
1302 + } else if (rev == 3 || rev == 4 || rev == 5) {
1303 + /* TODO: DLLP Power Management Threshold */
1304 + ssb_pcicore_serdes_workaround(pc);
1305 + /* TODO: ASPM */
1306 + } else if (rev == 7) {
1307 + /* TODO: No PLL down */
1308 + }
1309 +
1310 + if (rev >= 6) {
1311 + /* Miscellaneous Configuration Fixup */
1312 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1313 + if (!(tmp & 0x8000))
1314 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1315 + tmp | 0x8000);
1316 + }
1317 +}
1318
1319 /**************************************************
1320 * Generic and Clientmode operation code.
1321 **************************************************/
1322
1323 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1324 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1325 {
1326 + struct ssb_device *pdev = pc->dev;
1327 + struct ssb_bus *bus = pdev->bus;
1328 +
1329 + if (bus->bustype == SSB_BUSTYPE_PCI)
1330 + ssb_pcicore_fix_sprom_core_index(pc);
1331 +
1332 /* Disable PCI interrupts. */
1333 - ssb_write32(pc->dev, SSB_INTVEC, 0);
1334 + ssb_write32(pdev, SSB_INTVEC, 0);
1335 +
1336 + /* Additional PCIe always once-executed workarounds */
1337 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1338 + ssb_pcicore_serdes_workaround(pc);
1339 + /* TODO: ASPM */
1340 + /* TODO: Clock Request Update */
1341 + }
1342 }
1343
1344 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1345 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1346 {
1347 struct ssb_device *dev = pc->dev;
1348 - struct ssb_bus *bus;
1349
1350 if (!dev)
1351 return;
1352 - bus = dev->bus;
1353 if (!ssb_device_is_enabled(dev))
1354 ssb_device_enable(dev, 0);
1355
1356 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
1357 pcicore_write32(pc, 0x134, data);
1358 }
1359
1360 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1361 - u8 address, u16 data)
1362 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1363 +{
1364 + const u16 mdio_control = 0x128;
1365 + const u16 mdio_data = 0x12C;
1366 + u32 v;
1367 + int i;
1368 +
1369 + v = (1 << 30); /* Start of Transaction */
1370 + v |= (1 << 28); /* Write Transaction */
1371 + v |= (1 << 17); /* Turnaround */
1372 + v |= (0x1F << 18);
1373 + v |= (phy << 4);
1374 + pcicore_write32(pc, mdio_data, v);
1375 +
1376 + udelay(10);
1377 + for (i = 0; i < 200; i++) {
1378 + v = pcicore_read32(pc, mdio_control);
1379 + if (v & 0x100 /* Trans complete */)
1380 + break;
1381 + msleep(1);
1382 + }
1383 +}
1384 +
1385 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1386 {
1387 const u16 mdio_control = 0x128;
1388 const u16 mdio_data = 0x12C;
1389 + int max_retries = 10;
1390 + u16 ret = 0;
1391 u32 v;
1392 int i;
1393
1394 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1395 v |= 0x2; /* MDIO Clock Divisor */
1396 pcicore_write32(pc, mdio_control, v);
1397
1398 + if (pc->dev->id.revision >= 10) {
1399 + max_retries = 200;
1400 + ssb_pcie_mdio_set_phy(pc, device);
1401 + }
1402 +
1403 v = (1 << 30); /* Start of Transaction */
1404 - v |= (1 << 28); /* Write Transaction */
1405 + v |= (1 << 29); /* Read Transaction */
1406 v |= (1 << 17); /* Turnaround */
1407 - v |= (u32)device << 22;
1408 + if (pc->dev->id.revision < 10)
1409 + v |= (u32)device << 22;
1410 v |= (u32)address << 18;
1411 - v |= data;
1412 pcicore_write32(pc, mdio_data, v);
1413 /* Wait for the device to complete the transaction */
1414 udelay(10);
1415 - for (i = 0; i < 10; i++) {
1416 + for (i = 0; i < max_retries; i++) {
1417 v = pcicore_read32(pc, mdio_control);
1418 - if (v & 0x100 /* Trans complete */)
1419 + if (v & 0x100 /* Trans complete */) {
1420 + udelay(10);
1421 + ret = pcicore_read32(pc, mdio_data);
1422 break;
1423 + }
1424 msleep(1);
1425 }
1426 pcicore_write32(pc, mdio_control, 0);
1427 + return ret;
1428 }
1429
1430 -static void ssb_broadcast_value(struct ssb_device *dev,
1431 - u32 address, u32 data)
1432 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1433 + u8 address, u16 data)
1434 {
1435 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1436 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1437 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1438 + const u16 mdio_control = 0x128;
1439 + const u16 mdio_data = 0x12C;
1440 + int max_retries = 10;
1441 + u32 v;
1442 + int i;
1443
1444 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1445 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1446 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1447 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1448 -}
1449 + v = 0x80; /* Enable Preamble Sequence */
1450 + v |= 0x2; /* MDIO Clock Divisor */
1451 + pcicore_write32(pc, mdio_control, v);
1452
1453 -static void ssb_commit_settings(struct ssb_bus *bus)
1454 -{
1455 - struct ssb_device *dev;
1456 + if (pc->dev->id.revision >= 10) {
1457 + max_retries = 200;
1458 + ssb_pcie_mdio_set_phy(pc, device);
1459 + }
1460
1461 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1462 - if (WARN_ON(!dev))
1463 - return;
1464 - /* This forces an update of the cached registers. */
1465 - ssb_broadcast_value(dev, 0xFD8, 0);
1466 + v = (1 << 30); /* Start of Transaction */
1467 + v |= (1 << 28); /* Write Transaction */
1468 + v |= (1 << 17); /* Turnaround */
1469 + if (pc->dev->id.revision < 10)
1470 + v |= (u32)device << 22;
1471 + v |= (u32)address << 18;
1472 + v |= data;
1473 + pcicore_write32(pc, mdio_data, v);
1474 + /* Wait for the device to complete the transaction */
1475 + udelay(10);
1476 + for (i = 0; i < max_retries; i++) {
1477 + v = pcicore_read32(pc, mdio_control);
1478 + if (v & 0x100 /* Trans complete */)
1479 + break;
1480 + msleep(1);
1481 + }
1482 + pcicore_write32(pc, mdio_control, 0);
1483 }
1484
1485 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1486 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1487 if (pc->setup_done)
1488 goto out;
1489 if (pdev->id.coreid == SSB_DEV_PCI) {
1490 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1491 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1492 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1493 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1494 -
1495 - if (pdev->id.revision < 5) {
1496 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1497 - tmp &= ~SSB_IMCFGLO_SERTO;
1498 - tmp |= 2;
1499 - tmp &= ~SSB_IMCFGLO_REQTO;
1500 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1501 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1502 - ssb_commit_settings(bus);
1503 - } else if (pdev->id.revision >= 11) {
1504 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1505 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1506 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1507 - }
1508 + ssb_pcicore_pci_setup_workarounds(pc);
1509 } else {
1510 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1511 - //TODO: Better make defines for all these magic PCIE values.
1512 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1513 - /* TLP Workaround register. */
1514 - tmp = ssb_pcie_read(pc, 0x4);
1515 - tmp |= 0x8;
1516 - ssb_pcie_write(pc, 0x4, tmp);
1517 - }
1518 - if (pdev->id.revision == 0) {
1519 - const u8 serdes_rx_device = 0x1F;
1520 -
1521 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1522 - 2 /* Timer */, 0x8128);
1523 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1524 - 6 /* CDR */, 0x0100);
1525 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1526 - 7 /* CDR BW */, 0x1466);
1527 - } else if (pdev->id.revision == 1) {
1528 - /* DLLP Link Control register. */
1529 - tmp = ssb_pcie_read(pc, 0x100);
1530 - tmp |= 0x40;
1531 - ssb_pcie_write(pc, 0x100, tmp);
1532 - }
1533 + ssb_pcicore_pcie_setup_workarounds(pc);
1534 }
1535 pc->setup_done = 1;
1536 out:
1537 --- a/drivers/ssb/sprom.c
1538 +++ b/drivers/ssb/sprom.c
1539 @@ -2,7 +2,7 @@
1540 * Sonics Silicon Backplane
1541 * Common SPROM support routines
1542 *
1543 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1544 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1545 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1546 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1547 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1548 @@ -17,7 +17,7 @@
1549 #include <linux/slab.h>
1550
1551
1552 -static const struct ssb_sprom *fallback_sprom;
1553 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1554
1555
1556 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1557 @@ -145,36 +145,43 @@ out:
1558 }
1559
1560 /**
1561 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1562 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1563 + * fallback SPROM if no SPROM is found.
1564 *
1565 - * @sprom: The SPROM data structure to register.
1566 + * @sprom_callback: The callback function.
1567 *
1568 - * With this function the architecture implementation may register a fallback
1569 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1570 - * where no valid SPROM can be found in the shadow registers.
1571 + * With this function the architecture implementation may register a
1572 + * callback handler which fills the SPROM data structure. The fallback is
1573 + * only used for PCI based SSB devices, where no valid SPROM can be found
1574 + * in the shadow registers.
1575 + *
1576 + * This function is useful for weird architectures that have a half-assed
1577 + * SSB device hardwired to their PCI bus.
1578 + *
1579 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1580 + * devices currently don't use this fallback.
1581 + * Architectures must provide the SPROM for native SSB devices anyway, so
1582 + * the fallback also isn't used for native devices.
1583 *
1584 - * This function is useful for weird architectures that have a half-assed SSB device
1585 - * hardwired to their PCI bus.
1586 - *
1587 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1588 - * don't use this fallback.
1589 - * Architectures must provide the SPROM for native SSB devices anyway,
1590 - * so the fallback also isn't used for native devices.
1591 - *
1592 - * This function is available for architecture code, only. So it is not exported.
1593 + * This function is available for architecture code, only. So it is not
1594 + * exported.
1595 */
1596 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1597 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1598 + struct ssb_sprom *out))
1599 {
1600 - if (fallback_sprom)
1601 + if (get_fallback_sprom)
1602 return -EEXIST;
1603 - fallback_sprom = sprom;
1604 + get_fallback_sprom = sprom_callback;
1605
1606 return 0;
1607 }
1608
1609 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1610 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1611 {
1612 - return fallback_sprom;
1613 + if (!get_fallback_sprom)
1614 + return -ENOENT;
1615 +
1616 + return get_fallback_sprom(bus, out);
1617 }
1618
1619 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1620 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1621 /* this routine differs from specs as we do not access SPROM directly
1622 on PCMCIA */
1623 if (bus->bustype == SSB_BUSTYPE_PCI &&
1624 - bus->chipco.dev && /* can be unavailible! */
1625 + bus->chipco.dev && /* can be unavailable! */
1626 bus->chipco.dev->id.revision >= 31)
1627 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1628
1629 --- a/drivers/ssb/ssb_private.h
1630 +++ b/drivers/ssb/ssb_private.h
1631 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1632 const char *buf, size_t count,
1633 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1634 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1635 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1636 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1637 + struct ssb_sprom *out);
1638
1639
1640 /* core.c */
1641 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1642 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1643 @@ -8,7 +8,7 @@
1644 * gpio interface, extbus, and support for serial and parallel flashes.
1645 *
1646 * Copyright 2005, Broadcom Corporation
1647 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1648 + * Copyright 2006, Michael Buesch <m@bues.ch>
1649 *
1650 * Licensed under the GPL version 2. See COPYING for details.
1651 */
1652 @@ -123,6 +123,8 @@
1653 #define SSB_CHIPCO_FLASHDATA 0x0048
1654 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1655 #define SSB_CHIPCO_BCAST_DATA 0x0054
1656 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1657 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1658 #define SSB_CHIPCO_GPIOIN 0x0060
1659 #define SSB_CHIPCO_GPIOOUT 0x0064
1660 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1661 @@ -131,6 +133,9 @@
1662 #define SSB_CHIPCO_GPIOIRQ 0x0074
1663 #define SSB_CHIPCO_WATCHDOG 0x0080
1664 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1665 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1666 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1667 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1668 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1669 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1670 #define SSB_CHIPCO_CLOCK_N 0x0090
1671 @@ -189,8 +194,10 @@
1672 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1673 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1674 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1675 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1676 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1677 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1678 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1679 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1680 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1681 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1682 #define SSB_CHIPCO_UART0_DATA 0x0300
1683 #define SSB_CHIPCO_UART0_IMR 0x0304
1684 --- a/drivers/ssb/b43_pci_bridge.c
1685 +++ b/drivers/ssb/b43_pci_bridge.c
1686 @@ -5,12 +5,13 @@
1687 * because of its small size we include it in the SSB core
1688 * instead of creating a standalone module.
1689 *
1690 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1691 + * Copyright 2007 Michael Buesch <m@bues.ch>
1692 *
1693 * Licensed under the GNU/GPL. See COPYING for details.
1694 */
1695
1696 #include <linux/pci.h>
1697 +#include <linux/module.h>
1698 #include <linux/ssb/ssb.h>
1699
1700 #include "ssb_private.h"
1701 --- a/drivers/ssb/driver_extif.c
1702 +++ b/drivers/ssb/driver_extif.c
1703 @@ -3,7 +3,7 @@
1704 * Broadcom EXTIF core driver
1705 *
1706 * Copyright 2005, Broadcom Corporation
1707 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1708 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1709 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1710 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1711 *
1712 --- a/drivers/ssb/driver_mipscore.c
1713 +++ b/drivers/ssb/driver_mipscore.c
1714 @@ -3,7 +3,7 @@
1715 * Broadcom MIPS core driver
1716 *
1717 * Copyright 2005, Broadcom Corporation
1718 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1719 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1720 *
1721 * Licensed under the GNU/GPL. See COPYING for details.
1722 */
1723 --- a/drivers/ssb/embedded.c
1724 +++ b/drivers/ssb/embedded.c
1725 @@ -3,7 +3,7 @@
1726 * Embedded systems support code
1727 *
1728 * Copyright 2005-2008, Broadcom Corporation
1729 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1730 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1731 *
1732 * Licensed under the GNU/GPL. See COPYING for details.
1733 */
1734 --- a/drivers/ssb/pcmcia.c
1735 +++ b/drivers/ssb/pcmcia.c
1736 @@ -3,7 +3,7 @@
1737 * PCMCIA-Hostbus related functions
1738 *
1739 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1740 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1741 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1742 *
1743 * Licensed under the GNU/GPL. See COPYING for details.
1744 */
1745 --- a/drivers/ssb/sdio.c
1746 +++ b/drivers/ssb/sdio.c
1747 @@ -6,7 +6,7 @@
1748 *
1749 * Based on drivers/ssb/pcmcia.c
1750 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1751 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1752 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1753 *
1754 * Licensed under the GNU/GPL. See COPYING for details.
1755 *
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