cleanup ifxmips pci code
[openwrt.git] / target / linux / ifxmips / files / arch / mips / pci / ops-ifxmips.c
1 #include <linux/types.h>
2 #include <linux/pci.h>
3 #include <linux/kernel.h>
4 #include <linux/init.h>
5 #include <linux/delay.h>
6 #include <linux/mm.h>
7 #include <asm/ifxmips/ifxmips.h>
8 #include <asm/ifxmips/ifxmips_irq.h>
9 #include <asm/addrspace.h>
10 #include <linux/vmalloc.h>
11
12 #define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
13 #define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
14 #define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
15
16 #define PCI_ACCESS_READ 0
17 #define PCI_ACCESS_WRITE 1
18
19 extern u32 ifxmips_pci_mapped_cfg;
20
21 static int
22 ifxmips_pci_config_access(unsigned char access_type,
23 struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
24 {
25 unsigned long cfg_base;
26 unsigned long flags;
27
28 u32 temp;
29
30 /* IFXMips support slot from 0 to 15 */
31 /* dev_fn 0&0x68 (AD29) is ifxmips itself */
32 if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
33 || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
34 return 1;
35
36 local_irq_save(flags);
37
38 cfg_base = ifxmips_pci_mapped_cfg;
39 cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
40 IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
41
42 /* Perform access */
43 if (access_type == PCI_ACCESS_WRITE)
44 {
45 #ifdef CONFIG_SWAP_IO_SPACE
46 ifxmips_w32(swab32(*data), ((u32*)cfg_base));
47 #else
48 ifxmips_w32(*data, ((u32*)cfg_base));
49 #endif
50 } else {
51 *data = ifxmips_r32(((u32*)(cfg_base)));
52 #ifdef CONFIG_SWAP_IO_SPACE
53 *data = swab32(*data);
54 #endif
55 }
56 wmb();
57
58 /* clean possible Master abort */
59 cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
60 temp = ifxmips_r32(((u32*)(cfg_base)));
61 #ifdef CONFIG_SWAP_IO_SPACE
62 temp = swab32 (temp);
63 #endif
64 cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
65 ifxmips_w32(temp, ((u32*)cfg_base));
66
67 local_irq_restore(flags);
68
69 if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
70 return 1;
71
72 return 0;
73 }
74
75 int
76 ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
77 int where, int size, u32 * val)
78 {
79 u32 data = 0;
80
81 if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
82 return PCIBIOS_DEVICE_NOT_FOUND;
83
84 if (size == 1)
85 *val = (data >> ((where & 3) << 3)) & 0xff;
86 else if (size == 2)
87 *val = (data >> ((where & 3) << 3)) & 0xffff;
88 else
89 *val = data;
90
91 return PCIBIOS_SUCCESSFUL;
92 }
93
94 int
95 ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
96 int where, int size, u32 val)
97 {
98 u32 data = 0;
99
100 if (size == 4)
101 {
102 data = val;
103 } else {
104 if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
105 return PCIBIOS_DEVICE_NOT_FOUND;
106
107 if (size == 1)
108 data = (data & ~(0xff << ((where & 3) << 3))) |
109 (val << ((where & 3) << 3));
110 else if (size == 2)
111 data = (data & ~(0xffff << ((where & 3) << 3))) |
112 (val << ((where & 3) << 3));
113 }
114
115 if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
116 return PCIBIOS_DEVICE_NOT_FOUND;
117
118 return PCIBIOS_SUCCESSFUL;
119 }
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