target/linux/ar71xx/files/drivers/mtd/wrt160nl_part.c

   1 /*
   2  * Copyright (C) 2009 Christian Daniel <cd@maintech.de>
   3  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  *
  19  * TRX flash partition table.
  20  * Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/partitions.h>
  31
  32 struct cybertan_header {
  33         char    magic[4];
  34         u8      res1[4];
  35         char    fw_date[3];
  36         char    fw_ver[3];
  37         char    id[4];
  38         char    hw_ver;
  39         char    unused;
  40         u8      flags[2];
  41         u8      res2[10];
  42 };
  43
  44 #define TRX_PARTS       6
  45 #define TRX_MAGIC       0x30524448
  46 #define TRX_MAX_OFFSET  3
  47
  48 struct trx_header {
  49         uint32_t magic;           /* "HDR0" */
  50         uint32_t len;             /* Length of file including header */
  51         uint32_t crc32;           /* 32-bit CRC from flag_version to end of file */
  52         uint32_t flag_version;    /* 0:15 flags, 16:31 version */
  53         uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
  54 };
  55
  56 #define IH_MAGIC        0x27051956      /* Image Magic Number */
  57 #define IH_NMLEN        32              /* Image Name Length */
  58
  59 struct uimage_header {
  60         uint32_t        ih_magic;       /* Image Header Magic Number */
  61         uint32_t        ih_hcrc;        /* Image Header CRC Checksum */
  62         uint32_t        ih_time;        /* Image Creation Timestamp */
  63         uint32_t        ih_size;        /* Image Data Size */
  64         uint32_t        ih_load;        /* Data» Load  Address */
  65         uint32_t        ih_ep;          /* Entry Point Address */
  66         uint32_t        ih_dcrc;        /* Image Data CRC Checksum */
  67         uint8_t         ih_os;          /* Operating System */
  68         uint8_t         ih_arch;        /* CPU architecture */
  69         uint8_t         ih_type;        /* Image Type */
  70         uint8_t         ih_comp;        /* Compression Type */
  71         uint8_t         ih_name[IH_NMLEN];      /* Image Name */
  72 };
  73
  74 struct wrt160nl_header {
  75         struct cybertan_header  cybertan;
  76         struct trx_header       trx;
  77         struct uimage_header    uimage;
  78 } __attribute__ ((packed));
  79
  80 static struct mtd_partition trx_parts[TRX_PARTS];
  81
  82 #define WRT160NL_UBOOT_LEN      0x40000
  83 #define WRT160NL_ART_LEN        0x10000
  84 #define WRT160NL_NVRAM_LEN      0x10000
  85
  86 static int wrt160nl_parse_partitions(struct mtd_info *master,
  87                                      struct mtd_partition **pparts,
  88                                      unsigned long origin)
  89 {
  90         struct wrt160nl_header *header;
  91         struct trx_header *theader;
  92         struct uimage_header *uheader;
  93         size_t retlen;
  94         unsigned int kernel_len;
  95         unsigned int uboot_len;
  96         unsigned int nvram_len;
  97         unsigned int art_len;
  98         int ret;
  99
 100         uboot_len = max_t(unsigned int, master->erasesize, WRT160NL_UBOOT_LEN);
 101         nvram_len = max_t(unsigned int, master->erasesize, WRT160NL_NVRAM_LEN);
 102         art_len = max_t(unsigned int, master->erasesize, WRT160NL_ART_LEN);
 103
 104         header = vmalloc(sizeof(*header));
 105         if (!header) {
 106                 return -ENOMEM;
 107                 goto out;
 108         }
 109
 110         ret = master->read(master, uboot_len, sizeof(*header),
 111                            &retlen, (void *) header);
 112         if (ret)
 113                 goto free_hdr;
 114
 115         if (retlen != sizeof(*header)) {
 116                 ret = -EIO;
 117                 goto free_hdr;
 118         }
 119
 120         if (strncmp(header->cybertan.magic, "NL16", 4) != 0) {
 121                 printk(KERN_NOTICE "%s: no WRT160NL signature found\n",
 122                         master->name);
 123                 goto free_hdr;
 124         }
 125
 126         theader = &header->trx;
 127         if (le32_to_cpu(theader->magic) != TRX_MAGIC) {
 128                 printk(KERN_NOTICE "%s: no TRX header found\n", master->name);
 129                 goto free_hdr;
 130         }
 131
 132         uheader = &header->uimage;
 133         if (uheader->ih_magic != IH_MAGIC) {
 134                 printk(KERN_NOTICE "%s: no uImage found\n", master->name);
 135                 goto free_hdr;
 136         }
 137
 138         kernel_len = le32_to_cpu(theader->offsets[1]) +
 139                 sizeof(struct cybertan_header);
 140
 141         trx_parts[0].name = "u-boot";
 142         trx_parts[0].offset = 0;
 143         trx_parts[0].size = uboot_len;
 144         trx_parts[0].mask_flags = MTD_WRITEABLE;
 145
 146         trx_parts[1].name = "kernel";
 147         trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;
 148         trx_parts[1].size = kernel_len;
 149         trx_parts[1].mask_flags = 0;
 150
 151         trx_parts[2].name = "rootfs";
 152         trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
 153         trx_parts[2].size = master->size - uboot_len - nvram_len - art_len -
 154                 trx_parts[1].size;
 155         trx_parts[2].mask_flags = 0;
 156
 157         trx_parts[3].name = "nvram";
 158         trx_parts[3].offset = master->size - nvram_len - art_len;
 159         trx_parts[3].size = nvram_len;
 160         trx_parts[3].mask_flags = MTD_WRITEABLE;
 161
 162         trx_parts[4].name = "art";
 163         trx_parts[4].offset = master->size - art_len;
 164         trx_parts[4].size = art_len;
 165         trx_parts[4].mask_flags = MTD_WRITEABLE;
 166
 167         trx_parts[5].name = "firmware";
 168         trx_parts[5].offset = uboot_len;
 169         trx_parts[5].size = master->size - uboot_len - nvram_len - art_len;
 170         trx_parts[5].mask_flags = 0;
 171
 172         *pparts = trx_parts;
 173         ret = TRX_PARTS;
 174
 175 free_hdr:
 176         vfree(header);
 177 out:
 178         return ret;
 179 }
 180
 181 static struct mtd_part_parser wrt160nl_parser = {
 182         .owner          = THIS_MODULE,
 183         .parse_fn       = wrt160nl_parse_partitions,
 184         .name           = "wrt160nl",
 185 };
 186
 187 static int __init wrt160nl_parser_init(void)
 188 {
 189         return register_mtd_parser(&wrt160nl_parser);
 190 }
 191
 192 module_init(wrt160nl_parser_init);
 193
 194 MODULE_LICENSE("GPL");
 195 MODULE_AUTHOR("Christian Daniel <cd@maintech.de>");