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lua: Fixed some cross-platform issues for PPC (and probably other architectures)
[openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-q.c
1 /*
2 * ADM5120 HCD (Host Controller Driver) for USB
3 *
4 * Copyright (C) 2007,2008 Gabor Juhos <juhosg at openwrt.org>
5 *
6 * This file was derived from: drivers/usb/host/ohci-q.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15
16 #include <linux/irq.h>
17
18 /*-------------------------------------------------------------------------*/
19
20 /*
21 * URB goes back to driver, and isn't reissued.
22 * It's completely gone from HC data structures.
23 * PRECONDITION: ahcd lock held, irqs blocked.
24 */
25 static void
26 finish_urb(struct admhcd *ahcd, struct urb *urb, int status)
27 __releases(ahcd->lock)
28 __acquires(ahcd->lock)
29 {
30 urb_priv_free(ahcd, urb->hcpriv);
31
32 if (likely(status == -EINPROGRESS))
33 status = 0;
34
35 switch (usb_pipetype(urb->pipe)) {
36 case PIPE_ISOCHRONOUS:
37 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
38 break;
39 case PIPE_INTERRUPT:
40 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
41 break;
42 }
43
44 #ifdef ADMHC_VERBOSE_DEBUG
45 urb_print(ahcd, urb, "RET", usb_pipeout (urb->pipe), status);
46 #endif
47
48 /* urb->complete() can reenter this HCD */
49 usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb);
50 spin_unlock(&ahcd->lock);
51 usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status);
52 spin_lock(&ahcd->lock);
53 }
54
55
56 /*-------------------------------------------------------------------------*
57 * ED handling functions
58 *-------------------------------------------------------------------------*/
59
60 #if 0 /* FIXME */
61 /* search for the right schedule branch to use for a periodic ed.
62 * does some load balancing; returns the branch, or negative errno.
63 */
64 static int balance(struct admhcd *ahcd, int interval, int load)
65 {
66 int i, branch = -ENOSPC;
67
68 /* iso periods can be huge; iso tds specify frame numbers */
69 if (interval > NUM_INTS)
70 interval = NUM_INTS;
71
72 /* search for the least loaded schedule branch of that period
73 * that has enough bandwidth left unreserved.
74 */
75 for (i = 0; i < interval ; i++) {
76 if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
77 int j;
78
79 /* usb 1.1 says 90% of one frame */
80 for (j = i; j < NUM_INTS; j += interval) {
81 if ((ahcd->load [j] + load) > 900)
82 break;
83 }
84 if (j < NUM_INTS)
85 continue;
86 branch = i;
87 }
88 }
89 return branch;
90 }
91 #endif
92
93 /*-------------------------------------------------------------------------*/
94
95 #if 0 /* FIXME */
96 /* both iso and interrupt requests have periods; this routine puts them
97 * into the schedule tree in the apppropriate place. most iso devices use
98 * 1msec periods, but that's not required.
99 */
100 static void periodic_link (struct admhcd *ahcd, struct ed *ed)
101 {
102 unsigned i;
103
104 admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
105 (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
106 ed, ed->branch, ed->load, ed->interval);
107
108 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
109 struct ed **prev = &ahcd->periodic [i];
110 __hc32 *prev_p = &ahcd->hcca->int_table [i];
111 struct ed *here = *prev;
112
113 /* sorting each branch by period (slow before fast)
114 * lets us share the faster parts of the tree.
115 * (plus maybe: put interrupt eds before iso)
116 */
117 while (here && ed != here) {
118 if (ed->interval > here->interval)
119 break;
120 prev = &here->ed_next;
121 prev_p = &here->hwNextED;
122 here = *prev;
123 }
124 if (ed != here) {
125 ed->ed_next = here;
126 if (here)
127 ed->hwNextED = *prev_p;
128 wmb ();
129 *prev = ed;
130 *prev_p = cpu_to_hc32(ahcd, ed->dma);
131 wmb();
132 }
133 ahcd->load [i] += ed->load;
134 }
135 admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
136 }
137 #endif
138
139 /* link an ed into the HC chain */
140
141 static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
142 {
143 struct ed *old_tail;
144
145 if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
146 return -EAGAIN;
147
148 ed->state = ED_OPER;
149
150 old_tail = ahcd->ed_tails[ed->type];
151
152 ed->ed_next = old_tail->ed_next;
153 if (ed->ed_next) {
154 ed->ed_next->ed_prev = ed;
155 ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
156 }
157 ed->ed_prev = old_tail;
158
159 old_tail->ed_next = ed;
160 old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
161
162 ahcd->ed_tails[ed->type] = ed;
163
164 admhc_dma_enable(ahcd);
165
166 return 0;
167 }
168
169 /*-------------------------------------------------------------------------*/
170
171 #if 0 /* FIXME */
172 /* scan the periodic table to find and unlink this ED */
173 static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
174 {
175 int i;
176
177 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
178 struct ed *temp;
179 struct ed **prev = &ahcd->periodic [i];
180 __hc32 *prev_p = &ahcd->hcca->int_table [i];
181
182 while (*prev && (temp = *prev) != ed) {
183 prev_p = &temp->hwNextED;
184 prev = &temp->ed_next;
185 }
186 if (*prev) {
187 *prev_p = ed->hwNextED;
188 *prev = ed->ed_next;
189 }
190 ahcd->load [i] -= ed->load;
191 }
192
193 admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
194 admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
195 (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
196 ed, ed->branch, ed->load, ed->interval);
197 }
198 #endif
199
200 /* unlink an ed from the HC chain.
201 * just the link to the ed is unlinked.
202 * the link from the ed still points to another operational ed or 0
203 * so the HC can eventually finish the processing of the unlinked ed
204 * (assuming it already started that, which needn't be true).
205 *
206 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
207 * it won't. ED_SKIP means the HC will finish its current transaction,
208 * but won't start anything new. The TD queue may still grow; device
209 * drivers don't know about this HCD-internal state.
210 *
211 * When the HC can't see the ED, something changes ED_UNLINK to one of:
212 *
213 * - ED_OPER: when there's any request queued, the ED gets rescheduled
214 * immediately. HC should be working on them.
215 *
216 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
217 * to care about this ED; safe to disable the endpoint.
218 *
219 * When finish_unlinks() runs later, after SOF interrupt, it will often
220 * complete one or more URB unlinks before making that state change.
221 */
222 static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
223 {
224
225 #ifdef ADMHC_VERBOSE_DEBUG
226 admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
227 #endif
228
229 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
230 wmb();
231 ed->state = ED_UNLINK;
232
233 /* remove this ED from the HC list */
234 ed->ed_prev->hwNextED = ed->hwNextED;
235
236 /* and remove it from our list also */
237 ed->ed_prev->ed_next = ed->ed_next;
238
239 if (ed->ed_next)
240 ed->ed_next->ed_prev = ed->ed_prev;
241
242 if (ahcd->ed_tails[ed->type] == ed)
243 ahcd->ed_tails[ed->type] = ed->ed_prev;
244 }
245
246 /*-------------------------------------------------------------------------*/
247
248 static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
249 {
250 struct ed *ed;
251 struct td *td;
252
253 ed = ed_alloc(ahcd, GFP_ATOMIC);
254 if (!ed)
255 goto err;
256
257 /* dummy td; end of td list for this ed */
258 td = td_alloc(ahcd, GFP_ATOMIC);
259 if (!td)
260 goto err_free_ed;
261
262 switch (type) {
263 case PIPE_INTERRUPT:
264 info |= ED_INT;
265 break;
266 case PIPE_ISOCHRONOUS:
267 info |= ED_ISO;
268 break;
269 }
270
271 ed->dummy = td;
272 ed->state = ED_IDLE;
273 ed->type = type;
274
275 ed->hwINFO = cpu_to_hc32(ahcd, info);
276 ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
277 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
278
279 return ed;
280
281 err_free_ed:
282 ed_free(ahcd, ed);
283 err:
284 return NULL;
285 }
286
287 /* get and maybe (re)init an endpoint. init _should_ be done only as part
288 * of enumeration, usb_set_configuration() or usb_set_interface().
289 */
290 static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
291 struct usb_device *udev, unsigned int pipe, int interval)
292 {
293 struct ed *ed;
294 unsigned long flags;
295
296 spin_lock_irqsave(&ahcd->lock, flags);
297
298 ed = ep->hcpriv;
299 if (!ed) {
300 u32 info;
301
302 /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
303 * suceeds ... otherwise we wouldn't need "pipe".
304 */
305 info = usb_pipedevice(pipe);
306 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
307 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
308 if (udev->speed == USB_SPEED_FULL)
309 info |= ED_SPEED_FULL;
310
311 ed = ed_create(ahcd, usb_pipetype(pipe), info);
312 if (ed)
313 ep->hcpriv = ed;
314 }
315
316 spin_unlock_irqrestore(&ahcd->lock, flags);
317
318 return ed;
319 }
320
321 /*-------------------------------------------------------------------------*/
322
323 /* request unlinking of an endpoint from an operational HC.
324 * put the ep on the rm_list
325 * real work is done at the next start frame (SOFI) hardware interrupt
326 * caller guarantees HCD is running, so hardware access is safe,
327 * and that ed->state is ED_OPER
328 */
329 static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
330 {
331
332 #ifdef ADMHC_VERBOSE_DEBUG
333 admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
334 #endif
335
336 ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
337 ed_deschedule(ahcd, ed);
338
339 /* add this ED into the remove list */
340 ed->ed_rm_next = ahcd->ed_rm_list;
341 ahcd->ed_rm_list = ed;
342
343 /* enable SOF interrupt */
344 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
345 admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
346 /* flush those writes */
347 admhc_writel_flush(ahcd);
348
349 /* SOF interrupt might get delayed; record the frame counter value that
350 * indicates when the HC isn't looking at it, so concurrent unlinks
351 * behave. frame_no wraps every 2^16 msec, and changes right before
352 * SOF is triggered.
353 */
354 ed->tick = admhc_frame_no(ahcd) + 1;
355 }
356
357 /*-------------------------------------------------------------------------*
358 * TD handling functions
359 *-------------------------------------------------------------------------*/
360
361 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
362
363 static void
364 td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
365 struct urb *urb, int index)
366 {
367 struct td *td, *td_pt;
368 struct urb_priv *urb_priv = urb->hcpriv;
369 int hash;
370 u32 cbl = 0;
371
372 #if 1
373 if (index == (urb_priv->td_cnt - 1) &&
374 ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
375 cbl |= TD_IE;
376 #else
377 if (index == (urb_priv->td_cnt - 1))
378 cbl |= TD_IE;
379 #endif
380
381 /* use this td as the next dummy */
382 td_pt = urb_priv->td[index];
383
384 /* fill the old dummy TD */
385 td = urb_priv->td[index] = urb_priv->ed->dummy;
386 urb_priv->ed->dummy = td_pt;
387
388 td->ed = urb_priv->ed;
389 td->next_dl_td = NULL;
390 td->index = index;
391 td->urb = urb;
392 td->data_dma = data;
393 if (!len)
394 data = 0;
395
396 if (data)
397 cbl |= (len & TD_BL_MASK);
398
399 info |= TD_OWN;
400
401 /* setup hardware specific fields */
402 td->hwINFO = cpu_to_hc32(ahcd, info);
403 td->hwDBP = cpu_to_hc32(ahcd, data);
404 td->hwCBL = cpu_to_hc32(ahcd, cbl);
405 td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
406
407 /* append to queue */
408 list_add_tail(&td->td_list, &td->ed->td_list);
409
410 /* hash it for later reverse mapping */
411 hash = TD_HASH_FUNC(td->td_dma);
412 td->td_hash = ahcd->td_hash[hash];
413 ahcd->td_hash[hash] = td;
414
415 /* HC might read the TD (or cachelines) right away ... */
416 wmb();
417 td->ed->hwTailP = td->hwNextTD;
418 }
419
420 /*-------------------------------------------------------------------------*/
421
422 /* Prepare all TDs of a transfer, and queue them onto the ED.
423 * Caller guarantees HC is active.
424 * Usually the ED is already on the schedule, so TDs might be
425 * processed as soon as they're queued.
426 */
427 static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
428 {
429 struct urb_priv *urb_priv = urb->hcpriv;
430 dma_addr_t data;
431 int data_len = urb->transfer_buffer_length;
432 int cnt = 0;
433 u32 info = 0;
434 int is_out = usb_pipeout(urb->pipe);
435 u32 toggle = 0;
436
437 /* OHCI handles the bulk/interrupt data toggles itself. We just
438 * use the device toggle bits for resetting, and rely on the fact
439 * that resetting toggle is meaningless if the endpoint is active.
440 */
441
442 if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
443 toggle = TD_T_CARRY;
444 } else {
445 toggle = TD_T_DATA0;
446 usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
447 is_out, 1);
448 }
449
450 urb_priv->td_idx = 0;
451 list_add(&urb_priv->pending, &ahcd->pending);
452
453 if (data_len)
454 data = urb->transfer_dma;
455 else
456 data = 0;
457
458 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
459 * using TD_CC_GET, as well as by seeing them on the done list.
460 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
461 */
462 switch (urb_priv->ed->type) {
463 case PIPE_INTERRUPT:
464 info = is_out
465 ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
466 : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
467
468 /* setup service interval and starting frame number */
469 info |= (urb->start_frame & TD_FN_MASK);
470 info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
471
472 td_fill(ahcd, info, data, data_len, urb, cnt);
473 cnt++;
474
475 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
476 break;
477
478 case PIPE_BULK:
479 info = is_out
480 ? TD_SCC_NOTACCESSED | TD_DP_OUT
481 : TD_SCC_NOTACCESSED | TD_DP_IN;
482
483 /* TDs _could_ transfer up to 8K each */
484 while (data_len > TD_DATALEN_MAX) {
485 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
486 data, TD_DATALEN_MAX, urb, cnt);
487 data += TD_DATALEN_MAX;
488 data_len -= TD_DATALEN_MAX;
489 cnt++;
490 }
491
492 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
493 data_len, urb, cnt);
494 cnt++;
495
496 if ((urb->transfer_flags & URB_ZERO_PACKET)
497 && (cnt < urb_priv->td_cnt)) {
498 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
499 0, 0, urb, cnt);
500 cnt++;
501 }
502 break;
503
504 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
505 * any DATA phase works normally, and the STATUS ack is special.
506 */
507 case PIPE_CONTROL:
508 /* fill a TD for the setup */
509 info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
510 td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
511
512 if (data_len > 0) {
513 /* fill a TD for the data */
514 info = TD_SCC_NOTACCESSED | TD_T_DATA1;
515 info |= is_out ? TD_DP_OUT : TD_DP_IN;
516 /* NOTE: mishandles transfers >8K, some >4K */
517 td_fill(ahcd, info, data, data_len, urb, cnt++);
518 }
519
520 /* fill a TD for the ACK */
521 info = (is_out || data_len == 0)
522 ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
523 : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
524 td_fill(ahcd, info, data, 0, urb, cnt++);
525
526 break;
527
528 /* ISO has no retransmit, so no toggle;
529 * Each TD could handle multiple consecutive frames (interval 1);
530 * we could often reduce the number of TDs here.
531 */
532 case PIPE_ISOCHRONOUS:
533 info = is_out
534 ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
535 : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
536
537 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
538 int frame = urb->start_frame;
539
540 frame += cnt * urb->interval;
541 frame &= TD_FN_MASK;
542 td_fill(ahcd, info | frame,
543 data + urb->iso_frame_desc[cnt].offset,
544 urb->iso_frame_desc[cnt].length, urb, cnt);
545 }
546 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
547 break;
548 }
549
550 if (urb_priv->td_cnt != cnt)
551 admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
552 }
553
554 /*-------------------------------------------------------------------------*
555 * Done List handling functions
556 *-------------------------------------------------------------------------*/
557
558 /* calculate transfer length/status and update the urb */
559 static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
560 {
561 struct urb_priv *urb_priv = urb->hcpriv;
562 u32 info;
563 u32 bl;
564 u32 tdDBP;
565 int type = usb_pipetype(urb->pipe);
566 int cc;
567 int status = -EINPROGRESS;
568
569 info = hc32_to_cpup(ahcd, &td->hwINFO);
570 tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
571 bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
572 cc = TD_CC_GET(info);
573
574 /* ISO ... drivers see per-TD length/status */
575 if (type == PIPE_ISOCHRONOUS) {
576 /* TODO */
577 int dlen = 0;
578
579 /* NOTE: assumes FC in tdINFO == 0, and that
580 * only the first of 0..MAXPSW psws is used.
581 */
582 if (info & TD_CC) /* hc didn't touch? */
583 return status;
584
585 if (usb_pipeout(urb->pipe))
586 dlen = urb->iso_frame_desc[td->index].length;
587 else {
588 /* short reads are always OK for ISO */
589 if (cc == TD_CC_DATAUNDERRUN)
590 cc = TD_CC_NOERROR;
591 dlen = tdDBP - td->data_dma + bl;
592 }
593
594 urb->actual_length += dlen;
595 urb->iso_frame_desc[td->index].actual_length = dlen;
596 urb->iso_frame_desc[td->index].status = cc_to_error[cc];
597
598 if (cc != TD_CC_NOERROR)
599 admhc_vdbg (ahcd,
600 "urb %p iso td %p (%d) len %d cc %d\n",
601 urb, td, 1 + td->index, dlen, cc);
602
603 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
604 * except that "setup" bytes aren't counted and "short" transfers
605 * might not be reported as errors.
606 */
607 } else {
608 /* update packet status if needed (short is normally ok) */
609 if (cc == TD_CC_DATAUNDERRUN
610 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
611 cc = TD_CC_NOERROR;
612
613 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
614 status = cc_to_error[cc];
615
616
617 /* count all non-empty packets except control SETUP packet */
618 if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
619 urb->actual_length += tdDBP - td->data_dma + bl;
620 }
621
622 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
623 admhc_vdbg(ahcd,
624 "urb %p td %p (%d) cc %d, len=%d/%d\n",
625 urb, td, td->index, cc,
626 urb->actual_length,
627 urb->transfer_buffer_length);
628 }
629
630 list_del(&td->td_list);
631 urb_priv->td_idx++;
632
633 return status;
634 }
635
636 /*-------------------------------------------------------------------------*/
637
638 static inline void
639 ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
640 {
641 struct urb *urb = td->urb;
642 struct urb_priv *urb_priv = urb->hcpriv;
643 struct ed *ed = td->ed;
644 struct list_head *tmp = td->td_list.next;
645 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
646
647 admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
648 /* clear ed halt; this is the td that caused it, but keep it inactive
649 * until its urb->complete() has a chance to clean up.
650 */
651 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
652 wmb();
653 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
654
655 /* Get rid of all later tds from this urb. We don't have
656 * to be careful: no errors and nothing was transferred.
657 * Also patch the ed so it looks as if those tds completed normally.
658 */
659 while (tmp != &ed->td_list) {
660 struct td *next;
661
662 next = list_entry(tmp, struct td, td_list);
663 tmp = next->td_list.next;
664
665 if (next->urb != urb)
666 break;
667
668 /* NOTE: if multi-td control DATA segments get supported,
669 * this urb had one of them, this td wasn't the last td
670 * in that segment (TD_R clear), this ed halted because
671 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
672 * then we need to leave the control STATUS packet queued
673 * and clear ED_SKIP.
674 */
675 list_del(&next->td_list);
676 urb_priv->td_cnt++;
677 ed->hwHeadP = next->hwNextTD | toggle;
678 }
679
680 /* help for troubleshooting: report anything that
681 * looks odd ... that doesn't include protocol stalls
682 * (or maybe some other things)
683 */
684 switch (cc) {
685 case TD_CC_DATAUNDERRUN:
686 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
687 break;
688 /* fallthrough */
689 case TD_CC_STALL:
690 if (usb_pipecontrol(urb->pipe))
691 break;
692 /* fallthrough */
693 default:
694 admhc_dbg (ahcd,
695 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
696 urb, urb->dev->devpath,
697 usb_pipeendpoint (urb->pipe),
698 usb_pipein (urb->pipe) ? "in" : "out",
699 hc32_to_cpu(ahcd, td->hwINFO),
700 cc, cc_to_error [cc]);
701 }
702 }
703
704 /*-------------------------------------------------------------------------*/
705
706 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
707 static void
708 finish_unlinks(struct admhcd *ahcd, u16 tick)
709 {
710 struct ed *ed, **last;
711
712 rescan_all:
713 for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
714 struct list_head *entry, *tmp;
715 int completed, modified;
716 __hc32 *prev;
717
718 /* only take off EDs that the HC isn't using, accounting for
719 * frame counter wraps and EDs with partially retired TDs
720 */
721 if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
722 if (tick_before (tick, ed->tick)) {
723 skip_ed:
724 last = &ed->ed_rm_next;
725 continue;
726 }
727 #if 0
728 if (!list_empty(&ed->td_list)) {
729 struct td *td;
730 u32 head;
731
732 td = list_entry(ed->td_list.next, struct td,
733 td_list);
734 head = hc32_to_cpu(ahcd, ed->hwHeadP) &
735 TD_MASK;
736
737 /* INTR_WDH may need to clean up first */
738 if (td->td_dma != head)
739 goto skip_ed;
740 }
741 #endif
742 }
743
744 /* reentrancy: if we drop the schedule lock, someone might
745 * have modified this list. normally it's just prepending
746 * entries (which we'd ignore), but paranoia won't hurt.
747 */
748 *last = ed->ed_rm_next;
749 ed->ed_rm_next = NULL;
750 modified = 0;
751
752 /* unlink urbs as requested, but rescan the list after
753 * we call a completion since it might have unlinked
754 * another (earlier) urb
755 *
756 * When we get here, the HC doesn't see this ed. But it
757 * must not be rescheduled until all completed URBs have
758 * been given back to the driver.
759 */
760 rescan_this:
761 completed = 0;
762 prev = &ed->hwHeadP;
763 list_for_each_safe(entry, tmp, &ed->td_list) {
764 struct td *td;
765 struct urb *urb;
766 struct urb_priv *urb_priv;
767 __hc32 savebits;
768 int status;
769
770 td = list_entry(entry, struct td, td_list);
771 urb = td->urb;
772 urb_priv = td->urb->hcpriv;
773
774 if (!urb->unlinked) {
775 prev = &td->hwNextTD;
776 continue;
777 }
778
779 if ((urb_priv) == NULL)
780 continue;
781
782 /* patch pointer hc uses */
783 savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
784 *prev = td->hwNextTD | savebits;
785
786 /* HC may have partly processed this TD */
787 #ifdef ADMHC_VERBOSE_DEBUG
788 urb_print(ahcd, urb, "PARTIAL", 0);
789 #endif
790 status = td_done(ahcd, urb, td);
791
792 /* if URB is done, clean up */
793 if (urb_priv->td_idx == urb_priv->td_cnt) {
794 modified = completed = 1;
795 finish_urb(ahcd, urb, status);
796 }
797 }
798 if (completed && !list_empty(&ed->td_list))
799 goto rescan_this;
800
801 /* ED's now officially unlinked, hc doesn't see */
802 ed->state = ED_IDLE;
803 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
804 ed->hwNextED = 0;
805 wmb();
806 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
807
808 /* but if there's work queued, reschedule */
809 if (!list_empty(&ed->td_list)) {
810 if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
811 ed_schedule(ahcd, ed);
812 }
813
814 if (modified)
815 goto rescan_all;
816 }
817 }
818
819 /*-------------------------------------------------------------------------*/
820
821 /*
822 * Process normal completions (error or success) and clean the schedules.
823 *
824 * This is the main path for handing urbs back to drivers. The only other
825 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
826 * scanning the (re-reversed) donelist as this does.
827 */
828
829 static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
830 {
831 struct list_head *entry,*tmp;
832 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
833
834 #ifdef ADMHC_VERBOSE_DEBUG
835 admhc_dump_ed(ahcd, "UNHALT", ed, 0);
836 #endif
837 /* clear ed halt; this is the td that caused it, but keep it inactive
838 * until its urb->complete() has a chance to clean up.
839 */
840 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
841 wmb();
842 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
843
844 list_for_each_safe(entry, tmp, &ed->td_list) {
845 struct td *td = list_entry(entry, struct td, td_list);
846 __hc32 info;
847
848 if (td->urb != urb)
849 break;
850
851 info = td->hwINFO;
852 info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
853 td->hwINFO = info;
854
855 ed->hwHeadP = td->hwNextTD | toggle;
856 wmb();
857 }
858
859 }
860
861 static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
862 {
863 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
864
865 ed->hwHeadP = ed->hwTailP | toggle;
866 }
867
868
869 static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
870 {
871 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
872 }
873
874 static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
875 struct td *td)
876 {
877 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
878 (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
879 }
880
881 static void ed_update(struct admhcd *ahcd, struct ed *ed)
882 {
883 struct list_head *entry,*tmp;
884
885 #ifdef ADMHC_VERBOSE_DEBUG
886 admhc_dump_ed(ahcd, "UPDATE", ed, 1);
887 #endif
888
889 list_for_each_safe(entry, tmp, &ed->td_list) {
890 struct td *td = list_entry(entry, struct td, td_list);
891 struct urb *urb = td->urb;
892 struct urb_priv *urb_priv = urb->hcpriv;
893 int status;
894
895 if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
896 break;
897
898 /* update URB's length and status from TD */
899 status = td_done(ahcd, urb, td);
900 if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
901 ed_unhalt(ahcd, ed, urb);
902
903 if (ed->type == PIPE_INTERRUPT)
904 ed_intr_refill(ahcd,ed);
905
906 /* If all this urb's TDs are done, call complete() */
907 if (urb_priv->td_idx == urb_priv->td_cnt)
908 finish_urb(ahcd, urb, status);
909
910 /* clean schedule: unlink EDs that are no longer busy */
911 if (list_empty(&ed->td_list)) {
912 if (ed->state == ED_OPER)
913 start_ed_unlink(ahcd, ed);
914
915 /* ... reenabling halted EDs only after fault cleanup */
916 } else if ((ed->hwINFO & cpu_to_hc32(ahcd,
917 ED_SKIP | ED_DEQUEUE))
918 == cpu_to_hc32(ahcd, ED_SKIP)) {
919 td = list_entry(ed->td_list.next, struct td, td_list);
920 #if 0
921 if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
922 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
923 /* ... hc may need waking-up */
924 switch (ed->type) {
925 case PIPE_CONTROL:
926 admhc_writel (ahcd, OHCI_CLF,
927 &ahcd->regs->cmdstatus);
928 break;
929 case PIPE_BULK:
930 admhc_writel (ahcd, OHCI_BLF,
931 &ahcd->regs->cmdstatus);
932 break;
933 }
934 }
935 #else
936 if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
937 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
938 #endif
939 }
940
941 }
942 }
943
944 /* there are some tds completed; called in_irq(), with HCD locked */
945 static void admhc_td_complete(struct admhcd *ahcd)
946 {
947 struct ed *ed;
948
949 for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
950 if (ed->state != ED_OPER)
951 continue;
952
953 ed_update(ahcd, ed);
954 }
955 }
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