target/linux/orion/patches/000-orion_git_sync.patch

   1 --- a/MAINTAINERS
   2 +++ b/MAINTAINERS
   3 @@ -2690,12 +2690,10 @@
   4  S:     Maintained
   5
   6  MARVELL MV643XX ETHERNET DRIVER
   7 -P:     Dale Farnsworth
   8 -M:     dale@farnsworth.org
   9 -P:     Manish Lachwani
  10 -M:     mlachwani@mvista.com
  11 +P:     Lennert Buytenhek
  12 +M:     buytenh@marvell.com
  13  L:     netdev@vger.kernel.org
  14 -S:     Odd Fixes for 2.4; Maintained for 2.6.
  15 +S:     Supported
  16
  17  MATROX FRAMEBUFFER DRIVER
  18  P:     Petr Vandrovec
  19 --- a/arch/arm/Kconfig
  20 +++ b/arch/arm/Kconfig
  21 @@ -84,6 +84,11 @@
  22         bool
  23         default y
  24
  25 +config HAVE_LATENCYTOP_SUPPORT
  26 +       bool
  27 +       depends on !SMP
  28 +       default y
  29 +
  30  config LOCKDEP_SUPPORT
  31         bool
  32         default y
  33 @@ -347,6 +352,16 @@
  34           If you have any questions or comments about the Linux kernel port
  35           to this board, send e-mail to <sjhill@cotw.com>.
  36
  37 +config ARCH_KIRKWOOD
  38 +       bool "Marvell Kirkwood"
  39 +       select PCI
  40 +       select GENERIC_TIME
  41 +       select GENERIC_CLOCKEVENTS
  42 +       select PLAT_ORION
  43 +       help
  44 +         Support for the following Marvell Kirkwood series SoCs:
  45 +         88F6180, 88F6192 and 88F6281.
  46 +
  47  config ARCH_KS8695
  48         bool "Micrel/Kendin KS8695"
  49         select GENERIC_GPIO
  50 @@ -365,6 +380,24 @@
  51
  52           <http://www.digi.com/products/microprocessors/index.jsp>
  53
  54 +config ARCH_LOKI
  55 +       bool "Marvell Loki (88RC8480)"
  56 +       select GENERIC_TIME
  57 +       select GENERIC_CLOCKEVENTS
  58 +       select PLAT_ORION
  59 +       help
  60 +         Support for the Marvell Loki (88RC8480) SoC.
  61 +
  62 +config ARCH_MV78XX0
  63 +       bool "Marvell MV78xx0"
  64 +       select PCI
  65 +       select GENERIC_TIME
  66 +       select GENERIC_CLOCKEVENTS
  67 +       select PLAT_ORION
  68 +       help
  69 +         Support for the following Marvell MV78xx0 series SoCs:
  70 +         MV781x0, MV782x0.
  71 +
  72  config ARCH_MXC
  73         bool "Freescale MXC/iMX-based"
  74         select ARCH_MTD_XIP
  75 @@ -381,7 +414,8 @@
  76         select PLAT_ORION
  77         help
  78           Support for the following Marvell Orion 5x series SoCs:
  79 -         Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
  80 +         Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
  81 +         Orion-2 (5281).
  82
  83  config ARCH_PNX4008
  84         bool "Philips Nexperia PNX4008 Mobile"
  85 @@ -502,6 +536,10 @@
  86
  87  source "arch/arm/mach-ixp23xx/Kconfig"
  88
  89 +source "arch/arm/mach-loki/Kconfig"
  90 +
  91 +source "arch/arm/mach-mv78xx0/Kconfig"
  92 +
  93  source "arch/arm/mach-pxa/Kconfig"
  94
  95  source "arch/arm/mach-sa1100/Kconfig"
  96 @@ -514,6 +552,8 @@
  97
  98  source "arch/arm/mach-orion5x/Kconfig"
  99
 100 +source "arch/arm/mach-kirkwood/Kconfig"
 101 +
 102  source "arch/arm/plat-s3c24xx/Kconfig"
 103  source "arch/arm/plat-s3c/Kconfig"
 104
 105 --- a/arch/arm/Makefile
 106 +++ b/arch/arm/Makefile
 107 @@ -135,11 +135,14 @@
 108   machine-$(CONFIG_ARCH_NETX)      := netx
 109   machine-$(CONFIG_ARCH_NS9XXX)    := ns9xxx
 110   machine-$(CONFIG_ARCH_DAVINCI)           := davinci
 111 + machine-$(CONFIG_ARCH_KIRKWOOD)   := kirkwood
 112   machine-$(CONFIG_ARCH_KS8695)     := ks8695
 113    incdir-$(CONFIG_ARCH_MXC)       := mxc
 114   machine-$(CONFIG_ARCH_MX3)       := mx3
 115   machine-$(CONFIG_ARCH_ORION5X)           := orion5x
 116   machine-$(CONFIG_ARCH_MSM7X00A)   := msm
 117 + machine-$(CONFIG_ARCH_LOKI)       := loki
 118 + machine-$(CONFIG_ARCH_MV78XX0)    := mv78xx0
 119
 120  ifeq ($(CONFIG_ARCH_EBSA110),y)
 121  # This is what happens if you forget the IOCS16 line.
 122 --- a/arch/arm/boot/compressed/head.S
 123 +++ b/arch/arm/boot/compressed/head.S
 124 @@ -623,8 +623,8 @@
 125                 b       __armv4_mmu_cache_off
 126                 b       __armv4_mmu_cache_flush
 127
 128 -               .word   0x56055310              @ Feroceon
 129 -               .word   0xfffffff0
 130 +               .word   0x56050000              @ Feroceon
 131 +               .word   0xff0f0000
 132                 b       __armv4_mmu_cache_on
 133                 b       __armv4_mmu_cache_off
 134                 b       __armv5tej_mmu_cache_flush
 135 --- /dev/null
 136 +++ b/arch/arm/configs/kirkwood_defconfig
 137 @@ -0,0 +1,1426 @@
 138 +#
 139 +# Automatically generated make config: don't edit
 140 +# Linux kernel version: 2.6.26-rc5
 141 +# Sun Jun 22 15:51:25 2008
 142 +#
 143 +CONFIG_ARM=y
 144 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 145 +CONFIG_GENERIC_GPIO=y
 146 +CONFIG_GENERIC_TIME=y
 147 +CONFIG_GENERIC_CLOCKEVENTS=y
 148 +CONFIG_MMU=y
 149 +# CONFIG_NO_IOPORT is not set
 150 +CONFIG_GENERIC_HARDIRQS=y
 151 +CONFIG_STACKTRACE_SUPPORT=y
 152 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
 153 +CONFIG_LOCKDEP_SUPPORT=y
 154 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 155 +CONFIG_HARDIRQS_SW_RESEND=y
 156 +CONFIG_GENERIC_IRQ_PROBE=y
 157 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
 158 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
 159 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 160 +CONFIG_GENERIC_HWEIGHT=y
 161 +CONFIG_GENERIC_CALIBRATE_DELAY=y
 162 +CONFIG_ARCH_SUPPORTS_AOUT=y
 163 +CONFIG_ZONE_DMA=y
 164 +CONFIG_VECTORS_BASE=0xffff0000
 165 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 166 +
 167 +#
 168 +# General setup
 169 +#
 170 +CONFIG_EXPERIMENTAL=y
 171 +CONFIG_BROKEN_ON_SMP=y
 172 +CONFIG_LOCK_KERNEL=y
 173 +CONFIG_INIT_ENV_ARG_LIMIT=32
 174 +CONFIG_LOCALVERSION=""
 175 +CONFIG_LOCALVERSION_AUTO=y
 176 +CONFIG_SWAP=y
 177 +CONFIG_SYSVIPC=y
 178 +CONFIG_SYSVIPC_SYSCTL=y
 179 +# CONFIG_POSIX_MQUEUE is not set
 180 +# CONFIG_BSD_PROCESS_ACCT is not set
 181 +# CONFIG_TASKSTATS is not set
 182 +# CONFIG_AUDIT is not set
 183 +# CONFIG_IKCONFIG is not set
 184 +CONFIG_LOG_BUF_SHIFT=14
 185 +# CONFIG_CGROUPS is not set
 186 +# CONFIG_GROUP_SCHED is not set
 187 +# CONFIG_SYSFS_DEPRECATED_V2 is not set
 188 +# CONFIG_RELAY is not set
 189 +# CONFIG_NAMESPACES is not set
 190 +# CONFIG_BLK_DEV_INITRD is not set
 191 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 192 +CONFIG_SYSCTL=y
 193 +CONFIG_EMBEDDED=y
 194 +CONFIG_UID16=y
 195 +CONFIG_SYSCTL_SYSCALL=y
 196 +CONFIG_SYSCTL_SYSCALL_CHECK=y
 197 +CONFIG_KALLSYMS=y
 198 +# CONFIG_KALLSYMS_ALL is not set
 199 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
 200 +CONFIG_HOTPLUG=y
 201 +CONFIG_PRINTK=y
 202 +CONFIG_BUG=y
 203 +CONFIG_ELF_CORE=y
 204 +CONFIG_COMPAT_BRK=y
 205 +CONFIG_BASE_FULL=y
 206 +CONFIG_FUTEX=y
 207 +CONFIG_ANON_INODES=y
 208 +CONFIG_EPOLL=y
 209 +CONFIG_SIGNALFD=y
 210 +CONFIG_TIMERFD=y
 211 +CONFIG_EVENTFD=y
 212 +CONFIG_SHMEM=y
 213 +CONFIG_VM_EVENT_COUNTERS=y
 214 +CONFIG_SLAB=y
 215 +# CONFIG_SLUB is not set
 216 +# CONFIG_SLOB is not set
 217 +CONFIG_PROFILING=y
 218 +# CONFIG_MARKERS is not set
 219 +CONFIG_OPROFILE=y
 220 +CONFIG_HAVE_OPROFILE=y
 221 +CONFIG_KPROBES=y
 222 +CONFIG_KRETPROBES=y
 223 +CONFIG_HAVE_KPROBES=y
 224 +CONFIG_HAVE_KRETPROBES=y
 225 +# CONFIG_HAVE_DMA_ATTRS is not set
 226 +CONFIG_PROC_PAGE_MONITOR=y
 227 +CONFIG_SLABINFO=y
 228 +CONFIG_RT_MUTEXES=y
 229 +# CONFIG_TINY_SHMEM is not set
 230 +CONFIG_BASE_SMALL=0
 231 +CONFIG_MODULES=y
 232 +# CONFIG_MODULE_FORCE_LOAD is not set
 233 +CONFIG_MODULE_UNLOAD=y
 234 +# CONFIG_MODULE_FORCE_UNLOAD is not set
 235 +# CONFIG_MODVERSIONS is not set
 236 +# CONFIG_MODULE_SRCVERSION_ALL is not set
 237 +# CONFIG_KMOD is not set
 238 +CONFIG_BLOCK=y
 239 +# CONFIG_LBD is not set
 240 +# CONFIG_BLK_DEV_IO_TRACE is not set
 241 +# CONFIG_LSF is not set
 242 +# CONFIG_BLK_DEV_BSG is not set
 243 +
 244 +#
 245 +# IO Schedulers
 246 +#
 247 +CONFIG_IOSCHED_NOOP=y
 248 +CONFIG_IOSCHED_AS=y
 249 +CONFIG_IOSCHED_DEADLINE=y
 250 +CONFIG_IOSCHED_CFQ=y
 251 +# CONFIG_DEFAULT_AS is not set
 252 +# CONFIG_DEFAULT_DEADLINE is not set
 253 +CONFIG_DEFAULT_CFQ=y
 254 +# CONFIG_DEFAULT_NOOP is not set
 255 +CONFIG_DEFAULT_IOSCHED="cfq"
 256 +CONFIG_CLASSIC_RCU=y
 257 +
 258 +#
 259 +# System Type
 260 +#
 261 +# CONFIG_ARCH_AAEC2000 is not set
 262 +# CONFIG_ARCH_INTEGRATOR is not set
 263 +# CONFIG_ARCH_REALVIEW is not set
 264 +# CONFIG_ARCH_VERSATILE is not set
 265 +# CONFIG_ARCH_AT91 is not set
 266 +# CONFIG_ARCH_CLPS7500 is not set
 267 +# CONFIG_ARCH_CLPS711X is not set
 268 +# CONFIG_ARCH_CO285 is not set
 269 +# CONFIG_ARCH_EBSA110 is not set
 270 +# CONFIG_ARCH_EP93XX is not set
 271 +# CONFIG_ARCH_FOOTBRIDGE is not set
 272 +# CONFIG_ARCH_NETX is not set
 273 +# CONFIG_ARCH_H720X is not set
 274 +# CONFIG_ARCH_IMX is not set
 275 +# CONFIG_ARCH_IOP13XX is not set
 276 +# CONFIG_ARCH_IOP32X is not set
 277 +# CONFIG_ARCH_IOP33X is not set
 278 +# CONFIG_ARCH_IXP23XX is not set
 279 +# CONFIG_ARCH_IXP2000 is not set
 280 +# CONFIG_ARCH_IXP4XX is not set
 281 +# CONFIG_ARCH_L7200 is not set
 282 +CONFIG_ARCH_KIRKWOOD=y
 283 +# CONFIG_ARCH_KS8695 is not set
 284 +# CONFIG_ARCH_NS9XXX is not set
 285 +# CONFIG_ARCH_LOKI is not set
 286 +# CONFIG_ARCH_MV78XX0 is not set
 287 +# CONFIG_ARCH_MXC is not set
 288 +# CONFIG_ARCH_ORION5X is not set
 289 +# CONFIG_ARCH_PNX4008 is not set
 290 +# CONFIG_ARCH_PXA is not set
 291 +# CONFIG_ARCH_RPC is not set
 292 +# CONFIG_ARCH_SA1100 is not set
 293 +# CONFIG_ARCH_S3C2410 is not set
 294 +# CONFIG_ARCH_SHARK is not set
 295 +# CONFIG_ARCH_LH7A40X is not set
 296 +# CONFIG_ARCH_DAVINCI is not set
 297 +# CONFIG_ARCH_OMAP is not set
 298 +# CONFIG_ARCH_MSM7X00A is not set
 299 +
 300 +#
 301 +# Marvell Kirkwood Implementations
 302 +#
 303 +CONFIG_MACH_DB88F6281_BP=y
 304 +CONFIG_MACH_RD88F6192_NAS=y
 305 +CONFIG_MACH_RD88F6281=y
 306 +
 307 +#
 308 +# Boot options
 309 +#
 310 +
 311 +#
 312 +# Power management
 313 +#
 314 +CONFIG_PLAT_ORION=y
 315 +
 316 +#
 317 +# Processor Type
 318 +#
 319 +CONFIG_CPU_32=y
 320 +CONFIG_CPU_FEROCEON=y
 321 +# CONFIG_CPU_FEROCEON_OLD_ID is not set
 322 +CONFIG_CPU_32v5=y
 323 +CONFIG_CPU_ABRT_EV5T=y
 324 +CONFIG_CPU_PABRT_NOIFAR=y
 325 +CONFIG_CPU_CACHE_VIVT=y
 326 +CONFIG_CPU_COPY_FEROCEON=y
 327 +CONFIG_CPU_TLB_FEROCEON=y
 328 +CONFIG_CPU_CP15=y
 329 +CONFIG_CPU_CP15_MMU=y
 330 +
 331 +#
 332 +# Processor Features
 333 +#
 334 +CONFIG_ARM_THUMB=y
 335 +# CONFIG_CPU_ICACHE_DISABLE is not set
 336 +# CONFIG_CPU_DCACHE_DISABLE is not set
 337 +CONFIG_OUTER_CACHE=y
 338 +CONFIG_CACHE_FEROCEON_L2=y
 339 +
 340 +#
 341 +# Bus support
 342 +#
 343 +CONFIG_PCI=y
 344 +CONFIG_PCI_SYSCALL=y
 345 +# CONFIG_ARCH_SUPPORTS_MSI is not set
 346 +CONFIG_PCI_LEGACY=y
 347 +# CONFIG_PCI_DEBUG is not set
 348 +# CONFIG_PCCARD is not set
 349 +
 350 +#
 351 +# Kernel Features
 352 +#
 353 +CONFIG_TICK_ONESHOT=y
 354 +CONFIG_NO_HZ=y
 355 +CONFIG_HIGH_RES_TIMERS=y
 356 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 357 +CONFIG_PREEMPT=y
 358 +CONFIG_HZ=100
 359 +CONFIG_AEABI=y
 360 +# CONFIG_OABI_COMPAT is not set
 361 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 362 +CONFIG_SELECT_MEMORY_MODEL=y
 363 +CONFIG_FLATMEM_MANUAL=y
 364 +# CONFIG_DISCONTIGMEM_MANUAL is not set
 365 +# CONFIG_SPARSEMEM_MANUAL is not set
 366 +CONFIG_FLATMEM=y
 367 +CONFIG_FLAT_NODE_MEM_MAP=y
 368 +# CONFIG_SPARSEMEM_STATIC is not set
 369 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 370 +CONFIG_PAGEFLAGS_EXTENDED=y
 371 +CONFIG_SPLIT_PTLOCK_CPUS=4096
 372 +# CONFIG_RESOURCES_64BIT is not set
 373 +CONFIG_ZONE_DMA_FLAG=1
 374 +CONFIG_BOUNCE=y
 375 +CONFIG_VIRT_TO_BUS=y
 376 +CONFIG_ALIGNMENT_TRAP=y
 377 +
 378 +#
 379 +# Boot options
 380 +#
 381 +CONFIG_ZBOOT_ROM_TEXT=0x0
 382 +CONFIG_ZBOOT_ROM_BSS=0x0
 383 +CONFIG_CMDLINE=""
 384 +# CONFIG_XIP_KERNEL is not set
 385 +# CONFIG_KEXEC is not set
 386 +
 387 +#
 388 +# Floating point emulation
 389 +#
 390 +
 391 +#
 392 +# At least one emulation must be selected
 393 +#
 394 +# CONFIG_VFP is not set
 395 +
 396 +#
 397 +# Userspace binary formats
 398 +#
 399 +CONFIG_BINFMT_ELF=y
 400 +# CONFIG_BINFMT_AOUT is not set
 401 +# CONFIG_BINFMT_MISC is not set
 402 +
 403 +#
 404 +# Power management options
 405 +#
 406 +# CONFIG_PM is not set
 407 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
 408 +
 409 +#
 410 +# Networking
 411 +#
 412 +CONFIG_NET=y
 413 +
 414 +#
 415 +# Networking options
 416 +#
 417 +CONFIG_PACKET=y
 418 +CONFIG_PACKET_MMAP=y
 419 +CONFIG_UNIX=y
 420 +CONFIG_XFRM=y
 421 +# CONFIG_XFRM_USER is not set
 422 +# CONFIG_XFRM_SUB_POLICY is not set
 423 +# CONFIG_XFRM_MIGRATE is not set
 424 +# CONFIG_XFRM_STATISTICS is not set
 425 +# CONFIG_NET_KEY is not set
 426 +CONFIG_INET=y
 427 +CONFIG_IP_MULTICAST=y
 428 +# CONFIG_IP_ADVANCED_ROUTER is not set
 429 +CONFIG_IP_FIB_HASH=y
 430 +CONFIG_IP_PNP=y
 431 +CONFIG_IP_PNP_DHCP=y
 432 +CONFIG_IP_PNP_BOOTP=y
 433 +# CONFIG_IP_PNP_RARP is not set
 434 +# CONFIG_NET_IPIP is not set
 435 +# CONFIG_NET_IPGRE is not set
 436 +# CONFIG_IP_MROUTE is not set
 437 +# CONFIG_ARPD is not set
 438 +# CONFIG_SYN_COOKIES is not set
 439 +# CONFIG_INET_AH is not set
 440 +# CONFIG_INET_ESP is not set
 441 +# CONFIG_INET_IPCOMP is not set
 442 +# CONFIG_INET_XFRM_TUNNEL is not set
 443 +# CONFIG_INET_TUNNEL is not set
 444 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
 445 +CONFIG_INET_XFRM_MODE_TUNNEL=y
 446 +CONFIG_INET_XFRM_MODE_BEET=y
 447 +# CONFIG_INET_LRO is not set
 448 +CONFIG_INET_DIAG=y
 449 +CONFIG_INET_TCP_DIAG=y
 450 +# CONFIG_TCP_CONG_ADVANCED is not set
 451 +CONFIG_TCP_CONG_CUBIC=y
 452 +CONFIG_DEFAULT_TCP_CONG="cubic"
 453 +# CONFIG_TCP_MD5SIG is not set
 454 +# CONFIG_IPV6 is not set
 455 +# CONFIG_NETWORK_SECMARK is not set
 456 +# CONFIG_NETFILTER is not set
 457 +# CONFIG_IP_DCCP is not set
 458 +# CONFIG_IP_SCTP is not set
 459 +# CONFIG_TIPC is not set
 460 +# CONFIG_ATM is not set
 461 +# CONFIG_BRIDGE is not set
 462 +# CONFIG_VLAN_8021Q is not set
 463 +# CONFIG_DECNET is not set
 464 +# CONFIG_LLC2 is not set
 465 +# CONFIG_IPX is not set
 466 +# CONFIG_ATALK is not set
 467 +# CONFIG_X25 is not set
 468 +# CONFIG_LAPB is not set
 469 +# CONFIG_ECONET is not set
 470 +# CONFIG_WAN_ROUTER is not set
 471 +# CONFIG_NET_SCHED is not set
 472 +
 473 +#
 474 +# Network testing
 475 +#
 476 +CONFIG_NET_PKTGEN=m
 477 +# CONFIG_NET_TCPPROBE is not set
 478 +# CONFIG_HAMRADIO is not set
 479 +# CONFIG_CAN is not set
 480 +# CONFIG_IRDA is not set
 481 +# CONFIG_BT is not set
 482 +# CONFIG_AF_RXRPC is not set
 483 +
 484 +#
 485 +# Wireless
 486 +#
 487 +# CONFIG_CFG80211 is not set
 488 +CONFIG_WIRELESS_EXT=y
 489 +# CONFIG_MAC80211 is not set
 490 +# CONFIG_IEEE80211 is not set
 491 +# CONFIG_RFKILL is not set
 492 +# CONFIG_NET_9P is not set
 493 +
 494 +#
 495 +# Device Drivers
 496 +#
 497 +
 498 +#
 499 +# Generic Driver Options
 500 +#
 501 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 502 +CONFIG_STANDALONE=y
 503 +CONFIG_PREVENT_FIRMWARE_BUILD=y
 504 +CONFIG_FW_LOADER=y
 505 +# CONFIG_DEBUG_DRIVER is not set
 506 +# CONFIG_DEBUG_DEVRES is not set
 507 +# CONFIG_SYS_HYPERVISOR is not set
 508 +# CONFIG_CONNECTOR is not set
 509 +CONFIG_MTD=y
 510 +# CONFIG_MTD_DEBUG is not set
 511 +# CONFIG_MTD_CONCAT is not set
 512 +CONFIG_MTD_PARTITIONS=y
 513 +# CONFIG_MTD_REDBOOT_PARTS is not set
 514 +CONFIG_MTD_CMDLINE_PARTS=y
 515 +# CONFIG_MTD_AFS_PARTS is not set
 516 +# CONFIG_MTD_AR7_PARTS is not set
 517 +
 518 +#
 519 +# User Modules And Translation Layers
 520 +#
 521 +CONFIG_MTD_CHAR=y
 522 +CONFIG_MTD_BLKDEVS=y
 523 +CONFIG_MTD_BLOCK=y
 524 +# CONFIG_FTL is not set
 525 +# CONFIG_NFTL is not set
 526 +# CONFIG_INFTL is not set
 527 +# CONFIG_RFD_FTL is not set
 528 +# CONFIG_SSFDC is not set
 529 +# CONFIG_MTD_OOPS is not set
 530 +
 531 +#
 532 +# RAM/ROM/Flash chip drivers
 533 +#
 534 +CONFIG_MTD_CFI=y
 535 +CONFIG_MTD_JEDECPROBE=y
 536 +CONFIG_MTD_GEN_PROBE=y
 537 +CONFIG_MTD_CFI_ADV_OPTIONS=y
 538 +CONFIG_MTD_CFI_NOSWAP=y
 539 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
 540 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
 541 +CONFIG_MTD_CFI_GEOMETRY=y
 542 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
 543 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
 544 +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
 545 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
 546 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
 547 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 548 +CONFIG_MTD_CFI_I1=y
 549 +CONFIG_MTD_CFI_I2=y
 550 +# CONFIG_MTD_CFI_I4 is not set
 551 +# CONFIG_MTD_CFI_I8 is not set
 552 +# CONFIG_MTD_OTP is not set
 553 +CONFIG_MTD_CFI_INTELEXT=y
 554 +# CONFIG_MTD_CFI_AMDSTD is not set
 555 +CONFIG_MTD_CFI_STAA=y
 556 +CONFIG_MTD_CFI_UTIL=y
 557 +# CONFIG_MTD_RAM is not set
 558 +# CONFIG_MTD_ROM is not set
 559 +# CONFIG_MTD_ABSENT is not set
 560 +
 561 +#
 562 +# Mapping drivers for chip access
 563 +#
 564 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
 565 +CONFIG_MTD_PHYSMAP=y
 566 +CONFIG_MTD_PHYSMAP_START=0x0
 567 +CONFIG_MTD_PHYSMAP_LEN=0x0
 568 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 569 +# CONFIG_MTD_ARM_INTEGRATOR is not set
 570 +# CONFIG_MTD_IMPA7 is not set
 571 +# CONFIG_MTD_INTEL_VR_NOR is not set
 572 +# CONFIG_MTD_PLATRAM is not set
 573 +
 574 +#
 575 +# Self-contained MTD device drivers
 576 +#
 577 +# CONFIG_MTD_PMC551 is not set
 578 +# CONFIG_MTD_DATAFLASH is not set
 579 +CONFIG_MTD_M25P80=y
 580 +CONFIG_M25PXX_USE_FAST_READ=y
 581 +# CONFIG_MTD_SLRAM is not set
 582 +# CONFIG_MTD_PHRAM is not set
 583 +# CONFIG_MTD_MTDRAM is not set
 584 +# CONFIG_MTD_BLOCK2MTD is not set
 585 +
 586 +#
 587 +# Disk-On-Chip Device Drivers
 588 +#
 589 +# CONFIG_MTD_DOC2000 is not set
 590 +# CONFIG_MTD_DOC2001 is not set
 591 +# CONFIG_MTD_DOC2001PLUS is not set
 592 +CONFIG_MTD_NAND=y
 593 +CONFIG_MTD_NAND_VERIFY_WRITE=y
 594 +# CONFIG_MTD_NAND_ECC_SMC is not set
 595 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 596 +CONFIG_MTD_NAND_IDS=y
 597 +# CONFIG_MTD_NAND_DISKONCHIP is not set
 598 +# CONFIG_MTD_NAND_CAFE is not set
 599 +# CONFIG_MTD_NAND_NANDSIM is not set
 600 +# CONFIG_MTD_NAND_PLATFORM is not set
 601 +# CONFIG_MTD_ALAUDA is not set
 602 +CONFIG_MTD_NAND_ORION=y
 603 +# CONFIG_MTD_ONENAND is not set
 604 +
 605 +#
 606 +# UBI - Unsorted block images
 607 +#
 608 +# CONFIG_MTD_UBI is not set
 609 +# CONFIG_PARPORT is not set
 610 +CONFIG_BLK_DEV=y
 611 +# CONFIG_BLK_CPQ_DA is not set
 612 +# CONFIG_BLK_CPQ_CISS_DA is not set
 613 +# CONFIG_BLK_DEV_DAC960 is not set
 614 +# CONFIG_BLK_DEV_UMEM is not set
 615 +# CONFIG_BLK_DEV_COW_COMMON is not set
 616 +CONFIG_BLK_DEV_LOOP=y
 617 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 618 +# CONFIG_BLK_DEV_NBD is not set
 619 +# CONFIG_BLK_DEV_SX8 is not set
 620 +# CONFIG_BLK_DEV_UB is not set
 621 +# CONFIG_BLK_DEV_RAM is not set
 622 +# CONFIG_CDROM_PKTCDVD is not set
 623 +# CONFIG_ATA_OVER_ETH is not set
 624 +# CONFIG_MISC_DEVICES is not set
 625 +CONFIG_HAVE_IDE=y
 626 +# CONFIG_IDE is not set
 627 +
 628 +#
 629 +# SCSI device support
 630 +#
 631 +# CONFIG_RAID_ATTRS is not set
 632 +CONFIG_SCSI=y
 633 +CONFIG_SCSI_DMA=y
 634 +# CONFIG_SCSI_TGT is not set
 635 +# CONFIG_SCSI_NETLINK is not set
 636 +# CONFIG_SCSI_PROC_FS is not set
 637 +
 638 +#
 639 +# SCSI support type (disk, tape, CD-ROM)
 640 +#
 641 +CONFIG_BLK_DEV_SD=y
 642 +# CONFIG_CHR_DEV_ST is not set
 643 +# CONFIG_CHR_DEV_OSST is not set
 644 +CONFIG_BLK_DEV_SR=m
 645 +# CONFIG_BLK_DEV_SR_VENDOR is not set
 646 +CONFIG_CHR_DEV_SG=m
 647 +# CONFIG_CHR_DEV_SCH is not set
 648 +
 649 +#
 650 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 651 +#
 652 +# CONFIG_SCSI_MULTI_LUN is not set
 653 +# CONFIG_SCSI_CONSTANTS is not set
 654 +# CONFIG_SCSI_LOGGING is not set
 655 +# CONFIG_SCSI_SCAN_ASYNC is not set
 656 +CONFIG_SCSI_WAIT_SCAN=m
 657 +
 658 +#
 659 +# SCSI Transports
 660 +#
 661 +# CONFIG_SCSI_SPI_ATTRS is not set
 662 +# CONFIG_SCSI_FC_ATTRS is not set
 663 +# CONFIG_SCSI_ISCSI_ATTRS is not set
 664 +# CONFIG_SCSI_SAS_LIBSAS is not set
 665 +# CONFIG_SCSI_SRP_ATTRS is not set
 666 +CONFIG_SCSI_LOWLEVEL=y
 667 +# CONFIG_ISCSI_TCP is not set
 668 +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
 669 +# CONFIG_SCSI_3W_9XXX is not set
 670 +# CONFIG_SCSI_ACARD is not set
 671 +# CONFIG_SCSI_AACRAID is not set
 672 +# CONFIG_SCSI_AIC7XXX is not set
 673 +# CONFIG_SCSI_AIC7XXX_OLD is not set
 674 +# CONFIG_SCSI_AIC79XX is not set
 675 +# CONFIG_SCSI_AIC94XX is not set
 676 +# CONFIG_SCSI_DPT_I2O is not set
 677 +# CONFIG_SCSI_ADVANSYS is not set
 678 +# CONFIG_SCSI_ARCMSR is not set
 679 +# CONFIG_MEGARAID_NEWGEN is not set
 680 +# CONFIG_MEGARAID_LEGACY is not set
 681 +# CONFIG_MEGARAID_SAS is not set
 682 +# CONFIG_SCSI_HPTIOP is not set
 683 +# CONFIG_SCSI_DMX3191D is not set
 684 +# CONFIG_SCSI_FUTURE_DOMAIN is not set
 685 +# CONFIG_SCSI_IPS is not set
 686 +# CONFIG_SCSI_INITIO is not set
 687 +# CONFIG_SCSI_INIA100 is not set
 688 +# CONFIG_SCSI_MVSAS is not set
 689 +# CONFIG_SCSI_STEX is not set
 690 +# CONFIG_SCSI_SYM53C8XX_2 is not set
 691 +# CONFIG_SCSI_IPR is not set
 692 +# CONFIG_SCSI_QLOGIC_1280 is not set
 693 +# CONFIG_SCSI_QLA_FC is not set
 694 +# CONFIG_SCSI_QLA_ISCSI is not set
 695 +# CONFIG_SCSI_LPFC is not set
 696 +# CONFIG_SCSI_DC395x is not set
 697 +# CONFIG_SCSI_DC390T is not set
 698 +# CONFIG_SCSI_NSP32 is not set
 699 +# CONFIG_SCSI_DEBUG is not set
 700 +# CONFIG_SCSI_SRP is not set
 701 +CONFIG_ATA=y
 702 +# CONFIG_ATA_NONSTANDARD is not set
 703 +CONFIG_SATA_PMP=y
 704 +# CONFIG_SATA_AHCI is not set
 705 +# CONFIG_SATA_SIL24 is not set
 706 +CONFIG_ATA_SFF=y
 707 +# CONFIG_SATA_SVW is not set
 708 +# CONFIG_ATA_PIIX is not set
 709 +CONFIG_SATA_MV=y
 710 +# CONFIG_SATA_NV is not set
 711 +# CONFIG_PDC_ADMA is not set
 712 +# CONFIG_SATA_QSTOR is not set
 713 +# CONFIG_SATA_PROMISE is not set
 714 +# CONFIG_SATA_SX4 is not set
 715 +# CONFIG_SATA_SIL is not set
 716 +# CONFIG_SATA_SIS is not set
 717 +# CONFIG_SATA_ULI is not set
 718 +# CONFIG_SATA_VIA is not set
 719 +# CONFIG_SATA_VITESSE is not set
 720 +# CONFIG_SATA_INIC162X is not set
 721 +# CONFIG_PATA_ALI is not set
 722 +# CONFIG_PATA_AMD is not set
 723 +# CONFIG_PATA_ARTOP is not set
 724 +# CONFIG_PATA_ATIIXP is not set
 725 +# CONFIG_PATA_CMD640_PCI is not set
 726 +# CONFIG_PATA_CMD64X is not set
 727 +# CONFIG_PATA_CS5520 is not set
 728 +# CONFIG_PATA_CS5530 is not set
 729 +# CONFIG_PATA_CYPRESS is not set
 730 +# CONFIG_PATA_EFAR is not set
 731 +# CONFIG_ATA_GENERIC is not set
 732 +# CONFIG_PATA_HPT366 is not set
 733 +# CONFIG_PATA_HPT37X is not set
 734 +# CONFIG_PATA_HPT3X2N is not set
 735 +# CONFIG_PATA_HPT3X3 is not set
 736 +# CONFIG_PATA_IT821X is not set
 737 +# CONFIG_PATA_IT8213 is not set
 738 +# CONFIG_PATA_JMICRON is not set
 739 +# CONFIG_PATA_TRIFLEX is not set
 740 +# CONFIG_PATA_MARVELL is not set
 741 +# CONFIG_PATA_MPIIX is not set
 742 +# CONFIG_PATA_OLDPIIX is not set
 743 +# CONFIG_PATA_NETCELL is not set
 744 +# CONFIG_PATA_NINJA32 is not set
 745 +# CONFIG_PATA_NS87410 is not set
 746 +# CONFIG_PATA_NS87415 is not set
 747 +# CONFIG_PATA_OPTI is not set
 748 +# CONFIG_PATA_OPTIDMA is not set
 749 +# CONFIG_PATA_PDC_OLD is not set
 750 +# CONFIG_PATA_RADISYS is not set
 751 +# CONFIG_PATA_RZ1000 is not set
 752 +# CONFIG_PATA_SC1200 is not set
 753 +# CONFIG_PATA_SERVERWORKS is not set
 754 +# CONFIG_PATA_PDC2027X is not set
 755 +# CONFIG_PATA_SIL680 is not set
 756 +# CONFIG_PATA_SIS is not set
 757 +# CONFIG_PATA_VIA is not set
 758 +# CONFIG_PATA_WINBOND is not set
 759 +# CONFIG_PATA_PLATFORM is not set
 760 +# CONFIG_PATA_SCH is not set
 761 +# CONFIG_MD is not set
 762 +# CONFIG_FUSION is not set
 763 +
 764 +#
 765 +# IEEE 1394 (FireWire) support
 766 +#
 767 +# CONFIG_FIREWIRE is not set
 768 +# CONFIG_IEEE1394 is not set
 769 +# CONFIG_I2O is not set
 770 +CONFIG_NETDEVICES=y
 771 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
 772 +# CONFIG_DUMMY is not set
 773 +# CONFIG_BONDING is not set
 774 +# CONFIG_MACVLAN is not set
 775 +# CONFIG_EQUALIZER is not set
 776 +# CONFIG_TUN is not set
 777 +# CONFIG_VETH is not set
 778 +# CONFIG_ARCNET is not set
 779 +# CONFIG_PHYLIB is not set
 780 +CONFIG_NET_ETHERNET=y
 781 +CONFIG_MII=y
 782 +# CONFIG_AX88796 is not set
 783 +# CONFIG_HAPPYMEAL is not set
 784 +# CONFIG_SUNGEM is not set
 785 +# CONFIG_CASSINI is not set
 786 +# CONFIG_NET_VENDOR_3COM is not set
 787 +# CONFIG_SMC91X is not set
 788 +# CONFIG_DM9000 is not set
 789 +# CONFIG_ENC28J60 is not set
 790 +# CONFIG_NET_TULIP is not set
 791 +# CONFIG_HP100 is not set
 792 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
 793 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
 794 +# CONFIG_IBM_NEW_EMAC_TAH is not set
 795 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 796 +CONFIG_NET_PCI=y
 797 +# CONFIG_PCNET32 is not set
 798 +# CONFIG_AMD8111_ETH is not set
 799 +# CONFIG_ADAPTEC_STARFIRE is not set
 800 +# CONFIG_B44 is not set
 801 +# CONFIG_FORCEDETH is not set
 802 +# CONFIG_EEPRO100 is not set
 803 +# CONFIG_E100 is not set
 804 +# CONFIG_FEALNX is not set
 805 +# CONFIG_NATSEMI is not set
 806 +# CONFIG_NE2K_PCI is not set
 807 +# CONFIG_8139CP is not set
 808 +# CONFIG_8139TOO is not set
 809 +# CONFIG_R6040 is not set
 810 +# CONFIG_SIS900 is not set
 811 +# CONFIG_EPIC100 is not set
 812 +# CONFIG_SUNDANCE is not set
 813 +# CONFIG_TLAN is not set
 814 +# CONFIG_VIA_RHINE is not set
 815 +# CONFIG_SC92031 is not set
 816 +CONFIG_NETDEV_1000=y
 817 +# CONFIG_ACENIC is not set
 818 +# CONFIG_DL2K is not set
 819 +CONFIG_E1000=y
 820 +CONFIG_E1000_NAPI=y
 821 +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
 822 +# CONFIG_E1000E is not set
 823 +# CONFIG_E1000E_ENABLED is not set
 824 +# CONFIG_IP1000 is not set
 825 +# CONFIG_IGB is not set
 826 +# CONFIG_NS83820 is not set
 827 +# CONFIG_HAMACHI is not set
 828 +# CONFIG_YELLOWFIN is not set
 829 +# CONFIG_R8169 is not set
 830 +# CONFIG_SIS190 is not set
 831 +# CONFIG_SKGE is not set
 832 +# CONFIG_SKY2 is not set
 833 +# CONFIG_VIA_VELOCITY is not set
 834 +# CONFIG_TIGON3 is not set
 835 +# CONFIG_BNX2 is not set
 836 +CONFIG_MV643XX_ETH=y
 837 +# CONFIG_QLA3XXX is not set
 838 +# CONFIG_ATL1 is not set
 839 +# CONFIG_NETDEV_10000 is not set
 840 +# CONFIG_TR is not set
 841 +
 842 +#
 843 +# Wireless LAN
 844 +#
 845 +# CONFIG_WLAN_PRE80211 is not set
 846 +# CONFIG_WLAN_80211 is not set
 847 +# CONFIG_IWLWIFI_LEDS is not set
 848 +
 849 +#
 850 +# USB Network Adapters
 851 +#
 852 +# CONFIG_USB_CATC is not set
 853 +# CONFIG_USB_KAWETH is not set
 854 +# CONFIG_USB_PEGASUS is not set
 855 +# CONFIG_USB_RTL8150 is not set
 856 +# CONFIG_USB_USBNET is not set
 857 +# CONFIG_WAN is not set
 858 +# CONFIG_FDDI is not set
 859 +# CONFIG_HIPPI is not set
 860 +# CONFIG_PPP is not set
 861 +# CONFIG_SLIP is not set
 862 +# CONFIG_NET_FC is not set
 863 +# CONFIG_NETCONSOLE is not set
 864 +# CONFIG_NETPOLL is not set
 865 +# CONFIG_NET_POLL_CONTROLLER is not set
 866 +# CONFIG_ISDN is not set
 867 +
 868 +#
 869 +# Input device support
 870 +#
 871 +CONFIG_INPUT=y
 872 +# CONFIG_INPUT_FF_MEMLESS is not set
 873 +# CONFIG_INPUT_POLLDEV is not set
 874 +
 875 +#
 876 +# Userland interfaces
 877 +#
 878 +CONFIG_INPUT_MOUSEDEV=y
 879 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
 880 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 881 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 882 +# CONFIG_INPUT_JOYDEV is not set
 883 +# CONFIG_INPUT_EVDEV is not set
 884 +# CONFIG_INPUT_EVBUG is not set
 885 +
 886 +#
 887 +# Input Device Drivers
 888 +#
 889 +# CONFIG_INPUT_KEYBOARD is not set
 890 +# CONFIG_INPUT_MOUSE is not set
 891 +# CONFIG_INPUT_JOYSTICK is not set
 892 +# CONFIG_INPUT_TABLET is not set
 893 +# CONFIG_INPUT_TOUCHSCREEN is not set
 894 +# CONFIG_INPUT_MISC is not set
 895 +
 896 +#
 897 +# Hardware I/O ports
 898 +#
 899 +# CONFIG_SERIO is not set
 900 +# CONFIG_GAMEPORT is not set
 901 +
 902 +#
 903 +# Character devices
 904 +#
 905 +# CONFIG_VT is not set
 906 +# CONFIG_DEVKMEM is not set
 907 +# CONFIG_SERIAL_NONSTANDARD is not set
 908 +# CONFIG_NOZOMI is not set
 909 +
 910 +#
 911 +# Serial drivers
 912 +#
 913 +CONFIG_SERIAL_8250=y
 914 +CONFIG_SERIAL_8250_CONSOLE=y
 915 +# CONFIG_SERIAL_8250_PCI is not set
 916 +CONFIG_SERIAL_8250_NR_UARTS=4
 917 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 918 +# CONFIG_SERIAL_8250_EXTENDED is not set
 919 +
 920 +#
 921 +# Non-8250 serial port support
 922 +#
 923 +CONFIG_SERIAL_CORE=y
 924 +CONFIG_SERIAL_CORE_CONSOLE=y
 925 +# CONFIG_SERIAL_JSM is not set
 926 +CONFIG_UNIX98_PTYS=y
 927 +CONFIG_LEGACY_PTYS=y
 928 +CONFIG_LEGACY_PTY_COUNT=16
 929 +# CONFIG_IPMI_HANDLER is not set
 930 +# CONFIG_HW_RANDOM is not set
 931 +# CONFIG_NVRAM is not set
 932 +# CONFIG_R3964 is not set
 933 +# CONFIG_APPLICOM is not set
 934 +# CONFIG_RAW_DRIVER is not set
 935 +# CONFIG_TCG_TPM is not set
 936 +CONFIG_DEVPORT=y
 937 +CONFIG_I2C=y
 938 +CONFIG_I2C_BOARDINFO=y
 939 +CONFIG_I2C_CHARDEV=y
 940 +
 941 +#
 942 +# I2C Hardware Bus support
 943 +#
 944 +# CONFIG_I2C_ALI1535 is not set
 945 +# CONFIG_I2C_ALI1563 is not set
 946 +# CONFIG_I2C_ALI15X3 is not set
 947 +# CONFIG_I2C_AMD756 is not set
 948 +# CONFIG_I2C_AMD8111 is not set
 949 +# CONFIG_I2C_GPIO is not set
 950 +# CONFIG_I2C_I801 is not set
 951 +# CONFIG_I2C_I810 is not set
 952 +# CONFIG_I2C_PIIX4 is not set
 953 +# CONFIG_I2C_NFORCE2 is not set
 954 +# CONFIG_I2C_OCORES is not set
 955 +# CONFIG_I2C_PARPORT_LIGHT is not set
 956 +# CONFIG_I2C_PROSAVAGE is not set
 957 +# CONFIG_I2C_SAVAGE4 is not set
 958 +# CONFIG_I2C_SIMTEC is not set
 959 +# CONFIG_I2C_SIS5595 is not set
 960 +# CONFIG_I2C_SIS630 is not set
 961 +# CONFIG_I2C_SIS96X is not set
 962 +# CONFIG_I2C_TAOS_EVM is not set
 963 +# CONFIG_I2C_STUB is not set
 964 +# CONFIG_I2C_TINY_USB is not set
 965 +# CONFIG_I2C_VIA is not set
 966 +# CONFIG_I2C_VIAPRO is not set
 967 +# CONFIG_I2C_VOODOO3 is not set
 968 +# CONFIG_I2C_PCA_PLATFORM is not set
 969 +CONFIG_I2C_MV64XXX=y
 970 +
 971 +#
 972 +# Miscellaneous I2C Chip support
 973 +#
 974 +# CONFIG_DS1682 is not set
 975 +# CONFIG_SENSORS_EEPROM is not set
 976 +# CONFIG_SENSORS_PCF8574 is not set
 977 +# CONFIG_PCF8575 is not set
 978 +# CONFIG_SENSORS_PCF8591 is not set
 979 +# CONFIG_SENSORS_MAX6875 is not set
 980 +# CONFIG_SENSORS_TSL2550 is not set
 981 +# CONFIG_I2C_DEBUG_CORE is not set
 982 +# CONFIG_I2C_DEBUG_ALGO is not set
 983 +# CONFIG_I2C_DEBUG_BUS is not set
 984 +# CONFIG_I2C_DEBUG_CHIP is not set
 985 +CONFIG_SPI=y
 986 +# CONFIG_SPI_DEBUG is not set
 987 +CONFIG_SPI_MASTER=y
 988 +
 989 +#
 990 +# SPI Master Controller Drivers
 991 +#
 992 +# CONFIG_SPI_BITBANG is not set
 993 +CONFIG_SPI_ORION=y
 994 +
 995 +#
 996 +# SPI Protocol Masters
 997 +#
 998 +# CONFIG_SPI_AT25 is not set
 999 +# CONFIG_SPI_SPIDEV is not set
1000 +# CONFIG_SPI_TLE62X0 is not set
1001 +# CONFIG_W1 is not set
1002 +# CONFIG_POWER_SUPPLY is not set
1003 +# CONFIG_HWMON is not set
1004 +# CONFIG_WATCHDOG is not set
1005 +
1006 +#
1007 +# Sonics Silicon Backplane
1008 +#
1009 +CONFIG_SSB_POSSIBLE=y
1010 +# CONFIG_SSB is not set
1011 +
1012 +#
1013 +# Multifunction device drivers
1014 +#
1015 +# CONFIG_MFD_SM501 is not set
1016 +# CONFIG_MFD_ASIC3 is not set
1017 +# CONFIG_HTC_PASIC3 is not set
1018 +
1019 +#
1020 +# Multimedia devices
1021 +#
1022 +
1023 +#
1024 +# Multimedia core support
1025 +#
1026 +# CONFIG_VIDEO_DEV is not set
1027 +# CONFIG_DVB_CORE is not set
1028 +# CONFIG_VIDEO_MEDIA is not set
1029 +
1030 +#
1031 +# Multimedia drivers
1032 +#
1033 +# CONFIG_DAB is not set
1034 +
1035 +#
1036 +# Graphics support
1037 +#
1038 +# CONFIG_DRM is not set
1039 +# CONFIG_VGASTATE is not set
1040 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1041 +# CONFIG_FB is not set
1042 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1043 +
1044 +#
1045 +# Display device support
1046 +#
1047 +# CONFIG_DISPLAY_SUPPORT is not set
1048 +
1049 +#
1050 +# Sound
1051 +#
1052 +# CONFIG_SOUND is not set
1053 +CONFIG_HID_SUPPORT=y
1054 +CONFIG_HID=y
1055 +# CONFIG_HID_DEBUG is not set
1056 +# CONFIG_HIDRAW is not set
1057 +
1058 +#
1059 +# USB Input Devices
1060 +#
1061 +CONFIG_USB_HID=y
1062 +# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1063 +# CONFIG_HID_FF is not set
1064 +# CONFIG_USB_HIDDEV is not set
1065 +CONFIG_USB_SUPPORT=y
1066 +CONFIG_USB_ARCH_HAS_HCD=y
1067 +CONFIG_USB_ARCH_HAS_OHCI=y
1068 +CONFIG_USB_ARCH_HAS_EHCI=y
1069 +CONFIG_USB=y
1070 +# CONFIG_USB_DEBUG is not set
1071 +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1072 +
1073 +#
1074 +# Miscellaneous USB options
1075 +#
1076 +CONFIG_USB_DEVICEFS=y
1077 +CONFIG_USB_DEVICE_CLASS=y
1078 +# CONFIG_USB_DYNAMIC_MINORS is not set
1079 +# CONFIG_USB_OTG is not set
1080 +# CONFIG_USB_OTG_WHITELIST is not set
1081 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1082 +
1083 +#
1084 +# USB Host Controller Drivers
1085 +#
1086 +# CONFIG_USB_C67X00_HCD is not set
1087 +CONFIG_USB_EHCI_HCD=y
1088 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
1089 +CONFIG_USB_EHCI_TT_NEWSCHED=y
1090 +# CONFIG_USB_ISP116X_HCD is not set
1091 +# CONFIG_USB_ISP1760_HCD is not set
1092 +# CONFIG_USB_OHCI_HCD is not set
1093 +# CONFIG_USB_UHCI_HCD is not set
1094 +# CONFIG_USB_SL811_HCD is not set
1095 +# CONFIG_USB_R8A66597_HCD is not set
1096 +
1097 +#
1098 +# USB Device Class drivers
1099 +#
1100 +# CONFIG_USB_ACM is not set
1101 +CONFIG_USB_PRINTER=y
1102 +# CONFIG_USB_WDM is not set
1103 +
1104 +#
1105 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1106 +#
1107 +
1108 +#
1109 +# may also be needed; see USB_STORAGE Help for more information
1110 +#
1111 +CONFIG_USB_STORAGE=y
1112 +# CONFIG_USB_STORAGE_DEBUG is not set
1113 +CONFIG_USB_STORAGE_DATAFAB=y
1114 +CONFIG_USB_STORAGE_FREECOM=y
1115 +# CONFIG_USB_STORAGE_ISD200 is not set
1116 +CONFIG_USB_STORAGE_DPCM=y
1117 +# CONFIG_USB_STORAGE_USBAT is not set
1118 +CONFIG_USB_STORAGE_SDDR09=y
1119 +CONFIG_USB_STORAGE_SDDR55=y
1120 +CONFIG_USB_STORAGE_JUMPSHOT=y
1121 +# CONFIG_USB_STORAGE_ALAUDA is not set
1122 +# CONFIG_USB_STORAGE_ONETOUCH is not set
1123 +# CONFIG_USB_STORAGE_KARMA is not set
1124 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1125 +# CONFIG_USB_LIBUSUAL is not set
1126 +
1127 +#
1128 +# USB Imaging devices
1129 +#
1130 +# CONFIG_USB_MDC800 is not set
1131 +# CONFIG_USB_MICROTEK is not set
1132 +# CONFIG_USB_MON is not set
1133 +
1134 +#
1135 +# USB port drivers
1136 +#
1137 +# CONFIG_USB_SERIAL is not set
1138 +
1139 +#
1140 +# USB Miscellaneous drivers
1141 +#
1142 +# CONFIG_USB_EMI62 is not set
1143 +# CONFIG_USB_EMI26 is not set
1144 +# CONFIG_USB_ADUTUX is not set
1145 +# CONFIG_USB_AUERSWALD is not set
1146 +# CONFIG_USB_RIO500 is not set
1147 +# CONFIG_USB_LEGOTOWER is not set
1148 +# CONFIG_USB_LCD is not set
1149 +# CONFIG_USB_BERRY_CHARGE is not set
1150 +# CONFIG_USB_LED is not set
1151 +# CONFIG_USB_CYPRESS_CY7C63 is not set
1152 +# CONFIG_USB_CYTHERM is not set
1153 +# CONFIG_USB_PHIDGET is not set
1154 +# CONFIG_USB_IDMOUSE is not set
1155 +# CONFIG_USB_FTDI_ELAN is not set
1156 +# CONFIG_USB_APPLEDISPLAY is not set
1157 +# CONFIG_USB_SISUSBVGA is not set
1158 +# CONFIG_USB_LD is not set
1159 +# CONFIG_USB_TRANCEVIBRATOR is not set
1160 +# CONFIG_USB_IOWARRIOR is not set
1161 +# CONFIG_USB_TEST is not set
1162 +# CONFIG_USB_ISIGHTFW is not set
1163 +# CONFIG_USB_GADGET is not set
1164 +# CONFIG_MMC is not set
1165 +CONFIG_NEW_LEDS=y
1166 +# CONFIG_LEDS_CLASS is not set
1167 +
1168 +#
1169 +# LED drivers
1170 +#
1171 +
1172 +#
1173 +# LED Triggers
1174 +#
1175 +# CONFIG_LEDS_TRIGGERS is not set
1176 +CONFIG_RTC_LIB=y
1177 +CONFIG_RTC_CLASS=y
1178 +# CONFIG_RTC_DEBUG is not set
1179 +
1180 +#
1181 +# RTC interfaces
1182 +#
1183 +CONFIG_RTC_INTF_SYSFS=y
1184 +CONFIG_RTC_INTF_PROC=y
1185 +CONFIG_RTC_INTF_DEV=y
1186 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1187 +# CONFIG_RTC_DRV_TEST is not set
1188 +
1189 +#
1190 +# I2C RTC drivers
1191 +#
1192 +# CONFIG_RTC_DRV_DS1307 is not set
1193 +# CONFIG_RTC_DRV_DS1374 is not set
1194 +# CONFIG_RTC_DRV_DS1672 is not set
1195 +# CONFIG_RTC_DRV_MAX6900 is not set
1196 +CONFIG_RTC_DRV_MV=y
1197 +# CONFIG_RTC_DRV_RS5C372 is not set
1198 +# CONFIG_RTC_DRV_ISL1208 is not set
1199 +# CONFIG_RTC_DRV_X1205 is not set
1200 +# CONFIG_RTC_DRV_PCF8563 is not set
1201 +# CONFIG_RTC_DRV_PCF8583 is not set
1202 +# CONFIG_RTC_DRV_M41T80 is not set
1203 +# CONFIG_RTC_DRV_S35390A is not set
1204 +
1205 +#
1206 +# SPI RTC drivers
1207 +#
1208 +# CONFIG_RTC_DRV_MAX6902 is not set
1209 +# CONFIG_RTC_DRV_R9701 is not set
1210 +# CONFIG_RTC_DRV_RS5C348 is not set
1211 +
1212 +#
1213 +# Platform RTC drivers
1214 +#
1215 +# CONFIG_RTC_DRV_CMOS is not set
1216 +# CONFIG_RTC_DRV_DS1511 is not set
1217 +# CONFIG_RTC_DRV_DS1553 is not set
1218 +# CONFIG_RTC_DRV_DS1742 is not set
1219 +# CONFIG_RTC_DRV_STK17TA8 is not set
1220 +# CONFIG_RTC_DRV_M48T86 is not set
1221 +# CONFIG_RTC_DRV_M48T59 is not set
1222 +# CONFIG_RTC_DRV_V3020 is not set
1223 +
1224 +#
1225 +# on-CPU RTC drivers
1226 +#
1227 +CONFIG_DMADEVICES=y
1228 +
1229 +#
1230 +# DMA Devices
1231 +#
1232 +CONFIG_MV_XOR=y
1233 +CONFIG_DMA_ENGINE=y
1234 +
1235 +#
1236 +# DMA Clients
1237 +#
1238 +# CONFIG_NET_DMA is not set
1239 +# CONFIG_UIO is not set
1240 +
1241 +#
1242 +# File systems
1243 +#
1244 +CONFIG_EXT2_FS=y
1245 +# CONFIG_EXT2_FS_XATTR is not set
1246 +# CONFIG_EXT2_FS_XIP is not set
1247 +CONFIG_EXT3_FS=y
1248 +# CONFIG_EXT3_FS_XATTR is not set
1249 +# CONFIG_EXT4DEV_FS is not set
1250 +CONFIG_JBD=y
1251 +# CONFIG_REISERFS_FS is not set
1252 +# CONFIG_JFS_FS is not set
1253 +# CONFIG_FS_POSIX_ACL is not set
1254 +CONFIG_XFS_FS=y
1255 +# CONFIG_XFS_QUOTA is not set
1256 +# CONFIG_XFS_POSIX_ACL is not set
1257 +# CONFIG_XFS_RT is not set
1258 +# CONFIG_XFS_DEBUG is not set
1259 +# CONFIG_OCFS2_FS is not set
1260 +CONFIG_DNOTIFY=y
1261 +CONFIG_INOTIFY=y
1262 +CONFIG_INOTIFY_USER=y
1263 +# CONFIG_QUOTA is not set
1264 +# CONFIG_AUTOFS_FS is not set
1265 +# CONFIG_AUTOFS4_FS is not set
1266 +# CONFIG_FUSE_FS is not set
1267 +
1268 +#
1269 +# CD-ROM/DVD Filesystems
1270 +#
1271 +CONFIG_ISO9660_FS=y
1272 +CONFIG_JOLIET=y
1273 +# CONFIG_ZISOFS is not set
1274 +CONFIG_UDF_FS=m
1275 +CONFIG_UDF_NLS=y
1276 +
1277 +#
1278 +# DOS/FAT/NT Filesystems
1279 +#
1280 +CONFIG_FAT_FS=y
1281 +CONFIG_MSDOS_FS=y
1282 +CONFIG_VFAT_FS=y
1283 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1284 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1285 +# CONFIG_NTFS_FS is not set
1286 +
1287 +#
1288 +# Pseudo filesystems
1289 +#
1290 +CONFIG_PROC_FS=y
1291 +CONFIG_PROC_SYSCTL=y
1292 +CONFIG_SYSFS=y
1293 +CONFIG_TMPFS=y
1294 +# CONFIG_TMPFS_POSIX_ACL is not set
1295 +# CONFIG_HUGETLB_PAGE is not set
1296 +# CONFIG_CONFIGFS_FS is not set
1297 +
1298 +#
1299 +# Miscellaneous filesystems
1300 +#
1301 +# CONFIG_ADFS_FS is not set
1302 +# CONFIG_AFFS_FS is not set
1303 +# CONFIG_HFS_FS is not set
1304 +# CONFIG_HFSPLUS_FS is not set
1305 +# CONFIG_BEFS_FS is not set
1306 +# CONFIG_BFS_FS is not set
1307 +# CONFIG_EFS_FS is not set
1308 +CONFIG_JFFS2_FS=y
1309 +CONFIG_JFFS2_FS_DEBUG=0
1310 +CONFIG_JFFS2_FS_WRITEBUFFER=y
1311 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1312 +# CONFIG_JFFS2_SUMMARY is not set
1313 +# CONFIG_JFFS2_FS_XATTR is not set
1314 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1315 +CONFIG_JFFS2_ZLIB=y
1316 +# CONFIG_JFFS2_LZO is not set
1317 +CONFIG_JFFS2_RTIME=y
1318 +# CONFIG_JFFS2_RUBIN is not set
1319 +CONFIG_CRAMFS=y
1320 +# CONFIG_VXFS_FS is not set
1321 +# CONFIG_MINIX_FS is not set
1322 +# CONFIG_HPFS_FS is not set
1323 +# CONFIG_QNX4FS_FS is not set
1324 +# CONFIG_ROMFS_FS is not set
1325 +# CONFIG_SYSV_FS is not set
1326 +# CONFIG_UFS_FS is not set
1327 +CONFIG_NETWORK_FILESYSTEMS=y
1328 +CONFIG_NFS_FS=y
1329 +CONFIG_NFS_V3=y
1330 +# CONFIG_NFS_V3_ACL is not set
1331 +# CONFIG_NFS_V4 is not set
1332 +# CONFIG_NFSD is not set
1333 +CONFIG_ROOT_NFS=y
1334 +CONFIG_LOCKD=y
1335 +CONFIG_LOCKD_V4=y
1336 +CONFIG_NFS_COMMON=y
1337 +CONFIG_SUNRPC=y
1338 +# CONFIG_SUNRPC_BIND34 is not set
1339 +# CONFIG_RPCSEC_GSS_KRB5 is not set
1340 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
1341 +# CONFIG_SMB_FS is not set
1342 +# CONFIG_CIFS is not set
1343 +# CONFIG_NCP_FS is not set
1344 +# CONFIG_CODA_FS is not set
1345 +# CONFIG_AFS_FS is not set
1346 +
1347 +#
1348 +# Partition Types
1349 +#
1350 +CONFIG_PARTITION_ADVANCED=y
1351 +# CONFIG_ACORN_PARTITION is not set
1352 +# CONFIG_OSF_PARTITION is not set
1353 +# CONFIG_AMIGA_PARTITION is not set
1354 +# CONFIG_ATARI_PARTITION is not set
1355 +# CONFIG_MAC_PARTITION is not set
1356 +CONFIG_MSDOS_PARTITION=y
1357 +# CONFIG_BSD_DISKLABEL is not set
1358 +# CONFIG_MINIX_SUBPARTITION is not set
1359 +# CONFIG_SOLARIS_X86_PARTITION is not set
1360 +# CONFIG_UNIXWARE_DISKLABEL is not set
1361 +# CONFIG_LDM_PARTITION is not set
1362 +# CONFIG_SGI_PARTITION is not set
1363 +# CONFIG_ULTRIX_PARTITION is not set
1364 +# CONFIG_SUN_PARTITION is not set
1365 +# CONFIG_KARMA_PARTITION is not set
1366 +# CONFIG_EFI_PARTITION is not set
1367 +# CONFIG_SYSV68_PARTITION is not set
1368 +CONFIG_NLS=y
1369 +CONFIG_NLS_DEFAULT="iso8859-1"
1370 +CONFIG_NLS_CODEPAGE_437=y
1371 +# CONFIG_NLS_CODEPAGE_737 is not set
1372 +# CONFIG_NLS_CODEPAGE_775 is not set
1373 +CONFIG_NLS_CODEPAGE_850=y
1374 +# CONFIG_NLS_CODEPAGE_852 is not set
1375 +# CONFIG_NLS_CODEPAGE_855 is not set
1376 +# CONFIG_NLS_CODEPAGE_857 is not set
1377 +# CONFIG_NLS_CODEPAGE_860 is not set
1378 +# CONFIG_NLS_CODEPAGE_861 is not set
1379 +# CONFIG_NLS_CODEPAGE_862 is not set
1380 +# CONFIG_NLS_CODEPAGE_863 is not set
1381 +# CONFIG_NLS_CODEPAGE_864 is not set
1382 +# CONFIG_NLS_CODEPAGE_865 is not set
1383 +# CONFIG_NLS_CODEPAGE_866 is not set
1384 +# CONFIG_NLS_CODEPAGE_869 is not set
1385 +# CONFIG_NLS_CODEPAGE_936 is not set
1386 +# CONFIG_NLS_CODEPAGE_950 is not set
1387 +# CONFIG_NLS_CODEPAGE_932 is not set
1388 +# CONFIG_NLS_CODEPAGE_949 is not set
1389 +# CONFIG_NLS_CODEPAGE_874 is not set
1390 +# CONFIG_NLS_ISO8859_8 is not set
1391 +# CONFIG_NLS_CODEPAGE_1250 is not set
1392 +# CONFIG_NLS_CODEPAGE_1251 is not set
1393 +# CONFIG_NLS_ASCII is not set
1394 +CONFIG_NLS_ISO8859_1=y
1395 +CONFIG_NLS_ISO8859_2=y
1396 +# CONFIG_NLS_ISO8859_3 is not set
1397 +# CONFIG_NLS_ISO8859_4 is not set
1398 +# CONFIG_NLS_ISO8859_5 is not set
1399 +# CONFIG_NLS_ISO8859_6 is not set
1400 +# CONFIG_NLS_ISO8859_7 is not set
1401 +# CONFIG_NLS_ISO8859_9 is not set
1402 +# CONFIG_NLS_ISO8859_13 is not set
1403 +# CONFIG_NLS_ISO8859_14 is not set
1404 +# CONFIG_NLS_ISO8859_15 is not set
1405 +# CONFIG_NLS_KOI8_R is not set
1406 +# CONFIG_NLS_KOI8_U is not set
1407 +CONFIG_NLS_UTF8=y
1408 +# CONFIG_DLM is not set
1409 +
1410 +#
1411 +# Kernel hacking
1412 +#
1413 +# CONFIG_PRINTK_TIME is not set
1414 +CONFIG_ENABLE_WARN_DEPRECATED=y
1415 +CONFIG_ENABLE_MUST_CHECK=y
1416 +CONFIG_FRAME_WARN=1024
1417 +CONFIG_MAGIC_SYSRQ=y
1418 +# CONFIG_UNUSED_SYMBOLS is not set
1419 +# CONFIG_DEBUG_FS is not set
1420 +# CONFIG_HEADERS_CHECK is not set
1421 +CONFIG_DEBUG_KERNEL=y
1422 +# CONFIG_DEBUG_SHIRQ is not set
1423 +CONFIG_DETECT_SOFTLOCKUP=y
1424 +# CONFIG_SCHED_DEBUG is not set
1425 +# CONFIG_SCHEDSTATS is not set
1426 +# CONFIG_TIMER_STATS is not set
1427 +# CONFIG_DEBUG_OBJECTS is not set
1428 +# CONFIG_DEBUG_SLAB is not set
1429 +# CONFIG_DEBUG_PREEMPT is not set
1430 +# CONFIG_DEBUG_RT_MUTEXES is not set
1431 +# CONFIG_RT_MUTEX_TESTER is not set
1432 +# CONFIG_DEBUG_SPINLOCK is not set
1433 +# CONFIG_DEBUG_MUTEXES is not set
1434 +# CONFIG_DEBUG_LOCK_ALLOC is not set
1435 +# CONFIG_PROVE_LOCKING is not set
1436 +# CONFIG_LOCK_STAT is not set
1437 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1438 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1439 +# CONFIG_DEBUG_KOBJECT is not set
1440 +# CONFIG_DEBUG_BUGVERBOSE is not set
1441 +CONFIG_DEBUG_INFO=y
1442 +# CONFIG_DEBUG_VM is not set
1443 +# CONFIG_DEBUG_WRITECOUNT is not set
1444 +# CONFIG_DEBUG_LIST is not set
1445 +# CONFIG_DEBUG_SG is not set
1446 +CONFIG_FRAME_POINTER=y
1447 +# CONFIG_BOOT_PRINTK_DELAY is not set
1448 +# CONFIG_RCU_TORTURE_TEST is not set
1449 +# CONFIG_KPROBES_SANITY_TEST is not set
1450 +# CONFIG_BACKTRACE_SELF_TEST is not set
1451 +# CONFIG_LKDTM is not set
1452 +# CONFIG_FAULT_INJECTION is not set
1453 +# CONFIG_LATENCYTOP is not set
1454 +# CONFIG_SAMPLES is not set
1455 +CONFIG_DEBUG_USER=y
1456 +CONFIG_DEBUG_ERRORS=y
1457 +# CONFIG_DEBUG_STACK_USAGE is not set
1458 +CONFIG_DEBUG_LL=y
1459 +# CONFIG_DEBUG_ICEDCC is not set
1460 +
1461 +#
1462 +# Security options
1463 +#
1464 +# CONFIG_KEYS is not set
1465 +# CONFIG_SECURITY is not set
1466 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1467 +CONFIG_ASYNC_CORE=y
1468 +CONFIG_CRYPTO=y
1469 +
1470 +#
1471 +# Crypto core or helper
1472 +#
1473 +CONFIG_CRYPTO_ALGAPI=m
1474 +CONFIG_CRYPTO_BLKCIPHER=m
1475 +CONFIG_CRYPTO_MANAGER=m
1476 +# CONFIG_CRYPTO_GF128MUL is not set
1477 +# CONFIG_CRYPTO_NULL is not set
1478 +# CONFIG_CRYPTO_CRYPTD is not set
1479 +# CONFIG_CRYPTO_AUTHENC is not set
1480 +# CONFIG_CRYPTO_TEST is not set
1481 +
1482 +#
1483 +# Authenticated Encryption with Associated Data
1484 +#
1485 +# CONFIG_CRYPTO_CCM is not set
1486 +# CONFIG_CRYPTO_GCM is not set
1487 +# CONFIG_CRYPTO_SEQIV is not set
1488 +
1489 +#
1490 +# Block modes
1491 +#
1492 +CONFIG_CRYPTO_CBC=m
1493 +# CONFIG_CRYPTO_CTR is not set
1494 +# CONFIG_CRYPTO_CTS is not set
1495 +CONFIG_CRYPTO_ECB=m
1496 +# CONFIG_CRYPTO_LRW is not set
1497 +CONFIG_CRYPTO_PCBC=m
1498 +# CONFIG_CRYPTO_XTS is not set
1499 +
1500 +#
1501 +# Hash modes
1502 +#
1503 +# CONFIG_CRYPTO_HMAC is not set
1504 +# CONFIG_CRYPTO_XCBC is not set
1505 +
1506 +#
1507 +# Digest
1508 +#
1509 +# CONFIG_CRYPTO_CRC32C is not set
1510 +# CONFIG_CRYPTO_MD4 is not set
1511 +# CONFIG_CRYPTO_MD5 is not set
1512 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
1513 +# CONFIG_CRYPTO_SHA1 is not set
1514 +# CONFIG_CRYPTO_SHA256 is not set
1515 +# CONFIG_CRYPTO_SHA512 is not set
1516 +# CONFIG_CRYPTO_TGR192 is not set
1517 +# CONFIG_CRYPTO_WP512 is not set
1518 +
1519 +#
1520 +# Ciphers
1521 +#
1522 +# CONFIG_CRYPTO_AES is not set
1523 +# CONFIG_CRYPTO_ANUBIS is not set
1524 +# CONFIG_CRYPTO_ARC4 is not set
1525 +# CONFIG_CRYPTO_BLOWFISH is not set
1526 +# CONFIG_CRYPTO_CAMELLIA is not set
1527 +# CONFIG_CRYPTO_CAST5 is not set
1528 +# CONFIG_CRYPTO_CAST6 is not set
1529 +# CONFIG_CRYPTO_DES is not set
1530 +# CONFIG_CRYPTO_FCRYPT is not set
1531 +# CONFIG_CRYPTO_KHAZAD is not set
1532 +# CONFIG_CRYPTO_SALSA20 is not set
1533 +# CONFIG_CRYPTO_SEED is not set
1534 +# CONFIG_CRYPTO_SERPENT is not set
1535 +# CONFIG_CRYPTO_TEA is not set
1536 +# CONFIG_CRYPTO_TWOFISH is not set
1537 +
1538 +#
1539 +# Compression
1540 +#
1541 +# CONFIG_CRYPTO_DEFLATE is not set
1542 +# CONFIG_CRYPTO_LZO is not set
1543 +CONFIG_CRYPTO_HW=y
1544 +# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1545 +
1546 +#
1547 +# Library routines
1548 +#
1549 +CONFIG_BITREVERSE=y
1550 +# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1551 +# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1552 +CONFIG_CRC_CCITT=y
1553 +CONFIG_CRC16=y
1554 +CONFIG_CRC_ITU_T=m
1555 +CONFIG_CRC32=y
1556 +# CONFIG_CRC7 is not set
1557 +CONFIG_LIBCRC32C=y
1558 +CONFIG_ZLIB_INFLATE=y
1559 +CONFIG_ZLIB_DEFLATE=y
1560 +CONFIG_PLIST=y
1561 +CONFIG_HAS_IOMEM=y
1562 +CONFIG_HAS_IOPORT=y
1563 +CONFIG_HAS_DMA=y
1564 --- /dev/null
1565 +++ b/arch/arm/configs/loki_defconfig
1566 @@ -0,0 +1,1147 @@
1567 +#
1568 +# Automatically generated make config: don't edit
1569 +# Linux kernel version: 2.6.26-rc5
1570 +# Fri Jun 13 03:07:49 2008
1571 +#
1572 +CONFIG_ARM=y
1573 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
1574 +# CONFIG_GENERIC_GPIO is not set
1575 +CONFIG_GENERIC_TIME=y
1576 +CONFIG_GENERIC_CLOCKEVENTS=y
1577 +CONFIG_MMU=y
1578 +# CONFIG_NO_IOPORT is not set
1579 +CONFIG_GENERIC_HARDIRQS=y
1580 +CONFIG_STACKTRACE_SUPPORT=y
1581 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
1582 +CONFIG_LOCKDEP_SUPPORT=y
1583 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1584 +CONFIG_HARDIRQS_SW_RESEND=y
1585 +CONFIG_GENERIC_IRQ_PROBE=y
1586 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
1587 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
1588 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
1589 +CONFIG_GENERIC_HWEIGHT=y
1590 +CONFIG_GENERIC_CALIBRATE_DELAY=y
1591 +CONFIG_ARCH_SUPPORTS_AOUT=y
1592 +CONFIG_ZONE_DMA=y
1593 +CONFIG_VECTORS_BASE=0xffff0000
1594 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1595 +
1596 +#
1597 +# General setup
1598 +#
1599 +CONFIG_EXPERIMENTAL=y
1600 +CONFIG_BROKEN_ON_SMP=y
1601 +CONFIG_LOCK_KERNEL=y
1602 +CONFIG_INIT_ENV_ARG_LIMIT=32
1603 +CONFIG_LOCALVERSION=""
1604 +CONFIG_LOCALVERSION_AUTO=y
1605 +CONFIG_SWAP=y
1606 +CONFIG_SYSVIPC=y
1607 +CONFIG_SYSVIPC_SYSCTL=y
1608 +# CONFIG_POSIX_MQUEUE is not set
1609 +# CONFIG_BSD_PROCESS_ACCT is not set
1610 +# CONFIG_TASKSTATS is not set
1611 +# CONFIG_AUDIT is not set
1612 +# CONFIG_IKCONFIG is not set
1613 +CONFIG_LOG_BUF_SHIFT=14
1614 +# CONFIG_CGROUPS is not set
1615 +# CONFIG_GROUP_SCHED is not set
1616 +# CONFIG_SYSFS_DEPRECATED_V2 is not set
1617 +# CONFIG_RELAY is not set
1618 +# CONFIG_NAMESPACES is not set
1619 +# CONFIG_BLK_DEV_INITRD is not set
1620 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1621 +CONFIG_SYSCTL=y
1622 +CONFIG_EMBEDDED=y
1623 +CONFIG_UID16=y
1624 +CONFIG_SYSCTL_SYSCALL=y
1625 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1626 +CONFIG_KALLSYMS=y
1627 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
1628 +CONFIG_HOTPLUG=y
1629 +CONFIG_PRINTK=y
1630 +CONFIG_BUG=y
1631 +CONFIG_ELF_CORE=y
1632 +CONFIG_COMPAT_BRK=y
1633 +CONFIG_BASE_FULL=y
1634 +CONFIG_FUTEX=y
1635 +CONFIG_ANON_INODES=y
1636 +CONFIG_EPOLL=y
1637 +CONFIG_SIGNALFD=y
1638 +CONFIG_TIMERFD=y
1639 +CONFIG_EVENTFD=y
1640 +CONFIG_SHMEM=y
1641 +CONFIG_VM_EVENT_COUNTERS=y
1642 +CONFIG_SLAB=y
1643 +# CONFIG_SLUB is not set
1644 +# CONFIG_SLOB is not set
1645 +# CONFIG_PROFILING is not set
1646 +# CONFIG_MARKERS is not set
1647 +CONFIG_HAVE_OPROFILE=y
1648 +# CONFIG_KPROBES is not set
1649 +CONFIG_HAVE_KPROBES=y
1650 +CONFIG_HAVE_KRETPROBES=y
1651 +# CONFIG_HAVE_DMA_ATTRS is not set
1652 +CONFIG_PROC_PAGE_MONITOR=y
1653 +CONFIG_SLABINFO=y
1654 +CONFIG_RT_MUTEXES=y
1655 +# CONFIG_TINY_SHMEM is not set
1656 +CONFIG_BASE_SMALL=0
1657 +CONFIG_MODULES=y
1658 +# CONFIG_MODULE_FORCE_LOAD is not set
1659 +CONFIG_MODULE_UNLOAD=y
1660 +# CONFIG_MODULE_FORCE_UNLOAD is not set
1661 +# CONFIG_MODVERSIONS is not set
1662 +# CONFIG_MODULE_SRCVERSION_ALL is not set
1663 +# CONFIG_KMOD is not set
1664 +CONFIG_BLOCK=y
1665 +# CONFIG_LBD is not set
1666 +# CONFIG_BLK_DEV_IO_TRACE is not set
1667 +# CONFIG_LSF is not set
1668 +# CONFIG_BLK_DEV_BSG is not set
1669 +
1670 +#
1671 +# IO Schedulers
1672 +#
1673 +CONFIG_IOSCHED_NOOP=y
1674 +CONFIG_IOSCHED_AS=y
1675 +CONFIG_IOSCHED_DEADLINE=y
1676 +CONFIG_IOSCHED_CFQ=y
1677 +# CONFIG_DEFAULT_AS is not set
1678 +# CONFIG_DEFAULT_DEADLINE is not set
1679 +CONFIG_DEFAULT_CFQ=y
1680 +# CONFIG_DEFAULT_NOOP is not set
1681 +CONFIG_DEFAULT_IOSCHED="cfq"
1682 +CONFIG_CLASSIC_RCU=y
1683 +
1684 +#
1685 +# System Type
1686 +#
1687 +# CONFIG_ARCH_AAEC2000 is not set
1688 +# CONFIG_ARCH_INTEGRATOR is not set
1689 +# CONFIG_ARCH_REALVIEW is not set
1690 +# CONFIG_ARCH_VERSATILE is not set
1691 +# CONFIG_ARCH_AT91 is not set
1692 +# CONFIG_ARCH_CLPS7500 is not set
1693 +# CONFIG_ARCH_CLPS711X is not set
1694 +# CONFIG_ARCH_CO285 is not set
1695 +# CONFIG_ARCH_EBSA110 is not set
1696 +# CONFIG_ARCH_EP93XX is not set
1697 +# CONFIG_ARCH_FOOTBRIDGE is not set
1698 +# CONFIG_ARCH_NETX is not set
1699 +# CONFIG_ARCH_H720X is not set
1700 +# CONFIG_ARCH_IMX is not set
1701 +# CONFIG_ARCH_IOP13XX is not set
1702 +# CONFIG_ARCH_IOP32X is not set
1703 +# CONFIG_ARCH_IOP33X is not set
1704 +# CONFIG_ARCH_IXP23XX is not set
1705 +# CONFIG_ARCH_IXP2000 is not set
1706 +# CONFIG_ARCH_IXP4XX is not set
1707 +# CONFIG_ARCH_L7200 is not set
1708 +# CONFIG_ARCH_KIRKWOOD is not set
1709 +# CONFIG_ARCH_KS8695 is not set
1710 +# CONFIG_ARCH_NS9XXX is not set
1711 +CONFIG_ARCH_LOKI=y
1712 +# CONFIG_ARCH_MV78XX0 is not set
1713 +# CONFIG_ARCH_MXC is not set
1714 +# CONFIG_ARCH_ORION5X is not set
1715 +# CONFIG_ARCH_PNX4008 is not set
1716 +# CONFIG_ARCH_PXA is not set
1717 +# CONFIG_ARCH_RPC is not set
1718 +# CONFIG_ARCH_SA1100 is not set
1719 +# CONFIG_ARCH_S3C2410 is not set
1720 +# CONFIG_ARCH_SHARK is not set
1721 +# CONFIG_ARCH_LH7A40X is not set
1722 +# CONFIG_ARCH_DAVINCI is not set
1723 +# CONFIG_ARCH_OMAP is not set
1724 +# CONFIG_ARCH_MSM7X00A is not set
1725 +
1726 +#
1727 +# Marvell Loki (88RC8480) Implementations
1728 +#
1729 +CONFIG_MACH_LB88RC8480=y
1730 +
1731 +#
1732 +# Boot options
1733 +#
1734 +
1735 +#
1736 +# Power management
1737 +#
1738 +CONFIG_PLAT_ORION=y
1739 +
1740 +#
1741 +# Processor Type
1742 +#
1743 +CONFIG_CPU_32=y
1744 +CONFIG_CPU_FEROCEON=y
1745 +# CONFIG_CPU_FEROCEON_OLD_ID is not set
1746 +CONFIG_CPU_32v5=y
1747 +CONFIG_CPU_ABRT_EV5T=y
1748 +CONFIG_CPU_PABRT_NOIFAR=y
1749 +CONFIG_CPU_CACHE_VIVT=y
1750 +CONFIG_CPU_COPY_FEROCEON=y
1751 +CONFIG_CPU_TLB_FEROCEON=y
1752 +CONFIG_CPU_CP15=y
1753 +CONFIG_CPU_CP15_MMU=y
1754 +
1755 +#
1756 +# Processor Features
1757 +#
1758 +CONFIG_ARM_THUMB=y
1759 +# CONFIG_CPU_ICACHE_DISABLE is not set
1760 +# CONFIG_CPU_DCACHE_DISABLE is not set
1761 +# CONFIG_OUTER_CACHE is not set
1762 +
1763 +#
1764 +# Bus support
1765 +#
1766 +# CONFIG_PCI_SYSCALL is not set
1767 +# CONFIG_ARCH_SUPPORTS_MSI is not set
1768 +# CONFIG_PCCARD is not set
1769 +
1770 +#
1771 +# Kernel Features
1772 +#
1773 +CONFIG_TICK_ONESHOT=y
1774 +CONFIG_NO_HZ=y
1775 +CONFIG_HIGH_RES_TIMERS=y
1776 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1777 +CONFIG_PREEMPT=y
1778 +CONFIG_HZ=100
1779 +CONFIG_AEABI=y
1780 +CONFIG_OABI_COMPAT=y
1781 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
1782 +CONFIG_SELECT_MEMORY_MODEL=y
1783 +CONFIG_FLATMEM_MANUAL=y
1784 +# CONFIG_DISCONTIGMEM_MANUAL is not set
1785 +# CONFIG_SPARSEMEM_MANUAL is not set
1786 +CONFIG_FLATMEM=y
1787 +CONFIG_FLAT_NODE_MEM_MAP=y
1788 +# CONFIG_SPARSEMEM_STATIC is not set
1789 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
1790 +CONFIG_PAGEFLAGS_EXTENDED=y
1791 +CONFIG_SPLIT_PTLOCK_CPUS=4096
1792 +# CONFIG_RESOURCES_64BIT is not set
1793 +CONFIG_ZONE_DMA_FLAG=1
1794 +CONFIG_BOUNCE=y
1795 +CONFIG_VIRT_TO_BUS=y
1796 +CONFIG_ALIGNMENT_TRAP=y
1797 +
1798 +#
1799 +# Boot options
1800 +#
1801 +CONFIG_ZBOOT_ROM_TEXT=0x0
1802 +CONFIG_ZBOOT_ROM_BSS=0x0
1803 +CONFIG_CMDLINE=""
1804 +# CONFIG_XIP_KERNEL is not set
1805 +# CONFIG_KEXEC is not set
1806 +
1807 +#
1808 +# Floating point emulation
1809 +#
1810 +
1811 +#
1812 +# At least one emulation must be selected
1813 +#
1814 +# CONFIG_FPE_NWFPE is not set
1815 +# CONFIG_FPE_FASTFPE is not set
1816 +# CONFIG_VFP is not set
1817 +
1818 +#
1819 +# Userspace binary formats
1820 +#
1821 +CONFIG_BINFMT_ELF=y
1822 +# CONFIG_BINFMT_AOUT is not set
1823 +# CONFIG_BINFMT_MISC is not set
1824 +
1825 +#
1826 +# Power management options
1827 +#
1828 +# CONFIG_PM is not set
1829 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1830 +
1831 +#
1832 +# Networking
1833 +#
1834 +CONFIG_NET=y
1835 +
1836 +#
1837 +# Networking options
1838 +#
1839 +CONFIG_PACKET=y
1840 +CONFIG_PACKET_MMAP=y
1841 +CONFIG_UNIX=y
1842 +CONFIG_XFRM=y
1843 +# CONFIG_XFRM_USER is not set
1844 +# CONFIG_XFRM_SUB_POLICY is not set
1845 +# CONFIG_XFRM_MIGRATE is not set
1846 +# CONFIG_XFRM_STATISTICS is not set
1847 +# CONFIG_NET_KEY is not set
1848 +CONFIG_INET=y
1849 +CONFIG_IP_MULTICAST=y
1850 +# CONFIG_IP_ADVANCED_ROUTER is not set
1851 +CONFIG_IP_FIB_HASH=y
1852 +CONFIG_IP_PNP=y
1853 +CONFIG_IP_PNP_DHCP=y
1854 +CONFIG_IP_PNP_BOOTP=y
1855 +# CONFIG_IP_PNP_RARP is not set
1856 +# CONFIG_NET_IPIP is not set
1857 +# CONFIG_NET_IPGRE is not set
1858 +# CONFIG_IP_MROUTE is not set
1859 +# CONFIG_ARPD is not set
1860 +# CONFIG_SYN_COOKIES is not set
1861 +# CONFIG_INET_AH is not set
1862 +# CONFIG_INET_ESP is not set
1863 +# CONFIG_INET_IPCOMP is not set
1864 +# CONFIG_INET_XFRM_TUNNEL is not set
1865 +# CONFIG_INET_TUNNEL is not set
1866 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
1867 +CONFIG_INET_XFRM_MODE_TUNNEL=y
1868 +CONFIG_INET_XFRM_MODE_BEET=y
1869 +# CONFIG_INET_LRO is not set
1870 +CONFIG_INET_DIAG=y
1871 +CONFIG_INET_TCP_DIAG=y
1872 +# CONFIG_TCP_CONG_ADVANCED is not set
1873 +CONFIG_TCP_CONG_CUBIC=y
1874 +CONFIG_DEFAULT_TCP_CONG="cubic"
1875 +# CONFIG_TCP_MD5SIG is not set
1876 +# CONFIG_IPV6 is not set
1877 +# CONFIG_NETWORK_SECMARK is not set
1878 +# CONFIG_NETFILTER is not set
1879 +# CONFIG_IP_DCCP is not set
1880 +# CONFIG_IP_SCTP is not set
1881 +# CONFIG_TIPC is not set
1882 +# CONFIG_ATM is not set
1883 +# CONFIG_BRIDGE is not set
1884 +# CONFIG_VLAN_8021Q is not set
1885 +# CONFIG_DECNET is not set
1886 +# CONFIG_LLC2 is not set
1887 +# CONFIG_IPX is not set
1888 +# CONFIG_ATALK is not set
1889 +# CONFIG_X25 is not set
1890 +# CONFIG_LAPB is not set
1891 +# CONFIG_ECONET is not set
1892 +# CONFIG_WAN_ROUTER is not set
1893 +# CONFIG_NET_SCHED is not set
1894 +
1895 +#
1896 +# Network testing
1897 +#
1898 +CONFIG_NET_PKTGEN=m
1899 +# CONFIG_HAMRADIO is not set
1900 +# CONFIG_CAN is not set
1901 +# CONFIG_IRDA is not set
1902 +# CONFIG_BT is not set
1903 +# CONFIG_AF_RXRPC is not set
1904 +
1905 +#
1906 +# Wireless
1907 +#
1908 +# CONFIG_CFG80211 is not set
1909 +CONFIG_WIRELESS_EXT=y
1910 +# CONFIG_MAC80211 is not set
1911 +# CONFIG_IEEE80211 is not set
1912 +# CONFIG_RFKILL is not set
1913 +# CONFIG_NET_9P is not set
1914 +
1915 +#
1916 +# Device Drivers
1917 +#
1918 +
1919 +#
1920 +# Generic Driver Options
1921 +#
1922 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1923 +CONFIG_STANDALONE=y
1924 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1925 +CONFIG_FW_LOADER=y
1926 +# CONFIG_SYS_HYPERVISOR is not set
1927 +# CONFIG_CONNECTOR is not set
1928 +CONFIG_MTD=y
1929 +# CONFIG_MTD_DEBUG is not set
1930 +# CONFIG_MTD_CONCAT is not set
1931 +CONFIG_MTD_PARTITIONS=y
1932 +# CONFIG_MTD_REDBOOT_PARTS is not set
1933 +CONFIG_MTD_CMDLINE_PARTS=y
1934 +# CONFIG_MTD_AFS_PARTS is not set
1935 +# CONFIG_MTD_AR7_PARTS is not set
1936 +
1937 +#
1938 +# User Modules And Translation Layers
1939 +#
1940 +CONFIG_MTD_CHAR=y
1941 +CONFIG_MTD_BLKDEVS=y
1942 +CONFIG_MTD_BLOCK=y
1943 +CONFIG_FTL=y
1944 +CONFIG_NFTL=y
1945 +# CONFIG_NFTL_RW is not set
1946 +# CONFIG_INFTL is not set
1947 +# CONFIG_RFD_FTL is not set
1948 +# CONFIG_SSFDC is not set
1949 +# CONFIG_MTD_OOPS is not set
1950 +
1951 +#
1952 +# RAM/ROM/Flash chip drivers
1953 +#
1954 +CONFIG_MTD_CFI=y
1955 +CONFIG_MTD_JEDECPROBE=y
1956 +CONFIG_MTD_GEN_PROBE=y
1957 +CONFIG_MTD_CFI_ADV_OPTIONS=y
1958 +CONFIG_MTD_CFI_NOSWAP=y
1959 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
1960 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
1961 +CONFIG_MTD_CFI_GEOMETRY=y
1962 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
1963 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
1964 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
1965 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1966 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1967 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1968 +CONFIG_MTD_CFI_I1=y
1969 +CONFIG_MTD_CFI_I2=y
1970 +CONFIG_MTD_CFI_I4=y
1971 +# CONFIG_MTD_CFI_I8 is not set
1972 +# CONFIG_MTD_OTP is not set
1973 +CONFIG_MTD_CFI_INTELEXT=y
1974 +CONFIG_MTD_CFI_AMDSTD=y
1975 +CONFIG_MTD_CFI_STAA=y
1976 +CONFIG_MTD_CFI_UTIL=y
1977 +# CONFIG_MTD_RAM is not set
1978 +# CONFIG_MTD_ROM is not set
1979 +# CONFIG_MTD_ABSENT is not set
1980 +
1981 +#
1982 +# Mapping drivers for chip access
1983 +#
1984 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1985 +CONFIG_MTD_PHYSMAP=y
1986 +CONFIG_MTD_PHYSMAP_START=0x0
1987 +CONFIG_MTD_PHYSMAP_LEN=0x0
1988 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0
1989 +# CONFIG_MTD_ARM_INTEGRATOR is not set
1990 +# CONFIG_MTD_IMPA7 is not set
1991 +# CONFIG_MTD_PLATRAM is not set
1992 +
1993 +#
1994 +# Self-contained MTD device drivers
1995 +#
1996 +# CONFIG_MTD_DATAFLASH is not set
1997 +CONFIG_MTD_M25P80=y
1998 +CONFIG_M25PXX_USE_FAST_READ=y
1999 +# CONFIG_MTD_SLRAM is not set
2000 +# CONFIG_MTD_PHRAM is not set
2001 +# CONFIG_MTD_MTDRAM is not set
2002 +# CONFIG_MTD_BLOCK2MTD is not set
2003 +
2004 +#
2005 +# Disk-On-Chip Device Drivers
2006 +#
2007 +# CONFIG_MTD_DOC2000 is not set
2008 +# CONFIG_MTD_DOC2001 is not set
2009 +# CONFIG_MTD_DOC2001PLUS is not set
2010 +CONFIG_MTD_NAND=y
2011 +CONFIG_MTD_NAND_VERIFY_WRITE=y
2012 +# CONFIG_MTD_NAND_ECC_SMC is not set
2013 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
2014 +CONFIG_MTD_NAND_IDS=y
2015 +# CONFIG_MTD_NAND_DISKONCHIP is not set
2016 +# CONFIG_MTD_NAND_NANDSIM is not set
2017 +# CONFIG_MTD_NAND_PLATFORM is not set
2018 +# CONFIG_MTD_ALAUDA is not set
2019 +CONFIG_MTD_NAND_ORION=y
2020 +# CONFIG_MTD_ONENAND is not set
2021 +
2022 +#
2023 +# UBI - Unsorted block images
2024 +#
2025 +# CONFIG_MTD_UBI is not set
2026 +# CONFIG_PARPORT is not set
2027 +CONFIG_BLK_DEV=y
2028 +# CONFIG_BLK_DEV_COW_COMMON is not set
2029 +CONFIG_BLK_DEV_LOOP=y
2030 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2031 +# CONFIG_BLK_DEV_NBD is not set
2032 +# CONFIG_BLK_DEV_UB is not set
2033 +# CONFIG_BLK_DEV_RAM is not set
2034 +# CONFIG_CDROM_PKTCDVD is not set
2035 +# CONFIG_ATA_OVER_ETH is not set
2036 +# CONFIG_MISC_DEVICES is not set
2037 +CONFIG_HAVE_IDE=y
2038 +# CONFIG_IDE is not set
2039 +
2040 +#
2041 +# SCSI device support
2042 +#
2043 +# CONFIG_RAID_ATTRS is not set
2044 +CONFIG_SCSI=y
2045 +CONFIG_SCSI_DMA=y
2046 +# CONFIG_SCSI_TGT is not set
2047 +# CONFIG_SCSI_NETLINK is not set
2048 +# CONFIG_SCSI_PROC_FS is not set
2049 +
2050 +#
2051 +# SCSI support type (disk, tape, CD-ROM)
2052 +#
2053 +CONFIG_BLK_DEV_SD=y
2054 +# CONFIG_CHR_DEV_ST is not set
2055 +# CONFIG_CHR_DEV_OSST is not set
2056 +CONFIG_BLK_DEV_SR=m
2057 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2058 +CONFIG_CHR_DEV_SG=m
2059 +# CONFIG_CHR_DEV_SCH is not set
2060 +
2061 +#
2062 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2063 +#
2064 +# CONFIG_SCSI_MULTI_LUN is not set
2065 +# CONFIG_SCSI_CONSTANTS is not set
2066 +# CONFIG_SCSI_LOGGING is not set
2067 +# CONFIG_SCSI_SCAN_ASYNC is not set
2068 +CONFIG_SCSI_WAIT_SCAN=m
2069 +
2070 +#
2071 +# SCSI Transports
2072 +#
2073 +# CONFIG_SCSI_SPI_ATTRS is not set
2074 +# CONFIG_SCSI_FC_ATTRS is not set
2075 +# CONFIG_SCSI_ISCSI_ATTRS is not set
2076 +# CONFIG_SCSI_SAS_LIBSAS is not set
2077 +# CONFIG_SCSI_SRP_ATTRS is not set
2078 +CONFIG_SCSI_LOWLEVEL=y
2079 +# CONFIG_ISCSI_TCP is not set
2080 +# CONFIG_SCSI_DEBUG is not set
2081 +CONFIG_ATA=y
2082 +# CONFIG_ATA_NONSTANDARD is not set
2083 +CONFIG_SATA_PMP=y
2084 +CONFIG_ATA_SFF=y
2085 +CONFIG_SATA_MV=y
2086 +# CONFIG_PATA_PLATFORM is not set
2087 +# CONFIG_MD is not set
2088 +CONFIG_NETDEVICES=y
2089 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
2090 +# CONFIG_DUMMY is not set
2091 +# CONFIG_BONDING is not set
2092 +# CONFIG_MACVLAN is not set
2093 +# CONFIG_EQUALIZER is not set
2094 +# CONFIG_TUN is not set
2095 +# CONFIG_VETH is not set
2096 +# CONFIG_PHYLIB is not set
2097 +CONFIG_NET_ETHERNET=y
2098 +CONFIG_MII=y
2099 +# CONFIG_AX88796 is not set
2100 +# CONFIG_SMC91X is not set
2101 +# CONFIG_DM9000 is not set
2102 +# CONFIG_ENC28J60 is not set
2103 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
2104 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
2105 +# CONFIG_IBM_NEW_EMAC_TAH is not set
2106 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2107 +# CONFIG_B44 is not set
2108 +CONFIG_NETDEV_1000=y
2109 +# CONFIG_E1000E_ENABLED is not set
2110 +CONFIG_MV643XX_ETH=y
2111 +# CONFIG_NETDEV_10000 is not set
2112 +
2113 +#
2114 +# Wireless LAN
2115 +#
2116 +# CONFIG_WLAN_PRE80211 is not set
2117 +# CONFIG_WLAN_80211 is not set
2118 +# CONFIG_IWLWIFI_LEDS is not set
2119 +
2120 +#
2121 +# USB Network Adapters
2122 +#
2123 +# CONFIG_USB_CATC is not set
2124 +# CONFIG_USB_KAWETH is not set
2125 +# CONFIG_USB_PEGASUS is not set
2126 +# CONFIG_USB_RTL8150 is not set
2127 +# CONFIG_USB_USBNET is not set
2128 +# CONFIG_WAN is not set
2129 +# CONFIG_PPP is not set
2130 +# CONFIG_SLIP is not set
2131 +# CONFIG_NETCONSOLE is not set
2132 +# CONFIG_NETPOLL is not set
2133 +# CONFIG_NET_POLL_CONTROLLER is not set
2134 +# CONFIG_ISDN is not set
2135 +
2136 +#
2137 +# Input device support
2138 +#
2139 +CONFIG_INPUT=y
2140 +# CONFIG_INPUT_FF_MEMLESS is not set
2141 +# CONFIG_INPUT_POLLDEV is not set
2142 +
2143 +#
2144 +# Userland interfaces
2145 +#
2146 +CONFIG_INPUT_MOUSEDEV=y
2147 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
2148 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2149 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2150 +# CONFIG_INPUT_JOYDEV is not set
2151 +# CONFIG_INPUT_EVDEV is not set
2152 +# CONFIG_INPUT_EVBUG is not set
2153 +
2154 +#
2155 +# Input Device Drivers
2156 +#
2157 +# CONFIG_INPUT_KEYBOARD is not set
2158 +# CONFIG_INPUT_MOUSE is not set
2159 +# CONFIG_INPUT_JOYSTICK is not set
2160 +# CONFIG_INPUT_TABLET is not set
2161 +# CONFIG_INPUT_TOUCHSCREEN is not set
2162 +# CONFIG_INPUT_MISC is not set
2163 +
2164 +#
2165 +# Hardware I/O ports
2166 +#
2167 +# CONFIG_SERIO is not set
2168 +# CONFIG_GAMEPORT is not set
2169 +
2170 +#
2171 +# Character devices
2172 +#
2173 +CONFIG_VT=y
2174 +CONFIG_VT_CONSOLE=y
2175 +CONFIG_HW_CONSOLE=y
2176 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
2177 +CONFIG_DEVKMEM=y
2178 +# CONFIG_SERIAL_NONSTANDARD is not set
2179 +
2180 +#
2181 +# Serial drivers
2182 +#
2183 +CONFIG_SERIAL_8250=y
2184 +CONFIG_SERIAL_8250_CONSOLE=y
2185 +CONFIG_SERIAL_8250_NR_UARTS=4
2186 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
2187 +# CONFIG_SERIAL_8250_EXTENDED is not set
2188 +
2189 +#
2190 +# Non-8250 serial port support
2191 +#
2192 +CONFIG_SERIAL_CORE=y
2193 +CONFIG_SERIAL_CORE_CONSOLE=y
2194 +CONFIG_UNIX98_PTYS=y
2195 +CONFIG_LEGACY_PTYS=y
2196 +CONFIG_LEGACY_PTY_COUNT=16
2197 +# CONFIG_IPMI_HANDLER is not set
2198 +CONFIG_HW_RANDOM=m
2199 +# CONFIG_NVRAM is not set
2200 +# CONFIG_R3964 is not set
2201 +# CONFIG_RAW_DRIVER is not set
2202 +# CONFIG_TCG_TPM is not set
2203 +CONFIG_I2C=y
2204 +CONFIG_I2C_BOARDINFO=y
2205 +CONFIG_I2C_CHARDEV=y
2206 +
2207 +#
2208 +# I2C Hardware Bus support
2209 +#
2210 +# CONFIG_I2C_OCORES is not set
2211 +# CONFIG_I2C_PARPORT_LIGHT is not set
2212 +# CONFIG_I2C_SIMTEC is not set
2213 +# CONFIG_I2C_TAOS_EVM is not set
2214 +# CONFIG_I2C_STUB is not set
2215 +# CONFIG_I2C_TINY_USB is not set
2216 +# CONFIG_I2C_PCA_PLATFORM is not set
2217 +CONFIG_I2C_MV64XXX=y
2218 +
2219 +#
2220 +# Miscellaneous I2C Chip support
2221 +#
2222 +# CONFIG_DS1682 is not set
2223 +# CONFIG_SENSORS_EEPROM is not set
2224 +# CONFIG_SENSORS_PCF8574 is not set
2225 +# CONFIG_PCF8575 is not set
2226 +# CONFIG_SENSORS_PCF8591 is not set
2227 +# CONFIG_SENSORS_MAX6875 is not set
2228 +# CONFIG_SENSORS_TSL2550 is not set
2229 +# CONFIG_I2C_DEBUG_CORE is not set
2230 +# CONFIG_I2C_DEBUG_ALGO is not set
2231 +# CONFIG_I2C_DEBUG_BUS is not set
2232 +# CONFIG_I2C_DEBUG_CHIP is not set
2233 +CONFIG_SPI=y
2234 +CONFIG_SPI_MASTER=y
2235 +
2236 +#
2237 +# SPI Master Controller Drivers
2238 +#
2239 +# CONFIG_SPI_BITBANG is not set
2240 +
2241 +#
2242 +# SPI Protocol Masters
2243 +#
2244 +# CONFIG_SPI_AT25 is not set
2245 +# CONFIG_SPI_SPIDEV is not set
2246 +# CONFIG_SPI_TLE62X0 is not set
2247 +# CONFIG_W1 is not set
2248 +# CONFIG_POWER_SUPPLY is not set
2249 +# CONFIG_HWMON is not set
2250 +# CONFIG_WATCHDOG is not set
2251 +
2252 +#
2253 +# Sonics Silicon Backplane
2254 +#
2255 +CONFIG_SSB_POSSIBLE=y
2256 +# CONFIG_SSB is not set
2257 +
2258 +#
2259 +# Multifunction device drivers
2260 +#
2261 +# CONFIG_MFD_SM501 is not set
2262 +# CONFIG_MFD_ASIC3 is not set
2263 +# CONFIG_HTC_PASIC3 is not set
2264 +
2265 +#
2266 +# Multimedia devices
2267 +#
2268 +
2269 +#
2270 +# Multimedia core support
2271 +#
2272 +# CONFIG_VIDEO_DEV is not set
2273 +# CONFIG_DVB_CORE is not set
2274 +# CONFIG_VIDEO_MEDIA is not set
2275 +
2276 +#
2277 +# Multimedia drivers
2278 +#
2279 +# CONFIG_DAB is not set
2280 +
2281 +#
2282 +# Graphics support
2283 +#
2284 +# CONFIG_VGASTATE is not set
2285 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
2286 +# CONFIG_FB is not set
2287 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
2288 +
2289 +#
2290 +# Display device support
2291 +#
2292 +# CONFIG_DISPLAY_SUPPORT is not set
2293 +
2294 +#
2295 +# Console display driver support
2296 +#
2297 +# CONFIG_VGA_CONSOLE is not set
2298 +CONFIG_DUMMY_CONSOLE=y
2299 +
2300 +#
2301 +# Sound
2302 +#
2303 +# CONFIG_SOUND is not set
2304 +CONFIG_HID_SUPPORT=y
2305 +CONFIG_HID=y
2306 +# CONFIG_HID_DEBUG is not set
2307 +# CONFIG_HIDRAW is not set
2308 +
2309 +#
2310 +# USB Input Devices
2311 +#
2312 +CONFIG_USB_HID=y
2313 +# CONFIG_USB_HIDINPUT_POWERBOOK is not set
2314 +# CONFIG_HID_FF is not set
2315 +# CONFIG_USB_HIDDEV is not set
2316 +CONFIG_USB_SUPPORT=y
2317 +CONFIG_USB_ARCH_HAS_HCD=y
2318 +# CONFIG_USB_ARCH_HAS_OHCI is not set
2319 +# CONFIG_USB_ARCH_HAS_EHCI is not set
2320 +CONFIG_USB=y
2321 +# CONFIG_USB_DEBUG is not set
2322 +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
2323 +
2324 +#
2325 +# Miscellaneous USB options
2326 +#
2327 +CONFIG_USB_DEVICEFS=y
2328 +CONFIG_USB_DEVICE_CLASS=y
2329 +# CONFIG_USB_DYNAMIC_MINORS is not set
2330 +# CONFIG_USB_OTG is not set
2331 +# CONFIG_USB_OTG_WHITELIST is not set
2332 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
2333 +
2334 +#
2335 +# USB Host Controller Drivers
2336 +#
2337 +# CONFIG_USB_C67X00_HCD is not set
2338 +# CONFIG_USB_ISP116X_HCD is not set
2339 +# CONFIG_USB_ISP1760_HCD is not set
2340 +# CONFIG_USB_SL811_HCD is not set
2341 +# CONFIG_USB_R8A66597_HCD is not set
2342 +
2343 +#
2344 +# USB Device Class drivers
2345 +#
2346 +# CONFIG_USB_ACM is not set
2347 +CONFIG_USB_PRINTER=y
2348 +# CONFIG_USB_WDM is not set
2349 +
2350 +#
2351 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
2352 +#
2353 +
2354 +#
2355 +# may also be needed; see USB_STORAGE Help for more information
2356 +#
2357 +CONFIG_USB_STORAGE=y
2358 +# CONFIG_USB_STORAGE_DEBUG is not set
2359 +CONFIG_USB_STORAGE_DATAFAB=y
2360 +CONFIG_USB_STORAGE_FREECOM=y
2361 +# CONFIG_USB_STORAGE_ISD200 is not set
2362 +CONFIG_USB_STORAGE_DPCM=y
2363 +# CONFIG_USB_STORAGE_USBAT is not set
2364 +CONFIG_USB_STORAGE_SDDR09=y
2365 +CONFIG_USB_STORAGE_SDDR55=y
2366 +CONFIG_USB_STORAGE_JUMPSHOT=y
2367 +# CONFIG_USB_STORAGE_ALAUDA is not set
2368 +# CONFIG_USB_STORAGE_ONETOUCH is not set
2369 +# CONFIG_USB_STORAGE_KARMA is not set
2370 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2371 +# CONFIG_USB_LIBUSUAL is not set
2372 +
2373 +#
2374 +# USB Imaging devices
2375 +#
2376 +# CONFIG_USB_MDC800 is not set
2377 +# CONFIG_USB_MICROTEK is not set
2378 +# CONFIG_USB_MON is not set
2379 +
2380 +#
2381 +# USB port drivers
2382 +#
2383 +# CONFIG_USB_SERIAL is not set
2384 +
2385 +#
2386 +# USB Miscellaneous drivers
2387 +#
2388 +# CONFIG_USB_EMI62 is not set
2389 +# CONFIG_USB_EMI26 is not set
2390 +# CONFIG_USB_ADUTUX is not set
2391 +# CONFIG_USB_AUERSWALD is not set
2392 +# CONFIG_USB_RIO500 is not set
2393 +# CONFIG_USB_LEGOTOWER is not set
2394 +# CONFIG_USB_LCD is not set
2395 +# CONFIG_USB_BERRY_CHARGE is not set
2396 +# CONFIG_USB_LED is not set
2397 +# CONFIG_USB_CYPRESS_CY7C63 is not set
2398 +# CONFIG_USB_CYTHERM is not set
2399 +# CONFIG_USB_PHIDGET is not set
2400 +# CONFIG_USB_IDMOUSE is not set
2401 +# CONFIG_USB_FTDI_ELAN is not set
2402 +# CONFIG_USB_APPLEDISPLAY is not set
2403 +# CONFIG_USB_LD is not set
2404 +# CONFIG_USB_TRANCEVIBRATOR is not set
2405 +# CONFIG_USB_IOWARRIOR is not set
2406 +# CONFIG_USB_TEST is not set
2407 +# CONFIG_USB_ISIGHTFW is not set
2408 +# CONFIG_USB_GADGET is not set
2409 +# CONFIG_MMC is not set
2410 +CONFIG_NEW_LEDS=y
2411 +# CONFIG_LEDS_CLASS is not set
2412 +
2413 +#
2414 +# LED drivers
2415 +#
2416 +
2417 +#
2418 +# LED Triggers
2419 +#
2420 +# CONFIG_LEDS_TRIGGERS is not set
2421 +CONFIG_RTC_LIB=y
2422 +# CONFIG_RTC_CLASS is not set
2423 +# CONFIG_UIO is not set
2424 +
2425 +#
2426 +# File systems
2427 +#
2428 +CONFIG_EXT2_FS=y
2429 +# CONFIG_EXT2_FS_XATTR is not set
2430 +# CONFIG_EXT2_FS_XIP is not set
2431 +CONFIG_EXT3_FS=y
2432 +# CONFIG_EXT3_FS_XATTR is not set
2433 +# CONFIG_EXT4DEV_FS is not set
2434 +CONFIG_JBD=y
2435 +# CONFIG_REISERFS_FS is not set
2436 +# CONFIG_JFS_FS is not set
2437 +# CONFIG_FS_POSIX_ACL is not set
2438 +CONFIG_XFS_FS=y
2439 +# CONFIG_XFS_QUOTA is not set
2440 +# CONFIG_XFS_POSIX_ACL is not set
2441 +# CONFIG_XFS_RT is not set
2442 +# CONFIG_XFS_DEBUG is not set
2443 +# CONFIG_OCFS2_FS is not set
2444 +CONFIG_DNOTIFY=y
2445 +CONFIG_INOTIFY=y
2446 +CONFIG_INOTIFY_USER=y
2447 +# CONFIG_QUOTA is not set
2448 +# CONFIG_AUTOFS_FS is not set
2449 +# CONFIG_AUTOFS4_FS is not set
2450 +# CONFIG_FUSE_FS is not set
2451 +
2452 +#
2453 +# CD-ROM/DVD Filesystems
2454 +#
2455 +CONFIG_ISO9660_FS=y
2456 +# CONFIG_JOLIET is not set
2457 +# CONFIG_ZISOFS is not set
2458 +CONFIG_UDF_FS=m
2459 +CONFIG_UDF_NLS=y
2460 +
2461 +#
2462 +# DOS/FAT/NT Filesystems
2463 +#
2464 +CONFIG_FAT_FS=y
2465 +CONFIG_MSDOS_FS=y
2466 +CONFIG_VFAT_FS=y
2467 +CONFIG_FAT_DEFAULT_CODEPAGE=437
2468 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2469 +# CONFIG_NTFS_FS is not set
2470 +
2471 +#
2472 +# Pseudo filesystems
2473 +#
2474 +CONFIG_PROC_FS=y
2475 +CONFIG_PROC_SYSCTL=y
2476 +CONFIG_SYSFS=y
2477 +CONFIG_TMPFS=y
2478 +# CONFIG_TMPFS_POSIX_ACL is not set
2479 +# CONFIG_HUGETLB_PAGE is not set
2480 +# CONFIG_CONFIGFS_FS is not set
2481 +
2482 +#
2483 +# Miscellaneous filesystems
2484 +#
2485 +# CONFIG_ADFS_FS is not set
2486 +# CONFIG_AFFS_FS is not set
2487 +# CONFIG_HFS_FS is not set
2488 +# CONFIG_HFSPLUS_FS is not set
2489 +# CONFIG_BEFS_FS is not set
2490 +# CONFIG_BFS_FS is not set
2491 +# CONFIG_EFS_FS is not set
2492 +CONFIG_JFFS2_FS=y
2493 +CONFIG_JFFS2_FS_DEBUG=0
2494 +CONFIG_JFFS2_FS_WRITEBUFFER=y
2495 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
2496 +# CONFIG_JFFS2_SUMMARY is not set
2497 +# CONFIG_JFFS2_FS_XATTR is not set
2498 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2499 +CONFIG_JFFS2_ZLIB=y
2500 +# CONFIG_JFFS2_LZO is not set
2501 +CONFIG_JFFS2_RTIME=y
2502 +# CONFIG_JFFS2_RUBIN is not set
2503 +CONFIG_CRAMFS=y
2504 +# CONFIG_VXFS_FS is not set
2505 +# CONFIG_MINIX_FS is not set
2506 +# CONFIG_HPFS_FS is not set
2507 +# CONFIG_QNX4FS_FS is not set
2508 +# CONFIG_ROMFS_FS is not set
2509 +# CONFIG_SYSV_FS is not set
2510 +# CONFIG_UFS_FS is not set
2511 +CONFIG_NETWORK_FILESYSTEMS=y
2512 +CONFIG_NFS_FS=y
2513 +CONFIG_NFS_V3=y
2514 +# CONFIG_NFS_V3_ACL is not set
2515 +# CONFIG_NFS_V4 is not set
2516 +# CONFIG_NFSD is not set
2517 +CONFIG_ROOT_NFS=y
2518 +CONFIG_LOCKD=y
2519 +CONFIG_LOCKD_V4=y
2520 +CONFIG_NFS_COMMON=y
2521 +CONFIG_SUNRPC=y
2522 +# CONFIG_SUNRPC_BIND34 is not set
2523 +# CONFIG_RPCSEC_GSS_KRB5 is not set
2524 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
2525 +# CONFIG_SMB_FS is not set
2526 +# CONFIG_CIFS is not set
2527 +# CONFIG_NCP_FS is not set
2528 +# CONFIG_CODA_FS is not set
2529 +# CONFIG_AFS_FS is not set
2530 +
2531 +#
2532 +# Partition Types
2533 +#
2534 +CONFIG_PARTITION_ADVANCED=y
2535 +# CONFIG_ACORN_PARTITION is not set
2536 +# CONFIG_OSF_PARTITION is not set
2537 +# CONFIG_AMIGA_PARTITION is not set
2538 +# CONFIG_ATARI_PARTITION is not set
2539 +# CONFIG_MAC_PARTITION is not set
2540 +CONFIG_MSDOS_PARTITION=y
2541 +CONFIG_BSD_DISKLABEL=y
2542 +CONFIG_MINIX_SUBPARTITION=y
2543 +CONFIG_SOLARIS_X86_PARTITION=y
2544 +CONFIG_UNIXWARE_DISKLABEL=y
2545 +CONFIG_LDM_PARTITION=y
2546 +CONFIG_LDM_DEBUG=y
2547 +# CONFIG_SGI_PARTITION is not set
2548 +# CONFIG_ULTRIX_PARTITION is not set
2549 +CONFIG_SUN_PARTITION=y
2550 +# CONFIG_KARMA_PARTITION is not set
2551 +# CONFIG_EFI_PARTITION is not set
2552 +# CONFIG_SYSV68_PARTITION is not set
2553 +CONFIG_NLS=y
2554 +CONFIG_NLS_DEFAULT="iso8859-1"
2555 +CONFIG_NLS_CODEPAGE_437=y
2556 +# CONFIG_NLS_CODEPAGE_737 is not set
2557 +# CONFIG_NLS_CODEPAGE_775 is not set
2558 +CONFIG_NLS_CODEPAGE_850=y
2559 +# CONFIG_NLS_CODEPAGE_852 is not set
2560 +# CONFIG_NLS_CODEPAGE_855 is not set
2561 +# CONFIG_NLS_CODEPAGE_857 is not set
2562 +# CONFIG_NLS_CODEPAGE_860 is not set
2563 +# CONFIG_NLS_CODEPAGE_861 is not set
2564 +# CONFIG_NLS_CODEPAGE_862 is not set
2565 +# CONFIG_NLS_CODEPAGE_863 is not set
2566 +# CONFIG_NLS_CODEPAGE_864 is not set
2567 +# CONFIG_NLS_CODEPAGE_865 is not set
2568 +# CONFIG_NLS_CODEPAGE_866 is not set
2569 +# CONFIG_NLS_CODEPAGE_869 is not set
2570 +# CONFIG_NLS_CODEPAGE_936 is not set
2571 +# CONFIG_NLS_CODEPAGE_950 is not set
2572 +# CONFIG_NLS_CODEPAGE_932 is not set
2573 +# CONFIG_NLS_CODEPAGE_949 is not set
2574 +# CONFIG_NLS_CODEPAGE_874 is not set
2575 +# CONFIG_NLS_ISO8859_8 is not set
2576 +# CONFIG_NLS_CODEPAGE_1250 is not set
2577 +# CONFIG_NLS_CODEPAGE_1251 is not set
2578 +# CONFIG_NLS_ASCII is not set
2579 +CONFIG_NLS_ISO8859_1=y
2580 +CONFIG_NLS_ISO8859_2=y
2581 +# CONFIG_NLS_ISO8859_3 is not set
2582 +# CONFIG_NLS_ISO8859_4 is not set
2583 +# CONFIG_NLS_ISO8859_5 is not set
2584 +# CONFIG_NLS_ISO8859_6 is not set
2585 +# CONFIG_NLS_ISO8859_7 is not set
2586 +# CONFIG_NLS_ISO8859_9 is not set
2587 +# CONFIG_NLS_ISO8859_13 is not set
2588 +# CONFIG_NLS_ISO8859_14 is not set
2589 +# CONFIG_NLS_ISO8859_15 is not set
2590 +# CONFIG_NLS_KOI8_R is not set
2591 +# CONFIG_NLS_KOI8_U is not set
2592 +# CONFIG_NLS_UTF8 is not set
2593 +# CONFIG_DLM is not set
2594 +
2595 +#
2596 +# Kernel hacking
2597 +#
2598 +# CONFIG_PRINTK_TIME is not set
2599 +CONFIG_ENABLE_WARN_DEPRECATED=y
2600 +CONFIG_ENABLE_MUST_CHECK=y
2601 +CONFIG_FRAME_WARN=1024
2602 +CONFIG_MAGIC_SYSRQ=y
2603 +# CONFIG_UNUSED_SYMBOLS is not set
2604 +# CONFIG_DEBUG_FS is not set
2605 +# CONFIG_HEADERS_CHECK is not set
2606 +# CONFIG_DEBUG_KERNEL is not set
2607 +# CONFIG_DEBUG_BUGVERBOSE is not set
2608 +CONFIG_FRAME_POINTER=y
2609 +# CONFIG_LATENCYTOP is not set
2610 +# CONFIG_SAMPLES is not set
2611 +CONFIG_DEBUG_USER=y
2612 +
2613 +#
2614 +# Security options
2615 +#
2616 +# CONFIG_KEYS is not set
2617 +# CONFIG_SECURITY is not set
2618 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2619 +CONFIG_CRYPTO=y
2620 +
2621 +#
2622 +# Crypto core or helper
2623 +#
2624 +CONFIG_CRYPTO_ALGAPI=m
2625 +CONFIG_CRYPTO_BLKCIPHER=m
2626 +CONFIG_CRYPTO_MANAGER=m
2627 +# CONFIG_CRYPTO_GF128MUL is not set
2628 +# CONFIG_CRYPTO_NULL is not set
2629 +# CONFIG_CRYPTO_CRYPTD is not set
2630 +# CONFIG_CRYPTO_AUTHENC is not set
2631 +# CONFIG_CRYPTO_TEST is not set
2632 +
2633 +#
2634 +# Authenticated Encryption with Associated Data
2635 +#
2636 +# CONFIG_CRYPTO_CCM is not set
2637 +# CONFIG_CRYPTO_GCM is not set
2638 +# CONFIG_CRYPTO_SEQIV is not set
2639 +
2640 +#
2641 +# Block modes
2642 +#
2643 +CONFIG_CRYPTO_CBC=m
2644 +# CONFIG_CRYPTO_CTR is not set
2645 +# CONFIG_CRYPTO_CTS is not set
2646 +CONFIG_CRYPTO_ECB=m
2647 +# CONFIG_CRYPTO_LRW is not set
2648 +CONFIG_CRYPTO_PCBC=m
2649 +# CONFIG_CRYPTO_XTS is not set
2650 +
2651 +#
2652 +# Hash modes
2653 +#
2654 +# CONFIG_CRYPTO_HMAC is not set
2655 +# CONFIG_CRYPTO_XCBC is not set
2656 +
2657 +#
2658 +# Digest
2659 +#
2660 +# CONFIG_CRYPTO_CRC32C is not set
2661 +# CONFIG_CRYPTO_MD4 is not set
2662 +# CONFIG_CRYPTO_MD5 is not set
2663 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
2664 +# CONFIG_CRYPTO_SHA1 is not set
2665 +# CONFIG_CRYPTO_SHA256 is not set
2666 +# CONFIG_CRYPTO_SHA512 is not set
2667 +# CONFIG_CRYPTO_TGR192 is not set
2668 +# CONFIG_CRYPTO_WP512 is not set
2669 +
2670 +#
2671 +# Ciphers
2672 +#
2673 +# CONFIG_CRYPTO_AES is not set
2674 +# CONFIG_CRYPTO_ANUBIS is not set
2675 +# CONFIG_CRYPTO_ARC4 is not set
2676 +# CONFIG_CRYPTO_BLOWFISH is not set
2677 +# CONFIG_CRYPTO_CAMELLIA is not set
2678 +# CONFIG_CRYPTO_CAST5 is not set
2679 +# CONFIG_CRYPTO_CAST6 is not set
2680 +# CONFIG_CRYPTO_DES is not set
2681 +# CONFIG_CRYPTO_FCRYPT is not set
2682 +# CONFIG_CRYPTO_KHAZAD is not set
2683 +# CONFIG_CRYPTO_SALSA20 is not set
2684 +# CONFIG_CRYPTO_SEED is not set
2685 +# CONFIG_CRYPTO_SERPENT is not set
2686 +# CONFIG_CRYPTO_TEA is not set
2687 +# CONFIG_CRYPTO_TWOFISH is not set
2688 +
2689 +#
2690 +# Compression
2691 +#
2692 +# CONFIG_CRYPTO_DEFLATE is not set
2693 +# CONFIG_CRYPTO_LZO is not set
2694 +CONFIG_CRYPTO_HW=y
2695 +
2696 +#
2697 +# Library routines
2698 +#
2699 +CONFIG_BITREVERSE=y
2700 +# CONFIG_GENERIC_FIND_FIRST_BIT is not set
2701 +# CONFIG_GENERIC_FIND_NEXT_BIT is not set
2702 +CONFIG_CRC_CCITT=y
2703 +CONFIG_CRC16=y
2704 +CONFIG_CRC_ITU_T=m
2705 +CONFIG_CRC32=y
2706 +# CONFIG_CRC7 is not set
2707 +CONFIG_LIBCRC32C=y
2708 +CONFIG_ZLIB_INFLATE=y
2709 +CONFIG_ZLIB_DEFLATE=y
2710 +CONFIG_PLIST=y
2711 +CONFIG_HAS_IOMEM=y
2712 +CONFIG_HAS_IOPORT=y
2713 +CONFIG_HAS_DMA=y
2714 --- /dev/null
2715 +++ b/arch/arm/configs/mv78xx0_defconfig
2716 @@ -0,0 +1,1445 @@
2717 +#
2718 +# Automatically generated make config: don't edit
2719 +# Linux kernel version: 2.6.26-rc5
2720 +# Fri Jun 13 02:57:32 2008
2721 +#
2722 +CONFIG_ARM=y
2723 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
2724 +# CONFIG_GENERIC_GPIO is not set
2725 +CONFIG_GENERIC_TIME=y
2726 +CONFIG_GENERIC_CLOCKEVENTS=y
2727 +CONFIG_MMU=y
2728 +# CONFIG_NO_IOPORT is not set
2729 +CONFIG_GENERIC_HARDIRQS=y
2730 +CONFIG_STACKTRACE_SUPPORT=y
2731 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
2732 +CONFIG_LOCKDEP_SUPPORT=y
2733 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2734 +CONFIG_HARDIRQS_SW_RESEND=y
2735 +CONFIG_GENERIC_IRQ_PROBE=y
2736 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2737 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2738 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2739 +CONFIG_GENERIC_HWEIGHT=y
2740 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2741 +CONFIG_ARCH_SUPPORTS_AOUT=y
2742 +CONFIG_ZONE_DMA=y
2743 +CONFIG_VECTORS_BASE=0xffff0000
2744 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2745 +
2746 +#
2747 +# General setup
2748 +#
2749 +CONFIG_EXPERIMENTAL=y
2750 +CONFIG_BROKEN_ON_SMP=y
2751 +CONFIG_LOCK_KERNEL=y
2752 +CONFIG_INIT_ENV_ARG_LIMIT=32
2753 +CONFIG_LOCALVERSION=""
2754 +CONFIG_LOCALVERSION_AUTO=y
2755 +CONFIG_SWAP=y
2756 +CONFIG_SYSVIPC=y
2757 +CONFIG_SYSVIPC_SYSCTL=y
2758 +# CONFIG_POSIX_MQUEUE is not set
2759 +# CONFIG_BSD_PROCESS_ACCT is not set
2760 +# CONFIG_TASKSTATS is not set
2761 +# CONFIG_AUDIT is not set
2762 +# CONFIG_IKCONFIG is not set
2763 +CONFIG_LOG_BUF_SHIFT=14
2764 +# CONFIG_CGROUPS is not set
2765 +# CONFIG_GROUP_SCHED is not set
2766 +CONFIG_SYSFS_DEPRECATED=y
2767 +CONFIG_SYSFS_DEPRECATED_V2=y
2768 +# CONFIG_RELAY is not set
2769 +# CONFIG_NAMESPACES is not set
2770 +# CONFIG_BLK_DEV_INITRD is not set
2771 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2772 +CONFIG_SYSCTL=y
2773 +CONFIG_EMBEDDED=y
2774 +CONFIG_UID16=y
2775 +CONFIG_SYSCTL_SYSCALL=y
2776 +CONFIG_SYSCTL_SYSCALL_CHECK=y
2777 +CONFIG_KALLSYMS=y
2778 +CONFIG_KALLSYMS_ALL=y
2779 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2780 +CONFIG_HOTPLUG=y
2781 +CONFIG_PRINTK=y
2782 +CONFIG_BUG=y
2783 +CONFIG_ELF_CORE=y
2784 +CONFIG_COMPAT_BRK=y
2785 +CONFIG_BASE_FULL=y
2786 +CONFIG_FUTEX=y
2787 +CONFIG_ANON_INODES=y
2788 +CONFIG_EPOLL=y
2789 +CONFIG_SIGNALFD=y
2790 +CONFIG_TIMERFD=y
2791 +CONFIG_EVENTFD=y
2792 +CONFIG_SHMEM=y
2793 +CONFIG_VM_EVENT_COUNTERS=y
2794 +# CONFIG_SLUB_DEBUG is not set
2795 +# CONFIG_SLAB is not set
2796 +CONFIG_SLUB=y
2797 +# CONFIG_SLOB is not set
2798 +CONFIG_PROFILING=y
2799 +# CONFIG_MARKERS is not set
2800 +CONFIG_OPROFILE=y
2801 +CONFIG_HAVE_OPROFILE=y
2802 +CONFIG_KPROBES=y
2803 +CONFIG_KRETPROBES=y
2804 +CONFIG_HAVE_KPROBES=y
2805 +CONFIG_HAVE_KRETPROBES=y
2806 +# CONFIG_HAVE_DMA_ATTRS is not set
2807 +CONFIG_PROC_PAGE_MONITOR=y
2808 +CONFIG_RT_MUTEXES=y
2809 +# CONFIG_TINY_SHMEM is not set
2810 +CONFIG_BASE_SMALL=0
2811 +CONFIG_MODULES=y
2812 +# CONFIG_MODULE_FORCE_LOAD is not set
2813 +CONFIG_MODULE_UNLOAD=y
2814 +# CONFIG_MODULE_FORCE_UNLOAD is not set
2815 +# CONFIG_MODVERSIONS is not set
2816 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2817 +# CONFIG_KMOD is not set
2818 +CONFIG_BLOCK=y
2819 +# CONFIG_LBD is not set
2820 +# CONFIG_BLK_DEV_IO_TRACE is not set
2821 +# CONFIG_LSF is not set
2822 +# CONFIG_BLK_DEV_BSG is not set
2823 +
2824 +#
2825 +# IO Schedulers
2826 +#
2827 +CONFIG_IOSCHED_NOOP=y
2828 +CONFIG_IOSCHED_AS=y
2829 +CONFIG_IOSCHED_DEADLINE=y
2830 +CONFIG_IOSCHED_CFQ=y
2831 +# CONFIG_DEFAULT_AS is not set
2832 +# CONFIG_DEFAULT_DEADLINE is not set
2833 +CONFIG_DEFAULT_CFQ=y
2834 +# CONFIG_DEFAULT_NOOP is not set
2835 +CONFIG_DEFAULT_IOSCHED="cfq"
2836 +CONFIG_CLASSIC_RCU=y
2837 +
2838 +#
2839 +# System Type
2840 +#
2841 +# CONFIG_ARCH_AAEC2000 is not set
2842 +# CONFIG_ARCH_INTEGRATOR is not set
2843 +# CONFIG_ARCH_REALVIEW is not set
2844 +# CONFIG_ARCH_VERSATILE is not set
2845 +# CONFIG_ARCH_AT91 is not set
2846 +# CONFIG_ARCH_CLPS7500 is not set
2847 +# CONFIG_ARCH_CLPS711X is not set
2848 +# CONFIG_ARCH_CO285 is not set
2849 +# CONFIG_ARCH_EBSA110 is not set
2850 +# CONFIG_ARCH_EP93XX is not set
2851 +# CONFIG_ARCH_FOOTBRIDGE is not set
2852 +# CONFIG_ARCH_NETX is not set
2853 +# CONFIG_ARCH_H720X is not set
2854 +# CONFIG_ARCH_IMX is not set
2855 +# CONFIG_ARCH_IOP13XX is not set
2856 +# CONFIG_ARCH_IOP32X is not set
2857 +# CONFIG_ARCH_IOP33X is not set
2858 +# CONFIG_ARCH_IXP23XX is not set
2859 +# CONFIG_ARCH_IXP2000 is not set
2860 +# CONFIG_ARCH_IXP4XX is not set
2861 +# CONFIG_ARCH_L7200 is not set
2862 +# CONFIG_ARCH_KIRKWOOD is not set
2863 +# CONFIG_ARCH_KS8695 is not set
2864 +# CONFIG_ARCH_NS9XXX is not set
2865 +# CONFIG_ARCH_LOKI is not set
2866 +CONFIG_ARCH_MV78XX0=y
2867 +# CONFIG_ARCH_MXC is not set
2868 +# CONFIG_ARCH_ORION5X is not set
2869 +# CONFIG_ARCH_PNX4008 is not set
2870 +# CONFIG_ARCH_PXA is not set
2871 +# CONFIG_ARCH_RPC is not set
2872 +# CONFIG_ARCH_SA1100 is not set
2873 +# CONFIG_ARCH_S3C2410 is not set
2874 +# CONFIG_ARCH_SHARK is not set
2875 +# CONFIG_ARCH_LH7A40X is not set
2876 +# CONFIG_ARCH_DAVINCI is not set
2877 +# CONFIG_ARCH_OMAP is not set
2878 +# CONFIG_ARCH_MSM7X00A is not set
2879 +
2880 +#
2881 +# Marvell MV78xx0 Implementations
2882 +#
2883 +CONFIG_MACH_DB78X00_BP=y
2884 +
2885 +#
2886 +# Boot options
2887 +#
2888 +
2889 +#
2890 +# Power management
2891 +#
2892 +CONFIG_PLAT_ORION=y
2893 +
2894 +#
2895 +# Processor Type
2896 +#
2897 +CONFIG_CPU_32=y
2898 +CONFIG_CPU_FEROCEON=y
2899 +CONFIG_CPU_FEROCEON_OLD_ID=y
2900 +CONFIG_CPU_32v5=y
2901 +CONFIG_CPU_ABRT_EV5T=y
2902 +CONFIG_CPU_PABRT_NOIFAR=y
2903 +CONFIG_CPU_CACHE_VIVT=y
2904 +CONFIG_CPU_COPY_FEROCEON=y
2905 +CONFIG_CPU_TLB_FEROCEON=y
2906 +CONFIG_CPU_CP15=y
2907 +CONFIG_CPU_CP15_MMU=y
2908 +
2909 +#
2910 +# Processor Features
2911 +#
2912 +CONFIG_ARM_THUMB=y
2913 +# CONFIG_CPU_ICACHE_DISABLE is not set
2914 +# CONFIG_CPU_DCACHE_DISABLE is not set
2915 +CONFIG_OUTER_CACHE=y
2916 +CONFIG_CACHE_FEROCEON_L2=y
2917 +
2918 +#
2919 +# Bus support
2920 +#
2921 +CONFIG_PCI=y
2922 +CONFIG_PCI_SYSCALL=y
2923 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2924 +CONFIG_PCI_LEGACY=y
2925 +# CONFIG_PCI_DEBUG is not set
2926 +# CONFIG_PCCARD is not set
2927 +
2928 +#
2929 +# Kernel Features
2930 +#
2931 +CONFIG_TICK_ONESHOT=y
2932 +CONFIG_NO_HZ=y
2933 +CONFIG_HIGH_RES_TIMERS=y
2934 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2935 +CONFIG_PREEMPT=y
2936 +CONFIG_HZ=100
2937 +CONFIG_AEABI=y
2938 +CONFIG_OABI_COMPAT=y
2939 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
2940 +CONFIG_SELECT_MEMORY_MODEL=y
2941 +CONFIG_FLATMEM_MANUAL=y
2942 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2943 +# CONFIG_SPARSEMEM_MANUAL is not set
2944 +CONFIG_FLATMEM=y
2945 +CONFIG_FLAT_NODE_MEM_MAP=y
2946 +# CONFIG_SPARSEMEM_STATIC is not set
2947 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
2948 +CONFIG_PAGEFLAGS_EXTENDED=y
2949 +CONFIG_SPLIT_PTLOCK_CPUS=4096
2950 +# CONFIG_RESOURCES_64BIT is not set
2951 +CONFIG_ZONE_DMA_FLAG=1
2952 +CONFIG_BOUNCE=y
2953 +CONFIG_VIRT_TO_BUS=y
2954 +CONFIG_ALIGNMENT_TRAP=y
2955 +
2956 +#
2957 +# Boot options
2958 +#
2959 +CONFIG_ZBOOT_ROM_TEXT=0x0
2960 +CONFIG_ZBOOT_ROM_BSS=0x0
2961 +CONFIG_CMDLINE=""
2962 +# CONFIG_XIP_KERNEL is not set
2963 +# CONFIG_KEXEC is not set
2964 +
2965 +#
2966 +# Floating point emulation
2967 +#
2968 +
2969 +#
2970 +# At least one emulation must be selected
2971 +#
2972 +CONFIG_FPE_NWFPE=y
2973 +# CONFIG_FPE_NWFPE_XP is not set
2974 +# CONFIG_FPE_FASTFPE is not set
2975 +CONFIG_VFP=y
2976 +
2977 +#
2978 +# Userspace binary formats
2979 +#
2980 +CONFIG_BINFMT_ELF=y
2981 +# CONFIG_BINFMT_AOUT is not set
2982 +# CONFIG_BINFMT_MISC is not set
2983 +
2984 +#
2985 +# Power management options
2986 +#
2987 +# CONFIG_PM is not set
2988 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2989 +
2990 +#
2991 +# Networking
2992 +#
2993 +CONFIG_NET=y
2994 +
2995 +#
2996 +# Networking options
2997 +#
2998 +CONFIG_PACKET=y
2999 +CONFIG_PACKET_MMAP=y
3000 +CONFIG_UNIX=y
3001 +CONFIG_XFRM=y
3002 +# CONFIG_XFRM_USER is not set
3003 +# CONFIG_XFRM_SUB_POLICY is not set
3004 +# CONFIG_XFRM_MIGRATE is not set
3005 +# CONFIG_XFRM_STATISTICS is not set
3006 +# CONFIG_NET_KEY is not set
3007 +CONFIG_INET=y
3008 +CONFIG_IP_MULTICAST=y
3009 +# CONFIG_IP_ADVANCED_ROUTER is not set
3010 +CONFIG_IP_FIB_HASH=y
3011 +CONFIG_IP_PNP=y
3012 +CONFIG_IP_PNP_DHCP=y
3013 +CONFIG_IP_PNP_BOOTP=y
3014 +# CONFIG_IP_PNP_RARP is not set
3015 +# CONFIG_NET_IPIP is not set
3016 +# CONFIG_NET_IPGRE is not set
3017 +# CONFIG_IP_MROUTE is not set
3018 +# CONFIG_ARPD is not set
3019 +# CONFIG_SYN_COOKIES is not set
3020 +# CONFIG_INET_AH is not set
3021 +# CONFIG_INET_ESP is not set
3022 +# CONFIG_INET_IPCOMP is not set
3023 +# CONFIG_INET_XFRM_TUNNEL is not set
3024 +# CONFIG_INET_TUNNEL is not set
3025 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
3026 +CONFIG_INET_XFRM_MODE_TUNNEL=y
3027 +CONFIG_INET_XFRM_MODE_BEET=y
3028 +# CONFIG_INET_LRO is not set
3029 +CONFIG_INET_DIAG=y
3030 +CONFIG_INET_TCP_DIAG=y
3031 +# CONFIG_TCP_CONG_ADVANCED is not set
3032 +CONFIG_TCP_CONG_CUBIC=y
3033 +CONFIG_DEFAULT_TCP_CONG="cubic"
3034 +# CONFIG_TCP_MD5SIG is not set
3035 +# CONFIG_IPV6 is not set
3036 +# CONFIG_NETWORK_SECMARK is not set
3037 +# CONFIG_NETFILTER is not set
3038 +# CONFIG_IP_DCCP is not set
3039 +# CONFIG_IP_SCTP is not set
3040 +# CONFIG_TIPC is not set
3041 +# CONFIG_ATM is not set
3042 +# CONFIG_BRIDGE is not set
3043 +# CONFIG_VLAN_8021Q is not set
3044 +# CONFIG_DECNET is not set
3045 +# CONFIG_LLC2 is not set
3046 +# CONFIG_IPX is not set
3047 +# CONFIG_ATALK is not set
3048 +# CONFIG_X25 is not set
3049 +# CONFIG_LAPB is not set
3050 +# CONFIG_ECONET is not set
3051 +# CONFIG_WAN_ROUTER is not set
3052 +# CONFIG_NET_SCHED is not set
3053 +
3054 +#
3055 +# Network testing
3056 +#
3057 +CONFIG_NET_PKTGEN=m
3058 +# CONFIG_NET_TCPPROBE is not set
3059 +# CONFIG_HAMRADIO is not set
3060 +# CONFIG_CAN is not set
3061 +# CONFIG_IRDA is not set
3062 +# CONFIG_BT is not set
3063 +# CONFIG_AF_RXRPC is not set
3064 +
3065 +#
3066 +# Wireless
3067 +#
3068 +# CONFIG_CFG80211 is not set
3069 +CONFIG_WIRELESS_EXT=y
3070 +# CONFIG_MAC80211 is not set
3071 +# CONFIG_IEEE80211 is not set
3072 +# CONFIG_RFKILL is not set
3073 +# CONFIG_NET_9P is not set
3074 +
3075 +#
3076 +# Device Drivers
3077 +#
3078 +
3079 +#
3080 +# Generic Driver Options
3081 +#
3082 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
3083 +CONFIG_STANDALONE=y
3084 +CONFIG_PREVENT_FIRMWARE_BUILD=y
3085 +CONFIG_FW_LOADER=y
3086 +# CONFIG_DEBUG_DRIVER is not set
3087 +# CONFIG_DEBUG_DEVRES is not set
3088 +# CONFIG_SYS_HYPERVISOR is not set
3089 +# CONFIG_CONNECTOR is not set
3090 +CONFIG_MTD=y
3091 +# CONFIG_MTD_DEBUG is not set
3092 +# CONFIG_MTD_CONCAT is not set
3093 +CONFIG_MTD_PARTITIONS=y
3094 +# CONFIG_MTD_REDBOOT_PARTS is not set
3095 +CONFIG_MTD_CMDLINE_PARTS=y
3096 +# CONFIG_MTD_AFS_PARTS is not set
3097 +# CONFIG_MTD_AR7_PARTS is not set
3098 +
3099 +#
3100 +# User Modules And Translation Layers
3101 +#
3102 +CONFIG_MTD_CHAR=y
3103 +CONFIG_MTD_BLKDEVS=y
3104 +CONFIG_MTD_BLOCK=y
3105 +# CONFIG_FTL is not set
3106 +# CONFIG_NFTL is not set
3107 +# CONFIG_INFTL is not set
3108 +# CONFIG_RFD_FTL is not set
3109 +# CONFIG_SSFDC is not set
3110 +# CONFIG_MTD_OOPS is not set
3111 +
3112 +#
3113 +# RAM/ROM/Flash chip drivers
3114 +#
3115 +CONFIG_MTD_CFI=y
3116 +CONFIG_MTD_JEDECPROBE=y
3117 +CONFIG_MTD_GEN_PROBE=y
3118 +CONFIG_MTD_CFI_ADV_OPTIONS=y
3119 +CONFIG_MTD_CFI_NOSWAP=y
3120 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
3121 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
3122 +CONFIG_MTD_CFI_GEOMETRY=y
3123 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
3124 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
3125 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
3126 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
3127 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
3128 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
3129 +CONFIG_MTD_CFI_I1=y
3130 +CONFIG_MTD_CFI_I2=y
3131 +# CONFIG_MTD_CFI_I4 is not set
3132 +# CONFIG_MTD_CFI_I8 is not set
3133 +# CONFIG_MTD_OTP is not set
3134 +CONFIG_MTD_CFI_INTELEXT=y
3135 +CONFIG_MTD_CFI_AMDSTD=y
3136 +# CONFIG_MTD_CFI_STAA is not set
3137 +CONFIG_MTD_CFI_UTIL=y
3138 +# CONFIG_MTD_RAM is not set
3139 +# CONFIG_MTD_ROM is not set
3140 +# CONFIG_MTD_ABSENT is not set
3141 +
3142 +#
3143 +# Mapping drivers for chip access
3144 +#
3145 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
3146 +CONFIG_MTD_PHYSMAP=y
3147 +CONFIG_MTD_PHYSMAP_START=0x0
3148 +CONFIG_MTD_PHYSMAP_LEN=0x0
3149 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0
3150 +# CONFIG_MTD_ARM_INTEGRATOR is not set
3151 +# CONFIG_MTD_IMPA7 is not set
3152 +# CONFIG_MTD_INTEL_VR_NOR is not set
3153 +# CONFIG_MTD_PLATRAM is not set
3154 +
3155 +#
3156 +# Self-contained MTD device drivers
3157 +#
3158 +# CONFIG_MTD_PMC551 is not set
3159 +# CONFIG_MTD_SLRAM is not set
3160 +# CONFIG_MTD_PHRAM is not set
3161 +# CONFIG_MTD_MTDRAM is not set
3162 +# CONFIG_MTD_BLOCK2MTD is not set
3163 +
3164 +#
3165 +# Disk-On-Chip Device Drivers
3166 +#
3167 +# CONFIG_MTD_DOC2000 is not set
3168 +# CONFIG_MTD_DOC2001 is not set
3169 +# CONFIG_MTD_DOC2001PLUS is not set
3170 +CONFIG_MTD_NAND=y
3171 +CONFIG_MTD_NAND_VERIFY_WRITE=y
3172 +# CONFIG_MTD_NAND_ECC_SMC is not set
3173 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
3174 +CONFIG_MTD_NAND_IDS=y
3175 +# CONFIG_MTD_NAND_DISKONCHIP is not set
3176 +# CONFIG_MTD_NAND_CAFE is not set
3177 +# CONFIG_MTD_NAND_NANDSIM is not set
3178 +# CONFIG_MTD_NAND_PLATFORM is not set
3179 +# CONFIG_MTD_ALAUDA is not set
3180 +CONFIG_MTD_NAND_ORION=y
3181 +# CONFIG_MTD_ONENAND is not set
3182 +
3183 +#
3184 +# UBI - Unsorted block images
3185 +#
3186 +# CONFIG_MTD_UBI is not set
3187 +# CONFIG_PARPORT is not set
3188 +CONFIG_BLK_DEV=y
3189 +# CONFIG_BLK_CPQ_DA is not set
3190 +# CONFIG_BLK_CPQ_CISS_DA is not set
3191 +# CONFIG_BLK_DEV_DAC960 is not set
3192 +# CONFIG_BLK_DEV_UMEM is not set
3193 +# CONFIG_BLK_DEV_COW_COMMON is not set
3194 +CONFIG_BLK_DEV_LOOP=y
3195 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
3196 +# CONFIG_BLK_DEV_NBD is not set
3197 +# CONFIG_BLK_DEV_SX8 is not set
3198 +# CONFIG_BLK_DEV_UB is not set
3199 +# CONFIG_BLK_DEV_RAM is not set
3200 +# CONFIG_CDROM_PKTCDVD is not set
3201 +# CONFIG_ATA_OVER_ETH is not set
3202 +CONFIG_MISC_DEVICES=y
3203 +# CONFIG_PHANTOM is not set
3204 +# CONFIG_EEPROM_93CX6 is not set
3205 +# CONFIG_SGI_IOC4 is not set
3206 +# CONFIG_TIFM_CORE is not set
3207 +# CONFIG_ENCLOSURE_SERVICES is not set
3208 +CONFIG_HAVE_IDE=y
3209 +# CONFIG_IDE is not set
3210 +
3211 +#
3212 +# SCSI device support
3213 +#
3214 +# CONFIG_RAID_ATTRS is not set
3215 +CONFIG_SCSI=y
3216 +CONFIG_SCSI_DMA=y
3217 +# CONFIG_SCSI_TGT is not set
3218 +# CONFIG_SCSI_NETLINK is not set
3219 +# CONFIG_SCSI_PROC_FS is not set
3220 +
3221 +#
3222 +# SCSI support type (disk, tape, CD-ROM)
3223 +#
3224 +CONFIG_BLK_DEV_SD=y
3225 +# CONFIG_CHR_DEV_ST is not set
3226 +# CONFIG_CHR_DEV_OSST is not set
3227 +CONFIG_BLK_DEV_SR=m
3228 +# CONFIG_BLK_DEV_SR_VENDOR is not set
3229 +CONFIG_CHR_DEV_SG=m
3230 +# CONFIG_CHR_DEV_SCH is not set
3231 +
3232 +#
3233 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
3234 +#
3235 +# CONFIG_SCSI_MULTI_LUN is not set
3236 +# CONFIG_SCSI_CONSTANTS is not set
3237 +# CONFIG_SCSI_LOGGING is not set
3238 +# CONFIG_SCSI_SCAN_ASYNC is not set
3239 +CONFIG_SCSI_WAIT_SCAN=m
3240 +
3241 +#
3242 +# SCSI Transports
3243 +#
3244 +# CONFIG_SCSI_SPI_ATTRS is not set
3245 +# CONFIG_SCSI_FC_ATTRS is not set
3246 +# CONFIG_SCSI_ISCSI_ATTRS is not set
3247 +# CONFIG_SCSI_SAS_LIBSAS is not set
3248 +# CONFIG_SCSI_SRP_ATTRS is not set
3249 +CONFIG_SCSI_LOWLEVEL=y
3250 +# CONFIG_ISCSI_TCP is not set
3251 +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
3252 +# CONFIG_SCSI_3W_9XXX is not set
3253 +# CONFIG_SCSI_ACARD is not set
3254 +# CONFIG_SCSI_AACRAID is not set
3255 +# CONFIG_SCSI_AIC7XXX is not set
3256 +# CONFIG_SCSI_AIC7XXX_OLD is not set
3257 +# CONFIG_SCSI_AIC79XX is not set
3258 +# CONFIG_SCSI_AIC94XX is not set
3259 +# CONFIG_SCSI_DPT_I2O is not set
3260 +# CONFIG_SCSI_ADVANSYS is not set
3261 +# CONFIG_SCSI_ARCMSR is not set
3262 +# CONFIG_MEGARAID_NEWGEN is not set
3263 +# CONFIG_MEGARAID_LEGACY is not set
3264 +# CONFIG_MEGARAID_SAS is not set
3265 +# CONFIG_SCSI_HPTIOP is not set
3266 +# CONFIG_SCSI_DMX3191D is not set
3267 +# CONFIG_SCSI_FUTURE_DOMAIN is not set
3268 +# CONFIG_SCSI_IPS is not set
3269 +# CONFIG_SCSI_INITIO is not set
3270 +# CONFIG_SCSI_INIA100 is not set
3271 +# CONFIG_SCSI_MVSAS is not set
3272 +# CONFIG_SCSI_STEX is not set
3273 +# CONFIG_SCSI_SYM53C8XX_2 is not set
3274 +# CONFIG_SCSI_IPR is not set
3275 +# CONFIG_SCSI_QLOGIC_1280 is not set
3276 +# CONFIG_SCSI_QLA_FC is not set
3277 +# CONFIG_SCSI_QLA_ISCSI is not set
3278 +# CONFIG_SCSI_LPFC is not set
3279 +# CONFIG_SCSI_DC395x is not set
3280 +# CONFIG_SCSI_DC390T is not set
3281 +# CONFIG_SCSI_NSP32 is not set
3282 +# CONFIG_SCSI_DEBUG is not set
3283 +# CONFIG_SCSI_SRP is not set
3284 +CONFIG_ATA=y
3285 +# CONFIG_ATA_NONSTANDARD is not set
3286 +CONFIG_SATA_PMP=y
3287 +# CONFIG_SATA_AHCI is not set
3288 +# CONFIG_SATA_SIL24 is not set
3289 +CONFIG_ATA_SFF=y
3290 +# CONFIG_SATA_SVW is not set
3291 +# CONFIG_ATA_PIIX is not set
3292 +CONFIG_SATA_MV=y
3293 +# CONFIG_SATA_NV is not set
3294 +# CONFIG_PDC_ADMA is not set
3295 +# CONFIG_SATA_QSTOR is not set
3296 +# CONFIG_SATA_PROMISE is not set
3297 +# CONFIG_SATA_SX4 is not set
3298 +# CONFIG_SATA_SIL is not set
3299 +# CONFIG_SATA_SIS is not set
3300 +# CONFIG_SATA_ULI is not set
3301 +# CONFIG_SATA_VIA is not set
3302 +# CONFIG_SATA_VITESSE is not set
3303 +# CONFIG_SATA_INIC162X is not set
3304 +# CONFIG_PATA_ALI is not set
3305 +# CONFIG_PATA_AMD is not set
3306 +# CONFIG_PATA_ARTOP is not set
3307 +# CONFIG_PATA_ATIIXP is not set
3308 +# CONFIG_PATA_CMD640_PCI is not set
3309 +# CONFIG_PATA_CMD64X is not set
3310 +# CONFIG_PATA_CS5520 is not set
3311 +# CONFIG_PATA_CS5530 is not set
3312 +# CONFIG_PATA_CYPRESS is not set
3313 +# CONFIG_PATA_EFAR is not set
3314 +# CONFIG_ATA_GENERIC is not set
3315 +# CONFIG_PATA_HPT366 is not set
3316 +# CONFIG_PATA_HPT37X is not set
3317 +# CONFIG_PATA_HPT3X2N is not set
3318 +# CONFIG_PATA_HPT3X3 is not set
3319 +# CONFIG_PATA_IT821X is not set
3320 +# CONFIG_PATA_IT8213 is not set
3321 +# CONFIG_PATA_JMICRON is not set
3322 +# CONFIG_PATA_TRIFLEX is not set
3323 +# CONFIG_PATA_MARVELL is not set
3324 +# CONFIG_PATA_MPIIX is not set
3325 +# CONFIG_PATA_OLDPIIX is not set
3326 +# CONFIG_PATA_NETCELL is not set
3327 +# CONFIG_PATA_NINJA32 is not set
3328 +# CONFIG_PATA_NS87410 is not set
3329 +# CONFIG_PATA_NS87415 is not set
3330 +# CONFIG_PATA_OPTI is not set
3331 +# CONFIG_PATA_OPTIDMA is not set
3332 +# CONFIG_PATA_PDC_OLD is not set
3333 +# CONFIG_PATA_RADISYS is not set
3334 +# CONFIG_PATA_RZ1000 is not set
3335 +# CONFIG_PATA_SC1200 is not set
3336 +# CONFIG_PATA_SERVERWORKS is not set
3337 +# CONFIG_PATA_PDC2027X is not set
3338 +# CONFIG_PATA_SIL680 is not set
3339 +# CONFIG_PATA_SIS is not set
3340 +# CONFIG_PATA_VIA is not set
3341 +# CONFIG_PATA_WINBOND is not set
3342 +# CONFIG_PATA_PLATFORM is not set
3343 +# CONFIG_PATA_SCH is not set
3344 +# CONFIG_MD is not set
3345 +# CONFIG_FUSION is not set
3346 +
3347 +#
3348 +# IEEE 1394 (FireWire) support
3349 +#
3350 +# CONFIG_FIREWIRE is not set
3351 +# CONFIG_IEEE1394 is not set
3352 +# CONFIG_I2O is not set
3353 +CONFIG_NETDEVICES=y
3354 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
3355 +# CONFIG_DUMMY is not set
3356 +# CONFIG_BONDING is not set
3357 +# CONFIG_MACVLAN is not set
3358 +# CONFIG_EQUALIZER is not set
3359 +# CONFIG_TUN is not set
3360 +# CONFIG_VETH is not set
3361 +# CONFIG_ARCNET is not set
3362 +# CONFIG_PHYLIB is not set
3363 +CONFIG_NET_ETHERNET=y
3364 +CONFIG_MII=y
3365 +# CONFIG_AX88796 is not set
3366 +# CONFIG_HAPPYMEAL is not set
3367 +# CONFIG_SUNGEM is not set
3368 +# CONFIG_CASSINI is not set
3369 +# CONFIG_NET_VENDOR_3COM is not set
3370 +# CONFIG_SMC91X is not set
3371 +# CONFIG_DM9000 is not set
3372 +# CONFIG_NET_TULIP is not set
3373 +# CONFIG_HP100 is not set
3374 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
3375 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
3376 +# CONFIG_IBM_NEW_EMAC_TAH is not set
3377 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
3378 +CONFIG_NET_PCI=y
3379 +# CONFIG_PCNET32 is not set
3380 +# CONFIG_AMD8111_ETH is not set
3381 +# CONFIG_ADAPTEC_STARFIRE is not set
3382 +# CONFIG_B44 is not set
3383 +# CONFIG_FORCEDETH is not set
3384 +# CONFIG_EEPRO100 is not set
3385 +# CONFIG_E100 is not set
3386 +# CONFIG_FEALNX is not set
3387 +# CONFIG_NATSEMI is not set
3388 +# CONFIG_NE2K_PCI is not set
3389 +# CONFIG_8139CP is not set
3390 +# CONFIG_8139TOO is not set
3391 +# CONFIG_R6040 is not set
3392 +# CONFIG_SIS900 is not set
3393 +# CONFIG_EPIC100 is not set
3394 +# CONFIG_SUNDANCE is not set
3395 +# CONFIG_TLAN is not set
3396 +# CONFIG_VIA_RHINE is not set
3397 +# CONFIG_SC92031 is not set
3398 +CONFIG_NETDEV_1000=y
3399 +# CONFIG_ACENIC is not set
3400 +# CONFIG_DL2K is not set
3401 +# CONFIG_E1000 is not set
3402 +# CONFIG_E1000E is not set
3403 +# CONFIG_E1000E_ENABLED is not set
3404 +# CONFIG_IP1000 is not set
3405 +# CONFIG_IGB is not set
3406 +# CONFIG_NS83820 is not set
3407 +# CONFIG_HAMACHI is not set
3408 +# CONFIG_YELLOWFIN is not set
3409 +# CONFIG_R8169 is not set
3410 +# CONFIG_SIS190 is not set
3411 +# CONFIG_SKGE is not set
3412 +# CONFIG_SKY2 is not set
3413 +# CONFIG_VIA_VELOCITY is not set
3414 +# CONFIG_TIGON3 is not set
3415 +# CONFIG_BNX2 is not set
3416 +CONFIG_MV643XX_ETH=y
3417 +# CONFIG_QLA3XXX is not set
3418 +# CONFIG_ATL1 is not set
3419 +# CONFIG_NETDEV_10000 is not set
3420 +# CONFIG_TR is not set
3421 +
3422 +#
3423 +# Wireless LAN
3424 +#
3425 +# CONFIG_WLAN_PRE80211 is not set
3426 +# CONFIG_WLAN_80211 is not set
3427 +# CONFIG_IWLWIFI_LEDS is not set
3428 +
3429 +#
3430 +# USB Network Adapters
3431 +#
3432 +# CONFIG_USB_CATC is not set
3433 +# CONFIG_USB_KAWETH is not set
3434 +# CONFIG_USB_PEGASUS is not set
3435 +# CONFIG_USB_RTL8150 is not set
3436 +# CONFIG_USB_USBNET is not set
3437 +# CONFIG_WAN is not set
3438 +# CONFIG_FDDI is not set
3439 +# CONFIG_HIPPI is not set
3440 +# CONFIG_PPP is not set
3441 +# CONFIG_SLIP is not set
3442 +# CONFIG_NET_FC is not set
3443 +# CONFIG_NETCONSOLE is not set
3444 +# CONFIG_NETPOLL is not set
3445 +# CONFIG_NET_POLL_CONTROLLER is not set
3446 +# CONFIG_ISDN is not set
3447 +
3448 +#
3449 +# Input device support
3450 +#
3451 +CONFIG_INPUT=y
3452 +# CONFIG_INPUT_FF_MEMLESS is not set
3453 +# CONFIG_INPUT_POLLDEV is not set
3454 +
3455 +#
3456 +# Userland interfaces
3457 +#
3458 +# CONFIG_INPUT_MOUSEDEV is not set
3459 +# CONFIG_INPUT_JOYDEV is not set
3460 +CONFIG_INPUT_EVDEV=y
3461 +# CONFIG_INPUT_EVBUG is not set
3462 +
3463 +#
3464 +# Input Device Drivers
3465 +#
3466 +# CONFIG_INPUT_KEYBOARD is not set
3467 +# CONFIG_INPUT_MOUSE is not set
3468 +# CONFIG_INPUT_JOYSTICK is not set
3469 +# CONFIG_INPUT_TABLET is not set
3470 +# CONFIG_INPUT_TOUCHSCREEN is not set
3471 +# CONFIG_INPUT_MISC is not set
3472 +
3473 +#
3474 +# Hardware I/O ports
3475 +#
3476 +# CONFIG_SERIO is not set
3477 +# CONFIG_GAMEPORT is not set
3478 +
3479 +#
3480 +# Character devices
3481 +#
3482 +# CONFIG_VT is not set
3483 +CONFIG_DEVKMEM=y
3484 +# CONFIG_SERIAL_NONSTANDARD is not set
3485 +# CONFIG_NOZOMI is not set
3486 +
3487 +#
3488 +# Serial drivers
3489 +#
3490 +CONFIG_SERIAL_8250=y
3491 +CONFIG_SERIAL_8250_CONSOLE=y
3492 +# CONFIG_SERIAL_8250_PCI is not set
3493 +CONFIG_SERIAL_8250_NR_UARTS=4
3494 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
3495 +# CONFIG_SERIAL_8250_EXTENDED is not set
3496 +
3497 +#
3498 +# Non-8250 serial port support
3499 +#
3500 +CONFIG_SERIAL_CORE=y
3501 +CONFIG_SERIAL_CORE_CONSOLE=y
3502 +# CONFIG_SERIAL_JSM is not set
3503 +CONFIG_UNIX98_PTYS=y
3504 +CONFIG_LEGACY_PTYS=y
3505 +CONFIG_LEGACY_PTY_COUNT=16
3506 +# CONFIG_IPMI_HANDLER is not set
3507 +# CONFIG_HW_RANDOM is not set
3508 +# CONFIG_NVRAM is not set
3509 +# CONFIG_R3964 is not set
3510 +# CONFIG_APPLICOM is not set
3511 +# CONFIG_RAW_DRIVER is not set
3512 +# CONFIG_TCG_TPM is not set
3513 +CONFIG_DEVPORT=y
3514 +CONFIG_I2C=y
3515 +CONFIG_I2C_BOARDINFO=y
3516 +CONFIG_I2C_CHARDEV=y
3517 +
3518 +#
3519 +# I2C Hardware Bus support
3520 +#
3521 +# CONFIG_I2C_ALI1535 is not set
3522 +# CONFIG_I2C_ALI1563 is not set
3523 +# CONFIG_I2C_ALI15X3 is not set
3524 +# CONFIG_I2C_AMD756 is not set
3525 +# CONFIG_I2C_AMD8111 is not set
3526 +# CONFIG_I2C_I801 is not set
3527 +# CONFIG_I2C_I810 is not set
3528 +# CONFIG_I2C_PIIX4 is not set
3529 +# CONFIG_I2C_NFORCE2 is not set
3530 +# CONFIG_I2C_OCORES is not set
3531 +# CONFIG_I2C_PARPORT_LIGHT is not set
3532 +# CONFIG_I2C_PROSAVAGE is not set
3533 +# CONFIG_I2C_SAVAGE4 is not set
3534 +# CONFIG_I2C_SIMTEC is not set
3535 +# CONFIG_I2C_SIS5595 is not set
3536 +# CONFIG_I2C_SIS630 is not set
3537 +# CONFIG_I2C_SIS96X is not set
3538 +# CONFIG_I2C_TAOS_EVM is not set
3539 +# CONFIG_I2C_STUB is not set
3540 +# CONFIG_I2C_TINY_USB is not set
3541 +# CONFIG_I2C_VIA is not set
3542 +# CONFIG_I2C_VIAPRO is not set
3543 +# CONFIG_I2C_VOODOO3 is not set
3544 +# CONFIG_I2C_PCA_PLATFORM is not set
3545 +CONFIG_I2C_MV64XXX=y
3546 +
3547 +#
3548 +# Miscellaneous I2C Chip support
3549 +#
3550 +# CONFIG_DS1682 is not set
3551 +# CONFIG_SENSORS_EEPROM is not set
3552 +# CONFIG_SENSORS_PCF8574 is not set
3553 +# CONFIG_PCF8575 is not set
3554 +# CONFIG_SENSORS_PCF8591 is not set
3555 +# CONFIG_SENSORS_MAX6875 is not set
3556 +# CONFIG_SENSORS_TSL2550 is not set
3557 +# CONFIG_I2C_DEBUG_CORE is not set
3558 +# CONFIG_I2C_DEBUG_ALGO is not set
3559 +# CONFIG_I2C_DEBUG_BUS is not set
3560 +# CONFIG_I2C_DEBUG_CHIP is not set
3561 +# CONFIG_SPI is not set
3562 +# CONFIG_W1 is not set
3563 +# CONFIG_POWER_SUPPLY is not set
3564 +CONFIG_HWMON=y
3565 +# CONFIG_HWMON_VID is not set
3566 +# CONFIG_SENSORS_AD7418 is not set
3567 +# CONFIG_SENSORS_ADM1021 is not set
3568 +# CONFIG_SENSORS_ADM1025 is not set
3569 +# CONFIG_SENSORS_ADM1026 is not set
3570 +# CONFIG_SENSORS_ADM1029 is not set
3571 +# CONFIG_SENSORS_ADM1031 is not set
3572 +# CONFIG_SENSORS_ADM9240 is not set
3573 +# CONFIG_SENSORS_ADT7470 is not set
3574 +# CONFIG_SENSORS_ADT7473 is not set
3575 +# CONFIG_SENSORS_ATXP1 is not set
3576 +# CONFIG_SENSORS_DS1621 is not set
3577 +# CONFIG_SENSORS_I5K_AMB is not set
3578 +# CONFIG_SENSORS_F71805F is not set
3579 +# CONFIG_SENSORS_F71882FG is not set
3580 +# CONFIG_SENSORS_F75375S is not set
3581 +# CONFIG_SENSORS_GL518SM is not set
3582 +# CONFIG_SENSORS_GL520SM is not set
3583 +# CONFIG_SENSORS_IT87 is not set
3584 +# CONFIG_SENSORS_LM63 is not set
3585 +# CONFIG_SENSORS_LM75 is not set
3586 +# CONFIG_SENSORS_LM77 is not set
3587 +# CONFIG_SENSORS_LM78 is not set
3588 +# CONFIG_SENSORS_LM80 is not set
3589 +# CONFIG_SENSORS_LM83 is not set
3590 +# CONFIG_SENSORS_LM85 is not set
3591 +# CONFIG_SENSORS_LM87 is not set
3592 +# CONFIG_SENSORS_LM90 is not set
3593 +# CONFIG_SENSORS_LM92 is not set
3594 +# CONFIG_SENSORS_LM93 is not set
3595 +# CONFIG_SENSORS_MAX1619 is not set
3596 +# CONFIG_SENSORS_MAX6650 is not set
3597 +# CONFIG_SENSORS_PC87360 is not set
3598 +# CONFIG_SENSORS_PC87427 is not set
3599 +# CONFIG_SENSORS_SIS5595 is not set
3600 +# CONFIG_SENSORS_DME1737 is not set
3601 +# CONFIG_SENSORS_SMSC47M1 is not set
3602 +# CONFIG_SENSORS_SMSC47M192 is not set
3603 +# CONFIG_SENSORS_SMSC47B397 is not set
3604 +# CONFIG_SENSORS_ADS7828 is not set
3605 +# CONFIG_SENSORS_THMC50 is not set
3606 +# CONFIG_SENSORS_VIA686A is not set
3607 +# CONFIG_SENSORS_VT1211 is not set
3608 +# CONFIG_SENSORS_VT8231 is not set
3609 +# CONFIG_SENSORS_W83781D is not set
3610 +# CONFIG_SENSORS_W83791D is not set
3611 +# CONFIG_SENSORS_W83792D is not set
3612 +# CONFIG_SENSORS_W83793 is not set
3613 +# CONFIG_SENSORS_W83L785TS is not set
3614 +# CONFIG_SENSORS_W83L786NG is not set
3615 +# CONFIG_SENSORS_W83627HF is not set
3616 +# CONFIG_SENSORS_W83627EHF is not set
3617 +# CONFIG_HWMON_DEBUG_CHIP is not set
3618 +# CONFIG_WATCHDOG is not set
3619 +
3620 +#
3621 +# Sonics Silicon Backplane
3622 +#
3623 +CONFIG_SSB_POSSIBLE=y
3624 +# CONFIG_SSB is not set
3625 +
3626 +#
3627 +# Multifunction device drivers
3628 +#
3629 +# CONFIG_MFD_SM501 is not set
3630 +# CONFIG_MFD_ASIC3 is not set
3631 +# CONFIG_HTC_PASIC3 is not set
3632 +
3633 +#
3634 +# Multimedia devices
3635 +#
3636 +
3637 +#
3638 +# Multimedia core support
3639 +#
3640 +# CONFIG_VIDEO_DEV is not set
3641 +# CONFIG_DVB_CORE is not set
3642 +# CONFIG_VIDEO_MEDIA is not set
3643 +
3644 +#
3645 +# Multimedia drivers
3646 +#
3647 +# CONFIG_DAB is not set
3648 +
3649 +#
3650 +# Graphics support
3651 +#
3652 +# CONFIG_DRM is not set
3653 +# CONFIG_VGASTATE is not set
3654 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
3655 +# CONFIG_FB is not set
3656 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
3657 +
3658 +#
3659 +# Display device support
3660 +#
3661 +# CONFIG_DISPLAY_SUPPORT is not set
3662 +
3663 +#
3664 +# Sound
3665 +#
3666 +# CONFIG_SOUND is not set
3667 +CONFIG_HID_SUPPORT=y
3668 +CONFIG_HID=y
3669 +# CONFIG_HID_DEBUG is not set
3670 +# CONFIG_HIDRAW is not set
3671 +
3672 +#
3673 +# USB Input Devices
3674 +#
3675 +CONFIG_USB_HID=y
3676 +# CONFIG_USB_HIDINPUT_POWERBOOK is not set
3677 +# CONFIG_HID_FF is not set
3678 +# CONFIG_USB_HIDDEV is not set
3679 +CONFIG_USB_SUPPORT=y
3680 +CONFIG_USB_ARCH_HAS_HCD=y
3681 +CONFIG_USB_ARCH_HAS_OHCI=y
3682 +CONFIG_USB_ARCH_HAS_EHCI=y
3683 +CONFIG_USB=y
3684 +# CONFIG_USB_DEBUG is not set
3685 +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
3686 +
3687 +#
3688 +# Miscellaneous USB options
3689 +#
3690 +CONFIG_USB_DEVICEFS=y
3691 +CONFIG_USB_DEVICE_CLASS=y
3692 +# CONFIG_USB_DYNAMIC_MINORS is not set
3693 +# CONFIG_USB_OTG is not set
3694 +# CONFIG_USB_OTG_WHITELIST is not set
3695 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
3696 +
3697 +#
3698 +# USB Host Controller Drivers
3699 +#
3700 +# CONFIG_USB_C67X00_HCD is not set
3701 +CONFIG_USB_EHCI_HCD=y
3702 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
3703 +CONFIG_USB_EHCI_TT_NEWSCHED=y
3704 +# CONFIG_USB_ISP116X_HCD is not set
3705 +# CONFIG_USB_ISP1760_HCD is not set
3706 +# CONFIG_USB_OHCI_HCD is not set
3707 +# CONFIG_USB_UHCI_HCD is not set
3708 +# CONFIG_USB_SL811_HCD is not set
3709 +# CONFIG_USB_R8A66597_HCD is not set
3710 +
3711 +#
3712 +# USB Device Class drivers
3713 +#
3714 +# CONFIG_USB_ACM is not set
3715 +CONFIG_USB_PRINTER=y
3716 +# CONFIG_USB_WDM is not set
3717 +
3718 +#
3719 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3720 +#
3721 +
3722 +#
3723 +# may also be needed; see USB_STORAGE Help for more information
3724 +#
3725 +CONFIG_USB_STORAGE=y
3726 +# CONFIG_USB_STORAGE_DEBUG is not set
3727 +CONFIG_USB_STORAGE_DATAFAB=y
3728 +CONFIG_USB_STORAGE_FREECOM=y
3729 +# CONFIG_USB_STORAGE_ISD200 is not set
3730 +CONFIG_USB_STORAGE_DPCM=y
3731 +# CONFIG_USB_STORAGE_USBAT is not set
3732 +CONFIG_USB_STORAGE_SDDR09=y
3733 +CONFIG_USB_STORAGE_SDDR55=y
3734 +CONFIG_USB_STORAGE_JUMPSHOT=y
3735 +# CONFIG_USB_STORAGE_ALAUDA is not set
3736 +# CONFIG_USB_STORAGE_ONETOUCH is not set
3737 +# CONFIG_USB_STORAGE_KARMA is not set
3738 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
3739 +# CONFIG_USB_LIBUSUAL is not set
3740 +
3741 +#
3742 +# USB Imaging devices
3743 +#
3744 +# CONFIG_USB_MDC800 is not set
3745 +# CONFIG_USB_MICROTEK is not set
3746 +# CONFIG_USB_MON is not set
3747 +
3748 +#
3749 +# USB port drivers
3750 +#
3751 +# CONFIG_USB_SERIAL is not set
3752 +
3753 +#
3754 +# USB Miscellaneous drivers
3755 +#
3756 +# CONFIG_USB_EMI62 is not set
3757 +# CONFIG_USB_EMI26 is not set
3758 +# CONFIG_USB_ADUTUX is not set
3759 +# CONFIG_USB_AUERSWALD is not set
3760 +# CONFIG_USB_RIO500 is not set
3761 +# CONFIG_USB_LEGOTOWER is not set
3762 +# CONFIG_USB_LCD is not set
3763 +# CONFIG_USB_BERRY_CHARGE is not set
3764 +# CONFIG_USB_LED is not set
3765 +# CONFIG_USB_CYPRESS_CY7C63 is not set
3766 +# CONFIG_USB_CYTHERM is not set
3767 +# CONFIG_USB_PHIDGET is not set
3768 +# CONFIG_USB_IDMOUSE is not set
3769 +# CONFIG_USB_FTDI_ELAN is not set
3770 +# CONFIG_USB_APPLEDISPLAY is not set
3771 +# CONFIG_USB_SISUSBVGA is not set
3772 +# CONFIG_USB_LD is not set
3773 +# CONFIG_USB_TRANCEVIBRATOR is not set
3774 +# CONFIG_USB_IOWARRIOR is not set
3775 +# CONFIG_USB_TEST is not set
3776 +# CONFIG_USB_ISIGHTFW is not set
3777 +# CONFIG_USB_GADGET is not set
3778 +# CONFIG_MMC is not set
3779 +CONFIG_NEW_LEDS=y
3780 +CONFIG_LEDS_CLASS=y
3781 +
3782 +#
3783 +# LED drivers
3784 +#
3785 +
3786 +#
3787 +# LED Triggers
3788 +#
3789 +CONFIG_LEDS_TRIGGERS=y
3790 +CONFIG_LEDS_TRIGGER_TIMER=y
3791 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
3792 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
3793 +CONFIG_RTC_LIB=y
3794 +CONFIG_RTC_CLASS=y
3795 +CONFIG_RTC_HCTOSYS=y
3796 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3797 +# CONFIG_RTC_DEBUG is not set
3798 +
3799 +#
3800 +# RTC interfaces
3801 +#
3802 +CONFIG_RTC_INTF_SYSFS=y
3803 +CONFIG_RTC_INTF_PROC=y
3804 +CONFIG_RTC_INTF_DEV=y
3805 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3806 +# CONFIG_RTC_DRV_TEST is not set
3807 +
3808 +#
3809 +# I2C RTC drivers
3810 +#
3811 +CONFIG_RTC_DRV_DS1307=y
3812 +# CONFIG_RTC_DRV_DS1374 is not set
3813 +# CONFIG_RTC_DRV_DS1672 is not set
3814 +# CONFIG_RTC_DRV_MAX6900 is not set
3815 +CONFIG_RTC_DRV_RS5C372=y
3816 +# CONFIG_RTC_DRV_ISL1208 is not set
3817 +# CONFIG_RTC_DRV_X1205 is not set
3818 +# CONFIG_RTC_DRV_PCF8563 is not set
3819 +# CONFIG_RTC_DRV_PCF8583 is not set
3820 +CONFIG_RTC_DRV_M41T80=y
3821 +# CONFIG_RTC_DRV_M41T80_WDT is not set
3822 +# CONFIG_RTC_DRV_S35390A is not set
3823 +
3824 +#
3825 +# SPI RTC drivers
3826 +#
3827 +
3828 +#
3829 +# Platform RTC drivers
3830 +#
3831 +# CONFIG_RTC_DRV_CMOS is not set
3832 +# CONFIG_RTC_DRV_DS1511 is not set
3833 +# CONFIG_RTC_DRV_DS1553 is not set
3834 +# CONFIG_RTC_DRV_DS1742 is not set
3835 +# CONFIG_RTC_DRV_STK17TA8 is not set
3836 +# CONFIG_RTC_DRV_M48T86 is not set
3837 +# CONFIG_RTC_DRV_M48T59 is not set
3838 +# CONFIG_RTC_DRV_V3020 is not set
3839 +
3840 +#
3841 +# on-CPU RTC drivers
3842 +#
3843 +# CONFIG_UIO is not set
3844 +
3845 +#
3846 +# File systems
3847 +#
3848 +CONFIG_EXT2_FS=y
3849 +# CONFIG_EXT2_FS_XATTR is not set
3850 +# CONFIG_EXT2_FS_XIP is not set
3851 +CONFIG_EXT3_FS=y
3852 +# CONFIG_EXT3_FS_XATTR is not set
3853 +# CONFIG_EXT4DEV_FS is not set
3854 +CONFIG_JBD=y
3855 +# CONFIG_REISERFS_FS is not set
3856 +# CONFIG_JFS_FS is not set
3857 +# CONFIG_FS_POSIX_ACL is not set
3858 +# CONFIG_XFS_FS is not set
3859 +# CONFIG_OCFS2_FS is not set
3860 +CONFIG_DNOTIFY=y
3861 +CONFIG_INOTIFY=y
3862 +CONFIG_INOTIFY_USER=y
3863 +# CONFIG_QUOTA is not set
3864 +# CONFIG_AUTOFS_FS is not set
3865 +# CONFIG_AUTOFS4_FS is not set
3866 +# CONFIG_FUSE_FS is not set
3867 +
3868 +#
3869 +# CD-ROM/DVD Filesystems
3870 +#
3871 +CONFIG_ISO9660_FS=m
3872 +CONFIG_JOLIET=y
3873 +# CONFIG_ZISOFS is not set
3874 +CONFIG_UDF_FS=m
3875 +CONFIG_UDF_NLS=y
3876 +
3877 +#
3878 +# DOS/FAT/NT Filesystems
3879 +#
3880 +CONFIG_FAT_FS=y
3881 +CONFIG_MSDOS_FS=y
3882 +CONFIG_VFAT_FS=y
3883 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3884 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3885 +# CONFIG_NTFS_FS is not set
3886 +
3887 +#
3888 +# Pseudo filesystems
3889 +#
3890 +CONFIG_PROC_FS=y
3891 +CONFIG_PROC_SYSCTL=y
3892 +CONFIG_SYSFS=y
3893 +CONFIG_TMPFS=y
3894 +# CONFIG_TMPFS_POSIX_ACL is not set
3895 +# CONFIG_HUGETLB_PAGE is not set
3896 +# CONFIG_CONFIGFS_FS is not set
3897 +
3898 +#
3899 +# Miscellaneous filesystems
3900 +#
3901 +# CONFIG_ADFS_FS is not set
3902 +# CONFIG_AFFS_FS is not set
3903 +# CONFIG_HFS_FS is not set
3904 +# CONFIG_HFSPLUS_FS is not set
3905 +# CONFIG_BEFS_FS is not set
3906 +# CONFIG_BFS_FS is not set
3907 +# CONFIG_EFS_FS is not set
3908 +CONFIG_JFFS2_FS=y
3909 +CONFIG_JFFS2_FS_DEBUG=0
3910 +CONFIG_JFFS2_FS_WRITEBUFFER=y
3911 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3912 +# CONFIG_JFFS2_SUMMARY is not set
3913 +# CONFIG_JFFS2_FS_XATTR is not set
3914 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3915 +CONFIG_JFFS2_ZLIB=y
3916 +# CONFIG_JFFS2_LZO is not set
3917 +CONFIG_JFFS2_RTIME=y
3918 +# CONFIG_JFFS2_RUBIN is not set
3919 +CONFIG_CRAMFS=y
3920 +# CONFIG_VXFS_FS is not set
3921 +# CONFIG_MINIX_FS is not set
3922 +# CONFIG_HPFS_FS is not set
3923 +# CONFIG_QNX4FS_FS is not set
3924 +# CONFIG_ROMFS_FS is not set
3925 +# CONFIG_SYSV_FS is not set
3926 +# CONFIG_UFS_FS is not set
3927 +CONFIG_NETWORK_FILESYSTEMS=y
3928 +CONFIG_NFS_FS=y
3929 +CONFIG_NFS_V3=y
3930 +# CONFIG_NFS_V3_ACL is not set
3931 +# CONFIG_NFS_V4 is not set
3932 +# CONFIG_NFSD is not set
3933 +CONFIG_ROOT_NFS=y
3934 +CONFIG_LOCKD=y
3935 +CONFIG_LOCKD_V4=y
3936 +CONFIG_NFS_COMMON=y
3937 +CONFIG_SUNRPC=y
3938 +# CONFIG_SUNRPC_BIND34 is not set
3939 +# CONFIG_RPCSEC_GSS_KRB5 is not set
3940 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
3941 +# CONFIG_SMB_FS is not set
3942 +# CONFIG_CIFS is not set
3943 +# CONFIG_NCP_FS is not set
3944 +# CONFIG_CODA_FS is not set
3945 +# CONFIG_AFS_FS is not set
3946 +
3947 +#
3948 +# Partition Types
3949 +#
3950 +CONFIG_PARTITION_ADVANCED=y
3951 +# CONFIG_ACORN_PARTITION is not set
3952 +# CONFIG_OSF_PARTITION is not set
3953 +# CONFIG_AMIGA_PARTITION is not set
3954 +# CONFIG_ATARI_PARTITION is not set
3955 +# CONFIG_MAC_PARTITION is not set
3956 +CONFIG_MSDOS_PARTITION=y
3957 +CONFIG_BSD_DISKLABEL=y
3958 +# CONFIG_MINIX_SUBPARTITION is not set
3959 +# CONFIG_SOLARIS_X86_PARTITION is not set
3960 +# CONFIG_UNIXWARE_DISKLABEL is not set
3961 +# CONFIG_LDM_PARTITION is not set
3962 +# CONFIG_SGI_PARTITION is not set
3963 +# CONFIG_ULTRIX_PARTITION is not set
3964 +# CONFIG_SUN_PARTITION is not set
3965 +# CONFIG_KARMA_PARTITION is not set
3966 +# CONFIG_EFI_PARTITION is not set
3967 +# CONFIG_SYSV68_PARTITION is not set
3968 +CONFIG_NLS=y
3969 +CONFIG_NLS_DEFAULT="iso8859-1"
3970 +CONFIG_NLS_CODEPAGE_437=y
3971 +# CONFIG_NLS_CODEPAGE_737 is not set
3972 +# CONFIG_NLS_CODEPAGE_775 is not set
3973 +CONFIG_NLS_CODEPAGE_850=y
3974 +# CONFIG_NLS_CODEPAGE_852 is not set
3975 +# CONFIG_NLS_CODEPAGE_855 is not set
3976 +# CONFIG_NLS_CODEPAGE_857 is not set
3977 +# CONFIG_NLS_CODEPAGE_860 is not set
3978 +# CONFIG_NLS_CODEPAGE_861 is not set
3979 +# CONFIG_NLS_CODEPAGE_862 is not set
3980 +# CONFIG_NLS_CODEPAGE_863 is not set
3981 +# CONFIG_NLS_CODEPAGE_864 is not set
3982 +# CONFIG_NLS_CODEPAGE_865 is not set
3983 +# CONFIG_NLS_CODEPAGE_866 is not set
3984 +# CONFIG_NLS_CODEPAGE_869 is not set
3985 +# CONFIG_NLS_CODEPAGE_936 is not set
3986 +# CONFIG_NLS_CODEPAGE_950 is not set
3987 +# CONFIG_NLS_CODEPAGE_932 is not set
3988 +# CONFIG_NLS_CODEPAGE_949 is not set
3989 +# CONFIG_NLS_CODEPAGE_874 is not set
3990 +# CONFIG_NLS_ISO8859_8 is not set
3991 +# CONFIG_NLS_CODEPAGE_1250 is not set
3992 +# CONFIG_NLS_CODEPAGE_1251 is not set
3993 +# CONFIG_NLS_ASCII is not set
3994 +CONFIG_NLS_ISO8859_1=y
3995 +CONFIG_NLS_ISO8859_2=y
3996 +# CONFIG_NLS_ISO8859_3 is not set
3997 +# CONFIG_NLS_ISO8859_4 is not set
3998 +# CONFIG_NLS_ISO8859_5 is not set
3999 +# CONFIG_NLS_ISO8859_6 is not set
4000 +# CONFIG_NLS_ISO8859_7 is not set
4001 +# CONFIG_NLS_ISO8859_9 is not set
4002 +# CONFIG_NLS_ISO8859_13 is not set
4003 +# CONFIG_NLS_ISO8859_14 is not set
4004 +# CONFIG_NLS_ISO8859_15 is not set
4005 +# CONFIG_NLS_KOI8_R is not set
4006 +# CONFIG_NLS_KOI8_U is not set
4007 +# CONFIG_NLS_UTF8 is not set
4008 +# CONFIG_DLM is not set
4009 +
4010 +#
4011 +# Kernel hacking
4012 +#
4013 +# CONFIG_PRINTK_TIME is not set
4014 +CONFIG_ENABLE_WARN_DEPRECATED=y
4015 +CONFIG_ENABLE_MUST_CHECK=y
4016 +CONFIG_FRAME_WARN=1024
4017 +CONFIG_MAGIC_SYSRQ=y
4018 +# CONFIG_UNUSED_SYMBOLS is not set
4019 +# CONFIG_DEBUG_FS is not set
4020 +# CONFIG_HEADERS_CHECK is not set
4021 +CONFIG_DEBUG_KERNEL=y
4022 +# CONFIG_DEBUG_SHIRQ is not set
4023 +CONFIG_DETECT_SOFTLOCKUP=y
4024 +CONFIG_SCHED_DEBUG=y
4025 +CONFIG_SCHEDSTATS=y
4026 +# CONFIG_TIMER_STATS is not set
4027 +# CONFIG_DEBUG_OBJECTS is not set
4028 +CONFIG_DEBUG_PREEMPT=y
4029 +# CONFIG_DEBUG_RT_MUTEXES is not set
4030 +# CONFIG_RT_MUTEX_TESTER is not set
4031 +# CONFIG_DEBUG_SPINLOCK is not set
4032 +# CONFIG_DEBUG_MUTEXES is not set
4033 +# CONFIG_DEBUG_LOCK_ALLOC is not set
4034 +# CONFIG_PROVE_LOCKING is not set
4035 +# CONFIG_LOCK_STAT is not set
4036 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
4037 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
4038 +# CONFIG_DEBUG_KOBJECT is not set
4039 +# CONFIG_DEBUG_BUGVERBOSE is not set
4040 +CONFIG_DEBUG_INFO=y
4041 +# CONFIG_DEBUG_VM is not set
4042 +# CONFIG_DEBUG_WRITECOUNT is not set
4043 +# CONFIG_DEBUG_LIST is not set
4044 +# CONFIG_DEBUG_SG is not set
4045 +CONFIG_FRAME_POINTER=y
4046 +# CONFIG_BOOT_PRINTK_DELAY is not set
4047 +# CONFIG_RCU_TORTURE_TEST is not set
4048 +# CONFIG_KPROBES_SANITY_TEST is not set
4049 +# CONFIG_BACKTRACE_SELF_TEST is not set
4050 +# CONFIG_LKDTM is not set
4051 +# CONFIG_FAULT_INJECTION is not set
4052 +# CONFIG_LATENCYTOP is not set
4053 +# CONFIG_SAMPLES is not set
4054 +CONFIG_DEBUG_USER=y
4055 +CONFIG_DEBUG_ERRORS=y
4056 +# CONFIG_DEBUG_STACK_USAGE is not set
4057 +CONFIG_DEBUG_LL=y
4058 +# CONFIG_DEBUG_ICEDCC is not set
4059 +
4060 +#
4061 +# Security options
4062 +#
4063 +# CONFIG_KEYS is not set
4064 +# CONFIG_SECURITY is not set
4065 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4066 +CONFIG_CRYPTO=y
4067 +
4068 +#
4069 +# Crypto core or helper
4070 +#
4071 +CONFIG_CRYPTO_ALGAPI=m
4072 +CONFIG_CRYPTO_BLKCIPHER=m
4073 +CONFIG_CRYPTO_MANAGER=m
4074 +# CONFIG_CRYPTO_GF128MUL is not set
4075 +# CONFIG_CRYPTO_NULL is not set
4076 +# CONFIG_CRYPTO_CRYPTD is not set
4077 +# CONFIG_CRYPTO_AUTHENC is not set
4078 +# CONFIG_CRYPTO_TEST is not set
4079 +
4080 +#
4081 +# Authenticated Encryption with Associated Data
4082 +#
4083 +# CONFIG_CRYPTO_CCM is not set
4084 +# CONFIG_CRYPTO_GCM is not set
4085 +# CONFIG_CRYPTO_SEQIV is not set
4086 +
4087 +#
4088 +# Block modes
4089 +#
4090 +CONFIG_CRYPTO_CBC=m
4091 +# CONFIG_CRYPTO_CTR is not set
4092 +# CONFIG_CRYPTO_CTS is not set
4093 +CONFIG_CRYPTO_ECB=m
4094 +# CONFIG_CRYPTO_LRW is not set
4095 +CONFIG_CRYPTO_PCBC=m
4096 +# CONFIG_CRYPTO_XTS is not set
4097 +
4098 +#
4099 +# Hash modes
4100 +#
4101 +# CONFIG_CRYPTO_HMAC is not set
4102 +# CONFIG_CRYPTO_XCBC is not set
4103 +
4104 +#
4105 +# Digest
4106 +#
4107 +# CONFIG_CRYPTO_CRC32C is not set
4108 +# CONFIG_CRYPTO_MD4 is not set
4109 +# CONFIG_CRYPTO_MD5 is not set
4110 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
4111 +# CONFIG_CRYPTO_SHA1 is not set
4112 +# CONFIG_CRYPTO_SHA256 is not set
4113 +# CONFIG_CRYPTO_SHA512 is not set
4114 +# CONFIG_CRYPTO_TGR192 is not set
4115 +# CONFIG_CRYPTO_WP512 is not set
4116 +
4117 +#
4118 +# Ciphers
4119 +#
4120 +# CONFIG_CRYPTO_AES is not set
4121 +# CONFIG_CRYPTO_ANUBIS is not set
4122 +# CONFIG_CRYPTO_ARC4 is not set
4123 +# CONFIG_CRYPTO_BLOWFISH is not set
4124 +# CONFIG_CRYPTO_CAMELLIA is not set
4125 +# CONFIG_CRYPTO_CAST5 is not set
4126 +# CONFIG_CRYPTO_CAST6 is not set
4127 +# CONFIG_CRYPTO_DES is not set
4128 +# CONFIG_CRYPTO_FCRYPT is not set
4129 +# CONFIG_CRYPTO_KHAZAD is not set
4130 +# CONFIG_CRYPTO_SALSA20 is not set
4131 +# CONFIG_CRYPTO_SEED is not set
4132 +# CONFIG_CRYPTO_SERPENT is not set
4133 +# CONFIG_CRYPTO_TEA is not set
4134 +# CONFIG_CRYPTO_TWOFISH is not set
4135 +
4136 +#
4137 +# Compression
4138 +#
4139 +# CONFIG_CRYPTO_DEFLATE is not set
4140 +# CONFIG_CRYPTO_LZO is not set
4141 +CONFIG_CRYPTO_HW=y
4142 +# CONFIG_CRYPTO_DEV_HIFN_795X is not set
4143 +
4144 +#
4145 +# Library routines
4146 +#
4147 +CONFIG_BITREVERSE=y
4148 +# CONFIG_GENERIC_FIND_FIRST_BIT is not set
4149 +# CONFIG_GENERIC_FIND_NEXT_BIT is not set
4150 +# CONFIG_CRC_CCITT is not set
4151 +# CONFIG_CRC16 is not set
4152 +CONFIG_CRC_ITU_T=m
4153 +CONFIG_CRC32=y
4154 +# CONFIG_CRC7 is not set
4155 +# CONFIG_LIBCRC32C is not set
4156 +CONFIG_ZLIB_INFLATE=y
4157 +CONFIG_ZLIB_DEFLATE=y
4158 +CONFIG_PLIST=y
4159 +CONFIG_HAS_IOMEM=y
4160 +CONFIG_HAS_IOPORT=y
4161 +CONFIG_HAS_DMA=y
4162 --- a/arch/arm/configs/orion5x_defconfig
4163 +++ b/arch/arm/configs/orion5x_defconfig
4164 @@ -1,7 +1,7 @@
4165  #
4166  # Automatically generated make config: don't edit
4167 -# Linux kernel version: 2.6.24
4168 -# Thu Feb  7 14:10:30 2008
4169 +# Linux kernel version: 2.6.26-rc4
4170 +# Mon Jun  2 23:54:48 2008
4171  #
4172  CONFIG_ARM=y
4173  CONFIG_SYS_SUPPORTS_APM_EMULATION=y
4174 @@ -21,6 +21,7 @@
4175  # CONFIG_ARCH_HAS_ILOG2_U64 is not set
4176  CONFIG_GENERIC_HWEIGHT=y
4177  CONFIG_GENERIC_CALIBRATE_DELAY=y
4178 +CONFIG_ARCH_SUPPORTS_AOUT=y
4179  CONFIG_ZONE_DMA=y
4180  CONFIG_VECTORS_BASE=0xffff0000
4181  CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
4182 @@ -40,24 +41,24 @@
4183  # CONFIG_POSIX_MQUEUE is not set
4184  # CONFIG_BSD_PROCESS_ACCT is not set
4185  # CONFIG_TASKSTATS is not set
4186 -# CONFIG_USER_NS is not set
4187 -# CONFIG_PID_NS is not set
4188  # CONFIG_AUDIT is not set
4189  # CONFIG_IKCONFIG is not set
4190  CONFIG_LOG_BUF_SHIFT=14
4191  # CONFIG_CGROUPS is not set
4192 -CONFIG_FAIR_GROUP_SCHED=y
4193 -CONFIG_FAIR_USER_SCHED=y
4194 -# CONFIG_FAIR_CGROUP_SCHED is not set
4195 +# CONFIG_GROUP_SCHED is not set
4196  CONFIG_SYSFS_DEPRECATED=y
4197 +CONFIG_SYSFS_DEPRECATED_V2=y
4198  # CONFIG_RELAY is not set
4199 +# CONFIG_NAMESPACES is not set
4200  # CONFIG_BLK_DEV_INITRD is not set
4201  CONFIG_CC_OPTIMIZE_FOR_SIZE=y
4202  CONFIG_SYSCTL=y
4203  CONFIG_EMBEDDED=y
4204  CONFIG_UID16=y
4205  CONFIG_SYSCTL_SYSCALL=y
4206 +CONFIG_SYSCTL_SYSCALL_CHECK=y
4207  CONFIG_KALLSYMS=y
4208 +CONFIG_KALLSYMS_ALL=y
4209  # CONFIG_KALLSYMS_EXTRA_PASS is not set
4210  CONFIG_HOTPLUG=y
4211  CONFIG_PRINTK=y
4212 @@ -73,20 +74,25 @@
4213  CONFIG_EVENTFD=y
4214  CONFIG_SHMEM=y
4215  CONFIG_VM_EVENT_COUNTERS=y
4216 -CONFIG_SLAB=y
4217 -# CONFIG_SLUB is not set
4218 +# CONFIG_SLUB_DEBUG is not set
4219 +# CONFIG_SLAB is not set
4220 +CONFIG_SLUB=y
4221  # CONFIG_SLOB is not set
4222 -# CONFIG_PROFILING is not set
4223 +CONFIG_PROFILING=y
4224  # CONFIG_MARKERS is not set
4225 +CONFIG_OPROFILE=y
4226  CONFIG_HAVE_OPROFILE=y
4227 -# CONFIG_KPROBES is not set
4228 +CONFIG_KPROBES=y
4229 +CONFIG_KRETPROBES=y
4230  CONFIG_HAVE_KPROBES=y
4231 +CONFIG_HAVE_KRETPROBES=y
4232 +# CONFIG_HAVE_DMA_ATTRS is not set
4233  CONFIG_PROC_PAGE_MONITOR=y
4234 -CONFIG_SLABINFO=y
4235  CONFIG_RT_MUTEXES=y
4236  # CONFIG_TINY_SHMEM is not set
4237  CONFIG_BASE_SMALL=0
4238  CONFIG_MODULES=y
4239 +# CONFIG_MODULE_FORCE_LOAD is not set
4240  CONFIG_MODULE_UNLOAD=y
4241  # CONFIG_MODULE_FORCE_UNLOAD is not set
4242  # CONFIG_MODVERSIONS is not set
4243 @@ -111,7 +117,6 @@
4244  # CONFIG_DEFAULT_NOOP is not set
4245  CONFIG_DEFAULT_IOSCHED="cfq"
4246  CONFIG_CLASSIC_RCU=y
4247 -# CONFIG_PREEMPT_RCU is not set
4248
4249  #
4250  # System Type
4251 @@ -160,6 +165,7 @@
4252  CONFIG_MACH_KUROBOX_PRO=y
4253  CONFIG_MACH_DNS323=y
4254  CONFIG_MACH_TS209=y
4255 +CONFIG_MACH_LINKSTATION_PRO=y
4256
4257  #
4258  # Boot options
4259 @@ -168,6 +174,7 @@
4260  #
4261  # Power management
4262  #
4263 +CONFIG_PLAT_ORION=y
4264
4265  #
4266  # Processor Type
4267 @@ -177,8 +184,9 @@
4268  CONFIG_CPU_FEROCEON_OLD_ID=y
4269  CONFIG_CPU_32v5=y
4270  CONFIG_CPU_ABRT_EV5T=y
4271 +CONFIG_CPU_PABRT_NOIFAR=y
4272  CONFIG_CPU_CACHE_VIVT=y
4273 -CONFIG_CPU_COPY_V4WB=y
4274 +CONFIG_CPU_COPY_FEROCEON=y
4275  CONFIG_CPU_TLB_V4WBI=y
4276  CONFIG_CPU_CP15=y
4277  CONFIG_CPU_CP15_MMU=y
4278 @@ -189,7 +197,6 @@
4279  CONFIG_ARM_THUMB=y
4280  # CONFIG_CPU_ICACHE_DISABLE is not set
4281  # CONFIG_CPU_DCACHE_DISABLE is not set
4282 -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
4283  # CONFIG_OUTER_CACHE is not set
4284
4285  #
4286 @@ -199,6 +206,7 @@
4287  CONFIG_PCI_SYSCALL=y
4288  # CONFIG_ARCH_SUPPORTS_MSI is not set
4289  CONFIG_PCI_LEGACY=y
4290 +# CONFIG_PCI_DEBUG is not set
4291  # CONFIG_PCCARD is not set
4292
4293  #
4294 @@ -221,6 +229,7 @@
4295  CONFIG_FLAT_NODE_MEM_MAP=y
4296  # CONFIG_SPARSEMEM_STATIC is not set
4297  # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
4298 +CONFIG_PAGEFLAGS_EXTENDED=y
4299  CONFIG_SPLIT_PTLOCK_CPUS=4096
4300  # CONFIG_RESOURCES_64BIT is not set
4301  CONFIG_ZONE_DMA_FLAG=1
4302 @@ -238,7 +247,6 @@
4303  CONFIG_CMDLINE=""
4304  # CONFIG_XIP_KERNEL is not set
4305  # CONFIG_KEXEC is not set
4306 -# CONFIG_ATAGS_PROC is not set
4307
4308  #
4309  # Floating point emulation
4310 @@ -311,8 +319,6 @@
4311  CONFIG_DEFAULT_TCP_CONG="cubic"
4312  # CONFIG_TCP_MD5SIG is not set
4313  # CONFIG_IPV6 is not set
4314 -# CONFIG_INET6_XFRM_TUNNEL is not set
4315 -# CONFIG_INET6_TUNNEL is not set
4316  # CONFIG_NETWORK_SECMARK is not set
4317  # CONFIG_NETFILTER is not set
4318  # CONFIG_IP_DCCP is not set
4319 @@ -335,6 +341,7 @@
4320  # Network testing
4321  #
4322  CONFIG_NET_PKTGEN=m
4323 +# CONFIG_NET_TCPPROBE is not set
4324  # CONFIG_HAMRADIO is not set
4325  # CONFIG_CAN is not set
4326  # CONFIG_IRDA is not set
4327 @@ -362,6 +369,8 @@
4328  CONFIG_STANDALONE=y
4329  CONFIG_PREVENT_FIRMWARE_BUILD=y
4330  CONFIG_FW_LOADER=y
4331 +# CONFIG_DEBUG_DRIVER is not set
4332 +# CONFIG_DEBUG_DEVRES is not set
4333  # CONFIG_SYS_HYPERVISOR is not set
4334  # CONFIG_CONNECTOR is not set
4335  CONFIG_MTD=y
4336 @@ -371,6 +380,7 @@
4337  # CONFIG_MTD_REDBOOT_PARTS is not set
4338  CONFIG_MTD_CMDLINE_PARTS=y
4339  # CONFIG_MTD_AFS_PARTS is not set
4340 +# CONFIG_MTD_AR7_PARTS is not set
4341
4342  #
4343  # User Modules And Translation Layers
4344 @@ -378,9 +388,8 @@
4345  CONFIG_MTD_CHAR=y
4346  CONFIG_MTD_BLKDEVS=y
4347  CONFIG_MTD_BLOCK=y
4348 -CONFIG_FTL=y
4349 -CONFIG_NFTL=y
4350 -# CONFIG_NFTL_RW is not set
4351 +# CONFIG_FTL is not set
4352 +# CONFIG_NFTL is not set
4353  # CONFIG_INFTL is not set
4354  # CONFIG_RFD_FTL is not set
4355  # CONFIG_SSFDC is not set
4356 @@ -405,12 +414,12 @@
4357  # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
4358  CONFIG_MTD_CFI_I1=y
4359  CONFIG_MTD_CFI_I2=y
4360 -CONFIG_MTD_CFI_I4=y
4361 +# CONFIG_MTD_CFI_I4 is not set
4362  # CONFIG_MTD_CFI_I8 is not set
4363  # CONFIG_MTD_OTP is not set
4364  CONFIG_MTD_CFI_INTELEXT=y
4365  CONFIG_MTD_CFI_AMDSTD=y
4366 -CONFIG_MTD_CFI_STAA=y
4367 +# CONFIG_MTD_CFI_STAA is not set
4368  CONFIG_MTD_CFI_UTIL=y
4369  # CONFIG_MTD_RAM is not set
4370  # CONFIG_MTD_ROM is not set
4371 @@ -481,6 +490,9 @@
4372  # CONFIG_EEPROM_93CX6 is not set
4373  # CONFIG_SGI_IOC4 is not set
4374  # CONFIG_TIFM_CORE is not set
4375 +# CONFIG_ENCLOSURE_SERVICES is not set
4376 +CONFIG_HAVE_IDE=y
4377 +# CONFIG_IDE is not set
4378
4379  #
4380  # SCSI device support
4381 @@ -542,6 +554,7 @@
4382  # CONFIG_SCSI_IPS is not set
4383  # CONFIG_SCSI_INITIO is not set
4384  # CONFIG_SCSI_INIA100 is not set
4385 +# CONFIG_SCSI_MVSAS is not set
4386  # CONFIG_SCSI_STEX is not set
4387  # CONFIG_SCSI_SYM53C8XX_2 is not set
4388  # CONFIG_SCSI_IPR is not set
4389 @@ -556,7 +569,10 @@
4390  # CONFIG_SCSI_SRP is not set
4391  CONFIG_ATA=y
4392  # CONFIG_ATA_NONSTANDARD is not set
4393 +CONFIG_SATA_PMP=y
4394  # CONFIG_SATA_AHCI is not set
4395 +# CONFIG_SATA_SIL24 is not set
4396 +CONFIG_ATA_SFF=y
4397  # CONFIG_SATA_SVW is not set
4398  # CONFIG_ATA_PIIX is not set
4399  CONFIG_SATA_MV=y
4400 @@ -566,7 +582,6 @@
4401  # CONFIG_SATA_PROMISE is not set
4402  # CONFIG_SATA_SX4 is not set
4403  # CONFIG_SATA_SIL is not set
4404 -# CONFIG_SATA_SIL24 is not set
4405  # CONFIG_SATA_SIS is not set
4406  # CONFIG_SATA_ULI is not set
4407  # CONFIG_SATA_VIA is not set
4408 @@ -611,6 +626,7 @@
4409  # CONFIG_PATA_VIA is not set
4410  # CONFIG_PATA_WINBOND is not set
4411  # CONFIG_PATA_PLATFORM is not set
4412 +# CONFIG_PATA_SCH is not set
4413  # CONFIG_MD is not set
4414  # CONFIG_FUSION is not set
4415
4416 @@ -652,7 +668,7 @@
4417  # CONFIG_B44 is not set
4418  # CONFIG_FORCEDETH is not set
4419  # CONFIG_EEPRO100 is not set
4420 -CONFIG_E100=y
4421 +# CONFIG_E100 is not set
4422  # CONFIG_FEALNX is not set
4423  # CONFIG_NATSEMI is not set
4424  # CONFIG_NE2K_PCI is not set
4425 @@ -668,9 +684,7 @@
4426  CONFIG_NETDEV_1000=y
4427  # CONFIG_ACENIC is not set
4428  # CONFIG_DL2K is not set
4429 -CONFIG_E1000=y
4430 -CONFIG_E1000_NAPI=y
4431 -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
4432 +# CONFIG_E1000 is not set
4433  # CONFIG_E1000E is not set
4434  # CONFIG_E1000E_ENABLED is not set
4435  # CONFIG_IP1000 is not set
4436 @@ -680,27 +694,15 @@
4437  # CONFIG_YELLOWFIN is not set
4438  # CONFIG_R8169 is not set
4439  # CONFIG_SIS190 is not set
4440 -CONFIG_SKGE=y
4441 -CONFIG_SKY2=y
4442 -# CONFIG_SK98LIN is not set
4443 +# CONFIG_SKGE is not set
4444 +# CONFIG_SKY2 is not set
4445  # CONFIG_VIA_VELOCITY is not set
4446 -CONFIG_TIGON3=y
4447 +# CONFIG_TIGON3 is not set
4448  # CONFIG_BNX2 is not set
4449  CONFIG_MV643XX_ETH=y
4450  # CONFIG_QLA3XXX is not set
4451  # CONFIG_ATL1 is not set
4452 -CONFIG_NETDEV_10000=y
4453 -# CONFIG_CHELSIO_T1 is not set
4454 -# CONFIG_CHELSIO_T3 is not set
4455 -# CONFIG_IXGBE is not set
4456 -# CONFIG_IXGB is not set
4457 -# CONFIG_S2IO is not set
4458 -# CONFIG_MYRI10GE is not set
4459 -# CONFIG_NETXEN_NIC is not set
4460 -# CONFIG_NIU is not set
4461 -# CONFIG_MLX4_CORE is not set
4462 -# CONFIG_TEHUTI is not set
4463 -# CONFIG_BNX2X is not set
4464 +# CONFIG_NETDEV_10000 is not set
4465  # CONFIG_TR is not set
4466
4467  #
4468 @@ -708,6 +710,7 @@
4469  #
4470  # CONFIG_WLAN_PRE80211 is not set
4471  # CONFIG_WLAN_80211 is not set
4472 +# CONFIG_IWLWIFI_LEDS is not set
4473
4474  #
4475  # USB Network Adapters
4476 @@ -738,12 +741,9 @@
4477  #
4478  # Userland interfaces
4479  #
4480 -CONFIG_INPUT_MOUSEDEV=y
4481 -CONFIG_INPUT_MOUSEDEV_PSAUX=y
4482 -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
4483 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
4484 +# CONFIG_INPUT_MOUSEDEV is not set
4485  # CONFIG_INPUT_JOYDEV is not set
4486 -# CONFIG_INPUT_EVDEV is not set
4487 +CONFIG_INPUT_EVDEV=y
4488  # CONFIG_INPUT_EVBUG is not set
4489
4490  #
4491 @@ -765,10 +765,8 @@
4492  #
4493  # Character devices
4494  #
4495 -CONFIG_VT=y
4496 -CONFIG_VT_CONSOLE=y
4497 -CONFIG_HW_CONSOLE=y
4498 -# CONFIG_VT_HW_CONSOLE_BINDING is not set
4499 +# CONFIG_VT is not set
4500 +CONFIG_DEVKMEM=y
4501  # CONFIG_SERIAL_NONSTANDARD is not set
4502  # CONFIG_NOZOMI is not set
4503
4504 @@ -777,7 +775,7 @@
4505  #
4506  CONFIG_SERIAL_8250=y
4507  CONFIG_SERIAL_8250_CONSOLE=y
4508 -CONFIG_SERIAL_8250_PCI=y
4509 +# CONFIG_SERIAL_8250_PCI is not set
4510  CONFIG_SERIAL_8250_NR_UARTS=4
4511  CONFIG_SERIAL_8250_RUNTIME_UARTS=2
4512  # CONFIG_SERIAL_8250_EXTENDED is not set
4513 @@ -792,7 +790,7 @@
4514  CONFIG_LEGACY_PTYS=y
4515  CONFIG_LEGACY_PTY_COUNT=16
4516  # CONFIG_IPMI_HANDLER is not set
4517 -CONFIG_HW_RANDOM=m
4518 +# CONFIG_HW_RANDOM is not set
4519  # CONFIG_NVRAM is not set
4520  # CONFIG_R3964 is not set
4521  # CONFIG_APPLICOM is not set
4522 @@ -804,13 +802,6 @@
4523  CONFIG_I2C_CHARDEV=y
4524
4525  #
4526 -# I2C Algorithms
4527 -#
4528 -# CONFIG_I2C_ALGOBIT is not set
4529 -# CONFIG_I2C_ALGOPCF is not set
4530 -# CONFIG_I2C_ALGOPCA is not set
4531 -
4532 -#
4533  # I2C Hardware Bus support
4534  #
4535  # CONFIG_I2C_ALI1535 is not set
4536 @@ -837,6 +828,7 @@
4537  # CONFIG_I2C_VIA is not set
4538  # CONFIG_I2C_VIAPRO is not set
4539  # CONFIG_I2C_VOODOO3 is not set
4540 +# CONFIG_I2C_PCA_PLATFORM is not set
4541  CONFIG_I2C_MV64XXX=y
4542
4543  #
4544 @@ -847,19 +839,13 @@
4545  # CONFIG_SENSORS_PCF8574 is not set
4546  # CONFIG_PCF8575 is not set
4547  # CONFIG_SENSORS_PCF8591 is not set
4548 -# CONFIG_TPS65010 is not set
4549  # CONFIG_SENSORS_MAX6875 is not set
4550  # CONFIG_SENSORS_TSL2550 is not set
4551  # CONFIG_I2C_DEBUG_CORE is not set
4552  # CONFIG_I2C_DEBUG_ALGO is not set
4553  # CONFIG_I2C_DEBUG_BUS is not set
4554  # CONFIG_I2C_DEBUG_CHIP is not set
4555 -
4556 -#
4557 -# SPI support
4558 -#
4559  # CONFIG_SPI is not set
4560 -# CONFIG_SPI_MASTER is not set
4561  # CONFIG_W1 is not set
4562  # CONFIG_POWER_SUPPLY is not set
4563  CONFIG_HWMON=y
4564 @@ -872,6 +858,7 @@
4565  # CONFIG_SENSORS_ADM1031 is not set
4566  # CONFIG_SENSORS_ADM9240 is not set
4567  # CONFIG_SENSORS_ADT7470 is not set
4568 +# CONFIG_SENSORS_ADT7473 is not set
4569  # CONFIG_SENSORS_ATXP1 is not set
4570  # CONFIG_SENSORS_DS1621 is not set
4571  # CONFIG_SENSORS_I5K_AMB is not set
4572 @@ -901,6 +888,7 @@
4573  # CONFIG_SENSORS_SMSC47M1 is not set
4574  # CONFIG_SENSORS_SMSC47M192 is not set
4575  # CONFIG_SENSORS_SMSC47B397 is not set
4576 +# CONFIG_SENSORS_ADS7828 is not set
4577  # CONFIG_SENSORS_THMC50 is not set
4578  # CONFIG_SENSORS_VIA686A is not set
4579  # CONFIG_SENSORS_VT1211 is not set
4580 @@ -910,6 +898,7 @@
4581  # CONFIG_SENSORS_W83792D is not set
4582  # CONFIG_SENSORS_W83793 is not set
4583  # CONFIG_SENSORS_W83L785TS is not set
4584 +# CONFIG_SENSORS_W83L786NG is not set
4585  # CONFIG_SENSORS_W83627HF is not set
4586  # CONFIG_SENSORS_W83627EHF is not set
4587  # CONFIG_HWMON_DEBUG_CHIP is not set
4588 @@ -925,14 +914,24 @@
4589  # Multifunction device drivers
4590  #
4591  # CONFIG_MFD_SM501 is not set
4592 +# CONFIG_MFD_ASIC3 is not set
4593 +# CONFIG_HTC_PASIC3 is not set
4594
4595  #
4596  # Multimedia devices
4597  #
4598 +
4599 +#
4600 +# Multimedia core support
4601 +#
4602  # CONFIG_VIDEO_DEV is not set
4603  # CONFIG_DVB_CORE is not set
4604 -CONFIG_DAB=y
4605 -# CONFIG_USB_DABUSB is not set
4606 +# CONFIG_VIDEO_MEDIA is not set
4607 +
4608 +#
4609 +# Multimedia drivers
4610 +#
4611 +# CONFIG_DAB is not set
4612
4613  #
4614  # Graphics support
4615 @@ -949,12 +948,6 @@
4616  # CONFIG_DISPLAY_SUPPORT is not set
4617
4618  #
4619 -# Console display driver support
4620 -#
4621 -# CONFIG_VGA_CONSOLE is not set
4622 -CONFIG_DUMMY_CONSOLE=y
4623 -
4624 -#
4625  # Sound
4626  #
4627  # CONFIG_SOUND is not set
4628 @@ -985,14 +978,18 @@
4629  CONFIG_USB_DEVICE_CLASS=y
4630  # CONFIG_USB_DYNAMIC_MINORS is not set
4631  # CONFIG_USB_OTG is not set
4632 +# CONFIG_USB_OTG_WHITELIST is not set
4633 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
4634
4635  #
4636  # USB Host Controller Drivers
4637  #
4638 +# CONFIG_USB_C67X00_HCD is not set
4639  CONFIG_USB_EHCI_HCD=y
4640  CONFIG_USB_EHCI_ROOT_HUB_TT=y
4641  CONFIG_USB_EHCI_TT_NEWSCHED=y
4642  # CONFIG_USB_ISP116X_HCD is not set
4643 +# CONFIG_USB_ISP1760_HCD is not set
4644  # CONFIG_USB_OHCI_HCD is not set
4645  # CONFIG_USB_UHCI_HCD is not set
4646  # CONFIG_USB_SL811_HCD is not set
4647 @@ -1003,6 +1000,7 @@
4648  #
4649  # CONFIG_USB_ACM is not set
4650  CONFIG_USB_PRINTER=y
4651 +# CONFIG_USB_WDM is not set
4652
4653  #
4654  # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
4655 @@ -1022,7 +1020,9 @@
4656  CONFIG_USB_STORAGE_SDDR55=y
4657  CONFIG_USB_STORAGE_JUMPSHOT=y
4658  # CONFIG_USB_STORAGE_ALAUDA is not set
4659 +# CONFIG_USB_STORAGE_ONETOUCH is not set
4660  # CONFIG_USB_STORAGE_KARMA is not set
4661 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
4662  # CONFIG_USB_LIBUSUAL is not set
4663
4664  #
4665 @@ -1060,6 +1060,7 @@
4666  # CONFIG_USB_TRANCEVIBRATOR is not set
4667  # CONFIG_USB_IOWARRIOR is not set
4668  # CONFIG_USB_TEST is not set
4669 +# CONFIG_USB_ISIGHTFW is not set
4670  # CONFIG_USB_GADGET is not set
4671  # CONFIG_MMC is not set
4672  CONFIG_NEW_LEDS=y
4673 @@ -1076,6 +1077,7 @@
4674  CONFIG_LEDS_TRIGGERS=y
4675  CONFIG_LEDS_TRIGGER_TIMER=y
4676  CONFIG_LEDS_TRIGGER_HEARTBEAT=y
4677 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
4678  CONFIG_RTC_LIB=y
4679  CONFIG_RTC_CLASS=y
4680  CONFIG_RTC_HCTOSYS=y
4681 @@ -1105,6 +1107,7 @@
4682  # CONFIG_RTC_DRV_PCF8583 is not set
4683  CONFIG_RTC_DRV_M41T80=y
4684  # CONFIG_RTC_DRV_M41T80_WDT is not set
4685 +# CONFIG_RTC_DRV_S35390A is not set
4686
4687  #
4688  # SPI RTC drivers
4689 @@ -1125,6 +1128,7 @@
4690  #
4691  # on-CPU RTC drivers
4692  #
4693 +# CONFIG_UIO is not set
4694
4695  #
4696  # File systems
4697 @@ -1140,14 +1144,11 @@
4698  # CONFIG_JFS_FS is not set
4699  # CONFIG_FS_POSIX_ACL is not set
4700  # CONFIG_XFS_FS is not set
4701 -# CONFIG_GFS2_FS is not set
4702  # CONFIG_OCFS2_FS is not set
4703 -# CONFIG_MINIX_FS is not set
4704 -# CONFIG_ROMFS_FS is not set
4705 +CONFIG_DNOTIFY=y
4706  CONFIG_INOTIFY=y
4707  CONFIG_INOTIFY_USER=y
4708  # CONFIG_QUOTA is not set
4709 -CONFIG_DNOTIFY=y
4710  # CONFIG_AUTOFS_FS is not set
4711  # CONFIG_AUTOFS4_FS is not set
4712  # CONFIG_FUSE_FS is not set
4713 @@ -1155,8 +1156,8 @@
4714  #
4715  # CD-ROM/DVD Filesystems
4716  #
4717 -CONFIG_ISO9660_FS=y
4718 -# CONFIG_JOLIET is not set
4719 +CONFIG_ISO9660_FS=m
4720 +CONFIG_JOLIET=y
4721  # CONFIG_ZISOFS is not set
4722  CONFIG_UDF_FS=m
4723  CONFIG_UDF_NLS=y
4724 @@ -1205,8 +1206,10 @@
4725  # CONFIG_JFFS2_RUBIN is not set
4726  CONFIG_CRAMFS=y
4727  # CONFIG_VXFS_FS is not set
4728 +# CONFIG_MINIX_FS is not set
4729  # CONFIG_HPFS_FS is not set
4730  # CONFIG_QNX4FS_FS is not set
4731 +# CONFIG_ROMFS_FS is not set
4732  # CONFIG_SYSV_FS is not set
4733  # CONFIG_UFS_FS is not set
4734  CONFIG_NETWORK_FILESYSTEMS=y
4735 @@ -1214,7 +1217,6 @@
4736  CONFIG_NFS_V3=y
4737  # CONFIG_NFS_V3_ACL is not set
4738  # CONFIG_NFS_V4 is not set
4739 -# CONFIG_NFS_DIRECTIO is not set
4740  # CONFIG_NFSD is not set
4741  CONFIG_ROOT_NFS=y
4742  CONFIG_LOCKD=y
4743 @@ -1241,14 +1243,13 @@
4744  # CONFIG_MAC_PARTITION is not set
4745  CONFIG_MSDOS_PARTITION=y
4746  CONFIG_BSD_DISKLABEL=y
4747 -CONFIG_MINIX_SUBPARTITION=y
4748 -CONFIG_SOLARIS_X86_PARTITION=y
4749 -CONFIG_UNIXWARE_DISKLABEL=y
4750 -CONFIG_LDM_PARTITION=y
4751 -CONFIG_LDM_DEBUG=y
4752 +# CONFIG_MINIX_SUBPARTITION is not set
4753 +# CONFIG_SOLARIS_X86_PARTITION is not set
4754 +# CONFIG_UNIXWARE_DISKLABEL is not set
4755 +# CONFIG_LDM_PARTITION is not set
4756  # CONFIG_SGI_PARTITION is not set
4757  # CONFIG_ULTRIX_PARTITION is not set
4758 -CONFIG_SUN_PARTITION=y
4759 +# CONFIG_SUN_PARTITION is not set
4760  # CONFIG_KARMA_PARTITION is not set
4761  # CONFIG_EFI_PARTITION is not set
4762  # CONFIG_SYSV68_PARTITION is not set
4763 @@ -1300,15 +1301,48 @@
4764  # CONFIG_PRINTK_TIME is not set
4765  CONFIG_ENABLE_WARN_DEPRECATED=y
4766  CONFIG_ENABLE_MUST_CHECK=y
4767 -# CONFIG_MAGIC_SYSRQ is not set
4768 +CONFIG_FRAME_WARN=1024
4769 +CONFIG_MAGIC_SYSRQ=y
4770  # CONFIG_UNUSED_SYMBOLS is not set
4771  # CONFIG_DEBUG_FS is not set
4772  # CONFIG_HEADERS_CHECK is not set
4773 -# CONFIG_DEBUG_KERNEL is not set
4774 +CONFIG_DEBUG_KERNEL=y
4775 +# CONFIG_DEBUG_SHIRQ is not set
4776 +CONFIG_DETECT_SOFTLOCKUP=y
4777 +CONFIG_SCHED_DEBUG=y
4778 +CONFIG_SCHEDSTATS=y
4779 +# CONFIG_TIMER_STATS is not set
4780 +# CONFIG_DEBUG_OBJECTS is not set
4781 +CONFIG_DEBUG_PREEMPT=y
4782 +# CONFIG_DEBUG_RT_MUTEXES is not set
4783 +# CONFIG_RT_MUTEX_TESTER is not set
4784 +# CONFIG_DEBUG_SPINLOCK is not set
4785 +# CONFIG_DEBUG_MUTEXES is not set
4786 +# CONFIG_DEBUG_LOCK_ALLOC is not set
4787 +# CONFIG_PROVE_LOCKING is not set
4788 +# CONFIG_LOCK_STAT is not set
4789 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
4790 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
4791 +# CONFIG_DEBUG_KOBJECT is not set
4792  # CONFIG_DEBUG_BUGVERBOSE is not set
4793 +CONFIG_DEBUG_INFO=y
4794 +# CONFIG_DEBUG_VM is not set
4795 +# CONFIG_DEBUG_WRITECOUNT is not set
4796 +# CONFIG_DEBUG_LIST is not set
4797 +# CONFIG_DEBUG_SG is not set
4798  CONFIG_FRAME_POINTER=y
4799 +# CONFIG_BOOT_PRINTK_DELAY is not set
4800 +# CONFIG_RCU_TORTURE_TEST is not set
4801 +# CONFIG_KPROBES_SANITY_TEST is not set
4802 +# CONFIG_BACKTRACE_SELF_TEST is not set
4803 +# CONFIG_LKDTM is not set
4804 +# CONFIG_FAULT_INJECTION is not set
4805  # CONFIG_SAMPLES is not set
4806  CONFIG_DEBUG_USER=y
4807 +CONFIG_DEBUG_ERRORS=y
4808 +# CONFIG_DEBUG_STACK_USAGE is not set
4809 +CONFIG_DEBUG_LL=y
4810 +# CONFIG_DEBUG_ICEDCC is not set
4811
4812  #
4813  # Security options
4814 @@ -1317,50 +1351,79 @@
4815  # CONFIG_SECURITY is not set
4816  # CONFIG_SECURITY_FILE_CAPABILITIES is not set
4817  CONFIG_CRYPTO=y
4818 +
4819 +#
4820 +# Crypto core or helper
4821 +#
4822  CONFIG_CRYPTO_ALGAPI=m
4823  CONFIG_CRYPTO_BLKCIPHER=m
4824 -# CONFIG_CRYPTO_SEQIV is not set
4825  CONFIG_CRYPTO_MANAGER=m
4826 +# CONFIG_CRYPTO_GF128MUL is not set
4827 +# CONFIG_CRYPTO_NULL is not set
4828 +# CONFIG_CRYPTO_CRYPTD is not set
4829 +# CONFIG_CRYPTO_AUTHENC is not set
4830 +# CONFIG_CRYPTO_TEST is not set
4831 +
4832 +#
4833 +# Authenticated Encryption with Associated Data
4834 +#
4835 +# CONFIG_CRYPTO_CCM is not set
4836 +# CONFIG_CRYPTO_GCM is not set
4837 +# CONFIG_CRYPTO_SEQIV is not set
4838 +
4839 +#
4840 +# Block modes
4841 +#
4842 +CONFIG_CRYPTO_CBC=m
4843 +# CONFIG_CRYPTO_CTR is not set
4844 +# CONFIG_CRYPTO_CTS is not set
4845 +CONFIG_CRYPTO_ECB=m
4846 +# CONFIG_CRYPTO_LRW is not set
4847 +CONFIG_CRYPTO_PCBC=m
4848 +# CONFIG_CRYPTO_XTS is not set
4849 +
4850 +#
4851 +# Hash modes
4852 +#
4853  # CONFIG_CRYPTO_HMAC is not set
4854  # CONFIG_CRYPTO_XCBC is not set
4855 -# CONFIG_CRYPTO_NULL is not set
4856 +
4857 +#
4858 +# Digest
4859 +#
4860 +# CONFIG_CRYPTO_CRC32C is not set
4861  # CONFIG_CRYPTO_MD4 is not set
4862  # CONFIG_CRYPTO_MD5 is not set
4863 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
4864  # CONFIG_CRYPTO_SHA1 is not set
4865  # CONFIG_CRYPTO_SHA256 is not set
4866  # CONFIG_CRYPTO_SHA512 is not set
4867 -# CONFIG_CRYPTO_WP512 is not set
4868  # CONFIG_CRYPTO_TGR192 is not set
4869 -# CONFIG_CRYPTO_GF128MUL is not set
4870 -CONFIG_CRYPTO_ECB=m
4871 -CONFIG_CRYPTO_CBC=m
4872 -CONFIG_CRYPTO_PCBC=m
4873 -# CONFIG_CRYPTO_LRW is not set
4874 -# CONFIG_CRYPTO_XTS is not set
4875 -# CONFIG_CRYPTO_CTR is not set
4876 -# CONFIG_CRYPTO_GCM is not set
4877 -# CONFIG_CRYPTO_CCM is not set
4878 -# CONFIG_CRYPTO_CRYPTD is not set
4879 -# CONFIG_CRYPTO_DES is not set
4880 -# CONFIG_CRYPTO_FCRYPT is not set
4881 -# CONFIG_CRYPTO_BLOWFISH is not set
4882 -# CONFIG_CRYPTO_TWOFISH is not set
4883 -# CONFIG_CRYPTO_SERPENT is not set
4884 +# CONFIG_CRYPTO_WP512 is not set
4885 +
4886 +#
4887 +# Ciphers
4888 +#
4889  # CONFIG_CRYPTO_AES is not set
4890 +# CONFIG_CRYPTO_ANUBIS is not set
4891 +# CONFIG_CRYPTO_ARC4 is not set
4892 +# CONFIG_CRYPTO_BLOWFISH is not set
4893 +# CONFIG_CRYPTO_CAMELLIA is not set
4894  # CONFIG_CRYPTO_CAST5 is not set
4895  # CONFIG_CRYPTO_CAST6 is not set
4896 -# CONFIG_CRYPTO_TEA is not set
4897 -# CONFIG_CRYPTO_ARC4 is not set
4898 +# CONFIG_CRYPTO_DES is not set
4899 +# CONFIG_CRYPTO_FCRYPT is not set
4900  # CONFIG_CRYPTO_KHAZAD is not set
4901 -# CONFIG_CRYPTO_ANUBIS is not set
4902 -# CONFIG_CRYPTO_SEED is not set
4903  # CONFIG_CRYPTO_SALSA20 is not set
4904 +# CONFIG_CRYPTO_SEED is not set
4905 +# CONFIG_CRYPTO_SERPENT is not set
4906 +# CONFIG_CRYPTO_TEA is not set
4907 +# CONFIG_CRYPTO_TWOFISH is not set
4908 +
4909 +#
4910 +# Compression
4911 +#
4912  # CONFIG_CRYPTO_DEFLATE is not set
4913 -# CONFIG_CRYPTO_MICHAEL_MIC is not set
4914 -# CONFIG_CRYPTO_CRC32C is not set
4915 -# CONFIG_CRYPTO_CAMELLIA is not set
4916 -# CONFIG_CRYPTO_TEST is not set
4917 -# CONFIG_CRYPTO_AUTHENC is not set
4918  # CONFIG_CRYPTO_LZO is not set
4919  CONFIG_CRYPTO_HW=y
4920  # CONFIG_CRYPTO_DEV_HIFN_795X is not set
4921 @@ -1369,12 +1432,14 @@
4922  # Library routines
4923  #
4924  CONFIG_BITREVERSE=y
4925 -CONFIG_CRC_CCITT=y
4926 -CONFIG_CRC16=y
4927 -# CONFIG_CRC_ITU_T is not set
4928 +# CONFIG_GENERIC_FIND_FIRST_BIT is not set
4929 +# CONFIG_GENERIC_FIND_NEXT_BIT is not set
4930 +# CONFIG_CRC_CCITT is not set
4931 +# CONFIG_CRC16 is not set
4932 +CONFIG_CRC_ITU_T=m
4933  CONFIG_CRC32=y
4934  # CONFIG_CRC7 is not set
4935 -CONFIG_LIBCRC32C=y
4936 +# CONFIG_LIBCRC32C is not set
4937  CONFIG_ZLIB_INFLATE=y
4938  CONFIG_ZLIB_DEFLATE=y
4939  CONFIG_PLIST=y
4940 --- a/arch/arm/kernel/stacktrace.c
4941 +++ b/arch/arm/kernel/stacktrace.c
4942 @@ -36,6 +36,7 @@
4943  #ifdef CONFIG_STACKTRACE
4944  struct stack_trace_data {
4945         struct stack_trace *trace;
4946 +       unsigned int no_sched_functions;
4947         unsigned int skip;
4948  };
4949
4950 @@ -43,27 +44,52 @@
4951  {
4952         struct stack_trace_data *data = d;
4953         struct stack_trace *trace = data->trace;
4954 +       unsigned long addr = frame->lr;
4955
4956 +       if (data->no_sched_functions && in_sched_functions(addr))
4957 +               return 0;
4958         if (data->skip) {
4959                 data->skip--;
4960                 return 0;
4961         }
4962
4963 -       trace->entries[trace->nr_entries++] = frame->lr;
4964 +       trace->entries[trace->nr_entries++] = addr;
4965
4966         return trace->nr_entries >= trace->max_entries;
4967  }
4968
4969 -void save_stack_trace(struct stack_trace *trace)
4970 +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
4971  {
4972         struct stack_trace_data data;
4973         unsigned long fp, base;
4974
4975         data.trace = trace;
4976         data.skip = trace->skip;
4977 -       base = (unsigned long)task_stack_page(current);
4978 -       asm("mov %0, fp" : "=r" (fp));
4979 +       base = (unsigned long)task_stack_page(tsk);
4980 +
4981 +       if (tsk != current) {
4982 +#ifdef CONFIG_SMP
4983 +               /*
4984 +                * What guarantees do we have here that 'tsk'
4985 +                * is not running on another CPU?
4986 +                */
4987 +               BUG();
4988 +#else
4989 +               data.no_sched_functions = 1;
4990 +               fp = thread_saved_fp(tsk);
4991 +#endif
4992 +       } else {
4993 +               data.no_sched_functions = 0;
4994 +               asm("mov %0, fp" : "=r" (fp));
4995 +       }
4996
4997         walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
4998 +       if (trace->nr_entries < trace->max_entries)
4999 +               trace->entries[trace->nr_entries++] = ULONG_MAX;
5000 +}
5001 +
5002 +void save_stack_trace(struct stack_trace *trace)
5003 +{
5004 +       save_stack_trace_tsk(current, trace);
5005  }
5006  #endif
5007 --- a/arch/arm/lib/copy_template.S
5008 +++ b/arch/arm/lib/copy_template.S
5009 @@ -13,14 +13,6 @@
5010   */
5011
5012  /*
5013 - * This can be used to enable code to cacheline align the source pointer.
5014 - * Experiments on tested architectures (StrongARM and XScale) didn't show
5015 - * this a worthwhile thing to do.  That might be different in the future.
5016 - */
5017 -//#define CALGN(code...)       code
5018 -#define CALGN(code...)
5019 -
5020 -/*
5021   * Theory of operation
5022   * -------------------
5023   *
5024 @@ -82,7 +74,7 @@
5025                 stmfd   sp!, {r5 - r8}
5026                 blt     5f
5027
5028 -       CALGN(  ands    ip, r1, #31             )
5029 +       CALGN(  ands    ip, r0, #31             )
5030         CALGN(  rsb     r3, ip, #32             )
5031         CALGN(  sbcnes  r4, r3, r2              )  @ C is always set here
5032         CALGN(  bcs     2f                      )
5033 @@ -168,7 +160,7 @@
5034                 subs    r2, r2, #28
5035                 blt     14f
5036
5037 -       CALGN(  ands    ip, r1, #31             )
5038 +       CALGN(  ands    ip, r0, #31             )
5039         CALGN(  rsb     ip, ip, #32             )
5040         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
5041         CALGN(  subcc   r2, r2, ip              )
5042 --- a/arch/arm/lib/memmove.S
5043 +++ b/arch/arm/lib/memmove.S
5044 @@ -13,14 +13,6 @@
5045  #include <linux/linkage.h>
5046  #include <asm/assembler.h>
5047
5048 -/*
5049 - * This can be used to enable code to cacheline align the source pointer.
5050 - * Experiments on tested architectures (StrongARM and XScale) didn't show
5051 - * this a worthwhile thing to do.  That might be different in the future.
5052 - */
5053 -//#define CALGN(code...)        code
5054 -#define CALGN(code...)
5055 -
5056                 .text
5057
5058  /*
5059 @@ -55,11 +47,12 @@
5060                 stmfd   sp!, {r5 - r8}
5061                 blt     5f
5062
5063 -       CALGN(  ands    ip, r1, #31             )
5064 +       CALGN(  ands    ip, r0, #31             )
5065         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
5066         CALGN(  bcs     2f                      )
5067         CALGN(  adr     r4, 6f                  )
5068         CALGN(  subs    r2, r2, ip              )  @ C is set here
5069 +       CALGN(  rsb     ip, ip, #32             )
5070         CALGN(  add     pc, r4, ip              )
5071
5072         PLD(    pld     [r1, #-4]               )
5073 @@ -138,8 +131,7 @@
5074                 subs    r2, r2, #28
5075                 blt     14f
5076
5077 -       CALGN(  ands    ip, r1, #31             )
5078 -       CALGN(  rsb     ip, ip, #32             )
5079 +       CALGN(  ands    ip, r0, #31             )
5080         CALGN(  sbcnes  r4, ip, r2              )  @ C is always set here
5081         CALGN(  subcc   r2, r2, ip              )
5082         CALGN(  bcc     15f                     )
5083 --- a/arch/arm/lib/memset.S
5084 +++ b/arch/arm/lib/memset.S
5085 @@ -39,6 +39,9 @@
5086         mov     r3, r1
5087         cmp     r2, #16
5088         blt     4f
5089 +
5090 +#if ! CALGN(1)+0
5091 +
5092  /*
5093   * We need an extra register for this loop - save the return address and
5094   * use the LR
5095 @@ -64,6 +67,49 @@
5096         stmneia r0!, {r1, r3, ip, lr}
5097         ldr     lr, [sp], #4
5098
5099 +#else
5100 +
5101 +/*
5102 + * This version aligns the destination pointer in order to write
5103 + * whole cache lines at once.
5104 + */
5105 +
5106 +       stmfd   sp!, {r4-r7, lr}
5107 +       mov     r4, r1
5108 +       mov     r5, r1
5109 +       mov     r6, r1
5110 +       mov     r7, r1
5111 +       mov     ip, r1
5112 +       mov     lr, r1
5113 +
5114 +       cmp     r2, #96
5115 +       tstgt   r0, #31
5116 +       ble     3f
5117 +
5118 +       and     ip, r0, #31
5119 +       rsb     ip, ip, #32
5120 +       sub     r2, r2, ip
5121 +       movs    ip, ip, lsl #(32 - 4)
5122 +       stmcsia r0!, {r4, r5, r6, r7}
5123 +       stmmiia r0!, {r4, r5}
5124 +       tst     ip, #(1 << 30)
5125 +       mov     ip, r1
5126 +       strne   r1, [r0], #4
5127 +
5128 +3:     subs    r2, r2, #64
5129 +       stmgeia r0!, {r1, r3-r7, ip, lr}
5130 +       stmgeia r0!, {r1, r3-r7, ip, lr}
5131 +       bgt     3b
5132 +       ldmeqfd sp!, {r4-r7, pc}
5133 +
5134 +       tst     r2, #32
5135 +       stmneia r0!, {r1, r3-r7, ip, lr}
5136 +       tst     r2, #16
5137 +       stmneia r0!, {r4-r7}
5138 +       ldmfd   sp!, {r4-r7, lr}
5139 +
5140 +#endif
5141 +
5142  4:     tst     r2, #8
5143         stmneia r0!, {r1, r3}
5144         tst     r2, #4
5145 --- a/arch/arm/lib/memzero.S
5146 +++ b/arch/arm/lib/memzero.S
5147 @@ -39,6 +39,9 @@
5148   */
5149         cmp     r1, #16                 @ 1 we can skip this chunk if we
5150         blt     4f                      @ 1 have < 16 bytes
5151 +
5152 +#if ! CALGN(1)+0
5153 +
5154  /*
5155   * We need an extra register for this loop - save the return address and
5156   * use the LR
5157 @@ -64,6 +67,47 @@
5158         stmneia r0!, {r2, r3, ip, lr}   @ 4
5159         ldr     lr, [sp], #4            @ 1
5160
5161 +#else
5162 +
5163 +/*
5164 + * This version aligns the destination pointer in order to write
5165 + * whole cache lines at once.
5166 + */
5167 +
5168 +       stmfd   sp!, {r4-r7, lr}
5169 +       mov     r4, r2
5170 +       mov     r5, r2
5171 +       mov     r6, r2
5172 +       mov     r7, r2
5173 +       mov     ip, r2
5174 +       mov     lr, r2
5175 +
5176 +       cmp     r1, #96
5177 +       andgts  ip, r0, #31
5178 +       ble     3f
5179 +
5180 +       rsb     ip, ip, #32
5181 +       sub     r1, r1, ip
5182 +       movs    ip, ip, lsl #(32 - 4)
5183 +       stmcsia r0!, {r4, r5, r6, r7}
5184 +       stmmiia r0!, {r4, r5}
5185 +       movs    ip, ip, lsl #2
5186 +       strcs   r2, [r0], #4
5187 +
5188 +3:     subs    r1, r1, #64
5189 +       stmgeia r0!, {r2-r7, ip, lr}
5190 +       stmgeia r0!, {r2-r7, ip, lr}
5191 +       bgt     3b
5192 +       ldmeqfd sp!, {r4-r7, pc}
5193 +
5194 +       tst     r1, #32
5195 +       stmneia r0!, {r2-r7, ip, lr}
5196 +       tst     r1, #16
5197 +       stmneia r0!, {r4-r7}
5198 +       ldmfd   sp!, {r4-r7, lr}
5199 +
5200 +#endif
5201 +
5202  4:     tst     r1, #8                  @ 1 8 bytes or more?
5203         stmneia r0!, {r2, r3}           @ 2
5204         tst     r1, #4                  @ 1 4 bytes or more?
5205 --- /dev/null
5206 +++ b/arch/arm/mach-kirkwood/Kconfig
5207 @@ -0,0 +1,25 @@
5208 +if ARCH_KIRKWOOD
5209 +
5210 +menu "Marvell Kirkwood Implementations"
5211 +
5212 +config MACH_DB88F6281_BP
5213 +       bool "Marvell DB-88F6281-BP Development Board"
5214 +       help
5215 +         Say 'Y' here if you want your kernel to support the
5216 +         Marvell DB-88F6281-BP Development Board.
5217 +
5218 +config MACH_RD88F6192_NAS
5219 +       bool "Marvell RD-88F6192-NAS Reference Board"
5220 +       help
5221 +         Say 'Y' here if you want your kernel to support the
5222 +         Marvell RD-88F6192-NAS Reference Board.
5223 +
5224 +config MACH_RD88F6281
5225 +       bool "Marvell RD-88F6281 Reference Board"
5226 +       help
5227 +         Say 'Y' here if you want your kernel to support the
5228 +         Marvell RD-88F6281 Reference Board.
5229 +
5230 +endmenu
5231 +
5232 +endif
5233 --- /dev/null
5234 +++ b/arch/arm/mach-kirkwood/Makefile
5235 @@ -0,0 +1,5 @@
5236 +obj-y                          += common.o addr-map.o irq.o pcie.o
5237 +
5238 +obj-$(CONFIG_MACH_DB88F6281_BP)                += db88f6281-bp-setup.o
5239 +obj-$(CONFIG_MACH_RD88F6192_NAS)       += rd88f6192-nas-setup.o
5240 +obj-$(CONFIG_MACH_RD88F6192_NAS)       += rd88f6281-setup.o
5241 --- /dev/null
5242 +++ b/arch/arm/mach-kirkwood/Makefile.boot
5243 @@ -0,0 +1,3 @@
5244 +   zreladdr-y  := 0x00008000
5245 +params_phys-y  := 0x00000100
5246 +initrd_phys-y  := 0x00800000
5247 --- /dev/null
5248 +++ b/arch/arm/mach-kirkwood/addr-map.c
5249 @@ -0,0 +1,139 @@
5250 +/*
5251 + * arch/arm/mach-kirkwood/addr-map.c
5252 + *
5253 + * Address map functions for Marvell Kirkwood SoCs
5254 + *
5255 + * This file is licensed under the terms of the GNU General Public
5256 + * License version 2.  This program is licensed "as is" without any
5257 + * warranty of any kind, whether express or implied.
5258 + */
5259 +
5260 +#include <linux/kernel.h>
5261 +#include <linux/init.h>
5262 +#include <linux/mbus.h>
5263 +#include <linux/io.h>
5264 +#include <asm/hardware.h>
5265 +#include "common.h"
5266 +
5267 +/*
5268 + * Generic Address Decode Windows bit settings
5269 + */
5270 +#define TARGET_DDR             0
5271 +#define TARGET_DEV_BUS         1
5272 +#define TARGET_PCIE            4
5273 +#define ATTR_DEV_SPI_ROM       0x1e
5274 +#define ATTR_DEV_BOOT          0x1d
5275 +#define ATTR_DEV_NAND          0x2f
5276 +#define ATTR_DEV_CS3           0x37
5277 +#define ATTR_DEV_CS2           0x3b
5278 +#define ATTR_DEV_CS1           0x3d
5279 +#define ATTR_DEV_CS0           0x3e
5280 +#define ATTR_PCIE_IO           0xe0
5281 +#define ATTR_PCIE_MEM          0xe8
5282 +
5283 +/*
5284 + * Helpers to get DDR bank info
5285 + */
5286 +#define DDR_BASE_CS_OFF(n)     (0x0000 + ((n) << 3))
5287 +#define DDR_SIZE_CS_OFF(n)     (0x0004 + ((n) << 3))
5288 +
5289 +/*
5290 + * CPU Address Decode Windows registers
5291 + */
5292 +#define WIN_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
5293 +#define WIN_CTRL_OFF           0x0000
5294 +#define WIN_BASE_OFF           0x0004
5295 +#define WIN_REMAP_LO_OFF       0x0008
5296 +#define WIN_REMAP_HI_OFF       0x000c
5297 +
5298 +
5299 +struct mbus_dram_target_info kirkwood_mbus_dram_info;
5300 +
5301 +static int __init cpu_win_can_remap(int win)
5302 +{
5303 +       if (win < 4)
5304 +               return 1;
5305 +
5306 +       return 0;
5307 +}
5308 +
5309 +static void __init setup_cpu_win(int win, u32 base, u32 size,
5310 +                                u8 target, u8 attr, int remap)
5311 +{
5312 +       void __iomem *addr = (void __iomem *)WIN_OFF(win);
5313 +       u32 ctrl;
5314 +
5315 +       base &= 0xffff0000;
5316 +       ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
5317 +
5318 +       writel(base, addr + WIN_BASE_OFF);
5319 +       writel(ctrl, addr + WIN_CTRL_OFF);
5320 +       if (cpu_win_can_remap(win)) {
5321 +               if (remap < 0)
5322 +                       remap = base;
5323 +
5324 +               writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
5325 +               writel(0, addr + WIN_REMAP_HI_OFF);
5326 +       }
5327 +}
5328 +
5329 +void __init kirkwood_setup_cpu_mbus(void)
5330 +{
5331 +       void __iomem *addr;
5332 +       int i;
5333 +       int cs;
5334 +
5335 +       /*
5336 +        * First, disable and clear windows.
5337 +        */
5338 +       for (i = 0; i < 8; i++) {
5339 +               addr = (void __iomem *)WIN_OFF(i);
5340 +
5341 +               writel(0, addr + WIN_BASE_OFF);
5342 +               writel(0, addr + WIN_CTRL_OFF);
5343 +               if (cpu_win_can_remap(i)) {
5344 +                       writel(0, addr + WIN_REMAP_LO_OFF);
5345 +                       writel(0, addr + WIN_REMAP_HI_OFF);
5346 +               }
5347 +       }
5348 +
5349 +       /*
5350 +        * Setup windows for PCIe IO+MEM space.
5351 +        */
5352 +       setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
5353 +                     TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
5354 +       setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
5355 +                     TARGET_PCIE, ATTR_PCIE_MEM, -1);
5356 +
5357 +       /*
5358 +        * Setup window for NAND controller.
5359 +        */
5360 +       setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
5361 +                     TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
5362 +
5363 +       /*
5364 +        * Setup MBUS dram target info.
5365 +        */
5366 +       kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
5367 +
5368 +       addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
5369 +
5370 +       for (i = 0, cs = 0; i < 4; i++) {
5371 +               u32 base = readl(addr + DDR_BASE_CS_OFF(i));
5372 +               u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
5373 +
5374 +               /*
5375 +                * Chip select enabled?
5376 +                */
5377 +               if (size & 1) {
5378 +                       struct mbus_dram_window *w;
5379 +
5380 +                       w = &kirkwood_mbus_dram_info.cs[cs++];
5381 +                       w->cs_index = i;
5382 +                       w->mbus_attr = 0xf & ~(1 << i);
5383 +                       w->base = base & 0xffff0000;
5384 +                       w->size = (size | 0x0000ffff) + 1;
5385 +               }
5386 +       }
5387 +       kirkwood_mbus_dram_info.num_cs = cs;
5388 +}
5389 --- /dev/null
5390 +++ b/arch/arm/mach-kirkwood/common.c
5391 @@ -0,0 +1,326 @@
5392 +/*
5393 + * arch/arm/mach-kirkwood/common.c
5394 + *
5395 + * Core functions for Marvell Kirkwood SoCs
5396 + *
5397 + * This file is licensed under the terms of the GNU General Public
5398 + * License version 2.  This program is licensed "as is" without any
5399 + * warranty of any kind, whether express or implied.
5400 + */
5401 +
5402 +#include <linux/kernel.h>
5403 +#include <linux/init.h>
5404 +#include <linux/platform_device.h>
5405 +#include <linux/serial_8250.h>
5406 +#include <linux/mbus.h>
5407 +#include <linux/mv643xx_eth.h>
5408 +#include <linux/ata_platform.h>
5409 +#include <asm/page.h>
5410 +#include <asm/timex.h>
5411 +#include <asm/mach/map.h>
5412 +#include <asm/mach/time.h>
5413 +#include <asm/arch/kirkwood.h>
5414 +#include <asm/plat-orion/cache-feroceon-l2.h>
5415 +#include <asm/plat-orion/ehci-orion.h>
5416 +#include <asm/plat-orion/orion_nand.h>
5417 +#include <asm/plat-orion/time.h>
5418 +#include "common.h"
5419 +
5420 +/*****************************************************************************
5421 + * I/O Address Mapping
5422 + ****************************************************************************/
5423 +static struct map_desc kirkwood_io_desc[] __initdata = {
5424 +       {
5425 +               .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
5426 +               .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
5427 +               .length         = KIRKWOOD_PCIE_IO_SIZE,
5428 +               .type           = MT_DEVICE,
5429 +       }, {
5430 +               .virtual        = KIRKWOOD_REGS_VIRT_BASE,
5431 +               .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
5432 +               .length         = KIRKWOOD_REGS_SIZE,
5433 +               .type           = MT_DEVICE,
5434 +       },
5435 +};
5436 +
5437 +void __init kirkwood_map_io(void)
5438 +{
5439 +       iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
5440 +}
5441 +
5442 +
5443 +/*****************************************************************************
5444 + * EHCI
5445 + ****************************************************************************/
5446 +static struct orion_ehci_data kirkwood_ehci_data = {
5447 +       .dram           = &kirkwood_mbus_dram_info,
5448 +};
5449 +
5450 +static u64 ehci_dmamask = 0xffffffffUL;
5451 +
5452 +
5453 +/*****************************************************************************
5454 + * EHCI0
5455 + ****************************************************************************/
5456 +static struct resource kirkwood_ehci_resources[] = {
5457 +       {
5458 +               .start  = USB_PHYS_BASE,
5459 +               .end    = USB_PHYS_BASE + 0x0fff,
5460 +               .flags  = IORESOURCE_MEM,
5461 +       }, {
5462 +               .start  = IRQ_KIRKWOOD_USB,
5463 +               .end    = IRQ_KIRKWOOD_USB,
5464 +               .flags  = IORESOURCE_IRQ,
5465 +       },
5466 +};
5467 +
5468 +static struct platform_device kirkwood_ehci = {
5469 +       .name           = "orion-ehci",
5470 +       .id             = 0,
5471 +       .dev            = {
5472 +               .dma_mask               = &ehci_dmamask,
5473 +               .coherent_dma_mask      = 0xffffffff,
5474 +               .platform_data          = &kirkwood_ehci_data,
5475 +       },
5476 +       .resource       = kirkwood_ehci_resources,
5477 +       .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
5478 +};
5479 +
5480 +void __init kirkwood_ehci_init(void)
5481 +{
5482 +       platform_device_register(&kirkwood_ehci);
5483 +}
5484 +
5485 +
5486 +/*****************************************************************************
5487 + * GE00
5488 + ****************************************************************************/
5489 +struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
5490 +       .t_clk          = KIRKWOOD_TCLK,
5491 +       .dram           = &kirkwood_mbus_dram_info,
5492 +};
5493 +
5494 +static struct resource kirkwood_ge00_shared_resources[] = {
5495 +       {
5496 +               .name   = "ge00 base",
5497 +               .start  = GE00_PHYS_BASE + 0x2000,
5498 +               .end    = GE00_PHYS_BASE + 0x3fff,
5499 +               .flags  = IORESOURCE_MEM,
5500 +       },
5501 +};
5502 +
5503 +static struct platform_device kirkwood_ge00_shared = {
5504 +       .name           = MV643XX_ETH_SHARED_NAME,
5505 +       .id             = 0,
5506 +       .dev            = {
5507 +               .platform_data  = &kirkwood_ge00_shared_data,
5508 +       },
5509 +       .num_resources  = 1,
5510 +       .resource       = kirkwood_ge00_shared_resources,
5511 +};
5512 +
5513 +static struct resource kirkwood_ge00_resources[] = {
5514 +       {
5515 +               .name   = "ge00 irq",
5516 +               .start  = IRQ_KIRKWOOD_GE00_SUM,
5517 +               .end    = IRQ_KIRKWOOD_GE00_SUM,
5518 +               .flags  = IORESOURCE_IRQ,
5519 +       },
5520 +};
5521 +
5522 +static struct platform_device kirkwood_ge00 = {
5523 +       .name           = MV643XX_ETH_NAME,
5524 +       .id             = 0,
5525 +       .num_resources  = 1,
5526 +       .resource       = kirkwood_ge00_resources,
5527 +};
5528 +
5529 +void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
5530 +{
5531 +       eth_data->shared = &kirkwood_ge00_shared;
5532 +       kirkwood_ge00.dev.platform_data = eth_data;
5533 +
5534 +       platform_device_register(&kirkwood_ge00_shared);
5535 +       platform_device_register(&kirkwood_ge00);
5536 +}
5537 +
5538 +
5539 +/*****************************************************************************
5540 + * SoC RTC
5541 + ****************************************************************************/
5542 +static struct resource kirkwood_rtc_resource = {
5543 +       .start  = RTC_PHYS_BASE,
5544 +       .end    = RTC_PHYS_BASE + SZ_16 - 1,
5545 +       .flags  = IORESOURCE_MEM,
5546 +};
5547 +
5548 +void __init kirkwood_rtc_init(void)
5549 +{
5550 +       platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
5551 +}
5552 +
5553 +
5554 +/*****************************************************************************
5555 + * SATA
5556 + ****************************************************************************/
5557 +static struct resource kirkwood_sata_resources[] = {
5558 +       {
5559 +               .name   = "sata base",
5560 +               .start  = SATA_PHYS_BASE,
5561 +               .end    = SATA_PHYS_BASE + 0x5000 - 1,
5562 +               .flags  = IORESOURCE_MEM,
5563 +       }, {
5564 +               .name   = "sata irq",
5565 +               .start  = IRQ_KIRKWOOD_SATA,
5566 +               .end    = IRQ_KIRKWOOD_SATA,
5567 +               .flags  = IORESOURCE_IRQ,
5568 +       },
5569 +};
5570 +
5571 +static struct platform_device kirkwood_sata = {
5572 +       .name           = "sata_mv",
5573 +       .id             = 0,
5574 +       .dev            = {
5575 +               .coherent_dma_mask      = 0xffffffff,
5576 +       },
5577 +       .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
5578 +       .resource       = kirkwood_sata_resources,
5579 +};
5580 +
5581 +void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
5582 +{
5583 +       sata_data->dram = &kirkwood_mbus_dram_info;
5584 +       kirkwood_sata.dev.platform_data = sata_data;
5585 +       platform_device_register(&kirkwood_sata);
5586 +}
5587 +
5588 +
5589 +/*****************************************************************************
5590 + * UART0
5591 + ****************************************************************************/
5592 +static struct plat_serial8250_port kirkwood_uart0_data[] = {
5593 +       {
5594 +               .mapbase        = UART0_PHYS_BASE,
5595 +               .membase        = (char *)UART0_VIRT_BASE,
5596 +               .irq            = IRQ_KIRKWOOD_UART_0,
5597 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
5598 +               .iotype         = UPIO_MEM,
5599 +               .regshift       = 2,
5600 +               .uartclk        = KIRKWOOD_TCLK,
5601 +       }, {
5602 +       },
5603 +};
5604 +
5605 +static struct resource kirkwood_uart0_resources[] = {
5606 +       {
5607 +               .start          = UART0_PHYS_BASE,
5608 +               .end            = UART0_PHYS_BASE + 0xff,
5609 +               .flags          = IORESOURCE_MEM,
5610 +       }, {
5611 +               .start          = IRQ_KIRKWOOD_UART_0,
5612 +               .end            = IRQ_KIRKWOOD_UART_0,
5613 +               .flags          = IORESOURCE_IRQ,
5614 +       },
5615 +};
5616 +
5617 +static struct platform_device kirkwood_uart0 = {
5618 +       .name                   = "serial8250",
5619 +       .id                     = 0,
5620 +       .dev                    = {
5621 +               .platform_data  = kirkwood_uart0_data,
5622 +       },
5623 +       .resource               = kirkwood_uart0_resources,
5624 +       .num_resources          = ARRAY_SIZE(kirkwood_uart0_resources),
5625 +};
5626 +
5627 +void __init kirkwood_uart0_init(void)
5628 +{
5629 +       platform_device_register(&kirkwood_uart0);
5630 +}
5631 +
5632 +
5633 +/*****************************************************************************
5634 + * UART1
5635 + ****************************************************************************/
5636 +static struct plat_serial8250_port kirkwood_uart1_data[] = {
5637 +       {
5638 +               .mapbase        = UART1_PHYS_BASE,
5639 +               .membase        = (char *)UART1_VIRT_BASE,
5640 +               .irq            = IRQ_KIRKWOOD_UART_1,
5641 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
5642 +               .iotype         = UPIO_MEM,
5643 +               .regshift       = 2,
5644 +               .uartclk        = KIRKWOOD_TCLK,
5645 +       }, {
5646 +       },
5647 +};
5648 +
5649 +static struct resource kirkwood_uart1_resources[] = {
5650 +       {
5651 +               .start          = UART1_PHYS_BASE,
5652 +               .end            = UART1_PHYS_BASE + 0xff,
5653 +               .flags          = IORESOURCE_MEM,
5654 +       }, {
5655 +               .start          = IRQ_KIRKWOOD_UART_1,
5656 +               .end            = IRQ_KIRKWOOD_UART_1,
5657 +               .flags          = IORESOURCE_IRQ,
5658 +       },
5659 +};
5660 +
5661 +static struct platform_device kirkwood_uart1 = {
5662 +       .name                   = "serial8250",
5663 +       .id                     = 1,
5664 +       .dev                    = {
5665 +               .platform_data  = kirkwood_uart1_data,
5666 +       },
5667 +       .resource               = kirkwood_uart1_resources,
5668 +       .num_resources          = ARRAY_SIZE(kirkwood_uart1_resources),
5669 +};
5670 +
5671 +void __init kirkwood_uart1_init(void)
5672 +{
5673 +       platform_device_register(&kirkwood_uart1);
5674 +}
5675 +
5676 +
5677 +/*****************************************************************************
5678 + * Time handling
5679 + ****************************************************************************/
5680 +static void kirkwood_timer_init(void)
5681 +{
5682 +       orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
5683 +}
5684 +
5685 +struct sys_timer kirkwood_timer = {
5686 +       .init = kirkwood_timer_init,
5687 +};
5688 +
5689 +
5690 +/*****************************************************************************
5691 + * General
5692 + ****************************************************************************/
5693 +static char * __init kirkwood_id(void)
5694 +{
5695 +       switch (readl(DEVICE_ID) & 0x3) {
5696 +       case 0:
5697 +               return "88F6180";
5698 +       case 1:
5699 +               return "88F6192";
5700 +       case 2:
5701 +               return "88F6281";
5702 +       }
5703 +
5704 +       return "unknown 88F6000 variant";
5705 +}
5706 +
5707 +void __init kirkwood_init(void)
5708 +{
5709 +       printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
5710 +               kirkwood_id(), KIRKWOOD_TCLK);
5711 +
5712 +       kirkwood_setup_cpu_mbus();
5713 +
5714 +#ifdef CONFIG_CACHE_FEROCEON_L2
5715 +       feroceon_l2_init(1);
5716 +#endif
5717 +}
5718 --- /dev/null
5719 +++ b/arch/arm/mach-kirkwood/common.h
5720 @@ -0,0 +1,42 @@
5721 +/*
5722 + * arch/arm/mach-kirkwood/common.h
5723 + *
5724 + * Core functions for Marvell Kirkwood SoCs
5725 + *
5726 + * This file is licensed under the terms of the GNU General Public
5727 + * License version 2.  This program is licensed "as is" without any
5728 + * warranty of any kind, whether express or implied.
5729 + */
5730 +
5731 +#ifndef __ARCH_KIRKWOOD_COMMON_H
5732 +#define __ARCH_KIRKWOOD_COMMON_H
5733 +
5734 +struct mv643xx_eth_platform_data;
5735 +struct mv_sata_platform_data;
5736 +
5737 +/*
5738 + * Basic Kirkwood init functions used early by machine-setup.
5739 + */
5740 +void kirkwood_map_io(void);
5741 +void kirkwood_init(void);
5742 +void kirkwood_init_irq(void);
5743 +
5744 +extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
5745 +void kirkwood_setup_cpu_mbus(void);
5746 +void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
5747 +                               int maj, int min);
5748 +void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
5749 +                                int maj, int min);
5750 +
5751 +void kirkwood_ehci_init(void);
5752 +void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
5753 +void kirkwood_pcie_init(void);
5754 +void kirkwood_rtc_init(void);
5755 +void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
5756 +void kirkwood_uart0_init(void);
5757 +void kirkwood_uart1_init(void);
5758 +
5759 +extern struct sys_timer kirkwood_timer;
5760 +
5761 +
5762 +#endif
5763 --- /dev/null
5764 +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
5765 @@ -0,0 +1,68 @@
5766 +/*
5767 + * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
5768 + *
5769 + * Marvell DB-88F6281-BP Development Board Setup
5770 + *
5771 + * This file is licensed under the terms of the GNU General Public
5772 + * License version 2.  This program is licensed "as is" without any
5773 + * warranty of any kind, whether express or implied.
5774 + */
5775 +
5776 +#include <linux/kernel.h>
5777 +#include <linux/init.h>
5778 +#include <linux/platform_device.h>
5779 +#include <linux/pci.h>
5780 +#include <linux/irq.h>
5781 +#include <linux/mtd/physmap.h>
5782 +#include <linux/mtd/nand.h>
5783 +#include <linux/timer.h>
5784 +#include <linux/ata_platform.h>
5785 +#include <linux/mv643xx_eth.h>
5786 +#include <asm/mach-types.h>
5787 +#include <asm/mach/arch.h>
5788 +#include <asm/mach/pci.h>
5789 +#include <asm/arch/kirkwood.h>
5790 +#include "common.h"
5791 +
5792 +static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
5793 +       .phy_addr       = 8,
5794 +};
5795 +
5796 +static struct mv_sata_platform_data db88f6281_sata_data = {
5797 +       .n_ports        = 2,
5798 +};
5799 +
5800 +static void __init db88f6281_init(void)
5801 +{
5802 +       /*
5803 +        * Basic setup. Needs to be called early.
5804 +        */
5805 +       kirkwood_init();
5806 +
5807 +       kirkwood_ehci_init();
5808 +       kirkwood_ge00_init(&db88f6281_ge00_data);
5809 +       kirkwood_rtc_init();
5810 +       kirkwood_sata_init(&db88f6281_sata_data);
5811 +       kirkwood_uart0_init();
5812 +       kirkwood_uart1_init();
5813 +}
5814 +
5815 +static int __init db88f6281_pci_init(void)
5816 +{
5817 +       if (machine_is_db88f6281_bp())
5818 +               kirkwood_pcie_init();
5819 +
5820 +       return 0;
5821 +}
5822 +subsys_initcall(db88f6281_pci_init);
5823 +
5824 +MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
5825 +       /* Maintainer: Saeed Bishara <saeed@marvell.com> */
5826 +       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
5827 +       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
5828 +       .boot_params    = 0x00000100,
5829 +       .init_machine   = db88f6281_init,
5830 +       .map_io         = kirkwood_map_io,
5831 +       .init_irq       = kirkwood_init_irq,
5832 +       .timer          = &kirkwood_timer,
5833 +MACHINE_END
5834 --- /dev/null
5835 +++ b/arch/arm/mach-kirkwood/irq.c
5836 @@ -0,0 +1,22 @@
5837 +/*
5838 + * arch/arm/mach-kirkwood/irq.c
5839 + *
5840 + * Kirkwood IRQ handling.
5841 + *
5842 + * This file is licensed under the terms of the GNU General Public
5843 + * License version 2.  This program is licensed "as is" without any
5844 + * warranty of any kind, whether express or implied.
5845 + */
5846 +
5847 +#include <linux/kernel.h>
5848 +#include <linux/init.h>
5849 +#include <linux/irq.h>
5850 +#include <linux/io.h>
5851 +#include <asm/plat-orion/irq.h>
5852 +#include "common.h"
5853 +
5854 +void __init kirkwood_init_irq(void)
5855 +{
5856 +       orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
5857 +       orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
5858 +}
5859 --- /dev/null
5860 +++ b/arch/arm/mach-kirkwood/pcie.c
5861 @@ -0,0 +1,180 @@
5862 +/*
5863 + * arch/arm/mach-kirkwood/pcie.c
5864 + *
5865 + * PCIe functions for Marvell Kirkwood SoCs
5866 + *
5867 + * This file is licensed under the terms of the GNU General Public
5868 + * License version 2.  This program is licensed "as is" without any
5869 + * warranty of any kind, whether express or implied.
5870 + */
5871 +
5872 +#include <linux/kernel.h>
5873 +#include <linux/pci.h>
5874 +#include <linux/mbus.h>
5875 +#include <asm/mach/pci.h>
5876 +#include <asm/plat-orion/pcie.h>
5877 +#include "common.h"
5878 +
5879 +
5880 +#define PCIE_BASE      ((void __iomem *)PCIE_VIRT_BASE)
5881 +
5882 +static int pcie_valid_config(int bus, int dev)
5883 +{
5884 +       /*
5885 +        * Don't go out when trying to access --
5886 +        * 1. nonexisting device on local bus
5887 +        * 2. where there's no device connected (no link)
5888 +        */
5889 +       if (bus == 0 && dev == 0)
5890 +               return 1;
5891 +
5892 +       if (!orion_pcie_link_up(PCIE_BASE))
5893 +               return 0;
5894 +
5895 +       if (bus == 0 && dev != 1)
5896 +               return 0;
5897 +
5898 +       return 1;
5899 +}
5900 +
5901 +
5902 +/*
5903 + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
5904 + * and then reading the PCIE_CONF_DATA register. Need to make sure these
5905 + * transactions are atomic.
5906 + */
5907 +static DEFINE_SPINLOCK(kirkwood_pcie_lock);
5908 +
5909 +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
5910 +                       int size, u32 *val)
5911 +{
5912 +       unsigned long flags;
5913 +       int ret;
5914 +
5915 +       if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
5916 +               *val = 0xffffffff;
5917 +               return PCIBIOS_DEVICE_NOT_FOUND;
5918 +       }
5919 +
5920 +       spin_lock_irqsave(&kirkwood_pcie_lock, flags);
5921 +       ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
5922 +       spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
5923 +
5924 +       return ret;
5925 +}
5926 +
5927 +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
5928 +                       int where, int size, u32 val)
5929 +{
5930 +       unsigned long flags;
5931 +       int ret;
5932 +
5933 +       if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
5934 +               return PCIBIOS_DEVICE_NOT_FOUND;
5935 +
5936 +       spin_lock_irqsave(&kirkwood_pcie_lock, flags);
5937 +       ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
5938 +       spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
5939 +
5940 +       return ret;
5941 +}
5942 +
5943 +static struct pci_ops pcie_ops = {
5944 +       .read = pcie_rd_conf,
5945 +       .write = pcie_wr_conf,
5946 +};
5947 +
5948 +
5949 +static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
5950 +{
5951 +       struct resource *res;
5952 +
5953 +       /*
5954 +        * Generic PCIe unit setup.
5955 +        */
5956 +       orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
5957 +
5958 +       /*
5959 +        * Request resources.
5960 +        */
5961 +       res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
5962 +       if (!res)
5963 +               panic("pcie_setup unable to alloc resources");
5964 +
5965 +       /*
5966 +        * IORESOURCE_IO
5967 +        */
5968 +       res[0].name = "PCIe I/O Space";
5969 +       res[0].flags = IORESOURCE_IO;
5970 +       res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
5971 +       res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
5972 +       if (request_resource(&ioport_resource, &res[0]))
5973 +               panic("Request PCIe IO resource failed\n");
5974 +       sys->resource[0] = &res[0];
5975 +
5976 +       /*
5977 +        * IORESOURCE_MEM
5978 +        */
5979 +       res[1].name = "PCIe Memory Space";
5980 +       res[1].flags = IORESOURCE_MEM;
5981 +       res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
5982 +       res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
5983 +       if (request_resource(&iomem_resource, &res[1]))
5984 +               panic("Request PCIe Memory resource failed\n");
5985 +       sys->resource[1] = &res[1];
5986 +
5987 +       sys->resource[2] = NULL;
5988 +       sys->io_offset = 0;
5989 +
5990 +       return 1;
5991 +}
5992 +
5993 +static void __devinit rc_pci_fixup(struct pci_dev *dev)
5994 +{
5995 +       /*
5996 +        * Prevent enumeration of root complex.
5997 +        */
5998 +       if (dev->bus->parent == NULL && dev->devfn == 0) {
5999 +               int i;
6000 +
6001 +               for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6002 +                       dev->resource[i].start = 0;
6003 +                       dev->resource[i].end   = 0;
6004 +                       dev->resource[i].flags = 0;
6005 +               }
6006 +       }
6007 +}
6008 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
6009 +
6010 +static struct pci_bus __init *
6011 +kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
6012 +{
6013 +       struct pci_bus *bus;
6014 +
6015 +       if (nr == 0) {
6016 +               bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
6017 +       } else {
6018 +               bus = NULL;
6019 +               BUG();
6020 +       }
6021 +
6022 +       return bus;
6023 +}
6024 +
6025 +static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
6026 +{
6027 +       return IRQ_KIRKWOOD_PCIE;
6028 +}
6029 +
6030 +static struct hw_pci kirkwood_pci __initdata = {
6031 +       .nr_controllers = 1,
6032 +       .swizzle        = pci_std_swizzle,
6033 +       .setup          = kirkwood_pcie_setup,
6034 +       .scan           = kirkwood_pcie_scan_bus,
6035 +       .map_irq        = kirkwood_pcie_map_irq,
6036 +};
6037 +
6038 +void __init kirkwood_pcie_init(void)
6039 +{
6040 +       pci_common_init(&kirkwood_pci);
6041 +}
6042 --- /dev/null
6043 +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
6044 @@ -0,0 +1,69 @@
6045 +/*
6046 + * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
6047 + *
6048 + * Marvell RD-88F6192-NAS Reference Board Setup
6049 + *
6050 + * This file is licensed under the terms of the GNU General Public
6051 + * License version 2.  This program is licensed "as is" without any
6052 + * warranty of any kind, whether express or implied.
6053 + */
6054 +
6055 +#include <linux/kernel.h>
6056 +#include <linux/init.h>
6057 +#include <linux/platform_device.h>
6058 +#include <linux/pci.h>
6059 +#include <linux/irq.h>
6060 +#include <linux/mtd/physmap.h>
6061 +#include <linux/mtd/nand.h>
6062 +#include <linux/timer.h>
6063 +#include <linux/ata_platform.h>
6064 +#include <linux/mv643xx_eth.h>
6065 +#include <asm/mach-types.h>
6066 +#include <asm/mach/arch.h>
6067 +#include <asm/mach/pci.h>
6068 +#include <asm/arch/kirkwood.h>
6069 +#include "common.h"
6070 +
6071 +#define RD88F6192_GPIO_USB_VBUS                10
6072 +
6073 +static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
6074 +       .phy_addr       = 8,
6075 +};
6076 +
6077 +static struct mv_sata_platform_data rd88f6192_sata_data = {
6078 +       .n_ports        = 2,
6079 +};
6080 +
6081 +static void __init rd88f6192_init(void)
6082 +{
6083 +       /*
6084 +        * Basic setup. Needs to be called early.
6085 +        */
6086 +       kirkwood_init();
6087 +
6088 +       kirkwood_ehci_init();
6089 +       kirkwood_ge00_init(&rd88f6192_ge00_data);
6090 +       kirkwood_rtc_init();
6091 +       kirkwood_sata_init(&rd88f6192_sata_data);
6092 +       kirkwood_uart0_init();
6093 +}
6094 +
6095 +static int __init rd88f6192_pci_init(void)
6096 +{
6097 +       if (machine_is_rd88f6192_nas())
6098 +               kirkwood_pcie_init();
6099 +
6100 +       return 0;
6101 +}
6102 +subsys_initcall(rd88f6192_pci_init);
6103 +
6104 +MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
6105 +       /* Maintainer: Saeed Bishara <saeed@marvell.com> */
6106 +       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
6107 +       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
6108 +       .boot_params    = 0x00000100,
6109 +       .init_machine   = rd88f6192_init,
6110 +       .map_io         = kirkwood_map_io,
6111 +       .init_irq       = kirkwood_init_irq,
6112 +       .timer          = &kirkwood_timer,
6113 +MACHINE_END
6114 --- /dev/null
6115 +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
6116 @@ -0,0 +1,112 @@
6117 +/*
6118 + * arch/arm/mach-kirkwood/rd88f6281-setup.c
6119 + *
6120 + * Marvell RD-88F6281 Reference Board Setup
6121 + *
6122 + * This file is licensed under the terms of the GNU General Public
6123 + * License version 2.  This program is licensed "as is" without any
6124 + * warranty of any kind, whether express or implied.
6125 + */
6126 +
6127 +#include <linux/kernel.h>
6128 +#include <linux/init.h>
6129 +#include <linux/platform_device.h>
6130 +#include <linux/pci.h>
6131 +#include <linux/irq.h>
6132 +#include <linux/mtd/physmap.h>
6133 +#include <linux/mtd/nand.h>
6134 +#include <linux/timer.h>
6135 +#include <linux/ata_platform.h>
6136 +#include <linux/mv643xx_eth.h>
6137 +#include <asm/mach-types.h>
6138 +#include <asm/mach/arch.h>
6139 +#include <asm/mach/pci.h>
6140 +#include <asm/arch/kirkwood.h>
6141 +#include <asm/plat-orion/orion_nand.h>
6142 +#include "common.h"
6143 +
6144 +static struct mtd_partition rd88f6281_nand_parts[] = {
6145 +       {
6146 +               .name = "u-boot",
6147 +               .offset = 0,
6148 +               .size = SZ_1M
6149 +       }, {
6150 +               .name = "uImage",
6151 +               .offset = MTDPART_OFS_NXTBLK,
6152 +               .size = SZ_2M
6153 +       }, {
6154 +               .name = "root",
6155 +               .offset = MTDPART_OFS_NXTBLK,
6156 +               .size = MTDPART_SIZ_FULL
6157 +       },
6158 +};
6159 +
6160 +static struct resource rd88f6281_nand_resource = {
6161 +       .flags          = IORESOURCE_MEM,
6162 +       .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
6163 +       .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
6164 +                         KIRKWOOD_NAND_MEM_SIZE - 1,
6165 +};
6166 +
6167 +static struct orion_nand_data rd88f6281_nand_data = {
6168 +       .parts          = rd88f6281_nand_parts,
6169 +       .nr_parts       = ARRAY_SIZE(rd88f6281_nand_parts),
6170 +       .cle            = 0,
6171 +       .ale            = 1,
6172 +       .width          = 8,
6173 +};
6174 +
6175 +static struct platform_device rd88f6281_nand_flash = {
6176 +       .name           = "orion_nand",
6177 +       .id             = -1,
6178 +       .dev            = {
6179 +               .platform_data  = &rd88f6281_nand_data,
6180 +       },
6181 +       .resource       = &rd88f6281_nand_resource,
6182 +       .num_resources  = 1,
6183 +};
6184 +
6185 +static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
6186 +       .phy_addr       = -1,
6187 +};
6188 +
6189 +static struct mv_sata_platform_data rd88f6281_sata_data = {
6190 +       .n_ports        = 2,
6191 +};
6192 +
6193 +static void __init rd88f6281_init(void)
6194 +{
6195 +       /*
6196 +        * Basic setup. Needs to be called early.
6197 +        */
6198 +       kirkwood_init();
6199 +
6200 +       kirkwood_ehci_init();
6201 +       kirkwood_ge00_init(&rd88f6281_ge00_data);
6202 +       kirkwood_rtc_init();
6203 +       kirkwood_sata_init(&rd88f6281_sata_data);
6204 +       kirkwood_uart0_init();
6205 +       kirkwood_uart1_init();
6206 +
6207 +       platform_device_register(&rd88f6281_nand_flash);
6208 +}
6209 +
6210 +static int __init rd88f6281_pci_init(void)
6211 +{
6212 +       if (machine_is_rd88f6281())
6213 +               kirkwood_pcie_init();
6214 +
6215 +       return 0;
6216 +}
6217 +subsys_initcall(rd88f6281_pci_init);
6218 +
6219 +MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
6220 +       /* Maintainer: Saeed Bishara <saeed@marvell.com> */
6221 +       .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
6222 +       .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
6223 +       .boot_params    = 0x00000100,
6224 +       .init_machine   = rd88f6281_init,
6225 +       .map_io         = kirkwood_map_io,
6226 +       .init_irq       = kirkwood_init_irq,
6227 +       .timer          = &kirkwood_timer,
6228 +MACHINE_END
6229 --- /dev/null
6230 +++ b/arch/arm/mach-loki/Kconfig
6231 @@ -0,0 +1,13 @@
6232 +if ARCH_LOKI
6233 +
6234 +menu "Marvell Loki (88RC8480) Implementations"
6235 +
6236 +config MACH_LB88RC8480
6237 +       bool "Marvell LB88RC8480 Development Board"
6238 +       help
6239 +         Say 'Y' here if you want your kernel to support the
6240 +         Marvell LB88RC8480 Development Board.
6241 +
6242 +endmenu
6243 +
6244 +endif
6245 --- /dev/null
6246 +++ b/arch/arm/mach-loki/Makefile
6247 @@ -0,0 +1,3 @@
6248 +obj-y                          += common.o addr-map.o irq.o
6249 +
6250 +obj-$(CONFIG_MACH_LB88RC8480)  += lb88rc8480-setup.o
6251 --- /dev/null
6252 +++ b/arch/arm/mach-loki/Makefile.boot
6253 @@ -0,0 +1,3 @@
6254 +   zreladdr-y  := 0x00008000
6255 +params_phys-y  := 0x00000100
6256 +initrd_phys-y  := 0x00800000
6257 --- /dev/null
6258 +++ b/arch/arm/mach-loki/addr-map.c
6259 @@ -0,0 +1,121 @@
6260 +/*
6261 + * arch/arm/mach-loki/addr-map.c
6262 + *
6263 + * Address map functions for Marvell Loki (88RC8480) SoCs
6264 + *
6265 + * This file is licensed under the terms of the GNU General Public
6266 + * License version 2.  This program is licensed "as is" without any
6267 + * warranty of any kind, whether express or implied.
6268 + */
6269 +
6270 +#include <linux/kernel.h>
6271 +#include <linux/init.h>
6272 +#include <linux/mbus.h>
6273 +#include <asm/hardware.h>
6274 +#include <asm/io.h>
6275 +#include "common.h"
6276 +
6277 +/*
6278 + * Generic Address Decode Windows bit settings
6279 + */
6280 +#define TARGET_DDR             0
6281 +#define TARGET_DEV_BUS         1
6282 +#define TARGET_PCIE0           3
6283 +#define TARGET_PCIE1           4
6284 +#define ATTR_DEV_BOOT          0x0f
6285 +#define ATTR_DEV_CS2           0x1b
6286 +#define ATTR_DEV_CS1           0x1d
6287 +#define ATTR_DEV_CS0           0x1e
6288 +#define ATTR_PCIE_IO           0x51
6289 +#define ATTR_PCIE_MEM          0x59
6290 +
6291 +/*
6292 + * Helpers to get DDR bank info
6293 + */
6294 +#define DDR_SIZE_CS(n)         DDR_REG(0x1500 + ((n) << 3))
6295 +#define DDR_BASE_CS(n)         DDR_REG(0x1504 + ((n) << 3))
6296 +
6297 +/*
6298 + * CPU Address Decode Windows registers
6299 + */
6300 +#define CPU_WIN_CTRL(n)                BRIDGE_REG(0x000 | ((n) << 4))
6301 +#define CPU_WIN_BASE(n)                BRIDGE_REG(0x004 | ((n) << 4))
6302 +#define CPU_WIN_REMAP_LO(n)    BRIDGE_REG(0x008 | ((n) << 4))
6303 +#define CPU_WIN_REMAP_HI(n)    BRIDGE_REG(0x00c | ((n) << 4))
6304 +
6305 +
6306 +struct mbus_dram_target_info loki_mbus_dram_info;
6307 +
6308 +static void __init setup_cpu_win(int win, u32 base, u32 size,
6309 +                                u8 target, u8 attr, int remap)
6310 +{
6311 +       u32 ctrl;
6312 +
6313 +       base &= 0xffff0000;
6314 +       ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
6315 +
6316 +       writel(base, CPU_WIN_BASE(win));
6317 +       writel(ctrl, CPU_WIN_CTRL(win));
6318 +       if (win < 2) {
6319 +               if (remap < 0)
6320 +                       remap = base;
6321 +
6322 +               writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
6323 +               writel(0, CPU_WIN_REMAP_HI(win));
6324 +       }
6325 +}
6326 +
6327 +void __init loki_setup_cpu_mbus(void)
6328 +{
6329 +       int i;
6330 +       int cs;
6331 +
6332 +       /*
6333 +        * First, disable and clear windows.
6334 +        */
6335 +       for (i = 0; i < 8; i++) {
6336 +               writel(0, CPU_WIN_BASE(i));
6337 +               writel(0, CPU_WIN_CTRL(i));
6338 +               if (i < 2) {
6339 +                       writel(0, CPU_WIN_REMAP_LO(i));
6340 +                       writel(0, CPU_WIN_REMAP_HI(i));
6341 +               }
6342 +       }
6343 +
6344 +       /*
6345 +        * Setup windows for PCIe IO+MEM space.
6346 +        */
6347 +       setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
6348 +                     TARGET_PCIE0, ATTR_PCIE_MEM, -1);
6349 +       setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
6350 +                     TARGET_PCIE1, ATTR_PCIE_MEM, -1);
6351 +
6352 +       /*
6353 +        * Setup MBUS dram target info.
6354 +        */
6355 +       loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
6356 +
6357 +       for (i = 0, cs = 0; i < 4; i++) {
6358 +               u32 base = readl(DDR_BASE_CS(i));
6359 +               u32 size = readl(DDR_SIZE_CS(i));
6360 +
6361 +               /*
6362 +                * Chip select enabled?
6363 +                */
6364 +               if (size & 1) {
6365 +                       struct mbus_dram_window *w;
6366 +
6367 +                       w = &loki_mbus_dram_info.cs[cs++];
6368 +                       w->cs_index = i;
6369 +                       w->mbus_attr = 0xf & ~(1 << i);
6370 +                       w->base = base & 0xffff0000;
6371 +                       w->size = (size | 0x0000ffff) + 1;
6372 +               }
6373 +       }
6374 +       loki_mbus_dram_info.num_cs = cs;
6375 +}
6376 +
6377 +void __init loki_setup_dev_boot_win(u32 base, u32 size)
6378 +{
6379 +       setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
6380 +}
6381 --- /dev/null
6382 +++ b/arch/arm/mach-loki/common.c
6383 @@ -0,0 +1,305 @@
6384 +/*
6385 + * arch/arm/mach-loki/common.c
6386 + *
6387 + * Core functions for Marvell Loki (88RC8480) SoCs
6388 + *
6389 + * This file is licensed under the terms of the GNU General Public
6390 + * License version 2.  This program is licensed "as is" without any
6391 + * warranty of any kind, whether express or implied.
6392 + */
6393 +
6394 +#include <linux/kernel.h>
6395 +#include <linux/init.h>
6396 +#include <linux/platform_device.h>
6397 +#include <linux/serial_8250.h>
6398 +#include <linux/mbus.h>
6399 +#include <linux/mv643xx_eth.h>
6400 +#include <asm/page.h>
6401 +#include <asm/timex.h>
6402 +#include <asm/mach/map.h>
6403 +#include <asm/mach/time.h>
6404 +#include <asm/arch/loki.h>
6405 +#include <asm/plat-orion/orion_nand.h>
6406 +#include <asm/plat-orion/time.h>
6407 +#include "common.h"
6408 +
6409 +/*****************************************************************************
6410 + * I/O Address Mapping
6411 + ****************************************************************************/
6412 +static struct map_desc loki_io_desc[] __initdata = {
6413 +       {
6414 +               .virtual        = LOKI_REGS_VIRT_BASE,
6415 +               .pfn            = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
6416 +               .length         = LOKI_REGS_SIZE,
6417 +               .type           = MT_DEVICE,
6418 +       },
6419 +};
6420 +
6421 +void __init loki_map_io(void)
6422 +{
6423 +       iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
6424 +}
6425 +
6426 +
6427 +/*****************************************************************************
6428 + * GE0
6429 + ****************************************************************************/
6430 +struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
6431 +       .t_clk          = LOKI_TCLK,
6432 +       .dram           = &loki_mbus_dram_info,
6433 +};
6434 +
6435 +static struct resource loki_ge0_shared_resources[] = {
6436 +       {
6437 +               .name   = "ge0 base",
6438 +               .start  = GE0_PHYS_BASE + 0x2000,
6439 +               .end    = GE0_PHYS_BASE + 0x3fff,
6440 +               .flags  = IORESOURCE_MEM,
6441 +       },
6442 +};
6443 +
6444 +static struct platform_device loki_ge0_shared = {
6445 +       .name           = MV643XX_ETH_SHARED_NAME,
6446 +       .id             = 0,
6447 +       .dev            = {
6448 +               .platform_data  = &loki_ge0_shared_data,
6449 +       },
6450 +       .num_resources  = 1,
6451 +       .resource       = loki_ge0_shared_resources,
6452 +};
6453 +
6454 +static struct resource loki_ge0_resources[] = {
6455 +       {
6456 +               .name   = "ge0 irq",
6457 +               .start  = IRQ_LOKI_GBE_A_INT,
6458 +               .end    = IRQ_LOKI_GBE_A_INT,
6459 +               .flags  = IORESOURCE_IRQ,
6460 +       },
6461 +};
6462 +
6463 +static struct platform_device loki_ge0 = {
6464 +       .name           = MV643XX_ETH_NAME,
6465 +       .id             = 0,
6466 +       .num_resources  = 1,
6467 +       .resource       = loki_ge0_resources,
6468 +};
6469 +
6470 +void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
6471 +{
6472 +       eth_data->shared = &loki_ge0_shared;
6473 +       loki_ge0.dev.platform_data = eth_data;
6474 +
6475 +       writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
6476 +       platform_device_register(&loki_ge0_shared);
6477 +       platform_device_register(&loki_ge0);
6478 +}
6479 +
6480 +
6481 +/*****************************************************************************
6482 + * GE1
6483 + ****************************************************************************/
6484 +struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
6485 +       .t_clk          = LOKI_TCLK,
6486 +       .dram           = &loki_mbus_dram_info,
6487 +};
6488 +
6489 +static struct resource loki_ge1_shared_resources[] = {
6490 +       {
6491 +               .name   = "ge1 base",
6492 +               .start  = GE1_PHYS_BASE + 0x2000,
6493 +               .end    = GE1_PHYS_BASE + 0x3fff,
6494 +               .flags  = IORESOURCE_MEM,
6495 +       },
6496 +};
6497 +
6498 +static struct platform_device loki_ge1_shared = {
6499 +       .name           = MV643XX_ETH_SHARED_NAME,
6500 +       .id             = 1,
6501 +       .dev            = {
6502 +               .platform_data  = &loki_ge1_shared_data,
6503 +       },
6504 +       .num_resources  = 1,
6505 +       .resource       = loki_ge1_shared_resources,
6506 +};
6507 +
6508 +static struct resource loki_ge1_resources[] = {
6509 +       {
6510 +               .name   = "ge1 irq",
6511 +               .start  = IRQ_LOKI_GBE_B_INT,
6512 +               .end    = IRQ_LOKI_GBE_B_INT,
6513 +               .flags  = IORESOURCE_IRQ,
6514 +       },
6515 +};
6516 +
6517 +static struct platform_device loki_ge1 = {
6518 +       .name           = MV643XX_ETH_NAME,
6519 +       .id             = 1,
6520 +       .num_resources  = 1,
6521 +       .resource       = loki_ge1_resources,
6522 +};
6523 +
6524 +void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
6525 +{
6526 +       eth_data->shared = &loki_ge1_shared;
6527 +       loki_ge1.dev.platform_data = eth_data;
6528 +
6529 +       writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
6530 +       platform_device_register(&loki_ge1_shared);
6531 +       platform_device_register(&loki_ge1);
6532 +}
6533 +
6534 +
6535 +/*****************************************************************************
6536 + * SAS/SATA
6537 + ****************************************************************************/
6538 +static struct resource loki_sas_resources[] = {
6539 +       {
6540 +               .name   = "mvsas0 mem",
6541 +               .start  = SAS0_PHYS_BASE,
6542 +               .end    = SAS0_PHYS_BASE + 0x01ff,
6543 +               .flags  = IORESOURCE_MEM,
6544 +       }, {
6545 +               .name   = "mvsas0 irq",
6546 +               .start  = IRQ_LOKI_SAS_A,
6547 +               .end    = IRQ_LOKI_SAS_A,
6548 +               .flags  = IORESOURCE_IRQ,
6549 +       }, {
6550 +               .name   = "mvsas1 mem",
6551 +               .start  = SAS1_PHYS_BASE,
6552 +               .end    = SAS1_PHYS_BASE + 0x01ff,
6553 +               .flags  = IORESOURCE_MEM,
6554 +       }, {
6555 +               .name   = "mvsas1 irq",
6556 +               .start  = IRQ_LOKI_SAS_B,
6557 +               .end    = IRQ_LOKI_SAS_B,
6558 +               .flags  = IORESOURCE_IRQ,
6559 +       },
6560 +};
6561 +
6562 +static struct platform_device loki_sas = {
6563 +       .name           = "mvsas",
6564 +       .id             = 0,
6565 +       .dev            = {
6566 +               .coherent_dma_mask      = 0xffffffff,
6567 +       },
6568 +       .num_resources  = ARRAY_SIZE(loki_sas_resources),
6569 +       .resource       = loki_sas_resources,
6570 +};
6571 +
6572 +void __init loki_sas_init(void)
6573 +{
6574 +       writel(0x8300f707, DDR_REG(0x1424));
6575 +       platform_device_register(&loki_sas);
6576 +}
6577 +
6578 +
6579 +/*****************************************************************************
6580 + * UART0
6581 + ****************************************************************************/
6582 +static struct plat_serial8250_port loki_uart0_data[] = {
6583 +       {
6584 +               .mapbase        = UART0_PHYS_BASE,
6585 +               .membase        = (char *)UART0_VIRT_BASE,
6586 +               .irq            = IRQ_LOKI_UART0,
6587 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
6588 +               .iotype         = UPIO_MEM,
6589 +               .regshift       = 2,
6590 +               .uartclk        = LOKI_TCLK,
6591 +       }, {
6592 +       },
6593 +};
6594 +
6595 +static struct resource loki_uart0_resources[] = {
6596 +       {
6597 +               .start          = UART0_PHYS_BASE,
6598 +               .end            = UART0_PHYS_BASE + 0xff,
6599 +               .flags          = IORESOURCE_MEM,
6600 +       }, {
6601 +               .start          = IRQ_LOKI_UART0,
6602 +               .end            = IRQ_LOKI_UART0,
6603 +               .flags          = IORESOURCE_IRQ,
6604 +       },
6605 +};
6606 +
6607 +static struct platform_device loki_uart0 = {
6608 +       .name                   = "serial8250",
6609 +       .id                     = 0,
6610 +       .dev                    = {
6611 +               .platform_data  = loki_uart0_data,
6612 +       },
6613 +       .resource               = loki_uart0_resources,
6614 +       .num_resources          = ARRAY_SIZE(loki_uart0_resources),
6615 +};
6616 +
6617 +void __init loki_uart0_init(void)
6618 +{
6619 +       platform_device_register(&loki_uart0);
6620 +}
6621 +
6622 +
6623 +/*****************************************************************************
6624 + * UART1
6625 + ****************************************************************************/
6626 +static struct plat_serial8250_port loki_uart1_data[] = {
6627 +       {
6628 +               .mapbase        = UART1_PHYS_BASE,
6629 +               .membase        = (char *)UART1_VIRT_BASE,
6630 +               .irq            = IRQ_LOKI_UART1,
6631 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
6632 +               .iotype         = UPIO_MEM,
6633 +               .regshift       = 2,
6634 +               .uartclk        = LOKI_TCLK,
6635 +       }, {
6636 +       },
6637 +};
6638 +
6639 +static struct resource loki_uart1_resources[] = {
6640 +       {
6641 +               .start          = UART1_PHYS_BASE,
6642 +               .end            = UART1_PHYS_BASE + 0xff,
6643 +               .flags          = IORESOURCE_MEM,
6644 +       }, {
6645 +               .start          = IRQ_LOKI_UART1,
6646 +               .end            = IRQ_LOKI_UART1,
6647 +               .flags          = IORESOURCE_IRQ,
6648 +       },
6649 +};
6650 +
6651 +static struct platform_device loki_uart1 = {
6652 +       .name                   = "serial8250",
6653 +       .id                     = 1,
6654 +       .dev                    = {
6655 +               .platform_data  = loki_uart1_data,
6656 +       },
6657 +       .resource               = loki_uart1_resources,
6658 +       .num_resources          = ARRAY_SIZE(loki_uart1_resources),
6659 +};
6660 +
6661 +void __init loki_uart1_init(void)
6662 +{
6663 +       platform_device_register(&loki_uart1);
6664 +}
6665 +
6666 +
6667 +/*****************************************************************************
6668 + * Time handling
6669 + ****************************************************************************/
6670 +static void loki_timer_init(void)
6671 +{
6672 +       orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
6673 +}
6674 +
6675 +struct sys_timer loki_timer = {
6676 +       .init = loki_timer_init,
6677 +};
6678 +
6679 +
6680 +/*****************************************************************************
6681 + * General
6682 + ****************************************************************************/
6683 +void __init loki_init(void)
6684 +{
6685 +       printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
6686 +
6687 +       loki_setup_cpu_mbus();
6688 +}
6689 --- /dev/null
6690 +++ b/arch/arm/mach-loki/common.h
6691 @@ -0,0 +1,36 @@
6692 +/*
6693 + * arch/arm/mach-loki/common.h
6694 + *
6695 + * Core functions for Marvell Loki (88RC8480) SoCs
6696 + *
6697 + * This file is licensed under the terms of the GNU General Public
6698 + * License version 2.  This program is licensed "as is" without any
6699 + * warranty of any kind, whether express or implied.
6700 + */
6701 +
6702 +#ifndef __ARCH_LOKI_COMMON_H
6703 +#define __ARCH_LOKI_COMMON_H
6704 +
6705 +struct mv643xx_eth_platform_data;
6706 +
6707 +/*
6708 + * Basic Loki init functions used early by machine-setup.
6709 + */
6710 +void loki_map_io(void);
6711 +void loki_init(void);
6712 +void loki_init_irq(void);
6713 +
6714 +extern struct mbus_dram_target_info loki_mbus_dram_info;
6715 +void loki_setup_cpu_mbus(void);
6716 +void loki_setup_dev_boot_win(u32 base, u32 size);
6717 +
6718 +void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
6719 +void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
6720 +void loki_sas_init(void);
6721 +void loki_uart0_init(void);
6722 +void loki_uart1_init(void);
6723 +
6724 +extern struct sys_timer loki_timer;
6725 +
6726 +
6727 +#endif
6728 --- /dev/null
6729 +++ b/arch/arm/mach-loki/irq.c
6730 @@ -0,0 +1,21 @@
6731 +/*
6732 + * arch/arm/mach-loki/irq.c
6733 + *
6734 + * Marvell Loki (88RC8480) IRQ handling.
6735 + *
6736 + * This file is licensed under the terms of the GNU General Public
6737 + * License version 2.  This program is licensed "as is" without any
6738 + * warranty of any kind, whether express or implied.
6739 + */
6740 +
6741 +#include <linux/kernel.h>
6742 +#include <linux/init.h>
6743 +#include <linux/irq.h>
6744 +#include <asm/io.h>
6745 +#include <asm/plat-orion/irq.h>
6746 +#include "common.h"
6747 +
6748 +void __init loki_init_irq(void)
6749 +{
6750 +       orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
6751 +}
6752 --- /dev/null
6753 +++ b/arch/arm/mach-loki/lb88rc8480-setup.c
6754 @@ -0,0 +1,100 @@
6755 +/*
6756 + * arch/arm/mach-loki/lb88rc8480-setup.c
6757 + *
6758 + * Marvell LB88RC8480 Development Board Setup
6759 + *
6760 + * This file is licensed under the terms of the GNU General Public
6761 + * License version 2.  This program is licensed "as is" without any
6762 + * warranty of any kind, whether express or implied.
6763 + */
6764 +
6765 +#include <linux/kernel.h>
6766 +#include <linux/init.h>
6767 +#include <linux/platform_device.h>
6768 +#include <linux/irq.h>
6769 +#include <linux/mtd/physmap.h>
6770 +#include <linux/mtd/nand.h>
6771 +#include <linux/timer.h>
6772 +#include <linux/ata_platform.h>
6773 +#include <linux/mv643xx_eth.h>
6774 +#include <asm/mach-types.h>
6775 +#include <asm/mach/arch.h>
6776 +#include <asm/arch/loki.h>
6777 +#include "common.h"
6778 +
6779 +#define LB88RC8480_FLASH_BOOT_CS_BASE  0xf8000000
6780 +#define LB88RC8480_FLASH_BOOT_CS_SIZE  SZ_128M
6781 +
6782 +#define LB88RC8480_NOR_BOOT_BASE       0xff000000
6783 +#define LB88RC8480_NOR_BOOT_SIZE       SZ_16M
6784 +
6785 +static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
6786 +       {
6787 +               .name   = "kernel",
6788 +               .offset = 0,
6789 +               .size   = SZ_2M,
6790 +       }, {
6791 +               .name   = "root-fs",
6792 +               .offset = SZ_2M,
6793 +               .size   = (SZ_8M + SZ_4M + SZ_1M),
6794 +       }, {
6795 +               .name   = "u-boot",
6796 +               .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
6797 +               .size   = SZ_1M,
6798 +       },
6799 +};
6800 +
6801 +static struct physmap_flash_data lb88rc8480_boot_flash_data = {
6802 +       .parts          = lb88rc8480_boot_flash_parts,
6803 +       .nr_parts       = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
6804 +       .width          = 1,    /* 8 bit bus width */
6805 +};
6806 +
6807 +static struct resource lb88rc8480_boot_flash_resource = {
6808 +       .flags  = IORESOURCE_MEM,
6809 +       .start  = LB88RC8480_NOR_BOOT_BASE,
6810 +       .end    = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
6811 +};
6812 +
6813 +static struct platform_device lb88rc8480_boot_flash = {
6814 +       .name   = "physmap-flash",
6815 +       .id     = 0,
6816 +       .dev    = {
6817 +               .platform_data  = &lb88rc8480_boot_flash_data,
6818 +       },
6819 +       .num_resources  = 1,
6820 +       .resource       = &lb88rc8480_boot_flash_resource,
6821 +};
6822 +
6823 +static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
6824 +       .phy_addr       = 1,
6825 +       .mac_addr       = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
6826 +};
6827 +
6828 +static void __init lb88rc8480_init(void)
6829 +{
6830 +       /*
6831 +        * Basic setup. Needs to be called early.
6832 +        */
6833 +       loki_init();
6834 +
6835 +       loki_ge0_init(&lb88rc8480_ge0_data);
6836 +       loki_sas_init();
6837 +       loki_uart0_init();
6838 +       loki_uart1_init();
6839 +
6840 +       loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
6841 +                               LB88RC8480_FLASH_BOOT_CS_SIZE);
6842 +       platform_device_register(&lb88rc8480_boot_flash);
6843 +}
6844 +
6845 +MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
6846 +       /* Maintainer: Ke Wei <kewei@marvell.com> */
6847 +       .phys_io        = LOKI_REGS_PHYS_BASE,
6848 +       .io_pg_offst    = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
6849 +       .boot_params    = 0x00000100,
6850 +       .init_machine   = lb88rc8480_init,
6851 +       .map_io         = loki_map_io,
6852 +       .init_irq       = loki_init_irq,
6853 +       .timer          = &loki_timer,
6854 +MACHINE_END
6855 --- /dev/null
6856 +++ b/arch/arm/mach-mv78xx0/Kconfig
6857 @@ -0,0 +1,13 @@
6858 +if ARCH_MV78XX0
6859 +
6860 +menu "Marvell MV78xx0 Implementations"
6861 +
6862 +config MACH_DB78X00_BP
6863 +       bool "Marvell DB-78x00-BP Development Board"
6864 +       help
6865 +         Say 'Y' here if you want your kernel to support the
6866 +         Marvell DB-78x00-BP Development Board.
6867 +
6868 +endmenu
6869 +
6870 +endif
6871 --- /dev/null
6872 +++ b/arch/arm/mach-mv78xx0/Makefile
6873 @@ -0,0 +1,2 @@
6874 +obj-y                          += common.o addr-map.o irq.o pcie.o
6875 +obj-$(CONFIG_MACH_DB78X00_BP)  += db78x00-bp-setup.o
6876 --- /dev/null
6877 +++ b/arch/arm/mach-mv78xx0/Makefile.boot
6878 @@ -0,0 +1,3 @@
6879 +   zreladdr-y  := 0x00008000
6880 +params_phys-y  := 0x00000100
6881 +initrd_phys-y  := 0x00800000
6882 --- /dev/null
6883 +++ b/arch/arm/mach-mv78xx0/addr-map.c
6884 @@ -0,0 +1,156 @@
6885 +/*
6886 + * arch/arm/mach-mv78xx0/addr-map.c
6887 + *
6888 + * Address map functions for Marvell MV78xx0 SoCs
6889 + *
6890 + * This file is licensed under the terms of the GNU General Public
6891 + * License version 2.  This program is licensed "as is" without any
6892 + * warranty of any kind, whether express or implied.
6893 + */
6894 +
6895 +#include <linux/kernel.h>
6896 +#include <linux/init.h>
6897 +#include <linux/mbus.h>
6898 +#include <asm/io.h>
6899 +#include "common.h"
6900 +
6901 +/*
6902 + * Generic Address Decode Windows bit settings
6903 + */
6904 +#define TARGET_DDR             0
6905 +#define TARGET_DEV_BUS         1
6906 +#define TARGET_PCIE0           4
6907 +#define TARGET_PCIE1           8
6908 +#define TARGET_PCIE(i)         ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
6909 +#define ATTR_DEV_SPI_ROM       0x1f
6910 +#define ATTR_DEV_BOOT          0x2f
6911 +#define ATTR_DEV_CS3           0x37
6912 +#define ATTR_DEV_CS2           0x3b
6913 +#define ATTR_DEV_CS1           0x3d
6914 +#define ATTR_DEV_CS0           0x3e
6915 +#define ATTR_PCIE_IO(l)                (0xf0 & ~(0x10 << (l)))
6916 +#define ATTR_PCIE_MEM(l)       (0xf8 & ~(0x10 << (l)))
6917 +
6918 +/*
6919 + * Helpers to get DDR bank info
6920 + */
6921 +#define DDR_BASE_CS_OFF(n)     (0x0000 + ((n) << 3))
6922 +#define DDR_SIZE_CS_OFF(n)     (0x0004 + ((n) << 3))
6923 +
6924 +/*
6925 + * CPU Address Decode Windows registers
6926 + */
6927 +#define WIN0_OFF(n)            (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
6928 +#define WIN8_OFF(n)            (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
6929 +#define WIN_CTRL_OFF           0x0000
6930 +#define WIN_BASE_OFF           0x0004
6931 +#define WIN_REMAP_LO_OFF       0x0008
6932 +#define WIN_REMAP_HI_OFF       0x000c
6933 +
6934 +
6935 +struct mbus_dram_target_info mv78xx0_mbus_dram_info;
6936 +
6937 +static void __init __iomem *win_cfg_base(int win)
6938 +{
6939 +       /*
6940 +        * Find the control register base address for this window.
6941 +        *
6942 +        * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
6943 +        * MBUS bridge depending on which CPU core we're running on,
6944 +        * so we don't need to take that into account here.
6945 +        */
6946 +
6947 +       return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
6948 +}
6949 +
6950 +static int __init cpu_win_can_remap(int win)
6951 +{
6952 +       if (win < 8)
6953 +               return 1;
6954 +
6955 +       return 0;
6956 +}
6957 +
6958 +static void __init setup_cpu_win(int win, u32 base, u32 size,
6959 +                                u8 target, u8 attr, int remap)
6960 +{
6961 +       void __iomem *addr = win_cfg_base(win);
6962 +       u32 ctrl;
6963 +
6964 +       base &= 0xffff0000;
6965 +       ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
6966 +
6967 +       writel(base, addr + WIN_BASE_OFF);
6968 +       writel(ctrl, addr + WIN_CTRL_OFF);
6969 +       if (cpu_win_can_remap(win)) {
6970 +               if (remap < 0)
6971 +                       remap = base;
6972 +
6973 +               writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
6974 +               writel(0, addr + WIN_REMAP_HI_OFF);
6975 +       }
6976 +}
6977 +
6978 +void __init mv78xx0_setup_cpu_mbus(void)
6979 +{
6980 +       void __iomem *addr;
6981 +       int i;
6982 +       int cs;
6983 +
6984 +       /*
6985 +        * First, disable and clear windows.
6986 +        */
6987 +       for (i = 0; i < 14; i++) {
6988 +               addr = win_cfg_base(i);
6989 +
6990 +               writel(0, addr + WIN_BASE_OFF);
6991 +               writel(0, addr + WIN_CTRL_OFF);
6992 +               if (cpu_win_can_remap(i)) {
6993 +                       writel(0, addr + WIN_REMAP_LO_OFF);
6994 +                       writel(0, addr + WIN_REMAP_HI_OFF);
6995 +               }
6996 +       }
6997 +
6998 +       /*
6999 +        * Setup MBUS dram target info.
7000 +        */
7001 +       mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
7002 +
7003 +       if (mv78xx0_core_index() == 0)
7004 +               addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
7005 +       else
7006 +               addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
7007 +
7008 +       for (i = 0, cs = 0; i < 4; i++) {
7009 +               u32 base = readl(addr + DDR_BASE_CS_OFF(i));
7010 +               u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
7011 +
7012 +               /*
7013 +                * Chip select enabled?
7014 +                */
7015 +               if (size & 1) {
7016 +                       struct mbus_dram_window *w;
7017 +
7018 +                       w = &mv78xx0_mbus_dram_info.cs[cs++];
7019 +                       w->cs_index = i;
7020 +                       w->mbus_attr = 0xf & ~(1 << i);
7021 +                       w->base = base & 0xffff0000;
7022 +                       w->size = (size | 0x0000ffff) + 1;
7023 +               }
7024 +       }
7025 +       mv78xx0_mbus_dram_info.num_cs = cs;
7026 +}
7027 +
7028 +void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
7029 +                                     int maj, int min)
7030 +{
7031 +       setup_cpu_win(window, base, size, TARGET_PCIE(maj),
7032 +                     ATTR_PCIE_IO(min), -1);
7033 +}
7034 +
7035 +void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
7036 +                                      int maj, int min)
7037 +{
7038 +       setup_cpu_win(window, base, size, TARGET_PCIE(maj),
7039 +                     ATTR_PCIE_MEM(min), -1);
7040 +}
7041 --- /dev/null
7042 +++ b/arch/arm/mach-mv78xx0/common.c
7043 @@ -0,0 +1,754 @@
7044 +/*
7045 + * arch/arm/mach-mv78xx0/common.c
7046 + *
7047 + * Core functions for Marvell MV78xx0 SoCs
7048 + *
7049 + * This file is licensed under the terms of the GNU General Public
7050 + * License version 2.  This program is licensed "as is" without any
7051 + * warranty of any kind, whether express or implied.
7052 + */
7053 +
7054 +#include <linux/kernel.h>
7055 +#include <linux/init.h>
7056 +#include <linux/platform_device.h>
7057 +#include <linux/serial_8250.h>
7058 +#include <linux/mbus.h>
7059 +#include <linux/mv643xx_eth.h>
7060 +#include <linux/ata_platform.h>
7061 +#include <asm/mach/map.h>
7062 +#include <asm/mach/time.h>
7063 +#include <asm/arch/mv78xx0.h>
7064 +#include <asm/plat-orion/cache-feroceon-l2.h>
7065 +#include <asm/plat-orion/ehci-orion.h>
7066 +#include <asm/plat-orion/orion_nand.h>
7067 +#include <asm/plat-orion/time.h>
7068 +#include "common.h"
7069 +
7070 +
7071 +/*****************************************************************************
7072 + * Common bits
7073 + ****************************************************************************/
7074 +int mv78xx0_core_index(void)
7075 +{
7076 +       u32 extra;
7077 +
7078 +       /*
7079 +        * Read Extra Features register.
7080 +        */
7081 +       __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
7082 +
7083 +       return !!(extra & 0x00004000);
7084 +}
7085 +
7086 +static int get_hclk(void)
7087 +{
7088 +       int hclk;
7089 +
7090 +       /*
7091 +        * HCLK tick rate is configured by DEV_D[7:5] pins.
7092 +        */
7093 +       switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
7094 +       case 0:
7095 +               hclk = 166666667;
7096 +               break;
7097 +       case 1:
7098 +               hclk = 200000000;
7099 +               break;
7100 +       case 2:
7101 +               hclk = 266666667;
7102 +               break;
7103 +       case 3:
7104 +               hclk = 333333333;
7105 +               break;
7106 +       case 4:
7107 +               hclk = 400000000;
7108 +               break;
7109 +       default:
7110 +               panic("unknown HCLK PLL setting: %.8x\n",
7111 +                       readl(SAMPLE_AT_RESET_LOW));
7112 +       }
7113 +
7114 +       return hclk;
7115 +}
7116 +
7117 +static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
7118 +{
7119 +       u32 cfg;
7120 +
7121 +       /*
7122 +        * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
7123 +        * PCLK/L2CLK by bits [19:14].
7124 +        */
7125 +       if (core_index == 0) {
7126 +               cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
7127 +       } else {
7128 +               cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
7129 +       }
7130 +
7131 +       /*
7132 +        * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
7133 +        * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
7134 +        */
7135 +       *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
7136 +
7137 +       /*
7138 +        * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
7139 +        * ratio (1, 2, 3).
7140 +        */
7141 +       *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
7142 +}
7143 +
7144 +static int get_tclk(void)
7145 +{
7146 +       int tclk;
7147 +
7148 +       /*
7149 +        * TCLK tick rate is configured by DEV_A[2:0] strap pins.
7150 +        */
7151 +       switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
7152 +       case 1:
7153 +               tclk = 166666667;
7154 +               break;
7155 +       case 3:
7156 +               tclk = 200000000;
7157 +               break;
7158 +       default:
7159 +               panic("unknown TCLK PLL setting: %.8x\n",
7160 +                       readl(SAMPLE_AT_RESET_HIGH));
7161 +       }
7162 +
7163 +       return tclk;
7164 +}
7165 +
7166 +
7167 +/*****************************************************************************
7168 + * I/O Address Mapping
7169 + ****************************************************************************/
7170 +static struct map_desc mv78xx0_io_desc[] __initdata = {
7171 +       {
7172 +               .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
7173 +               .pfn            = 0,
7174 +               .length         = MV78XX0_CORE_REGS_SIZE,
7175 +               .type           = MT_DEVICE,
7176 +       }, {
7177 +               .virtual        = MV78XX0_PCIE_IO_VIRT_BASE(0),
7178 +               .pfn            = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
7179 +               .length         = MV78XX0_PCIE_IO_SIZE * 8,
7180 +               .type           = MT_DEVICE,
7181 +       }, {
7182 +               .virtual        = MV78XX0_REGS_VIRT_BASE,
7183 +               .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
7184 +               .length         = MV78XX0_REGS_SIZE,
7185 +               .type           = MT_DEVICE,
7186 +       },
7187 +};
7188 +
7189 +void __init mv78xx0_map_io(void)
7190 +{
7191 +       unsigned long phys;
7192 +
7193 +       /*
7194 +        * Map the right set of per-core registers depending on
7195 +        * which core we are running on.
7196 +        */
7197 +       if (mv78xx0_core_index() == 0) {
7198 +               phys = MV78XX0_CORE0_REGS_PHYS_BASE;
7199 +       } else {
7200 +               phys = MV78XX0_CORE1_REGS_PHYS_BASE;
7201 +       }
7202 +       mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
7203 +
7204 +       iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
7205 +}
7206 +
7207 +
7208 +/*****************************************************************************
7209 + * EHCI
7210 + ****************************************************************************/
7211 +static struct orion_ehci_data mv78xx0_ehci_data = {
7212 +       .dram           = &mv78xx0_mbus_dram_info,
7213 +};
7214 +
7215 +static u64 ehci_dmamask = 0xffffffffUL;
7216 +
7217 +
7218 +/*****************************************************************************
7219 + * EHCI0
7220 + ****************************************************************************/
7221 +static struct resource mv78xx0_ehci0_resources[] = {
7222 +       {
7223 +               .start  = USB0_PHYS_BASE,
7224 +               .end    = USB0_PHYS_BASE + 0x0fff,
7225 +               .flags  = IORESOURCE_MEM,
7226 +       }, {
7227 +               .start  = IRQ_MV78XX0_USB_0,
7228 +               .end    = IRQ_MV78XX0_USB_0,
7229 +               .flags  = IORESOURCE_IRQ,
7230 +       },
7231 +};
7232 +
7233 +static struct platform_device mv78xx0_ehci0 = {
7234 +       .name           = "orion-ehci",
7235 +       .id             = 0,
7236 +       .dev            = {
7237 +               .dma_mask               = &ehci_dmamask,
7238 +               .coherent_dma_mask      = 0xffffffff,
7239 +               .platform_data          = &mv78xx0_ehci_data,
7240 +       },
7241 +       .resource       = mv78xx0_ehci0_resources,
7242 +       .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
7243 +};
7244 +
7245 +void __init mv78xx0_ehci0_init(void)
7246 +{
7247 +       platform_device_register(&mv78xx0_ehci0);
7248 +}
7249 +
7250 +
7251 +/*****************************************************************************
7252 + * EHCI1
7253 + ****************************************************************************/
7254 +static struct resource mv78xx0_ehci1_resources[] = {
7255 +       {
7256 +               .start  = USB1_PHYS_BASE,
7257 +               .end    = USB1_PHYS_BASE + 0x0fff,
7258 +               .flags  = IORESOURCE_MEM,
7259 +       }, {
7260 +               .start  = IRQ_MV78XX0_USB_1,
7261 +               .end    = IRQ_MV78XX0_USB_1,
7262 +               .flags  = IORESOURCE_IRQ,
7263 +       },
7264 +};
7265 +
7266 +static struct platform_device mv78xx0_ehci1 = {
7267 +       .name           = "orion-ehci",
7268 +       .id             = 1,
7269 +       .dev            = {
7270 +               .dma_mask               = &ehci_dmamask,
7271 +               .coherent_dma_mask      = 0xffffffff,
7272 +               .platform_data          = &mv78xx0_ehci_data,
7273 +       },
7274 +       .resource       = mv78xx0_ehci1_resources,
7275 +       .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
7276 +};
7277 +
7278 +void __init mv78xx0_ehci1_init(void)
7279 +{
7280 +       platform_device_register(&mv78xx0_ehci1);
7281 +}
7282 +
7283 +
7284 +/*****************************************************************************
7285 + * EHCI2
7286 + ****************************************************************************/
7287 +static struct resource mv78xx0_ehci2_resources[] = {
7288 +       {
7289 +               .start  = USB2_PHYS_BASE,
7290 +               .end    = USB2_PHYS_BASE + 0x0fff,
7291 +               .flags  = IORESOURCE_MEM,
7292 +       }, {
7293 +               .start  = IRQ_MV78XX0_USB_2,
7294 +               .end    = IRQ_MV78XX0_USB_2,
7295 +               .flags  = IORESOURCE_IRQ,
7296 +       },
7297 +};
7298 +
7299 +static struct platform_device mv78xx0_ehci2 = {
7300 +       .name           = "orion-ehci",
7301 +       .id             = 2,
7302 +       .dev            = {
7303 +               .dma_mask               = &ehci_dmamask,
7304 +               .coherent_dma_mask      = 0xffffffff,
7305 +               .platform_data          = &mv78xx0_ehci_data,
7306 +       },
7307 +       .resource       = mv78xx0_ehci2_resources,
7308 +       .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
7309 +};
7310 +
7311 +void __init mv78xx0_ehci2_init(void)
7312 +{
7313 +       platform_device_register(&mv78xx0_ehci2);
7314 +}
7315 +
7316 +
7317 +/*****************************************************************************
7318 + * GE00
7319 + ****************************************************************************/
7320 +struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
7321 +       .t_clk          = 0,
7322 +       .dram           = &mv78xx0_mbus_dram_info,
7323 +};
7324 +
7325 +static struct resource mv78xx0_ge00_shared_resources[] = {
7326 +       {
7327 +               .name   = "ge00 base",
7328 +               .start  = GE00_PHYS_BASE + 0x2000,
7329 +               .end    = GE00_PHYS_BASE + 0x3fff,
7330 +               .flags  = IORESOURCE_MEM,
7331 +       },
7332 +};
7333 +
7334 +static struct platform_device mv78xx0_ge00_shared = {
7335 +       .name           = MV643XX_ETH_SHARED_NAME,
7336 +       .id             = 0,
7337 +       .dev            = {
7338 +               .platform_data  = &mv78xx0_ge00_shared_data,
7339 +       },
7340 +       .num_resources  = 1,
7341 +       .resource       = mv78xx0_ge00_shared_resources,
7342 +};
7343 +
7344 +static struct resource mv78xx0_ge00_resources[] = {
7345 +       {
7346 +               .name   = "ge00 irq",
7347 +               .start  = IRQ_MV78XX0_GE00_SUM,
7348 +               .end    = IRQ_MV78XX0_GE00_SUM,
7349 +               .flags  = IORESOURCE_IRQ,
7350 +       },
7351 +};
7352 +
7353 +static struct platform_device mv78xx0_ge00 = {
7354 +       .name           = MV643XX_ETH_NAME,
7355 +       .id             = 0,
7356 +       .num_resources  = 1,
7357 +       .resource       = mv78xx0_ge00_resources,
7358 +};
7359 +
7360 +void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
7361 +{
7362 +       eth_data->shared = &mv78xx0_ge00_shared;
7363 +       mv78xx0_ge00.dev.platform_data = eth_data;
7364 +
7365 +       platform_device_register(&mv78xx0_ge00_shared);
7366 +       platform_device_register(&mv78xx0_ge00);
7367 +}
7368 +
7369 +
7370 +/*****************************************************************************
7371 + * GE01
7372 + ****************************************************************************/
7373 +struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
7374 +       .t_clk          = 0,
7375 +       .dram           = &mv78xx0_mbus_dram_info,
7376 +};
7377 +
7378 +static struct resource mv78xx0_ge01_shared_resources[] = {
7379 +       {
7380 +               .name   = "ge01 base",
7381 +               .start  = GE01_PHYS_BASE + 0x2000,
7382 +               .end    = GE01_PHYS_BASE + 0x3fff,
7383 +               .flags  = IORESOURCE_MEM,
7384 +       },
7385 +};
7386 +
7387 +static struct platform_device mv78xx0_ge01_shared = {
7388 +       .name           = MV643XX_ETH_SHARED_NAME,
7389 +       .id             = 1,
7390 +       .dev            = {
7391 +               .platform_data  = &mv78xx0_ge01_shared_data,
7392 +       },
7393 +       .num_resources  = 1,
7394 +       .resource       = mv78xx0_ge01_shared_resources,
7395 +};
7396 +
7397 +static struct resource mv78xx0_ge01_resources[] = {
7398 +       {
7399 +               .name   = "ge01 irq",
7400 +               .start  = IRQ_MV78XX0_GE01_SUM,
7401 +               .end    = IRQ_MV78XX0_GE01_SUM,
7402 +               .flags  = IORESOURCE_IRQ,
7403 +       },
7404 +};
7405 +
7406 +static struct platform_device mv78xx0_ge01 = {
7407 +       .name           = MV643XX_ETH_NAME,
7408 +       .id             = 1,
7409 +       .num_resources  = 1,
7410 +       .resource       = mv78xx0_ge01_resources,
7411 +};
7412 +
7413 +void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
7414 +{
7415 +       eth_data->shared = &mv78xx0_ge01_shared;
7416 +       eth_data->shared_smi = &mv78xx0_ge00_shared;
7417 +       mv78xx0_ge01.dev.platform_data = eth_data;
7418 +
7419 +       platform_device_register(&mv78xx0_ge01_shared);
7420 +       platform_device_register(&mv78xx0_ge01);
7421 +}
7422 +
7423 +
7424 +/*****************************************************************************
7425 + * GE10
7426 + ****************************************************************************/
7427 +struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
7428 +       .t_clk          = 0,
7429 +       .dram           = &mv78xx0_mbus_dram_info,
7430 +};
7431 +
7432 +static struct resource mv78xx0_ge10_shared_resources[] = {
7433 +       {
7434 +               .name   = "ge10 base",
7435 +               .start  = GE10_PHYS_BASE + 0x2000,
7436 +               .end    = GE10_PHYS_BASE + 0x3fff,
7437 +               .flags  = IORESOURCE_MEM,
7438 +       },
7439 +};
7440 +
7441 +static struct platform_device mv78xx0_ge10_shared = {
7442 +       .name           = MV643XX_ETH_SHARED_NAME,
7443 +       .id             = 2,
7444 +       .dev            = {
7445 +               .platform_data  = &mv78xx0_ge10_shared_data,
7446 +       },
7447 +       .num_resources  = 1,
7448 +       .resource       = mv78xx0_ge10_shared_resources,
7449 +};
7450 +
7451 +static struct resource mv78xx0_ge10_resources[] = {
7452 +       {
7453 +               .name   = "ge10 irq",
7454 +               .start  = IRQ_MV78XX0_GE10_SUM,
7455 +               .end    = IRQ_MV78XX0_GE10_SUM,
7456 +               .flags  = IORESOURCE_IRQ,
7457 +       },
7458 +};
7459 +
7460 +static struct platform_device mv78xx0_ge10 = {
7461 +       .name           = MV643XX_ETH_NAME,
7462 +       .id             = 2,
7463 +       .num_resources  = 1,
7464 +       .resource       = mv78xx0_ge10_resources,
7465 +};
7466 +
7467 +void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
7468 +{
7469 +       eth_data->shared = &mv78xx0_ge10_shared;
7470 +       eth_data->shared_smi = &mv78xx0_ge00_shared;
7471 +       mv78xx0_ge10.dev.platform_data = eth_data;
7472 +
7473 +       platform_device_register(&mv78xx0_ge10_shared);
7474 +       platform_device_register(&mv78xx0_ge10);
7475 +}
7476 +
7477 +
7478 +/*****************************************************************************
7479 + * GE11
7480 + ****************************************************************************/
7481 +struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
7482 +       .t_clk          = 0,
7483 +       .dram           = &mv78xx0_mbus_dram_info,
7484 +};
7485 +
7486 +static struct resource mv78xx0_ge11_shared_resources[] = {
7487 +       {
7488 +               .name   = "ge11 base",
7489 +               .start  = GE11_PHYS_BASE + 0x2000,
7490 +               .end    = GE11_PHYS_BASE + 0x3fff,
7491 +               .flags  = IORESOURCE_MEM,
7492 +       },
7493 +};
7494 +
7495 +static struct platform_device mv78xx0_ge11_shared = {
7496 +       .name           = MV643XX_ETH_SHARED_NAME,
7497 +       .id             = 3,
7498 +       .dev            = {
7499 +               .platform_data  = &mv78xx0_ge11_shared_data,
7500 +       },
7501 +       .num_resources  = 1,
7502 +       .resource       = mv78xx0_ge11_shared_resources,
7503 +};
7504 +
7505 +static struct resource mv78xx0_ge11_resources[] = {
7506 +       {
7507 +               .name   = "ge11 irq",
7508 +               .start  = IRQ_MV78XX0_GE11_SUM,
7509 +               .end    = IRQ_MV78XX0_GE11_SUM,
7510 +               .flags  = IORESOURCE_IRQ,
7511 +       },
7512 +};
7513 +
7514 +static struct platform_device mv78xx0_ge11 = {
7515 +       .name           = MV643XX_ETH_NAME,
7516 +       .id             = 3,
7517 +       .num_resources  = 1,
7518 +       .resource       = mv78xx0_ge11_resources,
7519 +};
7520 +
7521 +void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
7522 +{
7523 +       eth_data->shared = &mv78xx0_ge11_shared;
7524 +       eth_data->shared_smi = &mv78xx0_ge00_shared;
7525 +       mv78xx0_ge11.dev.platform_data = eth_data;
7526 +
7527 +       platform_device_register(&mv78xx0_ge11_shared);
7528 +       platform_device_register(&mv78xx0_ge11);
7529 +}
7530 +
7531 +
7532 +/*****************************************************************************
7533 + * SATA
7534 + ****************************************************************************/
7535 +static struct resource mv78xx0_sata_resources[] = {
7536 +       {
7537 +               .name   = "sata base",
7538 +               .start  = SATA_PHYS_BASE,
7539 +               .end    = SATA_PHYS_BASE + 0x5000 - 1,
7540 +               .flags  = IORESOURCE_MEM,
7541 +       }, {
7542 +               .name   = "sata irq",
7543 +               .start  = IRQ_MV78XX0_SATA,
7544 +               .end    = IRQ_MV78XX0_SATA,
7545 +               .flags  = IORESOURCE_IRQ,
7546 +       },
7547 +};
7548 +
7549 +static struct platform_device mv78xx0_sata = {
7550 +       .name           = "sata_mv",
7551 +       .id             = 0,
7552 +       .dev            = {
7553 +               .coherent_dma_mask      = 0xffffffff,
7554 +       },
7555 +       .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
7556 +       .resource       = mv78xx0_sata_resources,
7557 +};
7558 +
7559 +void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
7560 +{
7561 +       sata_data->dram = &mv78xx0_mbus_dram_info;
7562 +       mv78xx0_sata.dev.platform_data = sata_data;
7563 +       platform_device_register(&mv78xx0_sata);
7564 +}
7565 +
7566 +
7567 +/*****************************************************************************
7568 + * UART0
7569 + ****************************************************************************/
7570 +static struct plat_serial8250_port mv78xx0_uart0_data[] = {
7571 +       {
7572 +               .mapbase        = UART0_PHYS_BASE,
7573 +               .membase        = (char *)UART0_VIRT_BASE,
7574 +               .irq            = IRQ_MV78XX0_UART_0,
7575 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
7576 +               .iotype         = UPIO_MEM,
7577 +               .regshift       = 2,
7578 +               .uartclk        = 0,
7579 +       }, {
7580 +       },
7581 +};
7582 +
7583 +static struct resource mv78xx0_uart0_resources[] = {
7584 +       {
7585 +               .start          = UART0_PHYS_BASE,
7586 +               .end            = UART0_PHYS_BASE + 0xff,
7587 +               .flags          = IORESOURCE_MEM,
7588 +       }, {
7589 +               .start          = IRQ_MV78XX0_UART_0,
7590 +               .end            = IRQ_MV78XX0_UART_0,
7591 +               .flags          = IORESOURCE_IRQ,
7592 +       },
7593 +};
7594 +
7595 +static struct platform_device mv78xx0_uart0 = {
7596 +       .name                   = "serial8250",
7597 +       .id                     = 0,
7598 +       .dev                    = {
7599 +               .platform_data  = mv78xx0_uart0_data,
7600 +       },
7601 +       .resource               = mv78xx0_uart0_resources,
7602 +       .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
7603 +};
7604 +
7605 +void __init mv78xx0_uart0_init(void)
7606 +{
7607 +       platform_device_register(&mv78xx0_uart0);
7608 +}
7609 +
7610 +
7611 +/*****************************************************************************
7612 + * UART1
7613 + ****************************************************************************/
7614 +static struct plat_serial8250_port mv78xx0_uart1_data[] = {
7615 +       {
7616 +               .mapbase        = UART1_PHYS_BASE,
7617 +               .membase        = (char *)UART1_VIRT_BASE,
7618 +               .irq            = IRQ_MV78XX0_UART_1,
7619 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
7620 +               .iotype         = UPIO_MEM,
7621 +               .regshift       = 2,
7622 +               .uartclk        = 0,
7623 +       }, {
7624 +       },
7625 +};
7626 +
7627 +static struct resource mv78xx0_uart1_resources[] = {
7628 +       {
7629 +               .start          = UART1_PHYS_BASE,
7630 +               .end            = UART1_PHYS_BASE + 0xff,
7631 +               .flags          = IORESOURCE_MEM,
7632 +       }, {
7633 +               .start          = IRQ_MV78XX0_UART_1,
7634 +               .end            = IRQ_MV78XX0_UART_1,
7635 +               .flags          = IORESOURCE_IRQ,
7636 +       },
7637 +};
7638 +
7639 +static struct platform_device mv78xx0_uart1 = {
7640 +       .name                   = "serial8250",
7641 +       .id                     = 1,
7642 +       .dev                    = {
7643 +               .platform_data  = mv78xx0_uart1_data,
7644 +       },
7645 +       .resource               = mv78xx0_uart1_resources,
7646 +       .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
7647 +};
7648 +
7649 +void __init mv78xx0_uart1_init(void)
7650 +{
7651 +       platform_device_register(&mv78xx0_uart1);
7652 +}
7653 +
7654 +
7655 +/*****************************************************************************
7656 + * UART2
7657 + ****************************************************************************/
7658 +static struct plat_serial8250_port mv78xx0_uart2_data[] = {
7659 +       {
7660 +               .mapbase        = UART2_PHYS_BASE,
7661 +               .membase        = (char *)UART2_VIRT_BASE,
7662 +               .irq            = IRQ_MV78XX0_UART_2,
7663 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
7664 +               .iotype         = UPIO_MEM,
7665 +               .regshift       = 2,
7666 +               .uartclk        = 0,
7667 +       }, {
7668 +       },
7669 +};
7670 +
7671 +static struct resource mv78xx0_uart2_resources[] = {
7672 +       {
7673 +               .start          = UART2_PHYS_BASE,
7674 +               .end            = UART2_PHYS_BASE + 0xff,
7675 +               .flags          = IORESOURCE_MEM,
7676 +       }, {
7677 +               .start          = IRQ_MV78XX0_UART_2,
7678 +               .end            = IRQ_MV78XX0_UART_2,
7679 +               .flags          = IORESOURCE_IRQ,
7680 +       },
7681 +};
7682 +
7683 +static struct platform_device mv78xx0_uart2 = {
7684 +       .name                   = "serial8250",
7685 +       .id                     = 2,
7686 +       .dev                    = {
7687 +               .platform_data  = mv78xx0_uart2_data,
7688 +       },
7689 +       .resource               = mv78xx0_uart2_resources,
7690 +       .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
7691 +};
7692 +
7693 +void __init mv78xx0_uart2_init(void)
7694 +{
7695 +       platform_device_register(&mv78xx0_uart2);
7696 +}
7697 +
7698 +
7699 +/*****************************************************************************
7700 + * UART3
7701 + ****************************************************************************/
7702 +static struct plat_serial8250_port mv78xx0_uart3_data[] = {
7703 +       {
7704 +               .mapbase        = UART3_PHYS_BASE,
7705 +               .membase        = (char *)UART3_VIRT_BASE,
7706 +               .irq            = IRQ_MV78XX0_UART_3,
7707 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
7708 +               .iotype         = UPIO_MEM,
7709 +               .regshift       = 2,
7710 +               .uartclk        = 0,
7711 +       }, {
7712 +       },
7713 +};
7714 +
7715 +static struct resource mv78xx0_uart3_resources[] = {
7716 +       {
7717 +               .start          = UART3_PHYS_BASE,
7718 +               .end            = UART3_PHYS_BASE + 0xff,
7719 +               .flags          = IORESOURCE_MEM,
7720 +       }, {
7721 +               .start          = IRQ_MV78XX0_UART_3,
7722 +               .end            = IRQ_MV78XX0_UART_3,
7723 +               .flags          = IORESOURCE_IRQ,
7724 +       },
7725 +};
7726 +
7727 +static struct platform_device mv78xx0_uart3 = {
7728 +       .name                   = "serial8250",
7729 +       .id                     = 3,
7730 +       .dev                    = {
7731 +               .platform_data  = mv78xx0_uart3_data,
7732 +       },
7733 +       .resource               = mv78xx0_uart3_resources,
7734 +       .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
7735 +};
7736 +
7737 +void __init mv78xx0_uart3_init(void)
7738 +{
7739 +       platform_device_register(&mv78xx0_uart3);
7740 +}
7741 +
7742 +
7743 +/*****************************************************************************
7744 + * Time handling
7745 + ****************************************************************************/
7746 +static void mv78xx0_timer_init(void)
7747 +{
7748 +       orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
7749 +}
7750 +
7751 +struct sys_timer mv78xx0_timer = {
7752 +       .init = mv78xx0_timer_init,
7753 +};
7754 +
7755 +
7756 +/*****************************************************************************
7757 + * General
7758 + ****************************************************************************/
7759 +static int __init is_l2_writethrough(void)
7760 +{
7761 +       return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
7762 +}
7763 +
7764 +void __init mv78xx0_init(void)
7765 +{
7766 +       int core_index;
7767 +       int hclk;
7768 +       int pclk;
7769 +       int l2clk;
7770 +       int tclk;
7771 +
7772 +       core_index = mv78xx0_core_index();
7773 +       hclk = get_hclk();
7774 +       get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
7775 +       tclk = get_tclk();
7776 +
7777 +       printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
7778 +       printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
7779 +       printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
7780 +       printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
7781 +       printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
7782 +
7783 +       mv78xx0_setup_cpu_mbus();
7784 +
7785 +#ifdef CONFIG_CACHE_FEROCEON_L2
7786 +       feroceon_l2_init(is_l2_writethrough());
7787 +#endif
7788 +
7789 +       mv78xx0_ge00_shared_data.t_clk = tclk;
7790 +       mv78xx0_ge01_shared_data.t_clk = tclk;
7791 +       mv78xx0_ge10_shared_data.t_clk = tclk;
7792 +       mv78xx0_ge11_shared_data.t_clk = tclk;
7793 +       mv78xx0_uart0_data[0].uartclk = tclk;
7794 +       mv78xx0_uart1_data[0].uartclk = tclk;
7795 +       mv78xx0_uart2_data[0].uartclk = tclk;
7796 +       mv78xx0_uart3_data[0].uartclk = tclk;
7797 +}
7798 --- /dev/null
7799 +++ b/arch/arm/mach-mv78xx0/common.h
7800 @@ -0,0 +1,49 @@
7801 +/*
7802 + * arch/arm/mach-mv78xx0/common.h
7803 + *
7804 + * Core functions for Marvell MV78xx0 SoCs
7805 + *
7806 + * This file is licensed under the terms of the GNU General Public
7807 + * License version 2.  This program is licensed "as is" without any
7808 + * warranty of any kind, whether express or implied.
7809 + */
7810 +
7811 +#ifndef __ARCH_MV78XX0_COMMON_H
7812 +#define __ARCH_MV78XX0_COMMON_H
7813 +
7814 +struct mv643xx_eth_platform_data;
7815 +struct mv_sata_platform_data;
7816 +
7817 +/*
7818 + * Basic MV78xx0 init functions used early by machine-setup.
7819 + */
7820 +int mv78xx0_core_index(void);
7821 +void mv78xx0_map_io(void);
7822 +void mv78xx0_init(void);
7823 +void mv78xx0_init_irq(void);
7824 +
7825 +extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
7826 +void mv78xx0_setup_cpu_mbus(void);
7827 +void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
7828 +                              int maj, int min);
7829 +void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
7830 +                               int maj, int min);
7831 +
7832 +void mv78xx0_ehci0_init(void);
7833 +void mv78xx0_ehci1_init(void);
7834 +void mv78xx0_ehci2_init(void);
7835 +void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
7836 +void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
7837 +void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
7838 +void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
7839 +void mv78xx0_pcie_init(int init_port0, int init_port1);
7840 +void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
7841 +void mv78xx0_uart0_init(void);
7842 +void mv78xx0_uart1_init(void);
7843 +void mv78xx0_uart2_init(void);
7844 +void mv78xx0_uart3_init(void);
7845 +
7846 +extern struct sys_timer mv78xx0_timer;
7847 +
7848 +
7849 +#endif
7850 --- /dev/null
7851 +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
7852 @@ -0,0 +1,94 @@
7853 +/*
7854 + * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
7855 + *
7856 + * Marvell DB-78x00-BP Development Board Setup
7857 + *
7858 + * This file is licensed under the terms of the GNU General Public
7859 + * License version 2.  This program is licensed "as is" without any
7860 + * warranty of any kind, whether express or implied.
7861 + */
7862 +
7863 +#include <linux/kernel.h>
7864 +#include <linux/init.h>
7865 +#include <linux/platform_device.h>
7866 +#include <linux/ata_platform.h>
7867 +#include <linux/mv643xx_eth.h>
7868 +#include <asm/arch/mv78xx0.h>
7869 +#include <asm/mach-types.h>
7870 +#include <asm/mach/arch.h>
7871 +#include "common.h"
7872 +
7873 +static struct mv643xx_eth_platform_data db78x00_ge00_data = {
7874 +       .phy_addr       = 8,
7875 +};
7876 +
7877 +static struct mv643xx_eth_platform_data db78x00_ge01_data = {
7878 +       .phy_addr       = 9,
7879 +};
7880 +
7881 +static struct mv643xx_eth_platform_data db78x00_ge10_data = {
7882 +       .phy_addr       = -1,
7883 +};
7884 +
7885 +static struct mv643xx_eth_platform_data db78x00_ge11_data = {
7886 +       .phy_addr       = -1,
7887 +};
7888 +
7889 +static struct mv_sata_platform_data db78x00_sata_data = {
7890 +       .n_ports        = 2,
7891 +};
7892 +
7893 +static void __init db78x00_init(void)
7894 +{
7895 +       /*
7896 +        * Basic MV78xx0 setup. Needs to be called early.
7897 +        */
7898 +       mv78xx0_init();
7899 +
7900 +       /*
7901 +        * Partition on-chip peripherals between the two CPU cores.
7902 +        */
7903 +       if (mv78xx0_core_index() == 0) {
7904 +               mv78xx0_ehci0_init();
7905 +               mv78xx0_ehci1_init();
7906 +               mv78xx0_ehci2_init();
7907 +               mv78xx0_ge00_init(&db78x00_ge00_data);
7908 +               mv78xx0_ge01_init(&db78x00_ge01_data);
7909 +               mv78xx0_ge10_init(&db78x00_ge10_data);
7910 +               mv78xx0_ge11_init(&db78x00_ge11_data);
7911 +               mv78xx0_sata_init(&db78x00_sata_data);
7912 +               mv78xx0_uart0_init();
7913 +               mv78xx0_uart2_init();
7914 +       } else {
7915 +               mv78xx0_uart1_init();
7916 +               mv78xx0_uart3_init();
7917 +       }
7918 +}
7919 +
7920 +static int __init db78x00_pci_init(void)
7921 +{
7922 +       if (machine_is_db78x00_bp()) {
7923 +               /*
7924 +                * Assign the x16 PCIe slot on the board to CPU core
7925 +                * #0, and let CPU core #1 have the four x1 slots.
7926 +                */
7927 +               if (mv78xx0_core_index() == 0)
7928 +                       mv78xx0_pcie_init(0, 1);
7929 +               else
7930 +                       mv78xx0_pcie_init(1, 0);
7931 +       }
7932 +
7933 +       return 0;
7934 +}
7935 +subsys_initcall(db78x00_pci_init);
7936 +
7937 +MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
7938 +       /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
7939 +       .phys_io        = MV78XX0_REGS_PHYS_BASE,
7940 +       .io_pg_offst    = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
7941 +       .boot_params    = 0x00000100,
7942 +       .init_machine   = db78x00_init,
7943 +       .map_io         = mv78xx0_map_io,
7944 +       .init_irq       = mv78xx0_init_irq,
7945 +       .timer          = &mv78xx0_timer,
7946 +MACHINE_END
7947 --- /dev/null
7948 +++ b/arch/arm/mach-mv78xx0/irq.c
7949 @@ -0,0 +1,22 @@
7950 +/*
7951 + * arch/arm/mach-mv78xx0/irq.c
7952 + *
7953 + * MV78xx0 IRQ handling.
7954 + *
7955 + * This file is licensed under the terms of the GNU General Public
7956 + * License version 2.  This program is licensed "as is" without any
7957 + * warranty of any kind, whether express or implied.
7958 + */
7959 +
7960 +#include <linux/kernel.h>
7961 +#include <linux/init.h>
7962 +#include <linux/pci.h>
7963 +#include <asm/arch/mv78xx0.h>
7964 +#include <asm/plat-orion/irq.h>
7965 +#include "common.h"
7966 +
7967 +void __init mv78xx0_init_irq(void)
7968 +{
7969 +       orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
7970 +       orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
7971 +}
7972 --- /dev/null
7973 +++ b/arch/arm/mach-mv78xx0/pcie.c
7974 @@ -0,0 +1,312 @@
7975 +/*
7976 + * arch/arm/mach-mv78xx0/pcie.c
7977 + *
7978 + * PCIe functions for Marvell MV78xx0 SoCs
7979 + *
7980 + * This file is licensed under the terms of the GNU General Public
7981 + * License version 2.  This program is licensed "as is" without any
7982 + * warranty of any kind, whether express or implied.
7983 + */
7984 +
7985 +#include <linux/kernel.h>
7986 +#include <linux/pci.h>
7987 +#include <linux/mbus.h>
7988 +#include <asm/mach/pci.h>
7989 +#include <asm/plat-orion/pcie.h>
7990 +#include "common.h"
7991 +
7992 +struct pcie_port {
7993 +       u8                      maj;
7994 +       u8                      min;
7995 +       u8                      root_bus_nr;
7996 +       void __iomem            *base;
7997 +       spinlock_t              conf_lock;
7998 +       char                    io_space_name[16];
7999 +       char                    mem_space_name[16];
8000 +       struct resource         res[2];
8001 +};
8002 +
8003 +static struct pcie_port pcie_port[8];
8004 +static int num_pcie_ports;
8005 +static struct resource pcie_io_space;
8006 +static struct resource pcie_mem_space;
8007 +
8008 +
8009 +static void __init mv78xx0_pcie_preinit(void)
8010 +{
8011 +       int i;
8012 +       u32 size_each;
8013 +       u32 start;
8014 +       int win;
8015 +
8016 +       pcie_io_space.name = "PCIe I/O Space";
8017 +       pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
8018 +       pcie_io_space.end =
8019 +               MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
8020 +       pcie_io_space.flags = IORESOURCE_IO;
8021 +       if (request_resource(&iomem_resource, &pcie_io_space))
8022 +               panic("can't allocate PCIe I/O space");
8023 +
8024 +       pcie_mem_space.name = "PCIe MEM Space";
8025 +       pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
8026 +       pcie_mem_space.end =
8027 +               MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
8028 +       pcie_mem_space.flags = IORESOURCE_MEM;
8029 +       if (request_resource(&iomem_resource, &pcie_mem_space))
8030 +               panic("can't allocate PCIe MEM space");
8031 +
8032 +       for (i = 0; i < num_pcie_ports; i++) {
8033 +               struct pcie_port *pp = pcie_port + i;
8034 +
8035 +               snprintf(pp->io_space_name, sizeof(pp->io_space_name),
8036 +                       "PCIe %d.%d I/O", pp->maj, pp->min);
8037 +               pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
8038 +               pp->res[0].name = pp->io_space_name;
8039 +               pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
8040 +               pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
8041 +               pp->res[0].flags = IORESOURCE_IO;
8042 +
8043 +               snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
8044 +                       "PCIe %d.%d MEM", pp->maj, pp->min);
8045 +               pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
8046 +               pp->res[1].name = pp->mem_space_name;
8047 +               pp->res[1].flags = IORESOURCE_MEM;
8048 +       }
8049 +
8050 +       switch (num_pcie_ports) {
8051 +       case 0:
8052 +               size_each = 0;
8053 +               break;
8054 +
8055 +       case 1:
8056 +               size_each = 0x30000000;
8057 +               break;
8058 +
8059 +       case 2 ... 3:
8060 +               size_each = 0x10000000;
8061 +               break;
8062 +
8063 +       case 4 ... 6:
8064 +               size_each = 0x08000000;
8065 +               break;
8066 +
8067 +       case 7:
8068 +               size_each = 0x04000000;
8069 +               break;
8070 +
8071 +       default:
8072 +               panic("invalid number of PCIe ports");
8073 +       }
8074 +
8075 +       start = MV78XX0_PCIE_MEM_PHYS_BASE;
8076 +       for (i = 0; i < num_pcie_ports; i++) {
8077 +               struct pcie_port *pp = pcie_port + i;
8078 +
8079 +               pp->res[1].start = start;
8080 +               pp->res[1].end = start + size_each - 1;
8081 +               start += size_each;
8082 +       }
8083 +
8084 +       for (i = 0; i < num_pcie_ports; i++) {
8085 +               struct pcie_port *pp = pcie_port + i;
8086 +
8087 +               if (request_resource(&pcie_io_space, &pp->res[0]))
8088 +                       panic("can't allocate PCIe I/O sub-space");
8089 +
8090 +               if (request_resource(&pcie_mem_space, &pp->res[1]))
8091 +                       panic("can't allocate PCIe MEM sub-space");
8092 +       }
8093 +
8094 +       win = 0;
8095 +       for (i = 0; i < num_pcie_ports; i++) {
8096 +               struct pcie_port *pp = pcie_port + i;
8097 +
8098 +               mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
8099 +                       pp->res[0].end - pp->res[0].start + 1,
8100 +                       pp->maj, pp->min);
8101 +
8102 +               mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
8103 +                       pp->res[1].end - pp->res[1].start + 1,
8104 +                       pp->maj, pp->min);
8105 +       }
8106 +}
8107 +
8108 +static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
8109 +{
8110 +       struct pcie_port *pp;
8111 +
8112 +       if (nr >= num_pcie_ports)
8113 +               return 0;
8114 +
8115 +       pp = &pcie_port[nr];
8116 +       pp->root_bus_nr = sys->busnr;
8117 +
8118 +       /*
8119 +        * Generic PCIe unit setup.
8120 +        */
8121 +       orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
8122 +       orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
8123 +
8124 +       sys->resource[0] = &pp->res[0];
8125 +       sys->resource[1] = &pp->res[1];
8126 +       sys->resource[2] = NULL;
8127 +
8128 +       return 1;
8129 +}
8130 +
8131 +static struct pcie_port *bus_to_port(int bus)
8132 +{
8133 +       int i;
8134 +
8135 +       for (i = num_pcie_ports - 1; i >= 0; i--) {
8136 +               int rbus = pcie_port[i].root_bus_nr;
8137 +               if (rbus != -1 && rbus <= bus)
8138 +                       break;
8139 +       }
8140 +
8141 +       return i >= 0 ? pcie_port + i : NULL;
8142 +}
8143 +
8144 +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
8145 +{
8146 +       /*
8147 +        * Don't go out when trying to access nonexisting devices
8148 +        * on the local bus.
8149 +        */
8150 +       if (bus == pp->root_bus_nr && dev > 1)
8151 +               return 0;
8152 +
8153 +       return 1;
8154 +}
8155 +
8156 +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
8157 +                       int size, u32 *val)
8158 +{
8159 +       struct pcie_port *pp = bus_to_port(bus->number);
8160 +       unsigned long flags;
8161 +       int ret;
8162 +
8163 +       if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
8164 +               *val = 0xffffffff;
8165 +               return PCIBIOS_DEVICE_NOT_FOUND;
8166 +       }
8167 +
8168 +       spin_lock_irqsave(&pp->conf_lock, flags);
8169 +       ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
8170 +       spin_unlock_irqrestore(&pp->conf_lock, flags);
8171 +
8172 +       return ret;
8173 +}
8174 +
8175 +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
8176 +                       int where, int size, u32 val)
8177 +{
8178 +       struct pcie_port *pp = bus_to_port(bus->number);
8179 +       unsigned long flags;
8180 +       int ret;
8181 +
8182 +       if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
8183 +               return PCIBIOS_DEVICE_NOT_FOUND;
8184 +
8185 +       spin_lock_irqsave(&pp->conf_lock, flags);
8186 +       ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
8187 +       spin_unlock_irqrestore(&pp->conf_lock, flags);
8188 +
8189 +       return ret;
8190 +}
8191 +
8192 +static struct pci_ops pcie_ops = {
8193 +       .read = pcie_rd_conf,
8194 +       .write = pcie_wr_conf,
8195 +};
8196 +
8197 +static void __devinit rc_pci_fixup(struct pci_dev *dev)
8198 +{
8199 +       /*
8200 +        * Prevent enumeration of root complex.
8201 +        */
8202 +       if (dev->bus->parent == NULL && dev->devfn == 0) {
8203 +               int i;
8204 +
8205 +               for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
8206 +                       dev->resource[i].start = 0;
8207 +                       dev->resource[i].end   = 0;
8208 +                       dev->resource[i].flags = 0;
8209 +               }
8210 +       }
8211 +}
8212 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
8213 +
8214 +static struct pci_bus __init *
8215 +mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
8216 +{
8217 +       struct pci_bus *bus;
8218 +
8219 +       if (nr < num_pcie_ports) {
8220 +               bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
8221 +       } else {
8222 +               bus = NULL;
8223 +               BUG();
8224 +       }
8225 +
8226 +       return bus;
8227 +}
8228 +
8229 +static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
8230 +{
8231 +       struct pcie_port *pp = bus_to_port(dev->bus->number);
8232 +
8233 +       return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
8234 +}
8235 +
8236 +static struct hw_pci mv78xx0_pci __initdata = {
8237 +       .nr_controllers = 8,
8238 +       .preinit        = mv78xx0_pcie_preinit,
8239 +       .swizzle        = pci_std_swizzle,
8240 +       .setup          = mv78xx0_pcie_setup,
8241 +       .scan           = mv78xx0_pcie_scan_bus,
8242 +       .map_irq        = mv78xx0_pcie_map_irq,
8243 +};
8244 +
8245 +static void __init add_pcie_port(int maj, int min, unsigned long base)
8246 +{
8247 +       printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
8248 +
8249 +       if (orion_pcie_link_up((void __iomem *)base)) {
8250 +               struct pcie_port *pp = &pcie_port[num_pcie_ports++];
8251 +
8252 +               printk("link up\n");
8253 +
8254 +               pp->maj = maj;
8255 +               pp->min = min;
8256 +               pp->root_bus_nr = -1;
8257 +               pp->base = (void __iomem *)base;
8258 +               spin_lock_init(&pp->conf_lock);
8259 +               memset(pp->res, 0, sizeof(pp->res));
8260 +       } else {
8261 +               printk("link down, ignoring\n");
8262 +       }
8263 +}
8264 +
8265 +void __init mv78xx0_pcie_init(int init_port0, int init_port1)
8266 +{
8267 +       if (init_port0) {
8268 +               add_pcie_port(0, 0, PCIE00_VIRT_BASE);
8269 +               if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
8270 +                       add_pcie_port(0, 1, PCIE01_VIRT_BASE);
8271 +                       add_pcie_port(0, 2, PCIE02_VIRT_BASE);
8272 +                       add_pcie_port(0, 3, PCIE03_VIRT_BASE);
8273 +               }
8274 +       }
8275 +
8276 +       if (init_port1) {
8277 +               add_pcie_port(1, 0, PCIE10_VIRT_BASE);
8278 +               if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
8279 +                       add_pcie_port(1, 1, PCIE11_VIRT_BASE);
8280 +                       add_pcie_port(1, 2, PCIE12_VIRT_BASE);
8281 +                       add_pcie_port(1, 3, PCIE13_VIRT_BASE);
8282 +               }
8283 +       }
8284 +
8285 +       pci_common_init(&mv78xx0_pci);
8286 +}
8287 --- a/arch/arm/mach-orion5x/Kconfig
8288 +++ b/arch/arm/mach-orion5x/Kconfig
8289 @@ -44,6 +44,36 @@
8290           Buffalo Linkstation Pro/Live platform. Both v1 and
8291           v2 devices are supported.
8292
8293 +config MACH_TS409
8294 +       bool "QNAP TS-409"
8295 +       help
8296 +         Say 'Y' here if you want your kernel to support the
8297 +         QNAP TS-409 platform.
8298 +
8299 +config MACH_WRT350N_V2
8300 +       bool "Linksys WRT350N v2"
8301 +       help
8302 +         Say 'Y' here if you want your kernel to support the
8303 +         Linksys WRT350N v2 platform.
8304 +
8305 +config MACH_TS78XX
8306 +       bool "Technologic Systems TS-78xx"
8307 +       help
8308 +         Say 'Y' here if you want your kernel to support the
8309 +         Technologic Systems TS-78xx platform.
8310 +
8311 +config MACH_MV2120
8312 +       bool "HP Media Vault mv2120"
8313 +       help
8314 +         Say 'Y' here if you want your kernel to support the
8315 +         HP Media Vault mv2120 or mv5100.
8316 +
8317 +config MACH_MSS2
8318 +       bool "Maxtor Shared Storage II"
8319 +       help
8320 +         Say 'Y' here if you want your kernel to support the
8321 +         Maxtor Shared Storage II platform.
8322 +
8323  endmenu
8324
8325  endif
8326 --- a/arch/arm/mach-orion5x/Makefile
8327 +++ b/arch/arm/mach-orion5x/Makefile
8328 @@ -1,7 +1,12 @@
8329 -obj-y                          += common.o addr-map.o pci.o gpio.o irq.o
8330 +obj-y                          += common.o addr-map.o pci.o gpio.o irq.o mpp.o
8331  obj-$(CONFIG_MACH_DB88F5281)   += db88f5281-setup.o
8332  obj-$(CONFIG_MACH_RD88F5182)   += rd88f5182-setup.o
8333  obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
8334  obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
8335  obj-$(CONFIG_MACH_DNS323)      += dns323-setup.o
8336 -obj-$(CONFIG_MACH_TS209)       += ts209-setup.o
8337 +obj-$(CONFIG_MACH_TS209)       += ts209-setup.o tsx09-common.o
8338 +obj-$(CONFIG_MACH_TS409)       += ts409-setup.o tsx09-common.o
8339 +obj-$(CONFIG_MACH_WRT350N_V2)  += wrt350n-v2-setup.o
8340 +obj-$(CONFIG_MACH_TS78XX)      += ts78xx-setup.o
8341 +obj-$(CONFIG_MACH_MV2120)      += mv2120-setup.o
8342 +obj-$(CONFIG_MACH_MSS2)                += mss2-setup.o
8343 --- a/arch/arm/mach-orion5x/addr-map.c
8344 +++ b/arch/arm/mach-orion5x/addr-map.c
8345 @@ -70,6 +70,7 @@
8346
8347
8348  struct mbus_dram_target_info orion5x_mbus_dram_info;
8349 +static int __initdata win_alloc_count;
8350
8351  static int __init orion5x_cpu_win_can_remap(int win)
8352  {
8353 @@ -87,16 +88,22 @@
8354  static void __init setup_cpu_win(int win, u32 base, u32 size,
8355                                  u8 target, u8 attr, int remap)
8356  {
8357 -       orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
8358 -       orion5x_write(CPU_WIN_CTRL(win),
8359 -               ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
8360 +       if (win >= 8) {
8361 +               printk(KERN_ERR "setup_cpu_win: trying to allocate "
8362 +                               "window %d\n", win);
8363 +               return;
8364 +       }
8365 +
8366 +       writel(base & 0xffff0000, CPU_WIN_BASE(win));
8367 +       writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
8368 +               CPU_WIN_CTRL(win));
8369
8370         if (orion5x_cpu_win_can_remap(win)) {
8371                 if (remap < 0)
8372                         remap = base;
8373
8374 -               orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
8375 -               orion5x_write(CPU_WIN_REMAP_HI(win), 0);
8376 +               writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
8377 +               writel(0, CPU_WIN_REMAP_HI(win));
8378         }
8379  }
8380
8381 @@ -109,11 +116,11 @@
8382          * First, disable and clear windows.
8383          */
8384         for (i = 0; i < 8; i++) {
8385 -               orion5x_write(CPU_WIN_BASE(i), 0);
8386 -               orion5x_write(CPU_WIN_CTRL(i), 0);
8387 +               writel(0, CPU_WIN_BASE(i));
8388 +               writel(0, CPU_WIN_CTRL(i));
8389                 if (orion5x_cpu_win_can_remap(i)) {
8390 -                       orion5x_write(CPU_WIN_REMAP_LO(i), 0);
8391 -                       orion5x_write(CPU_WIN_REMAP_HI(i), 0);
8392 +                       writel(0, CPU_WIN_REMAP_LO(i));
8393 +                       writel(0, CPU_WIN_REMAP_HI(i));
8394                 }
8395         }
8396
8397 @@ -128,6 +135,7 @@
8398                 TARGET_PCIE, ATTR_PCIE_MEM, -1);
8399         setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
8400                 TARGET_PCI, ATTR_PCI_MEM, -1);
8401 +       win_alloc_count = 4;
8402
8403         /*
8404          * Setup MBUS dram target info.
8405 @@ -147,8 +155,8 @@
8406                         w = &orion5x_mbus_dram_info.cs[cs++];
8407                         w->cs_index = i;
8408                         w->mbus_attr = 0xf & ~(1 << i);
8409 -                       w->base = base & 0xff000000;
8410 -                       w->size = (size | 0x00ffffff) + 1;
8411 +                       w->base = base & 0xffff0000;
8412 +                       w->size = (size | 0x0000ffff) + 1;
8413                 }
8414         }
8415         orion5x_mbus_dram_info.num_cs = cs;
8416 @@ -156,25 +164,30 @@
8417
8418  void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
8419  {
8420 -       setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
8421 +       setup_cpu_win(win_alloc_count++, base, size,
8422 +                     TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
8423  }
8424
8425  void __init orion5x_setup_dev0_win(u32 base, u32 size)
8426  {
8427 -       setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
8428 +       setup_cpu_win(win_alloc_count++, base, size,
8429 +                     TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
8430  }
8431
8432  void __init orion5x_setup_dev1_win(u32 base, u32 size)
8433  {
8434 -       setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
8435 +       setup_cpu_win(win_alloc_count++, base, size,
8436 +                     TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
8437  }
8438
8439  void __init orion5x_setup_dev2_win(u32 base, u32 size)
8440  {
8441 -       setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
8442 +       setup_cpu_win(win_alloc_count++, base, size,
8443 +                     TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
8444  }
8445
8446  void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
8447  {
8448 -       setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
8449 +       setup_cpu_win(win_alloc_count++, base, size,
8450 +                     TARGET_PCIE, ATTR_PCIE_WA, -1);
8451  }
8452 --- a/arch/arm/mach-orion5x/common.c
8453 +++ b/arch/arm/mach-orion5x/common.c
8454 @@ -39,25 +39,22 @@
8455                 .virtual        = ORION5X_REGS_VIRT_BASE,
8456                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
8457                 .length         = ORION5X_REGS_SIZE,
8458 -               .type           = MT_DEVICE
8459 -       },
8460 -       {
8461 +               .type           = MT_DEVICE,
8462 +       }, {
8463                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
8464                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
8465                 .length         = ORION5X_PCIE_IO_SIZE,
8466 -               .type           = MT_DEVICE
8467 -       },
8468 -       {
8469 +               .type           = MT_DEVICE,
8470 +       }, {
8471                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
8472                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
8473                 .length         = ORION5X_PCI_IO_SIZE,
8474 -               .type           = MT_DEVICE
8475 -       },
8476 -       {
8477 +               .type           = MT_DEVICE,
8478 +       }, {
8479                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
8480                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
8481                 .length         = ORION5X_PCIE_WA_SIZE,
8482 -               .type           = MT_DEVICE
8483 +               .type           = MT_DEVICE,
8484         },
8485  };
8486
8487 @@ -66,101 +63,32 @@
8488         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
8489  }
8490
8491 +
8492  /*****************************************************************************
8493 - * UART
8494 + * EHCI
8495   ****************************************************************************/
8496 -
8497 -static struct resource orion5x_uart_resources[] = {
8498 -       {
8499 -               .start          = UART0_PHYS_BASE,
8500 -               .end            = UART0_PHYS_BASE + 0xff,
8501 -               .flags          = IORESOURCE_MEM,
8502 -       },
8503 -       {
8504 -               .start          = IRQ_ORION5X_UART0,
8505 -               .end            = IRQ_ORION5X_UART0,
8506 -               .flags          = IORESOURCE_IRQ,
8507 -       },
8508 -       {
8509 -               .start          = UART1_PHYS_BASE,
8510 -               .end            = UART1_PHYS_BASE + 0xff,
8511 -               .flags          = IORESOURCE_MEM,
8512 -       },
8513 -       {
8514 -               .start          = IRQ_ORION5X_UART1,
8515 -               .end            = IRQ_ORION5X_UART1,
8516 -               .flags          = IORESOURCE_IRQ,
8517 -       },
8518 -};
8519 -
8520 -static struct plat_serial8250_port orion5x_uart_data[] = {
8521 -       {
8522 -               .mapbase        = UART0_PHYS_BASE,
8523 -               .membase        = (char *)UART0_VIRT_BASE,
8524 -               .irq            = IRQ_ORION5X_UART0,
8525 -               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
8526 -               .iotype         = UPIO_MEM,
8527 -               .regshift       = 2,
8528 -               .uartclk        = ORION5X_TCLK,
8529 -       },
8530 -       {
8531 -               .mapbase        = UART1_PHYS_BASE,
8532 -               .membase        = (char *)UART1_VIRT_BASE,
8533 -               .irq            = IRQ_ORION5X_UART1,
8534 -               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
8535 -               .iotype         = UPIO_MEM,
8536 -               .regshift       = 2,
8537 -               .uartclk        = ORION5X_TCLK,
8538 -       },
8539 -       { },
8540 +static struct orion_ehci_data orion5x_ehci_data = {
8541 +       .dram           = &orion5x_mbus_dram_info,
8542  };
8543
8544 -static struct platform_device orion5x_uart = {
8545 -       .name                   = "serial8250",
8546 -       .id                     = PLAT8250_DEV_PLATFORM,
8547 -       .dev                    = {
8548 -               .platform_data  = orion5x_uart_data,
8549 -       },
8550 -       .resource               = orion5x_uart_resources,
8551 -       .num_resources          = ARRAY_SIZE(orion5x_uart_resources),
8552 -};
8553 +static u64 ehci_dmamask = 0xffffffffUL;
8554
8555 -/*******************************************************************************
8556 - * USB Controller - 2 interfaces
8557 - ******************************************************************************/
8558
8559 +/*****************************************************************************
8560 + * EHCI0
8561 + ****************************************************************************/
8562  static struct resource orion5x_ehci0_resources[] = {
8563         {
8564                 .start  = ORION5X_USB0_PHYS_BASE,
8565                 .end    = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
8566                 .flags  = IORESOURCE_MEM,
8567 -       },
8568 -       {
8569 +       }, {
8570                 .start  = IRQ_ORION5X_USB0_CTRL,
8571                 .end    = IRQ_ORION5X_USB0_CTRL,
8572                 .flags  = IORESOURCE_IRQ,
8573         },
8574  };
8575
8576 -static struct resource orion5x_ehci1_resources[] = {
8577 -       {
8578 -               .start  = ORION5X_USB1_PHYS_BASE,
8579 -               .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
8580 -               .flags  = IORESOURCE_MEM,
8581 -       },
8582 -       {
8583 -               .start  = IRQ_ORION5X_USB1_CTRL,
8584 -               .end    = IRQ_ORION5X_USB1_CTRL,
8585 -               .flags  = IORESOURCE_IRQ,
8586 -       },
8587 -};
8588 -
8589 -static struct orion_ehci_data orion5x_ehci_data = {
8590 -       .dram           = &orion5x_mbus_dram_info,
8591 -};
8592 -
8593 -static u64 ehci_dmamask = 0xffffffffUL;
8594 -
8595  static struct platform_device orion5x_ehci0 = {
8596         .name           = "orion-ehci",
8597         .id             = 0,
8598 @@ -173,6 +101,27 @@
8599         .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
8600  };
8601
8602 +void __init orion5x_ehci0_init(void)
8603 +{
8604 +       platform_device_register(&orion5x_ehci0);
8605 +}
8606 +
8607 +
8608 +/*****************************************************************************
8609 + * EHCI1
8610 + ****************************************************************************/
8611 +static struct resource orion5x_ehci1_resources[] = {
8612 +       {
8613 +               .start  = ORION5X_USB1_PHYS_BASE,
8614 +               .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
8615 +               .flags  = IORESOURCE_MEM,
8616 +       }, {
8617 +               .start  = IRQ_ORION5X_USB1_CTRL,
8618 +               .end    = IRQ_ORION5X_USB1_CTRL,
8619 +               .flags  = IORESOURCE_IRQ,
8620 +       },
8621 +};
8622 +
8623  static struct platform_device orion5x_ehci1 = {
8624         .name           = "orion-ehci",
8625         .id             = 1,
8626 @@ -185,11 +134,15 @@
8627         .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
8628  };
8629
8630 +void __init orion5x_ehci1_init(void)
8631 +{
8632 +       platform_device_register(&orion5x_ehci1);
8633 +}
8634 +
8635 +
8636  /*****************************************************************************
8637 - * Gigabit Ethernet port
8638 - * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
8639 + * GigE
8640   ****************************************************************************/
8641 -
8642  struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
8643         .dram           = &orion5x_mbus_dram_info,
8644         .t_clk          = ORION5X_TCLK,
8645 @@ -219,7 +172,7 @@
8646                 .start  = IRQ_ORION5X_ETH_SUM,
8647                 .end    = IRQ_ORION5X_ETH_SUM,
8648                 .flags  = IORESOURCE_IRQ,
8649 -       }
8650 +       },
8651  };
8652
8653  static struct platform_device orion5x_eth = {
8654 @@ -238,11 +191,10 @@
8655         platform_device_register(&orion5x_eth);
8656  }
8657
8658 +
8659  /*****************************************************************************
8660 - * I2C controller
8661 - * (The Orion and Discovery (MV643xx) families share the same I2C controller)
8662 + * I2C
8663   ****************************************************************************/
8664 -
8665  static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
8666         .freq_m         = 8, /* assumes 166 MHz TCLK */
8667         .freq_n         = 3,
8668 @@ -251,16 +203,15 @@
8669
8670  static struct resource orion5x_i2c_resources[] = {
8671         {
8672 -               .name   = "i2c base",
8673 -               .start  = I2C_PHYS_BASE,
8674 -               .end    = I2C_PHYS_BASE + 0x20 -1,
8675 -               .flags  = IORESOURCE_MEM,
8676 -       },
8677 -       {
8678 -               .name   = "i2c irq",
8679 -               .start  = IRQ_ORION5X_I2C,
8680 -               .end    = IRQ_ORION5X_I2C,
8681 -               .flags  = IORESOURCE_IRQ,
8682 +               .name   = "i2c base",
8683 +               .start  = I2C_PHYS_BASE,
8684 +               .end    = I2C_PHYS_BASE + 0x1f,
8685 +               .flags  = IORESOURCE_MEM,
8686 +       }, {
8687 +               .name   = "i2c irq",
8688 +               .start  = IRQ_ORION5X_I2C,
8689 +               .end    = IRQ_ORION5X_I2C,
8690 +               .flags  = IORESOURCE_IRQ,
8691         },
8692  };
8693
8694 @@ -270,36 +221,41 @@
8695         .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
8696         .resource       = orion5x_i2c_resources,
8697         .dev            = {
8698 -               .platform_data = &orion5x_i2c_pdata,
8699 +               .platform_data  = &orion5x_i2c_pdata,
8700         },
8701  };
8702
8703 +void __init orion5x_i2c_init(void)
8704 +{
8705 +       platform_device_register(&orion5x_i2c);
8706 +}
8707 +
8708 +
8709  /*****************************************************************************
8710 - * Sata port
8711 + * SATA
8712   ****************************************************************************/
8713  static struct resource orion5x_sata_resources[] = {
8714 -        {
8715 -                .name   = "sata base",
8716 -                .start  = ORION5X_SATA_PHYS_BASE,
8717 -                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
8718 -                .flags  = IORESOURCE_MEM,
8719 -        },
8720         {
8721 -                .name   = "sata irq",
8722 -                .start  = IRQ_ORION5X_SATA,
8723 -                .end    = IRQ_ORION5X_SATA,
8724 -                .flags  = IORESOURCE_IRQ,
8725 -        },
8726 +               .name   = "sata base",
8727 +               .start  = ORION5X_SATA_PHYS_BASE,
8728 +               .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
8729 +               .flags  = IORESOURCE_MEM,
8730 +       }, {
8731 +               .name   = "sata irq",
8732 +               .start  = IRQ_ORION5X_SATA,
8733 +               .end    = IRQ_ORION5X_SATA,
8734 +               .flags  = IORESOURCE_IRQ,
8735 +       },
8736  };
8737
8738  static struct platform_device orion5x_sata = {
8739 -       .name           = "sata_mv",
8740 -       .id             = 0,
8741 +       .name           = "sata_mv",
8742 +       .id             = 0,
8743         .dev            = {
8744                 .coherent_dma_mask      = 0xffffffff,
8745         },
8746 -       .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
8747 -       .resource       = orion5x_sata_resources,
8748 +       .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
8749 +       .resource       = orion5x_sata_resources,
8750  };
8751
8752  void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
8753 @@ -309,23 +265,111 @@
8754         platform_device_register(&orion5x_sata);
8755  }
8756
8757 +
8758  /*****************************************************************************
8759 - * Time handling
8760 + * UART0
8761 + ****************************************************************************/
8762 +static struct plat_serial8250_port orion5x_uart0_data[] = {
8763 +       {
8764 +               .mapbase        = UART0_PHYS_BASE,
8765 +               .membase        = (char *)UART0_VIRT_BASE,
8766 +               .irq            = IRQ_ORION5X_UART0,
8767 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
8768 +               .iotype         = UPIO_MEM,
8769 +               .regshift       = 2,
8770 +               .uartclk        = ORION5X_TCLK,
8771 +       }, {
8772 +       },
8773 +};
8774 +
8775 +static struct resource orion5x_uart0_resources[] = {
8776 +       {
8777 +               .start          = UART0_PHYS_BASE,
8778 +               .end            = UART0_PHYS_BASE + 0xff,
8779 +               .flags          = IORESOURCE_MEM,
8780 +       }, {
8781 +               .start          = IRQ_ORION5X_UART0,
8782 +               .end            = IRQ_ORION5X_UART0,
8783 +               .flags          = IORESOURCE_IRQ,
8784 +       },
8785 +};
8786 +
8787 +static struct platform_device orion5x_uart0 = {
8788 +       .name                   = "serial8250",
8789 +       .id                     = PLAT8250_DEV_PLATFORM,
8790 +       .dev                    = {
8791 +               .platform_data  = orion5x_uart0_data,
8792 +       },
8793 +       .resource               = orion5x_uart0_resources,
8794 +       .num_resources          = ARRAY_SIZE(orion5x_uart0_resources),
8795 +};
8796 +
8797 +void __init orion5x_uart0_init(void)
8798 +{
8799 +       platform_device_register(&orion5x_uart0);
8800 +}
8801 +
8802 +
8803 +/*****************************************************************************
8804 + * UART1
8805   ****************************************************************************/
8806 +static struct plat_serial8250_port orion5x_uart1_data[] = {
8807 +       {
8808 +               .mapbase        = UART1_PHYS_BASE,
8809 +               .membase        = (char *)UART1_VIRT_BASE,
8810 +               .irq            = IRQ_ORION5X_UART1,
8811 +               .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
8812 +               .iotype         = UPIO_MEM,
8813 +               .regshift       = 2,
8814 +               .uartclk        = ORION5X_TCLK,
8815 +       }, {
8816 +       },
8817 +};
8818 +
8819 +static struct resource orion5x_uart1_resources[] = {
8820 +       {
8821 +               .start          = UART1_PHYS_BASE,
8822 +               .end            = UART1_PHYS_BASE + 0xff,
8823 +               .flags          = IORESOURCE_MEM,
8824 +       }, {
8825 +               .start          = IRQ_ORION5X_UART1,
8826 +               .end            = IRQ_ORION5X_UART1,
8827 +               .flags          = IORESOURCE_IRQ,
8828 +       },
8829 +};
8830 +
8831 +static struct platform_device orion5x_uart1 = {
8832 +       .name                   = "serial8250",
8833 +       .id                     = PLAT8250_DEV_PLATFORM1,
8834 +       .dev                    = {
8835 +               .platform_data  = orion5x_uart1_data,
8836 +       },
8837 +       .resource               = orion5x_uart1_resources,
8838 +       .num_resources          = ARRAY_SIZE(orion5x_uart1_resources),
8839 +};
8840 +
8841 +void __init orion5x_uart1_init(void)
8842 +{
8843 +       platform_device_register(&orion5x_uart1);
8844 +}
8845 +
8846
8847 +/*****************************************************************************
8848 + * Time handling
8849 + ****************************************************************************/
8850  static void orion5x_timer_init(void)
8851  {
8852         orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
8853  }
8854
8855  struct sys_timer orion5x_timer = {
8856 -        .init = orion5x_timer_init,
8857 +       .init = orion5x_timer_init,
8858  };
8859
8860 +
8861  /*****************************************************************************
8862   * General
8863   ****************************************************************************/
8864 -
8865  /*
8866   * Identify device ID and rev from PCIe configuration header space '0'.
8867   */
8868 @@ -350,8 +394,10 @@
8869         } else if (*dev == MV88F5181_DEV_ID) {
8870                 if (*rev == MV88F5181_REV_B1) {
8871                         *dev_name = "MV88F5181-Rev-B1";
8872 +               } else if (*rev == MV88F5181L_REV_A1) {
8873 +                       *dev_name = "MV88F5181L-Rev-A1";
8874                 } else {
8875 -                       *dev_name = "MV88F5181-Rev-Unsupported";
8876 +                       *dev_name = "MV88F5181(L)-Rev-Unsupported";
8877                 }
8878         } else {
8879                 *dev_name = "Device-Unknown";
8880 @@ -370,15 +416,6 @@
8881          * Setup Orion address map
8882          */
8883         orion5x_setup_cpu_mbus_bridge();
8884 -
8885 -       /*
8886 -        * Register devices.
8887 -        */
8888 -       platform_device_register(&orion5x_uart);
8889 -       platform_device_register(&orion5x_ehci0);
8890 -       if (dev == MV88F5182_DEV_ID)
8891 -               platform_device_register(&orion5x_ehci1);
8892 -       platform_device_register(&orion5x_i2c);
8893  }
8894
8895  /*
8896 --- a/arch/arm/mach-orion5x/common.h
8897 +++ b/arch/arm/mach-orion5x/common.h
8898 @@ -1,10 +1,12 @@
8899  #ifndef __ARCH_ORION5X_COMMON_H
8900  #define __ARCH_ORION5X_COMMON_H
8901
8902 +struct mv643xx_eth_platform_data;
8903 +struct mv_sata_platform_data;
8904 +
8905  /*
8906   * Basic Orion init functions used early by machine-setup.
8907   */
8908 -
8909  void orion5x_map_io(void);
8910  void orion5x_init_irq(void);
8911  void orion5x_init(void);
8912 @@ -23,13 +25,19 @@
8913  void orion5x_setup_dev2_win(u32 base, u32 size);
8914  void orion5x_setup_pcie_wa_win(u32 base, u32 size);
8915
8916 +void orion5x_ehci0_init(void);
8917 +void orion5x_ehci1_init(void);
8918 +void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
8919 +void orion5x_i2c_init(void);
8920 +void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
8921 +void orion5x_uart0_init(void);
8922 +void orion5x_uart1_init(void);
8923 +
8924  /*
8925 - * Shared code used internally by other Orion core functions.
8926 - * (/mach-orion/pci.c)
8927 + * PCIe/PCI functions.
8928   */
8929 -
8930 -struct pci_sys_data;
8931  struct pci_bus;
8932 +struct pci_sys_data;
8933
8934  void orion5x_pcie_id(u32 *dev, u32 *rev);
8935  int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
8936 @@ -40,26 +48,9 @@
8937   * Valid GPIO pins according to MPP setup, used by machine-setup.
8938   * (/mach-orion/gpio.c).
8939   */
8940 -
8941 -void orion5x_gpio_set_valid_pins(u32 pins);
8942 +void orion5x_gpio_set_valid(unsigned pin, int valid);
8943  void gpio_display(void);       /* debug */
8944
8945 -/*
8946 - * Pull in Orion Ethernet platform_data, used by machine-setup
8947 - */
8948 -
8949 -struct mv643xx_eth_platform_data;
8950 -
8951 -void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
8952 -
8953 -/*
8954 - * Orion Sata platform_data, used by machine-setup
8955 - */
8956 -
8957 -struct mv_sata_platform_data;
8958 -
8959 -void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
8960 -
8961  struct machine_desc;
8962  struct meminfo;
8963  struct tag;
8964 --- a/arch/arm/mach-orion5x/db88f5281-setup.c
8965 +++ b/arch/arm/mach-orion5x/db88f5281-setup.c
8966 @@ -27,6 +27,7 @@
8967  #include <asm/arch/orion5x.h>
8968  #include <asm/plat-orion/orion_nand.h>
8969  #include "common.h"
8970 +#include "mpp.h"
8971
8972  /*****************************************************************************
8973   * DB-88F5281 on board devices
8974 @@ -86,7 +87,7 @@
8975         .name           = "physmap-flash",
8976         .id             = 0,
8977         .dev            = {
8978 -               .platform_data = &db88f5281_boot_flash_data,
8979 +               .platform_data  = &db88f5281_boot_flash_data,
8980         },
8981         .num_resources  = 1,
8982         .resource       = &db88f5281_boot_flash_resource,
8983 @@ -110,7 +111,7 @@
8984         .name           = "physmap-flash",
8985         .id             = 1,
8986         .dev            = {
8987 -               .platform_data = &db88f5281_nor_flash_data,
8988 +               .platform_data  = &db88f5281_nor_flash_data,
8989         },
8990         .num_resources  = 1,
8991         .resource       = &db88f5281_nor_flash_resource,
8992 @@ -125,18 +126,15 @@
8993                 .name = "kernel",
8994                 .offset = 0,
8995                 .size = SZ_2M,
8996 -       },
8997 -       {
8998 +       }, {
8999                 .name = "root",
9000                 .offset = SZ_2M,
9001                 .size = (SZ_16M - SZ_2M),
9002 -       },
9003 -       {
9004 +       }, {
9005                 .name = "user",
9006                 .offset = SZ_16M,
9007                 .size = SZ_8M,
9008 -       },
9009 -       {
9010 +       }, {
9011                 .name = "recovery",
9012                 .offset = (SZ_16M + SZ_8M),
9013                 .size = SZ_8M,
9014 @@ -288,7 +286,6 @@
9015   ****************************************************************************/
9016  static struct mv643xx_eth_platform_data db88f5281_eth_data = {
9017         .phy_addr       = 8,
9018 -       .force_phy_addr = 1,
9019  };
9020
9021  /*****************************************************************************
9022 @@ -301,11 +298,28 @@
9023  /*****************************************************************************
9024   * General Setup
9025   ****************************************************************************/
9026 -
9027 -static struct platform_device *db88f5281_devs[] __initdata = {
9028 -       &db88f5281_boot_flash,
9029 -       &db88f5281_nor_flash,
9030 -       &db88f5281_nand_flash,
9031 +static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
9032 +       {  0, MPP_GPIO },               /* USB Over Current */
9033 +       {  1, MPP_GPIO },               /* USB Vbat input */
9034 +       {  2, MPP_PCI_ARB },            /* PCI_REQn[2] */
9035 +       {  3, MPP_PCI_ARB },            /* PCI_GNTn[2] */
9036 +       {  4, MPP_PCI_ARB },            /* PCI_REQn[3] */
9037 +       {  5, MPP_PCI_ARB },            /* PCI_GNTn[3] */
9038 +       {  6, MPP_GPIO },               /* JP0, CON17.2 */
9039 +       {  7, MPP_GPIO },               /* JP1, CON17.1 */
9040 +       {  8, MPP_GPIO },               /* JP2, CON11.2 */
9041 +       {  9, MPP_GPIO },               /* JP3, CON11.3 */
9042 +       { 10, MPP_GPIO },               /* RTC int */
9043 +       { 11, MPP_GPIO },               /* Baud Rate Generator */
9044 +       { 12, MPP_GPIO },               /* PCI int 1 */
9045 +       { 13, MPP_GPIO },               /* PCI int 2 */
9046 +       { 14, MPP_NAND },               /* NAND_REn[2] */
9047 +       { 15, MPP_NAND },               /* NAND_WEn[2] */
9048 +       { 16, MPP_UART },               /* UART1_RX */
9049 +       { 17, MPP_UART },               /* UART1_TX */
9050 +       { 18, MPP_UART },               /* UART1_CTSn */
9051 +       { 19, MPP_UART },               /* UART1_RTSn */
9052 +       { -1 },
9053  };
9054
9055  static void __init db88f5281_init(void)
9056 @@ -315,39 +329,31 @@
9057          */
9058         orion5x_init();
9059
9060 +       orion5x_mpp_conf(db88f5281_mpp_modes);
9061 +       writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
9062 +
9063         /*
9064 -        * Setup the CPU address decode windows for our on-board devices
9065 +        * Configure peripherals.
9066          */
9067 +       orion5x_ehci0_init();
9068 +       orion5x_eth_init(&db88f5281_eth_data);
9069 +       orion5x_i2c_init();
9070 +       orion5x_uart0_init();
9071 +       orion5x_uart1_init();
9072 +
9073         orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
9074                                 DB88F5281_NOR_BOOT_SIZE);
9075 +       platform_device_register(&db88f5281_boot_flash);
9076 +
9077         orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
9078 -       orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
9079 -       orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
9080
9081 -       /*
9082 -        * Setup Multiplexing Pins:
9083 -        * MPP0: GPIO (USB Over Current)        MPP1: GPIO (USB Vbat input)
9084 -        * MPP2: PCI_REQn[2]                    MPP3: PCI_GNTn[2]
9085 -        * MPP4: PCI_REQn[3]                    MPP5: PCI_GNTn[3]
9086 -        * MPP6: GPIO (JP0, CON17.2)            MPP7: GPIO (JP1, CON17.1)
9087 -        * MPP8: GPIO (JP2, CON11.2)            MPP9: GPIO (JP3, CON11.3)
9088 -        * MPP10: GPIO (RTC int)                MPP11: GPIO (Baud Rate Generator)
9089 -        * MPP12: GPIO (PCI int 1)              MPP13: GPIO (PCI int 2)
9090 -        * MPP14: NAND_REn[2]                   MPP15: NAND_WEn[2]
9091 -        * MPP16: UART1_RX                      MPP17: UART1_TX
9092 -        * MPP18: UART1_CTS                     MPP19: UART1_RTS
9093 -        * MPP-DEV: DEV_D[16:31]
9094 -        */
9095 -       orion5x_write(MPP_0_7_CTRL, 0x00222203);
9096 -       orion5x_write(MPP_8_15_CTRL, 0x44000000);
9097 -       orion5x_write(MPP_16_19_CTRL, 0);
9098 -       orion5x_write(MPP_DEV_CTRL, 0);
9099 +       orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
9100 +       platform_device_register(&db88f5281_nor_flash);
9101
9102 -       orion5x_gpio_set_valid_pins(0x00003fc3);
9103 +       orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
9104 +       platform_device_register(&db88f5281_nand_flash);
9105
9106 -       platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
9107         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
9108 -       orion5x_eth_init(&db88f5281_eth_data);
9109  }
9110
9111  MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
9112 --- a/arch/arm/mach-orion5x/dns323-setup.c
9113 +++ b/arch/arm/mach-orion5x/dns323-setup.c
9114 @@ -27,6 +27,7 @@
9115  #include <asm/mach/pci.h>
9116  #include <asm/arch/orion5x.h>
9117  #include "common.h"
9118 +#include "mpp.h"
9119
9120  #define DNS323_GPIO_LED_RIGHT_AMBER    1
9121  #define DNS323_GPIO_LED_LEFT_AMBER     2
9122 @@ -52,8 +53,6 @@
9123         if (irq != -1)
9124                 return irq;
9125
9126 -       pr_err("%s: requested mapping for unknown device\n", __func__);
9127 -
9128         return -1;
9129  }
9130
9131 @@ -81,7 +80,6 @@
9132
9133  static struct mv643xx_eth_platform_data dns323_eth_data = {
9134         .phy_addr = 8,
9135 -       .force_phy_addr = 1,
9136  };
9137
9138  /****************************************************************************
9139 @@ -119,7 +117,7 @@
9140                 .name   = "u-boot",
9141                 .size   = 0x00030000,
9142                 .offset = 0x007d0000,
9143 -       }
9144 +       },
9145  };
9146
9147  static struct physmap_flash_data dns323_nor_flash_data = {
9148 @@ -137,7 +135,9 @@
9149  static struct platform_device dns323_nor_flash = {
9150         .name           = "physmap-flash",
9151         .id             = 0,
9152 -       .dev            = { .platform_data = &dns323_nor_flash_data, },
9153 +       .dev            = {
9154 +               .platform_data  = &dns323_nor_flash_data,
9155 +       },
9156         .resource       = &dns323_nor_flash_resource,
9157         .num_resources  = 1,
9158  };
9159 @@ -170,7 +170,9 @@
9160  static struct platform_device dns323_gpio_leds = {
9161         .name           = "leds-gpio",
9162         .id             = -1,
9163 -       .dev            = { .platform_data = &dns323_led_data, },
9164 +       .dev            = {
9165 +               .platform_data  = &dns323_led_data,
9166 +       },
9167  };
9168
9169  /****************************************************************************
9170 @@ -183,35 +185,53 @@
9171                 .gpio           = DNS323_GPIO_KEY_RESET,
9172                 .desc           = "Reset Button",
9173                 .active_low     = 1,
9174 -       },
9175 -       {
9176 +       }, {
9177                 .code           = KEY_POWER,
9178                 .gpio           = DNS323_GPIO_KEY_POWER,
9179                 .desc           = "Power Button",
9180                 .active_low     = 1,
9181 -       }
9182 +       },
9183  };
9184
9185  static struct gpio_keys_platform_data dns323_button_data = {
9186         .buttons        = dns323_buttons,
9187 -       .nbuttons       = ARRAY_SIZE(dns323_buttons),
9188 +       .nbuttons       = ARRAY_SIZE(dns323_buttons),
9189  };
9190
9191  static struct platform_device dns323_button_device = {
9192         .name           = "gpio-keys",
9193         .id             = -1,
9194         .num_resources  = 0,
9195 -       .dev            = { .platform_data  = &dns323_button_data, },
9196 +       .dev            = {
9197 +               .platform_data  = &dns323_button_data,
9198 +       },
9199  };
9200
9201  /****************************************************************************
9202   * General Setup
9203   */
9204 -
9205 -static struct platform_device *dns323_plat_devices[] __initdata = {
9206 -       &dns323_nor_flash,
9207 -       &dns323_gpio_leds,
9208 -       &dns323_button_device,
9209 +static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
9210 +       {  0, MPP_PCIE_RST_OUTn },
9211 +       {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
9212 +       {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
9213 +       {  3, MPP_UNUSED },
9214 +       {  4, MPP_GPIO },               /* power button LED */
9215 +       {  5, MPP_GPIO },               /* power button LED */
9216 +       {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
9217 +       {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
9218 +       {  8, MPP_GPIO },               /* triggers power off */
9219 +       {  9, MPP_GPIO },               /* power button switch */
9220 +       { 10, MPP_GPIO },               /* reset button switch */
9221 +       { 11, MPP_UNUSED },
9222 +       { 12, MPP_UNUSED },
9223 +       { 13, MPP_UNUSED },
9224 +       { 14, MPP_UNUSED },
9225 +       { 15, MPP_UNUSED },
9226 +       { 16, MPP_UNUSED },
9227 +       { 17, MPP_UNUSED },
9228 +       { 18, MPP_UNUSED },
9229 +       { 19, MPP_UNUSED },
9230 +       { -1 },
9231  };
9232
9233  /*
9234 @@ -225,17 +245,15 @@
9235  static struct i2c_board_info __initdata dns323_i2c_devices[] = {
9236         {
9237                 I2C_BOARD_INFO("g760a", 0x3e),
9238 -       },
9239  #if 0
9240         /* this entry requires the new-style driver model lm75 driver,
9241          * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
9242 -       {
9243 +       }, {
9244                 I2C_BOARD_INFO("g751", 0x48),
9245 -       },
9246  #endif
9247 -       {
9248 +       }, {
9249                 I2C_BOARD_INFO("m41t80", 0x68),
9250 -       }
9251 +       },
9252  };
9253
9254  /* DNS-323 specific power off method */
9255 @@ -250,62 +268,35 @@
9256         /* Setup basic Orion functions. Need to be called early. */
9257         orion5x_init();
9258
9259 +       orion5x_mpp_conf(dns323_mpp_modes);
9260 +       writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
9261 +
9262 +       /*
9263 +        * Configure peripherals.
9264 +        */
9265 +       orion5x_ehci0_init();
9266 +       orion5x_eth_init(&dns323_eth_data);
9267 +       orion5x_i2c_init();
9268 +       orion5x_uart0_init();
9269 +
9270         /* setup flash mapping
9271          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
9272          */
9273         orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
9274 +       platform_device_register(&dns323_nor_flash);
9275
9276 -       /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe
9277 -        *
9278 -        * Open a special address decode windows for the PCIe WA.
9279 -        */
9280 -       orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
9281 -                               ORION5X_PCIE_WA_SIZE);
9282 -
9283 -       /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
9284 -       orion5x_write(MPP_0_7_CTRL, 0);
9285 -       orion5x_write(MPP_8_15_CTRL, 0);
9286 -       orion5x_write(MPP_16_19_CTRL, 0);
9287 -       orion5x_write(MPP_DEV_CTRL, 0);
9288 -
9289 -       /* Define used GPIO pins
9290 -
9291 -         GPIO Map:
9292 -
9293 -         |  0 |     | PEX_RST_OUT (not controlled by GPIO)
9294 -         |  1 | Out | right amber LED (= sata ch0 LED)  (low-active)
9295 -         |  2 | Out | left  amber LED (= sata ch1 LED)  (low-active)
9296 -         |  3 | Out | //unknown//
9297 -         |  4 | Out | power button LED (low-active, together with pin #5)
9298 -         |  5 | Out | power button LED (low-active, together with pin #4)
9299 -         |  6 | In  | GMT G751-2f overtemp. shutdown signal (low-active)
9300 -         |  7 | In  | M41T80 nIRQ/OUT/SQW signal
9301 -         |  8 | Out | triggers power off (high-active)
9302 -         |  9 | In  | power button switch (low-active)
9303 -         | 10 | In  | reset button switch (low-active)
9304 -         | 11 | Out | //unknown//
9305 -         | 12 | Out | //unknown//
9306 -         | 13 | Out | //unknown//
9307 -         | 14 | Out | //unknown//
9308 -         | 15 | Out | //unknown//
9309 -       */
9310 -       orion5x_gpio_set_valid_pins(0x07f6);
9311 -
9312 -       /* register dns323 specific power-off method */
9313 -       if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
9314 -           || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
9315 -               pr_err("DNS323: failed to setup power-off GPIO\n");
9316 -
9317 -       pm_power_off = dns323_power_off;
9318 +       platform_device_register(&dns323_gpio_leds);
9319
9320 -       /* register flash and other platform devices */
9321 -       platform_add_devices(dns323_plat_devices,
9322 -                            ARRAY_SIZE(dns323_plat_devices));
9323 +       platform_device_register(&dns323_button_device);
9324
9325         i2c_register_board_info(0, dns323_i2c_devices,
9326                                 ARRAY_SIZE(dns323_i2c_devices));
9327
9328 -       orion5x_eth_init(&dns323_eth_data);
9329 +       /* register dns323 specific power-off method */
9330 +       if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
9331 +           gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
9332 +               pr_err("DNS323: failed to setup power-off GPIO\n");
9333 +       pm_power_off = dns323_power_off;
9334  }
9335
9336  /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
9337 --- a/arch/arm/mach-orion5x/gpio.c
9338 +++ b/arch/arm/mach-orion5x/gpio.c
9339 @@ -24,9 +24,12 @@
9340  static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
9341  static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
9342
9343 -void __init orion5x_gpio_set_valid_pins(u32 pins)
9344 +void __init orion5x_gpio_set_valid(unsigned pin, int valid)
9345  {
9346 -       gpio_valid[0] = pins;
9347 +       if (valid)
9348 +               __set_bit(pin, gpio_valid);
9349 +       else
9350 +               __clear_bit(pin, gpio_valid);
9351  }
9352
9353  /*
9354 @@ -93,10 +96,10 @@
9355  {
9356         int val, mask = 1 << pin;
9357
9358 -       if (orion5x_read(GPIO_IO_CONF) & mask)
9359 -               val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
9360 +       if (readl(GPIO_IO_CONF) & mask)
9361 +               val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL);
9362         else
9363 -               val = orion5x_read(GPIO_OUT);
9364 +               val = readl(GPIO_OUT);
9365
9366         return val & mask;
9367  }
9368 @@ -188,39 +191,39 @@
9369                         printk("GPIO, free\n");
9370                 } else {
9371                         printk("GPIO, used by %s, ", gpio_label[i]);
9372 -                       if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
9373 +                       if (readl(GPIO_IO_CONF) & (1 << i)) {
9374                                 printk("input, active %s, level %s, edge %s\n",
9375 -                               ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
9376 -                               ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
9377 -                               ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
9378 +                               ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
9379 +                               ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
9380 +                               ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
9381                         } else {
9382 -                               printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
9383 +                               printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1);
9384                         }
9385                 }
9386         }
9387
9388         printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
9389 -                               MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
9390 +                               MPP_0_7_CTRL, readl(MPP_0_7_CTRL));
9391         printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
9392 -                               MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
9393 +                               MPP_8_15_CTRL, readl(MPP_8_15_CTRL));
9394         printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
9395 -                               MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
9396 +                               MPP_16_19_CTRL, readl(MPP_16_19_CTRL));
9397         printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
9398 -                               MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
9399 +                               MPP_DEV_CTRL, readl(MPP_DEV_CTRL));
9400         printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
9401 -                               GPIO_OUT, orion5x_read(GPIO_OUT));
9402 +                               GPIO_OUT, readl(GPIO_OUT));
9403         printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
9404 -                               GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
9405 +                               GPIO_IO_CONF, readl(GPIO_IO_CONF));
9406         printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
9407 -                               GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
9408 +                               GPIO_BLINK_EN, readl(GPIO_BLINK_EN));
9409         printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
9410 -                               GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
9411 +                               GPIO_IN_POL, readl(GPIO_IN_POL));
9412         printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
9413 -                               GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
9414 +                               GPIO_DATA_IN, readl(GPIO_DATA_IN));
9415         printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
9416 -                               GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
9417 +                               GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK));
9418         printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
9419 -                               GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
9420 +                               GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE));
9421         printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
9422 -                               GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
9423 +                               GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK));
9424  }
9425 --- a/arch/arm/mach-orion5x/irq.c
9426 +++ b/arch/arm/mach-orion5x/irq.c
9427 @@ -82,7 +82,7 @@
9428         int pin = irq_to_gpio(irq);
9429         struct irq_desc *desc;
9430
9431 -       if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
9432 +       if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
9433                 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
9434                                 "(irq %d, pin %d).\n", irq, pin);
9435                 return -EINVAL;
9436 @@ -117,7 +117,7 @@
9437                 /*
9438                  * set initial polarity based on current input level
9439                  */
9440 -               if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
9441 +               if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
9442                     & (1 << pin))
9443                         orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
9444                 else
9445 @@ -149,8 +149,8 @@
9446
9447         BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
9448         offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
9449 -       cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
9450 -               (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
9451 +       cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
9452 +               (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
9453
9454         for (pin = offs; pin < offs + 8; pin++) {
9455                 if (cause & (1 << pin)) {
9456 @@ -158,9 +158,9 @@
9457                         desc = irq_desc + irq;
9458                         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
9459                                 /* Swap polarity (race with GPIO line) */
9460 -                               u32 polarity = orion5x_read(GPIO_IN_POL);
9461 +                               u32 polarity = readl(GPIO_IN_POL);
9462                                 polarity ^= 1 << pin;
9463 -                               orion5x_write(GPIO_IN_POL, polarity);
9464 +                               writel(polarity, GPIO_IN_POL);
9465                         }
9466                         desc_handle_irq(irq, desc);
9467                 }
9468 @@ -175,9 +175,9 @@
9469         /*
9470          * Mask and clear GPIO IRQ interrupts
9471          */
9472 -       orion5x_write(GPIO_LEVEL_MASK, 0x0);
9473 -       orion5x_write(GPIO_EDGE_MASK, 0x0);
9474 -       orion5x_write(GPIO_EDGE_CAUSE, 0x0);
9475 +       writel(0x0, GPIO_LEVEL_MASK);
9476 +       writel(0x0, GPIO_EDGE_MASK);
9477 +       writel(0x0, GPIO_EDGE_CAUSE);
9478
9479         /*
9480          * Register chained level handlers for GPIO IRQs by default.
9481 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
9482 +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
9483 @@ -13,10 +13,12 @@
9484  #include <linux/platform_device.h>
9485  #include <linux/pci.h>
9486  #include <linux/irq.h>
9487 +#include <linux/delay.h>
9488  #include <linux/mtd/physmap.h>
9489  #include <linux/mtd/nand.h>
9490  #include <linux/mv643xx_eth.h>
9491  #include <linux/i2c.h>
9492 +#include <linux/serial_reg.h>
9493  #include <linux/ata_platform.h>
9494  #include <asm/mach-types.h>
9495  #include <asm/gpio.h>
9496 @@ -25,6 +27,7 @@
9497  #include <asm/arch/orion5x.h>
9498  #include <asm/plat-orion/orion_nand.h>
9499  #include "common.h"
9500 +#include "mpp.h"
9501
9502  /*****************************************************************************
9503   * KUROBOX-PRO Info
9504 @@ -53,13 +56,11 @@
9505                 .name   = "uImage",
9506                 .offset = 0,
9507                 .size   = SZ_4M,
9508 -       },
9509 -       {
9510 +       }, {
9511                 .name   = "rootfs",
9512                 .offset = SZ_4M,
9513                 .size   = SZ_64M,
9514 -       },
9515 -       {
9516 +       }, {
9517                 .name   = "extra",
9518                 .offset = SZ_4M + SZ_64M,
9519                 .size   = SZ_256M - (SZ_4M + SZ_64M),
9520 @@ -132,8 +133,6 @@
9521         /*
9522          * PCI isn't used on the Kuro
9523          */
9524 -       printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
9525 -
9526         return -1;
9527  }
9528
9529 @@ -161,7 +160,6 @@
9530
9531  static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
9532         .phy_addr       = 8,
9533 -       .force_phy_addr = 1,
9534  };
9535
9536  /*****************************************************************************
9537 @@ -175,12 +173,169 @@
9538   * SATA
9539   ****************************************************************************/
9540  static struct mv_sata_platform_data kurobox_pro_sata_data = {
9541 -       .n_ports        = 2,
9542 +       .n_ports        = 2,
9543  };
9544
9545  /*****************************************************************************
9546 + * Kurobox Pro specific power off method via UART1-attached microcontroller
9547 + ****************************************************************************/
9548 +
9549 +#define UART1_REG(x)   (UART1_VIRT_BASE + ((UART_##x) << 2))
9550 +
9551 +static int kurobox_pro_miconread(unsigned char *buf, int count)
9552 +{
9553 +       int i;
9554 +       int timeout;
9555 +
9556 +       for (i = 0; i < count; i++) {
9557 +               timeout = 10;
9558 +
9559 +               while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
9560 +                       if (--timeout == 0)
9561 +                               break;
9562 +                       udelay(1000);
9563 +               }
9564 +
9565 +               if (timeout == 0)
9566 +                       break;
9567 +               buf[i] = readl(UART1_REG(RX));
9568 +       }
9569 +
9570 +       /* return read bytes */
9571 +       return i;
9572 +}
9573 +
9574 +static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
9575 +{
9576 +       int i = 0;
9577 +
9578 +       while (count--) {
9579 +               while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
9580 +                       barrier();
9581 +               writel(buf[i++], UART1_REG(TX));
9582 +       }
9583 +
9584 +       return 0;
9585 +}
9586 +
9587 +static int kurobox_pro_miconsend(const unsigned char *data, int count)
9588 +{
9589 +       int i;
9590 +       unsigned char checksum = 0;
9591 +       unsigned char recv_buf[40];
9592 +       unsigned char send_buf[40];
9593 +       unsigned char correct_ack[3];
9594 +       int retry = 2;
9595 +
9596 +       /* Generate checksum */
9597 +       for (i = 0; i < count; i++)
9598 +               checksum -=  data[i];
9599 +
9600 +       do {
9601 +               /* Send data */
9602 +               kurobox_pro_miconwrite(data, count);
9603 +
9604 +               /* send checksum */
9605 +               kurobox_pro_miconwrite(&checksum, 1);
9606 +
9607 +               if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
9608 +                       printk(KERN_ERR ">%s: receive failed.\n", __func__);
9609 +
9610 +                       /* send preamble to clear the receive buffer */
9611 +                       memset(&send_buf, 0xff, sizeof(send_buf));
9612 +                       kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
9613 +
9614 +                       /* make dummy reads */
9615 +                       mdelay(100);
9616 +                       kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
9617 +               } else {
9618 +                       /* Generate expected ack */
9619 +                       correct_ack[0] = 0x01;
9620 +                       correct_ack[1] = data[1];
9621 +                       correct_ack[2] = 0x00;
9622 +
9623 +                       /* checksum Check */
9624 +                       if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
9625 +                            recv_buf[3]) & 0xFF) {
9626 +                               printk(KERN_ERR ">%s: Checksum Error : "
9627 +                                       "Received data[%02x, %02x, %02x, %02x]"
9628 +                                       "\n", __func__, recv_buf[0],
9629 +                                       recv_buf[1], recv_buf[2], recv_buf[3]);
9630 +                       } else {
9631 +                               /* Check Received Data */
9632 +                               if (correct_ack[0] == recv_buf[0] &&
9633 +                                   correct_ack[1] == recv_buf[1] &&
9634 +                                   correct_ack[2] == recv_buf[2]) {
9635 +                                       /* Interval for next command */
9636 +                                       mdelay(10);
9637 +
9638 +                                       /* Receive ACK */
9639 +                                       return 0;
9640 +                               }
9641 +                       }
9642 +                       /* Received NAK or illegal Data */
9643 +                       printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
9644 +                                       "Received\n", __func__);
9645 +               }
9646 +       } while (retry--);
9647 +
9648 +       /* Interval for next command */
9649 +       mdelay(10);
9650 +
9651 +       return -1;
9652 +}
9653 +
9654 +static void kurobox_pro_power_off(void)
9655 +{
9656 +       const unsigned char watchdogkill[]      = {0x01, 0x35, 0x00};
9657 +       const unsigned char shutdownwait[]      = {0x00, 0x0c};
9658 +       const unsigned char poweroff[]          = {0x00, 0x06};
9659 +       /* 38400 baud divisor */
9660 +       const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400));
9661 +
9662 +       pr_info("%s: triggering power-off...\n", __func__);
9663 +
9664 +       /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
9665 +       writel(0x83, UART1_REG(LCR));
9666 +       writel(divisor & 0xff, UART1_REG(DLL));
9667 +       writel((divisor >> 8) & 0xff, UART1_REG(DLM));
9668 +       writel(0x1b, UART1_REG(LCR));
9669 +       writel(0x00, UART1_REG(IER));
9670 +       writel(0x07, UART1_REG(FCR));
9671 +       writel(0x00, UART1_REG(MCR));
9672 +
9673 +       /* Send the commands to shutdown the Kurobox Pro */
9674 +       kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
9675 +       kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
9676 +       kurobox_pro_miconsend(poweroff, sizeof(poweroff));
9677 +}
9678 +
9679 +/*****************************************************************************
9680   * General Setup
9681   ****************************************************************************/
9682 +static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
9683 +       {  0, MPP_UNUSED },
9684 +       {  1, MPP_UNUSED },
9685 +       {  2, MPP_GPIO },               /* GPIO Micon */
9686 +       {  3, MPP_GPIO },               /* GPIO Rtc */
9687 +       {  4, MPP_UNUSED },
9688 +       {  5, MPP_UNUSED },
9689 +       {  6, MPP_NAND },               /* NAND Flash REn */
9690 +       {  7, MPP_NAND },               /* NAND Flash WEn */
9691 +       {  8, MPP_UNUSED },
9692 +       {  9, MPP_UNUSED },
9693 +       { 10, MPP_UNUSED },
9694 +       { 11, MPP_UNUSED },
9695 +       { 12, MPP_SATA_LED },           /* SATA 0 presence */
9696 +       { 13, MPP_SATA_LED },           /* SATA 1 presence */
9697 +       { 14, MPP_SATA_LED },           /* SATA 0 active */
9698 +       { 15, MPP_SATA_LED },           /* SATA 1 active */
9699 +       { 16, MPP_UART },               /* UART1 RXD */
9700 +       { 17, MPP_UART },               /* UART1 TXD */
9701 +       { 18, MPP_UART },               /* UART1 CTSn */
9702 +       { 19, MPP_UART },               /* UART1 RTSn */
9703 +       { -1 },
9704 +};
9705
9706  static void __init kurobox_pro_init(void)
9707  {
9708 @@ -189,46 +344,32 @@
9709          */
9710         orion5x_init();
9711
9712 -       /*
9713 -        * Setup the CPU address decode windows for our devices
9714 -        */
9715 -       orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
9716 -                               KUROBOX_PRO_NOR_BOOT_SIZE);
9717 -       orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
9718 +       orion5x_mpp_conf(kurobox_pro_mpp_modes);
9719
9720         /*
9721 -        * Open a special address decode windows for the PCIe WA.
9722 +        * Configure peripherals.
9723          */
9724 -       orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
9725 -                               ORION5X_PCIE_WA_SIZE);
9726 -
9727 -       /*
9728 -        * Setup Multiplexing Pins --
9729 -        * MPP[0-1] Not used
9730 -        * MPP[2] GPIO Micon
9731 -        * MPP[3] GPIO RTC
9732 -        * MPP[4-5] Not used
9733 -        * MPP[6] Nand Flash REn
9734 -        * MPP[7] Nand Flash WEn
9735 -        * MPP[8-11] Not used
9736 -        * MPP[12] SATA 0 presence Indication
9737 -        * MPP[13] SATA 1 presence Indication
9738 -        * MPP[14] SATA 0 active Indication
9739 -        * MPP[15] SATA 1 active indication
9740 -        * MPP[16-19] Not used
9741 -        */
9742 -       orion5x_write(MPP_0_7_CTRL, 0x44220003);
9743 -       orion5x_write(MPP_8_15_CTRL, 0x55550000);
9744 -       orion5x_write(MPP_16_19_CTRL, 0x0);
9745 -
9746 -       orion5x_gpio_set_valid_pins(0x0000000c);
9747 +       orion5x_ehci0_init();
9748 +       orion5x_ehci1_init();
9749 +       orion5x_eth_init(&kurobox_pro_eth_data);
9750 +       orion5x_i2c_init();
9751 +       orion5x_sata_init(&kurobox_pro_sata_data);
9752 +       orion5x_uart0_init();
9753
9754 +       orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
9755 +                                  KUROBOX_PRO_NOR_BOOT_SIZE);
9756         platform_device_register(&kurobox_pro_nor_flash);
9757 -       if (machine_is_kurobox_pro())
9758 +
9759 +       if (machine_is_kurobox_pro()) {
9760 +               orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
9761 +                                      KUROBOX_PRO_NAND_SIZE);
9762                 platform_device_register(&kurobox_pro_nand_flash);
9763 +       }
9764 +
9765         i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
9766 -       orion5x_eth_init(&kurobox_pro_eth_data);
9767 -       orion5x_sata_init(&kurobox_pro_sata_data);
9768 +
9769 +       /* register Kurobox Pro specific power-off method */
9770 +       pm_power_off = kurobox_pro_power_off;
9771  }
9772
9773  #ifdef CONFIG_MACH_KUROBOX_PRO
9774 --- /dev/null
9775 +++ b/arch/arm/mach-orion5x/mpp.c
9776 @@ -0,0 +1,163 @@
9777 +/*
9778 + * arch/arm/mach-orion5x/mpp.c
9779 + *
9780 + * MPP functions for Marvell Orion 5x SoCs
9781 + *
9782 + * This file is licensed under the terms of the GNU General Public
9783 + * License version 2.  This program is licensed "as is" without any
9784 + * warranty of any kind, whether express or implied.
9785 + */
9786 +
9787 +#include <linux/kernel.h>
9788 +#include <linux/init.h>
9789 +#include <linux/mbus.h>
9790 +#include <asm/hardware.h>
9791 +#include <asm/io.h>
9792 +#include "common.h"
9793 +#include "mpp.h"
9794 +
9795 +static int is_5181l(void)
9796 +{
9797 +       u32 dev;
9798 +       u32 rev;
9799 +
9800 +       orion5x_pcie_id(&dev, &rev);
9801 +
9802 +       return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
9803 +}
9804 +
9805 +static int is_5182(void)
9806 +{
9807 +       u32 dev;
9808 +       u32 rev;
9809 +
9810 +       orion5x_pcie_id(&dev, &rev);
9811 +
9812 +       return !!(dev == MV88F5182_DEV_ID);
9813 +}
9814 +
9815 +static int is_5281(void)
9816 +{
9817 +       u32 dev;
9818 +       u32 rev;
9819 +
9820 +       orion5x_pcie_id(&dev, &rev);
9821 +
9822 +       return !!(dev == MV88F5281_DEV_ID);
9823 +}
9824 +
9825 +static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
9826 +{
9827 +       switch (type) {
9828 +       case MPP_UNUSED:
9829 +       case MPP_GPIO:
9830 +               if (mpp == 0)
9831 +                       return 3;
9832 +               if (mpp >= 1 && mpp <= 15)
9833 +                       return 0;
9834 +               if (mpp >= 16 && mpp <= 19) {
9835 +                       if (is_5182())
9836 +                               return 5;
9837 +                       if (type == MPP_UNUSED)
9838 +                               return 0;
9839 +               }
9840 +               return -1;
9841 +
9842 +       case MPP_PCIE_RST_OUTn:
9843 +               if (mpp == 0)
9844 +                       return 0;
9845 +               return -1;
9846 +
9847 +       case MPP_PCI_ARB:
9848 +               if (mpp >= 0 && mpp <= 7)
9849 +                       return 2;
9850 +               return -1;
9851 +
9852 +       case MPP_PCI_PMEn:
9853 +               if (mpp == 2)
9854 +                       return 3;
9855 +               return -1;
9856 +
9857 +       case MPP_GIGE:
9858 +               if (mpp >= 8 && mpp <= 19)
9859 +                       return 1;
9860 +               return -1;
9861 +
9862 +       case MPP_NAND:
9863 +               if (is_5182() || is_5281()) {
9864 +                       if (mpp >= 4 && mpp <= 7)
9865 +                               return 4;
9866 +                       if (mpp >= 12 && mpp <= 17)
9867 +                               return 4;
9868 +               }
9869 +               return -1;
9870 +
9871 +       case MPP_PCI_CLK:
9872 +               if (is_5181l() && mpp >= 6 && mpp <= 7)
9873 +                       return 5;
9874 +               return -1;
9875 +
9876 +       case MPP_SATA_LED:
9877 +               if (is_5182()) {
9878 +                       if (mpp >= 4 && mpp <= 7)
9879 +                               return 5;
9880 +                       if (mpp >= 12 && mpp <= 15)
9881 +                               return 5;
9882 +               }
9883 +               return -1;
9884 +
9885 +       case MPP_UART:
9886 +               if (mpp >= 16 && mpp <= 19)
9887 +                       return 0;
9888 +               return -1;
9889 +       }
9890 +
9891 +       printk(KERN_INFO "unknown MPP type %d\n", type);
9892 +
9893 +       return -1;
9894 +}
9895 +
9896 +void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
9897 +{
9898 +       u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
9899 +       u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
9900 +       u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
9901 +
9902 +       while (mode->mpp >= 0) {
9903 +               u32 *reg;
9904 +               int num_type;
9905 +               int shift;
9906 +
9907 +               if (mode->mpp >= 0 && mode->mpp <= 7)
9908 +                       reg = &mpp_0_7_ctrl;
9909 +               else if (mode->mpp >= 8 && mode->mpp <= 15)
9910 +                       reg = &mpp_8_15_ctrl;
9911 +               else if (mode->mpp >= 16 && mode->mpp <= 19)
9912 +                       reg = &mpp_16_19_ctrl;
9913 +               else {
9914 +                       printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
9915 +                                       "(%d)\n", mode->mpp);
9916 +                       continue;
9917 +               }
9918 +
9919 +               num_type = determine_type_encoding(mode->mpp, mode->type);
9920 +               if (num_type < 0) {
9921 +                       printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
9922 +                                       "combination (%d, %d)\n", mode->mpp,
9923 +                                       mode->type);
9924 +                       continue;
9925 +               }
9926 +
9927 +               shift = (mode->mpp & 7) << 2;
9928 +               *reg &= ~(0xf << shift);
9929 +               *reg |= (num_type & 0xf) << shift;
9930 +
9931 +               orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
9932 +
9933 +               mode++;
9934 +       }
9935 +
9936 +       writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
9937 +       writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
9938 +       writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
9939 +}
9940 --- /dev/null
9941 +++ b/arch/arm/mach-orion5x/mpp.h
9942 @@ -0,0 +1,74 @@
9943 +#ifndef __ARCH_ORION5X_MPP_H
9944 +#define __ARCH_ORION5X_MPP_H
9945 +
9946 +enum orion5x_mpp_type {
9947 +       /*
9948 +        * This MPP is unused.
9949 +        */
9950 +       MPP_UNUSED,
9951 +
9952 +       /*
9953 +        * This MPP pin is used as a generic GPIO pin.  Valid for
9954 +        * MPPs 0-15 and device bus data pins 16-31.  On 5182, also
9955 +        * valid for MPPs 16-19.
9956 +        */
9957 +       MPP_GPIO,
9958 +
9959 +       /*
9960 +        * This MPP is used as PCIe_RST_OUTn pin.  Valid for
9961 +        * MPP 0 only.
9962 +        */
9963 +       MPP_PCIE_RST_OUTn,
9964 +
9965 +       /*
9966 +        * This MPP is used as PCI arbiter pin (REQn/GNTn).
9967 +        * Valid for MPPs 0-7 only.
9968 +        */
9969 +       MPP_PCI_ARB,
9970 +
9971 +       /*
9972 +        * This MPP is used as PCI_PMEn pin.  Valid for MPP 2 only.
9973 +        */
9974 +       MPP_PCI_PMEn,
9975 +
9976 +       /*
9977 +        * This MPP is used as GigE half-duplex (COL, CRS) or GMII
9978 +        * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin.  Valid for
9979 +        * MPPs 8-19 only.
9980 +        */
9981 +       MPP_GIGE,
9982 +
9983 +       /*
9984 +        * This MPP is used as NAND REn/WEn pin.  Valid for MPPs
9985 +        * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
9986 +        */
9987 +       MPP_NAND,
9988 +
9989 +       /*
9990 +        * This MPP is used as a PCI clock output pin.  Valid for
9991 +        * MPPs 6-7 only, and only on the 5181l.
9992 +        */
9993 +       MPP_PCI_CLK,
9994 +
9995 +       /*
9996 +        * This MPP is used as a SATA presence/activity LED.
9997 +        * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
9998 +        */
9999 +       MPP_SATA_LED,
10000 +
10001 +       /*
10002 +        * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
10003 +        * Valid for MPPs 16-19 only.
10004 +        */
10005 +       MPP_UART,
10006 +};
10007 +
10008 +struct orion5x_mpp_mode {
10009 +       int                     mpp;
10010 +       enum orion5x_mpp_type   type;
10011 +};
10012 +
10013 +void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
10014 +
10015 +
10016 +#endif
10017 --- /dev/null
10018 +++ b/arch/arm/mach-orion5x/mss2-setup.c
10019 @@ -0,0 +1,270 @@
10020 +/*
10021 + * Maxtor Shared Storage II Board Setup
10022 + *
10023 + * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
10024 + *
10025 + * This program is free software; you can redistribute it and/or
10026 + * modify it under the terms of the GNU General Public License
10027 + * as published by the Free Software Foundation; either version
10028 + * 2 of the License, or (at your option) any later version.
10029 + */
10030 +
10031 +#include <linux/kernel.h>
10032 +#include <linux/init.h>
10033 +#include <linux/platform_device.h>
10034 +#include <linux/pci.h>
10035 +#include <linux/irq.h>
10036 +#include <linux/mtd/physmap.h>
10037 +#include <linux/mv643xx_eth.h>
10038 +#include <linux/leds.h>
10039 +#include <linux/gpio_keys.h>
10040 +#include <linux/input.h>
10041 +#include <linux/i2c.h>
10042 +#include <linux/ata_platform.h>
10043 +#include <linux/gpio.h>
10044 +#include <asm/mach-types.h>
10045 +#include <asm/mach/arch.h>
10046 +#include <asm/mach/pci.h>
10047 +#include <asm/arch/orion5x.h>
10048 +#include "common.h"
10049 +#include "mpp.h"
10050 +
10051 +#define MSS2_NOR_BOOT_BASE     0xff800000
10052 +#define MSS2_NOR_BOOT_SIZE     SZ_256K
10053 +
10054 +/*****************************************************************************
10055 + * Maxtor Shared Storage II Info
10056 + ****************************************************************************/
10057 +
10058 +/*
10059 + * Maxtor Shared Storage II hardware :
10060 + * - Marvell 88F5182-A2 C500
10061 + * - Marvell 88E1111 Gigabit Ethernet PHY
10062 + * - RTC M41T81 (@0x68) on I2C bus
10063 + * - 256KB NOR flash
10064 + * - 64MB of RAM
10065 + */
10066 +
10067 +/*****************************************************************************
10068 + * 256KB NOR Flash on BOOT Device
10069 + ****************************************************************************/
10070 +
10071 +static struct physmap_flash_data mss2_nor_flash_data = {
10072 +       .width          = 1,
10073 +};
10074 +
10075 +static struct resource mss2_nor_flash_resource = {
10076 +       .flags          = IORESOURCE_MEM,
10077 +       .start          = MSS2_NOR_BOOT_BASE,
10078 +       .end            = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1,
10079 +};
10080 +
10081 +static struct platform_device mss2_nor_flash = {
10082 +       .name           = "physmap-flash",
10083 +       .id             = 0,
10084 +       .dev            = {
10085 +               .platform_data  = &mss2_nor_flash_data,
10086 +       },
10087 +       .resource       = &mss2_nor_flash_resource,
10088 +       .num_resources  = 1,
10089 +};
10090 +
10091 +/****************************************************************************
10092 + * PCI setup
10093 + ****************************************************************************/
10094 +static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
10095 +{
10096 +       int irq;
10097 +
10098 +       /*
10099 +        * Check for devices with hard-wired IRQs.
10100 +        */
10101 +       irq = orion5x_pci_map_irq(dev, slot, pin);
10102 +       if (irq != -1)
10103 +               return irq;
10104 +
10105 +       return -1;
10106 +}
10107 +
10108 +static struct hw_pci mss2_pci __initdata = {
10109 +       .nr_controllers = 2,
10110 +       .swizzle        = pci_std_swizzle,
10111 +       .setup          = orion5x_pci_sys_setup,
10112 +       .scan           = orion5x_pci_sys_scan_bus,
10113 +       .map_irq        = mss2_pci_map_irq,
10114 +};
10115 +
10116 +static int __init mss2_pci_init(void)
10117 +{
10118 +       if (machine_is_mss2())
10119 +               pci_common_init(&mss2_pci);
10120 +
10121 +       return 0;
10122 +}
10123 +subsys_initcall(mss2_pci_init);
10124 +
10125 +
10126 +/*****************************************************************************
10127 + * Ethernet
10128 + ****************************************************************************/
10129 +
10130 +static struct mv643xx_eth_platform_data mss2_eth_data = {
10131 +       .phy_addr       = 8,
10132 +};
10133 +
10134 +/*****************************************************************************
10135 + * SATA
10136 + ****************************************************************************/
10137 +
10138 +static struct mv_sata_platform_data mss2_sata_data = {
10139 +       .n_ports        = 2,
10140 +};
10141 +
10142 +/*****************************************************************************
10143 + * GPIO buttons
10144 + ****************************************************************************/
10145 +
10146 +#define MSS2_GPIO_KEY_RESET    12
10147 +#define MSS2_GPIO_KEY_POWER    11
10148 +
10149 +static struct gpio_keys_button mss2_buttons[] = {
10150 +       {
10151 +               .code           = KEY_POWER,
10152 +               .gpio           = MSS2_GPIO_KEY_POWER,
10153 +               .desc           = "Power",
10154 +               .active_low     = 1,
10155 +       }, {
10156 +               .code           = KEY_RESTART,
10157 +               .gpio           = MSS2_GPIO_KEY_RESET,
10158 +               .desc           = "Reset",
10159 +               .active_low     = 1,
10160 +       },
10161 +};
10162 +
10163 +static struct gpio_keys_platform_data mss2_button_data = {
10164 +       .buttons        = mss2_buttons,
10165 +       .nbuttons       = ARRAY_SIZE(mss2_buttons),
10166 +};
10167 +
10168 +static struct platform_device mss2_button_device = {
10169 +       .name           = "gpio-keys",
10170 +       .id             = -1,
10171 +       .dev            = {
10172 +               .platform_data  = &mss2_button_data,
10173 +       },
10174 +};
10175 +
10176 +/*****************************************************************************
10177 + * RTC m41t81 on I2C bus
10178 + ****************************************************************************/
10179 +
10180 +#define MSS2_GPIO_RTC_IRQ      3
10181 +
10182 +static struct i2c_board_info __initdata mss2_i2c_rtc = {
10183 +       I2C_BOARD_INFO("m41t81", 0x68),
10184 +};
10185 +
10186 +/*****************************************************************************
10187 + * MSS2 power off method
10188 + ****************************************************************************/
10189 +/*
10190 + * On the Maxtor Shared Storage II, the shutdown process is the following :
10191 + * - Userland modifies U-boot env to tell U-boot to go idle at next boot
10192 + * - The board reboots
10193 + * - U-boot starts and go into an idle mode until the user press "power"
10194 + */
10195 +static void mss2_power_off(void)
10196 +{
10197 +       u32 reg;
10198 +
10199 +       /*
10200 +        * Enable and issue soft reset
10201 +        */
10202 +       reg = readl(CPU_RESET_MASK);
10203 +       reg |= 1 << 2;
10204 +       writel(reg, CPU_RESET_MASK);
10205 +
10206 +       reg = readl(CPU_SOFT_RESET);
10207 +       reg |= 1;
10208 +       writel(reg, CPU_SOFT_RESET);
10209 +}
10210 +
10211 +/****************************************************************************
10212 + * General Setup
10213 + ****************************************************************************/
10214 +static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
10215 +       {  0, MPP_GPIO },               /* Power LED */
10216 +       {  1, MPP_GPIO },               /* Error LED */
10217 +       {  2, MPP_UNUSED },
10218 +       {  3, MPP_GPIO },               /* RTC interrupt */
10219 +       {  4, MPP_GPIO },               /* HDD ind. (Single/Dual)*/
10220 +       {  5, MPP_GPIO },               /* HD0 5V control */
10221 +       {  6, MPP_GPIO },               /* HD0 12V control */
10222 +       {  7, MPP_GPIO },               /* HD1 5V control */
10223 +       {  8, MPP_GPIO },               /* HD1 12V control */
10224 +       {  9, MPP_UNUSED },
10225 +       { 10, MPP_GPIO },               /* Fan control */
10226 +       { 11, MPP_GPIO },               /* Power button */
10227 +       { 12, MPP_GPIO },               /* Reset button */
10228 +       { 13, MPP_UNUSED },
10229 +       { 14, MPP_SATA_LED },           /* SATA 0 active */
10230 +       { 15, MPP_SATA_LED },           /* SATA 1 active */
10231 +       { 16, MPP_UNUSED },
10232 +       { 17, MPP_UNUSED },
10233 +       { 18, MPP_UNUSED },
10234 +       { 19, MPP_UNUSED },
10235 +       { -1 },
10236 +};
10237 +
10238 +static void __init mss2_init(void)
10239 +{
10240 +       /* Setup basic Orion functions. Need to be called early. */
10241 +       orion5x_init();
10242 +
10243 +       orion5x_mpp_conf(mss2_mpp_modes);
10244 +
10245 +       /*
10246 +        * MPP[20] Unused
10247 +        * MPP[21] PCI clock
10248 +        * MPP[22] USB 0 over current
10249 +        * MPP[23] USB 1 over current
10250 +        */
10251 +
10252 +       /*
10253 +        * Configure peripherals.
10254 +        */
10255 +       orion5x_ehci0_init();
10256 +       orion5x_ehci1_init();
10257 +       orion5x_eth_init(&mss2_eth_data);
10258 +       orion5x_i2c_init();
10259 +       orion5x_sata_init(&mss2_sata_data);
10260 +       orion5x_uart0_init();
10261 +
10262 +       orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
10263 +       platform_device_register(&mss2_nor_flash);
10264 +
10265 +       platform_device_register(&mss2_button_device);
10266 +
10267 +       if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) {
10268 +               if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0)
10269 +                       mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ);
10270 +               else
10271 +                       gpio_free(MSS2_GPIO_RTC_IRQ);
10272 +       }
10273 +       i2c_register_board_info(0, &mss2_i2c_rtc, 1);
10274 +
10275 +       /* register mss2 specific power-off method */
10276 +       pm_power_off = mss2_power_off;
10277 +}
10278 +
10279 +MACHINE_START(MSS2, "Maxtor Shared Storage II")
10280 +       /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
10281 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
10282 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
10283 +       .boot_params    = 0x00000100,
10284 +       .init_machine   = mss2_init,
10285 +       .map_io         = orion5x_map_io,
10286 +       .init_irq       = orion5x_init_irq,
10287 +       .timer          = &orion5x_timer,
10288 +       .fixup          = tag_fixup_mem32
10289 +MACHINE_END
10290 --- /dev/null
10291 +++ b/arch/arm/mach-orion5x/mv2120-setup.c
10292 @@ -0,0 +1,194 @@
10293 +/*
10294 + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
10295 + * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
10296 + *
10297 + * This program is free software; you can redistribute it and/or modify
10298 + * it under the terms of the GNU Lesser General Public License as
10299 + * published by the Free Software Foundation; either version 2 of the
10300 + * License, or (at your option) any later version.
10301 + */
10302 +
10303 +#include <linux/kernel.h>
10304 +#include <linux/init.h>
10305 +#include <linux/platform_device.h>
10306 +#include <linux/irq.h>
10307 +#include <linux/mtd/physmap.h>
10308 +#include <linux/mv643xx_eth.h>
10309 +#include <linux/leds.h>
10310 +#include <linux/gpio_keys.h>
10311 +#include <linux/input.h>
10312 +#include <linux/i2c.h>
10313 +#include <linux/ata_platform.h>
10314 +#include <asm/mach-types.h>
10315 +#include <asm/gpio.h>
10316 +#include <asm/mach/arch.h>
10317 +#include <asm/arch/orion5x.h>
10318 +#include "common.h"
10319 +#include "mpp.h"
10320 +
10321 +#define MV2120_NOR_BOOT_BASE   0xf4000000
10322 +#define MV2120_NOR_BOOT_SIZE   SZ_512K
10323 +
10324 +#define MV2120_GPIO_RTC_IRQ    3
10325 +#define MV2120_GPIO_KEY_RESET  17
10326 +#define MV2120_GPIO_KEY_POWER  18
10327 +#define MV2120_GPIO_POWER_OFF  19
10328 +
10329 +
10330 +/*****************************************************************************
10331 + * Ethernet
10332 + ****************************************************************************/
10333 +static struct mv643xx_eth_platform_data mv2120_eth_data = {
10334 +       .phy_addr       = 8,
10335 +};
10336 +
10337 +static struct mv_sata_platform_data mv2120_sata_data = {
10338 +       .n_ports        = 2,
10339 +};
10340 +
10341 +static struct mtd_partition mv2120_partitions[] = {
10342 +       {
10343 +               .name   = "firmware",
10344 +               .size   = 0x00080000,
10345 +               .offset = 0,
10346 +       },
10347 +};
10348 +
10349 +static struct physmap_flash_data mv2120_nor_flash_data = {
10350 +       .width          = 1,
10351 +       .parts          = mv2120_partitions,
10352 +       .nr_parts       = ARRAY_SIZE(mv2120_partitions)
10353 +};
10354 +
10355 +static struct resource mv2120_nor_flash_resource = {
10356 +       .flags          = IORESOURCE_MEM,
10357 +       .start          = MV2120_NOR_BOOT_BASE,
10358 +       .end            = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
10359 +};
10360 +
10361 +static struct platform_device mv2120_nor_flash = {
10362 +       .name           = "physmap-flash",
10363 +       .id             = 0,
10364 +       .dev            = {
10365 +               .platform_data  = &mv2120_nor_flash_data,
10366 +       },
10367 +       .resource       = &mv2120_nor_flash_resource,
10368 +       .num_resources  = 1,
10369 +};
10370 +
10371 +static struct gpio_keys_button mv2120_buttons[] = {
10372 +       {
10373 +               .code           = KEY_RESTART,
10374 +               .gpio           = MV2120_GPIO_KEY_RESET,
10375 +               .desc           = "reset",
10376 +               .active_low     = 1,
10377 +       }, {
10378 +               .code           = KEY_POWER,
10379 +               .gpio           = MV2120_GPIO_KEY_POWER,
10380 +               .desc           = "power",
10381 +               .active_low     = 1,
10382 +       },
10383 +};
10384 +
10385 +static struct gpio_keys_platform_data mv2120_button_data = {
10386 +       .buttons        = mv2120_buttons,
10387 +       .nbuttons       = ARRAY_SIZE(mv2120_buttons),
10388 +};
10389 +
10390 +static struct platform_device mv2120_button_device = {
10391 +       .name           = "gpio-keys",
10392 +       .id             = -1,
10393 +       .num_resources  = 0,
10394 +       .dev            = {
10395 +               .platform_data  = &mv2120_button_data,
10396 +       },
10397 +};
10398 +
10399 +
10400 +/****************************************************************************
10401 + * General Setup
10402 + ****************************************************************************/
10403 +static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
10404 +       {  0, MPP_GPIO },               /* Sys status LED */
10405 +       {  1, MPP_GPIO },               /* Sys error LED */
10406 +       {  2, MPP_GPIO },               /* OverTemp interrupt */
10407 +       {  3, MPP_GPIO },               /* RTC interrupt */
10408 +       {  4, MPP_GPIO },               /* V_LED 5V */
10409 +       {  5, MPP_GPIO },               /* V_LED 3.3V */
10410 +       {  6, MPP_UNUSED },
10411 +       {  7, MPP_UNUSED },
10412 +       {  8, MPP_GPIO },               /* SATA 0 fail LED */
10413 +       {  9, MPP_GPIO },               /* SATA 1 fail LED */
10414 +       { 10, MPP_UNUSED },
10415 +       { 11, MPP_UNUSED },
10416 +       { 12, MPP_SATA_LED },           /* SATA 0 presence */
10417 +       { 13, MPP_SATA_LED },           /* SATA 1 presence */
10418 +       { 14, MPP_SATA_LED },           /* SATA 0 active */
10419 +       { 15, MPP_SATA_LED },           /* SATA 1 active */
10420 +       { 16, MPP_UNUSED },
10421 +       { 17, MPP_GPIO },               /* Reset button */
10422 +       { 18, MPP_GPIO },               /* Power button */
10423 +       { 19, MPP_GPIO },               /* Power off */
10424 +       { -1 },
10425 +};
10426 +
10427 +static struct i2c_board_info __initdata mv2120_i2c_rtc = {
10428 +       I2C_BOARD_INFO("rtc-pcf8563", 0x51),
10429 +       .irq    = 0,
10430 +};
10431 +
10432 +static void mv2120_power_off(void)
10433 +{
10434 +       pr_info("%s: triggering power-off...\n", __func__);
10435 +       gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
10436 +}
10437 +
10438 +static void __init mv2120_init(void)
10439 +{
10440 +       /* Setup basic Orion functions. Need to be called early. */
10441 +       orion5x_init();
10442 +
10443 +       orion5x_mpp_conf(mv2120_mpp_modes);
10444 +
10445 +       /*
10446 +        * Configure peripherals.
10447 +        */
10448 +       orion5x_ehci0_init();
10449 +       orion5x_ehci1_init();
10450 +       orion5x_eth_init(&mv2120_eth_data);
10451 +       orion5x_i2c_init();
10452 +       orion5x_sata_init(&mv2120_sata_data);
10453 +       orion5x_uart0_init();
10454 +
10455 +       orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
10456 +       platform_device_register(&mv2120_nor_flash);
10457 +
10458 +       platform_device_register(&mv2120_button_device);
10459 +
10460 +       if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
10461 +               if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
10462 +                       mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
10463 +               else
10464 +                       gpio_free(MV2120_GPIO_RTC_IRQ);
10465 +       }
10466 +       i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
10467 +
10468 +       /* register mv2120 specific power-off method */
10469 +       if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
10470 +           gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
10471 +               pr_err("mv2120: failed to setup power-off GPIO\n");
10472 +       pm_power_off = mv2120_power_off;
10473 +}
10474 +
10475 +/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
10476 +MACHINE_START(MV2120, "HP Media Vault mv2120")
10477 +       /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
10478 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
10479 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
10480 +       .boot_params    = 0x00000100,
10481 +       .init_machine   = mv2120_init,
10482 +       .map_io         = orion5x_map_io,
10483 +       .init_irq       = orion5x_init_irq,
10484 +       .timer          = &orion5x_timer,
10485 +       .fixup          = tag_fixup_mem32
10486 +MACHINE_END
10487 --- a/arch/arm/mach-orion5x/pci.c
10488 +++ b/arch/arm/mach-orion5x/pci.c
10489 @@ -152,6 +152,8 @@
10490         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
10491                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
10492                                    "read transaction workaround\n");
10493 +               orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
10494 +                                         ORION5X_PCIE_WA_SIZE);
10495                 pcie_ops.read = pcie_rd_conf_wa;
10496         }
10497
10498 @@ -240,13 +242,13 @@
10499   * PCI Address Decode Windows registers
10500   */
10501  #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
10502 -                               ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
10503 -                               ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
10504 -                               ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
10505 -#define PCI_BAR_REMAP_DDR_CS(n)        (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
10506 -                               ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
10507 -                               ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
10508 -                               ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
10509 +                                ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
10510 +                                ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
10511 +                                ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
10512 +#define PCI_BAR_REMAP_DDR_CS(n)        (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
10513 +                                ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
10514 +                                ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
10515 +                                ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
10516  #define PCI_BAR_ENABLE         ORION5X_PCI_REG(0xc3c)
10517  #define PCI_ADDR_DECODE_CTRL   ORION5X_PCI_REG(0xd3c)
10518
10519 @@ -266,7 +268,7 @@
10520
10521  static int orion5x_pci_local_bus_nr(void)
10522  {
10523 -       u32 conf = orion5x_read(PCI_P2P_CONF);
10524 +       u32 conf = readl(PCI_P2P_CONF);
10525         return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
10526  }
10527
10528 @@ -276,11 +278,11 @@
10529         unsigned long flags;
10530         spin_lock_irqsave(&orion5x_pci_lock, flags);
10531
10532 -       orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
10533 -                       PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
10534 -                       PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
10535 +       writel(PCI_CONF_BUS(bus) |
10536 +               PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
10537 +               PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
10538
10539 -       *val = orion5x_read(PCI_CONF_DATA);
10540 +       *val = readl(PCI_CONF_DATA);
10541
10542         if (size == 1)
10543                 *val = (*val >> (8*(where & 0x3))) & 0xff;
10544 @@ -300,9 +302,9 @@
10545
10546         spin_lock_irqsave(&orion5x_pci_lock, flags);
10547
10548 -       orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
10549 -                       PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
10550 -                       PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
10551 +       writel(PCI_CONF_BUS(bus) |
10552 +               PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
10553 +               PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
10554
10555         if (size == 4) {
10556                 __raw_writel(val, PCI_CONF_DATA);
10557 @@ -353,9 +355,9 @@
10558
10559  static void __init orion5x_pci_set_bus_nr(int nr)
10560  {
10561 -       u32 p2p = orion5x_read(PCI_P2P_CONF);
10562 +       u32 p2p = readl(PCI_P2P_CONF);
10563
10564 -       if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
10565 +       if (readl(PCI_MODE) & PCI_MODE_PCIX) {
10566                 /*
10567                  * PCI-X mode
10568                  */
10569 @@ -372,7 +374,7 @@
10570                  */
10571                 p2p &= ~PCI_P2P_BUS_MASK;
10572                 p2p |= (nr << PCI_P2P_BUS_OFFS);
10573 -               orion5x_write(PCI_P2P_CONF, p2p);
10574 +               writel(p2p, PCI_P2P_CONF);
10575         }
10576  }
10577
10578 @@ -399,7 +401,7 @@
10579          * First, disable windows.
10580          */
10581         win_enable = 0xffffffff;
10582 -       orion5x_write(PCI_BAR_ENABLE, win_enable);
10583 +       writel(win_enable, PCI_BAR_ENABLE);
10584
10585         /*
10586          * Setup windows for DDR banks.
10587 @@ -425,10 +427,10 @@
10588                  */
10589                 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
10590                 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
10591 -               orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
10592 -                               (cs->size - 1) & 0xfffff000);
10593 -               orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
10594 -                               cs->base & 0xfffff000);
10595 +               writel((cs->size - 1) & 0xfffff000,
10596 +                       PCI_BAR_SIZE_DDR_CS(cs->cs_index));
10597 +               writel(cs->base & 0xfffff000,
10598 +                       PCI_BAR_REMAP_DDR_CS(cs->cs_index));
10599
10600                 /*
10601                  * Enable decode window for this chip select.
10602 @@ -439,7 +441,7 @@
10603         /*
10604          * Re-enable decode windows.
10605          */
10606 -       orion5x_write(PCI_BAR_ENABLE, win_enable);
10607 +       writel(win_enable, PCI_BAR_ENABLE);
10608
10609         /*
10610          * Disable automatic update of address remaping when writing to BARs.
10611 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c
10612 +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
10613 @@ -26,6 +26,7 @@
10614  #include <asm/mach/pci.h>
10615  #include <asm/arch/orion5x.h>
10616  #include "common.h"
10617 +#include "mpp.h"
10618
10619  /*****************************************************************************
10620   * RD-88F5182 Info
10621 @@ -125,6 +126,7 @@
10622
10623                 leds_event = rd88f5182_dbgled_event;
10624         }
10625 +
10626         return 0;
10627  }
10628
10629 @@ -220,7 +222,6 @@
10630
10631  static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
10632         .phy_addr       = 8,
10633 -       .force_phy_addr = 1,
10634  };
10635
10636  /*****************************************************************************
10637 @@ -234,15 +235,34 @@
10638   * Sata
10639   ****************************************************************************/
10640  static struct mv_sata_platform_data rd88f5182_sata_data = {
10641 -       .n_ports        = 2,
10642 +       .n_ports        = 2,
10643  };
10644
10645  /*****************************************************************************
10646   * General Setup
10647   ****************************************************************************/
10648 -
10649 -static struct platform_device *rd88f5182_devices[] __initdata = {
10650 -       &rd88f5182_nor_flash,
10651 +static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
10652 +       {  0, MPP_GPIO },               /* Debug Led */
10653 +       {  1, MPP_GPIO },               /* Reset Switch */
10654 +       {  2, MPP_UNUSED },
10655 +       {  3, MPP_GPIO },               /* RTC Int */
10656 +       {  4, MPP_GPIO },
10657 +       {  5, MPP_GPIO },
10658 +       {  6, MPP_GPIO },               /* PCI_intA */
10659 +       {  7, MPP_GPIO },               /* PCI_intB */
10660 +       {  8, MPP_UNUSED },
10661 +       {  9, MPP_UNUSED },
10662 +       { 10, MPP_UNUSED },
10663 +       { 11, MPP_UNUSED },
10664 +       { 12, MPP_SATA_LED },           /* SATA 0 presence */
10665 +       { 13, MPP_SATA_LED },           /* SATA 1 presence */
10666 +       { 14, MPP_SATA_LED },           /* SATA 0 active */
10667 +       { 15, MPP_SATA_LED },           /* SATA 1 active */
10668 +       { 16, MPP_UNUSED },
10669 +       { 17, MPP_UNUSED },
10670 +       { 18, MPP_UNUSED },
10671 +       { 19, MPP_UNUSED },
10672 +       { -1 },
10673  };
10674
10675  static void __init rd88f5182_init(void)
10676 @@ -252,35 +272,9 @@
10677          */
10678         orion5x_init();
10679
10680 -       /*
10681 -        * Setup the CPU address decode windows for our devices
10682 -        */
10683 -       orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
10684 -                               RD88F5182_NOR_BOOT_SIZE);
10685 -       orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
10686 -
10687 -       /*
10688 -        * Open a special address decode windows for the PCIe WA.
10689 -        */
10690 -       orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
10691 -                               ORION5X_PCIE_WA_SIZE);
10692 +       orion5x_mpp_conf(rd88f5182_mpp_modes);
10693
10694         /*
10695 -        * Setup Multiplexing Pins --
10696 -        * MPP[0] Debug Led (GPIO - Out)
10697 -        * MPP[1] Debug Led (GPIO - Out)
10698 -        * MPP[2] N/A
10699 -        * MPP[3] RTC_Int (GPIO - In)
10700 -        * MPP[4] GPIO
10701 -        * MPP[5] GPIO
10702 -        * MPP[6] PCI_intA (GPIO - In)
10703 -        * MPP[7] PCI_intB (GPIO - In)
10704 -        * MPP[8-11] N/A
10705 -        * MPP[12] SATA 0 presence Indication
10706 -        * MPP[13] SATA 1 presence Indication
10707 -        * MPP[14] SATA 0 active Indication
10708 -        * MPP[15] SATA 1 active indication
10709 -        * MPP[16-19] Not used
10710          * MPP[20] PCI Clock to MV88F5182
10711          * MPP[21] PCI Clock to mini PCI CON11
10712          * MPP[22] USB 0 over current indication
10713 @@ -289,16 +283,23 @@
10714          * MPP[25] USB 0 over current enable
10715          */
10716
10717 -       orion5x_write(MPP_0_7_CTRL, 0x00000003);
10718 -       orion5x_write(MPP_8_15_CTRL, 0x55550000);
10719 -       orion5x_write(MPP_16_19_CTRL, 0x5555);
10720 +       /*
10721 +        * Configure peripherals.
10722 +        */
10723 +       orion5x_ehci0_init();
10724 +       orion5x_ehci1_init();
10725 +       orion5x_eth_init(&rd88f5182_eth_data);
10726 +       orion5x_i2c_init();
10727 +       orion5x_sata_init(&rd88f5182_sata_data);
10728 +       orion5x_uart0_init();
10729
10730 -       orion5x_gpio_set_valid_pins(0x000000fb);
10731 +       orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
10732 +                                  RD88F5182_NOR_BOOT_SIZE);
10733 +
10734 +       orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
10735 +       platform_device_register(&rd88f5182_nor_flash);
10736
10737 -       platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
10738         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
10739 -       orion5x_eth_init(&rd88f5182_eth_data);
10740 -       orion5x_sata_init(&rd88f5182_sata_data);
10741  }
10742
10743  MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
10744 --- a/arch/arm/mach-orion5x/ts209-setup.c
10745 +++ b/arch/arm/mach-orion5x/ts209-setup.c
10746 @@ -28,6 +28,8 @@
10747  #include <asm/mach/pci.h>
10748  #include <asm/arch/orion5x.h>
10749  #include "common.h"
10750 +#include "mpp.h"
10751 +#include "tsx09-common.h"
10752
10753  #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
10754  #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
10755 @@ -47,52 +49,54 @@
10756   ***************************************************************************/
10757  static struct mtd_partition qnap_ts209_partitions[] = {
10758         {
10759 -               .name       = "U-Boot",
10760 -               .size       = 0x00080000,
10761 -               .offset     = 0x00780000,
10762 -               .mask_flags = MTD_WRITEABLE,
10763 +               .name           = "U-Boot",
10764 +               .size           = 0x00080000,
10765 +               .offset         = 0x00780000,
10766 +               .mask_flags     = MTD_WRITEABLE,
10767         }, {
10768 -               .name   = "Kernel",
10769 -               .size   = 0x00200000,
10770 -               .offset = 0,
10771 +               .name           = "Kernel",
10772 +               .size           = 0x00200000,
10773 +               .offset         = 0,
10774         }, {
10775 -               .name   = "RootFS1",
10776 -               .size   = 0x00400000,
10777 -               .offset = 0x00200000,
10778 +               .name           = "RootFS1",
10779 +               .size           = 0x00400000,
10780 +               .offset         = 0x00200000,
10781         }, {
10782 -               .name   = "RootFS2",
10783 -               .size   = 0x00100000,
10784 -               .offset = 0x00600000,
10785 +               .name           = "RootFS2",
10786 +               .size           = 0x00100000,
10787 +               .offset         = 0x00600000,
10788         }, {
10789 -               .name   = "U-Boot Config",
10790 -               .size   = 0x00020000,
10791 -               .offset = 0x00760000,
10792 +               .name           = "U-Boot Config",
10793 +               .size           = 0x00020000,
10794 +               .offset         = 0x00760000,
10795         }, {
10796 -               .name       = "NAS Config",
10797 -               .size       = 0x00060000,
10798 -               .offset     = 0x00700000,
10799 -               .mask_flags = MTD_WRITEABLE,
10800 -       }
10801 +               .name           = "NAS Config",
10802 +               .size           = 0x00060000,
10803 +               .offset         = 0x00700000,
10804 +               .mask_flags     = MTD_WRITEABLE,
10805 +       },
10806  };
10807
10808  static struct physmap_flash_data qnap_ts209_nor_flash_data = {
10809 -       .width    = 1,
10810 -       .parts    = qnap_ts209_partitions,
10811 -       .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
10812 +       .width          = 1,
10813 +       .parts          = qnap_ts209_partitions,
10814 +       .nr_parts       = ARRAY_SIZE(qnap_ts209_partitions)
10815  };
10816
10817  static struct resource qnap_ts209_nor_flash_resource = {
10818 -       .flags = IORESOURCE_MEM,
10819 -       .start = QNAP_TS209_NOR_BOOT_BASE,
10820 -       .end   = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
10821 +       .flags  = IORESOURCE_MEM,
10822 +       .start  = QNAP_TS209_NOR_BOOT_BASE,
10823 +       .end    = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
10824  };
10825
10826  static struct platform_device qnap_ts209_nor_flash = {
10827 -       .name          = "physmap-flash",
10828 -       .id            = 0,
10829 -       .dev           = { .platform_data = &qnap_ts209_nor_flash_data, },
10830 -       .resource      = &qnap_ts209_nor_flash_resource,
10831 -       .num_resources = 1,
10832 +       .name           = "physmap-flash",
10833 +       .id             = 0,
10834 +       .dev            = {
10835 +               .platform_data  = &qnap_ts209_nor_flash_data,
10836 +       },
10837 +       .resource       = &qnap_ts209_nor_flash_resource,
10838 +       .num_resources  = 1,
10839  };
10840
10841  /*****************************************************************************
10842 @@ -164,12 +168,12 @@
10843  }
10844
10845  static struct hw_pci qnap_ts209_pci __initdata = {
10846 -       .nr_controllers = 2,
10847 -       .preinit        = qnap_ts209_pci_preinit,
10848 -       .swizzle        = pci_std_swizzle,
10849 -       .setup          = orion5x_pci_sys_setup,
10850 -       .scan           = orion5x_pci_sys_scan_bus,
10851 -       .map_irq        = qnap_ts209_pci_map_irq,
10852 +       .nr_controllers = 2,
10853 +       .preinit        = qnap_ts209_pci_preinit,
10854 +       .swizzle        = pci_std_swizzle,
10855 +       .setup          = orion5x_pci_sys_setup,
10856 +       .scan           = orion5x_pci_sys_scan_bus,
10857 +       .map_irq        = qnap_ts209_pci_map_irq,
10858  };
10859
10860  static int __init qnap_ts209_pci_init(void)
10861 @@ -183,96 +187,6 @@
10862  subsys_initcall(qnap_ts209_pci_init);
10863
10864  /*****************************************************************************
10865 - * Ethernet
10866 - ****************************************************************************/
10867 -
10868 -static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
10869 -       .phy_addr       = 8,
10870 -       .force_phy_addr = 1,
10871 -};
10872 -
10873 -static int __init parse_hex_nibble(char n)
10874 -{
10875 -       if (n >= '0' && n <= '9')
10876 -               return n - '0';
10877 -
10878 -       if (n >= 'A' && n <= 'F')
10879 -               return n - 'A' + 10;
10880 -
10881 -       if (n >= 'a' && n <= 'f')
10882 -               return n - 'a' + 10;
10883 -
10884 -       return -1;
10885 -}
10886 -
10887 -static int __init parse_hex_byte(const char *b)
10888 -{
10889 -       int hi;
10890 -       int lo;
10891 -
10892 -       hi = parse_hex_nibble(b[0]);
10893 -       lo = parse_hex_nibble(b[1]);
10894 -
10895 -       if (hi < 0 || lo < 0)
10896 -               return -1;
10897 -
10898 -       return (hi << 4) | lo;
10899 -}
10900 -
10901 -static int __init check_mac_addr(const char *addr_str)
10902 -{
10903 -       u_int8_t addr[6];
10904 -       int i;
10905 -
10906 -       for (i = 0; i < 6; i++) {
10907 -               int byte;
10908 -
10909 -               /*
10910 -                * Enforce "xx:xx:xx:xx:xx:xx\n" format.
10911 -                */
10912 -               if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
10913 -                       return -1;
10914 -
10915 -               byte = parse_hex_byte(addr_str + (i * 3));
10916 -               if (byte < 0)
10917 -                       return -1;
10918 -               addr[i] = byte;
10919 -       }
10920 -
10921 -       printk(KERN_INFO "ts209: found ethernet mac address ");
10922 -       for (i = 0; i < 6; i++)
10923 -               printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
10924 -
10925 -       memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
10926 -
10927 -       return 0;
10928 -}
10929 -
10930 -/*
10931 - * The 'NAS Config' flash partition has an ext2 filesystem which
10932 - * contains a file that has the ethernet MAC address in plain text
10933 - * (format "xx:xx:xx:xx:xx:xx\n".)
10934 - */
10935 -static void __init ts209_find_mac_addr(void)
10936 -{
10937 -       unsigned long addr;
10938 -
10939 -       for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
10940 -               char *nor_page;
10941 -               int ret = 0;
10942 -
10943 -               nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
10944 -               if (nor_page != NULL) {
10945 -                       ret = check_mac_addr(nor_page);
10946 -                       iounmap(nor_page);
10947 -               }
10948 -
10949 -               if (ret == 0)
10950 -                       break;
10951 -       }
10952 -}
10953 -
10954 -/*****************************************************************************
10955   * RTC S35390A on I2C bus
10956   ****************************************************************************/
10957
10958 @@ -280,7 +194,7 @@
10959
10960  static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
10961         I2C_BOARD_INFO("s35390a", 0x30),
10962 -       .irq         = 0,
10963 +       .irq    = 0,
10964  };
10965
10966  /****************************************************************************
10967 @@ -297,70 +211,63 @@
10968                 .gpio           = QNAP_TS209_GPIO_KEY_MEDIA,
10969                 .desc           = "USB Copy Button",
10970                 .active_low     = 1,
10971 -       },
10972 -       {
10973 +       }, {
10974                 .code           = KEY_POWER,
10975                 .gpio           = QNAP_TS209_GPIO_KEY_RESET,
10976                 .desc           = "Reset Button",
10977                 .active_low     = 1,
10978 -       }
10979 +       },
10980  };
10981
10982  static struct gpio_keys_platform_data qnap_ts209_button_data = {
10983         .buttons        = qnap_ts209_buttons,
10984 -       .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
10985 +       .nbuttons       = ARRAY_SIZE(qnap_ts209_buttons),
10986  };
10987
10988  static struct platform_device qnap_ts209_button_device = {
10989         .name           = "gpio-keys",
10990         .id             = -1,
10991         .num_resources  = 0,
10992 -       .dev            = { .platform_data  = &qnap_ts209_button_data, },
10993 +       .dev            = {
10994 +               .platform_data  = &qnap_ts209_button_data,
10995 +       },
10996  };
10997
10998  /*****************************************************************************
10999   * SATA
11000   ****************************************************************************/
11001  static struct mv_sata_platform_data qnap_ts209_sata_data = {
11002 -       .n_ports        = 2,
11003 +       .n_ports        = 2,
11004  };
11005
11006  /*****************************************************************************
11007
11008   * General Setup
11009   ****************************************************************************/
11010 -
11011 -static struct platform_device *qnap_ts209_devices[] __initdata = {
11012 -       &qnap_ts209_nor_flash,
11013 -       &qnap_ts209_button_device,
11014 +static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
11015 +       {  0, MPP_UNUSED },
11016 +       {  1, MPP_GPIO },               /* USB copy button */
11017 +       {  2, MPP_GPIO },               /* Load defaults button */
11018 +       {  3, MPP_GPIO },               /* GPIO RTC */
11019 +       {  4, MPP_UNUSED },
11020 +       {  5, MPP_UNUSED },
11021 +       {  6, MPP_GPIO },               /* PCI Int A */
11022 +       {  7, MPP_GPIO },               /* PCI Int B */
11023 +       {  8, MPP_UNUSED },
11024 +       {  9, MPP_UNUSED },
11025 +       { 10, MPP_UNUSED },
11026 +       { 11, MPP_UNUSED },
11027 +       { 12, MPP_SATA_LED },           /* SATA 0 presence */
11028 +       { 13, MPP_SATA_LED },           /* SATA 1 presence */
11029 +       { 14, MPP_SATA_LED },           /* SATA 0 active */
11030 +       { 15, MPP_SATA_LED },           /* SATA 1 active */
11031 +       { 16, MPP_UART },               /* UART1 RXD */
11032 +       { 17, MPP_UART },               /* UART1 TXD */
11033 +       { 18, MPP_GPIO },               /* SW_RST */
11034 +       { 19, MPP_UNUSED },
11035 +       { -1 },
11036  };
11037
11038 -/*
11039 - * QNAP TS-[12]09 specific power off method via UART1-attached PIC
11040 - */
11041 -
11042 -#define UART1_REG(x)  (UART1_VIRT_BASE + ((UART_##x) << 2))
11043 -
11044 -static void qnap_ts209_power_off(void)
11045 -{
11046 -       /* 19200 baud divisor */
11047 -       const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
11048 -
11049 -       pr_info("%s: triggering power-off...\n", __func__);
11050 -
11051 -       /* hijack uart1 and reset into sane state (19200,8n1) */
11052 -       orion5x_write(UART1_REG(LCR), 0x83);
11053 -       orion5x_write(UART1_REG(DLL), divisor & 0xff);
11054 -       orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
11055 -       orion5x_write(UART1_REG(LCR), 0x03);
11056 -       orion5x_write(UART1_REG(IER), 0x00);
11057 -       orion5x_write(UART1_REG(FCR), 0x00);
11058 -       orion5x_write(UART1_REG(MCR), 0x00);
11059 -
11060 -       /* send the power-off command 'A' to PIC */
11061 -       orion5x_write(UART1_REG(TX), 'A');
11062 -}
11063 -
11064  static void __init qnap_ts209_init(void)
11065  {
11066         /*
11067 @@ -368,51 +275,33 @@
11068          */
11069         orion5x_init();
11070
11071 -       /*
11072 -        * Setup flash mapping
11073 -        */
11074 -       orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
11075 -                           QNAP_TS209_NOR_BOOT_SIZE);
11076 -
11077 -       /*
11078 -        * Open a special address decode windows for the PCIe WA.
11079 -        */
11080 -       orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
11081 -                               ORION5X_PCIE_WA_SIZE);
11082 +       orion5x_mpp_conf(ts209_mpp_modes);
11083
11084         /*
11085 -        * Setup Multiplexing Pins --
11086 -        * MPP[0] Reserved
11087 -        * MPP[1] USB copy button (0 active)
11088 -        * MPP[2] Load defaults button (0 active)
11089 -        * MPP[3] GPIO RTC
11090 -        * MPP[4-5] Reserved
11091 -        * MPP[6] PCI Int A
11092 -        * MPP[7] PCI Int B
11093 -        * MPP[8-11] Reserved
11094 -        * MPP[12] SATA 0 presence
11095 -        * MPP[13] SATA 1 presence
11096 -        * MPP[14] SATA 0 active
11097 -        * MPP[15] SATA 1 active
11098 -        * MPP[16] UART1 RXD
11099 -        * MPP[17] UART1 TXD
11100 -        * MPP[18] SW_RST (0 active)
11101 -        * MPP[19] Reserved
11102          * MPP[20] PCI clock 0
11103          * MPP[21] PCI clock 1
11104          * MPP[22] USB 0 over current
11105          * MPP[23-25] Reserved
11106          */
11107 -       orion5x_write(MPP_0_7_CTRL, 0x3);
11108 -       orion5x_write(MPP_8_15_CTRL, 0x55550000);
11109 -       orion5x_write(MPP_16_19_CTRL, 0x5500);
11110 -       orion5x_gpio_set_valid_pins(0x3cc0fff);
11111
11112 -       /* register ts209 specific power-off method */
11113 -       pm_power_off = qnap_ts209_power_off;
11114 +       /*
11115 +        * Configure peripherals.
11116 +        */
11117 +       orion5x_ehci0_init();
11118 +       orion5x_ehci1_init();
11119 +       qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
11120 +                                qnap_ts209_partitions[5].offset,
11121 +                                qnap_ts209_partitions[5].size);
11122 +       orion5x_eth_init(&qnap_tsx09_eth_data);
11123 +       orion5x_i2c_init();
11124 +       orion5x_sata_init(&qnap_ts209_sata_data);
11125 +       orion5x_uart0_init();
11126 +
11127 +       orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
11128 +                                  QNAP_TS209_NOR_BOOT_SIZE);
11129 +       platform_device_register(&qnap_ts209_nor_flash);
11130
11131 -       platform_add_devices(qnap_ts209_devices,
11132 -                               ARRAY_SIZE(qnap_ts209_devices));
11133 +       platform_device_register(&qnap_ts209_button_device);
11134
11135         /* Get RTC IRQ and register the chip */
11136         if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
11137 @@ -425,14 +314,12 @@
11138                 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
11139         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
11140
11141 -       ts209_find_mac_addr();
11142 -       orion5x_eth_init(&qnap_ts209_eth_data);
11143 -
11144 -       orion5x_sata_init(&qnap_ts209_sata_data);
11145 +       /* register tsx09 specific power-off method */
11146 +       pm_power_off = qnap_tsx09_power_off;
11147  }
11148
11149  MACHINE_START(TS209, "QNAP TS-109/TS-209")
11150 -       /* Maintainer:  Byron Bradley <byron.bbradley@gmail.com> */
11151 +       /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
11152         .phys_io        = ORION5X_REGS_PHYS_BASE,
11153         .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
11154         .boot_params    = 0x00000100,
11155 --- /dev/null
11156 +++ b/arch/arm/mach-orion5x/ts409-setup.c
11157 @@ -0,0 +1,273 @@
11158 +/*
11159 + * QNAP TS-409 Board Setup
11160 + *
11161 + * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
11162 + *
11163 + * This program is free software; you can redistribute it and/or
11164 + * modify it under the terms of the GNU General Public License
11165 + * as published by the Free Software Foundation; either version
11166 + * 2 of the License, or (at your option) any later version.
11167 + */
11168 +
11169 +#include <linux/kernel.h>
11170 +#include <linux/init.h>
11171 +#include <linux/platform_device.h>
11172 +#include <linux/pci.h>
11173 +#include <linux/irq.h>
11174 +#include <linux/mtd/physmap.h>
11175 +#include <linux/mv643xx_eth.h>
11176 +#include <linux/gpio_keys.h>
11177 +#include <linux/input.h>
11178 +#include <linux/i2c.h>
11179 +#include <linux/serial_reg.h>
11180 +#include <asm/mach-types.h>
11181 +#include <asm/gpio.h>
11182 +#include <asm/mach/arch.h>
11183 +#include <asm/mach/pci.h>
11184 +#include <asm/arch/orion5x.h>
11185 +#include "common.h"
11186 +#include "mpp.h"
11187 +#include "tsx09-common.h"
11188 +
11189 +/*****************************************************************************
11190 + * QNAP TS-409 Info
11191 + ****************************************************************************/
11192 +
11193 +/*
11194 + * QNAP TS-409 hardware :
11195 + * - Marvell 88F5281-D0
11196 + * - Marvell 88SX7042 SATA controller (PCIe)
11197 + * - Marvell 88E1118 Gigabit Ethernet PHY
11198 + * - RTC S35390A (@0x30) on I2C bus
11199 + * - 8MB NOR flash
11200 + * - 256MB of DDR-2 RAM
11201 + */
11202 +
11203 +/*
11204 + * 8MB NOR flash Device bus boot chip select
11205 + */
11206 +
11207 +#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
11208 +#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
11209 +
11210 +/****************************************************************************
11211 + * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
11212 + *     partitions on the device because we want to keep compatability with
11213 + *     existing QNAP firmware.
11214 + *
11215 + * Layout as used by QNAP:
11216 + *  [2] 0x00000000-0x00200000 : "Kernel"
11217 + *  [3] 0x00200000-0x00600000 : "RootFS1"
11218 + *  [4] 0x00600000-0x00700000 : "RootFS2"
11219 + *  [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
11220 + *  [5] 0x00760000-0x00780000 : "U-Boot Config"
11221 + *  [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
11222 + ***************************************************************************/
11223 +static struct mtd_partition qnap_ts409_partitions[] = {
11224 +       {
11225 +               .name           = "U-Boot",
11226 +               .size           = 0x00080000,
11227 +               .offset         = 0x00780000,
11228 +               .mask_flags     = MTD_WRITEABLE,
11229 +       }, {
11230 +               .name           = "Kernel",
11231 +               .size           = 0x00200000,
11232 +               .offset         = 0,
11233 +       }, {
11234 +               .name           = "RootFS1",
11235 +               .size           = 0x00400000,
11236 +               .offset         = 0x00200000,
11237 +       }, {
11238 +               .name           = "RootFS2",
11239 +               .size           = 0x00100000,
11240 +               .offset         = 0x00600000,
11241 +       }, {
11242 +               .name           = "U-Boot Config",
11243 +               .size           = 0x00020000,
11244 +               .offset         = 0x00760000,
11245 +       }, {
11246 +               .name           = "NAS Config",
11247 +               .size           = 0x00060000,
11248 +               .offset         = 0x00700000,
11249 +               .mask_flags     = MTD_WRITEABLE,
11250 +       },
11251 +};
11252 +
11253 +static struct physmap_flash_data qnap_ts409_nor_flash_data = {
11254 +       .width          = 1,
11255 +       .parts          = qnap_ts409_partitions,
11256 +       .nr_parts       = ARRAY_SIZE(qnap_ts409_partitions)
11257 +};
11258 +
11259 +static struct resource qnap_ts409_nor_flash_resource = {
11260 +       .flags  = IORESOURCE_MEM,
11261 +       .start  = QNAP_TS409_NOR_BOOT_BASE,
11262 +       .end    = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
11263 +};
11264 +
11265 +static struct platform_device qnap_ts409_nor_flash = {
11266 +       .name           = "physmap-flash",
11267 +       .id             = 0,
11268 +       .dev            = { .platform_data = &qnap_ts409_nor_flash_data, },
11269 +       .num_resources  = 1,
11270 +       .resource       = &qnap_ts409_nor_flash_resource,
11271 +};
11272 +
11273 +/*****************************************************************************
11274 + * PCI
11275 + ****************************************************************************/
11276 +
11277 +static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11278 +{
11279 +       int irq;
11280 +
11281 +       /*
11282 +        * Check for devices with hard-wired IRQs.
11283 +        */
11284 +       irq = orion5x_pci_map_irq(dev, slot, pin);
11285 +       if (irq != -1)
11286 +               return irq;
11287 +
11288 +       /*
11289 +        * PCI isn't used on the TS-409
11290 +        */
11291 +       return -1;
11292 +}
11293 +
11294 +static struct hw_pci qnap_ts409_pci __initdata = {
11295 +       .nr_controllers = 2,
11296 +       .swizzle        = pci_std_swizzle,
11297 +       .setup          = orion5x_pci_sys_setup,
11298 +       .scan           = orion5x_pci_sys_scan_bus,
11299 +       .map_irq        = qnap_ts409_pci_map_irq,
11300 +};
11301 +
11302 +static int __init qnap_ts409_pci_init(void)
11303 +{
11304 +       if (machine_is_ts409())
11305 +               pci_common_init(&qnap_ts409_pci);
11306 +
11307 +       return 0;
11308 +}
11309 +
11310 +subsys_initcall(qnap_ts409_pci_init);
11311 +
11312 +/*****************************************************************************
11313 + * RTC S35390A on I2C bus
11314 + ****************************************************************************/
11315 +
11316 +#define TS409_RTC_GPIO 10
11317 +
11318 +static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
11319 +       I2C_BOARD_INFO("s35390a", 0x30),
11320 +};
11321 +
11322 +/****************************************************************************
11323 + * GPIO Attached Keys
11324 + *     Power button is attached to the PIC microcontroller
11325 + ****************************************************************************/
11326 +
11327 +#define QNAP_TS409_GPIO_KEY_MEDIA      15
11328 +
11329 +static struct gpio_keys_button qnap_ts409_buttons[] = {
11330 +       {
11331 +               .code           = KEY_RESTART,
11332 +               .gpio           = QNAP_TS409_GPIO_KEY_MEDIA,
11333 +               .desc           = "USB Copy Button",
11334 +               .active_low     = 1,
11335 +       },
11336 +};
11337 +
11338 +static struct gpio_keys_platform_data qnap_ts409_button_data = {
11339 +       .buttons        = qnap_ts409_buttons,
11340 +       .nbuttons       = ARRAY_SIZE(qnap_ts409_buttons),
11341 +};
11342 +
11343 +static struct platform_device qnap_ts409_button_device = {
11344 +       .name           = "gpio-keys",
11345 +       .id             = -1,
11346 +       .num_resources  = 0,
11347 +       .dev            = {
11348 +               .platform_data  = &qnap_ts409_button_data,
11349 +       },
11350 +};
11351 +
11352 +/*****************************************************************************
11353 + * General Setup
11354 + ****************************************************************************/
11355 +static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
11356 +       {  0, MPP_UNUSED },
11357 +       {  1, MPP_UNUSED },
11358 +       {  2, MPP_UNUSED },
11359 +       {  3, MPP_UNUSED },
11360 +       {  4, MPP_GPIO },               /* HDD 1 status */
11361 +       {  5, MPP_GPIO },               /* HDD 2 status */
11362 +       {  6, MPP_GPIO },               /* HDD 3 status */
11363 +       {  7, MPP_GPIO },               /* HDD 4 status */
11364 +       {  8, MPP_UNUSED },
11365 +       {  9, MPP_UNUSED },
11366 +       { 10, MPP_GPIO },               /* RTC int */
11367 +       { 11, MPP_UNUSED },
11368 +       { 12, MPP_UNUSED },
11369 +       { 13, MPP_UNUSED },
11370 +       { 14, MPP_GPIO },               /* SW_RST */
11371 +       { 15, MPP_GPIO },               /* USB copy button */
11372 +       { 16, MPP_UART },               /* UART1 RXD */
11373 +       { 17, MPP_UART },               /* UART1 TXD */
11374 +       { 18, MPP_UNUSED },
11375 +       { 19, MPP_UNUSED },
11376 +       { -1 },
11377 +};
11378 +
11379 +static void __init qnap_ts409_init(void)
11380 +{
11381 +       /*
11382 +        * Setup basic Orion functions. Need to be called early.
11383 +        */
11384 +       orion5x_init();
11385 +
11386 +       orion5x_mpp_conf(ts409_mpp_modes);
11387 +
11388 +       /*
11389 +        * Configure peripherals.
11390 +        */
11391 +       orion5x_ehci0_init();
11392 +       qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
11393 +                                qnap_ts409_partitions[5].offset,
11394 +                                qnap_ts409_partitions[5].size);
11395 +       orion5x_eth_init(&qnap_tsx09_eth_data);
11396 +       orion5x_i2c_init();
11397 +       orion5x_uart0_init();
11398 +
11399 +       orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
11400 +                                  QNAP_TS409_NOR_BOOT_SIZE);
11401 +       platform_device_register(&qnap_ts409_nor_flash);
11402 +
11403 +       platform_device_register(&qnap_ts409_button_device);
11404 +
11405 +       /* Get RTC IRQ and register the chip */
11406 +       if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
11407 +               if (gpio_direction_input(TS409_RTC_GPIO) == 0)
11408 +                       qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
11409 +               else
11410 +                       gpio_free(TS409_RTC_GPIO);
11411 +       }
11412 +       if (qnap_ts409_i2c_rtc.irq == 0)
11413 +               pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
11414 +       i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
11415 +
11416 +       /* register tsx09 specific power-off method */
11417 +       pm_power_off = qnap_tsx09_power_off;
11418 +}
11419 +
11420 +MACHINE_START(TS409, "QNAP TS-409")
11421 +       /* Maintainer:  Sylver Bruneau <sylver.bruneau@gmail.com> */
11422 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
11423 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
11424 +       .boot_params    = 0x00000100,
11425 +       .init_machine   = qnap_ts409_init,
11426 +       .map_io         = orion5x_map_io,
11427 +       .init_irq       = orion5x_init_irq,
11428 +       .timer          = &orion5x_timer,
11429 +       .fixup          = tag_fixup_mem32,
11430 +MACHINE_END
11431 --- /dev/null
11432 +++ b/arch/arm/mach-orion5x/ts78xx-setup.c
11433 @@ -0,0 +1,277 @@
11434 +/*
11435 + * arch/arm/mach-orion5x/ts78xx-setup.c
11436 + *
11437 + * Maintainer: Alexander Clouter <alex@digriz.org.uk>
11438 + *
11439 + * This file is licensed under the terms of the GNU General Public
11440 + * License version 2.  This program is licensed "as is" without any
11441 + * warranty of any kind, whether express or implied.
11442 + */
11443 +
11444 +#include <linux/kernel.h>
11445 +#include <linux/init.h>
11446 +#include <linux/platform_device.h>
11447 +#include <linux/mtd/physmap.h>
11448 +#include <linux/mv643xx_eth.h>
11449 +#include <linux/ata_platform.h>
11450 +#include <linux/m48t86.h>
11451 +#include <asm/mach-types.h>
11452 +#include <asm/mach/arch.h>
11453 +#include <asm/mach/map.h>
11454 +#include <asm/arch/orion5x.h>
11455 +#include "common.h"
11456 +#include "mpp.h"
11457 +
11458 +/*****************************************************************************
11459 + * TS-78xx Info
11460 + ****************************************************************************/
11461 +
11462 +/*
11463 + * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
11464 + */
11465 +#define TS78XX_FPGA_REGS_PHYS_BASE     0xe8000000
11466 +#define TS78XX_FPGA_REGS_VIRT_BASE     0xff900000
11467 +#define TS78XX_FPGA_REGS_SIZE          SZ_1M
11468 +
11469 +#define TS78XX_FPGA_REGS_SYSCON_ID     (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
11470 +#define TS78XX_FPGA_REGS_SYSCON_LCDI   (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
11471 +#define TS78XX_FPGA_REGS_SYSCON_LCDO   (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
11472 +
11473 +#define TS78XX_FPGA_REGS_RTC_CTRL      (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
11474 +#define TS78XX_FPGA_REGS_RTC_DATA      (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
11475 +
11476 +/*
11477 + * 512kB NOR flash Device
11478 + */
11479 +#define TS78XX_NOR_BOOT_BASE           0xff800000
11480 +#define TS78XX_NOR_BOOT_SIZE           SZ_512K
11481 +
11482 +/*****************************************************************************
11483 + * I/O Address Mapping
11484 + ****************************************************************************/
11485 +static struct map_desc ts78xx_io_desc[] __initdata = {
11486 +       {
11487 +               .virtual        = TS78XX_FPGA_REGS_VIRT_BASE,
11488 +               .pfn            = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
11489 +               .length         = TS78XX_FPGA_REGS_SIZE,
11490 +               .type           = MT_DEVICE,
11491 +       },
11492 +};
11493 +
11494 +void __init ts78xx_map_io(void)
11495 +{
11496 +       orion5x_map_io();
11497 +       iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
11498 +}
11499 +
11500 +/*****************************************************************************
11501 + * 512kB NOR Boot Flash - the chip is a M25P40
11502 + ****************************************************************************/
11503 +static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
11504 +       {
11505 +               .name           = "ts-bootrom",
11506 +               .offset         = 0,
11507 +               /* only the first 256kB is used */
11508 +               .size           = SZ_256K,
11509 +               .mask_flags     = MTD_WRITEABLE,
11510 +       },
11511 +};
11512 +
11513 +static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
11514 +       .width          = 1,
11515 +       .parts          = ts78xx_nor_boot_flash_resources,
11516 +       .nr_parts       = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
11517 +};
11518 +
11519 +static struct resource ts78xx_nor_boot_flash_resource = {
11520 +       .flags          = IORESOURCE_MEM,
11521 +       .start          = TS78XX_NOR_BOOT_BASE,
11522 +       .end            = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
11523 +};
11524 +
11525 +static struct platform_device ts78xx_nor_boot_flash = {
11526 +       .name           = "physmap-flash",
11527 +       .id             = -1,
11528 +       .dev            = {
11529 +               .platform_data  = &ts78xx_nor_boot_flash_data,
11530 +       },
11531 +       .num_resources  = 1,
11532 +       .resource       = &ts78xx_nor_boot_flash_resource,
11533 +};
11534 +
11535 +/*****************************************************************************
11536 + * Ethernet
11537 + ****************************************************************************/
11538 +static struct mv643xx_eth_platform_data ts78xx_eth_data = {
11539 +       .phy_addr       = 0,
11540 +       .force_phy_addr = 1,
11541 +};
11542 +
11543 +/*****************************************************************************
11544 + * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
11545 + ****************************************************************************/
11546 +#ifdef CONFIG_RTC_DRV_M48T86
11547 +static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
11548 +{
11549 +       writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
11550 +       return readb(TS78XX_FPGA_REGS_RTC_DATA);
11551 +}
11552 +
11553 +static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
11554 +{
11555 +       writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
11556 +       writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
11557 +}
11558 +
11559 +static struct m48t86_ops ts78xx_rtc_ops = {
11560 +       .readbyte       = ts78xx_rtc_readbyte,
11561 +       .writebyte      = ts78xx_rtc_writebyte,
11562 +};
11563 +
11564 +static struct platform_device ts78xx_rtc_device = {
11565 +       .name           = "rtc-m48t86",
11566 +       .id             = -1,
11567 +       .dev            = {
11568 +               .platform_data  = &ts78xx_rtc_ops,
11569 +       },
11570 +       .num_resources  = 0,
11571 +};
11572 +
11573 +/*
11574 + * TS uses some of the user storage space on the RTC chip so see if it is
11575 + * present; as it's an optional feature at purchase time and not all boards
11576 + * will have it present
11577 + *
11578 + * I've used the method TS use in their rtc7800.c example for the detection
11579 + *
11580 + * TODO: track down a guinea pig without an RTC to see if we can work out a
11581 + *             better RTC detection routine
11582 + */
11583 +static int __init ts78xx_rtc_init(void)
11584 +{
11585 +       unsigned char tmp_rtc0, tmp_rtc1;
11586 +
11587 +       tmp_rtc0 = ts78xx_rtc_readbyte(126);
11588 +       tmp_rtc1 = ts78xx_rtc_readbyte(127);
11589 +
11590 +       ts78xx_rtc_writebyte(0x00, 126);
11591 +       ts78xx_rtc_writebyte(0x55, 127);
11592 +       if (ts78xx_rtc_readbyte(127) == 0x55) {
11593 +               ts78xx_rtc_writebyte(0xaa, 127);
11594 +               if (ts78xx_rtc_readbyte(127) == 0xaa
11595 +                               && ts78xx_rtc_readbyte(126) == 0x00) {
11596 +                       ts78xx_rtc_writebyte(tmp_rtc0, 126);
11597 +                       ts78xx_rtc_writebyte(tmp_rtc1, 127);
11598 +                       platform_device_register(&ts78xx_rtc_device);
11599 +                       return 1;
11600 +               }
11601 +       }
11602 +
11603 +       return 0;
11604 +};
11605 +#else
11606 +static int __init ts78xx_rtc_init(void)
11607 +{
11608 +       return 0;
11609 +}
11610 +#endif
11611 +
11612 +/*****************************************************************************
11613 + * SATA
11614 + ****************************************************************************/
11615 +static struct mv_sata_platform_data ts78xx_sata_data = {
11616 +       .n_ports        = 2,
11617 +};
11618 +
11619 +/*****************************************************************************
11620 + * print some information regarding the board
11621 + ****************************************************************************/
11622 +static void __init ts78xx_print_board_id(void)
11623 +{
11624 +       unsigned int board_info;
11625 +
11626 +       board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
11627 +       printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
11628 +                               board_info & 0xff,
11629 +                               (board_info >> 8) & 0xffffff);
11630 +       board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
11631 +       printk("JP1=%d, JP2=%d\n",
11632 +                               (board_info >> 30) & 0x1,
11633 +                               (board_info >> 31) & 0x1);
11634 +};
11635 +
11636 +/*****************************************************************************
11637 + * General Setup
11638 + ****************************************************************************/
11639 +static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
11640 +       {  0, MPP_UNUSED },
11641 +       {  1, MPP_GPIO },               /* JTAG Clock */
11642 +       {  2, MPP_GPIO },               /* JTAG Data In */
11643 +       {  3, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB2B */
11644 +       {  4, MPP_GPIO },               /* JTAG Data Out */
11645 +       {  5, MPP_GPIO },               /* JTAG TMS */
11646 +       {  6, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
11647 +       {  7, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB22B */
11648 +       {  8, MPP_UNUSED },
11649 +       {  9, MPP_UNUSED },
11650 +       { 10, MPP_UNUSED },
11651 +       { 11, MPP_UNUSED },
11652 +       { 12, MPP_UNUSED },
11653 +       { 13, MPP_UNUSED },
11654 +       { 14, MPP_UNUSED },
11655 +       { 15, MPP_UNUSED },
11656 +       { 16, MPP_UART },
11657 +       { 17, MPP_UART },
11658 +       { 18, MPP_UART },
11659 +       { 19, MPP_UART },
11660 +       { -1 },
11661 +};
11662 +
11663 +static void __init ts78xx_init(void)
11664 +{
11665 +       /*
11666 +        * Setup basic Orion functions. Need to be called early.
11667 +        */
11668 +       orion5x_init();
11669 +
11670 +       ts78xx_print_board_id();
11671 +
11672 +       orion5x_mpp_conf(ts78xx_mpp_modes);
11673 +
11674 +       /*
11675 +        * MPP[20] PCI Clock Out 1
11676 +        * MPP[21] PCI Clock Out 0
11677 +        * MPP[22] Unused
11678 +        * MPP[23] Unused
11679 +        * MPP[24] Unused
11680 +        * MPP[25] Unused
11681 +        */
11682 +
11683 +       /*
11684 +        * Configure peripherals.
11685 +        */
11686 +       orion5x_ehci0_init();
11687 +       orion5x_ehci1_init();
11688 +       orion5x_eth_init(&ts78xx_eth_data);
11689 +       orion5x_sata_init(&ts78xx_sata_data);
11690 +       orion5x_uart0_init();
11691 +       orion5x_uart1_init();
11692 +
11693 +       orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
11694 +                                  TS78XX_NOR_BOOT_SIZE);
11695 +       platform_device_register(&ts78xx_nor_boot_flash);
11696 +
11697 +       if (!ts78xx_rtc_init())
11698 +               printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
11699 +}
11700 +
11701 +MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
11702 +       /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
11703 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
11704 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
11705 +       .boot_params    = 0x00000100,
11706 +       .init_machine   = ts78xx_init,
11707 +       .map_io         = ts78xx_map_io,
11708 +       .init_irq       = orion5x_init_irq,
11709 +       .timer          = &orion5x_timer,
11710 +MACHINE_END
11711 --- /dev/null
11712 +++ b/arch/arm/mach-orion5x/tsx09-common.c
11713 @@ -0,0 +1,132 @@
11714 +/*
11715 + * QNAP TS-x09 Boards common functions
11716 + *
11717 + * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
11718 + *             Byron Bradley <byron.bbradley@gmail.com>
11719 + *
11720 + * This program is free software; you can redistribute it and/or
11721 + * modify it under the terms of the GNU General Public License
11722 + * as published by the Free Software Foundation; either version
11723 + * 2 of the License, or (at your option) any later version.
11724 + */
11725 +
11726 +#include <linux/kernel.h>
11727 +#include <linux/pci.h>
11728 +#include <linux/mv643xx_eth.h>
11729 +#include <linux/serial_reg.h>
11730 +#include "tsx09-common.h"
11731 +
11732 +/*****************************************************************************
11733 + * QNAP TS-x09 specific power off method via UART1-attached PIC
11734 + ****************************************************************************/
11735 +
11736 +#define UART1_REG(x)   (UART1_VIRT_BASE + ((UART_##x) << 2))
11737 +
11738 +void qnap_tsx09_power_off(void)
11739 +{
11740 +       /* 19200 baud divisor */
11741 +       const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
11742 +
11743 +       pr_info("%s: triggering power-off...\n", __func__);
11744 +
11745 +       /* hijack uart1 and reset into sane state (19200,8n1) */
11746 +       writel(0x83, UART1_REG(LCR));
11747 +       writel(divisor & 0xff, UART1_REG(DLL));
11748 +       writel((divisor >> 8) & 0xff, UART1_REG(DLM));
11749 +       writel(0x03, UART1_REG(LCR));
11750 +       writel(0x00, UART1_REG(IER));
11751 +       writel(0x00, UART1_REG(FCR));
11752 +       writel(0x00, UART1_REG(MCR));
11753 +
11754 +       /* send the power-off command 'A' to PIC */
11755 +       writel('A', UART1_REG(TX));
11756 +}
11757 +
11758 +/*****************************************************************************
11759 + * Ethernet
11760 + ****************************************************************************/
11761 +
11762 +struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
11763 +       .phy_addr       = 8,
11764 +};
11765 +
11766 +static int __init qnap_tsx09_parse_hex_nibble(char n)
11767 +{
11768 +       if (n >= '0' && n <= '9')
11769 +               return n - '0';
11770 +
11771 +       if (n >= 'A' && n <= 'F')
11772 +               return n - 'A' + 10;
11773 +
11774 +       if (n >= 'a' && n <= 'f')
11775 +               return n - 'a' + 10;
11776 +
11777 +       return -1;
11778 +}
11779 +
11780 +static int __init qnap_tsx09_parse_hex_byte(const char *b)
11781 +{
11782 +       int hi;
11783 +       int lo;
11784 +
11785 +       hi = qnap_tsx09_parse_hex_nibble(b[0]);
11786 +       lo = qnap_tsx09_parse_hex_nibble(b[1]);
11787 +
11788 +       if (hi < 0 || lo < 0)
11789 +               return -1;
11790 +
11791 +       return (hi << 4) | lo;
11792 +}
11793 +
11794 +static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
11795 +{
11796 +       u_int8_t addr[6];
11797 +       int i;
11798 +
11799 +       for (i = 0; i < 6; i++) {
11800 +               int byte;
11801 +
11802 +               /*
11803 +                * Enforce "xx:xx:xx:xx:xx:xx\n" format.
11804 +                */
11805 +               if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
11806 +                       return -1;
11807 +
11808 +               byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
11809 +               if (byte < 0)
11810 +                       return -1;
11811 +               addr[i] = byte;
11812 +       }
11813 +
11814 +       printk(KERN_INFO "tsx09: found ethernet mac address ");
11815 +       for (i = 0; i < 6; i++)
11816 +               printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
11817 +
11818 +       memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
11819 +
11820 +       return 0;
11821 +}
11822 +
11823 +/*
11824 + * The 'NAS Config' flash partition has an ext2 filesystem which
11825 + * contains a file that has the ethernet MAC address in plain text
11826 + * (format "xx:xx:xx:xx:xx:xx\n").
11827 + */
11828 +void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
11829 +{
11830 +       unsigned long addr;
11831 +
11832 +       for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
11833 +               char *nor_page;
11834 +               int ret = 0;
11835 +
11836 +               nor_page = ioremap(addr, 1024);
11837 +               if (nor_page != NULL) {
11838 +                       ret = qnap_tsx09_check_mac_addr(nor_page);
11839 +                       iounmap(nor_page);
11840 +               }
11841 +
11842 +               if (ret == 0)
11843 +                       break;
11844 +       }
11845 +}
11846 --- /dev/null
11847 +++ b/arch/arm/mach-orion5x/tsx09-common.h
11848 @@ -0,0 +1,20 @@
11849 +#ifndef __ARCH_ORION5X_TSX09_COMMON_H
11850 +#define __ARCH_ORION5X_TSX09_COMMON_H
11851 +
11852 +/*
11853 + * QNAP TS-x09 Boards power-off function
11854 + */
11855 +extern void qnap_tsx09_power_off(void);
11856 +
11857 +/*
11858 + * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
11859 + */
11860 +extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
11861 +
11862 +/*
11863 + * QNAP TS-x09 Boards ethernet declaration
11864 + */
11865 +extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
11866 +
11867 +
11868 +#endif
11869 --- /dev/null
11870 +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
11871 @@ -0,0 +1,173 @@
11872 +/*
11873 + * arch/arm/mach-orion5x/wrt350n-v2-setup.c
11874 + *
11875 + * This file is licensed under the terms of the GNU General Public
11876 + * License version 2.  This program is licensed "as is" without any
11877 + * warranty of any kind, whether express or implied.
11878 + */
11879 +
11880 +#include <linux/kernel.h>
11881 +#include <linux/init.h>
11882 +#include <linux/platform_device.h>
11883 +#include <linux/pci.h>
11884 +#include <linux/irq.h>
11885 +#include <linux/delay.h>
11886 +#include <linux/mtd/physmap.h>
11887 +#include <linux/mv643xx_eth.h>
11888 +#include <asm/mach-types.h>
11889 +#include <asm/gpio.h>
11890 +#include <asm/mach/arch.h>
11891 +#include <asm/mach/pci.h>
11892 +#include <asm/arch/orion5x.h>
11893 +#include "common.h"
11894 +#include "mpp.h"
11895 +
11896 +static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
11897 +       {  0, MPP_GPIO },               /* Power LED green (0=on) */
11898 +       {  1, MPP_GPIO },               /* Security LED (0=on) */
11899 +       {  2, MPP_GPIO },               /* Internal Button (0=on) */
11900 +       {  3, MPP_GPIO },               /* Reset Button (0=on) */
11901 +       {  4, MPP_GPIO },               /* PCI int */
11902 +       {  5, MPP_GPIO },               /* Power LED orange (0=on) */
11903 +       {  6, MPP_GPIO },               /* USB LED (0=on) */
11904 +       {  7, MPP_GPIO },               /* Wireless LED (0=on) */
11905 +       {  8, MPP_UNUSED },             /* ??? */
11906 +       {  9, MPP_GIGE },               /* GE_RXERR */
11907 +       { 10, MPP_UNUSED },             /* ??? */
11908 +       { 11, MPP_UNUSED },             /* ??? */
11909 +       { 12, MPP_GIGE },               /* GE_TXD[4] */
11910 +       { 13, MPP_GIGE },               /* GE_TXD[5] */
11911 +       { 14, MPP_GIGE },               /* GE_TXD[6] */
11912 +       { 15, MPP_GIGE },               /* GE_TXD[7] */
11913 +       { 16, MPP_GIGE },               /* GE_RXD[4] */
11914 +       { 17, MPP_GIGE },               /* GE_RXD[5] */
11915 +       { 18, MPP_GIGE },               /* GE_RXD[6] */
11916 +       { 19, MPP_GIGE },               /* GE_RXD[7] */
11917 +       { -1 },
11918 +};
11919 +
11920 +/*
11921 + * 8M NOR flash Device bus boot chip select
11922 + */
11923 +#define WRT350N_V2_NOR_BOOT_BASE       0xf4000000
11924 +#define WRT350N_V2_NOR_BOOT_SIZE       SZ_8M
11925 +
11926 +static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
11927 +       {
11928 +               .name           = "kernel",
11929 +               .offset         = 0x00000000,
11930 +               .size           = 0x00760000,
11931 +       }, {
11932 +               .name           = "rootfs",
11933 +               .offset         = 0x001a0000,
11934 +               .size           = 0x005c0000,
11935 +       }, {
11936 +               .name           = "lang",
11937 +               .offset         = 0x00760000,
11938 +               .size           = 0x00040000,
11939 +       }, {
11940 +               .name           = "nvram",
11941 +               .offset         = 0x007a0000,
11942 +               .size           = 0x00020000,
11943 +       }, {
11944 +               .name           = "u-boot",
11945 +               .offset         = 0x007c0000,
11946 +               .size           = 0x00040000,
11947 +       },
11948 +};
11949 +
11950 +static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
11951 +       .width          = 1,
11952 +       .parts          = wrt350n_v2_nor_flash_partitions,
11953 +       .nr_parts       = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
11954 +};
11955 +
11956 +static struct resource wrt350n_v2_nor_flash_resource = {
11957 +       .flags          = IORESOURCE_MEM,
11958 +       .start          = WRT350N_V2_NOR_BOOT_BASE,
11959 +       .end            = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
11960 +};
11961 +
11962 +static struct platform_device wrt350n_v2_nor_flash = {
11963 +       .name                   = "physmap-flash",
11964 +       .id                     = 0,
11965 +       .dev            = {
11966 +               .platform_data  = &wrt350n_v2_nor_flash_data,
11967 +       },
11968 +       .num_resources          = 1,
11969 +       .resource               = &wrt350n_v2_nor_flash_resource,
11970 +};
11971 +
11972 +static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
11973 +       .phy_addr       = -1,
11974 +};
11975 +
11976 +static void __init wrt350n_v2_init(void)
11977 +{
11978 +       /*
11979 +        * Setup basic Orion functions. Need to be called early.
11980 +        */
11981 +       orion5x_init();
11982 +
11983 +       orion5x_mpp_conf(wrt350n_v2_mpp_modes);
11984 +
11985 +       /*
11986 +        * Configure peripherals.
11987 +        */
11988 +       orion5x_ehci0_init();
11989 +       orion5x_eth_init(&wrt350n_v2_eth_data);
11990 +       orion5x_uart0_init();
11991 +
11992 +       orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
11993 +                                  WRT350N_V2_NOR_BOOT_SIZE);
11994 +       platform_device_register(&wrt350n_v2_nor_flash);
11995 +}
11996 +
11997 +static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11998 +{
11999 +       int irq;
12000 +
12001 +       /*
12002 +        * Check for devices with hard-wired IRQs.
12003 +        */
12004 +       irq = orion5x_pci_map_irq(dev, slot, pin);
12005 +       if (irq != -1)
12006 +               return irq;
12007 +
12008 +       /*
12009 +        * Mini-PCI slot.
12010 +        */
12011 +       if (slot == 7)
12012 +               return gpio_to_irq(4);
12013 +
12014 +       return -1;
12015 +}
12016 +
12017 +static struct hw_pci wrt350n_v2_pci __initdata = {
12018 +       .nr_controllers = 2,
12019 +       .swizzle        = pci_std_swizzle,
12020 +       .setup          = orion5x_pci_sys_setup,
12021 +       .scan           = orion5x_pci_sys_scan_bus,
12022 +       .map_irq        = wrt350n_v2_pci_map_irq,
12023 +};
12024 +
12025 +static int __init wrt350n_v2_pci_init(void)
12026 +{
12027 +       if (machine_is_wrt350n_v2())
12028 +               pci_common_init(&wrt350n_v2_pci);
12029 +
12030 +       return 0;
12031 +}
12032 +subsys_initcall(wrt350n_v2_pci_init);
12033 +
12034 +MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
12035 +       /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
12036 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
12037 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
12038 +       .boot_params    = 0x00000100,
12039 +       .init_machine   = wrt350n_v2_init,
12040 +       .map_io         = orion5x_map_io,
12041 +       .init_irq       = orion5x_init_irq,
12042 +       .timer          = &orion5x_timer,
12043 +       .fixup          = tag_fixup_mem32,
12044 +MACHINE_END
12045 --- a/arch/arm/mm/Kconfig
12046 +++ b/arch/arm/mm/Kconfig
12047 @@ -365,7 +365,7 @@
12048  # Feroceon
12049  config CPU_FEROCEON
12050         bool
12051 -       depends on ARCH_ORION5X
12052 +       depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
12053         default y
12054         select CPU_32v5
12055         select CPU_ABRT_EV5T
12056 @@ -373,7 +373,7 @@
12057         select CPU_CACHE_VIVT
12058         select CPU_CP15_MMU
12059         select CPU_COPY_FEROCEON if MMU
12060 -       select CPU_TLB_V4WBI if MMU
12061 +       select CPU_TLB_FEROCEON if MMU
12062
12063  config CPU_FEROCEON_OLD_ID
12064         bool "Accept early Feroceon cores with an ARM926 ID"
12065 @@ -551,6 +551,11 @@
12066           ARM Architecture Version 4 TLB with writeback cache and invalidate
12067           instruction cache entry.
12068
12069 +config CPU_TLB_FEROCEON
12070 +       bool
12071 +       help
12072 +         Feroceon TLB (v4wbi with non-outer-cachable page table walks).
12073 +
12074  config CPU_TLB_V6
12075         bool
12076
12077 @@ -709,6 +714,14 @@
12078         bool
12079         default n
12080
12081 +config CACHE_FEROCEON_L2
12082 +       bool "Enable the Feroceon L2 cache controller"
12083 +       depends on ARCH_KIRKWOOD || ARCH_MV78XX0
12084 +       default y
12085 +       select OUTER_CACHE
12086 +       help
12087 +         This option enables the Feroceon L2 cache controller.
12088 +
12089  config CACHE_L2X0
12090         bool "Enable the L2x0 outer cache controller"
12091         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
12092 --- a/arch/arm/mm/Makefile
12093 +++ b/arch/arm/mm/Makefile
12094 @@ -46,6 +46,7 @@
12095  obj-$(CONFIG_CPU_TLB_V4WT)     += tlb-v4.o
12096  obj-$(CONFIG_CPU_TLB_V4WB)     += tlb-v4wb.o
12097  obj-$(CONFIG_CPU_TLB_V4WBI)    += tlb-v4wbi.o
12098 +obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o  # reuse v4wbi TLB functions
12099  obj-$(CONFIG_CPU_TLB_V6)       += tlb-v6.o
12100  obj-$(CONFIG_CPU_TLB_V7)       += tlb-v7.o
12101
12102 @@ -73,4 +74,5 @@
12103  obj-$(CONFIG_CPU_V6)           += proc-v6.o
12104  obj-$(CONFIG_CPU_V7)           += proc-v7.o
12105
12106 +obj-$(CONFIG_CACHE_FEROCEON_L2)        += cache-feroceon-l2.o
12107  obj-$(CONFIG_CACHE_L2X0)       += cache-l2x0.o
12108 --- /dev/null
12109 +++ b/arch/arm/mm/cache-feroceon-l2.c
12110 @@ -0,0 +1,318 @@
12111 +/*
12112 + * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
12113 + *
12114 + * Copyright (C) 2008 Marvell Semiconductor
12115 + *
12116 + * This file is licensed under the terms of the GNU General Public
12117 + * License version 2.  This program is licensed "as is" without any
12118 + * warranty of any kind, whether express or implied.
12119 + *
12120 + * References:
12121 + * - Unified Layer 2 Cache for Feroceon CPU Cores,
12122 + *   Document ID MV-S104858-00, Rev. A, October 23 2007.
12123 + */
12124 +
12125 +#include <linux/init.h>
12126 +#include <asm/cacheflush.h>
12127 +#include <asm/plat-orion/cache-feroceon-l2.h>
12128 +
12129 +
12130 +/*
12131 + * Low-level cache maintenance operations.
12132 + *
12133 + * As well as the regular 'clean/invalidate/flush L2 cache line by
12134 + * MVA' instructions, the Feroceon L2 cache controller also features
12135 + * 'clean/invalidate L2 range by MVA' operations.
12136 + *
12137 + * Cache range operations are initiated by writing the start and
12138 + * end addresses to successive cp15 registers, and process every
12139 + * cache line whose first byte address lies in the inclusive range
12140 + * [start:end].
12141 + *
12142 + * The cache range operations stall the CPU pipeline until completion.
12143 + *
12144 + * The range operations require two successive cp15 writes, in
12145 + * between which we don't want to be preempted.
12146 + */
12147 +static inline void l2_clean_pa(unsigned long addr)
12148 +{
12149 +       __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
12150 +}
12151 +
12152 +static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
12153 +{
12154 +       unsigned long flags;
12155 +
12156 +       /*
12157 +        * Make sure 'start' and 'end' reference the same page, as
12158 +        * L2 is PIPT and range operations only do a TLB lookup on
12159 +        * the start address.
12160 +        */
12161 +       BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
12162 +
12163 +       raw_local_irq_save(flags);
12164 +       __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
12165 +       __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
12166 +       raw_local_irq_restore(flags);
12167 +}
12168 +
12169 +static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
12170 +{
12171 +       l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
12172 +}
12173 +
12174 +static inline void l2_clean_inv_pa(unsigned long addr)
12175 +{
12176 +       __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
12177 +}
12178 +
12179 +static inline void l2_inv_pa(unsigned long addr)
12180 +{
12181 +       __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
12182 +}
12183 +
12184 +static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
12185 +{
12186 +       unsigned long flags;
12187 +
12188 +       /*
12189 +        * Make sure 'start' and 'end' reference the same page, as
12190 +        * L2 is PIPT and range operations only do a TLB lookup on
12191 +        * the start address.
12192 +        */
12193 +       BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
12194 +
12195 +       raw_local_irq_save(flags);
12196 +       __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
12197 +       __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
12198 +       raw_local_irq_restore(flags);
12199 +}
12200 +
12201 +static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
12202 +{
12203 +       l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
12204 +}
12205 +
12206 +
12207 +/*
12208 + * Linux primitives.
12209 + *
12210 + * Note that the end addresses passed to Linux primitives are
12211 + * noninclusive, while the hardware cache range operations use
12212 + * inclusive start and end addresses.
12213 + */
12214 +#define CACHE_LINE_SIZE                32
12215 +#define MAX_RANGE_SIZE         1024
12216 +
12217 +static int l2_wt_override;
12218 +
12219 +static unsigned long calc_range_end(unsigned long start, unsigned long end)
12220 +{
12221 +       unsigned long range_end;
12222 +
12223 +       BUG_ON(start & (CACHE_LINE_SIZE - 1));
12224 +       BUG_ON(end & (CACHE_LINE_SIZE - 1));
12225 +
12226 +       /*
12227 +        * Try to process all cache lines between 'start' and 'end'.
12228 +        */
12229 +       range_end = end;
12230 +
12231 +       /*
12232 +        * Limit the number of cache lines processed at once,
12233 +        * since cache range operations stall the CPU pipeline
12234 +        * until completion.
12235 +        */
12236 +       if (range_end > start + MAX_RANGE_SIZE)
12237 +               range_end = start + MAX_RANGE_SIZE;
12238 +
12239 +       /*
12240 +        * Cache range operations can't straddle a page boundary.
12241 +        */
12242 +       if (range_end > (start | (PAGE_SIZE - 1)) + 1)
12243 +               range_end = (start | (PAGE_SIZE - 1)) + 1;
12244 +
12245 +       return range_end;
12246 +}
12247 +
12248 +static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
12249 +{
12250 +       /*
12251 +        * Clean and invalidate partial first cache line.
12252 +        */
12253 +       if (start & (CACHE_LINE_SIZE - 1)) {
12254 +               l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
12255 +               start = (start | (CACHE_LINE_SIZE - 1)) + 1;
12256 +       }
12257 +
12258 +       /*
12259 +        * Clean and invalidate partial last cache line.
12260 +        */
12261 +       if (end & (CACHE_LINE_SIZE - 1)) {
12262 +               l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
12263 +               end &= ~(CACHE_LINE_SIZE - 1);
12264 +       }
12265 +
12266 +       /*
12267 +        * Invalidate all full cache lines between 'start' and 'end'.
12268 +        */
12269 +       while (start != end) {
12270 +               unsigned long range_end = calc_range_end(start, end);
12271 +               l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
12272 +               start = range_end;
12273 +       }
12274 +
12275 +       dsb();
12276 +}
12277 +
12278 +static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
12279 +{
12280 +       /*
12281 +        * If L2 is forced to WT, the L2 will always be clean and we
12282 +        * don't need to do anything here.
12283 +        */
12284 +       if (!l2_wt_override) {
12285 +               start &= ~(CACHE_LINE_SIZE - 1);
12286 +               end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
12287 +               while (start != end) {
12288 +                       unsigned long range_end = calc_range_end(start, end);
12289 +                       l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
12290 +                       start = range_end;
12291 +               }
12292 +       }
12293 +
12294 +       dsb();
12295 +}
12296 +
12297 +static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
12298 +{
12299 +       start &= ~(CACHE_LINE_SIZE - 1);
12300 +       end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
12301 +       while (start != end) {
12302 +               unsigned long range_end = calc_range_end(start, end);
12303 +               if (!l2_wt_override)
12304 +                       l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
12305 +               l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
12306 +               start = range_end;
12307 +       }
12308 +
12309 +       dsb();
12310 +}
12311 +
12312 +
12313 +/*
12314 + * Routines to disable and re-enable the D-cache and I-cache at run
12315 + * time.  These are necessary because the L2 cache can only be enabled
12316 + * or disabled while the L1 Dcache and Icache are both disabled.
12317 + */
12318 +static void __init invalidate_and_disable_dcache(void)
12319 +{
12320 +       u32 cr;
12321 +
12322 +       cr = get_cr();
12323 +       if (cr & CR_C) {
12324 +               unsigned long flags;
12325 +
12326 +               raw_local_irq_save(flags);
12327 +               flush_cache_all();
12328 +               set_cr(cr & ~CR_C);
12329 +               raw_local_irq_restore(flags);
12330 +       }
12331 +}
12332 +
12333 +static void __init enable_dcache(void)
12334 +{
12335 +       u32 cr;
12336 +
12337 +       cr = get_cr();
12338 +       if (!(cr & CR_C))
12339 +               set_cr(cr | CR_C);
12340 +}
12341 +
12342 +static void __init __invalidate_icache(void)
12343 +{
12344 +       int dummy;
12345 +
12346 +       __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
12347 +}
12348 +
12349 +static void __init invalidate_and_disable_icache(void)
12350 +{
12351 +       u32 cr;
12352 +
12353 +       cr = get_cr();
12354 +       if (cr & CR_I) {
12355 +               set_cr(cr & ~CR_I);
12356 +               __invalidate_icache();
12357 +       }
12358 +}
12359 +
12360 +static void __init enable_icache(void)
12361 +{
12362 +       u32 cr;
12363 +
12364 +       cr = get_cr();
12365 +       if (!(cr & CR_I))
12366 +               set_cr(cr | CR_I);
12367 +}
12368 +
12369 +static inline u32 read_extra_features(void)
12370 +{
12371 +       u32 u;
12372 +
12373 +       __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
12374 +
12375 +       return u;
12376 +}
12377 +
12378 +static inline void write_extra_features(u32 u)
12379 +{
12380 +       __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
12381 +}
12382 +
12383 +static void __init disable_l2_prefetch(void)
12384 +{
12385 +       u32 u;
12386 +
12387 +       /*
12388 +        * Read the CPU Extra Features register and verify that the
12389 +        * Disable L2 Prefetch bit is set.
12390 +        */
12391 +       u = read_extra_features();
12392 +       if (!(u & 0x01000000)) {
12393 +               printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
12394 +               write_extra_features(u | 0x01000000);
12395 +       }
12396 +}
12397 +
12398 +static void __init enable_l2(void)
12399 +{
12400 +       u32 u;
12401 +
12402 +       u = read_extra_features();
12403 +       if (!(u & 0x00400000)) {
12404 +               printk(KERN_INFO "Feroceon L2: Enabling L2\n");
12405 +
12406 +               invalidate_and_disable_dcache();
12407 +               invalidate_and_disable_icache();
12408 +               write_extra_features(u | 0x00400000);
12409 +               enable_icache();
12410 +               enable_dcache();
12411 +       }
12412 +}
12413 +
12414 +void __init feroceon_l2_init(int __l2_wt_override)
12415 +{
12416 +       l2_wt_override = __l2_wt_override;
12417 +
12418 +       disable_l2_prefetch();
12419 +
12420 +       outer_cache.inv_range = feroceon_l2_inv_range;
12421 +       outer_cache.clean_range = feroceon_l2_clean_range;
12422 +       outer_cache.flush_range = feroceon_l2_flush_range;
12423 +
12424 +       enable_l2();
12425 +
12426 +       printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
12427 +                        l2_wt_override ? ", in WT override mode" : "");
12428 +}
12429 --- a/arch/arm/mm/proc-feroceon.S
12430 +++ b/arch/arm/mm/proc-feroceon.S
12431 @@ -44,11 +44,31 @@
12432   */
12433  #define CACHE_DLINESIZE        32
12434
12435 +       .bss
12436 +       .align 3
12437 +__cache_params_loc:
12438 +       .space  8
12439 +
12440         .text
12441 +__cache_params:
12442 +       .word   __cache_params_loc
12443 +
12444  /*
12445   * cpu_feroceon_proc_init()
12446   */
12447  ENTRY(cpu_feroceon_proc_init)
12448 +       mrc     p15, 0, r0, c0, c0, 1           @ read cache type register
12449 +       ldr     r1, __cache_params
12450 +       mov     r2, #(16 << 5)
12451 +       tst     r0, #(1 << 16)                  @ get way
12452 +       mov     r0, r0, lsr #18                 @ get cache size order
12453 +       movne   r3, #((4 - 1) << 30)            @ 4-way
12454 +       and     r0, r0, #0xf
12455 +       moveq   r3, #0                          @ 1-way
12456 +       mov     r2, r2, lsl r0                  @ actual cache size
12457 +       movne   r2, r2, lsr #2                  @ turned into # of sets
12458 +       sub     r2, r2, #(1 << 5)
12459 +       stmia   r1, {r2, r3}
12460         mov     pc, lr
12461
12462  /*
12463 @@ -59,6 +79,13 @@
12464         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
12465         msr     cpsr_c, ip
12466         bl      feroceon_flush_kern_cache_all
12467 +
12468 +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
12469 +       mov     r0, #0
12470 +       mcr     p15, 1, r0, c15, c9, 0          @ clean L2
12471 +       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12472 +#endif
12473 +
12474         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
12475         bic     r0, r0, #0x1000                 @ ...i............
12476         bic     r0, r0, #0x000e                 @ ............wca.
12477 @@ -117,11 +144,19 @@
12478   */
12479  ENTRY(feroceon_flush_kern_cache_all)
12480         mov     r2, #VM_EXEC
12481 -       mov     ip, #0
12482 +
12483  __flush_whole_cache:
12484 -1:     mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
12485 -       bne     1b
12486 +       ldr     r1, __cache_params
12487 +       ldmia   r1, {r1, r3}
12488 +1:     orr     ip, r1, r3
12489 +2:     mcr     p15, 0, ip, c7, c14, 2          @ clean + invalidate D set/way
12490 +       subs    ip, ip, #(1 << 30)              @ next way
12491 +       bcs     2b
12492 +       subs    r1, r1, #(1 << 5)               @ next set
12493 +       bcs     1b
12494 +
12495         tst     r2, #VM_EXEC
12496 +       mov     ip, #0
12497         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
12498         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
12499         mov     pc, lr
12500 @@ -138,7 +173,6 @@
12501   */
12502         .align  5
12503  ENTRY(feroceon_flush_user_cache_range)
12504 -       mov     ip, #0
12505         sub     r3, r1, r0                      @ calculate total size
12506         cmp     r3, #CACHE_DLIMIT
12507         bgt     __flush_whole_cache
12508 @@ -152,6 +186,7 @@
12509         cmp     r0, r1
12510         blo     1b
12511         tst     r2, #VM_EXEC
12512 +       mov     ip, #0
12513         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
12514         mov     pc, lr
12515
12516 @@ -209,6 +244,20 @@
12517         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12518         mov     pc, lr
12519
12520 +       .align  5
12521 +ENTRY(feroceon_range_flush_kern_dcache_page)
12522 +       mrs     r2, cpsr
12523 +       add     r1, r0, #PAGE_SZ - CACHE_DLINESIZE      @ top addr is inclusive
12524 +       orr     r3, r2, #PSR_I_BIT
12525 +       msr     cpsr_c, r3                      @ disable interrupts
12526 +       mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
12527 +       mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
12528 +       msr     cpsr_c, r2                      @ restore interrupts
12529 +       mov     r0, #0
12530 +       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
12531 +       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12532 +       mov     pc, lr
12533 +
12534  /*
12535   *     dma_inv_range(start, end)
12536   *
12537 @@ -225,10 +274,10 @@
12538         .align  5
12539  ENTRY(feroceon_dma_inv_range)
12540         tst     r0, #CACHE_DLINESIZE - 1
12541 +       bic     r0, r0, #CACHE_DLINESIZE - 1
12542         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
12543         tst     r1, #CACHE_DLINESIZE - 1
12544         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
12545 -       bic     r0, r0, #CACHE_DLINESIZE - 1
12546  1:     mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
12547         add     r0, r0, #CACHE_DLINESIZE
12548         cmp     r0, r1
12549 @@ -236,6 +285,22 @@
12550         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12551         mov     pc, lr
12552
12553 +       .align  5
12554 +ENTRY(feroceon_range_dma_inv_range)
12555 +       mrs     r2, cpsr
12556 +       tst     r0, #CACHE_DLINESIZE - 1
12557 +       mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
12558 +       tst     r1, #CACHE_DLINESIZE - 1
12559 +       mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
12560 +       cmp     r1, r0
12561 +       subne   r1, r1, #1                      @ top address is inclusive
12562 +       orr     r3, r2, #PSR_I_BIT
12563 +       msr     cpsr_c, r3                      @ disable interrupts
12564 +       mcr     p15, 5, r0, c15, c14, 0         @ D inv range start
12565 +       mcr     p15, 5, r1, c15, c14, 1         @ D inv range top
12566 +       msr     cpsr_c, r2                      @ restore interrupts
12567 +       mov     pc, lr
12568 +
12569  /*
12570   *     dma_clean_range(start, end)
12571   *
12572 @@ -256,6 +321,19 @@
12573         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12574         mov     pc, lr
12575
12576 +       .align  5
12577 +ENTRY(feroceon_range_dma_clean_range)
12578 +       mrs     r2, cpsr
12579 +       cmp     r1, r0
12580 +       subne   r1, r1, #1                      @ top address is inclusive
12581 +       orr     r3, r2, #PSR_I_BIT
12582 +       msr     cpsr_c, r3                      @ disable interrupts
12583 +       mcr     p15, 5, r0, c15, c13, 0         @ D clean range start
12584 +       mcr     p15, 5, r1, c15, c13, 1         @ D clean range top
12585 +       msr     cpsr_c, r2                      @ restore interrupts
12586 +       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12587 +       mov     pc, lr
12588 +
12589  /*
12590   *     dma_flush_range(start, end)
12591   *
12592 @@ -274,6 +352,19 @@
12593         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12594         mov     pc, lr
12595
12596 +       .align  5
12597 +ENTRY(feroceon_range_dma_flush_range)
12598 +       mrs     r2, cpsr
12599 +       cmp     r1, r0
12600 +       subne   r1, r1, #1                      @ top address is inclusive
12601 +       orr     r3, r2, #PSR_I_BIT
12602 +       msr     cpsr_c, r3                      @ disable interrupts
12603 +       mcr     p15, 5, r0, c15, c15, 0         @ D clean/inv range start
12604 +       mcr     p15, 5, r1, c15, c15, 1         @ D clean/inv range top
12605 +       msr     cpsr_c, r2                      @ restore interrupts
12606 +       mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12607 +       mov     pc, lr
12608 +
12609  ENTRY(feroceon_cache_fns)
12610         .long   feroceon_flush_kern_cache_all
12611         .long   feroceon_flush_user_cache_all
12612 @@ -285,12 +376,33 @@
12613         .long   feroceon_dma_clean_range
12614         .long   feroceon_dma_flush_range
12615
12616 +ENTRY(feroceon_range_cache_fns)
12617 +       .long   feroceon_flush_kern_cache_all
12618 +       .long   feroceon_flush_user_cache_all
12619 +       .long   feroceon_flush_user_cache_range
12620 +       .long   feroceon_coherent_kern_range
12621 +       .long   feroceon_coherent_user_range
12622 +       .long   feroceon_range_flush_kern_dcache_page
12623 +       .long   feroceon_range_dma_inv_range
12624 +       .long   feroceon_range_dma_clean_range
12625 +       .long   feroceon_range_dma_flush_range
12626 +
12627         .align  5
12628  ENTRY(cpu_feroceon_dcache_clean_area)
12629 +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
12630 +       mov     r2, r0
12631 +       mov     r3, r1
12632 +#endif
12633  1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
12634         add     r0, r0, #CACHE_DLINESIZE
12635         subs    r1, r1, #CACHE_DLINESIZE
12636         bhi     1b
12637 +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
12638 +1:     mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
12639 +       add     r2, r2, #CACHE_DLINESIZE
12640 +       subs    r3, r3, #CACHE_DLINESIZE
12641 +       bhi     1b
12642 +#endif
12643         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12644         mov     pc, lr
12645
12646 @@ -306,16 +418,25 @@
12647         .align  5
12648  ENTRY(cpu_feroceon_switch_mm)
12649  #ifdef CONFIG_MMU
12650 -       mov     ip, #0
12651 -@ && 'Clean & Invalidate whole DCache'
12652 -1:     mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
12653 -       bne     1b
12654 -       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
12655 -       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
12656 +       /*
12657 +        * Note: we wish to call __flush_whole_cache but we need to preserve
12658 +        * lr to do so.  The only way without touching main memory is to
12659 +        * use r2 which is normally used to test the VM_EXEC flag, and
12660 +        * compensate locally for the skipped ops if it is not set.
12661 +        */
12662 +       mov     r2, lr                          @ abuse r2 to preserve lr
12663 +       bl      __flush_whole_cache
12664 +       @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
12665 +       tst     r2, #VM_EXEC
12666 +       mcreq   p15, 0, ip, c7, c5, 0           @ invalidate I cache
12667 +       mcreq   p15, 0, ip, c7, c10, 4          @ drain WB
12668 +
12669         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
12670         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
12671 -#endif
12672 +       mov     pc, r2
12673 +#else
12674         mov     pc, lr
12675 +#endif
12676
12677  /*
12678   * cpu_feroceon_set_pte_ext(ptep, pte, ext)
12679 @@ -345,6 +466,9 @@
12680         str     r2, [r0]                        @ hardware version
12681         mov     r0, r0
12682         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
12683 +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
12684 +       mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
12685 +#endif
12686         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
12687  #endif
12688         mov     pc, lr
12689 @@ -414,6 +538,21 @@
12690         .asciz  "Feroceon"
12691         .size   cpu_feroceon_name, . - cpu_feroceon_name
12692
12693 +       .type   cpu_88fr531_name, #object
12694 +cpu_88fr531_name:
12695 +       .asciz  "Feroceon 88FR531-vd"
12696 +       .size   cpu_88fr531_name, . - cpu_88fr531_name
12697 +
12698 +       .type   cpu_88fr571_name, #object
12699 +cpu_88fr571_name:
12700 +       .asciz  "Feroceon 88FR571-vd"
12701 +       .size   cpu_88fr571_name, . - cpu_88fr571_name
12702 +
12703 +       .type   cpu_88fr131_name, #object
12704 +cpu_88fr131_name:
12705 +       .asciz  "Feroceon 88FR131"
12706 +       .size   cpu_88fr131_name, . - cpu_88fr131_name
12707 +
12708         .align
12709
12710         .section ".proc.info.init", #alloc, #execinstr
12711 @@ -421,15 +560,15 @@
12712  #ifdef CONFIG_CPU_FEROCEON_OLD_ID
12713         .type   __feroceon_old_id_proc_info,#object
12714  __feroceon_old_id_proc_info:
12715 -       .long   0x41069260
12716 -       .long   0xfffffff0
12717 -       .long   PMD_TYPE_SECT | \
12718 +       .long   0x41009260
12719 +       .long   0xff00fff0
12720 +       .long   PMD_TYPE_SECT | \
12721                 PMD_SECT_BUFFERABLE | \
12722                 PMD_SECT_CACHEABLE | \
12723                 PMD_BIT4 | \
12724                 PMD_SECT_AP_WRITE | \
12725                 PMD_SECT_AP_READ
12726 -       .long   PMD_TYPE_SECT | \
12727 +       .long   PMD_TYPE_SECT | \
12728                 PMD_BIT4 | \
12729                 PMD_SECT_AP_WRITE | \
12730                 PMD_SECT_AP_READ
12731 @@ -445,17 +584,17 @@
12732         .size   __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
12733  #endif
12734
12735 -       .type   __feroceon_proc_info,#object
12736 -__feroceon_proc_info:
12737 +       .type   __88fr531_proc_info,#object
12738 +__88fr531_proc_info:
12739         .long   0x56055310
12740         .long   0xfffffff0
12741 -       .long   PMD_TYPE_SECT | \
12742 +       .long   PMD_TYPE_SECT | \
12743                 PMD_SECT_BUFFERABLE | \
12744                 PMD_SECT_CACHEABLE | \
12745                 PMD_BIT4 | \
12746                 PMD_SECT_AP_WRITE | \
12747                 PMD_SECT_AP_READ
12748 -       .long   PMD_TYPE_SECT | \
12749 +       .long   PMD_TYPE_SECT | \
12750                 PMD_BIT4 | \
12751                 PMD_SECT_AP_WRITE | \
12752                 PMD_SECT_AP_READ
12753 @@ -463,9 +602,59 @@
12754         .long   cpu_arch_name
12755         .long   cpu_elf_name
12756         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
12757 -       .long   cpu_feroceon_name
12758 +       .long   cpu_88fr531_name
12759         .long   feroceon_processor_functions
12760         .long   v4wbi_tlb_fns
12761         .long   feroceon_user_fns
12762         .long   feroceon_cache_fns
12763 -       .size   __feroceon_proc_info, . - __feroceon_proc_info
12764 +       .size   __88fr531_proc_info, . - __88fr531_proc_info
12765 +
12766 +       .type   __88fr571_proc_info,#object
12767 +__88fr571_proc_info:
12768 +       .long   0x56155710
12769 +       .long   0xfffffff0
12770 +       .long   PMD_TYPE_SECT | \
12771 +               PMD_SECT_BUFFERABLE | \
12772 +               PMD_SECT_CACHEABLE | \
12773 +               PMD_BIT4 | \
12774 +               PMD_SECT_AP_WRITE | \
12775 +               PMD_SECT_AP_READ
12776 +       .long   PMD_TYPE_SECT | \
12777 +               PMD_BIT4 | \
12778 +               PMD_SECT_AP_WRITE | \
12779 +               PMD_SECT_AP_READ
12780 +       b       __feroceon_setup
12781 +       .long   cpu_arch_name
12782 +       .long   cpu_elf_name
12783 +       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
12784 +       .long   cpu_88fr571_name
12785 +       .long   feroceon_processor_functions
12786 +       .long   v4wbi_tlb_fns
12787 +       .long   feroceon_user_fns
12788 +       .long   feroceon_range_cache_fns
12789 +       .size   __88fr571_proc_info, . - __88fr571_proc_info
12790 +
12791 +       .type   __88fr131_proc_info,#object
12792 +__88fr131_proc_info:
12793 +       .long   0x56251310
12794 +       .long   0xfffffff0
12795 +       .long   PMD_TYPE_SECT | \
12796 +               PMD_SECT_BUFFERABLE | \
12797 +               PMD_SECT_CACHEABLE | \
12798 +               PMD_BIT4 | \
12799 +               PMD_SECT_AP_WRITE | \
12800 +               PMD_SECT_AP_READ
12801 +       .long   PMD_TYPE_SECT | \
12802 +               PMD_BIT4 | \
12803 +               PMD_SECT_AP_WRITE | \
12804 +               PMD_SECT_AP_READ
12805 +       b       __feroceon_setup
12806 +       .long   cpu_arch_name
12807 +       .long   cpu_elf_name
12808 +       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
12809 +       .long   cpu_88fr131_name
12810 +       .long   feroceon_processor_functions
12811 +       .long   v4wbi_tlb_fns
12812 +       .long   feroceon_user_fns
12813 +       .long   feroceon_range_cache_fns
12814 +       .size   __88fr131_proc_info, . - __88fr131_proc_info
12815 --- a/arch/arm/plat-orion/irq.c
12816 +++ b/arch/arm/plat-orion/irq.c
12817 @@ -36,8 +36,8 @@
12818
12819  static struct irq_chip orion_irq_chip = {
12820         .name           = "orion_irq",
12821 -       .ack            = orion_irq_mask,
12822         .mask           = orion_irq_mask,
12823 +       .mask_ack       = orion_irq_mask,
12824         .unmask         = orion_irq_unmask,
12825  };
12826
12827 @@ -59,6 +59,7 @@
12828                 set_irq_chip(irq, &orion_irq_chip);
12829                 set_irq_chip_data(irq, maskaddr);
12830                 set_irq_handler(irq, handle_level_irq);
12831 +               irq_desc[irq].status |= IRQ_LEVEL;
12832                 set_irq_flags(irq, IRQF_VALID);
12833         }
12834  }
12835 --- a/arch/arm/plat-orion/pcie.c
12836 +++ b/arch/arm/plat-orion/pcie.c
12837 @@ -39,6 +39,7 @@
12838  #define PCIE_CONF_DATA_OFF     0x18fc
12839  #define PCIE_MASK_OFF          0x1910
12840  #define PCIE_CTRL_OFF          0x1a00
12841 +#define  PCIE_CTRL_X1_MODE             0x0001
12842  #define PCIE_STAT_OFF          0x1a04
12843  #define  PCIE_STAT_DEV_OFFS            20
12844  #define  PCIE_STAT_DEV_MASK            0x1f
12845 @@ -62,6 +63,11 @@
12846         return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
12847  }
12848
12849 +int __init orion_pcie_x4_mode(void __iomem *base)
12850 +{
12851 +       return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
12852 +}
12853 +
12854  int orion_pcie_get_local_bus_nr(void __iomem *base)
12855  {
12856         u32 stat = readl(base + PCIE_STAT_OFF);
12857 --- a/arch/arm/plat-orion/time.c
12858 +++ b/arch/arm/plat-orion/time.c
12859 @@ -74,7 +74,7 @@
12860         /*
12861          * Clear and enable clockevent timer interrupt.
12862          */
12863 -       writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
12864 +       writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
12865
12866         u = readl(BRIDGE_MASK);
12867         u |= BRIDGE_INT_TIMER1;
12868 @@ -138,7 +138,7 @@
12869                 /*
12870                  * ACK pending timer interrupt.
12871                  */
12872 -               writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
12873 +               writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
12874
12875         }
12876         local_irq_restore(flags);
12877 @@ -159,7 +159,7 @@
12878         /*
12879          * ACK timer interrupt and call event handler.
12880          */
12881 -       writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
12882 +       writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
12883         orion_clkevt.event_handler(&orion_clkevt);
12884
12885         return IRQ_HANDLED;
12886 --- a/drivers/net/mv643xx_eth.c
12887 +++ b/drivers/net/mv643xx_eth.c
12888 @@ -34,406 +34,145 @@
12889   * along with this program; if not, write to the Free Software
12890   * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
12891   */
12892 +
12893  #include <linux/init.h>
12894  #include <linux/dma-mapping.h>
12895  #include <linux/in.h>
12896 -#include <linux/ip.h>
12897  #include <linux/tcp.h>
12898  #include <linux/udp.h>
12899  #include <linux/etherdevice.h>
12900 -
12901 -#include <linux/bitops.h>
12902  #include <linux/delay.h>
12903  #include <linux/ethtool.h>
12904  #include <linux/platform_device.h>
12905 -
12906  #include <linux/module.h>
12907  #include <linux/kernel.h>
12908  #include <linux/spinlock.h>
12909  #include <linux/workqueue.h>
12910  #include <linux/mii.h>
12911 -
12912  #include <linux/mv643xx_eth.h>
12913 -
12914  #include <asm/io.h>
12915  #include <asm/types.h>
12916 -#include <asm/pgtable.h>
12917  #include <asm/system.h>
12918 -#include <asm/delay.h>
12919 -#include <asm/dma-mapping.h>
12920
12921 -#define MV643XX_CHECKSUM_OFFLOAD_TX
12922 -#define MV643XX_NAPI
12923 -#define MV643XX_TX_FAST_REFILL
12924 -#undef MV643XX_COAL
12925 -
12926 -#define MV643XX_TX_COAL 100
12927 -#ifdef MV643XX_COAL
12928 -#define MV643XX_RX_COAL 100
12929 -#endif
12930 +static char mv643xx_eth_driver_name[] = "mv643xx_eth";
12931 +static char mv643xx_eth_driver_version[] = "1.1";
12932
12933 -#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
12934 +#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
12935 +#define MV643XX_ETH_NAPI
12936 +#define MV643XX_ETH_TX_FAST_REFILL
12937 +
12938 +#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
12939  #define MAX_DESCS_PER_SKB      (MAX_SKB_FRAGS + 1)
12940  #else
12941  #define MAX_DESCS_PER_SKB      1
12942  #endif
12943
12944 -#define ETH_VLAN_HLEN          4
12945 -#define ETH_FCS_LEN            4
12946 -#define ETH_HW_IP_ALIGN                2               /* hw aligns IP header */
12947 -#define ETH_WRAPPER_LEN                (ETH_HW_IP_ALIGN + ETH_HLEN + \
12948 -                                       ETH_VLAN_HLEN + ETH_FCS_LEN)
12949 -#define ETH_RX_SKB_SIZE                (dev->mtu + ETH_WRAPPER_LEN + \
12950 -                                       dma_get_cache_alignment())
12951 -
12952  /*
12953   * Registers shared between all ports.
12954   */
12955 -#define PHY_ADDR_REG                           0x0000
12956 -#define SMI_REG                                        0x0004
12957 -#define WINDOW_BASE(i)                         (0x0200 + ((i) << 3))
12958 -#define WINDOW_SIZE(i)                         (0x0204 + ((i) << 3))
12959 -#define WINDOW_REMAP_HIGH(i)                   (0x0280 + ((i) << 2))
12960 -#define WINDOW_BAR_ENABLE                      0x0290
12961 -#define WINDOW_PROTECT(i)                      (0x0294 + ((i) << 4))
12962 +#define PHY_ADDR                       0x0000
12963 +#define SMI_REG                                0x0004
12964 +#define WINDOW_BASE(w)                 (0x0200 + ((w) << 3))
12965 +#define WINDOW_SIZE(w)                 (0x0204 + ((w) << 3))
12966 +#define WINDOW_REMAP_HIGH(w)           (0x0280 + ((w) << 2))
12967 +#define WINDOW_BAR_ENABLE              0x0290
12968 +#define WINDOW_PROTECT(w)              (0x0294 + ((w) << 4))
12969
12970  /*
12971   * Per-port registers.
12972   */
12973 -#define PORT_CONFIG_REG(p)                             (0x0400 + ((p) << 10))
12974 -#define PORT_CONFIG_EXTEND_REG(p)                      (0x0404 + ((p) << 10))
12975 -#define MAC_ADDR_LOW(p)                                        (0x0414 + ((p) << 10))
12976 -#define MAC_ADDR_HIGH(p)                               (0x0418 + ((p) << 10))
12977 -#define SDMA_CONFIG_REG(p)                             (0x041c + ((p) << 10))
12978 -#define PORT_SERIAL_CONTROL_REG(p)                     (0x043c + ((p) << 10))
12979 -#define PORT_STATUS_REG(p)                             (0x0444 + ((p) << 10))
12980 -#define TRANSMIT_QUEUE_COMMAND_REG(p)                  (0x0448 + ((p) << 10))
12981 -#define MAXIMUM_TRANSMIT_UNIT(p)                       (0x0458 + ((p) << 10))
12982 -#define INTERRUPT_CAUSE_REG(p)                         (0x0460 + ((p) << 10))
12983 -#define INTERRUPT_CAUSE_EXTEND_REG(p)                  (0x0464 + ((p) << 10))
12984 -#define INTERRUPT_MASK_REG(p)                          (0x0468 + ((p) << 10))
12985 -#define INTERRUPT_EXTEND_MASK_REG(p)                   (0x046c + ((p) << 10))
12986 -#define TX_FIFO_URGENT_THRESHOLD_REG(p)                        (0x0474 + ((p) << 10))
12987 -#define RX_CURRENT_QUEUE_DESC_PTR_0(p)                 (0x060c + ((p) << 10))
12988 -#define RECEIVE_QUEUE_COMMAND_REG(p)                   (0x0680 + ((p) << 10))
12989 -#define TX_CURRENT_QUEUE_DESC_PTR_0(p)                 (0x06c0 + ((p) << 10))
12990 -#define MIB_COUNTERS_BASE(p)                           (0x1000 + ((p) << 7))
12991 -#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p)      (0x1400 + ((p) << 10))
12992 -#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p)                (0x1500 + ((p) << 10))
12993 -#define DA_FILTER_UNICAST_TABLE_BASE(p)                        (0x1600 + ((p) << 10))
12994 -
12995 -/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
12996 -#define UNICAST_NORMAL_MODE            (0 << 0)
12997 -#define UNICAST_PROMISCUOUS_MODE       (1 << 0)
12998 -#define DEFAULT_RX_QUEUE(queue)                ((queue) << 1)
12999 -#define DEFAULT_RX_ARP_QUEUE(queue)    ((queue) << 4)
13000 -#define RECEIVE_BC_IF_NOT_IP_OR_ARP    (0 << 7)
13001 -#define REJECT_BC_IF_NOT_IP_OR_ARP     (1 << 7)
13002 -#define RECEIVE_BC_IF_IP               (0 << 8)
13003 -#define REJECT_BC_IF_IP                        (1 << 8)
13004 -#define RECEIVE_BC_IF_ARP              (0 << 9)
13005 -#define REJECT_BC_IF_ARP               (1 << 9)
13006 -#define TX_AM_NO_UPDATE_ERROR_SUMMARY  (1 << 12)
13007 -#define CAPTURE_TCP_FRAMES_DIS         (0 << 14)
13008 -#define CAPTURE_TCP_FRAMES_EN          (1 << 14)
13009 -#define CAPTURE_UDP_FRAMES_DIS         (0 << 15)
13010 -#define CAPTURE_UDP_FRAMES_EN          (1 << 15)
13011 -#define DEFAULT_RX_TCP_QUEUE(queue)    ((queue) << 16)
13012 -#define DEFAULT_RX_UDP_QUEUE(queue)    ((queue) << 19)
13013 -#define DEFAULT_RX_BPDU_QUEUE(queue)   ((queue) << 22)
13014 -
13015 -#define PORT_CONFIG_DEFAULT_VALUE                      \
13016 -               UNICAST_NORMAL_MODE             |       \
13017 -               DEFAULT_RX_QUEUE(0)             |       \
13018 -               DEFAULT_RX_ARP_QUEUE(0)         |       \
13019 -               RECEIVE_BC_IF_NOT_IP_OR_ARP     |       \
13020 -               RECEIVE_BC_IF_IP                |       \
13021 -               RECEIVE_BC_IF_ARP               |       \
13022 -               CAPTURE_TCP_FRAMES_DIS          |       \
13023 -               CAPTURE_UDP_FRAMES_DIS          |       \
13024 -               DEFAULT_RX_TCP_QUEUE(0)         |       \
13025 -               DEFAULT_RX_UDP_QUEUE(0)         |       \
13026 -               DEFAULT_RX_BPDU_QUEUE(0)
13027 -
13028 -/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
13029 -#define CLASSIFY_EN                            (1 << 0)
13030 -#define SPAN_BPDU_PACKETS_AS_NORMAL            (0 << 1)
13031 -#define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7                (1 << 1)
13032 -#define PARTITION_DISABLE                      (0 << 2)
13033 -#define PARTITION_ENABLE                       (1 << 2)
13034 -
13035 -#define PORT_CONFIG_EXTEND_DEFAULT_VALUE               \
13036 -               SPAN_BPDU_PACKETS_AS_NORMAL     |       \
13037 -               PARTITION_DISABLE
13038 -
13039 -/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
13040 -#define RIFB                           (1 << 0)
13041 -#define RX_BURST_SIZE_1_64BIT          (0 << 1)
13042 -#define RX_BURST_SIZE_2_64BIT          (1 << 1)
13043 +#define PORT_CONFIG(p)                 (0x0400 + ((p) << 10))
13044 +#define  UNICAST_PROMISCUOUS_MODE      0x00000001
13045 +#define PORT_CONFIG_EXT(p)             (0x0404 + ((p) << 10))
13046 +#define MAC_ADDR_LOW(p)                        (0x0414 + ((p) << 10))
13047 +#define MAC_ADDR_HIGH(p)               (0x0418 + ((p) << 10))
13048 +#define SDMA_CONFIG(p)                 (0x041c + ((p) << 10))
13049 +#define PORT_SERIAL_CONTROL(p)         (0x043c + ((p) << 10))
13050 +#define PORT_STATUS(p)                 (0x0444 + ((p) << 10))
13051 +#define  TX_FIFO_EMPTY                 0x00000400
13052 +#define TXQ_COMMAND(p)                 (0x0448 + ((p) << 10))
13053 +#define TXQ_FIX_PRIO_CONF(p)           (0x044c + ((p) << 10))
13054 +#define TX_BW_RATE(p)                  (0x0450 + ((p) << 10))
13055 +#define TX_BW_MTU(p)                   (0x0458 + ((p) << 10))
13056 +#define TX_BW_BURST(p)                 (0x045c + ((p) << 10))
13057 +#define INT_CAUSE(p)                   (0x0460 + ((p) << 10))
13058 +#define  INT_TX_END                    0x07f80000
13059 +#define  INT_RX                                0x0007fbfc
13060 +#define  INT_EXT                       0x00000002
13061 +#define INT_CAUSE_EXT(p)               (0x0464 + ((p) << 10))
13062 +#define  INT_EXT_LINK                  0x00100000
13063 +#define  INT_EXT_PHY                   0x00010000
13064 +#define  INT_EXT_TX_ERROR_0            0x00000100
13065 +#define  INT_EXT_TX_0                  0x00000001
13066 +#define  INT_EXT_TX                    0x0000ffff
13067 +#define INT_MASK(p)                    (0x0468 + ((p) << 10))
13068 +#define INT_MASK_EXT(p)                        (0x046c + ((p) << 10))
13069 +#define TX_FIFO_URGENT_THRESHOLD(p)    (0x0474 + ((p) << 10))
13070 +#define TXQ_FIX_PRIO_CONF_MOVED(p)     (0x04dc + ((p) << 10))
13071 +#define TX_BW_RATE_MOVED(p)            (0x04e0 + ((p) << 10))
13072 +#define TX_BW_MTU_MOVED(p)             (0x04e8 + ((p) << 10))
13073 +#define TX_BW_BURST_MOVED(p)           (0x04ec + ((p) << 10))
13074 +#define RXQ_CURRENT_DESC_PTR(p, q)     (0x060c + ((p) << 10) + ((q) << 4))
13075 +#define RXQ_COMMAND(p)                 (0x0680 + ((p) << 10))
13076 +#define TXQ_CURRENT_DESC_PTR(p, q)     (0x06c0 + ((p) << 10) + ((q) << 2))
13077 +#define TXQ_BW_TOKENS(p, q)            (0x0700 + ((p) << 10) + ((q) << 4))
13078 +#define TXQ_BW_CONF(p, q)              (0x0704 + ((p) << 10) + ((q) << 4))
13079 +#define TXQ_BW_WRR_CONF(p, q)          (0x0708 + ((p) << 10) + ((q) << 4))
13080 +#define MIB_COUNTERS(p)                        (0x1000 + ((p) << 7))
13081 +#define SPECIAL_MCAST_TABLE(p)         (0x1400 + ((p) << 10))
13082 +#define OTHER_MCAST_TABLE(p)           (0x1500 + ((p) << 10))
13083 +#define UNICAST_TABLE(p)               (0x1600 + ((p) << 10))
13084 +
13085 +
13086 +/*
13087 + * SDMA configuration register.
13088 + */
13089  #define RX_BURST_SIZE_4_64BIT          (2 << 1)
13090 -#define RX_BURST_SIZE_8_64BIT          (3 << 1)
13091 -#define RX_BURST_SIZE_16_64BIT         (4 << 1)
13092  #define BLM_RX_NO_SWAP                 (1 << 4)
13093 -#define BLM_RX_BYTE_SWAP               (0 << 4)
13094  #define BLM_TX_NO_SWAP                 (1 << 5)
13095 -#define BLM_TX_BYTE_SWAP               (0 << 5)
13096 -#define DESCRIPTORS_BYTE_SWAP          (1 << 6)
13097 -#define DESCRIPTORS_NO_SWAP            (0 << 6)
13098 -#define IPG_INT_RX(value)              (((value) & 0x3fff) << 8)
13099 -#define TX_BURST_SIZE_1_64BIT          (0 << 22)
13100 -#define TX_BURST_SIZE_2_64BIT          (1 << 22)
13101  #define TX_BURST_SIZE_4_64BIT          (2 << 22)
13102 -#define TX_BURST_SIZE_8_64BIT          (3 << 22)
13103 -#define TX_BURST_SIZE_16_64BIT         (4 << 22)
13104
13105  #if defined(__BIG_ENDIAN)
13106  #define PORT_SDMA_CONFIG_DEFAULT_VALUE         \
13107                 RX_BURST_SIZE_4_64BIT   |       \
13108 -               IPG_INT_RX(0)           |       \
13109                 TX_BURST_SIZE_4_64BIT
13110  #elif defined(__LITTLE_ENDIAN)
13111  #define PORT_SDMA_CONFIG_DEFAULT_VALUE         \
13112                 RX_BURST_SIZE_4_64BIT   |       \
13113                 BLM_RX_NO_SWAP          |       \
13114                 BLM_TX_NO_SWAP          |       \
13115 -               IPG_INT_RX(0)           |       \
13116                 TX_BURST_SIZE_4_64BIT
13117  #else
13118  #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
13119  #endif
13120
13121 -/* These macros describe Ethernet Port serial control reg (PSCR) bits */
13122 -#define SERIAL_PORT_DISABLE                    (0 << 0)
13123 -#define SERIAL_PORT_ENABLE                     (1 << 0)
13124 -#define DO_NOT_FORCE_LINK_PASS                 (0 << 1)
13125 -#define FORCE_LINK_PASS                                (1 << 1)
13126 -#define ENABLE_AUTO_NEG_FOR_DUPLX              (0 << 2)
13127 -#define DISABLE_AUTO_NEG_FOR_DUPLX             (1 << 2)
13128 -#define ENABLE_AUTO_NEG_FOR_FLOW_CTRL          (0 << 3)
13129 -#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL         (1 << 3)
13130 -#define ADV_NO_FLOW_CTRL                       (0 << 4)
13131 -#define ADV_SYMMETRIC_FLOW_CTRL                        (1 << 4)
13132 -#define FORCE_FC_MODE_NO_PAUSE_DIS_TX          (0 << 5)
13133 -#define FORCE_FC_MODE_TX_PAUSE_DIS             (1 << 5)
13134 -#define FORCE_BP_MODE_NO_JAM                   (0 << 7)
13135 -#define FORCE_BP_MODE_JAM_TX                   (1 << 7)
13136 -#define FORCE_BP_MODE_JAM_TX_ON_RX_ERR         (2 << 7)
13137 -#define SERIAL_PORT_CONTROL_RESERVED           (1 << 9)
13138 -#define FORCE_LINK_FAIL                                (0 << 10)
13139 -#define DO_NOT_FORCE_LINK_FAIL                 (1 << 10)
13140 -#define RETRANSMIT_16_ATTEMPTS                 (0 << 11)
13141 -#define RETRANSMIT_FOREVER                     (1 << 11)
13142 -#define ENABLE_AUTO_NEG_SPEED_GMII             (0 << 13)
13143 -#define DISABLE_AUTO_NEG_SPEED_GMII            (1 << 13)
13144 -#define DTE_ADV_0                              (0 << 14)
13145 -#define DTE_ADV_1                              (1 << 14)
13146 -#define DISABLE_AUTO_NEG_BYPASS                        (0 << 15)
13147 -#define ENABLE_AUTO_NEG_BYPASS                 (1 << 15)
13148 -#define AUTO_NEG_NO_CHANGE                     (0 << 16)
13149 -#define RESTART_AUTO_NEG                       (1 << 16)
13150 -#define MAX_RX_PACKET_1518BYTE                 (0 << 17)
13151 +
13152 +/*
13153 + * Port serial control register.
13154 + */
13155 +#define SET_MII_SPEED_TO_100                   (1 << 24)
13156 +#define SET_GMII_SPEED_TO_1000                 (1 << 23)
13157 +#define SET_FULL_DUPLEX_MODE                   (1 << 21)
13158  #define MAX_RX_PACKET_1522BYTE                 (1 << 17)
13159 -#define MAX_RX_PACKET_1552BYTE                 (2 << 17)
13160 -#define MAX_RX_PACKET_9022BYTE                 (3 << 17)
13161 -#define MAX_RX_PACKET_9192BYTE                 (4 << 17)
13162  #define MAX_RX_PACKET_9700BYTE                 (5 << 17)
13163  #define MAX_RX_PACKET_MASK                     (7 << 17)
13164 -#define CLR_EXT_LOOPBACK                       (0 << 20)
13165 -#define SET_EXT_LOOPBACK                       (1 << 20)
13166 -#define SET_HALF_DUPLEX_MODE                   (0 << 21)
13167 -#define SET_FULL_DUPLEX_MODE                   (1 << 21)
13168 -#define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
13169 -#define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX  (1 << 22)
13170 -#define SET_GMII_SPEED_TO_10_100               (0 << 23)
13171 -#define SET_GMII_SPEED_TO_1000                 (1 << 23)
13172 -#define SET_MII_SPEED_TO_10                    (0 << 24)
13173 -#define SET_MII_SPEED_TO_100                   (1 << 24)
13174 +#define DISABLE_AUTO_NEG_SPEED_GMII            (1 << 13)
13175 +#define DO_NOT_FORCE_LINK_FAIL                 (1 << 10)
13176 +#define SERIAL_PORT_CONTROL_RESERVED           (1 << 9)
13177 +#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL         (1 << 3)
13178 +#define DISABLE_AUTO_NEG_FOR_DUPLEX            (1 << 2)
13179 +#define FORCE_LINK_PASS                                (1 << 1)
13180 +#define SERIAL_PORT_ENABLE                     (1 << 0)
13181 +
13182 +#define DEFAULT_RX_QUEUE_SIZE          400
13183 +#define DEFAULT_TX_QUEUE_SIZE          800
13184
13185 -#define PORT_SERIAL_CONTROL_DEFAULT_VALUE              \
13186 -               DO_NOT_FORCE_LINK_PASS          |       \
13187 -               ENABLE_AUTO_NEG_FOR_DUPLX       |       \
13188 -               DISABLE_AUTO_NEG_FOR_FLOW_CTRL  |       \
13189 -               ADV_SYMMETRIC_FLOW_CTRL         |       \
13190 -               FORCE_FC_MODE_NO_PAUSE_DIS_TX   |       \
13191 -               FORCE_BP_MODE_NO_JAM            |       \
13192 -               (1 << 9) /* reserved */         |       \
13193 -               DO_NOT_FORCE_LINK_FAIL          |       \
13194 -               RETRANSMIT_16_ATTEMPTS          |       \
13195 -               ENABLE_AUTO_NEG_SPEED_GMII      |       \
13196 -               DTE_ADV_0                       |       \
13197 -               DISABLE_AUTO_NEG_BYPASS         |       \
13198 -               AUTO_NEG_NO_CHANGE              |       \
13199 -               MAX_RX_PACKET_9700BYTE          |       \
13200 -               CLR_EXT_LOOPBACK                |       \
13201 -               SET_FULL_DUPLEX_MODE            |       \
13202 -               ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
13203 -
13204 -/* These macros describe Ethernet Serial Status reg (PSR) bits */
13205 -#define PORT_STATUS_MODE_10_BIT                (1 << 0)
13206 -#define PORT_STATUS_LINK_UP            (1 << 1)
13207 -#define PORT_STATUS_FULL_DUPLEX                (1 << 2)
13208 -#define PORT_STATUS_FLOW_CONTROL       (1 << 3)
13209 -#define PORT_STATUS_GMII_1000          (1 << 4)
13210 -#define PORT_STATUS_MII_100            (1 << 5)
13211 -/* PSR bit 6 is undocumented */
13212 -#define PORT_STATUS_TX_IN_PROGRESS     (1 << 7)
13213 -#define PORT_STATUS_AUTONEG_BYPASSED   (1 << 8)
13214 -#define PORT_STATUS_PARTITION          (1 << 9)
13215 -#define PORT_STATUS_TX_FIFO_EMPTY      (1 << 10)
13216 -/* PSR bits 11-31 are reserved */
13217 -
13218 -#define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE       800
13219 -#define PORT_DEFAULT_RECEIVE_QUEUE_SIZE                400
13220 -
13221 -#define DESC_SIZE                              64
13222 -
13223 -#define ETH_RX_QUEUES_ENABLED  (1 << 0)        /* use only Q0 for receive */
13224 -#define ETH_TX_QUEUES_ENABLED  (1 << 0)        /* use only Q0 for transmit */
13225 -
13226 -#define ETH_INT_CAUSE_RX_DONE  (ETH_RX_QUEUES_ENABLED << 2)
13227 -#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
13228 -#define ETH_INT_CAUSE_RX       (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
13229 -#define ETH_INT_CAUSE_EXT      0x00000002
13230 -#define ETH_INT_UNMASK_ALL     (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
13231 -
13232 -#define ETH_INT_CAUSE_TX_DONE  (ETH_TX_QUEUES_ENABLED << 0)
13233 -#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
13234 -#define ETH_INT_CAUSE_TX       (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
13235 -#define ETH_INT_CAUSE_PHY      0x00010000
13236 -#define ETH_INT_CAUSE_STATE    0x00100000
13237 -#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
13238 -                                       ETH_INT_CAUSE_STATE)
13239 -
13240 -#define ETH_INT_MASK_ALL       0x00000000
13241 -#define ETH_INT_MASK_ALL_EXT   0x00000000
13242 -
13243 -#define PHY_WAIT_ITERATIONS    1000    /* 1000 iterations * 10uS = 10mS max */
13244 -#define PHY_WAIT_MICRO_SECONDS 10
13245 -
13246 -/* Buffer offset from buffer pointer */
13247 -#define RX_BUF_OFFSET                          0x2
13248 -
13249 -/* Gigabit Ethernet Unit Global Registers */
13250 -
13251 -/* MIB Counters register definitions */
13252 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW       0x0
13253 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH      0x4
13254 -#define ETH_MIB_BAD_OCTETS_RECEIVED            0x8
13255 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR      0xc
13256 -#define ETH_MIB_GOOD_FRAMES_RECEIVED           0x10
13257 -#define ETH_MIB_BAD_FRAMES_RECEIVED            0x14
13258 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED      0x18
13259 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED      0x1c
13260 -#define ETH_MIB_FRAMES_64_OCTETS               0x20
13261 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS                0x24
13262 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS       0x28
13263 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS       0x2c
13264 -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS      0x30
13265 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS      0x34
13266 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW           0x38
13267 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH          0x3c
13268 -#define ETH_MIB_GOOD_FRAMES_SENT               0x40
13269 -#define ETH_MIB_EXCESSIVE_COLLISION            0x44
13270 -#define ETH_MIB_MULTICAST_FRAMES_SENT          0x48
13271 -#define ETH_MIB_BROADCAST_FRAMES_SENT          0x4c
13272 -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED     0x50
13273 -#define ETH_MIB_FC_SENT                                0x54
13274 -#define ETH_MIB_GOOD_FC_RECEIVED               0x58
13275 -#define ETH_MIB_BAD_FC_RECEIVED                        0x5c
13276 -#define ETH_MIB_UNDERSIZE_RECEIVED             0x60
13277 -#define ETH_MIB_FRAGMENTS_RECEIVED             0x64
13278 -#define ETH_MIB_OVERSIZE_RECEIVED              0x68
13279 -#define ETH_MIB_JABBER_RECEIVED                        0x6c
13280 -#define ETH_MIB_MAC_RECEIVE_ERROR              0x70
13281 -#define ETH_MIB_BAD_CRC_EVENT                  0x74
13282 -#define ETH_MIB_COLLISION                      0x78
13283 -#define ETH_MIB_LATE_COLLISION                 0x7c
13284 -
13285 -/* Port serial status reg (PSR) */
13286 -#define ETH_INTERFACE_PCM                      0x00000001
13287 -#define ETH_LINK_IS_UP                         0x00000002
13288 -#define ETH_PORT_AT_FULL_DUPLEX                        0x00000004
13289 -#define ETH_RX_FLOW_CTRL_ENABLED               0x00000008
13290 -#define ETH_GMII_SPEED_1000                    0x00000010
13291 -#define ETH_MII_SPEED_100                      0x00000020
13292 -#define ETH_TX_IN_PROGRESS                     0x00000080
13293 -#define ETH_BYPASS_ACTIVE                      0x00000100
13294 -#define ETH_PORT_AT_PARTITION_STATE            0x00000200
13295 -#define ETH_PORT_TX_FIFO_EMPTY                 0x00000400
13296 -
13297 -/* SMI reg */
13298 -#define ETH_SMI_BUSY           0x10000000      /* 0 - Write, 1 - Read  */
13299 -#define ETH_SMI_READ_VALID     0x08000000      /* 0 - Write, 1 - Read  */
13300 -#define ETH_SMI_OPCODE_WRITE   0               /* Completion of Read   */
13301 -#define ETH_SMI_OPCODE_READ    0x04000000      /* Operation is in progress */
13302 -
13303 -/* Interrupt Cause Register Bit Definitions */
13304 -
13305 -/* SDMA command status fields macros */
13306 -
13307 -/* Tx & Rx descriptors status */
13308 -#define ETH_ERROR_SUMMARY                      0x00000001
13309 -
13310 -/* Tx & Rx descriptors command */
13311 -#define ETH_BUFFER_OWNED_BY_DMA                        0x80000000
13312 -
13313 -/* Tx descriptors status */
13314 -#define ETH_LC_ERROR                           0
13315 -#define ETH_UR_ERROR                           0x00000002
13316 -#define ETH_RL_ERROR                           0x00000004
13317 -#define ETH_LLC_SNAP_FORMAT                    0x00000200
13318 -
13319 -/* Rx descriptors status */
13320 -#define ETH_OVERRUN_ERROR                      0x00000002
13321 -#define ETH_MAX_FRAME_LENGTH_ERROR             0x00000004
13322 -#define ETH_RESOURCE_ERROR                     0x00000006
13323 -#define ETH_VLAN_TAGGED                                0x00080000
13324 -#define ETH_BPDU_FRAME                         0x00100000
13325 -#define ETH_UDP_FRAME_OVER_IP_V_4              0x00200000
13326 -#define ETH_OTHER_FRAME_TYPE                   0x00400000
13327 -#define ETH_LAYER_2_IS_ETH_V_2                 0x00800000
13328 -#define ETH_FRAME_TYPE_IP_V_4                  0x01000000
13329 -#define ETH_FRAME_HEADER_OK                    0x02000000
13330 -#define ETH_RX_LAST_DESC                       0x04000000
13331 -#define ETH_RX_FIRST_DESC                      0x08000000
13332 -#define ETH_UNKNOWN_DESTINATION_ADDR           0x10000000
13333 -#define ETH_RX_ENABLE_INTERRUPT                        0x20000000
13334 -#define ETH_LAYER_4_CHECKSUM_OK                        0x40000000
13335 -
13336 -/* Rx descriptors byte count */
13337 -#define ETH_FRAME_FRAGMENTED                   0x00000004
13338 -
13339 -/* Tx descriptors command */
13340 -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC                0x00000400
13341 -#define ETH_FRAME_SET_TO_VLAN                  0x00008000
13342 -#define ETH_UDP_FRAME                          0x00010000
13343 -#define ETH_GEN_TCP_UDP_CHECKSUM               0x00020000
13344 -#define ETH_GEN_IP_V_4_CHECKSUM                        0x00040000
13345 -#define ETH_ZERO_PADDING                       0x00080000
13346 -#define ETH_TX_LAST_DESC                       0x00100000
13347 -#define ETH_TX_FIRST_DESC                      0x00200000
13348 -#define ETH_GEN_CRC                            0x00400000
13349 -#define ETH_TX_ENABLE_INTERRUPT                        0x00800000
13350 -#define ETH_AUTO_MODE                          0x40000000
13351 -
13352 -#define ETH_TX_IHL_SHIFT                       11
13353 -
13354 -/* typedefs */
13355 -
13356 -typedef enum _eth_func_ret_status {
13357 -       ETH_OK,                 /* Returned as expected.                */
13358 -       ETH_ERROR,              /* Fundamental error.                   */
13359 -       ETH_RETRY,              /* Could not process request. Try later.*/
13360 -       ETH_END_OF_JOB,         /* Ring has nothing to process.         */
13361 -       ETH_QUEUE_FULL,         /* Ring resource error.                 */
13362 -       ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust.     */
13363 -} ETH_FUNC_RET_STATUS;
13364
13365 -/* These are for big-endian machines.  Little endian needs different
13366 - * definitions.
13367 +/*
13368 + * RX/TX descriptors.
13369   */
13370  #if defined(__BIG_ENDIAN)
13371 -struct eth_rx_desc {
13372 +struct rx_desc {
13373         u16 byte_cnt;           /* Descriptor buffer byte count         */
13374         u16 buf_size;           /* Buffer size                          */
13375         u32 cmd_sts;            /* Descriptor command status            */
13376 @@ -441,7 +180,7 @@
13377         u32 buf_ptr;            /* Descriptor buffer pointer            */
13378  };
13379
13380 -struct eth_tx_desc {
13381 +struct tx_desc {
13382         u16 byte_cnt;           /* buffer byte count                    */
13383         u16 l4i_chk;            /* CPU provided TCP checksum            */
13384         u32 cmd_sts;            /* Command/status field                 */
13385 @@ -449,7 +188,7 @@
13386         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
13387  };
13388  #elif defined(__LITTLE_ENDIAN)
13389 -struct eth_rx_desc {
13390 +struct rx_desc {
13391         u32 cmd_sts;            /* Descriptor command status            */
13392         u16 buf_size;           /* Buffer size                          */
13393         u16 byte_cnt;           /* Descriptor buffer byte count         */
13394 @@ -457,7 +196,7 @@
13395         u32 next_desc_ptr;      /* Next descriptor pointer              */
13396  };
13397
13398 -struct eth_tx_desc {
13399 +struct tx_desc {
13400         u32 cmd_sts;            /* Command/status field                 */
13401         u16 l4i_chk;            /* CPU provided TCP checksum            */
13402         u16 byte_cnt;           /* buffer byte count                    */
13403 @@ -468,18 +207,59 @@
13404  #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
13405  #endif
13406
13407 -/* Unified struct for Rx and Tx operations. The user is not required to        */
13408 -/* be familier with neither Tx nor Rx descriptors.                     */
13409 -struct pkt_info {
13410 -       unsigned short byte_cnt;        /* Descriptor buffer byte count */
13411 -       unsigned short l4i_chk;         /* Tx CPU provided TCP Checksum */
13412 -       unsigned int cmd_sts;           /* Descriptor command status    */
13413 -       dma_addr_t buf_ptr;             /* Descriptor buffer pointer    */
13414 -       struct sk_buff *return_info;    /* User resource return information */
13415 +/* RX & TX descriptor command */
13416 +#define BUFFER_OWNED_BY_DMA            0x80000000
13417 +
13418 +/* RX & TX descriptor status */
13419 +#define ERROR_SUMMARY                  0x00000001
13420 +
13421 +/* RX descriptor status */
13422 +#define LAYER_4_CHECKSUM_OK            0x40000000
13423 +#define RX_ENABLE_INTERRUPT            0x20000000
13424 +#define RX_FIRST_DESC                  0x08000000
13425 +#define RX_LAST_DESC                   0x04000000
13426 +
13427 +/* TX descriptor command */
13428 +#define TX_ENABLE_INTERRUPT            0x00800000
13429 +#define GEN_CRC                                0x00400000
13430 +#define TX_FIRST_DESC                  0x00200000
13431 +#define TX_LAST_DESC                   0x00100000
13432 +#define ZERO_PADDING                   0x00080000
13433 +#define GEN_IP_V4_CHECKSUM             0x00040000
13434 +#define GEN_TCP_UDP_CHECKSUM           0x00020000
13435 +#define UDP_FRAME                      0x00010000
13436 +
13437 +#define TX_IHL_SHIFT                   11
13438 +
13439 +
13440 +/* global *******************************************************************/
13441 +struct mv643xx_eth_shared_private {
13442 +       /*
13443 +        * Ethernet controller base address.
13444 +        */
13445 +       void __iomem *base;
13446 +
13447 +       /*
13448 +        * Protects access to SMI_REG, which is shared between ports.
13449 +        */
13450 +       spinlock_t phy_lock;
13451 +
13452 +       /*
13453 +        * Per-port MBUS window access register value.
13454 +        */
13455 +       u32 win_protect;
13456 +
13457 +       /*
13458 +        * Hardware-specific parameters.
13459 +        */
13460 +       unsigned int t_clk;
13461 +       int extended_rx_coal_limit;
13462 +       int tx_bw_control_moved;
13463  };
13464
13465 -/* Ethernet port specific information */
13466 -struct mv643xx_mib_counters {
13467 +
13468 +/* per-port *****************************************************************/
13469 +struct mib_counters {
13470         u64 good_octets_received;
13471         u32 bad_octets_received;
13472         u32 internal_mac_transmit_err;
13473 @@ -512,461 +292,282 @@
13474         u32 late_collision;
13475  };
13476
13477 -struct mv643xx_shared_private {
13478 -       void __iomem *eth_base;
13479 -
13480 -       /* used to protect SMI_REG, which is shared across ports */
13481 -       spinlock_t phy_lock;
13482 -
13483 -       u32 win_protect;
13484 -
13485 -       unsigned int t_clk;
13486 -};
13487 -
13488 -struct mv643xx_private {
13489 -       struct mv643xx_shared_private *shared;
13490 -       int port_num;                   /* User Ethernet port number    */
13491 -
13492 -       struct mv643xx_shared_private *shared_smi;
13493 +struct rx_queue {
13494 +       int index;
13495
13496 -       u32 rx_sram_addr;               /* Base address of rx sram area */
13497 -       u32 rx_sram_size;               /* Size of rx sram area         */
13498 -       u32 tx_sram_addr;               /* Base address of tx sram area */
13499 -       u32 tx_sram_size;               /* Size of tx sram area         */
13500 +       int rx_ring_size;
13501
13502 -       int rx_resource_err;            /* Rx ring resource error flag */
13503 +       int rx_desc_count;
13504 +       int rx_curr_desc;
13505 +       int rx_used_desc;
13506
13507 -       /* Tx/Rx rings managment indexes fields. For driver use */
13508 +       struct rx_desc *rx_desc_area;
13509 +       dma_addr_t rx_desc_dma;
13510 +       int rx_desc_area_size;
13511 +       struct sk_buff **rx_skb;
13512
13513 -       /* Next available and first returning Rx resource */
13514 -       int rx_curr_desc_q, rx_used_desc_q;
13515 +       struct timer_list rx_oom;
13516 +};
13517
13518 -       /* Next available and first returning Tx resource */
13519 -       int tx_curr_desc_q, tx_used_desc_q;
13520 +struct tx_queue {
13521 +       int index;
13522
13523 -#ifdef MV643XX_TX_FAST_REFILL
13524 -       u32 tx_clean_threshold;
13525 -#endif
13526 +       int tx_ring_size;
13527
13528 -       struct eth_rx_desc *p_rx_desc_area;
13529 -       dma_addr_t rx_desc_dma;
13530 -       int rx_desc_area_size;
13531 -       struct sk_buff **rx_skb;
13532 +       int tx_desc_count;
13533 +       int tx_curr_desc;
13534 +       int tx_used_desc;
13535
13536 -       struct eth_tx_desc *p_tx_desc_area;
13537 +       struct tx_desc *tx_desc_area;
13538         dma_addr_t tx_desc_dma;
13539         int tx_desc_area_size;
13540         struct sk_buff **tx_skb;
13541 +};
13542
13543 -       struct work_struct tx_timeout_task;
13544 +struct mv643xx_eth_private {
13545 +       struct mv643xx_eth_shared_private *shared;
13546 +       int port_num;
13547
13548         struct net_device *dev;
13549 -       struct napi_struct napi;
13550 -       struct net_device_stats stats;
13551 -       struct mv643xx_mib_counters mib_counters;
13552 +
13553 +       struct mv643xx_eth_shared_private *shared_smi;
13554 +       int phy_addr;
13555 +
13556         spinlock_t lock;
13557 -       /* Size of Tx Ring per queue */
13558 -       int tx_ring_size;
13559 -       /* Number of tx descriptors in use */
13560 -       int tx_desc_count;
13561 -       /* Size of Rx Ring per queue */
13562 -       int rx_ring_size;
13563 -       /* Number of rx descriptors in use */
13564 -       int rx_desc_count;
13565 +
13566 +       struct mib_counters mib_counters;
13567 +       struct work_struct tx_timeout_task;
13568 +       struct mii_if_info mii;
13569
13570         /*
13571 -        * Used in case RX Ring is empty, which can be caused when
13572 -        * system does not have resources (skb's)
13573 +        * RX state.
13574          */
13575 -       struct timer_list timeout;
13576 -
13577 -       u32 rx_int_coal;
13578 -       u32 tx_int_coal;
13579 -       struct mii_if_info mii;
13580 -};
13581 +       int default_rx_ring_size;
13582 +       unsigned long rx_desc_sram_addr;
13583 +       int rx_desc_sram_size;
13584 +       u8 rxq_mask;
13585 +       int rxq_primary;
13586 +       struct napi_struct napi;
13587 +       struct rx_queue rxq[8];
13588
13589 -/* Static function declarations */
13590 -static void eth_port_init(struct mv643xx_private *mp);
13591 -static void eth_port_reset(struct mv643xx_private *mp);
13592 -static void eth_port_start(struct net_device *dev);
13593 -
13594 -static void ethernet_phy_reset(struct mv643xx_private *mp);
13595 -
13596 -static void eth_port_write_smi_reg(struct mv643xx_private *mp,
13597 -                                  unsigned int phy_reg, unsigned int value);
13598 -
13599 -static void eth_port_read_smi_reg(struct mv643xx_private *mp,
13600 -                                 unsigned int phy_reg, unsigned int *value);
13601 -
13602 -static void eth_clear_mib_counters(struct mv643xx_private *mp);
13603 -
13604 -static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
13605 -                                           struct pkt_info *p_pkt_info);
13606 -static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
13607 -                                             struct pkt_info *p_pkt_info);
13608 -
13609 -static void eth_port_uc_addr_get(struct mv643xx_private *mp,
13610 -                                unsigned char *p_addr);
13611 -static void eth_port_uc_addr_set(struct mv643xx_private *mp,
13612 -                                unsigned char *p_addr);
13613 -static void eth_port_set_multicast_list(struct net_device *);
13614 -static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
13615 -                                               unsigned int queues);
13616 -static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
13617 -                                               unsigned int queues);
13618 -static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp);
13619 -static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp);
13620 -static int mv643xx_eth_open(struct net_device *);
13621 -static int mv643xx_eth_stop(struct net_device *);
13622 -static void eth_port_init_mac_tables(struct mv643xx_private *mp);
13623 -#ifdef MV643XX_NAPI
13624 -static int mv643xx_poll(struct napi_struct *napi, int budget);
13625 +       /*
13626 +        * TX state.
13627 +        */
13628 +       int default_tx_ring_size;
13629 +       unsigned long tx_desc_sram_addr;
13630 +       int tx_desc_sram_size;
13631 +       u8 txq_mask;
13632 +       int txq_primary;
13633 +       struct tx_queue txq[8];
13634 +#ifdef MV643XX_ETH_TX_FAST_REFILL
13635 +       int tx_clean_threshold;
13636  #endif
13637 -static int ethernet_phy_get(struct mv643xx_private *mp);
13638 -static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr);
13639 -static int ethernet_phy_detect(struct mv643xx_private *mp);
13640 -static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
13641 -static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
13642 -static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
13643 -static const struct ethtool_ops mv643xx_ethtool_ops;
13644 +};
13645
13646 -static char mv643xx_driver_name[] = "mv643xx_eth";
13647 -static char mv643xx_driver_version[] = "1.0";
13648
13649 -static inline u32 rdl(struct mv643xx_private *mp, int offset)
13650 +/* port register accessors **************************************************/
13651 +static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
13652  {
13653 -       return readl(mp->shared->eth_base + offset);
13654 +       return readl(mp->shared->base + offset);
13655  }
13656
13657 -static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
13658 +static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
13659  {
13660 -       writel(data, mp->shared->eth_base + offset);
13661 +       writel(data, mp->shared->base + offset);
13662  }
13663
13664 -/*
13665 - * Changes MTU (maximum transfer unit) of the gigabit ethenret port
13666 - *
13667 - * Input :     pointer to ethernet interface network device structure
13668 - *             new mtu size
13669 - * Output :    0 upon success, -EINVAL upon failure
13670 - */
13671 -static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
13672 -{
13673 -       if ((new_mtu > 9500) || (new_mtu < 64))
13674 -               return -EINVAL;
13675 -
13676 -       dev->mtu = new_mtu;
13677 -       if (!netif_running(dev))
13678 -               return 0;
13679 -
13680 -       /*
13681 -        * Stop and then re-open the interface. This will allocate RX
13682 -        * skbs of the new MTU.
13683 -        * There is a possible danger that the open will not succeed,
13684 -        * due to memory being full, which might fail the open function.
13685 -        */
13686 -       mv643xx_eth_stop(dev);
13687 -       if (mv643xx_eth_open(dev)) {
13688 -               printk(KERN_ERR "%s: Fatal error on opening device\n",
13689 -                       dev->name);
13690 -       }
13691 -
13692 -       return 0;
13693 -}
13694
13695 -/*
13696 - * mv643xx_eth_rx_refill_descs
13697 - *
13698 - * Fills / refills RX queue on a certain gigabit ethernet port
13699 - *
13700 - * Input :     pointer to ethernet interface network device structure
13701 - * Output :    N/A
13702 - */
13703 -static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
13704 +/* rxq/txq helper functions *************************************************/
13705 +static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
13706  {
13707 -       struct mv643xx_private *mp = netdev_priv(dev);
13708 -       struct pkt_info pkt_info;
13709 -       struct sk_buff *skb;
13710 -       int unaligned;
13711 -
13712 -       while (mp->rx_desc_count < mp->rx_ring_size) {
13713 -               skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
13714 -               if (!skb)
13715 -                       break;
13716 -               mp->rx_desc_count++;
13717 -               unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
13718 -               if (unaligned)
13719 -                       skb_reserve(skb, dma_get_cache_alignment() - unaligned);
13720 -               pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
13721 -               pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
13722 -               pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
13723 -                                       ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
13724 -               pkt_info.return_info = skb;
13725 -               if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
13726 -                       printk(KERN_ERR
13727 -                               "%s: Error allocating RX Ring\n", dev->name);
13728 -                       break;
13729 -               }
13730 -               skb_reserve(skb, ETH_HW_IP_ALIGN);
13731 -       }
13732 -       /*
13733 -        * If RX ring is empty of SKB, set a timer to try allocating
13734 -        * again at a later time.
13735 -        */
13736 -       if (mp->rx_desc_count == 0) {
13737 -               printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
13738 -               mp->timeout.expires = jiffies + (HZ / 10);      /* 100 mSec */
13739 -               add_timer(&mp->timeout);
13740 -       }
13741 +       return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
13742  }
13743
13744 -/*
13745 - * mv643xx_eth_rx_refill_descs_timer_wrapper
13746 - *
13747 - * Timer routine to wake up RX queue filling task. This function is
13748 - * used only in case the RX queue is empty, and all alloc_skb has
13749 - * failed (due to out of memory event).
13750 - *
13751 - * Input :     pointer to ethernet interface network device structure
13752 - * Output :    N/A
13753 - */
13754 -static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
13755 +static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
13756  {
13757 -       mv643xx_eth_rx_refill_descs((struct net_device *)data);
13758 +       return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13759  }
13760
13761 -/*
13762 - * mv643xx_eth_update_mac_address
13763 - *
13764 - * Update the MAC address of the port in the address table
13765 - *
13766 - * Input :     pointer to ethernet interface network device structure
13767 - * Output :    N/A
13768 - */
13769 -static void mv643xx_eth_update_mac_address(struct net_device *dev)
13770 +static void rxq_enable(struct rx_queue *rxq)
13771  {
13772 -       struct mv643xx_private *mp = netdev_priv(dev);
13773 -
13774 -       eth_port_init_mac_tables(mp);
13775 -       eth_port_uc_addr_set(mp, dev->dev_addr);
13776 +       struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
13777 +       wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
13778  }
13779
13780 -/*
13781 - * mv643xx_eth_set_rx_mode
13782 - *
13783 - * Change from promiscuos to regular rx mode
13784 - *
13785 - * Input :     pointer to ethernet interface network device structure
13786 - * Output :    N/A
13787 - */
13788 -static void mv643xx_eth_set_rx_mode(struct net_device *dev)
13789 +static void rxq_disable(struct rx_queue *rxq)
13790  {
13791 -       struct mv643xx_private *mp = netdev_priv(dev);
13792 -       u32 config_reg;
13793 -
13794 -       config_reg = rdl(mp, PORT_CONFIG_REG(mp->port_num));
13795 -       if (dev->flags & IFF_PROMISC)
13796 -               config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
13797 -       else
13798 -               config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
13799 -       wrl(mp, PORT_CONFIG_REG(mp->port_num), config_reg);
13800 +       struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
13801 +       u8 mask = 1 << rxq->index;
13802
13803 -       eth_port_set_multicast_list(dev);
13804 +       wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
13805 +       while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
13806 +               udelay(10);
13807  }
13808
13809 -/*
13810 - * mv643xx_eth_set_mac_address
13811 - *
13812 - * Change the interface's mac address.
13813 - * No special hardware thing should be done because interface is always
13814 - * put in promiscuous mode.
13815 - *
13816 - * Input :     pointer to ethernet interface network device structure and
13817 - *             a pointer to the designated entry to be added to the cache.
13818 - * Output :    zero upon success, negative upon failure
13819 - */
13820 -static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
13821 +static void txq_enable(struct tx_queue *txq)
13822  {
13823 -       int i;
13824 -
13825 -       for (i = 0; i < 6; i++)
13826 -               /* +2 is for the offset of the HW addr type */
13827 -               dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
13828 -       mv643xx_eth_update_mac_address(dev);
13829 -       return 0;
13830 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
13831 +       wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
13832  }
13833
13834 -/*
13835 - * mv643xx_eth_tx_timeout
13836 - *
13837 - * Called upon a timeout on transmitting a packet
13838 - *
13839 - * Input :     pointer to ethernet interface network device structure.
13840 - * Output :    N/A
13841 - */
13842 -static void mv643xx_eth_tx_timeout(struct net_device *dev)
13843 +static void txq_disable(struct tx_queue *txq)
13844  {
13845 -       struct mv643xx_private *mp = netdev_priv(dev);
13846 -
13847 -       printk(KERN_INFO "%s: TX timeout  ", dev->name);
13848 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
13849 +       u8 mask = 1 << txq->index;
13850
13851 -       /* Do the reset outside of interrupt context */
13852 -       schedule_work(&mp->tx_timeout_task);
13853 +       wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
13854 +       while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
13855 +               udelay(10);
13856  }
13857
13858 -/*
13859 - * mv643xx_eth_tx_timeout_task
13860 - *
13861 - * Actual routine to reset the adapter when a timeout on Tx has occurred
13862 - */
13863 -static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
13864 +static void __txq_maybe_wake(struct tx_queue *txq)
13865  {
13866 -       struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
13867 -                                                 tx_timeout_task);
13868 -       struct net_device *dev = mp->dev;
13869 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
13870
13871 -       if (!netif_running(dev))
13872 -               return;
13873 +       /*
13874 +        * netif_{stop,wake}_queue() flow control only applies to
13875 +        * the primary queue.
13876 +        */
13877 +       BUG_ON(txq->index != mp->txq_primary);
13878
13879 -       netif_stop_queue(dev);
13880 +       if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
13881 +               netif_wake_queue(mp->dev);
13882 +}
13883
13884 -       eth_port_reset(mp);
13885 -       eth_port_start(dev);
13886
13887 -       if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
13888 -               netif_wake_queue(dev);
13889 -}
13890 +/* rx ***********************************************************************/
13891 +static void txq_reclaim(struct tx_queue *txq, int force);
13892
13893 -/**
13894 - * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
13895 - *
13896 - * If force is non-zero, frees uncompleted descriptors as well
13897 - */
13898 -static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
13899 +static void rxq_refill(struct rx_queue *rxq)
13900  {
13901 -       struct mv643xx_private *mp = netdev_priv(dev);
13902 -       struct eth_tx_desc *desc;
13903 -       u32 cmd_sts;
13904 -       struct sk_buff *skb;
13905 +       struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
13906         unsigned long flags;
13907 -       int tx_index;
13908 -       dma_addr_t addr;
13909 -       int count;
13910 -       int released = 0;
13911 -
13912 -       while (mp->tx_desc_count > 0) {
13913 -               spin_lock_irqsave(&mp->lock, flags);
13914 -
13915 -               /* tx_desc_count might have changed before acquiring the lock */
13916 -               if (mp->tx_desc_count <= 0) {
13917 -                       spin_unlock_irqrestore(&mp->lock, flags);
13918 -                       return released;
13919 -               }
13920 -
13921 -               tx_index = mp->tx_used_desc_q;
13922 -               desc = &mp->p_tx_desc_area[tx_index];
13923 -               cmd_sts = desc->cmd_sts;
13924
13925 -               if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
13926 -                       spin_unlock_irqrestore(&mp->lock, flags);
13927 -                       return released;
13928 -               }
13929 +       spin_lock_irqsave(&mp->lock, flags);
13930
13931 -               mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
13932 -               mp->tx_desc_count--;
13933 +       while (rxq->rx_desc_count < rxq->rx_ring_size) {
13934 +               int skb_size;
13935 +               struct sk_buff *skb;
13936 +               int unaligned;
13937 +               int rx;
13938
13939 -               addr = desc->buf_ptr;
13940 -               count = desc->byte_cnt;
13941 -               skb = mp->tx_skb[tx_index];
13942 -               if (skb)
13943 -                       mp->tx_skb[tx_index] = NULL;
13944 +               /*
13945 +                * Reserve 2+14 bytes for an ethernet header (the
13946 +                * hardware automatically prepends 2 bytes of dummy
13947 +                * data to each received packet), 4 bytes for a VLAN
13948 +                * header, and 4 bytes for the trailing FCS -- 24
13949 +                * bytes total.
13950 +                */
13951 +               skb_size = mp->dev->mtu + 24;
13952
13953 -               if (cmd_sts & ETH_ERROR_SUMMARY) {
13954 -                       printk("%s: Error in TX\n", dev->name);
13955 -                       dev->stats.tx_errors++;
13956 -               }
13957 +               skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
13958 +               if (skb == NULL)
13959 +                       break;
13960
13961 -               spin_unlock_irqrestore(&mp->lock, flags);
13962 +               unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
13963 +               if (unaligned)
13964 +                       skb_reserve(skb, dma_get_cache_alignment() - unaligned);
13965
13966 -               if (cmd_sts & ETH_TX_FIRST_DESC)
13967 -                       dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
13968 -               else
13969 -                       dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
13970 +               rxq->rx_desc_count++;
13971 +               rx = rxq->rx_used_desc;
13972 +               rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
13973 +
13974 +               rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
13975 +                                               skb_size, DMA_FROM_DEVICE);
13976 +               rxq->rx_desc_area[rx].buf_size = skb_size;
13977 +               rxq->rx_skb[rx] = skb;
13978 +               wmb();
13979 +               rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
13980 +                                               RX_ENABLE_INTERRUPT;
13981 +               wmb();
13982
13983 -               if (skb)
13984 -                       dev_kfree_skb_irq(skb);
13985 +               /*
13986 +                * The hardware automatically prepends 2 bytes of
13987 +                * dummy data to each received packet, so that the
13988 +                * IP header ends up 16-byte aligned.
13989 +                */
13990 +               skb_reserve(skb, 2);
13991 +       }
13992
13993 -               released = 1;
13994 +       if (rxq->rx_desc_count != rxq->rx_ring_size) {
13995 +               rxq->rx_oom.expires = jiffies + (HZ / 10);
13996 +               add_timer(&rxq->rx_oom);
13997         }
13998
13999 -       return released;
14000 +       spin_unlock_irqrestore(&mp->lock, flags);
14001  }
14002
14003 -static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
14004 +static inline void rxq_refill_timer_wrapper(unsigned long data)
14005  {
14006 -       struct mv643xx_private *mp = netdev_priv(dev);
14007 -
14008 -       if (mv643xx_eth_free_tx_descs(dev, 0) &&
14009 -           mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
14010 -               netif_wake_queue(dev);
14011 +       rxq_refill((struct rx_queue *)data);
14012  }
14013
14014 -static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
14015 +static int rxq_process(struct rx_queue *rxq, int budget)
14016  {
14017 -       mv643xx_eth_free_tx_descs(dev, 1);
14018 -}
14019 +       struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
14020 +       struct net_device_stats *stats = &mp->dev->stats;
14021 +       int rx;
14022
14023 -/*
14024 - * mv643xx_eth_receive
14025 - *
14026 - * This function is forward packets that are received from the port's
14027 - * queues toward kernel core or FastRoute them to another interface.
14028 - *
14029 - * Input :     dev - a pointer to the required interface
14030 - *             max - maximum number to receive (0 means unlimted)
14031 - *
14032 - * Output :    number of served packets
14033 - */
14034 -static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
14035 -{
14036 -       struct mv643xx_private *mp = netdev_priv(dev);
14037 -       struct net_device_stats *stats = &dev->stats;
14038 -       unsigned int received_packets = 0;
14039 -       struct sk_buff *skb;
14040 -       struct pkt_info pkt_info;
14041 -
14042 -       while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
14043 -               dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
14044 -                                                       DMA_FROM_DEVICE);
14045 -               mp->rx_desc_count--;
14046 -               received_packets++;
14047 +       rx = 0;
14048 +       while (rx < budget) {
14049 +               struct rx_desc *rx_desc;
14050 +               unsigned int cmd_sts;
14051 +               struct sk_buff *skb;
14052 +               unsigned long flags;
14053 +
14054 +               spin_lock_irqsave(&mp->lock, flags);
14055 +
14056 +               rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
14057 +
14058 +               cmd_sts = rx_desc->cmd_sts;
14059 +               if (cmd_sts & BUFFER_OWNED_BY_DMA) {
14060 +                       spin_unlock_irqrestore(&mp->lock, flags);
14061 +                       break;
14062 +               }
14063 +               rmb();
14064 +
14065 +               skb = rxq->rx_skb[rxq->rx_curr_desc];
14066 +               rxq->rx_skb[rxq->rx_curr_desc] = NULL;
14067 +
14068 +               rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
14069 +
14070 +               spin_unlock_irqrestore(&mp->lock, flags);
14071 +
14072 +               dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
14073 +                                mp->dev->mtu + 24, DMA_FROM_DEVICE);
14074 +               rxq->rx_desc_count--;
14075 +               rx++;
14076
14077                 /*
14078                  * Update statistics.
14079 -                * Note byte count includes 4 byte CRC count
14080 +                *
14081 +                * Note that the descriptor byte count includes 2 dummy
14082 +                * bytes automatically inserted by the hardware at the
14083 +                * start of the packet (which we don't count), and a 4
14084 +                * byte CRC at the end of the packet (which we do count).
14085                  */
14086                 stats->rx_packets++;
14087 -               stats->rx_bytes += pkt_info.byte_cnt;
14088 -               skb = pkt_info.return_info;
14089 +               stats->rx_bytes += rx_desc->byte_cnt - 2;
14090 +
14091                 /*
14092 -                * In case received a packet without first / last bits on OR
14093 -                * the error summary bit is on, the packets needs to be dropeed.
14094 +                * In case we received a packet without first / last bits
14095 +                * on, or the error summary bit is set, the packet needs
14096 +                * to be dropped.
14097                  */
14098 -               if (((pkt_info.cmd_sts
14099 -                               & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
14100 -                                       (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
14101 -                               || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
14102 +               if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
14103 +                                       (RX_FIRST_DESC | RX_LAST_DESC))
14104 +                               || (cmd_sts & ERROR_SUMMARY)) {
14105                         stats->rx_dropped++;
14106 -                       if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
14107 -                                                       ETH_RX_LAST_DESC)) !=
14108 -                               (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
14109 +
14110 +                       if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
14111 +                               (RX_FIRST_DESC | RX_LAST_DESC)) {
14112                                 if (net_ratelimit())
14113 -                                       printk(KERN_ERR
14114 -                                               "%s: Received packet spread "
14115 -                                               "on multiple descriptors\n",
14116 -                                               dev->name);
14117 +                                       dev_printk(KERN_ERR, &mp->dev->dev,
14118 +                                                  "received packet spanning "
14119 +                                                  "multiple descriptors\n");
14120                         }
14121 -                       if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
14122 +
14123 +                       if (cmd_sts & ERROR_SUMMARY)
14124                                 stats->rx_errors++;
14125
14126                         dev_kfree_skb_irq(skb);
14127 @@ -975,668 +576,120 @@
14128                          * The -4 is for the CRC in the trailer of the
14129                          * received packet
14130                          */
14131 -                       skb_put(skb, pkt_info.byte_cnt - 4);
14132 +                       skb_put(skb, rx_desc->byte_cnt - 2 - 4);
14133
14134 -                       if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
14135 +                       if (cmd_sts & LAYER_4_CHECKSUM_OK) {
14136                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
14137                                 skb->csum = htons(
14138 -                                       (pkt_info.cmd_sts & 0x0007fff8) >> 3);
14139 +                                       (cmd_sts & 0x0007fff8) >> 3);
14140                         }
14141 -                       skb->protocol = eth_type_trans(skb, dev);
14142 -#ifdef MV643XX_NAPI
14143 +                       skb->protocol = eth_type_trans(skb, mp->dev);
14144 +#ifdef MV643XX_ETH_NAPI
14145                         netif_receive_skb(skb);
14146  #else
14147                         netif_rx(skb);
14148  #endif
14149                 }
14150 -               dev->last_rx = jiffies;
14151 +
14152 +               mp->dev->last_rx = jiffies;
14153         }
14154 -       mv643xx_eth_rx_refill_descs(dev);       /* Fill RX ring with skb's */
14155
14156 -       return received_packets;
14157 +       rxq_refill(rxq);
14158 +
14159 +       return rx;
14160  }
14161
14162 -/* Set the mv643xx port configuration register for the speed/duplex mode. */
14163 -static void mv643xx_eth_update_pscr(struct net_device *dev,
14164 -                                   struct ethtool_cmd *ecmd)
14165 +#ifdef MV643XX_ETH_NAPI
14166 +static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
14167  {
14168 -       struct mv643xx_private *mp = netdev_priv(dev);
14169 -       int port_num = mp->port_num;
14170 -       u32 o_pscr, n_pscr;
14171 -       unsigned int queues;
14172 +       struct mv643xx_eth_private *mp;
14173 +       int rx;
14174 +       int i;
14175
14176 -       o_pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
14177 -       n_pscr = o_pscr;
14178 +       mp = container_of(napi, struct mv643xx_eth_private, napi);
14179
14180 -       /* clear speed, duplex and rx buffer size fields */
14181 -       n_pscr &= ~(SET_MII_SPEED_TO_100  |
14182 -                  SET_GMII_SPEED_TO_1000 |
14183 -                  SET_FULL_DUPLEX_MODE   |
14184 -                  MAX_RX_PACKET_MASK);
14185 -
14186 -       if (ecmd->duplex == DUPLEX_FULL)
14187 -               n_pscr |= SET_FULL_DUPLEX_MODE;
14188 -
14189 -       if (ecmd->speed == SPEED_1000)
14190 -               n_pscr |= SET_GMII_SPEED_TO_1000 |
14191 -                         MAX_RX_PACKET_9700BYTE;
14192 -       else {
14193 -               if (ecmd->speed == SPEED_100)
14194 -                       n_pscr |= SET_MII_SPEED_TO_100;
14195 -               n_pscr |= MAX_RX_PACKET_1522BYTE;
14196 -       }
14197 -
14198 -       if (n_pscr != o_pscr) {
14199 -               if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
14200 -                       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
14201 -               else {
14202 -                       queues = mv643xx_eth_port_disable_tx(mp);
14203 +#ifdef MV643XX_ETH_TX_FAST_REFILL
14204 +       if (++mp->tx_clean_threshold > 5) {
14205 +               mp->tx_clean_threshold = 0;
14206 +               for (i = 0; i < 8; i++)
14207 +                       if (mp->txq_mask & (1 << i))
14208 +                               txq_reclaim(mp->txq + i, 0);
14209 +       }
14210 +#endif
14211
14212 -                       o_pscr &= ~SERIAL_PORT_ENABLE;
14213 -                       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
14214 -                       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
14215 -                       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
14216 -                       if (queues)
14217 -                               mv643xx_eth_port_enable_tx(mp, queues);
14218 -               }
14219 +       rx = 0;
14220 +       for (i = 7; rx < budget && i >= 0; i--)
14221 +               if (mp->rxq_mask & (1 << i))
14222 +                       rx += rxq_process(mp->rxq + i, budget - rx);
14223 +
14224 +       if (rx < budget) {
14225 +               netif_rx_complete(mp->dev, napi);
14226 +               wrl(mp, INT_CAUSE(mp->port_num), 0);
14227 +               wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
14228 +               wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
14229         }
14230 +
14231 +       return rx;
14232  }
14233 +#endif
14234
14235 -/*
14236 - * mv643xx_eth_int_handler
14237 - *
14238 - * Main interrupt handler for the gigbit ethernet ports
14239 - *
14240 - * Input :     irq     - irq number (not used)
14241 - *             dev_id  - a pointer to the required interface's data structure
14242 - *             regs    - not used
14243 - * Output :    N/A
14244 - */
14245
14246 -static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
14247 +/* tx ***********************************************************************/
14248 +static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
14249  {
14250 -       struct net_device *dev = (struct net_device *)dev_id;
14251 -       struct mv643xx_private *mp = netdev_priv(dev);
14252 -       u32 eth_int_cause, eth_int_cause_ext = 0;
14253 -       unsigned int port_num = mp->port_num;
14254 -
14255 -       /* Read interrupt cause registers */
14256 -       eth_int_cause = rdl(mp, INTERRUPT_CAUSE_REG(port_num)) &
14257 -                                               ETH_INT_UNMASK_ALL;
14258 -       if (eth_int_cause & ETH_INT_CAUSE_EXT) {
14259 -               eth_int_cause_ext = rdl(mp,
14260 -                       INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
14261 -                                               ETH_INT_UNMASK_ALL_EXT;
14262 -               wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num),
14263 -                                                       ~eth_int_cause_ext);
14264 -       }
14265 -
14266 -       /* PHY status changed */
14267 -       if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
14268 -               struct ethtool_cmd cmd;
14269 +       int frag;
14270
14271 -               if (mii_link_ok(&mp->mii)) {
14272 -                       mii_ethtool_gset(&mp->mii, &cmd);
14273 -                       mv643xx_eth_update_pscr(dev, &cmd);
14274 -                       mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
14275 -                       if (!netif_carrier_ok(dev)) {
14276 -                               netif_carrier_on(dev);
14277 -                               if (mp->tx_ring_size - mp->tx_desc_count >=
14278 -                                                       MAX_DESCS_PER_SKB)
14279 -                                       netif_wake_queue(dev);
14280 -                       }
14281 -               } else if (netif_carrier_ok(dev)) {
14282 -                       netif_stop_queue(dev);
14283 -                       netif_carrier_off(dev);
14284 -               }
14285 +       for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
14286 +               skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
14287 +               if (fragp->size <= 8 && fragp->page_offset & 7)
14288 +                       return 1;
14289         }
14290
14291 -#ifdef MV643XX_NAPI
14292 -       if (eth_int_cause & ETH_INT_CAUSE_RX) {
14293 -               /* schedule the NAPI poll routine to maintain port */
14294 -               wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
14295 +       return 0;
14296 +}
14297
14298 -               /* wait for previous write to complete */
14299 -               rdl(mp, INTERRUPT_MASK_REG(port_num));
14300 +static int txq_alloc_desc_index(struct tx_queue *txq)
14301 +{
14302 +       int tx_desc_curr;
14303
14304 -               netif_rx_schedule(dev, &mp->napi);
14305 -       }
14306 -#else
14307 -       if (eth_int_cause & ETH_INT_CAUSE_RX)
14308 -               mv643xx_eth_receive_queue(dev, INT_MAX);
14309 -#endif
14310 -       if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
14311 -               mv643xx_eth_free_completed_tx_descs(dev);
14312 +       BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
14313
14314 -       /*
14315 -        * If no real interrupt occured, exit.
14316 -        * This can happen when using gigE interrupt coalescing mechanism.
14317 -        */
14318 -       if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
14319 -               return IRQ_NONE;
14320 +       tx_desc_curr = txq->tx_curr_desc;
14321 +       txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
14322
14323 -       return IRQ_HANDLED;
14324 -}
14325 -
14326 -#ifdef MV643XX_COAL
14327 -
14328 -/*
14329 - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
14330 - *
14331 - * DESCRIPTION:
14332 - *     This routine sets the RX coalescing interrupt mechanism parameter.
14333 - *     This parameter is a timeout counter, that counts in 64 t_clk
14334 - *     chunks ; that when timeout event occurs a maskable interrupt
14335 - *     occurs.
14336 - *     The parameter is calculated using the tClk of the MV-643xx chip
14337 - *     , and the required delay of the interrupt in usec.
14338 - *
14339 - * INPUT:
14340 - *     struct mv643xx_private *mp      Ethernet port
14341 - *     unsigned int delay              Delay in usec
14342 - *
14343 - * OUTPUT:
14344 - *     Interrupt coalescing mechanism value is set in MV-643xx chip.
14345 - *
14346 - * RETURN:
14347 - *     The interrupt coalescing value set in the gigE port.
14348 - *
14349 - */
14350 -static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
14351 -                                       unsigned int delay)
14352 -{
14353 -       unsigned int port_num = mp->port_num;
14354 -       unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
14355 -
14356 -       /* Set RX Coalescing mechanism */
14357 -       wrl(mp, SDMA_CONFIG_REG(port_num),
14358 -               ((coal & 0x3fff) << 8) |
14359 -               (rdl(mp, SDMA_CONFIG_REG(port_num))
14360 -                       & 0xffc000ff));
14361 -
14362 -       return coal;
14363 -}
14364 -#endif
14365 -
14366 -/*
14367 - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
14368 - *
14369 - * DESCRIPTION:
14370 - *     This routine sets the TX coalescing interrupt mechanism parameter.
14371 - *     This parameter is a timeout counter, that counts in 64 t_clk
14372 - *     chunks ; that when timeout event occurs a maskable interrupt
14373 - *     occurs.
14374 - *     The parameter is calculated using the t_cLK frequency of the
14375 - *     MV-643xx chip and the required delay in the interrupt in uSec
14376 - *
14377 - * INPUT:
14378 - *     struct mv643xx_private *mp      Ethernet port
14379 - *     unsigned int delay              Delay in uSeconds
14380 - *
14381 - * OUTPUT:
14382 - *     Interrupt coalescing mechanism value is set in MV-643xx chip.
14383 - *
14384 - * RETURN:
14385 - *     The interrupt coalescing value set in the gigE port.
14386 - *
14387 - */
14388 -static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
14389 -                                       unsigned int delay)
14390 -{
14391 -       unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
14392 -
14393 -       /* Set TX Coalescing mechanism */
14394 -       wrl(mp, TX_FIFO_URGENT_THRESHOLD_REG(mp->port_num), coal << 4);
14395 -
14396 -       return coal;
14397 -}
14398 -
14399 -/*
14400 - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
14401 - *
14402 - * DESCRIPTION:
14403 - *     This function prepares a Rx chained list of descriptors and packet
14404 - *     buffers in a form of a ring. The routine must be called after port
14405 - *     initialization routine and before port start routine.
14406 - *     The Ethernet SDMA engine uses CPU bus addresses to access the various
14407 - *     devices in the system (i.e. DRAM). This function uses the ethernet
14408 - *     struct 'virtual to physical' routine (set by the user) to set the ring
14409 - *     with physical addresses.
14410 - *
14411 - * INPUT:
14412 - *     struct mv643xx_private *mp      Ethernet Port Control srtuct.
14413 - *
14414 - * OUTPUT:
14415 - *     The routine updates the Ethernet port control struct with information
14416 - *     regarding the Rx descriptors and buffers.
14417 - *
14418 - * RETURN:
14419 - *     None.
14420 - */
14421 -static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
14422 -{
14423 -       volatile struct eth_rx_desc *p_rx_desc;
14424 -       int rx_desc_num = mp->rx_ring_size;
14425 -       int i;
14426 -
14427 -       /* initialize the next_desc_ptr links in the Rx descriptors ring */
14428 -       p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
14429 -       for (i = 0; i < rx_desc_num; i++) {
14430 -               p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
14431 -                       ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
14432 -       }
14433 -
14434 -       /* Save Rx desc pointer to driver struct. */
14435 -       mp->rx_curr_desc_q = 0;
14436 -       mp->rx_used_desc_q = 0;
14437 -
14438 -       mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
14439 -}
14440 -
14441 -/*
14442 - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
14443 - *
14444 - * DESCRIPTION:
14445 - *     This function prepares a Tx chained list of descriptors and packet
14446 - *     buffers in a form of a ring. The routine must be called after port
14447 - *     initialization routine and before port start routine.
14448 - *     The Ethernet SDMA engine uses CPU bus addresses to access the various
14449 - *     devices in the system (i.e. DRAM). This function uses the ethernet
14450 - *     struct 'virtual to physical' routine (set by the user) to set the ring
14451 - *     with physical addresses.
14452 - *
14453 - * INPUT:
14454 - *     struct mv643xx_private *mp      Ethernet Port Control srtuct.
14455 - *
14456 - * OUTPUT:
14457 - *     The routine updates the Ethernet port control struct with information
14458 - *     regarding the Tx descriptors and buffers.
14459 - *
14460 - * RETURN:
14461 - *     None.
14462 - */
14463 -static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
14464 -{
14465 -       int tx_desc_num = mp->tx_ring_size;
14466 -       struct eth_tx_desc *p_tx_desc;
14467 -       int i;
14468 -
14469 -       /* Initialize the next_desc_ptr links in the Tx descriptors ring */
14470 -       p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
14471 -       for (i = 0; i < tx_desc_num; i++) {
14472 -               p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
14473 -                       ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
14474 -       }
14475 -
14476 -       mp->tx_curr_desc_q = 0;
14477 -       mp->tx_used_desc_q = 0;
14478 -
14479 -       mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
14480 -}
14481 -
14482 -static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
14483 -{
14484 -       struct mv643xx_private *mp = netdev_priv(dev);
14485 -       int err;
14486 -
14487 -       spin_lock_irq(&mp->lock);
14488 -       err = mii_ethtool_sset(&mp->mii, cmd);
14489 -       spin_unlock_irq(&mp->lock);
14490 -
14491 -       return err;
14492 -}
14493 -
14494 -static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
14495 -{
14496 -       struct mv643xx_private *mp = netdev_priv(dev);
14497 -       int err;
14498 -
14499 -       spin_lock_irq(&mp->lock);
14500 -       err = mii_ethtool_gset(&mp->mii, cmd);
14501 -       spin_unlock_irq(&mp->lock);
14502 -
14503 -       /* The PHY may support 1000baseT_Half, but the mv643xx does not */
14504 -       cmd->supported &= ~SUPPORTED_1000baseT_Half;
14505 -       cmd->advertising &= ~ADVERTISED_1000baseT_Half;
14506 -
14507 -       return err;
14508 -}
14509 -
14510 -/*
14511 - * mv643xx_eth_open
14512 - *
14513 - * This function is called when openning the network device. The function
14514 - * should initialize all the hardware, initialize cyclic Rx/Tx
14515 - * descriptors chain and buffers and allocate an IRQ to the network
14516 - * device.
14517 - *
14518 - * Input :     a pointer to the network device structure
14519 - *
14520 - * Output :    zero of success , nonzero if fails.
14521 - */
14522 -
14523 -static int mv643xx_eth_open(struct net_device *dev)
14524 -{
14525 -       struct mv643xx_private *mp = netdev_priv(dev);
14526 -       unsigned int port_num = mp->port_num;
14527 -       unsigned int size;
14528 -       int err;
14529 -
14530 -       /* Clear any pending ethernet port interrupts */
14531 -       wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
14532 -       wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
14533 -       /* wait for previous write to complete */
14534 -       rdl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num));
14535 -
14536 -       err = request_irq(dev->irq, mv643xx_eth_int_handler,
14537 -                       IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
14538 -       if (err) {
14539 -               printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
14540 -               return -EAGAIN;
14541 -       }
14542 -
14543 -       eth_port_init(mp);
14544 -
14545 -       memset(&mp->timeout, 0, sizeof(struct timer_list));
14546 -       mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
14547 -       mp->timeout.data = (unsigned long)dev;
14548 -
14549 -       /* Allocate RX and TX skb rings */
14550 -       mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
14551 -                                                               GFP_KERNEL);
14552 -       if (!mp->rx_skb) {
14553 -               printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
14554 -               err = -ENOMEM;
14555 -               goto out_free_irq;
14556 -       }
14557 -       mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
14558 -                                                               GFP_KERNEL);
14559 -       if (!mp->tx_skb) {
14560 -               printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
14561 -               err = -ENOMEM;
14562 -               goto out_free_rx_skb;
14563 -       }
14564 -
14565 -       /* Allocate TX ring */
14566 -       mp->tx_desc_count = 0;
14567 -       size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
14568 -       mp->tx_desc_area_size = size;
14569 -
14570 -       if (mp->tx_sram_size) {
14571 -               mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
14572 -                                                       mp->tx_sram_size);
14573 -               mp->tx_desc_dma = mp->tx_sram_addr;
14574 -       } else
14575 -               mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
14576 -                                                       &mp->tx_desc_dma,
14577 -                                                       GFP_KERNEL);
14578 -
14579 -       if (!mp->p_tx_desc_area) {
14580 -               printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
14581 -                                                       dev->name, size);
14582 -               err = -ENOMEM;
14583 -               goto out_free_tx_skb;
14584 -       }
14585 -       BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
14586 -       memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
14587 -
14588 -       ether_init_tx_desc_ring(mp);
14589 -
14590 -       /* Allocate RX ring */
14591 -       mp->rx_desc_count = 0;
14592 -       size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
14593 -       mp->rx_desc_area_size = size;
14594 -
14595 -       if (mp->rx_sram_size) {
14596 -               mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
14597 -                                                       mp->rx_sram_size);
14598 -               mp->rx_desc_dma = mp->rx_sram_addr;
14599 -       } else
14600 -               mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
14601 -                                                       &mp->rx_desc_dma,
14602 -                                                       GFP_KERNEL);
14603 -
14604 -       if (!mp->p_rx_desc_area) {
14605 -               printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
14606 -                                                       dev->name, size);
14607 -               printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
14608 -                                                       dev->name);
14609 -               if (mp->rx_sram_size)
14610 -                       iounmap(mp->p_tx_desc_area);
14611 -               else
14612 -                       dma_free_coherent(NULL, mp->tx_desc_area_size,
14613 -                                       mp->p_tx_desc_area, mp->tx_desc_dma);
14614 -               err = -ENOMEM;
14615 -               goto out_free_tx_skb;
14616 -       }
14617 -       memset((void *)mp->p_rx_desc_area, 0, size);
14618 -
14619 -       ether_init_rx_desc_ring(mp);
14620 -
14621 -       mv643xx_eth_rx_refill_descs(dev);       /* Fill RX ring with skb's */
14622 -
14623 -#ifdef MV643XX_NAPI
14624 -       napi_enable(&mp->napi);
14625 -#endif
14626 -
14627 -       eth_port_start(dev);
14628 -
14629 -       /* Interrupt Coalescing */
14630 -
14631 -#ifdef MV643XX_COAL
14632 -       mp->rx_int_coal =
14633 -               eth_port_set_rx_coal(mp, MV643XX_RX_COAL);
14634 -#endif
14635 -
14636 -       mp->tx_int_coal =
14637 -               eth_port_set_tx_coal(mp, MV643XX_TX_COAL);
14638 -
14639 -       /* Unmask phy and link status changes interrupts */
14640 -       wrl(mp, INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
14641 -
14642 -       /* Unmask RX buffer and TX end interrupt */
14643 -       wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
14644 -
14645 -       return 0;
14646 -
14647 -out_free_tx_skb:
14648 -       kfree(mp->tx_skb);
14649 -out_free_rx_skb:
14650 -       kfree(mp->rx_skb);
14651 -out_free_irq:
14652 -       free_irq(dev->irq, dev);
14653 -
14654 -       return err;
14655 -}
14656 -
14657 -static void mv643xx_eth_free_tx_rings(struct net_device *dev)
14658 -{
14659 -       struct mv643xx_private *mp = netdev_priv(dev);
14660 -
14661 -       /* Stop Tx Queues */
14662 -       mv643xx_eth_port_disable_tx(mp);
14663 -
14664 -       /* Free outstanding skb's on TX ring */
14665 -       mv643xx_eth_free_all_tx_descs(dev);
14666 -
14667 -       BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
14668 -
14669 -       /* Free TX ring */
14670 -       if (mp->tx_sram_size)
14671 -               iounmap(mp->p_tx_desc_area);
14672 -       else
14673 -               dma_free_coherent(NULL, mp->tx_desc_area_size,
14674 -                               mp->p_tx_desc_area, mp->tx_desc_dma);
14675 -}
14676 -
14677 -static void mv643xx_eth_free_rx_rings(struct net_device *dev)
14678 -{
14679 -       struct mv643xx_private *mp = netdev_priv(dev);
14680 -       int curr;
14681 -
14682 -       /* Stop RX Queues */
14683 -       mv643xx_eth_port_disable_rx(mp);
14684 -
14685 -       /* Free preallocated skb's on RX rings */
14686 -       for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
14687 -               if (mp->rx_skb[curr]) {
14688 -                       dev_kfree_skb(mp->rx_skb[curr]);
14689 -                       mp->rx_desc_count--;
14690 -               }
14691 -       }
14692 -
14693 -       if (mp->rx_desc_count)
14694 -               printk(KERN_ERR
14695 -                       "%s: Error in freeing Rx Ring. %d skb's still"
14696 -                       " stuck in RX Ring - ignoring them\n", dev->name,
14697 -                       mp->rx_desc_count);
14698 -       /* Free RX ring */
14699 -       if (mp->rx_sram_size)
14700 -               iounmap(mp->p_rx_desc_area);
14701 -       else
14702 -               dma_free_coherent(NULL, mp->rx_desc_area_size,
14703 -                               mp->p_rx_desc_area, mp->rx_desc_dma);
14704 -}
14705 -
14706 -/*
14707 - * mv643xx_eth_stop
14708 - *
14709 - * This function is used when closing the network device.
14710 - * It updates the hardware,
14711 - * release all memory that holds buffers and descriptors and release the IRQ.
14712 - * Input :     a pointer to the device structure
14713 - * Output :    zero if success , nonzero if fails
14714 - */
14715 -
14716 -static int mv643xx_eth_stop(struct net_device *dev)
14717 -{
14718 -       struct mv643xx_private *mp = netdev_priv(dev);
14719 -       unsigned int port_num = mp->port_num;
14720 -
14721 -       /* Mask all interrupts on ethernet port */
14722 -       wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
14723 -       /* wait for previous write to complete */
14724 -       rdl(mp, INTERRUPT_MASK_REG(port_num));
14725 -
14726 -#ifdef MV643XX_NAPI
14727 -       napi_disable(&mp->napi);
14728 -#endif
14729 -       netif_carrier_off(dev);
14730 -       netif_stop_queue(dev);
14731 -
14732 -       eth_port_reset(mp);
14733 -
14734 -       mv643xx_eth_free_tx_rings(dev);
14735 -       mv643xx_eth_free_rx_rings(dev);
14736 -
14737 -       free_irq(dev->irq, dev);
14738 -
14739 -       return 0;
14740 -}
14741 -
14742 -#ifdef MV643XX_NAPI
14743 -/*
14744 - * mv643xx_poll
14745 - *
14746 - * This function is used in case of NAPI
14747 - */
14748 -static int mv643xx_poll(struct napi_struct *napi, int budget)
14749 -{
14750 -       struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
14751 -       struct net_device *dev = mp->dev;
14752 -       unsigned int port_num = mp->port_num;
14753 -       int work_done;
14754 -
14755 -#ifdef MV643XX_TX_FAST_REFILL
14756 -       if (++mp->tx_clean_threshold > 5) {
14757 -               mv643xx_eth_free_completed_tx_descs(dev);
14758 -               mp->tx_clean_threshold = 0;
14759 -       }
14760 -#endif
14761 -
14762 -       work_done = 0;
14763 -       if ((rdl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
14764 -           != (u32) mp->rx_used_desc_q)
14765 -               work_done = mv643xx_eth_receive_queue(dev, budget);
14766 -
14767 -       if (work_done < budget) {
14768 -               netif_rx_complete(dev, napi);
14769 -               wrl(mp, INTERRUPT_CAUSE_REG(port_num), 0);
14770 -               wrl(mp, INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
14771 -               wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
14772 -       }
14773 -
14774 -       return work_done;
14775 -}
14776 -#endif
14777 -
14778 -/**
14779 - * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
14780 - *
14781 - * Hardware can't handle unaligned fragments smaller than 9 bytes.
14782 - * This helper function detects that case.
14783 - */
14784 -
14785 -static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
14786 -{
14787 -       unsigned int frag;
14788 -       skb_frag_t *fragp;
14789 -
14790 -       for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
14791 -               fragp = &skb_shinfo(skb)->frags[frag];
14792 -               if (fragp->size <= 8 && fragp->page_offset & 0x7)
14793 -                       return 1;
14794 -       }
14795 -       return 0;
14796 -}
14797 -
14798 -/**
14799 - * eth_alloc_tx_desc_index - return the index of the next available tx desc
14800 - */
14801 -static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
14802 -{
14803 -       int tx_desc_curr;
14804 -
14805 -       BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
14806 -
14807 -       tx_desc_curr = mp->tx_curr_desc_q;
14808 -       mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
14809 -
14810 -       BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
14811 +       BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
14812
14813         return tx_desc_curr;
14814  }
14815
14816 -/**
14817 - * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
14818 - *
14819 - * Ensure the data for each fragment to be transmitted is mapped properly,
14820 - * then fill in descriptors in the tx hw queue.
14821 - */
14822 -static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
14823 -                                  struct sk_buff *skb)
14824 +static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
14825  {
14826 +       int nr_frags = skb_shinfo(skb)->nr_frags;
14827         int frag;
14828 -       int tx_index;
14829 -       struct eth_tx_desc *desc;
14830 -
14831 -       for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
14832 -               skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
14833
14834 -               tx_index = eth_alloc_tx_desc_index(mp);
14835 -               desc = &mp->p_tx_desc_area[tx_index];
14836 +       for (frag = 0; frag < nr_frags; frag++) {
14837 +               skb_frag_t *this_frag;
14838 +               int tx_index;
14839 +               struct tx_desc *desc;
14840 +
14841 +               this_frag = &skb_shinfo(skb)->frags[frag];
14842 +               tx_index = txq_alloc_desc_index(txq);
14843 +               desc = &txq->tx_desc_area[tx_index];
14844
14845 -               desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
14846 -               /* Last Frag enables interrupt and frees the skb */
14847 -               if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
14848 -                       desc->cmd_sts |= ETH_ZERO_PADDING |
14849 -                                        ETH_TX_LAST_DESC |
14850 -                                        ETH_TX_ENABLE_INTERRUPT;
14851 -                       mp->tx_skb[tx_index] = skb;
14852 -               } else
14853 -                       mp->tx_skb[tx_index] = NULL;
14854 +               /*
14855 +                * The last fragment will generate an interrupt
14856 +                * which will free the skb on TX completion.
14857 +                */
14858 +               if (frag == nr_frags - 1) {
14859 +                       desc->cmd_sts = BUFFER_OWNED_BY_DMA |
14860 +                                       ZERO_PADDING | TX_LAST_DESC |
14861 +                                       TX_ENABLE_INTERRUPT;
14862 +                       txq->tx_skb[tx_index] = skb;
14863 +               } else {
14864 +                       desc->cmd_sts = BUFFER_OWNED_BY_DMA;
14865 +                       txq->tx_skb[tx_index] = NULL;
14866 +               }
14867
14868 -               desc = &mp->p_tx_desc_area[tx_index];
14869                 desc->l4i_chk = 0;
14870                 desc->byte_cnt = this_frag->size;
14871                 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
14872 @@ -1651,37 +704,28 @@
14873         return (__force __be16)sum;
14874  }
14875
14876 -/**
14877 - * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
14878 - *
14879 - * Ensure the data for an skb to be transmitted is mapped properly,
14880 - * then fill in descriptors in the tx hw queue and start the hardware.
14881 - */
14882 -static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
14883 -                                       struct sk_buff *skb)
14884 +static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
14885  {
14886 +       int nr_frags = skb_shinfo(skb)->nr_frags;
14887         int tx_index;
14888 -       struct eth_tx_desc *desc;
14889 +       struct tx_desc *desc;
14890         u32 cmd_sts;
14891         int length;
14892 -       int nr_frags = skb_shinfo(skb)->nr_frags;
14893
14894 -       cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
14895 +       cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
14896
14897 -       tx_index = eth_alloc_tx_desc_index(mp);
14898 -       desc = &mp->p_tx_desc_area[tx_index];
14899 +       tx_index = txq_alloc_desc_index(txq);
14900 +       desc = &txq->tx_desc_area[tx_index];
14901
14902         if (nr_frags) {
14903 -               eth_tx_fill_frag_descs(mp, skb);
14904 +               txq_submit_frag_skb(txq, skb);
14905
14906                 length = skb_headlen(skb);
14907 -               mp->tx_skb[tx_index] = NULL;
14908 +               txq->tx_skb[tx_index] = NULL;
14909         } else {
14910 -               cmd_sts |= ETH_ZERO_PADDING |
14911 -                          ETH_TX_LAST_DESC |
14912 -                          ETH_TX_ENABLE_INTERRUPT;
14913 +               cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
14914                 length = skb->len;
14915 -               mp->tx_skb[tx_index] = skb;
14916 +               txq->tx_skb[tx_index] = skb;
14917         }
14918
14919         desc->byte_cnt = length;
14920 @@ -1690,13 +734,13 @@
14921         if (skb->ip_summed == CHECKSUM_PARTIAL) {
14922                 BUG_ON(skb->protocol != htons(ETH_P_IP));
14923
14924 -               cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
14925 -                          ETH_GEN_IP_V_4_CHECKSUM  |
14926 -                          ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
14927 +               cmd_sts |= GEN_TCP_UDP_CHECKSUM |
14928 +                          GEN_IP_V4_CHECKSUM   |
14929 +                          ip_hdr(skb)->ihl << TX_IHL_SHIFT;
14930
14931                 switch (ip_hdr(skb)->protocol) {
14932                 case IPPROTO_UDP:
14933 -                       cmd_sts |= ETH_UDP_FRAME;
14934 +                       cmd_sts |= UDP_FRAME;
14935                         desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
14936                         break;
14937                 case IPPROTO_TCP:
14938 @@ -1707,7 +751,7 @@
14939                 }
14940         } else {
14941                 /* Errata BTS #50, IHL must be 5 if no HW checksum */
14942 -               cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
14943 +               cmd_sts |= 5 << TX_IHL_SHIFT;
14944                 desc->l4i_chk = 0;
14945         }
14946
14947 @@ -1717,1649 +761,1818 @@
14948
14949         /* ensure all descriptors are written before poking hardware */
14950         wmb();
14951 -       mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
14952 +       txq_enable(txq);
14953
14954 -       mp->tx_desc_count += nr_frags + 1;
14955 +       txq->tx_desc_count += nr_frags + 1;
14956  }
14957
14958 -/**
14959 - * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
14960 - *
14961 - */
14962 -static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
14963 +static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
14964  {
14965 -       struct mv643xx_private *mp = netdev_priv(dev);
14966 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
14967         struct net_device_stats *stats = &dev->stats;
14968 +       struct tx_queue *txq;
14969         unsigned long flags;
14970
14971 -       BUG_ON(netif_queue_stopped(dev));
14972 -
14973         if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
14974                 stats->tx_dropped++;
14975 -               printk(KERN_DEBUG "%s: failed to linearize tiny "
14976 -                               "unaligned fragment\n", dev->name);
14977 +               dev_printk(KERN_DEBUG, &dev->dev,
14978 +                          "failed to linearize skb with tiny "
14979 +                          "unaligned fragment\n");
14980                 return NETDEV_TX_BUSY;
14981         }
14982
14983         spin_lock_irqsave(&mp->lock, flags);
14984
14985 -       if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
14986 -               printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
14987 -               netif_stop_queue(dev);
14988 +       txq = mp->txq + mp->txq_primary;
14989 +
14990 +       if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
14991                 spin_unlock_irqrestore(&mp->lock, flags);
14992 -               return NETDEV_TX_BUSY;
14993 +               if (txq->index == mp->txq_primary && net_ratelimit())
14994 +                       dev_printk(KERN_ERR, &dev->dev,
14995 +                                  "primary tx queue full?!\n");
14996 +               kfree_skb(skb);
14997 +               return NETDEV_TX_OK;
14998         }
14999
15000 -       eth_tx_submit_descs_for_skb(mp, skb);
15001 +       txq_submit_skb(txq, skb);
15002         stats->tx_bytes += skb->len;
15003         stats->tx_packets++;
15004         dev->trans_start = jiffies;
15005
15006 -       if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
15007 -               netif_stop_queue(dev);
15008 +       if (txq->index == mp->txq_primary) {
15009 +               int entries_left;
15010 +
15011 +               entries_left = txq->tx_ring_size - txq->tx_desc_count;
15012 +               if (entries_left < MAX_DESCS_PER_SKB)
15013 +                       netif_stop_queue(dev);
15014 +       }
15015
15016         spin_unlock_irqrestore(&mp->lock, flags);
15017
15018         return NETDEV_TX_OK;
15019  }
15020
15021 -#ifdef CONFIG_NET_POLL_CONTROLLER
15022 -static void mv643xx_netpoll(struct net_device *netdev)
15023 +
15024 +/* tx rate control **********************************************************/
15025 +/*
15026 + * Set total maximum TX rate (shared by all TX queues for this port)
15027 + * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
15028 + */
15029 +static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
15030  {
15031 -       struct mv643xx_private *mp = netdev_priv(netdev);
15032 -       int port_num = mp->port_num;
15033 +       int token_rate;
15034 +       int mtu;
15035 +       int bucket_size;
15036 +
15037 +       token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
15038 +       if (token_rate > 1023)
15039 +               token_rate = 1023;
15040
15041 -       wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
15042 -       /* wait for previous write to complete */
15043 -       rdl(mp, INTERRUPT_MASK_REG(port_num));
15044 +       mtu = (mp->dev->mtu + 255) >> 8;
15045 +       if (mtu > 63)
15046 +               mtu = 63;
15047
15048 -       mv643xx_eth_int_handler(netdev->irq, netdev);
15049 +       bucket_size = (burst + 255) >> 8;
15050 +       if (bucket_size > 65535)
15051 +               bucket_size = 65535;
15052
15053 -       wrl(mp, INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
15054 +       if (mp->shared->tx_bw_control_moved) {
15055 +               wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
15056 +               wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
15057 +               wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
15058 +       } else {
15059 +               wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
15060 +               wrl(mp, TX_BW_MTU(mp->port_num), mtu);
15061 +               wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
15062 +       }
15063  }
15064 -#endif
15065
15066 -static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
15067 -                                    int speed, int duplex,
15068 -                                    struct ethtool_cmd *cmd)
15069 +static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
15070  {
15071 -       struct mv643xx_private *mp = netdev_priv(dev);
15072 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
15073 +       int token_rate;
15074 +       int bucket_size;
15075
15076 -       memset(cmd, 0, sizeof(*cmd));
15077 +       token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
15078 +       if (token_rate > 1023)
15079 +               token_rate = 1023;
15080
15081 -       cmd->port = PORT_MII;
15082 -       cmd->transceiver = XCVR_INTERNAL;
15083 -       cmd->phy_address = phy_address;
15084 +       bucket_size = (burst + 255) >> 8;
15085 +       if (bucket_size > 65535)
15086 +               bucket_size = 65535;
15087
15088 -       if (speed == 0) {
15089 -               cmd->autoneg = AUTONEG_ENABLE;
15090 -               /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
15091 -               cmd->speed = SPEED_100;
15092 -               cmd->advertising = ADVERTISED_10baseT_Half  |
15093 -                                  ADVERTISED_10baseT_Full  |
15094 -                                  ADVERTISED_100baseT_Half |
15095 -                                  ADVERTISED_100baseT_Full;
15096 -               if (mp->mii.supports_gmii)
15097 -                       cmd->advertising |= ADVERTISED_1000baseT_Full;
15098 -       } else {
15099 -               cmd->autoneg = AUTONEG_DISABLE;
15100 -               cmd->speed = speed;
15101 -               cmd->duplex = duplex;
15102 -       }
15103 +       wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
15104 +       wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
15105 +                       (bucket_size << 10) | token_rate);
15106  }
15107
15108 -/*/
15109 - * mv643xx_eth_probe
15110 - *
15111 - * First function called after registering the network device.
15112 - * It's purpose is to initialize the device as an ethernet device,
15113 - * fill the ethernet device structure with pointers * to functions,
15114 - * and set the MAC address of the interface
15115 - *
15116 - * Input :     struct device *
15117 - * Output :    -ENOMEM if failed , 0 if success
15118 - */
15119 -static int mv643xx_eth_probe(struct platform_device *pdev)
15120 +static void txq_set_fixed_prio_mode(struct tx_queue *txq)
15121  {
15122 -       struct mv643xx_eth_platform_data *pd;
15123 -       int port_num;
15124 -       struct mv643xx_private *mp;
15125 -       struct net_device *dev;
15126 -       u8 *p;
15127 -       struct resource *res;
15128 -       int err;
15129 -       struct ethtool_cmd cmd;
15130 -       int duplex = DUPLEX_HALF;
15131 -       int speed = 0;                  /* default to auto-negotiation */
15132 -       DECLARE_MAC_BUF(mac);
15133 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
15134 +       int off;
15135 +       u32 val;
15136
15137 -       pd = pdev->dev.platform_data;
15138 -       if (pd == NULL) {
15139 -               printk(KERN_ERR "No mv643xx_eth_platform_data\n");
15140 -               return -ENODEV;
15141 -       }
15142 +       /*
15143 +        * Turn on fixed priority mode.
15144 +        */
15145 +       if (mp->shared->tx_bw_control_moved)
15146 +               off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
15147 +       else
15148 +               off = TXQ_FIX_PRIO_CONF(mp->port_num);
15149
15150 -       if (pd->shared == NULL) {
15151 -               printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
15152 -               return -ENODEV;
15153 -       }
15154 +       val = rdl(mp, off);
15155 +       val |= 1 << txq->index;
15156 +       wrl(mp, off, val);
15157 +}
15158
15159 -       dev = alloc_etherdev(sizeof(struct mv643xx_private));
15160 -       if (!dev)
15161 -               return -ENOMEM;
15162 +static void txq_set_wrr(struct tx_queue *txq, int weight)
15163 +{
15164 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
15165 +       int off;
15166 +       u32 val;
15167
15168 -       platform_set_drvdata(pdev, dev);
15169 +       /*
15170 +        * Turn off fixed priority mode.
15171 +        */
15172 +       if (mp->shared->tx_bw_control_moved)
15173 +               off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
15174 +       else
15175 +               off = TXQ_FIX_PRIO_CONF(mp->port_num);
15176
15177 -       mp = netdev_priv(dev);
15178 -       mp->dev = dev;
15179 -#ifdef MV643XX_NAPI
15180 -       netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
15181 -#endif
15182 +       val = rdl(mp, off);
15183 +       val &= ~(1 << txq->index);
15184 +       wrl(mp, off, val);
15185
15186 -       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
15187 -       BUG_ON(!res);
15188 -       dev->irq = res->start;
15189 +       /*
15190 +        * Configure WRR weight for this queue.
15191 +        */
15192 +       off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
15193
15194 -       dev->open = mv643xx_eth_open;
15195 -       dev->stop = mv643xx_eth_stop;
15196 -       dev->hard_start_xmit = mv643xx_eth_start_xmit;
15197 -       dev->set_mac_address = mv643xx_eth_set_mac_address;
15198 -       dev->set_multicast_list = mv643xx_eth_set_rx_mode;
15199 +       val = rdl(mp, off);
15200 +       val = (val & ~0xff) | (weight & 0xff);
15201 +       wrl(mp, off, val);
15202 +}
15203
15204 -       /* No need to Tx Timeout */
15205 -       dev->tx_timeout = mv643xx_eth_tx_timeout;
15206
15207 -#ifdef CONFIG_NET_POLL_CONTROLLER
15208 -       dev->poll_controller = mv643xx_netpoll;
15209 -#endif
15210 +/* mii management interface *************************************************/
15211 +#define SMI_BUSY               0x10000000
15212 +#define SMI_READ_VALID         0x08000000
15213 +#define SMI_OPCODE_READ                0x04000000
15214 +#define SMI_OPCODE_WRITE       0x00000000
15215
15216 -       dev->watchdog_timeo = 2 * HZ;
15217 -       dev->base_addr = 0;
15218 -       dev->change_mtu = mv643xx_eth_change_mtu;
15219 -       dev->do_ioctl = mv643xx_eth_do_ioctl;
15220 -       SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
15221 +static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
15222 +                        unsigned int reg, unsigned int *value)
15223 +{
15224 +       void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
15225 +       unsigned long flags;
15226 +       int i;
15227 +
15228 +       /* the SMI register is a shared resource */
15229 +       spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
15230 +
15231 +       /* wait for the SMI register to become available */
15232 +       for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
15233 +               if (i == 1000) {
15234 +                       printk("%s: PHY busy timeout\n", mp->dev->name);
15235 +                       goto out;
15236 +               }
15237 +               udelay(10);
15238 +       }
15239 +
15240 +       writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
15241 +
15242 +       /* now wait for the data to be valid */
15243 +       for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
15244 +               if (i == 1000) {
15245 +                       printk("%s: PHY read timeout\n", mp->dev->name);
15246 +                       goto out;
15247 +               }
15248 +               udelay(10);
15249 +       }
15250 +
15251 +       *value = readl(smi_reg) & 0xffff;
15252 +out:
15253 +       spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
15254 +}
15255 +
15256 +static void smi_reg_write(struct mv643xx_eth_private *mp,
15257 +                         unsigned int addr,
15258 +                         unsigned int reg, unsigned int value)
15259 +{
15260 +       void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
15261 +       unsigned long flags;
15262 +       int i;
15263 +
15264 +       /* the SMI register is a shared resource */
15265 +       spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
15266 +
15267 +       /* wait for the SMI register to become available */
15268 +       for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
15269 +               if (i == 1000) {
15270 +                       printk("%s: PHY busy timeout\n", mp->dev->name);
15271 +                       goto out;
15272 +               }
15273 +               udelay(10);
15274 +       }
15275 +
15276 +       writel(SMI_OPCODE_WRITE | (reg << 21) |
15277 +               (addr << 16) | (value & 0xffff), smi_reg);
15278 +out:
15279 +       spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
15280 +}
15281 +
15282 +
15283 +/* mib counters *************************************************************/
15284 +static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
15285 +{
15286 +       return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
15287 +}
15288 +
15289 +static void mib_counters_clear(struct mv643xx_eth_private *mp)
15290 +{
15291 +       int i;
15292 +
15293 +       for (i = 0; i < 0x80; i += 4)
15294 +               mib_read(mp, i);
15295 +}
15296 +
15297 +static void mib_counters_update(struct mv643xx_eth_private *mp)
15298 +{
15299 +       struct mib_counters *p = &mp->mib_counters;
15300 +
15301 +       p->good_octets_received += mib_read(mp, 0x00);
15302 +       p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
15303 +       p->bad_octets_received += mib_read(mp, 0x08);
15304 +       p->internal_mac_transmit_err += mib_read(mp, 0x0c);
15305 +       p->good_frames_received += mib_read(mp, 0x10);
15306 +       p->bad_frames_received += mib_read(mp, 0x14);
15307 +       p->broadcast_frames_received += mib_read(mp, 0x18);
15308 +       p->multicast_frames_received += mib_read(mp, 0x1c);
15309 +       p->frames_64_octets += mib_read(mp, 0x20);
15310 +       p->frames_65_to_127_octets += mib_read(mp, 0x24);
15311 +       p->frames_128_to_255_octets += mib_read(mp, 0x28);
15312 +       p->frames_256_to_511_octets += mib_read(mp, 0x2c);
15313 +       p->frames_512_to_1023_octets += mib_read(mp, 0x30);
15314 +       p->frames_1024_to_max_octets += mib_read(mp, 0x34);
15315 +       p->good_octets_sent += mib_read(mp, 0x38);
15316 +       p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
15317 +       p->good_frames_sent += mib_read(mp, 0x40);
15318 +       p->excessive_collision += mib_read(mp, 0x44);
15319 +       p->multicast_frames_sent += mib_read(mp, 0x48);
15320 +       p->broadcast_frames_sent += mib_read(mp, 0x4c);
15321 +       p->unrec_mac_control_received += mib_read(mp, 0x50);
15322 +       p->fc_sent += mib_read(mp, 0x54);
15323 +       p->good_fc_received += mib_read(mp, 0x58);
15324 +       p->bad_fc_received += mib_read(mp, 0x5c);
15325 +       p->undersize_received += mib_read(mp, 0x60);
15326 +       p->fragments_received += mib_read(mp, 0x64);
15327 +       p->oversize_received += mib_read(mp, 0x68);
15328 +       p->jabber_received += mib_read(mp, 0x6c);
15329 +       p->mac_receive_error += mib_read(mp, 0x70);
15330 +       p->bad_crc_event += mib_read(mp, 0x74);
15331 +       p->collision += mib_read(mp, 0x78);
15332 +       p->late_collision += mib_read(mp, 0x7c);
15333 +}
15334 +
15335 +
15336 +/* ethtool ******************************************************************/
15337 +struct mv643xx_eth_stats {
15338 +       char stat_string[ETH_GSTRING_LEN];
15339 +       int sizeof_stat;
15340 +       int netdev_off;
15341 +       int mp_off;
15342 +};
15343 +
15344 +#define SSTAT(m)                                               \
15345 +       { #m, FIELD_SIZEOF(struct net_device_stats, m),         \
15346 +         offsetof(struct net_device, stats.m), -1 }
15347 +
15348 +#define MIBSTAT(m)                                             \
15349 +       { #m, FIELD_SIZEOF(struct mib_counters, m),             \
15350 +         -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
15351 +
15352 +static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
15353 +       SSTAT(rx_packets),
15354 +       SSTAT(tx_packets),
15355 +       SSTAT(rx_bytes),
15356 +       SSTAT(tx_bytes),
15357 +       SSTAT(rx_errors),
15358 +       SSTAT(tx_errors),
15359 +       SSTAT(rx_dropped),
15360 +       SSTAT(tx_dropped),
15361 +       MIBSTAT(good_octets_received),
15362 +       MIBSTAT(bad_octets_received),
15363 +       MIBSTAT(internal_mac_transmit_err),
15364 +       MIBSTAT(good_frames_received),
15365 +       MIBSTAT(bad_frames_received),
15366 +       MIBSTAT(broadcast_frames_received),
15367 +       MIBSTAT(multicast_frames_received),
15368 +       MIBSTAT(frames_64_octets),
15369 +       MIBSTAT(frames_65_to_127_octets),
15370 +       MIBSTAT(frames_128_to_255_octets),
15371 +       MIBSTAT(frames_256_to_511_octets),
15372 +       MIBSTAT(frames_512_to_1023_octets),
15373 +       MIBSTAT(frames_1024_to_max_octets),
15374 +       MIBSTAT(good_octets_sent),
15375 +       MIBSTAT(good_frames_sent),
15376 +       MIBSTAT(excessive_collision),
15377 +       MIBSTAT(multicast_frames_sent),
15378 +       MIBSTAT(broadcast_frames_sent),
15379 +       MIBSTAT(unrec_mac_control_received),
15380 +       MIBSTAT(fc_sent),
15381 +       MIBSTAT(good_fc_received),
15382 +       MIBSTAT(bad_fc_received),
15383 +       MIBSTAT(undersize_received),
15384 +       MIBSTAT(fragments_received),
15385 +       MIBSTAT(oversize_received),
15386 +       MIBSTAT(jabber_received),
15387 +       MIBSTAT(mac_receive_error),
15388 +       MIBSTAT(bad_crc_event),
15389 +       MIBSTAT(collision),
15390 +       MIBSTAT(late_collision),
15391 +};
15392 +
15393 +static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
15394 +{
15395 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15396 +       int err;
15397 +
15398 +       spin_lock_irq(&mp->lock);
15399 +       err = mii_ethtool_gset(&mp->mii, cmd);
15400 +       spin_unlock_irq(&mp->lock);
15401
15402 -#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
15403 -#ifdef MAX_SKB_FRAGS
15404         /*
15405 -        * Zero copy can only work if we use Discovery II memory. Else, we will
15406 -        * have to map the buffers to ISA memory which is only 16 MB
15407 +        * The MAC does not support 1000baseT_Half.
15408          */
15409 -       dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
15410 -#endif
15411 -#endif
15412 +       cmd->supported &= ~SUPPORTED_1000baseT_Half;
15413 +       cmd->advertising &= ~ADVERTISED_1000baseT_Half;
15414
15415 -       /* Configure the timeout task */
15416 -       INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
15417 +       return err;
15418 +}
15419
15420 -       spin_lock_init(&mp->lock);
15421 +static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
15422 +{
15423 +       cmd->supported = SUPPORTED_MII;
15424 +       cmd->advertising = ADVERTISED_MII;
15425 +       cmd->speed = SPEED_1000;
15426 +       cmd->duplex = DUPLEX_FULL;
15427 +       cmd->port = PORT_MII;
15428 +       cmd->phy_address = 0;
15429 +       cmd->transceiver = XCVR_INTERNAL;
15430 +       cmd->autoneg = AUTONEG_DISABLE;
15431 +       cmd->maxtxpkt = 1;
15432 +       cmd->maxrxpkt = 1;
15433
15434 -       mp->shared = platform_get_drvdata(pd->shared);
15435 -       port_num = mp->port_num = pd->port_number;
15436 +       return 0;
15437 +}
15438
15439 -       if (mp->shared->win_protect)
15440 -               wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
15441 +static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
15442 +{
15443 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15444 +       int err;
15445
15446 -       mp->shared_smi = mp->shared;
15447 -       if (pd->shared_smi != NULL)
15448 -               mp->shared_smi = platform_get_drvdata(pd->shared_smi);
15449 -
15450 -       /* set default config values */
15451 -       eth_port_uc_addr_get(mp, dev->dev_addr);
15452 -       mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
15453 -       mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
15454 +       /*
15455 +        * The MAC does not support 1000baseT_Half.
15456 +        */
15457 +       cmd->advertising &= ~ADVERTISED_1000baseT_Half;
15458
15459 -       if (is_valid_ether_addr(pd->mac_addr))
15460 -               memcpy(dev->dev_addr, pd->mac_addr, 6);
15461 +       spin_lock_irq(&mp->lock);
15462 +       err = mii_ethtool_sset(&mp->mii, cmd);
15463 +       spin_unlock_irq(&mp->lock);
15464
15465 -       if (pd->phy_addr || pd->force_phy_addr)
15466 -               ethernet_phy_set(mp, pd->phy_addr);
15467 +       return err;
15468 +}
15469
15470 -       if (pd->rx_queue_size)
15471 -               mp->rx_ring_size = pd->rx_queue_size;
15472 +static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
15473 +{
15474 +       return -EINVAL;
15475 +}
15476
15477 -       if (pd->tx_queue_size)
15478 -               mp->tx_ring_size = pd->tx_queue_size;
15479 +static void mv643xx_eth_get_drvinfo(struct net_device *dev,
15480 +                                   struct ethtool_drvinfo *drvinfo)
15481 +{
15482 +       strncpy(drvinfo->driver,  mv643xx_eth_driver_name, 32);
15483 +       strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
15484 +       strncpy(drvinfo->fw_version, "N/A", 32);
15485 +       strncpy(drvinfo->bus_info, "platform", 32);
15486 +       drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
15487 +}
15488 +
15489 +static int mv643xx_eth_nway_reset(struct net_device *dev)
15490 +{
15491 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15492
15493 -       if (pd->tx_sram_size) {
15494 -               mp->tx_sram_size = pd->tx_sram_size;
15495 -               mp->tx_sram_addr = pd->tx_sram_addr;
15496 +       return mii_nway_restart(&mp->mii);
15497 +}
15498 +
15499 +static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
15500 +{
15501 +       return -EINVAL;
15502 +}
15503 +
15504 +static u32 mv643xx_eth_get_link(struct net_device *dev)
15505 +{
15506 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15507 +
15508 +       return mii_link_ok(&mp->mii);
15509 +}
15510 +
15511 +static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
15512 +{
15513 +       return 1;
15514 +}
15515 +
15516 +static void mv643xx_eth_get_strings(struct net_device *dev,
15517 +                                   uint32_t stringset, uint8_t *data)
15518 +{
15519 +       int i;
15520 +
15521 +       if (stringset == ETH_SS_STATS) {
15522 +               for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
15523 +                       memcpy(data + i * ETH_GSTRING_LEN,
15524 +                               mv643xx_eth_stats[i].stat_string,
15525 +                               ETH_GSTRING_LEN);
15526 +               }
15527         }
15528 +}
15529 +
15530 +static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
15531 +                                         struct ethtool_stats *stats,
15532 +                                         uint64_t *data)
15533 +{
15534 +       struct mv643xx_eth_private *mp = dev->priv;
15535 +       int i;
15536 +
15537 +       mib_counters_update(mp);
15538 +
15539 +       for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
15540 +               const struct mv643xx_eth_stats *stat;
15541 +               void *p;
15542 +
15543 +               stat = mv643xx_eth_stats + i;
15544 +
15545 +               if (stat->netdev_off >= 0)
15546 +                       p = ((void *)mp->dev) + stat->netdev_off;
15547 +               else
15548 +                       p = ((void *)mp) + stat->mp_off;
15549
15550 -       if (pd->rx_sram_size) {
15551 -               mp->rx_sram_size = pd->rx_sram_size;
15552 -               mp->rx_sram_addr = pd->rx_sram_addr;
15553 +               data[i] = (stat->sizeof_stat == 8) ?
15554 +                               *(uint64_t *)p : *(uint32_t *)p;
15555         }
15556 +}
15557
15558 -       duplex = pd->duplex;
15559 -       speed = pd->speed;
15560 +static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
15561 +{
15562 +       if (sset == ETH_SS_STATS)
15563 +               return ARRAY_SIZE(mv643xx_eth_stats);
15564
15565 -       /* Hook up MII support for ethtool */
15566 -       mp->mii.dev = dev;
15567 -       mp->mii.mdio_read = mv643xx_mdio_read;
15568 -       mp->mii.mdio_write = mv643xx_mdio_write;
15569 -       mp->mii.phy_id = ethernet_phy_get(mp);
15570 -       mp->mii.phy_id_mask = 0x3f;
15571 -       mp->mii.reg_num_mask = 0x1f;
15572 +       return -EOPNOTSUPP;
15573 +}
15574
15575 -       err = ethernet_phy_detect(mp);
15576 -       if (err) {
15577 -               pr_debug("%s: No PHY detected at addr %d\n",
15578 -                               dev->name, ethernet_phy_get(mp));
15579 +static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
15580 +       .get_settings           = mv643xx_eth_get_settings,
15581 +       .set_settings           = mv643xx_eth_set_settings,
15582 +       .get_drvinfo            = mv643xx_eth_get_drvinfo,
15583 +       .nway_reset             = mv643xx_eth_nway_reset,
15584 +       .get_link               = mv643xx_eth_get_link,
15585 +       .set_sg                 = ethtool_op_set_sg,
15586 +       .get_strings            = mv643xx_eth_get_strings,
15587 +       .get_ethtool_stats      = mv643xx_eth_get_ethtool_stats,
15588 +       .get_sset_count         = mv643xx_eth_get_sset_count,
15589 +};
15590 +
15591 +static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
15592 +       .get_settings           = mv643xx_eth_get_settings_phyless,
15593 +       .set_settings           = mv643xx_eth_set_settings_phyless,
15594 +       .get_drvinfo            = mv643xx_eth_get_drvinfo,
15595 +       .nway_reset             = mv643xx_eth_nway_reset_phyless,
15596 +       .get_link               = mv643xx_eth_get_link_phyless,
15597 +       .set_sg                 = ethtool_op_set_sg,
15598 +       .get_strings            = mv643xx_eth_get_strings,
15599 +       .get_ethtool_stats      = mv643xx_eth_get_ethtool_stats,
15600 +       .get_sset_count         = mv643xx_eth_get_sset_count,
15601 +};
15602 +
15603 +
15604 +/* address handling *********************************************************/
15605 +static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
15606 +{
15607 +       unsigned int mac_h;
15608 +       unsigned int mac_l;
15609 +
15610 +       mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
15611 +       mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
15612 +
15613 +       addr[0] = (mac_h >> 24) & 0xff;
15614 +       addr[1] = (mac_h >> 16) & 0xff;
15615 +       addr[2] = (mac_h >> 8) & 0xff;
15616 +       addr[3] = mac_h & 0xff;
15617 +       addr[4] = (mac_l >> 8) & 0xff;
15618 +       addr[5] = mac_l & 0xff;
15619 +}
15620 +
15621 +static void init_mac_tables(struct mv643xx_eth_private *mp)
15622 +{
15623 +       int i;
15624 +
15625 +       for (i = 0; i < 0x100; i += 4) {
15626 +               wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
15627 +               wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
15628 +       }
15629 +
15630 +       for (i = 0; i < 0x10; i += 4)
15631 +               wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
15632 +}
15633 +
15634 +static void set_filter_table_entry(struct mv643xx_eth_private *mp,
15635 +                                  int table, unsigned char entry)
15636 +{
15637 +       unsigned int table_reg;
15638 +
15639 +       /* Set "accepts frame bit" at specified table entry */
15640 +       table_reg = rdl(mp, table + (entry & 0xfc));
15641 +       table_reg |= 0x01 << (8 * (entry & 3));
15642 +       wrl(mp, table + (entry & 0xfc), table_reg);
15643 +}
15644 +
15645 +static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
15646 +{
15647 +       unsigned int mac_h;
15648 +       unsigned int mac_l;
15649 +       int table;
15650 +
15651 +       mac_l = (addr[4] << 8) | addr[5];
15652 +       mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
15653 +
15654 +       wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
15655 +       wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
15656 +
15657 +       table = UNICAST_TABLE(mp->port_num);
15658 +       set_filter_table_entry(mp, table, addr[5] & 0x0f);
15659 +}
15660 +
15661 +static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
15662 +{
15663 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15664 +
15665 +       /* +2 is for the offset of the HW addr type */
15666 +       memcpy(dev->dev_addr, addr + 2, 6);
15667 +
15668 +       init_mac_tables(mp);
15669 +       uc_addr_set(mp, dev->dev_addr);
15670 +
15671 +       return 0;
15672 +}
15673 +
15674 +static int addr_crc(unsigned char *addr)
15675 +{
15676 +       int crc = 0;
15677 +       int i;
15678 +
15679 +       for (i = 0; i < 6; i++) {
15680 +               int j;
15681 +
15682 +               crc = (crc ^ addr[i]) << 8;
15683 +               for (j = 7; j >= 0; j--) {
15684 +                       if (crc & (0x100 << j))
15685 +                               crc ^= 0x107 << j;
15686 +               }
15687 +       }
15688 +
15689 +       return crc;
15690 +}
15691 +
15692 +static void mv643xx_eth_set_rx_mode(struct net_device *dev)
15693 +{
15694 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
15695 +       u32 port_config;
15696 +       struct dev_addr_list *addr;
15697 +       int i;
15698 +
15699 +       port_config = rdl(mp, PORT_CONFIG(mp->port_num));
15700 +       if (dev->flags & IFF_PROMISC)
15701 +               port_config |= UNICAST_PROMISCUOUS_MODE;
15702 +       else
15703 +               port_config &= ~UNICAST_PROMISCUOUS_MODE;
15704 +       wrl(mp, PORT_CONFIG(mp->port_num), port_config);
15705 +
15706 +       if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
15707 +               int port_num = mp->port_num;
15708 +               u32 accept = 0x01010101;
15709 +
15710 +               for (i = 0; i < 0x100; i += 4) {
15711 +                       wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
15712 +                       wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
15713 +               }
15714 +               return;
15715 +       }
15716 +
15717 +       for (i = 0; i < 0x100; i += 4) {
15718 +               wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
15719 +               wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
15720 +       }
15721 +
15722 +       for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
15723 +               u8 *a = addr->da_addr;
15724 +               int table;
15725 +
15726 +               if (addr->da_addrlen != 6)
15727 +                       continue;
15728 +
15729 +               if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
15730 +                       table = SPECIAL_MCAST_TABLE(mp->port_num);
15731 +                       set_filter_table_entry(mp, table, a[5]);
15732 +               } else {
15733 +                       int crc = addr_crc(a);
15734 +
15735 +                       table = OTHER_MCAST_TABLE(mp->port_num);
15736 +                       set_filter_table_entry(mp, table, crc);
15737 +               }
15738 +       }
15739 +}
15740 +
15741 +
15742 +/* rx/tx queue initialisation ***********************************************/
15743 +static int rxq_init(struct mv643xx_eth_private *mp, int index)
15744 +{
15745 +       struct rx_queue *rxq = mp->rxq + index;
15746 +       struct rx_desc *rx_desc;
15747 +       int size;
15748 +       int i;
15749 +
15750 +       rxq->index = index;
15751 +
15752 +       rxq->rx_ring_size = mp->default_rx_ring_size;
15753 +
15754 +       rxq->rx_desc_count = 0;
15755 +       rxq->rx_curr_desc = 0;
15756 +       rxq->rx_used_desc = 0;
15757 +
15758 +       size = rxq->rx_ring_size * sizeof(struct rx_desc);
15759 +
15760 +       if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
15761 +               rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
15762 +                                               mp->rx_desc_sram_size);
15763 +               rxq->rx_desc_dma = mp->rx_desc_sram_addr;
15764 +       } else {
15765 +               rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
15766 +                                                       &rxq->rx_desc_dma,
15767 +                                                       GFP_KERNEL);
15768 +       }
15769 +
15770 +       if (rxq->rx_desc_area == NULL) {
15771 +               dev_printk(KERN_ERR, &mp->dev->dev,
15772 +                          "can't allocate rx ring (%d bytes)\n", size);
15773                 goto out;
15774         }
15775 +       memset(rxq->rx_desc_area, 0, size);
15776
15777 -       ethernet_phy_reset(mp);
15778 -       mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
15779 -       mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
15780 -       mv643xx_eth_update_pscr(dev, &cmd);
15781 -       mv643xx_set_settings(dev, &cmd);
15782 +       rxq->rx_desc_area_size = size;
15783 +       rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
15784 +                                                               GFP_KERNEL);
15785 +       if (rxq->rx_skb == NULL) {
15786 +               dev_printk(KERN_ERR, &mp->dev->dev,
15787 +                          "can't allocate rx skb ring\n");
15788 +               goto out_free;
15789 +       }
15790
15791 -       SET_NETDEV_DEV(dev, &pdev->dev);
15792 -       err = register_netdev(dev);
15793 -       if (err)
15794 +       rx_desc = (struct rx_desc *)rxq->rx_desc_area;
15795 +       for (i = 0; i < rxq->rx_ring_size; i++) {
15796 +               int nexti = (i + 1) % rxq->rx_ring_size;
15797 +               rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
15798 +                                       nexti * sizeof(struct rx_desc);
15799 +       }
15800 +
15801 +       init_timer(&rxq->rx_oom);
15802 +       rxq->rx_oom.data = (unsigned long)rxq;
15803 +       rxq->rx_oom.function = rxq_refill_timer_wrapper;
15804 +
15805 +       return 0;
15806 +
15807 +
15808 +out_free:
15809 +       if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
15810 +               iounmap(rxq->rx_desc_area);
15811 +       else
15812 +               dma_free_coherent(NULL, size,
15813 +                                 rxq->rx_desc_area,
15814 +                                 rxq->rx_desc_dma);
15815 +
15816 +out:
15817 +       return -ENOMEM;
15818 +}
15819 +
15820 +static void rxq_deinit(struct rx_queue *rxq)
15821 +{
15822 +       struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
15823 +       int i;
15824 +
15825 +       rxq_disable(rxq);
15826 +
15827 +       del_timer_sync(&rxq->rx_oom);
15828 +
15829 +       for (i = 0; i < rxq->rx_ring_size; i++) {
15830 +               if (rxq->rx_skb[i]) {
15831 +                       dev_kfree_skb(rxq->rx_skb[i]);
15832 +                       rxq->rx_desc_count--;
15833 +               }
15834 +       }
15835 +
15836 +       if (rxq->rx_desc_count) {
15837 +               dev_printk(KERN_ERR, &mp->dev->dev,
15838 +                          "error freeing rx ring -- %d skbs stuck\n",
15839 +                          rxq->rx_desc_count);
15840 +       }
15841 +
15842 +       if (rxq->index == mp->rxq_primary &&
15843 +           rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
15844 +               iounmap(rxq->rx_desc_area);
15845 +       else
15846 +               dma_free_coherent(NULL, rxq->rx_desc_area_size,
15847 +                                 rxq->rx_desc_area, rxq->rx_desc_dma);
15848 +
15849 +       kfree(rxq->rx_skb);
15850 +}
15851 +
15852 +static int txq_init(struct mv643xx_eth_private *mp, int index)
15853 +{
15854 +       struct tx_queue *txq = mp->txq + index;
15855 +       struct tx_desc *tx_desc;
15856 +       int size;
15857 +       int i;
15858 +
15859 +       txq->index = index;
15860 +
15861 +       txq->tx_ring_size = mp->default_tx_ring_size;
15862 +
15863 +       txq->tx_desc_count = 0;
15864 +       txq->tx_curr_desc = 0;
15865 +       txq->tx_used_desc = 0;
15866 +
15867 +       size = txq->tx_ring_size * sizeof(struct tx_desc);
15868 +
15869 +       if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
15870 +               txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
15871 +                                               mp->tx_desc_sram_size);
15872 +               txq->tx_desc_dma = mp->tx_desc_sram_addr;
15873 +       } else {
15874 +               txq->tx_desc_area = dma_alloc_coherent(NULL, size,
15875 +                                                       &txq->tx_desc_dma,
15876 +                                                       GFP_KERNEL);
15877 +       }
15878 +
15879 +       if (txq->tx_desc_area == NULL) {
15880 +               dev_printk(KERN_ERR, &mp->dev->dev,
15881 +                          "can't allocate tx ring (%d bytes)\n", size);
15882                 goto out;
15883 +       }
15884 +       memset(txq->tx_desc_area, 0, size);
15885
15886 -       p = dev->dev_addr;
15887 -       printk(KERN_NOTICE
15888 -               "%s: port %d with MAC address %s\n",
15889 -               dev->name, port_num, print_mac(mac, p));
15890 +       txq->tx_desc_area_size = size;
15891 +       txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
15892 +                                                               GFP_KERNEL);
15893 +       if (txq->tx_skb == NULL) {
15894 +               dev_printk(KERN_ERR, &mp->dev->dev,
15895 +                          "can't allocate tx skb ring\n");
15896 +               goto out_free;
15897 +       }
15898
15899 -       if (dev->features & NETIF_F_SG)
15900 -               printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
15901 +       tx_desc = (struct tx_desc *)txq->tx_desc_area;
15902 +       for (i = 0; i < txq->tx_ring_size; i++) {
15903 +               int nexti = (i + 1) % txq->tx_ring_size;
15904 +               tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
15905 +                                       nexti * sizeof(struct tx_desc);
15906 +       }
15907
15908 -       if (dev->features & NETIF_F_IP_CSUM)
15909 -               printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
15910 -                                                               dev->name);
15911 +       return 0;
15912 +
15913 +
15914 +out_free:
15915 +       if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
15916 +               iounmap(txq->tx_desc_area);
15917 +       else
15918 +               dma_free_coherent(NULL, size,
15919 +                                 txq->tx_desc_area,
15920 +                                 txq->tx_desc_dma);
15921 +
15922 +out:
15923 +       return -ENOMEM;
15924 +}
15925 +
15926 +static void txq_reclaim(struct tx_queue *txq, int force)
15927 +{
15928 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
15929 +       unsigned long flags;
15930 +
15931 +       spin_lock_irqsave(&mp->lock, flags);
15932 +       while (txq->tx_desc_count > 0) {
15933 +               int tx_index;
15934 +               struct tx_desc *desc;
15935 +               u32 cmd_sts;
15936 +               struct sk_buff *skb;
15937 +               dma_addr_t addr;
15938 +               int count;
15939 +
15940 +               tx_index = txq->tx_used_desc;
15941 +               desc = &txq->tx_desc_area[tx_index];
15942 +               cmd_sts = desc->cmd_sts;
15943 +
15944 +               if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
15945 +                       break;
15946 +
15947 +               txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
15948 +               txq->tx_desc_count--;
15949 +
15950 +               addr = desc->buf_ptr;
15951 +               count = desc->byte_cnt;
15952 +               skb = txq->tx_skb[tx_index];
15953 +               txq->tx_skb[tx_index] = NULL;
15954 +
15955 +               if (cmd_sts & ERROR_SUMMARY) {
15956 +                       dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
15957 +                       mp->dev->stats.tx_errors++;
15958 +               }
15959 +
15960 +               /*
15961 +                * Drop mp->lock while we free the skb.
15962 +                */
15963 +               spin_unlock_irqrestore(&mp->lock, flags);
15964
15965 -#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
15966 -       printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
15967 +               if (cmd_sts & TX_FIRST_DESC)
15968 +                       dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
15969 +               else
15970 +                       dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
15971 +
15972 +               if (skb)
15973 +                       dev_kfree_skb_irq(skb);
15974 +
15975 +               spin_lock_irqsave(&mp->lock, flags);
15976 +       }
15977 +       spin_unlock_irqrestore(&mp->lock, flags);
15978 +}
15979 +
15980 +static void txq_deinit(struct tx_queue *txq)
15981 +{
15982 +       struct mv643xx_eth_private *mp = txq_to_mp(txq);
15983 +
15984 +       txq_disable(txq);
15985 +       txq_reclaim(txq, 1);
15986 +
15987 +       BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
15988 +
15989 +       if (txq->index == mp->txq_primary &&
15990 +           txq->tx_desc_area_size <= mp->tx_desc_sram_size)
15991 +               iounmap(txq->tx_desc_area);
15992 +       else
15993 +               dma_free_coherent(NULL, txq->tx_desc_area_size,
15994 +                                 txq->tx_desc_area, txq->tx_desc_dma);
15995 +
15996 +       kfree(txq->tx_skb);
15997 +}
15998 +
15999 +
16000 +/* netdev ops and related ***************************************************/
16001 +static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
16002 +{
16003 +       u32 pscr_o;
16004 +       u32 pscr_n;
16005 +
16006 +       pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
16007 +
16008 +       /* clear speed, duplex and rx buffer size fields */
16009 +       pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100   |
16010 +                           SET_GMII_SPEED_TO_1000 |
16011 +                           SET_FULL_DUPLEX_MODE   |
16012 +                           MAX_RX_PACKET_MASK);
16013 +
16014 +       if (speed == SPEED_1000) {
16015 +               pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
16016 +       } else {
16017 +               if (speed == SPEED_100)
16018 +                       pscr_n |= SET_MII_SPEED_TO_100;
16019 +               pscr_n |= MAX_RX_PACKET_1522BYTE;
16020 +       }
16021 +
16022 +       if (duplex == DUPLEX_FULL)
16023 +               pscr_n |= SET_FULL_DUPLEX_MODE;
16024 +
16025 +       if (pscr_n != pscr_o) {
16026 +               if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
16027 +                       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
16028 +               else {
16029 +                       int i;
16030 +
16031 +                       for (i = 0; i < 8; i++)
16032 +                               if (mp->txq_mask & (1 << i))
16033 +                                       txq_disable(mp->txq + i);
16034 +
16035 +                       pscr_o &= ~SERIAL_PORT_ENABLE;
16036 +                       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
16037 +                       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
16038 +                       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
16039 +
16040 +                       for (i = 0; i < 8; i++)
16041 +                               if (mp->txq_mask & (1 << i))
16042 +                                       txq_enable(mp->txq + i);
16043 +               }
16044 +       }
16045 +}
16046 +
16047 +static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
16048 +{
16049 +       struct net_device *dev = (struct net_device *)dev_id;
16050 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16051 +       u32 int_cause;
16052 +       u32 int_cause_ext;
16053 +       u32 txq_active;
16054 +
16055 +       int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
16056 +                       (INT_TX_END | INT_RX | INT_EXT);
16057 +       if (int_cause == 0)
16058 +               return IRQ_NONE;
16059 +
16060 +       int_cause_ext = 0;
16061 +       if (int_cause & INT_EXT) {
16062 +               int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
16063 +                               & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16064 +               wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
16065 +       }
16066 +
16067 +       if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
16068 +               if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
16069 +                       int i;
16070 +
16071 +                       if (mp->phy_addr != -1) {
16072 +                               struct ethtool_cmd cmd;
16073 +
16074 +                               mii_ethtool_gset(&mp->mii, &cmd);
16075 +                               update_pscr(mp, cmd.speed, cmd.duplex);
16076 +                       }
16077 +
16078 +                       for (i = 0; i < 8; i++)
16079 +                               if (mp->txq_mask & (1 << i))
16080 +                                       txq_enable(mp->txq + i);
16081 +
16082 +                       if (!netif_carrier_ok(dev)) {
16083 +                               netif_carrier_on(dev);
16084 +                               __txq_maybe_wake(mp->txq + mp->txq_primary);
16085 +                       }
16086 +               } else if (netif_carrier_ok(dev)) {
16087 +                       netif_stop_queue(dev);
16088 +                       netif_carrier_off(dev);
16089 +               }
16090 +       }
16091 +
16092 +       /*
16093 +        * RxBuffer or RxError set for any of the 8 queues?
16094 +        */
16095 +#ifdef MV643XX_ETH_NAPI
16096 +       if (int_cause & INT_RX) {
16097 +               wrl(mp, INT_MASK(mp->port_num), 0x00000000);
16098 +               rdl(mp, INT_MASK(mp->port_num));
16099 +
16100 +               netif_rx_schedule(dev, &mp->napi);
16101 +       }
16102 +#else
16103 +       if (int_cause & INT_RX) {
16104 +               int i;
16105 +
16106 +               for (i = 7; i >= 0; i--)
16107 +                       if (mp->rxq_mask & (1 << i))
16108 +                               rxq_process(mp->rxq + i, INT_MAX);
16109 +       }
16110  #endif
16111
16112 -#ifdef MV643XX_COAL
16113 -       printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
16114 -                                                               dev->name);
16115 -#endif
16116 +       txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
16117 +
16118 +       /*
16119 +        * TxBuffer or TxError set for any of the 8 queues?
16120 +        */
16121 +       if (int_cause_ext & INT_EXT_TX) {
16122 +               int i;
16123 +
16124 +               for (i = 0; i < 8; i++)
16125 +                       if (mp->txq_mask & (1 << i))
16126 +                               txq_reclaim(mp->txq + i, 0);
16127 +       }
16128 +
16129 +       /*
16130 +        * Any TxEnd interrupts?
16131 +        */
16132 +       if (int_cause & INT_TX_END) {
16133 +               int i;
16134 +
16135 +               wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
16136 +               for (i = 0; i < 8; i++) {
16137 +                       struct tx_queue *txq = mp->txq + i;
16138 +                       if (txq->tx_desc_count && !((txq_active >> i) & 1))
16139 +                               txq_enable(txq);
16140 +               }
16141 +       }
16142 +
16143 +       /*
16144 +        * Enough space again in the primary TX queue for a full packet?
16145 +        */
16146 +       if (int_cause_ext & INT_EXT_TX) {
16147 +               struct tx_queue *txq = mp->txq + mp->txq_primary;
16148 +               __txq_maybe_wake(txq);
16149 +       }
16150 +
16151 +       return IRQ_HANDLED;
16152 +}
16153 +
16154 +static void phy_reset(struct mv643xx_eth_private *mp)
16155 +{
16156 +       unsigned int data;
16157 +
16158 +       smi_reg_read(mp, mp->phy_addr, 0, &data);
16159 +       data |= 0x8000;
16160 +       smi_reg_write(mp, mp->phy_addr, 0, data);
16161 +
16162 +       do {
16163 +               udelay(1);
16164 +               smi_reg_read(mp, mp->phy_addr, 0, &data);
16165 +       } while (data & 0x8000);
16166 +}
16167 +
16168 +static void port_start(struct mv643xx_eth_private *mp)
16169 +{
16170 +       u32 pscr;
16171 +       int i;
16172 +
16173 +       /*
16174 +        * Configure basic link parameters.
16175 +        */
16176 +       pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
16177 +       pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
16178 +       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
16179 +       pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
16180 +               DISABLE_AUTO_NEG_SPEED_GMII    |
16181 +               DISABLE_AUTO_NEG_FOR_DUPLEX    |
16182 +               DO_NOT_FORCE_LINK_FAIL         |
16183 +               SERIAL_PORT_CONTROL_RESERVED;
16184 +       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
16185 +       pscr |= SERIAL_PORT_ENABLE;
16186 +       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
16187 +
16188 +       wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
16189 +
16190 +       /*
16191 +        * Perform PHY reset, if there is a PHY.
16192 +        */
16193 +       if (mp->phy_addr != -1) {
16194 +               struct ethtool_cmd cmd;
16195 +
16196 +               mv643xx_eth_get_settings(mp->dev, &cmd);
16197 +               phy_reset(mp);
16198 +               mv643xx_eth_set_settings(mp->dev, &cmd);
16199 +       }
16200 +
16201 +       /*
16202 +        * Configure TX path and queues.
16203 +        */
16204 +       tx_set_rate(mp, 1000000000, 16777216);
16205 +       for (i = 0; i < 8; i++) {
16206 +               struct tx_queue *txq = mp->txq + i;
16207 +               int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
16208 +               u32 addr;
16209 +
16210 +               if ((mp->txq_mask & (1 << i)) == 0)
16211 +                       continue;
16212 +
16213 +               addr = (u32)txq->tx_desc_dma;
16214 +               addr += txq->tx_curr_desc * sizeof(struct tx_desc);
16215 +               wrl(mp, off, addr);
16216 +
16217 +               txq_set_rate(txq, 1000000000, 16777216);
16218 +               txq_set_fixed_prio_mode(txq);
16219 +       }
16220 +
16221 +       /*
16222 +        * Add configured unicast address to address filter table.
16223 +        */
16224 +       uc_addr_set(mp, mp->dev->dev_addr);
16225 +
16226 +       /*
16227 +        * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
16228 +        * frames to RX queue #0.
16229 +        */
16230 +       wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
16231
16232 -#ifdef MV643XX_NAPI
16233 -       printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
16234 -#endif
16235 +       /*
16236 +        * Treat BPDUs as normal multicasts, and disable partition mode.
16237 +        */
16238 +       wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
16239
16240 -       if (mp->tx_sram_size > 0)
16241 -               printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
16242 +       /*
16243 +        * Enable the receive queues.
16244 +        */
16245 +       for (i = 0; i < 8; i++) {
16246 +               struct rx_queue *rxq = mp->rxq + i;
16247 +               int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
16248 +               u32 addr;
16249
16250 -       return 0;
16251 +               if ((mp->rxq_mask & (1 << i)) == 0)
16252 +                       continue;
16253
16254 -out:
16255 -       free_netdev(dev);
16256 +               addr = (u32)rxq->rx_desc_dma;
16257 +               addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
16258 +               wrl(mp, off, addr);
16259
16260 -       return err;
16261 +               rxq_enable(rxq);
16262 +       }
16263  }
16264
16265 -static int mv643xx_eth_remove(struct platform_device *pdev)
16266 +static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
16267  {
16268 -       struct net_device *dev = platform_get_drvdata(pdev);
16269 +       unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
16270 +       u32 val;
16271
16272 -       unregister_netdev(dev);
16273 -       flush_scheduled_work();
16274 +       val = rdl(mp, SDMA_CONFIG(mp->port_num));
16275 +       if (mp->shared->extended_rx_coal_limit) {
16276 +               if (coal > 0xffff)
16277 +                       coal = 0xffff;
16278 +               val &= ~0x023fff80;
16279 +               val |= (coal & 0x8000) << 10;
16280 +               val |= (coal & 0x7fff) << 7;
16281 +       } else {
16282 +               if (coal > 0x3fff)
16283 +                       coal = 0x3fff;
16284 +               val &= ~0x003fff00;
16285 +               val |= (coal & 0x3fff) << 8;
16286 +       }
16287 +       wrl(mp, SDMA_CONFIG(mp->port_num), val);
16288 +}
16289
16290 -       free_netdev(dev);
16291 -       platform_set_drvdata(pdev, NULL);
16292 -       return 0;
16293 +static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
16294 +{
16295 +       unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
16296 +
16297 +       if (coal > 0x3fff)
16298 +               coal = 0x3fff;
16299 +       wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16300  }
16301
16302 -static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
16303 -                                         struct mbus_dram_target_info *dram)
16304 +static int mv643xx_eth_open(struct net_device *dev)
16305  {
16306 -       void __iomem *base = msp->eth_base;
16307 -       u32 win_enable;
16308 -       u32 win_protect;
16309 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16310 +       int err;
16311         int i;
16312
16313 -       for (i = 0; i < 6; i++) {
16314 -               writel(0, base + WINDOW_BASE(i));
16315 -               writel(0, base + WINDOW_SIZE(i));
16316 -               if (i < 4)
16317 -                       writel(0, base + WINDOW_REMAP_HIGH(i));
16318 +       wrl(mp, INT_CAUSE(mp->port_num), 0);
16319 +       wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
16320 +       rdl(mp, INT_CAUSE_EXT(mp->port_num));
16321 +
16322 +       err = request_irq(dev->irq, mv643xx_eth_irq,
16323 +                         IRQF_SHARED | IRQF_SAMPLE_RANDOM,
16324 +                         dev->name, dev);
16325 +       if (err) {
16326 +               dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
16327 +               return -EAGAIN;
16328         }
16329
16330 -       win_enable = 0x3f;
16331 -       win_protect = 0;
16332 -
16333 -       for (i = 0; i < dram->num_cs; i++) {
16334 -               struct mbus_dram_window *cs = dram->cs + i;
16335 +       init_mac_tables(mp);
16336
16337 -               writel((cs->base & 0xffff0000) |
16338 -                       (cs->mbus_attr << 8) |
16339 -                       dram->mbus_dram_target_id, base + WINDOW_BASE(i));
16340 -               writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
16341 +       for (i = 0; i < 8; i++) {
16342 +               if ((mp->rxq_mask & (1 << i)) == 0)
16343 +                       continue;
16344 +
16345 +               err = rxq_init(mp, i);
16346 +               if (err) {
16347 +                       while (--i >= 0)
16348 +                               if (mp->rxq_mask & (1 << i))
16349 +                                       rxq_deinit(mp->rxq + i);
16350 +                       goto out;
16351 +               }
16352
16353 -               win_enable &= ~(1 << i);
16354 -               win_protect |= 3 << (2 * i);
16355 +               rxq_refill(mp->rxq + i);
16356         }
16357
16358 -       writel(win_enable, base + WINDOW_BAR_ENABLE);
16359 -       msp->win_protect = win_protect;
16360 -}
16361 -
16362 -static int mv643xx_eth_shared_probe(struct platform_device *pdev)
16363 -{
16364 -       static int mv643xx_version_printed = 0;
16365 -       struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
16366 -       struct mv643xx_shared_private *msp;
16367 -       struct resource *res;
16368 -       int ret;
16369 -
16370 -       if (!mv643xx_version_printed++)
16371 -               printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
16372 -
16373 -       ret = -EINVAL;
16374 -       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
16375 -       if (res == NULL)
16376 -               goto out;
16377 +       for (i = 0; i < 8; i++) {
16378 +               if ((mp->txq_mask & (1 << i)) == 0)
16379 +                       continue;
16380 +
16381 +               err = txq_init(mp, i);
16382 +               if (err) {
16383 +                       while (--i >= 0)
16384 +                               if (mp->txq_mask & (1 << i))
16385 +                                       txq_deinit(mp->txq + i);
16386 +                       goto out_free;
16387 +               }
16388 +       }
16389
16390 -       ret = -ENOMEM;
16391 -       msp = kmalloc(sizeof(*msp), GFP_KERNEL);
16392 -       if (msp == NULL)
16393 -               goto out;
16394 -       memset(msp, 0, sizeof(*msp));
16395 +#ifdef MV643XX_ETH_NAPI
16396 +       napi_enable(&mp->napi);
16397 +#endif
16398
16399 -       msp->eth_base = ioremap(res->start, res->end - res->start + 1);
16400 -       if (msp->eth_base == NULL)
16401 -               goto out_free;
16402 +       port_start(mp);
16403
16404 -       spin_lock_init(&msp->phy_lock);
16405 -       msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
16406 +       set_rx_coal(mp, 0);
16407 +       set_tx_coal(mp, 0);
16408
16409 -       platform_set_drvdata(pdev, msp);
16410 +       wrl(mp, INT_MASK_EXT(mp->port_num),
16411 +           INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16412
16413 -       /*
16414 -        * (Re-)program MBUS remapping windows if we are asked to.
16415 -        */
16416 -       if (pd != NULL && pd->dram != NULL)
16417 -               mv643xx_eth_conf_mbus_windows(msp, pd->dram);
16418 +       wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16419
16420         return 0;
16421
16422 +
16423  out_free:
16424 -       kfree(msp);
16425 +       for (i = 0; i < 8; i++)
16426 +               if (mp->rxq_mask & (1 << i))
16427 +                       rxq_deinit(mp->rxq + i);
16428  out:
16429 -       return ret;
16430 +       free_irq(dev->irq, dev);
16431 +
16432 +       return err;
16433  }
16434
16435 -static int mv643xx_eth_shared_remove(struct platform_device *pdev)
16436 +static void port_reset(struct mv643xx_eth_private *mp)
16437  {
16438 -       struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
16439 +       unsigned int data;
16440 +       int i;
16441
16442 -       iounmap(msp->eth_base);
16443 -       kfree(msp);
16444 +       for (i = 0; i < 8; i++) {
16445 +               if (mp->rxq_mask & (1 << i))
16446 +                       rxq_disable(mp->rxq + i);
16447 +               if (mp->txq_mask & (1 << i))
16448 +                       txq_disable(mp->txq + i);
16449 +       }
16450 +       while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
16451 +               udelay(10);
16452
16453 -       return 0;
16454 +       /* Reset the Enable bit in the Configuration Register */
16455 +       data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
16456 +       data &= ~(SERIAL_PORT_ENABLE            |
16457 +                 DO_NOT_FORCE_LINK_FAIL        |
16458 +                 FORCE_LINK_PASS);
16459 +       wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
16460  }
16461
16462 -static void mv643xx_eth_shutdown(struct platform_device *pdev)
16463 +static int mv643xx_eth_stop(struct net_device *dev)
16464  {
16465 -       struct net_device *dev = platform_get_drvdata(pdev);
16466 -       struct mv643xx_private *mp = netdev_priv(dev);
16467 -       unsigned int port_num = mp->port_num;
16468 -
16469 -       /* Mask all interrupts on ethernet port */
16470 -       wrl(mp, INTERRUPT_MASK_REG(port_num), 0);
16471 -       rdl(mp, INTERRUPT_MASK_REG(port_num));
16472 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16473 +       int i;
16474
16475 -       eth_port_reset(mp);
16476 -}
16477 +       wrl(mp, INT_MASK(mp->port_num), 0x00000000);
16478 +       rdl(mp, INT_MASK(mp->port_num));
16479
16480 -static struct platform_driver mv643xx_eth_driver = {
16481 -       .probe = mv643xx_eth_probe,
16482 -       .remove = mv643xx_eth_remove,
16483 -       .shutdown = mv643xx_eth_shutdown,
16484 -       .driver = {
16485 -               .name = MV643XX_ETH_NAME,
16486 -               .owner  = THIS_MODULE,
16487 -       },
16488 -};
16489 +#ifdef MV643XX_ETH_NAPI
16490 +       napi_disable(&mp->napi);
16491 +#endif
16492 +       netif_carrier_off(dev);
16493 +       netif_stop_queue(dev);
16494
16495 -static struct platform_driver mv643xx_eth_shared_driver = {
16496 -       .probe = mv643xx_eth_shared_probe,
16497 -       .remove = mv643xx_eth_shared_remove,
16498 -       .driver = {
16499 -               .name = MV643XX_ETH_SHARED_NAME,
16500 -               .owner  = THIS_MODULE,
16501 -       },
16502 -};
16503 +       free_irq(dev->irq, dev);
16504
16505 -/*
16506 - * mv643xx_init_module
16507 - *
16508 - * Registers the network drivers into the Linux kernel
16509 - *
16510 - * Input :     N/A
16511 - *
16512 - * Output :    N/A
16513 - */
16514 -static int __init mv643xx_init_module(void)
16515 -{
16516 -       int rc;
16517 +       port_reset(mp);
16518 +       mib_counters_update(mp);
16519
16520 -       rc = platform_driver_register(&mv643xx_eth_shared_driver);
16521 -       if (!rc) {
16522 -               rc = platform_driver_register(&mv643xx_eth_driver);
16523 -               if (rc)
16524 -                       platform_driver_unregister(&mv643xx_eth_shared_driver);
16525 +       for (i = 0; i < 8; i++) {
16526 +               if (mp->rxq_mask & (1 << i))
16527 +                       rxq_deinit(mp->rxq + i);
16528 +               if (mp->txq_mask & (1 << i))
16529 +                       txq_deinit(mp->txq + i);
16530         }
16531 -       return rc;
16532 -}
16533
16534 -/*
16535 - * mv643xx_cleanup_module
16536 - *
16537 - * Registers the network drivers into the Linux kernel
16538 - *
16539 - * Input :     N/A
16540 - *
16541 - * Output :    N/A
16542 - */
16543 -static void __exit mv643xx_cleanup_module(void)
16544 -{
16545 -       platform_driver_unregister(&mv643xx_eth_driver);
16546 -       platform_driver_unregister(&mv643xx_eth_shared_driver);
16547 +       return 0;
16548  }
16549
16550 -module_init(mv643xx_init_module);
16551 -module_exit(mv643xx_cleanup_module);
16552 -
16553 -MODULE_LICENSE("GPL");
16554 -MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
16555 -               " and Dale Farnsworth");
16556 -MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
16557 -MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
16558 -MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
16559 -
16560 -/*
16561 - * The second part is the low level driver of the gigE ethernet ports.
16562 - */
16563 -
16564 -/*
16565 - * Marvell's Gigabit Ethernet controller low level driver
16566 - *
16567 - * DESCRIPTION:
16568 - *     This file introduce low level API to Marvell's Gigabit Ethernet
16569 - *             controller. This Gigabit Ethernet Controller driver API controls
16570 - *             1) Operations (i.e. port init, start, reset etc').
16571 - *             2) Data flow (i.e. port send, receive etc').
16572 - *             Each Gigabit Ethernet port is controlled via
16573 - *             struct mv643xx_private.
16574 - *             This struct includes user configuration information as well as
16575 - *             driver internal data needed for its operations.
16576 - *
16577 - *             Supported Features:
16578 - *             - This low level driver is OS independent. Allocating memory for
16579 - *               the descriptor rings and buffers are not within the scope of
16580 - *               this driver.
16581 - *             - The user is free from Rx/Tx queue managing.
16582 - *             - This low level driver introduce functionality API that enable
16583 - *               the to operate Marvell's Gigabit Ethernet Controller in a
16584 - *               convenient way.
16585 - *             - Simple Gigabit Ethernet port operation API.
16586 - *             - Simple Gigabit Ethernet port data flow API.
16587 - *             - Data flow and operation API support per queue functionality.
16588 - *             - Support cached descriptors for better performance.
16589 - *             - Enable access to all four DRAM banks and internal SRAM memory
16590 - *               spaces.
16591 - *             - PHY access and control API.
16592 - *             - Port control register configuration API.
16593 - *             - Full control over Unicast and Multicast MAC configurations.
16594 - *
16595 - *             Operation flow:
16596 - *
16597 - *             Initialization phase
16598 - *             This phase complete the initialization of the the
16599 - *             mv643xx_private struct.
16600 - *             User information regarding port configuration has to be set
16601 - *             prior to calling the port initialization routine.
16602 - *
16603 - *             In this phase any port Tx/Rx activity is halted, MIB counters
16604 - *             are cleared, PHY address is set according to user parameter and
16605 - *             access to DRAM and internal SRAM memory spaces.
16606 - *
16607 - *             Driver ring initialization
16608 - *             Allocating memory for the descriptor rings and buffers is not
16609 - *             within the scope of this driver. Thus, the user is required to
16610 - *             allocate memory for the descriptors ring and buffers. Those
16611 - *             memory parameters are used by the Rx and Tx ring initialization
16612 - *             routines in order to curve the descriptor linked list in a form
16613 - *             of a ring.
16614 - *             Note: Pay special attention to alignment issues when using
16615 - *             cached descriptors/buffers. In this phase the driver store
16616 - *             information in the mv643xx_private struct regarding each queue
16617 - *             ring.
16618 - *
16619 - *             Driver start
16620 - *             This phase prepares the Ethernet port for Rx and Tx activity.
16621 - *             It uses the information stored in the mv643xx_private struct to
16622 - *             initialize the various port registers.
16623 - *
16624 - *             Data flow:
16625 - *             All packet references to/from the driver are done using
16626 - *             struct pkt_info.
16627 - *             This struct is a unified struct used with Rx and Tx operations.
16628 - *             This way the user is not required to be familiar with neither
16629 - *             Tx nor Rx descriptors structures.
16630 - *             The driver's descriptors rings are management by indexes.
16631 - *             Those indexes controls the ring resources and used to indicate
16632 - *             a SW resource error:
16633 - *             'current'
16634 - *             This index points to the current available resource for use. For
16635 - *             example in Rx process this index will point to the descriptor
16636 - *             that will be passed to the user upon calling the receive
16637 - *             routine.  In Tx process, this index will point to the descriptor
16638 - *             that will be assigned with the user packet info and transmitted.
16639 - *             'used'
16640 - *             This index points to the descriptor that need to restore its
16641 - *             resources. For example in Rx process, using the Rx buffer return
16642 - *             API will attach the buffer returned in packet info to the
16643 - *             descriptor pointed by 'used'. In Tx process, using the Tx
16644 - *             descriptor return will merely return the user packet info with
16645 - *             the command status of the transmitted buffer pointed by the
16646 - *             'used' index. Nevertheless, it is essential to use this routine
16647 - *             to update the 'used' index.
16648 - *             'first'
16649 - *             This index supports Tx Scatter-Gather. It points to the first
16650 - *             descriptor of a packet assembled of multiple buffers. For
16651 - *             example when in middle of Such packet we have a Tx resource
16652 - *             error the 'curr' index get the value of 'first' to indicate
16653 - *             that the ring returned to its state before trying to transmit
16654 - *             this packet.
16655 - *
16656 - *             Receive operation:
16657 - *             The eth_port_receive API set the packet information struct,
16658 - *             passed by the caller, with received information from the
16659 - *             'current' SDMA descriptor.
16660 - *             It is the user responsibility to return this resource back
16661 - *             to the Rx descriptor ring to enable the reuse of this source.
16662 - *             Return Rx resource is done using the eth_rx_return_buff API.
16663 - *
16664 - *     Prior to calling the initialization routine eth_port_init() the user
16665 - *     must set the following fields under mv643xx_private struct:
16666 - *     port_num                User Ethernet port number.
16667 - *     port_config             User port configuration value.
16668 - *     port_config_extend      User port config extend value.
16669 - *     port_sdma_config        User port SDMA config value.
16670 - *     port_serial_control     User port serial control value.
16671 - *
16672 - *             This driver data flow is done using the struct pkt_info which
16673 - *             is a unified struct for Rx and Tx operations:
16674 - *
16675 - *             byte_cnt        Tx/Rx descriptor buffer byte count.
16676 - *             l4i_chk         CPU provided TCP Checksum. For Tx operation
16677 - *                             only.
16678 - *             cmd_sts         Tx/Rx descriptor command status.
16679 - *             buf_ptr         Tx/Rx descriptor buffer pointer.
16680 - *             return_info     Tx/Rx user resource return information.
16681 - */
16682 -
16683 -/* Ethernet Port routines */
16684 -static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
16685 -                                           int table, unsigned char entry);
16686 -
16687 -/*
16688 - * eth_port_init - Initialize the Ethernet port driver
16689 - *
16690 - * DESCRIPTION:
16691 - *     This function prepares the ethernet port to start its activity:
16692 - *     1) Completes the ethernet port driver struct initialization toward port
16693 - *             start routine.
16694 - *     2) Resets the device to a quiescent state in case of warm reboot.
16695 - *     3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
16696 - *     4) Clean MAC tables. The reset status of those tables is unknown.
16697 - *     5) Set PHY address.
16698 - *     Note: Call this routine prior to eth_port_start routine and after
16699 - *     setting user values in the user fields of Ethernet port control
16700 - *     struct.
16701 - *
16702 - * INPUT:
16703 - *     struct mv643xx_private *mp      Ethernet port control struct
16704 - *
16705 - * OUTPUT:
16706 - *     See description.
16707 - *
16708 - * RETURN:
16709 - *     None.
16710 - */
16711 -static void eth_port_init(struct mv643xx_private *mp)
16712 +static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
16713  {
16714 -       mp->rx_resource_err = 0;
16715 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16716
16717 -       eth_port_reset(mp);
16718 +       if (mp->phy_addr != -1)
16719 +               return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
16720
16721 -       eth_port_init_mac_tables(mp);
16722 +       return -EOPNOTSUPP;
16723  }
16724
16725 -/*
16726 - * eth_port_start - Start the Ethernet port activity.
16727 - *
16728 - * DESCRIPTION:
16729 - *     This routine prepares the Ethernet port for Rx and Tx activity:
16730 - *      1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
16731 - *         has been initialized a descriptor's ring (using
16732 - *         ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
16733 - *      2. Initialize and enable the Ethernet configuration port by writing to
16734 - *         the port's configuration and command registers.
16735 - *      3. Initialize and enable the SDMA by writing to the SDMA's
16736 - *         configuration and command registers.  After completing these steps,
16737 - *         the ethernet port SDMA can starts to perform Rx and Tx activities.
16738 - *
16739 - *     Note: Each Rx and Tx queue descriptor's list must be initialized prior
16740 - *     to calling this function (use ether_init_tx_desc_ring for Tx queues
16741 - *     and ether_init_rx_desc_ring for Rx queues).
16742 - *
16743 - * INPUT:
16744 - *     dev - a pointer to the required interface
16745 - *
16746 - * OUTPUT:
16747 - *     Ethernet port is ready to receive and transmit.
16748 - *
16749 - * RETURN:
16750 - *     None.
16751 - */
16752 -static void eth_port_start(struct net_device *dev)
16753 +static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
16754  {
16755 -       struct mv643xx_private *mp = netdev_priv(dev);
16756 -       unsigned int port_num = mp->port_num;
16757 -       int tx_curr_desc, rx_curr_desc;
16758 -       u32 pscr;
16759 -       struct ethtool_cmd ethtool_cmd;
16760 -
16761 -       /* Assignment of Tx CTRP of given queue */
16762 -       tx_curr_desc = mp->tx_curr_desc_q;
16763 -       wrl(mp, TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
16764 -               (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
16765 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16766
16767 -       /* Assignment of Rx CRDP of given queue */
16768 -       rx_curr_desc = mp->rx_curr_desc_q;
16769 -       wrl(mp, RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
16770 -               (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
16771 -
16772 -       /* Add the assigned Ethernet address to the port's address table */
16773 -       eth_port_uc_addr_set(mp, dev->dev_addr);
16774 +       if (new_mtu < 64 || new_mtu > 9500)
16775 +               return -EINVAL;
16776
16777 -       /* Assign port configuration and command. */
16778 -       wrl(mp, PORT_CONFIG_REG(port_num),
16779 -                         PORT_CONFIG_DEFAULT_VALUE);
16780 +       dev->mtu = new_mtu;
16781 +       tx_set_rate(mp, 1000000000, 16777216);
16782
16783 -       wrl(mp, PORT_CONFIG_EXTEND_REG(port_num),
16784 -                         PORT_CONFIG_EXTEND_DEFAULT_VALUE);
16785 +       if (!netif_running(dev))
16786 +               return 0;
16787
16788 -       pscr = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
16789 +       /*
16790 +        * Stop and then re-open the interface. This will allocate RX
16791 +        * skbs of the new MTU.
16792 +        * There is a possible danger that the open will not succeed,
16793 +        * due to memory being full.
16794 +        */
16795 +       mv643xx_eth_stop(dev);
16796 +       if (mv643xx_eth_open(dev)) {
16797 +               dev_printk(KERN_ERR, &dev->dev,
16798 +                          "fatal error on re-opening device after "
16799 +                          "MTU change\n");
16800 +       }
16801
16802 -       pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
16803 -       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
16804 +       return 0;
16805 +}
16806
16807 -       pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
16808 -               DISABLE_AUTO_NEG_SPEED_GMII    |
16809 -               DISABLE_AUTO_NEG_FOR_DUPLX     |
16810 -               DO_NOT_FORCE_LINK_FAIL     |
16811 -               SERIAL_PORT_CONTROL_RESERVED;
16812 +static void tx_timeout_task(struct work_struct *ugly)
16813 +{
16814 +       struct mv643xx_eth_private *mp;
16815
16816 -       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
16817 +       mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
16818 +       if (netif_running(mp->dev)) {
16819 +               netif_stop_queue(mp->dev);
16820
16821 -       pscr |= SERIAL_PORT_ENABLE;
16822 -       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), pscr);
16823 +               port_reset(mp);
16824 +               port_start(mp);
16825
16826 -       /* Assign port SDMA configuration */
16827 -       wrl(mp, SDMA_CONFIG_REG(port_num),
16828 -                         PORT_SDMA_CONFIG_DEFAULT_VALUE);
16829 -
16830 -       /* Enable port Rx. */
16831 -       mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
16832 -
16833 -       /* Disable port bandwidth limits by clearing MTU register */
16834 -       wrl(mp, MAXIMUM_TRANSMIT_UNIT(port_num), 0);
16835 -
16836 -       /* save phy settings across reset */
16837 -       mv643xx_get_settings(dev, &ethtool_cmd);
16838 -       ethernet_phy_reset(mp);
16839 -       mv643xx_set_settings(dev, &ethtool_cmd);
16840 +               __txq_maybe_wake(mp->txq + mp->txq_primary);
16841 +       }
16842  }
16843
16844 -/*
16845 - * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
16846 - */
16847 -static void eth_port_uc_addr_set(struct mv643xx_private *mp,
16848 -                                unsigned char *p_addr)
16849 +static void mv643xx_eth_tx_timeout(struct net_device *dev)
16850  {
16851 -       unsigned int port_num = mp->port_num;
16852 -       unsigned int mac_h;
16853 -       unsigned int mac_l;
16854 -       int table;
16855 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16856
16857 -       mac_l = (p_addr[4] << 8) | (p_addr[5]);
16858 -       mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
16859 -                                                       (p_addr[3] << 0);
16860 -
16861 -       wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
16862 -       wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
16863 -
16864 -       /* Accept frames with this address */
16865 -       table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
16866 -       eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
16867 +       dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
16868 +
16869 +       schedule_work(&mp->tx_timeout_task);
16870  }
16871
16872 -/*
16873 - * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
16874 - */
16875 -static void eth_port_uc_addr_get(struct mv643xx_private *mp,
16876 -                                unsigned char *p_addr)
16877 +#ifdef CONFIG_NET_POLL_CONTROLLER
16878 +static void mv643xx_eth_netpoll(struct net_device *dev)
16879  {
16880 -       unsigned int port_num = mp->port_num;
16881 -       unsigned int mac_h;
16882 -       unsigned int mac_l;
16883 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16884 +
16885 +       wrl(mp, INT_MASK(mp->port_num), 0x00000000);
16886 +       rdl(mp, INT_MASK(mp->port_num));
16887
16888 -       mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
16889 -       mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
16890 +       mv643xx_eth_irq(dev->irq, dev);
16891
16892 -       p_addr[0] = (mac_h >> 24) & 0xff;
16893 -       p_addr[1] = (mac_h >> 16) & 0xff;
16894 -       p_addr[2] = (mac_h >> 8) & 0xff;
16895 -       p_addr[3] = mac_h & 0xff;
16896 -       p_addr[4] = (mac_l >> 8) & 0xff;
16897 -       p_addr[5] = mac_l & 0xff;
16898 +       wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
16899  }
16900 +#endif
16901
16902 -/*
16903 - * The entries in each table are indexed by a hash of a packet's MAC
16904 - * address.  One bit in each entry determines whether the packet is
16905 - * accepted.  There are 4 entries (each 8 bits wide) in each register
16906 - * of the table.  The bits in each entry are defined as follows:
16907 - *     0       Accept=1, Drop=0
16908 - *     3-1     Queue                   (ETH_Q0=0)
16909 - *     7-4     Reserved = 0;
16910 - */
16911 -static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
16912 -                                           int table, unsigned char entry)
16913 +static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
16914  {
16915 -       unsigned int table_reg;
16916 -       unsigned int tbl_offset;
16917 -       unsigned int reg_offset;
16918 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16919 +       int val;
16920
16921 -       tbl_offset = (entry / 4) * 4;   /* Register offset of DA table entry */
16922 -       reg_offset = entry % 4;         /* Entry offset within the register */
16923 +       smi_reg_read(mp, addr, reg, &val);
16924
16925 -       /* Set "accepts frame bit" at specified table entry */
16926 -       table_reg = rdl(mp, table + tbl_offset);
16927 -       table_reg |= 0x01 << (8 * reg_offset);
16928 -       wrl(mp, table + tbl_offset, table_reg);
16929 +       return val;
16930  }
16931
16932 -/*
16933 - * eth_port_mc_addr - Multicast address settings.
16934 - *
16935 - * The MV device supports multicast using two tables:
16936 - * 1) Special Multicast Table for MAC addresses of the form
16937 - *    0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
16938 - *    The MAC DA[7:0] bits are used as a pointer to the Special Multicast
16939 - *    Table entries in the DA-Filter table.
16940 - * 2) Other Multicast Table for multicast of another type. A CRC-8bit
16941 - *    is used as an index to the Other Multicast Table entries in the
16942 - *    DA-Filter table.  This function calculates the CRC-8bit value.
16943 - * In either case, eth_port_set_filter_table_entry() is then called
16944 - * to set to set the actual table entry.
16945 - */
16946 -static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
16947 +static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
16948  {
16949 -       unsigned int port_num = mp->port_num;
16950 -       unsigned int mac_h;
16951 -       unsigned int mac_l;
16952 -       unsigned char crc_result = 0;
16953 -       int table;
16954 -       int mac_array[48];
16955 -       int crc[8];
16956 -       int i;
16957 +       struct mv643xx_eth_private *mp = netdev_priv(dev);
16958 +       smi_reg_write(mp, addr, reg, val);
16959 +}
16960
16961 -       if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
16962 -           (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
16963 -               table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num);
16964 -               eth_port_set_filter_table_entry(mp, table, p_addr[5]);
16965 -               return;
16966 -       }
16967
16968 -       /* Calculate CRC-8 out of the given address */
16969 -       mac_h = (p_addr[0] << 8) | (p_addr[1]);
16970 -       mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
16971 -                       (p_addr[4] << 8) | (p_addr[5] << 0);
16972 -
16973 -       for (i = 0; i < 32; i++)
16974 -               mac_array[i] = (mac_l >> i) & 0x1;
16975 -       for (i = 32; i < 48; i++)
16976 -               mac_array[i] = (mac_h >> (i - 32)) & 0x1;
16977 -
16978 -       crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
16979 -                mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
16980 -                mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
16981 -                mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
16982 -                mac_array[8]  ^ mac_array[7]  ^ mac_array[6]  ^ mac_array[0];
16983 -
16984 -       crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
16985 -                mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
16986 -                mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
16987 -                mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
16988 -                mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
16989 -                mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
16990 -                mac_array[9]  ^ mac_array[6]  ^ mac_array[1]  ^ mac_array[0];
16991 -
16992 -       crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
16993 -                mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
16994 -                mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
16995 -                mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
16996 -                mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8]  ^
16997 -                mac_array[6]  ^ mac_array[2]  ^ mac_array[1]  ^ mac_array[0];
16998 -
16999 -       crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
17000 -                mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
17001 -                mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
17002 -                mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
17003 -                mac_array[13] ^ mac_array[11] ^ mac_array[9]  ^ mac_array[7]  ^
17004 -                mac_array[3]  ^ mac_array[2]  ^ mac_array[1];
17005 -
17006 -       crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
17007 -                mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
17008 -                mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
17009 -                mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
17010 -                mac_array[12] ^ mac_array[10] ^ mac_array[8]  ^ mac_array[4]  ^
17011 -                mac_array[3]  ^ mac_array[2];
17012 -
17013 -       crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
17014 -                mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
17015 -                mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
17016 -                mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
17017 -                mac_array[13] ^ mac_array[11] ^ mac_array[9]  ^ mac_array[5]  ^
17018 -                mac_array[4]  ^ mac_array[3];
17019 -
17020 -       crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
17021 -                mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
17022 -                mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
17023 -                mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
17024 -                mac_array[12] ^ mac_array[10] ^ mac_array[6]  ^ mac_array[5]  ^
17025 -                mac_array[4];
17026 -
17027 -       crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
17028 -                mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
17029 -                mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
17030 -                mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
17031 -                mac_array[11] ^ mac_array[7]  ^ mac_array[6]  ^ mac_array[5];
17032 +/* platform glue ************************************************************/
17033 +static void
17034 +mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
17035 +                             struct mbus_dram_target_info *dram)
17036 +{
17037 +       void __iomem *base = msp->base;
17038 +       u32 win_enable;
17039 +       u32 win_protect;
17040 +       int i;
17041
17042 -       for (i = 0; i < 8; i++)
17043 -               crc_result = crc_result | (crc[i] << i);
17044 +       for (i = 0; i < 6; i++) {
17045 +               writel(0, base + WINDOW_BASE(i));
17046 +               writel(0, base + WINDOW_SIZE(i));
17047 +               if (i < 4)
17048 +                       writel(0, base + WINDOW_REMAP_HIGH(i));
17049 +       }
17050
17051 -       table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num);
17052 -       eth_port_set_filter_table_entry(mp, table, crc_result);
17053 -}
17054 +       win_enable = 0x3f;
17055 +       win_protect = 0;
17056
17057 -/*
17058 - * Set the entire multicast list based on dev->mc_list.
17059 - */
17060 -static void eth_port_set_multicast_list(struct net_device *dev)
17061 -{
17062 +       for (i = 0; i < dram->num_cs; i++) {
17063 +               struct mbus_dram_window *cs = dram->cs + i;
17064
17065 -       struct dev_mc_list      *mc_list;
17066 -       int                     i;
17067 -       int                     table_index;
17068 -       struct mv643xx_private  *mp = netdev_priv(dev);
17069 -       unsigned int            eth_port_num = mp->port_num;
17070 -
17071 -       /* If the device is in promiscuous mode or in all multicast mode,
17072 -        * we will fully populate both multicast tables with accept.
17073 -        * This is guaranteed to yield a match on all multicast addresses...
17074 -        */
17075 -       if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
17076 -               for (table_index = 0; table_index <= 0xFC; table_index += 4) {
17077 -                       /* Set all entries in DA filter special multicast
17078 -                        * table (Ex_dFSMT)
17079 -                        * Set for ETH_Q0 for now
17080 -                        * Bits
17081 -                        * 0      Accept=1, Drop=0
17082 -                        * 3-1  Queue    ETH_Q0=0
17083 -                        * 7-4  Reserved = 0;
17084 -                        */
17085 -                       wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
17086 +               writel((cs->base & 0xffff0000) |
17087 +                       (cs->mbus_attr << 8) |
17088 +                       dram->mbus_dram_target_id, base + WINDOW_BASE(i));
17089 +               writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
17090
17091 -                       /* Set all entries in DA filter other multicast
17092 -                        * table (Ex_dFOMT)
17093 -                        * Set for ETH_Q0 for now
17094 -                        * Bits
17095 -                        * 0      Accept=1, Drop=0
17096 -                        * 3-1  Queue    ETH_Q0=0
17097 -                        * 7-4  Reserved = 0;
17098 -                        */
17099 -                       wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
17100 -               }
17101 -               return;
17102 +               win_enable &= ~(1 << i);
17103 +               win_protect |= 3 << (2 * i);
17104         }
17105
17106 -       /* We will clear out multicast tables every time we get the list.
17107 -        * Then add the entire new list...
17108 -        */
17109 -       for (table_index = 0; table_index <= 0xFC; table_index += 4) {
17110 -               /* Clear DA filter special multicast table (Ex_dFSMT) */
17111 -               wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
17112 -                               (eth_port_num) + table_index, 0);
17113 -
17114 -               /* Clear DA filter other multicast table (Ex_dFOMT) */
17115 -               wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE
17116 -                               (eth_port_num) + table_index, 0);
17117 -       }
17118 -
17119 -       /* Get pointer to net_device multicast list and add each one... */
17120 -       for (i = 0, mc_list = dev->mc_list;
17121 -                       (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
17122 -                       i++, mc_list = mc_list->next)
17123 -               if (mc_list->dmi_addrlen == 6)
17124 -                       eth_port_mc_addr(mp, mc_list->dmi_addr);
17125 +       writel(win_enable, base + WINDOW_BAR_ENABLE);
17126 +       msp->win_protect = win_protect;
17127  }
17128
17129 -/*
17130 - * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
17131 - *
17132 - * DESCRIPTION:
17133 - *     Go through all the DA filter tables (Unicast, Special Multicast &
17134 - *     Other Multicast) and set each entry to 0.
17135 - *
17136 - * INPUT:
17137 - *     struct mv643xx_private *mp      Ethernet Port.
17138 - *
17139 - * OUTPUT:
17140 - *     Multicast and Unicast packets are rejected.
17141 - *
17142 - * RETURN:
17143 - *     None.
17144 - */
17145 -static void eth_port_init_mac_tables(struct mv643xx_private *mp)
17146 +static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
17147  {
17148 -       unsigned int port_num = mp->port_num;
17149 -       int table_index;
17150 +       /*
17151 +        * Check whether we have a 14-bit coal limit field in bits
17152 +        * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
17153 +        * SDMA config register.
17154 +        */
17155 +       writel(0x02000000, msp->base + SDMA_CONFIG(0));
17156 +       if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
17157 +               msp->extended_rx_coal_limit = 1;
17158 +       else
17159 +               msp->extended_rx_coal_limit = 0;
17160
17161 -       /* Clear DA filter unicast table (Ex_dFUT) */
17162 -       for (table_index = 0; table_index <= 0xC; table_index += 4)
17163 -               wrl(mp, DA_FILTER_UNICAST_TABLE_BASE(port_num) +
17164 -                                       table_index, 0);
17165 -
17166 -       for (table_index = 0; table_index <= 0xFC; table_index += 4) {
17167 -               /* Clear DA filter special multicast table (Ex_dFSMT) */
17168 -               wrl(mp, DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num) +
17169 -                                       table_index, 0);
17170 -               /* Clear DA filter other multicast table (Ex_dFOMT) */
17171 -               wrl(mp, DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num) +
17172 -                                       table_index, 0);
17173 -       }
17174 +       /*
17175 +        * Check whether the TX rate control registers are in the
17176 +        * old or the new place.
17177 +        */
17178 +       writel(1, msp->base + TX_BW_MTU_MOVED(0));
17179 +       if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
17180 +               msp->tx_bw_control_moved = 1;
17181 +       else
17182 +               msp->tx_bw_control_moved = 0;
17183  }
17184
17185 -/*
17186 - * eth_clear_mib_counters - Clear all MIB counters
17187 - *
17188 - * DESCRIPTION:
17189 - *     This function clears all MIB counters of a specific ethernet port.
17190 - *     A read from the MIB counter will reset the counter.
17191 - *
17192 - * INPUT:
17193 - *     struct mv643xx_private *mp      Ethernet Port.
17194 - *
17195 - * OUTPUT:
17196 - *     After reading all MIB counters, the counters resets.
17197 - *
17198 - * RETURN:
17199 - *     MIB counter value.
17200 - *
17201 - */
17202 -static void eth_clear_mib_counters(struct mv643xx_private *mp)
17203 +static int mv643xx_eth_shared_probe(struct platform_device *pdev)
17204  {
17205 -       unsigned int port_num = mp->port_num;
17206 -       int i;
17207 -
17208 -       /* Perform dummy reads from MIB counters */
17209 -       for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
17210 -                                                                       i += 4)
17211 -               rdl(mp, MIB_COUNTERS_BASE(port_num) + i);
17212 -}
17213 +       static int mv643xx_eth_version_printed = 0;
17214 +       struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
17215 +       struct mv643xx_eth_shared_private *msp;
17216 +       struct resource *res;
17217 +       int ret;
17218
17219 -static inline u32 read_mib(struct mv643xx_private *mp, int offset)
17220 -{
17221 -       return rdl(mp, MIB_COUNTERS_BASE(mp->port_num) + offset);
17222 -}
17223 +       if (!mv643xx_eth_version_printed++)
17224 +               printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
17225
17226 -static void eth_update_mib_counters(struct mv643xx_private *mp)
17227 -{
17228 -       struct mv643xx_mib_counters *p = &mp->mib_counters;
17229 -       int offset;
17230 +       ret = -EINVAL;
17231 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17232 +       if (res == NULL)
17233 +               goto out;
17234
17235 -       p->good_octets_received +=
17236 -               read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
17237 -       p->good_octets_received +=
17238 -               (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
17239 +       ret = -ENOMEM;
17240 +       msp = kmalloc(sizeof(*msp), GFP_KERNEL);
17241 +       if (msp == NULL)
17242 +               goto out;
17243 +       memset(msp, 0, sizeof(*msp));
17244
17245 -       for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
17246 -                       offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
17247 -                       offset += 4)
17248 -               *(u32 *)((char *)p + offset) += read_mib(mp, offset);
17249 +       msp->base = ioremap(res->start, res->end - res->start + 1);
17250 +       if (msp->base == NULL)
17251 +               goto out_free;
17252
17253 -       p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
17254 -       p->good_octets_sent +=
17255 -               (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
17256 +       spin_lock_init(&msp->phy_lock);
17257
17258 -       for (offset = ETH_MIB_GOOD_FRAMES_SENT;
17259 -                       offset <= ETH_MIB_LATE_COLLISION;
17260 -                       offset += 4)
17261 -               *(u32 *)((char *)p + offset) += read_mib(mp, offset);
17262 -}
17263 +       /*
17264 +        * (Re-)program MBUS remapping windows if we are asked to.
17265 +        */
17266 +       if (pd != NULL && pd->dram != NULL)
17267 +               mv643xx_eth_conf_mbus_windows(msp, pd->dram);
17268
17269 -/*
17270 - * ethernet_phy_detect - Detect whether a phy is present
17271 - *
17272 - * DESCRIPTION:
17273 - *     This function tests whether there is a PHY present on
17274 - *     the specified port.
17275 - *
17276 - * INPUT:
17277 - *     struct mv643xx_private *mp      Ethernet Port.
17278 - *
17279 - * OUTPUT:
17280 - *     None
17281 - *
17282 - * RETURN:
17283 - *     0 on success
17284 - *     -ENODEV on failure
17285 - *
17286 - */
17287 -static int ethernet_phy_detect(struct mv643xx_private *mp)
17288 -{
17289 -       unsigned int phy_reg_data0;
17290 -       int auto_neg;
17291 +       /*
17292 +        * Detect hardware parameters.
17293 +        */
17294 +       msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
17295 +       infer_hw_params(msp);
17296
17297 -       eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
17298 -       auto_neg = phy_reg_data0 & 0x1000;
17299 -       phy_reg_data0 ^= 0x1000;        /* invert auto_neg */
17300 -       eth_port_write_smi_reg(mp, 0, phy_reg_data0);
17301 -
17302 -       eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
17303 -       if ((phy_reg_data0 & 0x1000) == auto_neg)
17304 -               return -ENODEV;                         /* change didn't take */
17305 +       platform_set_drvdata(pdev, msp);
17306
17307 -       phy_reg_data0 ^= 0x1000;
17308 -       eth_port_write_smi_reg(mp, 0, phy_reg_data0);
17309         return 0;
17310 +
17311 +out_free:
17312 +       kfree(msp);
17313 +out:
17314 +       return ret;
17315  }
17316
17317 -/*
17318 - * ethernet_phy_get - Get the ethernet port PHY address.
17319 - *
17320 - * DESCRIPTION:
17321 - *     This routine returns the given ethernet port PHY address.
17322 - *
17323 - * INPUT:
17324 - *     struct mv643xx_private *mp      Ethernet Port.
17325 - *
17326 - * OUTPUT:
17327 - *     None.
17328 - *
17329 - * RETURN:
17330 - *     PHY address.
17331 - *
17332 - */
17333 -static int ethernet_phy_get(struct mv643xx_private *mp)
17334 +static int mv643xx_eth_shared_remove(struct platform_device *pdev)
17335  {
17336 -       unsigned int reg_data;
17337 +       struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
17338
17339 -       reg_data = rdl(mp, PHY_ADDR_REG);
17340 +       iounmap(msp->base);
17341 +       kfree(msp);
17342
17343 -       return ((reg_data >> (5 * mp->port_num)) & 0x1f);
17344 +       return 0;
17345  }
17346
17347 -/*
17348 - * ethernet_phy_set - Set the ethernet port PHY address.
17349 - *
17350 - * DESCRIPTION:
17351 - *     This routine sets the given ethernet port PHY address.
17352 - *
17353 - * INPUT:
17354 - *     struct mv643xx_private *mp      Ethernet Port.
17355 - *     int             phy_addr        PHY address.
17356 - *
17357 - * OUTPUT:
17358 - *     None.
17359 - *
17360 - * RETURN:
17361 - *     None.
17362 - *
17363 - */
17364 -static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
17365 +static struct platform_driver mv643xx_eth_shared_driver = {
17366 +       .probe          = mv643xx_eth_shared_probe,
17367 +       .remove         = mv643xx_eth_shared_remove,
17368 +       .driver = {
17369 +               .name   = MV643XX_ETH_SHARED_NAME,
17370 +               .owner  = THIS_MODULE,
17371 +       },
17372 +};
17373 +
17374 +static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
17375  {
17376 -       u32 reg_data;
17377         int addr_shift = 5 * mp->port_num;
17378 +       u32 data;
17379
17380 -       reg_data = rdl(mp, PHY_ADDR_REG);
17381 -       reg_data &= ~(0x1f << addr_shift);
17382 -       reg_data |= (phy_addr & 0x1f) << addr_shift;
17383 -       wrl(mp, PHY_ADDR_REG, reg_data);
17384 +       data = rdl(mp, PHY_ADDR);
17385 +       data &= ~(0x1f << addr_shift);
17386 +       data |= (phy_addr & 0x1f) << addr_shift;
17387 +       wrl(mp, PHY_ADDR, data);
17388  }
17389
17390 -/*
17391 - * ethernet_phy_reset - Reset Ethernet port PHY.
17392 - *
17393 - * DESCRIPTION:
17394 - *     This routine utilizes the SMI interface to reset the ethernet port PHY.
17395 - *
17396 - * INPUT:
17397 - *     struct mv643xx_private *mp      Ethernet Port.
17398 - *
17399 - * OUTPUT:
17400 - *     The PHY is reset.
17401 - *
17402 - * RETURN:
17403 - *     None.
17404 - *
17405 - */
17406 -static void ethernet_phy_reset(struct mv643xx_private *mp)
17407 +static int phy_addr_get(struct mv643xx_eth_private *mp)
17408  {
17409 -       unsigned int phy_reg_data;
17410 +       unsigned int data;
17411
17412 -       /* Reset the PHY */
17413 -       eth_port_read_smi_reg(mp, 0, &phy_reg_data);
17414 -       phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
17415 -       eth_port_write_smi_reg(mp, 0, phy_reg_data);
17416 +       data = rdl(mp, PHY_ADDR);
17417
17418 -       /* wait for PHY to come out of reset */
17419 -       do {
17420 -               udelay(1);
17421 -               eth_port_read_smi_reg(mp, 0, &phy_reg_data);
17422 -       } while (phy_reg_data & 0x8000);
17423 +       return (data >> (5 * mp->port_num)) & 0x1f;
17424  }
17425
17426 -static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
17427 -                                       unsigned int queues)
17428 +static void set_params(struct mv643xx_eth_private *mp,
17429 +                      struct mv643xx_eth_platform_data *pd)
17430  {
17431 -       wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(mp->port_num), queues);
17432 -}
17433 +       struct net_device *dev = mp->dev;
17434
17435 -static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
17436 -                                       unsigned int queues)
17437 -{
17438 -       wrl(mp, RECEIVE_QUEUE_COMMAND_REG(mp->port_num), queues);
17439 -}
17440 +       if (is_valid_ether_addr(pd->mac_addr))
17441 +               memcpy(dev->dev_addr, pd->mac_addr, 6);
17442 +       else
17443 +               uc_addr_get(mp, dev->dev_addr);
17444
17445 -static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
17446 -{
17447 -       unsigned int port_num = mp->port_num;
17448 -       u32 queues;
17449 +       if (pd->phy_addr == -1) {
17450 +               mp->shared_smi = NULL;
17451 +               mp->phy_addr = -1;
17452 +       } else {
17453 +               mp->shared_smi = mp->shared;
17454 +               if (pd->shared_smi != NULL)
17455 +                       mp->shared_smi = platform_get_drvdata(pd->shared_smi);
17456 +
17457 +               if (pd->force_phy_addr || pd->phy_addr) {
17458 +                       mp->phy_addr = pd->phy_addr & 0x3f;
17459 +                       phy_addr_set(mp, mp->phy_addr);
17460 +               } else {
17461 +                       mp->phy_addr = phy_addr_get(mp);
17462 +               }
17463 +       }
17464
17465 -       /* Stop Tx port activity. Check port Tx activity. */
17466 -       queues = rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
17467 -       if (queues) {
17468 -               /* Issue stop command for active queues only */
17469 -               wrl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
17470 +       mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
17471 +       if (pd->rx_queue_size)
17472 +               mp->default_rx_ring_size = pd->rx_queue_size;
17473 +       mp->rx_desc_sram_addr = pd->rx_sram_addr;
17474 +       mp->rx_desc_sram_size = pd->rx_sram_size;
17475
17476 -               /* Wait for all Tx activity to terminate. */
17477 -               /* Check port cause register that all Tx queues are stopped */
17478 -               while (rdl(mp, TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
17479 -                       udelay(PHY_WAIT_MICRO_SECONDS);
17480 +       if (pd->rx_queue_mask)
17481 +               mp->rxq_mask = pd->rx_queue_mask;
17482 +       else
17483 +               mp->rxq_mask = 0x01;
17484 +       mp->rxq_primary = fls(mp->rxq_mask) - 1;
17485
17486 -               /* Wait for Tx FIFO to empty */
17487 -               while (rdl(mp, PORT_STATUS_REG(port_num)) &
17488 -                                                       ETH_PORT_TX_FIFO_EMPTY)
17489 -                       udelay(PHY_WAIT_MICRO_SECONDS);
17490 -       }
17491 +       mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
17492 +       if (pd->tx_queue_size)
17493 +               mp->default_tx_ring_size = pd->tx_queue_size;
17494 +       mp->tx_desc_sram_addr = pd->tx_sram_addr;
17495 +       mp->tx_desc_sram_size = pd->tx_sram_size;
17496
17497 -       return queues;
17498 +       if (pd->tx_queue_mask)
17499 +               mp->txq_mask = pd->tx_queue_mask;
17500 +       else
17501 +               mp->txq_mask = 0x01;
17502 +       mp->txq_primary = fls(mp->txq_mask) - 1;
17503  }
17504
17505 -static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
17506 +static int phy_detect(struct mv643xx_eth_private *mp)
17507  {
17508 -       unsigned int port_num = mp->port_num;
17509 -       u32 queues;
17510 +       unsigned int data;
17511 +       unsigned int data2;
17512
17513 -       /* Stop Rx port activity. Check port Rx activity. */
17514 -       queues = rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
17515 -       if (queues) {
17516 -               /* Issue stop command for active queues only */
17517 -               wrl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
17518 +       smi_reg_read(mp, mp->phy_addr, 0, &data);
17519 +       smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
17520
17521 -               /* Wait for all Rx activity to terminate. */
17522 -               /* Check port cause register that all Rx queues are stopped */
17523 -               while (rdl(mp, RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
17524 -                       udelay(PHY_WAIT_MICRO_SECONDS);
17525 -       }
17526 +       smi_reg_read(mp, mp->phy_addr, 0, &data2);
17527 +       if (((data ^ data2) & 0x1000) == 0)
17528 +               return -ENODEV;
17529 +
17530 +       smi_reg_write(mp, mp->phy_addr, 0, data);
17531
17532 -       return queues;
17533 +       return 0;
17534  }
17535
17536 -/*
17537 - * eth_port_reset - Reset Ethernet port
17538 - *
17539 - * DESCRIPTION:
17540 - *     This routine resets the chip by aborting any SDMA engine activity and
17541 - *     clearing the MIB counters. The Receiver and the Transmit unit are in
17542 - *     idle state after this command is performed and the port is disabled.
17543 - *
17544 - * INPUT:
17545 - *     struct mv643xx_private *mp      Ethernet Port.
17546 - *
17547 - * OUTPUT:
17548 - *     Channel activity is halted.
17549 - *
17550 - * RETURN:
17551 - *     None.
17552 - *
17553 - */
17554 -static void eth_port_reset(struct mv643xx_private *mp)
17555 +static int phy_init(struct mv643xx_eth_private *mp,
17556 +                   struct mv643xx_eth_platform_data *pd)
17557  {
17558 -       unsigned int port_num = mp->port_num;
17559 -       unsigned int reg_data;
17560 -
17561 -       mv643xx_eth_port_disable_tx(mp);
17562 -       mv643xx_eth_port_disable_rx(mp);
17563 -
17564 -       /* Clear all MIB counters */
17565 -       eth_clear_mib_counters(mp);
17566 +       struct ethtool_cmd cmd;
17567 +       int err;
17568
17569 -       /* Reset the Enable bit in the Configuration Register */
17570 -       reg_data = rdl(mp, PORT_SERIAL_CONTROL_REG(port_num));
17571 -       reg_data &= ~(SERIAL_PORT_ENABLE                |
17572 -                       DO_NOT_FORCE_LINK_FAIL  |
17573 -                       FORCE_LINK_PASS);
17574 -       wrl(mp, PORT_SERIAL_CONTROL_REG(port_num), reg_data);
17575 -}
17576 +       err = phy_detect(mp);
17577 +       if (err) {
17578 +               dev_printk(KERN_INFO, &mp->dev->dev,
17579 +                          "no PHY detected at addr %d\n", mp->phy_addr);
17580 +               return err;
17581 +       }
17582 +       phy_reset(mp);
17583
17584 +       mp->mii.phy_id = mp->phy_addr;
17585 +       mp->mii.phy_id_mask = 0x3f;
17586 +       mp->mii.reg_num_mask = 0x1f;
17587 +       mp->mii.dev = mp->dev;
17588 +       mp->mii.mdio_read = mv643xx_eth_mdio_read;
17589 +       mp->mii.mdio_write = mv643xx_eth_mdio_write;
17590
17591 -/*
17592 - * eth_port_read_smi_reg - Read PHY registers
17593 - *
17594 - * DESCRIPTION:
17595 - *     This routine utilize the SMI interface to interact with the PHY in
17596 - *     order to perform PHY register read.
17597 - *
17598 - * INPUT:
17599 - *     struct mv643xx_private *mp      Ethernet Port.
17600 - *     unsigned int    phy_reg         PHY register address offset.
17601 - *     unsigned int    *value          Register value buffer.
17602 - *
17603 - * OUTPUT:
17604 - *     Write the value of a specified PHY register into given buffer.
17605 - *
17606 - * RETURN:
17607 - *     false if the PHY is busy or read data is not in valid state.
17608 - *     true otherwise.
17609 - *
17610 - */
17611 -static void eth_port_read_smi_reg(struct mv643xx_private *mp,
17612 -                               unsigned int phy_reg, unsigned int *value)
17613 -{
17614 -       void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
17615 -       int phy_addr = ethernet_phy_get(mp);
17616 -       unsigned long flags;
17617 -       int i;
17618 +       mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
17619
17620 -       /* the SMI register is a shared resource */
17621 -       spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
17622 +       memset(&cmd, 0, sizeof(cmd));
17623
17624 -       /* wait for the SMI register to become available */
17625 -       for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
17626 -               if (i == PHY_WAIT_ITERATIONS) {
17627 -                       printk("%s: PHY busy timeout\n", mp->dev->name);
17628 -                       goto out;
17629 -               }
17630 -               udelay(PHY_WAIT_MICRO_SECONDS);
17631 +       cmd.port = PORT_MII;
17632 +       cmd.transceiver = XCVR_INTERNAL;
17633 +       cmd.phy_address = mp->phy_addr;
17634 +       if (pd->speed == 0) {
17635 +               cmd.autoneg = AUTONEG_ENABLE;
17636 +               cmd.speed = SPEED_100;
17637 +               cmd.advertising = ADVERTISED_10baseT_Half  |
17638 +                                 ADVERTISED_10baseT_Full  |
17639 +                                 ADVERTISED_100baseT_Half |
17640 +                                 ADVERTISED_100baseT_Full;
17641 +               if (mp->mii.supports_gmii)
17642 +                       cmd.advertising |= ADVERTISED_1000baseT_Full;
17643 +       } else {
17644 +               cmd.autoneg = AUTONEG_DISABLE;
17645 +               cmd.speed = pd->speed;
17646 +               cmd.duplex = pd->duplex;
17647         }
17648
17649 -       writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
17650 -               smi_reg);
17651 -
17652 -       /* now wait for the data to be valid */
17653 -       for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
17654 -               if (i == PHY_WAIT_ITERATIONS) {
17655 -                       printk("%s: PHY read timeout\n", mp->dev->name);
17656 -                       goto out;
17657 -               }
17658 -               udelay(PHY_WAIT_MICRO_SECONDS);
17659 -       }
17660 +       update_pscr(mp, cmd.speed, cmd.duplex);
17661 +       mv643xx_eth_set_settings(mp->dev, &cmd);
17662
17663 -       *value = readl(smi_reg) & 0xffff;
17664 -out:
17665 -       spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
17666 +       return 0;
17667  }
17668
17669 -/*
17670 - * eth_port_write_smi_reg - Write to PHY registers
17671 - *
17672 - * DESCRIPTION:
17673 - *     This routine utilize the SMI interface to interact with the PHY in
17674 - *     order to perform writes to PHY registers.
17675 - *
17676 - * INPUT:
17677 - *     struct mv643xx_private *mp      Ethernet Port.
17678 - *     unsigned int    phy_reg         PHY register address offset.
17679 - *     unsigned int    value           Register value.
17680 - *
17681 - * OUTPUT:
17682 - *     Write the given value to the specified PHY register.
17683 - *
17684 - * RETURN:
17685 - *     false if the PHY is busy.
17686 - *     true otherwise.
17687 - *
17688 - */
17689 -static void eth_port_write_smi_reg(struct mv643xx_private *mp,
17690 -                                  unsigned int phy_reg, unsigned int value)
17691 +static int mv643xx_eth_probe(struct platform_device *pdev)
17692  {
17693 -       void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
17694 -       int phy_addr = ethernet_phy_get(mp);
17695 -       unsigned long flags;
17696 -       int i;
17697 +       struct mv643xx_eth_platform_data *pd;
17698 +       struct mv643xx_eth_private *mp;
17699 +       struct net_device *dev;
17700 +       struct resource *res;
17701 +       DECLARE_MAC_BUF(mac);
17702 +       int err;
17703
17704 -       /* the SMI register is a shared resource */
17705 -       spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
17706 +       pd = pdev->dev.platform_data;
17707 +       if (pd == NULL) {
17708 +               dev_printk(KERN_ERR, &pdev->dev,
17709 +                          "no mv643xx_eth_platform_data\n");
17710 +               return -ENODEV;
17711 +       }
17712
17713 -       /* wait for the SMI register to become available */
17714 -       for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
17715 -               if (i == PHY_WAIT_ITERATIONS) {
17716 -                       printk("%s: PHY busy timeout\n", mp->dev->name);
17717 -                       goto out;
17718 -               }
17719 -               udelay(PHY_WAIT_MICRO_SECONDS);
17720 +       if (pd->shared == NULL) {
17721 +               dev_printk(KERN_ERR, &pdev->dev,
17722 +                          "no mv643xx_eth_platform_data->shared\n");
17723 +               return -ENODEV;
17724         }
17725
17726 -       writel((phy_addr << 16) | (phy_reg << 21) |
17727 -               ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
17728 -out:
17729 -       spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
17730 -}
17731 +       dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
17732 +       if (!dev)
17733 +               return -ENOMEM;
17734
17735 -/*
17736 - * Wrappers for MII support library.
17737 - */
17738 -static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
17739 -{
17740 -       struct mv643xx_private *mp = netdev_priv(dev);
17741 -       int val;
17742 +       mp = netdev_priv(dev);
17743 +       platform_set_drvdata(pdev, mp);
17744
17745 -       eth_port_read_smi_reg(mp, location, &val);
17746 -       return val;
17747 -}
17748 +       mp->shared = platform_get_drvdata(pd->shared);
17749 +       mp->port_num = pd->port_number;
17750
17751 -static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
17752 -{
17753 -       struct mv643xx_private *mp = netdev_priv(dev);
17754 -       eth_port_write_smi_reg(mp, location, val);
17755 -}
17756 +       mp->dev = dev;
17757 +#ifdef MV643XX_ETH_NAPI
17758 +       netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
17759 +#endif
17760
17761 -/*
17762 - * eth_port_receive - Get received information from Rx ring.
17763 - *
17764 - * DESCRIPTION:
17765 - *     This routine returns the received data to the caller. There is no
17766 - *     data copying during routine operation. All information is returned
17767 - *     using pointer to packet information struct passed from the caller.
17768 - *     If the routine exhausts Rx ring resources then the resource error flag
17769 - *     is set.
17770 - *
17771 - * INPUT:
17772 - *     struct mv643xx_private  *mp             Ethernet Port Control srtuct.
17773 - *     struct pkt_info         *p_pkt_info     User packet buffer.
17774 - *
17775 - * OUTPUT:
17776 - *     Rx ring current and used indexes are updated.
17777 - *
17778 - * RETURN:
17779 - *     ETH_ERROR in case the routine can not access Rx desc ring.
17780 - *     ETH_QUEUE_FULL if Rx ring resources are exhausted.
17781 - *     ETH_END_OF_JOB if there is no received data.
17782 - *     ETH_OK otherwise.
17783 - */
17784 -static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
17785 -                                               struct pkt_info *p_pkt_info)
17786 -{
17787 -       int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
17788 -       volatile struct eth_rx_desc *p_rx_desc;
17789 -       unsigned int command_status;
17790 -       unsigned long flags;
17791 +       set_params(mp, pd);
17792
17793 -       /* Do not process Rx ring in case of Rx ring resource error */
17794 -       if (mp->rx_resource_err)
17795 -               return ETH_QUEUE_FULL;
17796 +       spin_lock_init(&mp->lock);
17797
17798 -       spin_lock_irqsave(&mp->lock, flags);
17799 +       mib_counters_clear(mp);
17800 +       INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
17801
17802 -       /* Get the Rx Desc ring 'curr and 'used' indexes */
17803 -       rx_curr_desc = mp->rx_curr_desc_q;
17804 -       rx_used_desc = mp->rx_used_desc_q;
17805 -
17806 -       p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
17807 -
17808 -       /* The following parameters are used to save readings from memory */
17809 -       command_status = p_rx_desc->cmd_sts;
17810 -       rmb();
17811 +       if (mp->phy_addr != -1) {
17812 +               err = phy_init(mp, pd);
17813 +               if (err)
17814 +                       goto out;
17815
17816 -       /* Nothing to receive... */
17817 -       if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
17818 -               spin_unlock_irqrestore(&mp->lock, flags);
17819 -               return ETH_END_OF_JOB;
17820 +               SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
17821 +       } else {
17822 +               SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
17823         }
17824
17825 -       p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
17826 -       p_pkt_info->cmd_sts = command_status;
17827 -       p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
17828 -       p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
17829 -       p_pkt_info->l4i_chk = p_rx_desc->buf_size;
17830 -
17831 -       /*
17832 -        * Clean the return info field to indicate that the
17833 -        * packet has been moved to the upper layers
17834 -        */
17835 -       mp->rx_skb[rx_curr_desc] = NULL;
17836
17837 -       /* Update current index in data structure */
17838 -       rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
17839 -       mp->rx_curr_desc_q = rx_next_curr_desc;
17840 +       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
17841 +       BUG_ON(!res);
17842 +       dev->irq = res->start;
17843
17844 -       /* Rx descriptors exhausted. Set the Rx ring resource error flag */
17845 -       if (rx_next_curr_desc == rx_used_desc)
17846 -               mp->rx_resource_err = 1;
17847 +       dev->hard_start_xmit = mv643xx_eth_xmit;
17848 +       dev->open = mv643xx_eth_open;
17849 +       dev->stop = mv643xx_eth_stop;
17850 +       dev->set_multicast_list = mv643xx_eth_set_rx_mode;
17851 +       dev->set_mac_address = mv643xx_eth_set_mac_address;
17852 +       dev->do_ioctl = mv643xx_eth_ioctl;
17853 +       dev->change_mtu = mv643xx_eth_change_mtu;
17854 +       dev->tx_timeout = mv643xx_eth_tx_timeout;
17855 +#ifdef CONFIG_NET_POLL_CONTROLLER
17856 +       dev->poll_controller = mv643xx_eth_netpoll;
17857 +#endif
17858 +       dev->watchdog_timeo = 2 * HZ;
17859 +       dev->base_addr = 0;
17860
17861 -       spin_unlock_irqrestore(&mp->lock, flags);
17862 +#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
17863 +       /*
17864 +        * Zero copy can only work if we use Discovery II memory. Else, we will
17865 +        * have to map the buffers to ISA memory which is only 16 MB
17866 +        */
17867 +       dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
17868 +#endif
17869
17870 -       return ETH_OK;
17871 -}
17872 +       SET_NETDEV_DEV(dev, &pdev->dev);
17873
17874 -/*
17875 - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
17876 - *
17877 - * DESCRIPTION:
17878 - *     This routine returns a Rx buffer back to the Rx ring. It retrieves the
17879 - *     next 'used' descriptor and attached the returned buffer to it.
17880 - *     In case the Rx ring was in "resource error" condition, where there are
17881 - *     no available Rx resources, the function resets the resource error flag.
17882 - *
17883 - * INPUT:
17884 - *     struct mv643xx_private  *mp             Ethernet Port Control srtuct.
17885 - *     struct pkt_info         *p_pkt_info     Information on returned buffer.
17886 - *
17887 - * OUTPUT:
17888 - *     New available Rx resource in Rx descriptor ring.
17889 - *
17890 - * RETURN:
17891 - *     ETH_ERROR in case the routine can not access Rx desc ring.
17892 - *     ETH_OK otherwise.
17893 - */
17894 -static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
17895 -                                               struct pkt_info *p_pkt_info)
17896 -{
17897 -       int used_rx_desc;       /* Where to return Rx resource */
17898 -       volatile struct eth_rx_desc *p_used_rx_desc;
17899 -       unsigned long flags;
17900 +       if (mp->shared->win_protect)
17901 +               wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
17902
17903 -       spin_lock_irqsave(&mp->lock, flags);
17904 +       err = register_netdev(dev);
17905 +       if (err)
17906 +               goto out;
17907
17908 -       /* Get 'used' Rx descriptor */
17909 -       used_rx_desc = mp->rx_used_desc_q;
17910 -       p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
17911 +       dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
17912 +                  mp->port_num, print_mac(mac, dev->dev_addr));
17913
17914 -       p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
17915 -       p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
17916 -       mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
17917 +       if (dev->features & NETIF_F_SG)
17918 +               dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
17919
17920 -       /* Flush the write pipe */
17921 +       if (dev->features & NETIF_F_IP_CSUM)
17922 +               dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
17923
17924 -       /* Return the descriptor to DMA ownership */
17925 -       wmb();
17926 -       p_used_rx_desc->cmd_sts =
17927 -                       ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
17928 -       wmb();
17929 +#ifdef MV643XX_ETH_NAPI
17930 +       dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
17931 +#endif
17932
17933 -       /* Move the used descriptor pointer to the next descriptor */
17934 -       mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
17935 +       if (mp->tx_desc_sram_size > 0)
17936 +               dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
17937
17938 -       /* Any Rx return cancels the Rx resource error status */
17939 -       mp->rx_resource_err = 0;
17940 +       return 0;
17941
17942 -       spin_unlock_irqrestore(&mp->lock, flags);
17943 +out:
17944 +       free_netdev(dev);
17945
17946 -       return ETH_OK;
17947 +       return err;
17948  }
17949
17950 -/************* Begin ethtool support *************************/
17951 -
17952 -struct mv643xx_stats {
17953 -       char stat_string[ETH_GSTRING_LEN];
17954 -       int sizeof_stat;
17955 -       int stat_offset;
17956 -};
17957 -
17958 -#define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
17959 -                                       offsetof(struct mv643xx_private, m)
17960 -
17961 -static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
17962 -       { "rx_packets", MV643XX_STAT(stats.rx_packets) },
17963 -       { "tx_packets", MV643XX_STAT(stats.tx_packets) },
17964 -       { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
17965 -       { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
17966 -       { "rx_errors", MV643XX_STAT(stats.rx_errors) },
17967 -       { "tx_errors", MV643XX_STAT(stats.tx_errors) },
17968 -       { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
17969 -       { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
17970 -       { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
17971 -       { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
17972 -       { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
17973 -       { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
17974 -       { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
17975 -       { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
17976 -       { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
17977 -       { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
17978 -       { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
17979 -       { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
17980 -       { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
17981 -       { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
17982 -       { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
17983 -       { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
17984 -       { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
17985 -       { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
17986 -       { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
17987 -       { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
17988 -       { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
17989 -       { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
17990 -       { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
17991 -       { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
17992 -       { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
17993 -       { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
17994 -       { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
17995 -       { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
17996 -       { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
17997 -       { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
17998 -       { "collision", MV643XX_STAT(mib_counters.collision) },
17999 -       { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
18000 -};
18001 +static int mv643xx_eth_remove(struct platform_device *pdev)
18002 +{
18003 +       struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
18004
18005 -#define MV643XX_STATS_LEN      ARRAY_SIZE(mv643xx_gstrings_stats)
18006 +       unregister_netdev(mp->dev);
18007 +       flush_scheduled_work();
18008 +       free_netdev(mp->dev);
18009
18010 -static void mv643xx_get_drvinfo(struct net_device *netdev,
18011 -                               struct ethtool_drvinfo *drvinfo)
18012 -{
18013 -       strncpy(drvinfo->driver,  mv643xx_driver_name, 32);
18014 -       strncpy(drvinfo->version, mv643xx_driver_version, 32);
18015 -       strncpy(drvinfo->fw_version, "N/A", 32);
18016 -       strncpy(drvinfo->bus_info, "mv643xx", 32);
18017 -       drvinfo->n_stats = MV643XX_STATS_LEN;
18018 -}
18019 +       platform_set_drvdata(pdev, NULL);
18020
18021 -static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
18022 -{
18023 -       switch (sset) {
18024 -       case ETH_SS_STATS:
18025 -               return MV643XX_STATS_LEN;
18026 -       default:
18027 -               return -EOPNOTSUPP;
18028 -       }
18029 +       return 0;
18030  }
18031
18032 -static void mv643xx_get_ethtool_stats(struct net_device *netdev,
18033 -                               struct ethtool_stats *stats, uint64_t *data)
18034 +static void mv643xx_eth_shutdown(struct platform_device *pdev)
18035  {
18036 -       struct mv643xx_private *mp = netdev->priv;
18037 -       int i;
18038 +       struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
18039
18040 -       eth_update_mib_counters(mp);
18041 +       /* Mask all interrupts on ethernet port */
18042 +       wrl(mp, INT_MASK(mp->port_num), 0);
18043 +       rdl(mp, INT_MASK(mp->port_num));
18044
18045 -       for (i = 0; i < MV643XX_STATS_LEN; i++) {
18046 -               char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
18047 -               data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
18048 -                       sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
18049 -       }
18050 +       if (netif_running(mp->dev))
18051 +               port_reset(mp);
18052  }
18053
18054 -static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
18055 -                               uint8_t *data)
18056 -{
18057 -       int i;
18058 -
18059 -       switch(stringset) {
18060 -       case ETH_SS_STATS:
18061 -               for (i=0; i < MV643XX_STATS_LEN; i++) {
18062 -                       memcpy(data + i * ETH_GSTRING_LEN,
18063 -                                       mv643xx_gstrings_stats[i].stat_string,
18064 -                                       ETH_GSTRING_LEN);
18065 -               }
18066 -               break;
18067 -       }
18068 -}
18069 +static struct platform_driver mv643xx_eth_driver = {
18070 +       .probe          = mv643xx_eth_probe,
18071 +       .remove         = mv643xx_eth_remove,
18072 +       .shutdown       = mv643xx_eth_shutdown,
18073 +       .driver = {
18074 +               .name   = MV643XX_ETH_NAME,
18075 +               .owner  = THIS_MODULE,
18076 +       },
18077 +};
18078
18079 -static u32 mv643xx_eth_get_link(struct net_device *dev)
18080 +static int __init mv643xx_eth_init_module(void)
18081  {
18082 -       struct mv643xx_private *mp = netdev_priv(dev);
18083 -
18084 -       return mii_link_ok(&mp->mii);
18085 -}
18086 +       int rc;
18087
18088 -static int mv643xx_eth_nway_restart(struct net_device *dev)
18089 -{
18090 -       struct mv643xx_private *mp = netdev_priv(dev);
18091 +       rc = platform_driver_register(&mv643xx_eth_shared_driver);
18092 +       if (!rc) {
18093 +               rc = platform_driver_register(&mv643xx_eth_driver);
18094 +               if (rc)
18095 +                       platform_driver_unregister(&mv643xx_eth_shared_driver);
18096 +       }
18097
18098 -       return mii_nway_restart(&mp->mii);
18099 +       return rc;
18100  }
18101 +module_init(mv643xx_eth_init_module);
18102
18103 -static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
18104 +static void __exit mv643xx_eth_cleanup_module(void)
18105  {
18106 -       struct mv643xx_private *mp = netdev_priv(dev);
18107 -
18108 -       return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
18109 +       platform_driver_unregister(&mv643xx_eth_driver);
18110 +       platform_driver_unregister(&mv643xx_eth_shared_driver);
18111  }
18112 +module_exit(mv643xx_eth_cleanup_module);
18113
18114 -static const struct ethtool_ops mv643xx_ethtool_ops = {
18115 -       .get_settings           = mv643xx_get_settings,
18116 -       .set_settings           = mv643xx_set_settings,
18117 -       .get_drvinfo            = mv643xx_get_drvinfo,
18118 -       .get_link               = mv643xx_eth_get_link,
18119 -       .set_sg                 = ethtool_op_set_sg,
18120 -       .get_sset_count         = mv643xx_get_sset_count,
18121 -       .get_ethtool_stats      = mv643xx_get_ethtool_stats,
18122 -       .get_strings            = mv643xx_get_strings,
18123 -       .nway_reset             = mv643xx_eth_nway_restart,
18124 -};
18125 -
18126 -/************* End ethtool support *************************/
18127 +MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
18128 +             "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
18129 +MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
18130 +MODULE_LICENSE("GPL");
18131 +MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
18132 +MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
18133 --- /dev/null
18134 +++ b/include/asm-arm/arch-kirkwood/debug-macro.S
18135 @@ -0,0 +1,20 @@
18136 +/*
18137 + * include/asm-arm/arch-kirkwood/debug-macro.S
18138 + *
18139 + * This program is free software; you can redistribute it and/or modify
18140 + * it under the terms of the GNU General Public License version 2 as
18141 + * published by the Free Software Foundation.
18142 +*/
18143 +
18144 +#include <asm/arch/kirkwood.h>
18145 +
18146 +       .macro  addruart,rx
18147 +       mrc     p15, 0, \rx, c1, c0
18148 +       tst     \rx, #1                                 @ MMU enabled?
18149 +       ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
18150 +       ldrne   \rx, =KIRKWOOD_REGS_VIRT_BASE
18151 +       orr     \rx, \rx, #0x00012000
18152 +       .endm
18153 +
18154 +#define UART_SHIFT     2
18155 +#include <asm/hardware/debug-8250.S>
18156 --- /dev/null
18157 +++ b/include/asm-arm/arch-kirkwood/dma.h
18158 @@ -0,0 +1 @@
18159 +/* empty */
18160 --- /dev/null
18161 +++ b/include/asm-arm/arch-kirkwood/entry-macro.S
18162 @@ -0,0 +1,40 @@
18163 +/*
18164 + * include/asm-arm/arch-kirkwood/entry-macro.S
18165 + *
18166 + * Low-level IRQ helper macros for Marvell Kirkwood platforms
18167 + *
18168 + * This file is licensed under the terms of the GNU General Public
18169 + * License version 2.  This program is licensed "as is" without any
18170 + * warranty of any kind, whether express or implied.
18171 + */
18172 +
18173 +#include <asm/arch/kirkwood.h>
18174 +
18175 +       .macro  disable_fiq
18176 +       .endm
18177 +
18178 +       .macro  arch_ret_to_user, tmp1, tmp2
18179 +       .endm
18180 +
18181 +       .macro  get_irqnr_preamble, base, tmp
18182 +       ldr     \base, =IRQ_VIRT_BASE
18183 +       .endm
18184 +
18185 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
18186 +       @ check low interrupts
18187 +       ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
18188 +       ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
18189 +       mov     \irqnr, #31
18190 +       ands    \irqstat, \irqstat, \tmp
18191 +       bne     1001f
18192 +
18193 +       @ if no low interrupts set, check high interrupts
18194 +       ldr     \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
18195 +       ldr     \tmp, [\base, #IRQ_MASK_HIGH_OFF]
18196 +       mov     \irqnr, #63
18197 +       ands    \irqstat, \irqstat, \tmp
18198 +
18199 +       @ find first active interrupt source
18200 +1001:  clzne   \irqstat, \irqstat
18201 +       subne   \irqnr, \irqnr, \irqstat
18202 +       .endm
18203 --- /dev/null
18204 +++ b/include/asm-arm/arch-kirkwood/hardware.h
18205 @@ -0,0 +1,21 @@
18206 +/*
18207 + * include/asm-arm/arch-kirkwood/hardware.h
18208 + *
18209 + * This program is free software; you can redistribute it and/or modify
18210 + * it under the terms of the GNU General Public License version 2 as
18211 + * published by the Free Software Foundation.
18212 + */
18213 +
18214 +#ifndef __ASM_ARCH_HARDWARE_H
18215 +#define __ASM_ARCH_HARDWARE_H
18216 +
18217 +#include "kirkwood.h"
18218 +
18219 +#define pcibios_assign_all_busses()    1
18220 +
18221 +#define PCIBIOS_MIN_IO                 0x00001000
18222 +#define PCIBIOS_MIN_MEM                        0x01000000
18223 +#define PCIMEM_BASE                    KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
18224 +
18225 +
18226 +#endif
18227 --- /dev/null
18228 +++ b/include/asm-arm/arch-kirkwood/io.h
18229 @@ -0,0 +1,26 @@
18230 +/*
18231 + * include/asm-arm/arch-kirkwood/io.h
18232 + *
18233 + * This file is licensed under the terms of the GNU General Public
18234 + * License version 2.  This program is licensed "as is" without any
18235 + * warranty of any kind, whether express or implied.
18236 + */
18237 +
18238 +#ifndef __ASM_ARCH_IO_H
18239 +#define __ASM_ARCH_IO_H
18240 +
18241 +#include "kirkwood.h"
18242 +
18243 +#define IO_SPACE_LIMIT         0xffffffff
18244 +
18245 +static inline void __iomem *__io(unsigned long addr)
18246 +{
18247 +       return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
18248 +                                       + KIRKWOOD_PCIE_IO_VIRT_BASE);
18249 +}
18250 +
18251 +#define __io(a)                        __io(a)
18252 +#define __mem_pci(a)           (a)
18253 +
18254 +
18255 +#endif
18256 --- /dev/null
18257 +++ b/include/asm-arm/arch-kirkwood/irqs.h
18258 @@ -0,0 +1,63 @@
18259 +/*
18260 + * include/asm-arm/arch-kirkwood/irqs.h
18261 + *
18262 + * IRQ definitions for Marvell Kirkwood SoCs
18263 + *
18264 + * This file is licensed under the terms of the GNU General Public
18265 + * License version 2.  This program is licensed "as is" without any
18266 + * warranty of any kind, whether express or implied.
18267 + */
18268 +
18269 +#ifndef __ASM_ARCH_IRQS_H
18270 +#define __ASM_ARCH_IRQS_H
18271 +
18272 +#include "kirkwood.h"  /* need GPIO_MAX */
18273 +
18274 +/*
18275 + * Low Interrupt Controller
18276 + */
18277 +#define IRQ_KIRKWOOD_HIGH_SUM  0
18278 +#define IRQ_KIRKWOOD_BRIDGE    1
18279 +#define IRQ_KIRKWOOD_HOST2CPU  2
18280 +#define IRQ_KIRKWOOD_CPU2HOST  3
18281 +#define IRQ_KIRKWOOD_XOR_00    5
18282 +#define IRQ_KIRKWOOD_XOR_01    6
18283 +#define IRQ_KIRKWOOD_XOR_10    7
18284 +#define IRQ_KIRKWOOD_XOR_11    8
18285 +#define IRQ_KIRKWOOD_PCIE      9
18286 +#define IRQ_KIRKWOOD_GE00_SUM  11
18287 +#define IRQ_KIRKWOOD_GE01_SUM  15
18288 +#define IRQ_KIRKWOOD_USB       19
18289 +#define IRQ_KIRKWOOD_SATA      21
18290 +#define IRQ_KIRKWOOD_CRYPTO    22
18291 +#define IRQ_KIRKWOOD_SPI       23
18292 +#define IRQ_KIRKWOOD_I2S       24
18293 +#define IRQ_KIRKWOOD_TS_0      26
18294 +#define IRQ_KIRKWOOD_SDIO      28
18295 +#define IRQ_KIRKWOOD_TWSI      29
18296 +#define IRQ_KIRKWOOD_AVB       30
18297 +#define IRQ_KIRKWOOD_TDMI      31
18298 +
18299 +/*
18300 + * High Interrupt Controller
18301 + */
18302 +#define IRQ_KIRKWOOD_UART_0    33
18303 +#define IRQ_KIRKWOOD_UART_1    34
18304 +#define IRQ_KIRKWOOD_GPIO_LOW_0_7      35
18305 +#define IRQ_KIRKWOOD_GPIO_LOW_8_15     36
18306 +#define IRQ_KIRKWOOD_GPIO_LOW_16_23    37
18307 +#define IRQ_KIRKWOOD_GPIO_LOW_24_31    38
18308 +#define IRQ_KIRKWOOD_GPIO_HIGH_0_7     39
18309 +#define IRQ_KIRKWOOD_GPIO_HIGH_8_15    40
18310 +#define IRQ_KIRKWOOD_GPIO_HIGH_16_23   41
18311 +
18312 +/*
18313 + * KIRKWOOD General Purpose Pins
18314 + */
18315 +#define IRQ_KIRKWOOD_GPIO_START        64
18316 +#define NR_GPIO_IRQS           GPIO_MAX
18317 +
18318 +#define NR_IRQS                        (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
18319 +
18320 +
18321 +#endif
18322 --- /dev/null
18323 +++ b/include/asm-arm/arch-kirkwood/kirkwood.h
18324 @@ -0,0 +1,99 @@
18325 +/*
18326 + * include/asm-arm/arch-kirkwood/kirkwood.h
18327 + *
18328 + * Generic definitions for Marvell Kirkwood SoC flavors:
18329 + *  88F6180, 88F6192 and 88F6281.
18330 + *
18331 + * This file is licensed under the terms of the GNU General Public
18332 + * License version 2.  This program is licensed "as is" without any
18333 + * warranty of any kind, whether express or implied.
18334 + */
18335 +
18336 +#ifndef __ASM_ARCH_KIRKWOOD_H
18337 +#define __ASM_ARCH_KIRKWOOD_H
18338 +
18339 +/*
18340 + * Marvell Kirkwood address maps.
18341 + *
18342 + * phys
18343 + * e0000000    PCIe Memory space
18344 + * f1000000    on-chip peripheral registers
18345 + * f2000000    PCIe I/O space
18346 + * f3000000    NAND controller address window
18347 + *
18348 + * virt                phys            size
18349 + * fee00000    f1000000        1M      on-chip peripheral registers
18350 + * fef00000    f2000000        1M      PCIe I/O space
18351 + */
18352 +
18353 +#define KIRKWOOD_NAND_MEM_PHYS_BASE    0xf3000000
18354 +#define KIRKWOOD_NAND_MEM_SIZE         SZ_64K /* 1K is sufficient, but 64K
18355 +                                               * is the minimal window size
18356 +                                               */
18357 +
18358 +#define KIRKWOOD_PCIE_IO_PHYS_BASE     0xf2000000
18359 +#define KIRKWOOD_PCIE_IO_VIRT_BASE     0xfef00000
18360 +#define KIRKWOOD_PCIE_IO_BUS_BASE      0x00000000
18361 +#define KIRKWOOD_PCIE_IO_SIZE          SZ_1M
18362 +
18363 +#define KIRKWOOD_REGS_PHYS_BASE                0xf1000000
18364 +#define KIRKWOOD_REGS_VIRT_BASE                0xfee00000
18365 +#define KIRKWOOD_REGS_SIZE             SZ_1M
18366 +
18367 +#define KIRKWOOD_PCIE_MEM_PHYS_BASE    0xe0000000
18368 +#define KIRKWOOD_PCIE_MEM_SIZE         SZ_128M
18369 +
18370 +/*
18371 + * MBUS bridge registers.
18372 + */
18373 +#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
18374 +#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
18375 +#define   CPU_RESET            0x00000002
18376 +//#define   L2_WRITETHROUGH    0x00020000
18377 +#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
18378 +#define   SOFT_RESET_OUT_EN    0x00000004
18379 +#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
18380 +#define   SOFT_RESET           0x00000001
18381 +#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
18382 +#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
18383 +#define   BRIDGE_INT_TIMER0    0x0002
18384 +#define   BRIDGE_INT_TIMER1    0x0004
18385 +#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
18386 +#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
18387 +#define   IRQ_CAUSE_LOW_OFF    0x0000
18388 +#define   IRQ_MASK_LOW_OFF     0x0004
18389 +#define   IRQ_CAUSE_HIGH_OFF   0x0010
18390 +#define   IRQ_MASK_HIGH_OFF    0x0014
18391 +#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
18392 +
18393 +/*
18394 + * Register Map
18395 + */
18396 +#define DDR_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
18397 +#define  DDR_WINDOW_CPU_BASE   (DDR_VIRT_BASE | 0x1500)
18398 +
18399 +#define DEV_BUS_PHYS_BASE      (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
18400 +#define DEV_BUS_VIRT_BASE      (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
18401 +#define  SAMPLE_AT_RESET       (DEV_BUS_VIRT_BASE | 0x0030)
18402 +#define  DEVICE_ID             (DEV_BUS_VIRT_BASE | 0x0034)
18403 +#define  RTC_PHYS_BASE         (DEV_BUS_PHYS_BASE | 0x0300)
18404 +#define  SPI_PHYS_BASE         (DEV_BUS_PHYS_BASE | 0x0600)
18405 +#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2000)
18406 +#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2000)
18407 +#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
18408 +#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
18409 +
18410 +#define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
18411 +
18412 +#define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
18413 +
18414 +#define GE00_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
18415 +#define GE01_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
18416 +
18417 +#define SATA_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
18418 +
18419 +
18420 +#define GPIO_MAX               50
18421 +
18422 +
18423 +#endif
18424 --- /dev/null
18425 +++ b/include/asm-arm/arch-kirkwood/memory.h
18426 @@ -0,0 +1,14 @@
18427 +/*
18428 + * include/asm-arm/arch-kirkwood/memory.h
18429 + */
18430 +
18431 +#ifndef __ASM_ARCH_MEMORY_H
18432 +#define __ASM_ARCH_MEMORY_H
18433 +
18434 +#define PHYS_OFFSET            UL(0x00000000)
18435 +
18436 +#define __virt_to_bus(x)       __virt_to_phys(x)
18437 +#define __bus_to_virt(x)       __phys_to_virt(x)
18438 +
18439 +
18440 +#endif
18441 --- /dev/null
18442 +++ b/include/asm-arm/arch-kirkwood/system.h
18443 @@ -0,0 +1,37 @@
18444 +/*
18445 + * include/asm-arm/arch-kirkwood/system.h
18446 + *
18447 + * This file is licensed under the terms of the GNU General Public
18448 + * License version 2.  This program is licensed "as is" without any
18449 + * warranty of any kind, whether express or implied.
18450 + */
18451 +
18452 +#ifndef __ASM_ARCH_SYSTEM_H
18453 +#define __ASM_ARCH_SYSTEM_H
18454 +
18455 +#include <asm/arch/hardware.h>
18456 +#include <asm/arch/kirkwood.h>
18457 +
18458 +static inline void arch_idle(void)
18459 +{
18460 +       cpu_do_idle();
18461 +}
18462 +
18463 +static inline void arch_reset(char mode)
18464 +{
18465 +       /*
18466 +        * Enable soft reset to assert RSTOUTn.
18467 +        */
18468 +       writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
18469 +
18470 +       /*
18471 +        * Assert soft reset.
18472 +        */
18473 +       writel(SOFT_RESET, SYSTEM_SOFT_RESET);
18474 +
18475 +       while (1)
18476 +               ;
18477 +}
18478 +
18479 +
18480 +#endif
18481 --- /dev/null
18482 +++ b/include/asm-arm/arch-kirkwood/timex.h
18483 @@ -0,0 +1,11 @@
18484 +/*
18485 + * include/asm-arm/arch-kirkwood/timex.h
18486 + *
18487 + * This file is licensed under the terms of the GNU General Public
18488 + * License version 2.  This program is licensed "as is" without any
18489 + * warranty of any kind, whether express or implied.
18490 + */
18491 +
18492 +#define CLOCK_TICK_RATE                (100 * HZ)
18493 +
18494 +#define KIRKWOOD_TCLK          166666667
18495 --- /dev/null
18496 +++ b/include/asm-arm/arch-kirkwood/uncompress.h
18497 @@ -0,0 +1,47 @@
18498 +/*
18499 + * include/asm-arm/arch-kirkwood/uncompress.h
18500 + *
18501 + * This file is licensed under the terms of the GNU General Public
18502 + * License version 2.  This program is licensed "as is" without any
18503 + * warranty of any kind, whether express or implied.
18504 + */
18505 +
18506 +#include <linux/serial_reg.h>
18507 +#include <asm/arch/kirkwood.h>
18508 +
18509 +#define SERIAL_BASE    ((unsigned char *)UART0_PHYS_BASE)
18510 +
18511 +static void putc(const char c)
18512 +{
18513 +       unsigned char *base = SERIAL_BASE;
18514 +       int i;
18515 +
18516 +       for (i = 0; i < 0x1000; i++) {
18517 +               if (base[UART_LSR << 2] & UART_LSR_THRE)
18518 +                       break;
18519 +               barrier();
18520 +       }
18521 +
18522 +       base[UART_TX << 2] = c;
18523 +}
18524 +
18525 +static void flush(void)
18526 +{
18527 +       unsigned char *base = SERIAL_BASE;
18528 +       unsigned char mask;
18529 +       int i;
18530 +
18531 +       mask = UART_LSR_TEMT | UART_LSR_THRE;
18532 +
18533 +       for (i = 0; i < 0x1000; i++) {
18534 +               if ((base[UART_LSR << 2] & mask) == mask)
18535 +                       break;
18536 +               barrier();
18537 +       }
18538 +}
18539 +
18540 +/*
18541 + * nothing to do
18542 + */
18543 +#define arch_decomp_setup()
18544 +#define arch_decomp_wdog()
18545 --- /dev/null
18546 +++ b/include/asm-arm/arch-kirkwood/vmalloc.h
18547 @@ -0,0 +1,5 @@
18548 +/*
18549 + * include/asm-arm/arch-kirkwood/vmalloc.h
18550 + */
18551 +
18552 +#define VMALLOC_END    0xfe800000
18553 --- /dev/null
18554 +++ b/include/asm-arm/arch-loki/debug-macro.S
18555 @@ -0,0 +1,20 @@
18556 +/*
18557 + * include/asm-arm/arch-loki/debug-macro.S
18558 + *
18559 + * This program is free software; you can redistribute it and/or modify
18560 + * it under the terms of the GNU General Public License version 2 as
18561 + * published by the Free Software Foundation.
18562 +*/
18563 +
18564 +#include <asm/arch/loki.h>
18565 +
18566 +       .macro  addruart,rx
18567 +       mrc     p15, 0, \rx, c1, c0
18568 +       tst     \rx, #1                                 @ MMU enabled?
18569 +       ldreq   \rx, =LOKI_REGS_PHYS_BASE
18570 +       ldrne   \rx, =LOKI_REGS_VIRT_BASE
18571 +       orr     \rx, \rx, #0x00012000
18572 +       .endm
18573 +
18574 +#define UART_SHIFT     2
18575 +#include <asm/hardware/debug-8250.S>
18576 --- /dev/null
18577 +++ b/include/asm-arm/arch-loki/dma.h
18578 @@ -0,0 +1 @@
18579 +/* empty */
18580 --- /dev/null
18581 +++ b/include/asm-arm/arch-loki/entry-macro.S
18582 @@ -0,0 +1,30 @@
18583 +/*
18584 + * include/asm-arm/arch-loki/entry-macro.S
18585 + *
18586 + * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
18587 + *
18588 + * This file is licensed under the terms of the GNU General Public
18589 + * License version 2.  This program is licensed "as is" without any
18590 + * warranty of any kind, whether express or implied.
18591 + */
18592 +
18593 +#include <asm/arch/loki.h>
18594 +
18595 +       .macro  disable_fiq
18596 +       .endm
18597 +
18598 +       .macro  arch_ret_to_user, tmp1, tmp2
18599 +       .endm
18600 +
18601 +       .macro  get_irqnr_preamble, base, tmp
18602 +       ldr     \base, =IRQ_VIRT_BASE
18603 +       .endm
18604 +
18605 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
18606 +       ldr     \irqstat, [\base, #IRQ_CAUSE_OFF]
18607 +       ldr     \tmp, [\base, #IRQ_MASK_OFF]
18608 +       mov     \irqnr, #0
18609 +       ands    \irqstat, \irqstat, \tmp
18610 +       clzne   \irqnr, \irqstat
18611 +       rsbne   \irqnr, \irqnr, #31
18612 +       .endm
18613 --- /dev/null
18614 +++ b/include/asm-arm/arch-loki/hardware.h
18615 @@ -0,0 +1,15 @@
18616 +/*
18617 + * include/asm-arm/arch-loki/hardware.h
18618 + *
18619 + * This program is free software; you can redistribute it and/or modify
18620 + * it under the terms of the GNU General Public License version 2 as
18621 + * published by the Free Software Foundation.
18622 + */
18623 +
18624 +#ifndef __ASM_ARCH_HARDWARE_H
18625 +#define __ASM_ARCH_HARDWARE_H
18626 +
18627 +#include "loki.h"
18628 +
18629 +
18630 +#endif
18631 --- /dev/null
18632 +++ b/include/asm-arm/arch-loki/io.h
18633 @@ -0,0 +1,26 @@
18634 +/*
18635 + * include/asm-arm/arch-loki/io.h
18636 + *
18637 + * This file is licensed under the terms of the GNU General Public
18638 + * License version 2.  This program is licensed "as is" without any
18639 + * warranty of any kind, whether express or implied.
18640 + */
18641 +
18642 +#ifndef __ASM_ARCH_IO_H
18643 +#define __ASM_ARCH_IO_H
18644 +
18645 +#include "loki.h"
18646 +
18647 +#define IO_SPACE_LIMIT         0xffffffff
18648 +
18649 +static inline void __iomem *__io(unsigned long addr)
18650 +{
18651 +       return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
18652 +                                       + LOKI_PCIE0_IO_VIRT_BASE);
18653 +}
18654 +
18655 +#define __io(a)                        __io(a)
18656 +#define __mem_pci(a)           (a)
18657 +
18658 +
18659 +#endif
18660 --- /dev/null
18661 +++ b/include/asm-arm/arch-loki/irqs.h
18662 @@ -0,0 +1,58 @@
18663 +/*
18664 + * include/asm-arm/arch-loki/irqs.h
18665 + *
18666 + * IRQ definitions for Marvell Loki (88RC8480) SoCs
18667 + *
18668 + * This file is licensed under the terms of the GNU General Public
18669 + * License version 2.  This program is licensed "as is" without any
18670 + * warranty of any kind, whether express or implied.
18671 + */
18672 +
18673 +#ifndef __ASM_ARCH_IRQS_H
18674 +#define __ASM_ARCH_IRQS_H
18675 +
18676 +#include "loki.h"      /* need GPIO_MAX */
18677 +
18678 +/*
18679 + * Interrupt Controller
18680 + */
18681 +#define IRQ_LOKI_PCIE_A_CPU_DRBL       0
18682 +#define IRQ_LOKI_CPU_PCIE_A_DRBL       1
18683 +#define IRQ_LOKI_PCIE_B_CPU_DRBL       2
18684 +#define IRQ_LOKI_CPU_PCIE_B_DRBL       3
18685 +#define IRQ_LOKI_COM_A_ERR             6
18686 +#define IRQ_LOKI_COM_A_IN              7
18687 +#define IRQ_LOKI_COM_A_OUT             8
18688 +#define IRQ_LOKI_COM_B_ERR             9
18689 +#define IRQ_LOKI_COM_B_IN              10
18690 +#define IRQ_LOKI_COM_B_OUT             11
18691 +#define IRQ_LOKI_DMA_A                 12
18692 +#define IRQ_LOKI_DMA_B                 13
18693 +#define IRQ_LOKI_SAS_A                 14
18694 +#define IRQ_LOKI_SAS_B                 15
18695 +#define IRQ_LOKI_DDR                   16
18696 +#define IRQ_LOKI_XOR                   17
18697 +#define IRQ_LOKI_BRIDGE                        18
18698 +#define IRQ_LOKI_PCIE_A_ERR            20
18699 +#define IRQ_LOKI_PCIE_A_INT            21
18700 +#define IRQ_LOKI_PCIE_B_ERR            22
18701 +#define IRQ_LOKI_PCIE_B_INT            23
18702 +#define IRQ_LOKI_GBE_A_INT             24
18703 +#define IRQ_LOKI_GBE_B_INT             25
18704 +#define IRQ_LOKI_DEV_ERR               26
18705 +#define IRQ_LOKI_UART0                 27
18706 +#define IRQ_LOKI_UART1                 28
18707 +#define IRQ_LOKI_TWSI                  29
18708 +#define IRQ_LOKI_GPIO_23_0             30
18709 +#define IRQ_LOKI_GPIO_25_24            31
18710 +
18711 +/*
18712 + * Loki General Purpose Pins
18713 + */
18714 +#define IRQ_LOKI_GPIO_START    32
18715 +#define NR_GPIO_IRQS           GPIO_MAX
18716 +
18717 +#define NR_IRQS                        (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
18718 +
18719 +
18720 +#endif
18721 --- /dev/null
18722 +++ b/include/asm-arm/arch-loki/loki.h
18723 @@ -0,0 +1,97 @@
18724 +/*
18725 + * include/asm-arm/arch-loki/loki.h
18726 + *
18727 + * Generic definitions for Marvell Loki (88RC8480) SoC flavors
18728 + *
18729 + * This file is licensed under the terms of the GNU General Public
18730 + * License version 2.  This program is licensed "as is" without any
18731 + * warranty of any kind, whether express or implied.
18732 + */
18733 +
18734 +#ifndef __ASM_ARCH_LOKI_H
18735 +#define __ASM_ARCH_LOKI_H
18736 +
18737 +/*
18738 + * Marvell Loki (88RC8480) address maps.
18739 + *
18740 + * phys
18741 + * d0000000    on-chip peripheral registers
18742 + * e0000000    PCIe 0 Memory space
18743 + * e8000000    PCIe 1 Memory space
18744 + * f0000000    PCIe 0 I/O space
18745 + * f0100000    PCIe 1 I/O space
18746 + *
18747 + * virt                phys            size
18748 + * fed00000    d0000000        1M      on-chip peripheral registers
18749 + * fee00000    f0000000        64K     PCIe 0 I/O space
18750 + * fef00000    f0100000        64K     PCIe 1 I/O space
18751 + */
18752 +
18753 +#define LOKI_REGS_PHYS_BASE            0xd0000000
18754 +#define LOKI_REGS_VIRT_BASE            0xfed00000
18755 +#define LOKI_REGS_SIZE                 SZ_1M
18756 +
18757 +#define LOKI_PCIE0_IO_PHYS_BASE                0xf0000000
18758 +#define LOKI_PCIE0_IO_VIRT_BASE                0xfee00000
18759 +#define LOKI_PCIE0_IO_BUS_BASE         0x00000000
18760 +#define LOKI_PCIE0_IO_SIZE             SZ_64K
18761 +
18762 +#define LOKI_PCIE1_IO_PHYS_BASE                0xf0100000
18763 +#define LOKI_PCIE1_IO_VIRT_BASE                0xfef00000
18764 +#define LOKI_PCIE1_IO_BUS_BASE         0x00000000
18765 +#define LOKI_PCIE1_IO_SIZE             SZ_64K
18766 +
18767 +#define LOKI_PCIE0_MEM_PHYS_BASE       0xe0000000
18768 +#define LOKI_PCIE0_MEM_SIZE            SZ_128M
18769 +
18770 +#define LOKI_PCIE1_MEM_PHYS_BASE       0xe8000000
18771 +#define LOKI_PCIE1_MEM_SIZE            SZ_128M
18772 +
18773 +/*
18774 + * Register Map
18775 + */
18776 +#define DEV_BUS_PHYS_BASE      (LOKI_REGS_PHYS_BASE | 0x10000)
18777 +#define DEV_BUS_VIRT_BASE      (LOKI_REGS_VIRT_BASE | 0x10000)
18778 +#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2000)
18779 +#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2000)
18780 +#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
18781 +#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
18782 +
18783 +#define BRIDGE_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x20000)
18784 +#define  BRIDGE_REG(x)         (BRIDGE_VIRT_BASE | (x))
18785 +#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
18786 +#define   SOFT_RESET_OUT_EN    0x00000004
18787 +#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
18788 +#define   SOFT_RESET           0x00000001
18789 +#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
18790 +#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
18791 +#define   BRIDGE_INT_TIMER0    0x0002
18792 +#define   BRIDGE_INT_TIMER1    0x0004
18793 +#define   BRIDGE_INT_TIMER1_CLR        0x0004
18794 +#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
18795 +#define   IRQ_CAUSE_OFF                0x0000
18796 +#define   IRQ_MASK_OFF         0x0004
18797 +#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
18798 +
18799 +#define PCIE0_VIRT_BASE                (LOKI_REGS_VIRT_BASE | 0x30000)
18800 +
18801 +#define PCIE1_VIRT_BASE                (LOKI_REGS_VIRT_BASE | 0x40000)
18802 +
18803 +#define SAS0_PHYS_BASE         (LOKI_REGS_PHYS_BASE | 0x80000)
18804 +
18805 +#define SAS1_PHYS_BASE         (LOKI_REGS_PHYS_BASE | 0x90000)
18806 +
18807 +#define GE0_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0xa0000)
18808 +#define GE0_VIRT_BASE          (LOKI_REGS_VIRT_BASE | 0xa0000)
18809 +
18810 +#define GE1_PHYS_BASE          (LOKI_REGS_PHYS_BASE | 0xb0000)
18811 +#define GE1_VIRT_BASE          (LOKI_REGS_VIRT_BASE | 0xb0000)
18812 +
18813 +#define DDR_VIRT_BASE          (LOKI_REGS_VIRT_BASE | 0xf0000)
18814 +#define DDR_REG(x)             (DDR_VIRT_BASE | (x))
18815 +
18816 +
18817 +#define GPIO_MAX               8
18818 +
18819 +
18820 +#endif
18821 --- /dev/null
18822 +++ b/include/asm-arm/arch-loki/memory.h
18823 @@ -0,0 +1,14 @@
18824 +/*
18825 + * include/asm-arm/arch-loki/memory.h
18826 + */
18827 +
18828 +#ifndef __ASM_ARCH_MEMORY_H
18829 +#define __ASM_ARCH_MEMORY_H
18830 +
18831 +#define PHYS_OFFSET            UL(0x00000000)
18832 +
18833 +#define __virt_to_bus(x)       __virt_to_phys(x)
18834 +#define __bus_to_virt(x)       __phys_to_virt(x)
18835 +
18836 +
18837 +#endif
18838 --- /dev/null
18839 +++ b/include/asm-arm/arch-loki/system.h
18840 @@ -0,0 +1,37 @@
18841 +/*
18842 + * include/asm-arm/arch-loki/system.h
18843 + *
18844 + * This file is licensed under the terms of the GNU General Public
18845 + * License version 2.  This program is licensed "as is" without any
18846 + * warranty of any kind, whether express or implied.
18847 + */
18848 +
18849 +#ifndef __ASM_ARCH_SYSTEM_H
18850 +#define __ASM_ARCH_SYSTEM_H
18851 +
18852 +#include <asm/arch/hardware.h>
18853 +#include <asm/arch/loki.h>
18854 +
18855 +static inline void arch_idle(void)
18856 +{
18857 +       cpu_do_idle();
18858 +}
18859 +
18860 +static inline void arch_reset(char mode)
18861 +{
18862 +       /*
18863 +        * Enable soft reset to assert RSTOUTn.
18864 +        */
18865 +       writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
18866 +
18867 +       /*
18868 +        * Assert soft reset.
18869 +        */
18870 +       writel(SOFT_RESET, SYSTEM_SOFT_RESET);
18871 +
18872 +       while (1)
18873 +               ;
18874 +}
18875 +
18876 +
18877 +#endif
18878 --- /dev/null
18879 +++ b/include/asm-arm/arch-loki/timex.h
18880 @@ -0,0 +1,11 @@
18881 +/*
18882 + * include/asm-arm/arch-loki/timex.h
18883 + *
18884 + * This file is licensed under the terms of the GNU General Public
18885 + * License version 2.  This program is licensed "as is" without any
18886 + * warranty of any kind, whether express or implied.
18887 + */
18888 +
18889 +#define CLOCK_TICK_RATE                (100 * HZ)
18890 +
18891 +#define LOKI_TCLK              180000000
18892 --- /dev/null
18893 +++ b/include/asm-arm/arch-loki/uncompress.h
18894 @@ -0,0 +1,47 @@
18895 +/*
18896 + * include/asm-arm/arch-loki/uncompress.h
18897 + *
18898 + * This file is licensed under the terms of the GNU General Public
18899 + * License version 2.  This program is licensed "as is" without any
18900 + * warranty of any kind, whether express or implied.
18901 + */
18902 +
18903 +#include <linux/serial_reg.h>
18904 +#include <asm/arch/loki.h>
18905 +
18906 +#define SERIAL_BASE    ((unsigned char *)UART0_PHYS_BASE)
18907 +
18908 +static void putc(const char c)
18909 +{
18910 +       unsigned char *base = SERIAL_BASE;
18911 +       int i;
18912 +
18913 +       for (i = 0; i < 0x1000; i++) {
18914 +               if (base[UART_LSR << 2] & UART_LSR_THRE)
18915 +                       break;
18916 +               barrier();
18917 +       }
18918 +
18919 +       base[UART_TX << 2] = c;
18920 +}
18921 +
18922 +static void flush(void)
18923 +{
18924 +       unsigned char *base = SERIAL_BASE;
18925 +       unsigned char mask;
18926 +       int i;
18927 +
18928 +       mask = UART_LSR_TEMT | UART_LSR_THRE;
18929 +
18930 +       for (i = 0; i < 0x1000; i++) {
18931 +               if ((base[UART_LSR << 2] & mask) == mask)
18932 +                       break;
18933 +               barrier();
18934 +       }
18935 +}
18936 +
18937 +/*
18938 + * nothing to do
18939 + */
18940 +#define arch_decomp_setup()
18941 +#define arch_decomp_wdog()
18942 --- /dev/null
18943 +++ b/include/asm-arm/arch-loki/vmalloc.h
18944 @@ -0,0 +1,5 @@
18945 +/*
18946 + * include/asm-arm/arch-loki/vmalloc.h
18947 + */
18948 +
18949 +#define VMALLOC_END    0xfe800000
18950 --- /dev/null
18951 +++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
18952 @@ -0,0 +1,20 @@
18953 +/*
18954 + * include/asm-arm/arch-mv78xx0/debug-macro.S
18955 + *
18956 + * This program is free software; you can redistribute it and/or modify
18957 + * it under the terms of the GNU General Public License version 2 as
18958 + * published by the Free Software Foundation.
18959 +*/
18960 +
18961 +#include <asm/arch/mv78xx0.h>
18962 +
18963 +       .macro  addruart,rx
18964 +       mrc     p15, 0, \rx, c1, c0
18965 +       tst     \rx, #1                                 @ MMU enabled?
18966 +       ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
18967 +       ldrne   \rx, =MV78XX0_REGS_VIRT_BASE
18968 +       orr     \rx, \rx, #0x00012000
18969 +       .endm
18970 +
18971 +#define UART_SHIFT     2
18972 +#include <asm/hardware/debug-8250.S>
18973 --- /dev/null
18974 +++ b/include/asm-arm/arch-mv78xx0/dma.h
18975 @@ -0,0 +1 @@
18976 +/* empty */
18977 --- /dev/null
18978 +++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
18979 @@ -0,0 +1,39 @@
18980 +/*
18981 + * include/asm-arm/arch-mv78xx0/entry-macro.S
18982 + *
18983 + * Low-level IRQ helper macros for Marvell MV78xx0 platforms
18984 + *
18985 + * This file is licensed under the terms of the GNU General Public
18986 + * License version 2.  This program is licensed "as is" without any
18987 + * warranty of any kind, whether express or implied.
18988 + */
18989 +
18990 +#include <asm/arch/mv78xx0.h>
18991 +
18992 +       .macro  disable_fiq
18993 +       .endm
18994 +
18995 +       .macro  arch_ret_to_user, tmp1, tmp2
18996 +       .endm
18997 +
18998 +       .macro  get_irqnr_preamble, base, tmp
18999 +       ldr     \base, =IRQ_VIRT_BASE
19000 +       .endm
19001 +
19002 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
19003 +       @ check low interrupts
19004 +       ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
19005 +       ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
19006 +       mov     \irqnr, #31
19007 +       ands    \irqstat, \irqstat, \tmp
19008 +
19009 +       @ if no low interrupts set, check high interrupts
19010 +       ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
19011 +       ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
19012 +       moveq   \irqnr, #63
19013 +       andeqs  \irqstat, \irqstat, \tmp
19014 +
19015 +       @ find first active interrupt source
19016 +       clzne   \irqstat, \irqstat
19017 +       subne   \irqnr, \irqnr, \irqstat
19018 +       .endm
19019 --- /dev/null
19020 +++ b/include/asm-arm/arch-mv78xx0/hardware.h
19021 @@ -0,0 +1,21 @@
19022 +/*
19023 + * include/asm-arm/arch-mv78xx0/hardware.h
19024 + *
19025 + * This file is licensed under the terms of the GNU General Public
19026 + * License version 2.  This program is licensed "as is" without any
19027 + * warranty of any kind, whether express or implied.
19028 + */
19029 +
19030 +#ifndef __ASM_ARCH_HARDWARE_H
19031 +#define __ASM_ARCH_HARDWARE_H
19032 +
19033 +#include "mv78xx0.h"
19034 +
19035 +#define pcibios_assign_all_busses()    1
19036 +
19037 +#define PCIBIOS_MIN_IO                 0x00001000
19038 +#define PCIBIOS_MIN_MEM                        0x01000000
19039 +#define PCIMEM_BASE                    MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19040 +
19041 +
19042 +#endif
19043 --- /dev/null
19044 +++ b/include/asm-arm/arch-mv78xx0/io.h
19045 @@ -0,0 +1,26 @@
19046 +/*
19047 + * include/asm-arm/arch-mv78xx0/io.h
19048 + *
19049 + * This file is licensed under the terms of the GNU General Public
19050 + * License version 2.  This program is licensed "as is" without any
19051 + * warranty of any kind, whether express or implied.
19052 + */
19053 +
19054 +#ifndef __ASM_ARCH_IO_H
19055 +#define __ASM_ARCH_IO_H
19056 +
19057 +#include "mv78xx0.h"
19058 +
19059 +#define IO_SPACE_LIMIT         0xffffffff
19060 +
19061 +static inline void __iomem *__io(unsigned long addr)
19062 +{
19063 +       return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19064 +                                       + MV78XX0_PCIE_IO_VIRT_BASE(0));
19065 +}
19066 +
19067 +#define __io(a)                        __io(a)
19068 +#define __mem_pci(a)           (a)
19069 +
19070 +
19071 +#endif
19072 --- /dev/null
19073 +++ b/include/asm-arm/arch-mv78xx0/irqs.h
19074 @@ -0,0 +1,91 @@
19075 +/*
19076 + * include/asm-arm/arch-mv78xx0/irqs.h
19077 + *
19078 + * IRQ definitions for Marvell MV78xx0 SoCs
19079 + *
19080 + * This file is licensed under the terms of the GNU General Public
19081 + * License version 2.  This program is licensed "as is" without any
19082 + * warranty of any kind, whether express or implied.
19083 + */
19084 +
19085 +#ifndef __ASM_ARCH_IRQS_H
19086 +#define __ASM_ARCH_IRQS_H
19087 +
19088 +#include "mv78xx0.h"   /* need GPIO_MAX */
19089 +
19090 +/*
19091 + * MV78xx0 Low Interrupt Controller
19092 + */
19093 +#define IRQ_MV78XX0_ERR                0
19094 +#define IRQ_MV78XX0_SPI                1
19095 +#define IRQ_MV78XX0_I2C_0      2
19096 +#define IRQ_MV78XX0_I2C_1      3
19097 +#define IRQ_MV78XX0_IDMA_0     4
19098 +#define IRQ_MV78XX0_IDMA_1     5
19099 +#define IRQ_MV78XX0_IDMA_2     6
19100 +#define IRQ_MV78XX0_IDMA_3     7
19101 +#define IRQ_MV78XX0_TIMER_0    8
19102 +#define IRQ_MV78XX0_TIMER_1    9
19103 +#define IRQ_MV78XX0_TIMER_2    10
19104 +#define IRQ_MV78XX0_TIMER_3    11
19105 +#define IRQ_MV78XX0_UART_0     12
19106 +#define IRQ_MV78XX0_UART_1     13
19107 +#define IRQ_MV78XX0_UART_2     14
19108 +#define IRQ_MV78XX0_UART_3     15
19109 +#define IRQ_MV78XX0_USB_0      16
19110 +#define IRQ_MV78XX0_USB_1      17
19111 +#define IRQ_MV78XX0_USB_2      18
19112 +#define IRQ_MV78XX0_CRYPTO     19
19113 +#define IRQ_MV78XX0_SDIO_0     20
19114 +#define IRQ_MV78XX0_SDIO_1     21
19115 +#define IRQ_MV78XX0_XOR_0      22
19116 +#define IRQ_MV78XX0_XOR_1      23
19117 +#define IRQ_MV78XX0_I2S_0      24
19118 +#define IRQ_MV78XX0_I2S_1      25
19119 +#define IRQ_MV78XX0_SATA       26
19120 +#define IRQ_MV78XX0_TDMI       27
19121 +
19122 +/*
19123 + * MV78xx0 High Interrupt Controller
19124 + */
19125 +#define IRQ_MV78XX0_PCIE_00    32
19126 +#define IRQ_MV78XX0_PCIE_01    33
19127 +#define IRQ_MV78XX0_PCIE_02    34
19128 +#define IRQ_MV78XX0_PCIE_03    35
19129 +#define IRQ_MV78XX0_PCIE_10    36
19130 +#define IRQ_MV78XX0_PCIE_11    37
19131 +#define IRQ_MV78XX0_PCIE_12    38
19132 +#define IRQ_MV78XX0_PCIE_13    39
19133 +#define IRQ_MV78XX0_GE00_SUM   40
19134 +#define IRQ_MV78XX0_GE00_RX    41
19135 +#define IRQ_MV78XX0_GE00_TX    42
19136 +#define IRQ_MV78XX0_GE00_MISC  43
19137 +#define IRQ_MV78XX0_GE01_SUM   44
19138 +#define IRQ_MV78XX0_GE01_RX    45
19139 +#define IRQ_MV78XX0_GE01_TX    46
19140 +#define IRQ_MV78XX0_GE01_MISC  47
19141 +#define IRQ_MV78XX0_GE10_SUM   48
19142 +#define IRQ_MV78XX0_GE10_RX    49
19143 +#define IRQ_MV78XX0_GE10_TX    50
19144 +#define IRQ_MV78XX0_GE10_MISC  51
19145 +#define IRQ_MV78XX0_GE11_SUM   52
19146 +#define IRQ_MV78XX0_GE11_RX    53
19147 +#define IRQ_MV78XX0_GE11_TX    54
19148 +#define IRQ_MV78XX0_GE11_MISC  55
19149 +#define IRQ_MV78XX0_GPIO_0_7   56
19150 +#define IRQ_MV78XX0_GPIO_8_15  57
19151 +#define IRQ_MV78XX0_GPIO_16_23 58
19152 +#define IRQ_MV78XX0_GPIO_24_31 59
19153 +#define IRQ_MV78XX0_DB_IN      60
19154 +#define IRQ_MV78XX0_DB_OUT     61
19155 +
19156 +/*
19157 + * MV78XX0 General Purpose Pins
19158 + */
19159 +#define IRQ_MV78XX0_GPIO_START 64
19160 +#define NR_GPIO_IRQS           GPIO_MAX
19161 +
19162 +#define NR_IRQS                        (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
19163 +
19164 +
19165 +#endif
19166 --- /dev/null
19167 +++ b/include/asm-arm/arch-mv78xx0/memory.h
19168 @@ -0,0 +1,14 @@
19169 +/*
19170 + * include/asm-arm/arch-mv78xx0/memory.h
19171 + */
19172 +
19173 +#ifndef __ASM_ARCH_MEMORY_H
19174 +#define __ASM_ARCH_MEMORY_H
19175 +
19176 +#define PHYS_OFFSET            UL(0x00000000)
19177 +
19178 +#define __virt_to_bus(x)       __virt_to_phys(x)
19179 +#define __bus_to_virt(x)       __phys_to_virt(x)
19180 +
19181 +
19182 +#endif
19183 --- /dev/null
19184 +++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
19185 @@ -0,0 +1,126 @@
19186 +/*
19187 + * include/asm-arm/arch-mv78xx0/mv78xx0.h
19188 + *
19189 + * Generic definitions for Marvell MV78xx0 SoC flavors:
19190 + *  MV781x0 and MV782x0.
19191 + *
19192 + * This file is licensed under the terms of the GNU General Public
19193 + * License version 2.  This program is licensed "as is" without any
19194 + * warranty of any kind, whether express or implied.
19195 + */
19196 +
19197 +#ifndef __ASM_ARCH_MV78XX0_H
19198 +#define __ASM_ARCH_MV78XX0_H
19199 +
19200 +/*
19201 + * Marvell MV78xx0 address maps.
19202 + *
19203 + * phys
19204 + * c0000000    PCIe Memory space
19205 + * f0800000    PCIe #0 I/O space
19206 + * f0900000    PCIe #1 I/O space
19207 + * f0a00000    PCIe #2 I/O space
19208 + * f0b00000    PCIe #3 I/O space
19209 + * f0c00000    PCIe #4 I/O space
19210 + * f0d00000    PCIe #5 I/O space
19211 + * f0e00000    PCIe #6 I/O space
19212 + * f0f00000    PCIe #7 I/O space
19213 + * f1000000    on-chip peripheral registers
19214 + *
19215 + * virt                phys            size
19216 + * fe400000    f102x000        16K     core-specific peripheral registers
19217 + * fe700000    f0800000        1M      PCIe #0 I/O space
19218 + * fe800000    f0900000        1M      PCIe #1 I/O space
19219 + * fe900000    f0a00000        1M      PCIe #2 I/O space
19220 + * fea00000    f0b00000        1M      PCIe #3 I/O space
19221 + * feb00000    f0c00000        1M      PCIe #4 I/O space
19222 + * fec00000    f0d00000        1M      PCIe #5 I/O space
19223 + * fed00000    f0e00000        1M      PCIe #6 I/O space
19224 + * fee00000    f0f00000        1M      PCIe #7 I/O space
19225 + * fef00000    f1000000        1M      on-chip peripheral registers
19226 + */
19227 +#define MV78XX0_CORE0_REGS_PHYS_BASE   0xf1020000
19228 +#define MV78XX0_CORE1_REGS_PHYS_BASE   0xf1024000
19229 +#define MV78XX0_CORE_REGS_VIRT_BASE    0xfe400000
19230 +#define MV78XX0_CORE_REGS_SIZE         SZ_16K
19231 +
19232 +#define MV78XX0_PCIE_IO_PHYS_BASE(i)   (0xf0800000 + ((i) << 20))
19233 +#define MV78XX0_PCIE_IO_VIRT_BASE(i)   (0xfe700000 + ((i) << 20))
19234 +#define MV78XX0_PCIE_IO_SIZE           SZ_1M
19235 +
19236 +#define MV78XX0_REGS_PHYS_BASE         0xf1000000
19237 +#define MV78XX0_REGS_VIRT_BASE         0xfef00000
19238 +#define MV78XX0_REGS_SIZE              SZ_1M
19239 +
19240 +#define MV78XX0_PCIE_MEM_PHYS_BASE     0xc0000000
19241 +#define MV78XX0_PCIE_MEM_SIZE          0x30000000
19242 +
19243 +/*
19244 + * Core-specific peripheral registers.
19245 + */
19246 +#define BRIDGE_VIRT_BASE       (MV78XX0_CORE_REGS_VIRT_BASE)
19247 +#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
19248 +#define   L2_WRITETHROUGH      0x00020000
19249 +#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
19250 +#define   SOFT_RESET_OUT_EN    0x00000004
19251 +#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
19252 +#define   SOFT_RESET           0x00000001
19253 +#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
19254 +#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
19255 +#define   BRIDGE_INT_TIMER0    0x0002
19256 +#define   BRIDGE_INT_TIMER1    0x0004
19257 +#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
19258 +#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
19259 +#define   IRQ_CAUSE_LOW_OFF    0x0004
19260 +#define   IRQ_CAUSE_HIGH_OFF   0x0008
19261 +#define   IRQ_MASK_LOW_OFF     0x0010
19262 +#define   IRQ_MASK_HIGH_OFF    0x0014
19263 +#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
19264 +
19265 +/*
19266 + * Register Map
19267 + */
19268 +#define DDR_VIRT_BASE          (MV78XX0_REGS_VIRT_BASE | 0x00000)
19269 +#define  DDR_WINDOW_CPU0_BASE  (DDR_VIRT_BASE | 0x1500)
19270 +#define  DDR_WINDOW_CPU1_BASE  (DDR_VIRT_BASE | 0x1700)
19271 +
19272 +#define DEV_BUS_PHYS_BASE      (MV78XX0_REGS_PHYS_BASE | 0x10000)
19273 +#define DEV_BUS_VIRT_BASE      (MV78XX0_REGS_VIRT_BASE | 0x10000)
19274 +#define  SAMPLE_AT_RESET_LOW   (DEV_BUS_VIRT_BASE | 0x0030)
19275 +#define  SAMPLE_AT_RESET_HIGH  (DEV_BUS_VIRT_BASE | 0x0034)
19276 +#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2000)
19277 +#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2000)
19278 +#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
19279 +#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
19280 +#define  UART2_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2200)
19281 +#define  UART2_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2200)
19282 +#define  UART3_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2300)
19283 +#define  UART3_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2300)
19284 +
19285 +#define GE10_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x30000)
19286 +#define GE11_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x34000)
19287 +
19288 +#define PCIE00_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x40000)
19289 +#define PCIE01_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x44000)
19290 +#define PCIE02_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x48000)
19291 +#define PCIE03_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x4c000)
19292 +
19293 +#define USB0_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x50000)
19294 +#define USB1_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x51000)
19295 +#define USB2_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x52000)
19296 +
19297 +#define GE00_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x70000)
19298 +#define GE01_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0x74000)
19299 +
19300 +#define PCIE10_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x80000)
19301 +#define PCIE11_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x84000)
19302 +#define PCIE12_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x88000)
19303 +#define PCIE13_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x8c000)
19304 +
19305 +#define SATA_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0xa0000)
19306 +
19307 +
19308 +#define GPIO_MAX               32
19309 +
19310 +
19311 +#endif
19312 --- /dev/null
19313 +++ b/include/asm-arm/arch-mv78xx0/system.h
19314 @@ -0,0 +1,37 @@
19315 +/*
19316 + * include/asm-arm/arch-mv78xx0/system.h
19317 + *
19318 + * This file is licensed under the terms of the GNU General Public
19319 + * License version 2.  This program is licensed "as is" without any
19320 + * warranty of any kind, whether express or implied.
19321 + */
19322 +
19323 +#ifndef __ASM_ARCH_SYSTEM_H
19324 +#define __ASM_ARCH_SYSTEM_H
19325 +
19326 +#include <asm/arch/hardware.h>
19327 +#include <asm/arch/mv78xx0.h>
19328 +
19329 +static inline void arch_idle(void)
19330 +{
19331 +       cpu_do_idle();
19332 +}
19333 +
19334 +static inline void arch_reset(char mode)
19335 +{
19336 +       /*
19337 +        * Enable soft reset to assert RSTOUTn.
19338 +        */
19339 +       writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
19340 +
19341 +       /*
19342 +        * Assert soft reset.
19343 +        */
19344 +       writel(SOFT_RESET, SYSTEM_SOFT_RESET);
19345 +
19346 +       while (1)
19347 +               ;
19348 +}
19349 +
19350 +
19351 +#endif
19352 --- /dev/null
19353 +++ b/include/asm-arm/arch-mv78xx0/timex.h
19354 @@ -0,0 +1,9 @@
19355 +/*
19356 + * include/asm-arm/arch-mv78xx0/timex.h
19357 + *
19358 + * This file is licensed under the terms of the GNU General Public
19359 + * License version 2.  This program is licensed "as is" without any
19360 + * warranty of any kind, whether express or implied.
19361 + */
19362 +
19363 +#define CLOCK_TICK_RATE                (100 * HZ)
19364 --- /dev/null
19365 +++ b/include/asm-arm/arch-mv78xx0/uncompress.h
19366 @@ -0,0 +1,47 @@
19367 +/*
19368 + * include/asm-arm/arch-mv78xx0/uncompress.h
19369 + *
19370 + * This file is licensed under the terms of the GNU General Public
19371 + * License version 2.  This program is licensed "as is" without any
19372 + * warranty of any kind, whether express or implied.
19373 + */
19374 +
19375 +#include <linux/serial_reg.h>
19376 +#include <asm/arch/mv78xx0.h>
19377 +
19378 +#define SERIAL_BASE    ((unsigned char *)UART0_PHYS_BASE)
19379 +
19380 +static void putc(const char c)
19381 +{
19382 +       unsigned char *base = SERIAL_BASE;
19383 +       int i;
19384 +
19385 +       for (i = 0; i < 0x1000; i++) {
19386 +               if (base[UART_LSR << 2] & UART_LSR_THRE)
19387 +                       break;
19388 +               barrier();
19389 +       }
19390 +
19391 +       base[UART_TX << 2] = c;
19392 +}
19393 +
19394 +static void flush(void)
19395 +{
19396 +       unsigned char *base = SERIAL_BASE;
19397 +       unsigned char mask;
19398 +       int i;
19399 +
19400 +       mask = UART_LSR_TEMT | UART_LSR_THRE;
19401 +
19402 +       for (i = 0; i < 0x1000; i++) {
19403 +               if ((base[UART_LSR << 2] & mask) == mask)
19404 +                       break;
19405 +               barrier();
19406 +       }
19407 +}
19408 +
19409 +/*
19410 + * nothing to do
19411 + */
19412 +#define arch_decomp_setup()
19413 +#define arch_decomp_wdog()
19414 --- /dev/null
19415 +++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
19416 @@ -0,0 +1,5 @@
19417 +/*
19418 + * include/asm-arm/arch-mv78xx0/vmalloc.h
19419 + */
19420 +
19421 +#define VMALLOC_END    0xfe000000
19422 --- a/include/asm-arm/arch-orion5x/io.h
19423 +++ b/include/asm-arm/arch-orion5x/io.h
19424 @@ -14,7 +14,6 @@
19425  #include "orion5x.h"
19426
19427  #define IO_SPACE_LIMIT         0xffffffff
19428 -#define IO_SPACE_REMAP         ORION5X_PCI_SYS_IO_BASE
19429
19430  static inline void __iomem *
19431  __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
19432 @@ -53,15 +52,12 @@
19433  /*****************************************************************************
19434   * Helpers to access Orion registers
19435   ****************************************************************************/
19436 -#define orion5x_read(r)                __raw_readl(r)
19437 -#define orion5x_write(r, val)  __raw_writel(val, r)
19438 -
19439  /*
19440   * These are not preempt-safe.  Locks, if needed, must be taken
19441   * care of by the caller.
19442   */
19443 -#define orion5x_setbits(r, mask)       orion5x_write((r), orion5x_read(r) | (mask))
19444 -#define orion5x_clrbits(r, mask)       orion5x_write((r), orion5x_read(r) & ~(mask))
19445 +#define orion5x_setbits(r, mask)       writel(readl(r) | (mask), (r))
19446 +#define orion5x_clrbits(r, mask)       writel(readl(r) & ~(mask), (r))
19447
19448
19449  #endif
19450 --- a/include/asm-arm/arch-orion5x/orion5x.h
19451 +++ b/include/asm-arm/arch-orion5x/orion5x.h
19452 @@ -2,7 +2,7 @@
19453   * include/asm-arm/arch-orion5x/orion5x.h
19454   *
19455   * Generic definitions of Orion SoC flavors:
19456 - *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
19457 + *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
19458   *
19459   * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
19460   *
19461 @@ -63,9 +63,11 @@
19462  /*******************************************************************************
19463   * Supported Devices & Revisions
19464   ******************************************************************************/
19465 -/* Orion-1 (88F5181) */
19466 +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
19467  #define MV88F5181_DEV_ID       0x5181
19468  #define MV88F5181_REV_B1       3
19469 +#define MV88F5181L_REV_A0      8
19470 +#define MV88F5181L_REV_A1      9
19471  /* Orion-NAS (88F5182) */
19472  #define MV88F5182_DEV_ID       0x5182
19473  #define MV88F5182_REV_A2       2
19474 @@ -152,6 +154,7 @@
19475  #define BRIDGE_MASK            ORION5X_BRIDGE_REG(0x114)
19476  #define  BRIDGE_INT_TIMER0     0x0002
19477  #define  BRIDGE_INT_TIMER1     0x0004
19478 +#define  BRIDGE_INT_TIMER1_CLR (~0x0004)
19479  #define MAIN_IRQ_CAUSE         ORION5X_BRIDGE_REG(0x200)
19480  #define MAIN_IRQ_MASK          ORION5X_BRIDGE_REG(0x204)
19481
19482 --- a/include/asm-arm/arch-orion5x/uncompress.h
19483 +++ b/include/asm-arm/arch-orion5x/uncompress.h
19484 @@ -8,23 +8,38 @@
19485   * warranty of any kind, whether express or implied.
19486   */
19487
19488 +#include <linux/serial_reg.h>
19489  #include <asm/arch/orion5x.h>
19490
19491 -#define MV_UART_THR    ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
19492 -#define MV_UART_LSR    ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
19493 -
19494 -#define LSR_THRE       0x20
19495 +#define SERIAL_BASE    ((unsigned char *)UART0_PHYS_BASE)
19496
19497  static void putc(const char c)
19498  {
19499 -       int j = 0x1000;
19500 -       while (--j && !(*MV_UART_LSR & LSR_THRE))
19501 +       unsigned char *base = SERIAL_BASE;
19502 +       int i;
19503 +
19504 +       for (i = 0; i < 0x1000; i++) {
19505 +               if (base[UART_LSR << 2] & UART_LSR_THRE)
19506 +                       break;
19507                 barrier();
19508 -       *MV_UART_THR = c;
19509 +       }
19510 +
19511 +       base[UART_TX << 2] = c;
19512  }
19513
19514  static void flush(void)
19515  {
19516 +       unsigned char *base = SERIAL_BASE;
19517 +       unsigned char mask;
19518 +       int i;
19519 +
19520 +       mask = UART_LSR_TEMT | UART_LSR_THRE;
19521 +
19522 +       for (i = 0; i < 0x1000; i++) {
19523 +               if ((base[UART_LSR << 2] & mask) == mask)
19524 +                       break;
19525 +               barrier();
19526 +       }
19527  }
19528
19529  /*
19530 --- a/include/asm-arm/assembler.h
19531 +++ b/include/asm-arm/assembler.h
19532 @@ -56,6 +56,21 @@
19533  #endif
19534
19535  /*
19536 + * This can be used to enable code to cacheline align the destination
19537 + * pointer when bulk writing to memory.  Experiments on StrongARM and
19538 + * XScale didn't show this a worthwhile thing to do when the cache is not
19539 + * set to write-allocate (this would need further testing on XScale when WA
19540 + * is used).
19541 + *
19542 + * On Feroceon there is much to gain however, regardless of cache mode.
19543 + */
19544 +#ifdef CONFIG_CPU_FEROCEON
19545 +#define CALGN(code...) code
19546 +#else
19547 +#define CALGN(code...)
19548 +#endif
19549 +
19550 +/*
19551   * Enable and disable interrupts
19552   */
19553  #if __LINUX_ARM_ARCH__ >= 6
19554 --- a/include/asm-arm/cacheflush.h
19555 +++ b/include/asm-arm/cacheflush.h
19556 @@ -95,11 +95,7 @@
19557  #endif
19558
19559  #if defined(CONFIG_CPU_FEROCEON)
19560 -# ifdef _CACHE
19561 -#  define MULTI_CACHE 1
19562 -# else
19563 -#  define _CACHE feroceon
19564 -# endif
19565 +# define MULTI_CACHE 1
19566  #endif
19567
19568  #if defined(CONFIG_CPU_V6)
19569 --- /dev/null
19570 +++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
19571 @@ -0,0 +1,11 @@
19572 +/*
19573 + * include/asm-arm/plat-orion/cache-feroceon-l2.h
19574 + *
19575 + * Copyright (C) 2008 Marvell Semiconductor
19576 + *
19577 + * This file is licensed under the terms of the GNU General Public
19578 + * License version 2. This program is licensed "as is" without any
19579 + * warranty of any kind, whether express or implied.
19580 + */
19581 +
19582 +extern void __init feroceon_l2_init(int l2_wt_override);
19583 --- a/include/asm-arm/plat-orion/pcie.h
19584 +++ b/include/asm-arm/plat-orion/pcie.h
19585 @@ -14,6 +14,7 @@
19586  u32 orion_pcie_dev_id(void __iomem *base);
19587  u32 orion_pcie_rev(void __iomem *base);
19588  int orion_pcie_link_up(void __iomem *base);
19589 +int orion_pcie_x4_mode(void __iomem *base);
19590  int orion_pcie_get_local_bus_nr(void __iomem *base);
19591  void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
19592  void orion_pcie_setup(void __iomem *base,
19593 --- a/include/asm-arm/tlbflush.h
19594 +++ b/include/asm-arm/tlbflush.h
19595 @@ -39,6 +39,7 @@
19596  #define TLB_V6_D_ASID  (1 << 17)
19597  #define TLB_V6_I_ASID  (1 << 18)
19598
19599 +#define TLB_L2CLEAN_FR (1 << 29)               /* Feroceon */
19600  #define TLB_DCLEAN     (1 << 30)
19601  #define TLB_WB         (1 << 31)
19602
19603 @@ -51,6 +52,7 @@
19604   *       v4    - ARMv4 without write buffer
19605   *       v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
19606   *       v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
19607 + *       fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
19608   *       v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
19609   */
19610  #undef _TLB
19611 @@ -103,6 +105,23 @@
19612  # define v4wbi_always_flags    (-1UL)
19613  #endif
19614
19615 +#define fr_tlb_flags   (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
19616 +                        TLB_V4_I_FULL | TLB_V4_D_FULL | \
19617 +                        TLB_V4_I_PAGE | TLB_V4_D_PAGE)
19618 +
19619 +#ifdef CONFIG_CPU_TLB_FEROCEON
19620 +# define fr_possible_flags     fr_tlb_flags
19621 +# define fr_always_flags       fr_tlb_flags
19622 +# ifdef _TLB
19623 +#  define MULTI_TLB 1
19624 +# else
19625 +#  define _TLB v4wbi
19626 +# endif
19627 +#else
19628 +# define fr_possible_flags     0
19629 +# define fr_always_flags       (-1UL)
19630 +#endif
19631 +
19632  #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
19633                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
19634                          TLB_V4_D_PAGE)
19635 @@ -245,12 +264,14 @@
19636  #define possible_tlb_flags     (v3_possible_flags | \
19637                                  v4_possible_flags | \
19638                                  v4wbi_possible_flags | \
19639 +                                fr_possible_flags | \
19640                                  v4wb_possible_flags | \
19641                                  v6wbi_possible_flags)
19642
19643  #define always_tlb_flags       (v3_always_flags & \
19644                                  v4_always_flags & \
19645                                  v4wbi_always_flags & \
19646 +                                fr_always_flags & \
19647                                  v4wb_always_flags & \
19648                                  v6wbi_always_flags)
19649
19650 @@ -417,6 +438,11 @@
19651         if (tlb_flag(TLB_DCLEAN))
19652                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
19653                         : : "r" (pmd) : "cc");
19654 +
19655 +       if (tlb_flag(TLB_L2CLEAN_FR))
19656 +               asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
19657 +                       : : "r" (pmd) : "cc");
19658 +
19659         if (tlb_flag(TLB_WB))
19660                 dsb();
19661  }
19662 @@ -428,6 +454,10 @@
19663         if (tlb_flag(TLB_DCLEAN))
19664                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
19665                         : : "r" (pmd) : "cc");
19666 +
19667 +       if (tlb_flag(TLB_L2CLEAN_FR))
19668 +               asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
19669 +                       : : "r" (pmd) : "cc");
19670  }
19671
19672  #undef tlb_flag
19673 --- a/include/linux/mv643xx_eth.h
19674 +++ b/include/linux/mv643xx_eth.h
19675 @@ -17,30 +17,59 @@
19676
19677  struct mv643xx_eth_shared_platform_data {
19678         struct mbus_dram_target_info    *dram;
19679 -       unsigned int    t_clk;
19680 +       unsigned int            t_clk;
19681  };
19682
19683  struct mv643xx_eth_platform_data {
19684 +       /*
19685 +        * Pointer back to our parent instance, and our port number.
19686 +        */
19687         struct platform_device  *shared;
19688 -       int             port_number;
19689 +       int                     port_number;
19690
19691 +       /*
19692 +        * Whether a PHY is present, and if yes, at which address.
19693 +        */
19694         struct platform_device  *shared_smi;
19695 +       int                     force_phy_addr;
19696 +       int                     phy_addr;
19697
19698 -       u16             force_phy_addr; /* force override if phy_addr == 0 */
19699 -       u16             phy_addr;
19700 -
19701 -       /* If speed is 0, then speed and duplex are autonegotiated. */
19702 -       int             speed;          /* 0, SPEED_10, SPEED_100, SPEED_1000 */
19703 -       int             duplex;         /* DUPLEX_HALF or DUPLEX_FULL */
19704 -
19705 -       /* non-zero values of the following fields override defaults */
19706 -       u32             tx_queue_size;
19707 -       u32             rx_queue_size;
19708 -       u32             tx_sram_addr;
19709 -       u32             tx_sram_size;
19710 -       u32             rx_sram_addr;
19711 -       u32             rx_sram_size;
19712 -       u8              mac_addr[6];    /* mac address if non-zero*/
19713 +       /*
19714 +        * Use this MAC address if it is valid, overriding the
19715 +        * address that is already in the hardware.
19716 +        */
19717 +       u8                      mac_addr[6];
19718 +
19719 +       /*
19720 +        * If speed is 0, autonegotiation is enabled.
19721 +        *   Valid values for speed: 0, SPEED_10, SPEED_100, SPEED_1000.
19722 +        *   Valid values for duplex: DUPLEX_HALF, DUPLEX_FULL.
19723 +        */
19724 +       int                     speed;
19725 +       int                     duplex;
19726 +
19727 +       /*
19728 +        * Which RX/TX queues to use.
19729 +        */
19730 +       int                     rx_queue_mask;
19731 +       int                     tx_queue_mask;
19732 +
19733 +       /*
19734 +        * Override default RX/TX queue sizes if nonzero.
19735 +        */
19736 +       int                     rx_queue_size;
19737 +       int                     tx_queue_size;
19738 +
19739 +       /*
19740 +        * Use on-chip SRAM for RX/TX descriptors if size is nonzero
19741 +        * and sufficient to contain all descriptors for the requested
19742 +        * ring sizes.
19743 +        */
19744 +       unsigned long           rx_sram_addr;
19745 +       int                     rx_sram_size;
19746 +       unsigned long           tx_sram_addr;
19747 +       int                     tx_sram_size;
19748  };
19749
19750 -#endif /* __LINUX_MV643XX_ETH_H */
19751 +
19752 +#endif