target/linux/rb532/files/arch/mips/rb500/devices.c

   1 /*
   2  *  RouterBoard 500 Platform devices
   3  *
   4  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/ctype.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/gpio_keys.h>
  26 #include <linux/input.h>
  27
  28 #include <asm/bootinfo.h>
  29
  30 #include <asm/rc32434/rc32434.h>
  31 #include <asm/rc32434/dma.h>
  32 #include <asm/rc32434/dma_v.h>
  33 #include <asm/rc32434/eth.h>
  34 #include <asm/rc32434/rb.h>
  35
  36 #define ETH0_DMA_RX_IRQ         GROUP1_IRQ_BASE + 0
  37 #define ETH0_DMA_TX_IRQ         GROUP1_IRQ_BASE + 1
  38 #define ETH0_RX_OVR_IRQ         GROUP3_IRQ_BASE + 9
  39 #define ETH0_TX_UND_IRQ         GROUP3_IRQ_BASE + 10
  40
  41 #define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
  42 #define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
  43
  44 /* NAND definitions */
  45 #define MEM32(x) *((volatile unsigned *) (x))
  46
  47 #define GPIO_RDY (1 << 0x08)
  48 #define GPIO_WPX (1 << 0x09)
  49 #define GPIO_ALE (1 << 0x0a)
  50 #define GPIO_CLE (1 << 0x0b)
  51
  52 extern char* board_type;
  53
  54 static struct resource korina_dev0_res[] = {
  55         {
  56                 .name = "korina_regs",
  57                 .start = ETH0_PhysicalAddress,
  58                 .end = ETH0_PhysicalAddress + sizeof(ETH_t),
  59                 .flags = IORESOURCE_MEM,
  60          }, {
  61                 .name = "korina_rx",
  62                 .start = ETH0_DMA_RX_IRQ,
  63                 .end = ETH0_DMA_RX_IRQ,
  64                 .flags = IORESOURCE_IRQ
  65         }, {
  66                 .name = "korina_tx",
  67                 .start = ETH0_DMA_TX_IRQ,
  68                 .end = ETH0_DMA_TX_IRQ,
  69                 .flags = IORESOURCE_IRQ
  70         }, {
  71                 .name = "korina_ovr",
  72                 .start = ETH0_RX_OVR_IRQ,
  73                 .end = ETH0_RX_OVR_IRQ,
  74                 .flags = IORESOURCE_IRQ
  75         }, {
  76                 .name = "korina_und",
  77                 .start = ETH0_TX_UND_IRQ,
  78                 .end = ETH0_TX_UND_IRQ,
  79                 .flags = IORESOURCE_IRQ
  80         }, {
  81                 .name = "korina_dma_rx",
  82                 .start = ETH0_RX_DMA_ADDR,
  83                 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  84                 .flags = IORESOURCE_MEM,
  85          }, {
  86                 .name = "korina_dma_tx",
  87                 .start = ETH0_TX_DMA_ADDR,
  88                 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  89                 .flags = IORESOURCE_MEM,
  90          }
  91 };
  92
  93 static struct korina_device korina_dev0_data = {
  94         .name = "korina0",
  95         .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  96 };
  97
  98 static struct platform_device korina_dev0 = {
  99         .id = 0,
 100         .name = "korina",
 101         .dev.platform_data = &korina_dev0_data,
 102         .resource = korina_dev0_res,
 103         .num_resources = ARRAY_SIZE(korina_dev0_res),
 104 };
 105
 106 #define CF_GPIO_NUM 13
 107
 108 static struct resource cf_slot0_res[] = {
 109         {
 110                 .name = "cf_membase",
 111                 .flags = IORESOURCE_MEM
 112         }, {
 113                 .name = "cf_irq",
 114                 .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
 115                 .end = (8 + 4 * 32 + CF_GPIO_NUM),
 116                 .flags = IORESOURCE_IRQ
 117         }
 118 };
 119
 120 static struct cf_device cf_slot0_data = {
 121         .gpio_pin = 13
 122 };
 123
 124 static struct platform_device cf_slot0 = {
 125         .id = 0,
 126         .name = "rb500-cf",
 127         .dev.platform_data = &cf_slot0_data,
 128         .resource = cf_slot0_res,
 129         .num_resources = ARRAY_SIZE(cf_slot0_res),
 130 };
 131
 132 /* Resources and device for NAND.  There is no data needed and no irqs, so just define the memory used. */
 133
 134 /*
 135  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
 136  * will not be able to find the kernel that we load.  So set the oobinfo
 137  * when creating the partitions
 138  */
 139 static struct nand_ecclayout rb500_nand_ecclayout = {
 140         .eccbytes       = 6,
 141         .eccpos         = { 8, 9, 10, 13, 14, 15 },
 142         .oobavail       = 9,
 143         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
 144 };
 145
 146 int rb500_dev_ready(struct mtd_info *mtd)
 147 {
 148         return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
 149 }
 150
 151 void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 152 {
 153         struct nand_chip *chip = mtd->priv;
 154         unsigned char orbits, nandbits;
 155
 156         if (ctrl & NAND_CTRL_CHANGE) {
 157
 158                 orbits = (ctrl & NAND_CLE) << 1;
 159                 orbits |= (ctrl & NAND_ALE) >> 1;
 160
 161                 nandbits = (~ctrl & NAND_CLE) << 1;
 162                 nandbits |= (~ctrl & NAND_ALE) >> 1;
 163
 164                 changeLatchU5(orbits, nandbits);
 165         }
 166         if (cmd != NAND_CMD_NONE)
 167                 writeb(cmd, chip->IO_ADDR_W);
 168 }
 169
 170 static struct resource nand_slot0_res[] = {
 171         [0] = {
 172                 .name = "nand_membase",
 173                 .flags = IORESOURCE_MEM
 174         }
 175 };
 176
 177 struct platform_nand_data rb500_nand_data = {
 178         .ctrl.dev_ready = rb500_dev_ready,
 179         .ctrl.cmd_ctrl  = rb500_cmd_ctrl,
 180 };
 181
 182 static struct platform_device nand_slot0 = {
 183         .name = "gen_nand",
 184         .id = -1,
 185         .resource = nand_slot0_res,
 186         .num_resources = ARRAY_SIZE(nand_slot0_res),
 187         .dev.platform_data = &rb500_nand_data,
 188 };
 189
 190 static struct mtd_partition rb500_partition_info[] = {
 191         {
 192                 .name = "Routerboard NAND boot",
 193                 .offset = 0,
 194                 .size = 4 * 1024 * 1024,
 195         }, {
 196                 .name = "rootfs",
 197                 .offset = MTDPART_OFS_NXTBLK,
 198                 .size = MTDPART_SIZ_FULL,
 199         }
 200 };
 201
 202 static struct platform_device rb500_led = {
 203         .name = "rb500-led",
 204         .id = 0,
 205 };
 206
 207 static struct gpio_keys_button rb500_gpio_btn[] = {
 208         {
 209                 .gpio = 1,
 210                 .code = BTN_0,
 211                 .desc = "S1",
 212                 .active_low = 1,
 213         }
 214 };
 215
 216 static struct gpio_keys_platform_data rb500_gpio_btn_data = {
 217         .buttons = rb500_gpio_btn,
 218         .nbuttons = ARRAY_SIZE(rb500_gpio_btn),
 219 };
 220
 221 static struct platform_device rb500_button = {
 222         .name   = "gpio-keys",
 223         .id     = -1,
 224         .dev    = {
 225                 .platform_data = &rb500_gpio_btn_data,
 226         }
 227 };
 228
 229 static struct platform_device *rb500_devs[] = {
 230         &korina_dev0,
 231         &nand_slot0,
 232         &cf_slot0,
 233         &rb500_led,
 234         &rb500_button
 235 };
 236
 237 static void __init parse_mac_addr(char *macstr)
 238 {
 239         int i, j;
 240         unsigned char result, value;
 241
 242         for (i = 0; i < 6; i++) {
 243                 result = 0;
 244
 245                 if (i != 5 && *(macstr + 2) != ':')
 246                         return;
 247
 248                 for (j = 0; j < 2; j++) {
 249                         if (isxdigit(*macstr)
 250                             && (value =
 251                                 isdigit(*macstr) ? *macstr -
 252                                 '0' : toupper(*macstr) - 'A' + 10) < 16) {
 253                                 result = result * 16 + value;
 254                                 macstr++;
 255                         } else
 256                                 return;
 257                 }
 258
 259                 macstr++;
 260                 korina_dev0_data.mac[i] = result;
 261         }
 262 }
 263
 264
 265 /* DEVICE CONTROLLER 1 */
 266 #define CFG_DC_DEV1 (void*)0xb8010010
 267 #define CFG_DC_DEV2 (void*)0xb8010020
 268 #define CFG_DC_DEVBASE    0x0
 269 #define CFG_DC_DEVMASK    0x4
 270 #define CFG_DC_DEVC       0x8
 271 #define CFG_DC_DEVTC      0xC
 272
 273 /* NAND definitions */
 274 #define NAND_CHIP_DELAY 25
 275
 276 static int rb500_nand_fixup(struct mtd_info *mtd)
 277 {
 278         struct nand_chip *chip = mtd->priv;
 279
 280         if (mtd->writesize == 512)
 281                 chip->ecc.layout = &rb500_nand_ecclayout;
 282
 283         return 0;
 284 }
 285
 286 static void __init rb500_nand_setup(void)
 287 {
 288         switch (mips_machtype) {
 289         case MACH_MIKROTIK_RB532A:
 290                 changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
 291                 break;
 292         default:
 293                 changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
 294                 break;
 295         }
 296
 297         /* Setup NAND specific settings */
 298         rb500_nand_data.chip.nr_chips = 1;
 299         rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
 300         rb500_nand_data.chip.partitions = rb500_partition_info;
 301         rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
 302         rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
 303
 304         rb500_nand_data.chip.chip_fixup = &rb500_nand_fixup;
 305 }
 306
 307
 308 static int __init plat_setup_devices(void)
 309 {
 310         /* Look for the CF card reader */
 311         if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 312                 rb500_devs[1] = NULL;
 313         else {
 314                 cf_slot0_res[0].start =
 315                     readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 316                 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 317         }
 318
 319         /* Read the NAND resources from the device controller */
 320         nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
 321         nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 322
 323         /* Initialise the NAND device */
 324         rb500_nand_setup();
 325
 326         return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 327 }
 328
 329 static int __init setup_kmac(char *s)
 330 {
 331         printk("korina mac = %s\n", s);
 332         parse_mac_addr(s);
 333         return 0;
 334 }
 335
 336 __setup("kmac=", setup_kmac);
 337
 338 arch_initcall(plat_setup_devices);