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lua: Fixed some cross-platform issues for PPC (and probably other architectures)
[openwrt.git] / target / linux / rdc / files / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.19"
54 #define DRV_RELDATE "16Jun2008"
55
56 /* define bits of a debug mask */
57 #define DBG_PHY 0x00000001 /*!< show PHY read/write */
58 #define DBG_FREE_BUFS 0x00000002 /*!< show calls to r6040_free_*bufs */
59 #define DBG_RING 0x00000004 /*!< debug init./freeing of descr rings */
60 #define DBG_RX_BUF 0x00000008 /*!< show alloc. of new rx buf (in IRQ context !) */
61 #define DBG_TX_BUF 0x00000010 /*!< show arrival of new tx buf */
62 #define DBG_TX_DONE 0x00000020 /*!< debug TX done */
63 #define DBG_RX_DESCR 0x00000040 /*!< debug rx descr to be processed */
64 #define DBG_RX_DATA 0x00000080 /*!< show some user data of incoming packet */
65 #define DBG_EXIT 0x00000100 /*!< show exit code calls */
66 #define DBG_INIT 0x00000200 /*!< show init. code calls */
67 #define DBG_TX_RING_DUMP 0x00000400 /*!< dump the tx ring after creation */
68 #define DBG_RX_RING_DUMP 0x00000800 /*!< dump the rx ring after creation */
69 #define DBG_TX_DESCR 0x00001000 /*!< dump the setting of a descr for tx */
70 #define DBG_TX_DATA 0x00002000 /*!< dump some tx data */
71 #define DBG_IRQ 0x00004000 /*!< print inside the irq handler */
72 #define DBG_POLL 0x00008000 /*!< dump info on poll procedure */
73 #define DBG_MAC_ADDR 0x00010000 /*!< debug mac address setting */
74 #define DBG_OPEN 0x00020000 /*!< debug open proc. */
75
76 static int debug = 0;
77 module_param(debug, int, 0);
78 MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
79
80 /* define which debugs are left in the code during compilation */
81 #define DEBUG (-1) /* all debugs */
82
83 #define dbg(l, f, ...) \
84 do { \
85 if ((DEBUG & l) && (debug & l)) { \
86 printk(KERN_INFO DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__); \
87 } \
88 } while (0)
89
90 #define err(f, ...) printk(KERN_WARNING DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__)
91
92 /* PHY CHIP Address */
93 #define PHY1_ADDR 1 /* For MAC1 */
94 #define PHY2_ADDR 2 /* For MAC2 */
95 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
96 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
97
98 /* Time in jiffies before concluding the transmitter is hung. */
99 #define TX_TIMEOUT (6000 * HZ / 1000)
100
101 /* RDC MAC I/O Size */
102 #define R6040_IO_SIZE 256
103
104 /* MAX RDC MAC */
105 #define MAX_MAC 2
106
107 /* MAC registers */
108 #define MCR0 0x00 /* Control register 0 */
109 #define MCR1 0x04 /* Control register 1 */
110 #define MAC_RST 0x0001 /* Reset the MAC */
111 #define MBCR 0x08 /* Bus control */
112 #define MT_ICR 0x0C /* TX interrupt control */
113 #define MR_ICR 0x10 /* RX interrupt control */
114 #define MTPR 0x14 /* TX poll command register */
115 #define MR_BSR 0x18 /* RX buffer size */
116 #define MR_DCR 0x1A /* RX descriptor control */
117 #define MLSR 0x1C /* Last status */
118 #define MMDIO 0x20 /* MDIO control register */
119 #define MDIO_WRITE 0x4000 /* MDIO write */
120 #define MDIO_READ 0x2000 /* MDIO read */
121 #define MMRD 0x24 /* MDIO read data register */
122 #define MMWD 0x28 /* MDIO write data register */
123 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
124 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
125 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
126 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
127 #define MISR 0x3C /* Status register */
128 #define MIER 0x40 /* INT enable register */
129 #define MSK_INT 0x0000 /* Mask off interrupts */
130 #define RX_FINISH 0x0001 /* rx finished irq */
131 #define RX_NO_DESC 0x0002 /* rx no descr. avail. irq */
132 #define RX_FIFO_FULL 0x0004 /* rx fifo full irq */
133 #define RX_EARLY 0x0008 /* rx early irq */
134 #define TX_FINISH 0x0010 /* tx finished irq */
135 #define TX_EARLY 0x0080 /* tx early irq */
136 #define EVENT_OVRFL 0x0100 /* event counter overflow irq */
137 #define LINK_CHANGED 0x0200 /* PHY link changed irq */
138
139 #define ME_CISR 0x44 /* Event counter INT status */
140 #define ME_CIER 0x48 /* Event counter INT enable */
141 #define MR_CNT 0x50 /* Successfully received packet counter */
142 #define ME_CNT0 0x52 /* Event counter 0 */
143 #define ME_CNT1 0x54 /* Event counter 1 */
144 #define ME_CNT2 0x56 /* Event counter 2 */
145 #define ME_CNT3 0x58 /* Event counter 3 */
146 #define MT_CNT 0x5A /* Successfully transmit packet counter */
147 #define ME_CNT4 0x5C /* Event counter 4 */
148 #define MP_CNT 0x5E /* Pause frame counter register */
149 #define MAR0 0x60 /* Hash table 0 */
150 #define MAR1 0x62 /* Hash table 1 */
151 #define MAR2 0x64 /* Hash table 2 */
152 #define MAR3 0x66 /* Hash table 3 */
153 #define MID_0L 0x68 /* Multicast address MID0 Low */
154 #define MID_0M 0x6A /* Multicast address MID0 Medium */
155 #define MID_0H 0x6C /* Multicast address MID0 High */
156 #define MID_1L 0x70 /* MID1 Low */
157 #define MID_1M 0x72 /* MID1 Medium */
158 #define MID_1H 0x74 /* MID1 High */
159 #define MID_2L 0x78 /* MID2 Low */
160 #define MID_2M 0x7A /* MID2 Medium */
161 #define MID_2H 0x7C /* MID2 High */
162 #define MID_3L 0x80 /* MID3 Low */
163 #define MID_3M 0x82 /* MID3 Medium */
164 #define MID_3H 0x84 /* MID3 High */
165 #define PHY_CC 0x88 /* PHY status change configuration register */
166 #define PHY_ST 0x8A /* PHY status register */
167 #define MAC_SM 0xAC /* MAC status machine */
168 #define MAC_ID 0xBE /* Identifier register */
169
170 #define TX_DCNT 0x80 /* TX descriptor count */
171 #define RX_DCNT 0x80 /* RX descriptor count */
172 #define MAX_BUF_SIZE 0x600
173 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
174 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
175 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register:
176 - wait 1 host clock until SDRAM bus request
177 becomes high priority
178 - RX FIFO: 32 byte
179 - TX FIFO: 64 byte
180 - FIFO transfer length: 16 byte */
181 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
182
183 /* PHY settings */
184 #define ICPLUS_PHY_ID 0x0243
185
186 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
187 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
188 "Florian Fainelli <florian@openwrt.org>");
189 MODULE_LICENSE("GPL");
190 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
191
192 /*! which rx interrupts do we allow */
193 #define RX_INTS (RX_FIFO_FULL|RX_NO_DESC|RX_FINISH)
194 /*! which tx interrupts do we allow */
195 #define TX_INTS (TX_FINISH)
196 #define INT_MASK (RX_INTS | TX_INTS)
197
198 struct r6040_descriptor {
199 u16 status, len; /* 0-3 */
200 __le32 buf; /* 4-7 */
201 __le32 ndesc; /* 8-B */
202 u32 rev1; /* C-F */
203 char *vbufp; /* 10-13 */
204 struct r6040_descriptor *vndescp; /* 14-17 */
205 struct sk_buff *skb_ptr; /* 18-1B */
206 u32 rev2; /* 1C-1F */
207 } __attribute__((aligned(32)));
208
209 /*! defines for the status field in the r6040_descriptor */
210 #define DESC_STATUS_OWNER_MAC (1<<15) /*!< if set the MAC is the owner of this descriptor */
211 #define DESC_STATUS_RX_OK (1<<14) /*!< rx was successful */
212 #define DESC_STATUS_RX_ERR (1<<11) /*!< rx PHY error */
213 #define DESC_STATUS_RX_ERR_DRIBBLE (1<<10) /*!< rx dribble packet */
214 #define DESC_STATUS_RX_ERR_BUFLEN (1<< 9) /*!< rx length exceeded buffer size */
215 #define DESC_STATUS_RX_ERR_LONG (1<< 8) /*!< rx length > maximum packet length */
216 #define DESC_STATUS_RX_ERR_RUNT (1<< 7) /*!< rx: packet length < 64 byte */
217 #define DESC_STATUS_RX_ERR_CRC (1<< 6) /*!< rx: crc error */
218 #define DESC_STATUS_RX_BROADCAST (1<< 5) /*!< rx: broadcast (no error) */
219 #define DESC_STATUS_RX_MULTICAST (1<< 4) /*!< rx: multicast (no error) */
220 #define DESC_STATUS_RX_MCH_HIT (1<< 3) /*!< rx: multicast hit in hash table (no error) */
221 #define DESC_STATUS_RX_MIDH_HIT (1<< 2) /*!< rx: MID table hit (no error) */
222 #define DESC_STATUS_RX_IDX_MID_MASK 3 /*!< rx: mask for the index of matched MIDx */
223
224 struct r6040_private {
225 spinlock_t lock; /* driver lock */
226 struct timer_list timer;
227 struct pci_dev *pdev;
228 struct r6040_descriptor *rx_insert_ptr;
229 struct r6040_descriptor *rx_remove_ptr;
230 struct r6040_descriptor *tx_insert_ptr;
231 struct r6040_descriptor *tx_remove_ptr;
232 struct r6040_descriptor *rx_ring;
233 struct r6040_descriptor *tx_ring;
234 dma_addr_t rx_ring_dma;
235 dma_addr_t tx_ring_dma;
236 u16 tx_free_desc, phy_addr, phy_mode;
237 u16 mcr0, mcr1;
238 u16 switch_sig;
239 struct net_device *dev;
240 struct mii_if_info mii_if;
241 struct napi_struct napi;
242 void __iomem *base;
243 };
244
245 struct net_device *parent_dev;
246 static char *parent;
247 module_param(parent, charp, 0444);
248 MODULE_PARM_DESC(parent, "Parent network device name to get the MAC address from");
249
250 static char version[] __devinitdata = KERN_INFO DRV_NAME
251 ": RDC R6040 NAPI net driver,"
252 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
253
254 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
255
256 /* forward declarations */
257 void r6040_multicast_list(struct net_device *dev);
258
259 /* jal2: comment out to get more symbols for debugging */
260 //#define STATIC static
261 #define STATIC
262
263 #if DEBUG
264 /*! hexdump an memory area into a string. delim is taken as the delimiter between two bytes.
265 It is omitted if delim == '\0' */
266 STATIC char *hex2str(void *addr, char *buf, int nr_bytes, int delim)
267 {
268 unsigned char *src = addr;
269 char *outb = buf;
270
271 #define BIN2HEXDIGIT(x) ((x) < 10 ? '0'+(x) : 'A'-10+(x))
272
273 while (nr_bytes > 0) {
274 *outb++ = BIN2HEXDIGIT(*src>>4);
275 *outb++ = BIN2HEXDIGIT(*src&0xf);
276 if (delim)
277 *outb++ = delim;
278 nr_bytes--;
279 src++;
280 }
281
282 if (delim)
283 outb--;
284 *outb = '\0';
285 return buf;
286 }
287
288 #endif /* #if DEBUG */
289
290 /* Read a word data from PHY Chip */
291 STATIC int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
292 {
293 int limit = 2048;
294 u16 cmd;
295 int rc;
296
297 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
298 /* Wait for the read bit to be cleared */
299 while (limit--) {
300 cmd = ioread16(ioaddr + MMDIO);
301 if (cmd & MDIO_READ)
302 break;
303 }
304
305 if (limit <= 0)
306 err("phy addr x%x reg x%x timed out\n",
307 phy_addr, reg);
308
309 rc=ioread16(ioaddr + MMRD);
310
311 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, rc);
312 return rc;
313 }
314
315 /* Write a word data from PHY Chip */
316 STATIC void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
317 {
318 int limit = 2048;
319 u16 cmd;
320
321 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, val);
322
323 iowrite16(val, ioaddr + MMWD);
324 /* Write the command to the MDIO bus */
325 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
326 /* Wait for the write bit to be cleared */
327 while (limit--) {
328 cmd = ioread16(ioaddr + MMDIO);
329 if (cmd & MDIO_WRITE)
330 break;
331 }
332 if (limit <= 0)
333 err("phy addr x%x reg x%x val x%x timed out\n",
334 phy_addr, reg, val);
335 }
336
337 STATIC int mdio_read(struct net_device *dev, int mii_id, int reg)
338 {
339 struct r6040_private *lp = netdev_priv(dev);
340 void __iomem *ioaddr = lp->base;
341
342 return (phy_read(ioaddr, lp->phy_addr, reg));
343 }
344
345 STATIC void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
346 {
347 struct r6040_private *lp = netdev_priv(dev);
348 void __iomem *ioaddr = lp->base;
349
350 phy_write(ioaddr, lp->phy_addr, reg, val);
351 }
352
353 void r6040_free_txbufs(struct net_device *dev)
354 {
355 struct r6040_private *lp = netdev_priv(dev);
356 int i;
357
358 dbg(DBG_FREE_BUFS, "ENTER\n");
359 for (i = 0; i < TX_DCNT; i++) {
360 if (lp->tx_insert_ptr->skb_ptr) {
361 pci_unmap_single(lp->pdev,
362 le32_to_cpu(lp->tx_insert_ptr->buf),
363 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
364 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
365 lp->rx_insert_ptr->skb_ptr = NULL;
366 }
367 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
368 }
369 dbg(DBG_FREE_BUFS, "EXIT\n");
370 }
371
372 /*! unmap and free all rx skb */
373 void r6040_free_rxbufs(struct net_device *dev)
374 {
375 struct r6040_private *lp = netdev_priv(dev);
376 int i;
377
378 dbg(DBG_FREE_BUFS, "ENTER\n");
379 for (i = 0; i < RX_DCNT; i++) {
380 if (lp->rx_insert_ptr->skb_ptr) {
381 pci_unmap_single(lp->pdev,
382 le32_to_cpu(lp->rx_insert_ptr->buf),
383 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
384 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
385 lp->rx_insert_ptr->skb_ptr = NULL;
386 }
387 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
388 }
389 dbg(DBG_FREE_BUFS, "EXIT\n");
390
391 }
392
393 void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
394 dma_addr_t desc_dma, int size)
395 {
396 struct r6040_descriptor *desc = desc_ring;
397 dma_addr_t mapping = desc_dma;
398
399 dbg(DBG_RING, "desc_ring %p desc_dma %08x size x%x\n",
400 desc_ring, desc_dma, size);
401
402
403 while (size-- > 0) {
404 mapping += sizeof(*desc);
405 memset(desc, 0, sizeof(*desc));
406 desc->ndesc = cpu_to_le32(mapping);
407 desc->vndescp = desc + 1;
408 desc++;
409 }
410
411 /* last descriptor points to first one to close the descriptor ring */
412 desc--;
413 desc->ndesc = cpu_to_le32(desc_dma);
414 desc->vndescp = desc_ring;
415 }
416
417 #if (DEBUG & DBG_TX_RING_DUMP)
418 /*! dump the tx ring to syslog */
419 STATIC void
420 dump_tx_ring(struct r6040_private *lp)
421 {
422 int i;
423 struct r6040_descriptor *ptr;
424
425 printk(KERN_INFO "%s: nr_desc x%x tx_ring %p tx_ring_dma %08x "
426 "tx_insert %p tx_remove %p\n",
427 DRV_NAME, TX_DCNT, lp->tx_ring, lp->tx_ring_dma,
428 lp->tx_insert_ptr, lp->tx_remove_ptr);
429
430 if (lp->tx_ring) {
431 for(i=0, ptr=lp->tx_ring; i < TX_DCNT; i++, ptr++) {
432 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
433 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
434 DRV_NAME, i, ptr->status, ptr->len,
435 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
436 }
437 }
438 }
439 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
440
441 void r6040_init_txbufs(struct net_device *dev)
442 {
443 struct r6040_private *lp = netdev_priv(dev);
444
445 lp->tx_free_desc = TX_DCNT;
446
447 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
448 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
449
450 #if (DEBUG & DBG_TX_RING_DUMP)
451 if (debug & DBG_TX_RING_DUMP) {
452 dump_tx_ring(lp);
453 }
454 #endif
455 }
456
457 #if (DEBUG & DBG_RX_RING_DUMP)
458 /*! dump the rx ring to syslog */
459 STATIC void
460 dump_rx_ring(struct r6040_private *lp)
461 {
462 int i;
463 struct r6040_descriptor *ptr;
464
465 printk(KERN_INFO "%s: nr_desc x%x rx_ring %p rx_ring_dma %08x "
466 "rx_insert %p rx_remove %p\n",
467 DRV_NAME, RX_DCNT, lp->rx_ring, lp->rx_ring_dma,
468 lp->rx_insert_ptr, lp->rx_remove_ptr);
469
470 if (lp->rx_ring) {
471 for(i=0, ptr=lp->rx_ring; i < RX_DCNT; i++, ptr++) {
472 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
473 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
474 DRV_NAME, i, ptr->status, ptr->len,
475 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
476 }
477 }
478 }
479 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
480
481 int r6040_alloc_rxbufs(struct net_device *dev)
482 {
483 struct r6040_private *lp = netdev_priv(dev);
484 struct r6040_descriptor *desc;
485 struct sk_buff *skb;
486 int rc;
487
488 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
489 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
490
491 /* alloc skbs for the rx descriptors */
492 desc = lp->rx_ring;
493 do {
494 if (!(skb=netdev_alloc_skb(dev, MAX_BUF_SIZE))) {
495 err("failed to alloc skb for rx\n");
496 rc = -ENOMEM;
497 goto err_exit;
498 }
499 desc->skb_ptr = skb;
500 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
501 desc->skb_ptr->data,
502 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
503 desc->status = DESC_STATUS_OWNER_MAC;
504 desc = desc->vndescp;
505 } while (desc != lp->rx_ring);
506
507 #if (DEBUG & DBG_RX_RING_DUMP)
508 if (debug & DBG_RX_RING_DUMP) {
509 dump_rx_ring(lp);
510 }
511 #endif
512
513 return 0;
514
515 err_exit:
516 /* dealloc all previously allocated skb */
517 r6040_free_rxbufs(dev);
518 return rc;
519 }
520
521 /*! reset MAC and set all registers */
522 void r6040_init_mac_regs(struct r6040_private *lp)
523 {
524 void __iomem *ioaddr = lp->base;
525 int limit;
526 char obuf[3*ETH_ALEN] __attribute__ ((unused));
527
528 /* Mask Off Interrupt */
529 iowrite16(MSK_INT, ioaddr + MIER);
530
531 /* reset MAC */
532 iowrite16(MAC_RST, ioaddr + MCR1);
533 udelay(100);
534 limit=2048;
535 while ((ioread16(ioaddr + MCR1) & MAC_RST) && limit-- > 0);
536
537 /* Reset internal state machine */
538 iowrite16(2, ioaddr + MAC_SM);
539 iowrite16(0, ioaddr + MAC_SM);
540 udelay(5000);
541
542 /* Restore MAC Addresses */
543 r6040_multicast_list(lp->dev);
544
545 /* TODO: restore multcast and hash table */
546
547 /* MAC Bus Control Register */
548 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
549
550 /* Buffer Size Register */
551 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
552
553 /* write tx ring start address */
554 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
555 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
556
557 /* write rx ring start address */
558 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
559 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
560
561 /* set interrupt waiting time and packet numbers */
562 iowrite16(0, ioaddr + MT_ICR);
563 iowrite16(0, ioaddr + MR_ICR);
564
565 /* enable interrupts */
566 iowrite16(INT_MASK, ioaddr + MIER);
567
568 /* enable tx and rx */
569 iowrite16(lp->mcr0 | 0x0002, ioaddr);
570
571 /* let TX poll the descriptors - we may got called by r6040_tx_timeout which has left
572 some unsent tx buffers */
573 iowrite16(0x01, ioaddr + MTPR);
574 }
575
576 void r6040_tx_timeout(struct net_device *dev)
577 {
578 struct r6040_private *priv = netdev_priv(dev);
579 void __iomem *ioaddr = priv->base;
580
581 /* we read MISR, which clears on read (i.e. we may loose an RX interupt,
582 but this is an error anyhow ... */
583 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
584 "status %4.4x, PHY status %4.4x\n",
585 dev->name, ioread16(ioaddr + MIER),
586 ioread16(ioaddr + MISR),
587 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
588
589 dev->stats.tx_errors++;
590
591 /* Reset MAC and re-init all registers */
592 r6040_init_mac_regs(priv);
593 }
594
595 struct net_device_stats *r6040_get_stats(struct net_device *dev)
596 {
597 struct r6040_private *priv = netdev_priv(dev);
598 void __iomem *ioaddr = priv->base;
599 unsigned long flags;
600
601 spin_lock_irqsave(&priv->lock, flags);
602 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
603 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
604 spin_unlock_irqrestore(&priv->lock, flags);
605
606 return &dev->stats;
607 }
608
609 /* Stop RDC MAC and Free the allocated resource */
610 void r6040_down(struct net_device *dev)
611 {
612 struct r6040_private *lp = netdev_priv(dev);
613 void __iomem *ioaddr = lp->base;
614 struct pci_dev *pdev = lp->pdev;
615 int limit = 2048;
616
617 dbg(DBG_EXIT, "ENTER\n");
618
619 /* Stop MAC */
620 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
621 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
622 udelay(100);
623 while ((ioread16(ioaddr+MCR1) & 1) && limit-- > 0);
624
625 if (limit <= 0)
626 err("timeout while waiting for reset done.\n");
627
628 free_irq(dev->irq, dev);
629
630 /* Free RX buffer */
631 r6040_free_rxbufs(dev);
632
633 /* Free TX buffer */
634 r6040_free_txbufs(dev);
635
636 /* Free Descriptor memory */
637 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
638 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
639
640 dbg(DBG_EXIT, "EXIT\n");
641 }
642
643 int r6040_close(struct net_device *dev)
644 {
645 struct r6040_private *lp = netdev_priv(dev);
646
647 dbg(DBG_EXIT, "ENTER\n");
648
649 /* deleted timer */
650 del_timer_sync(&lp->timer);
651 spin_lock_irq(&lp->lock);
652 napi_disable(&lp->napi);
653 netif_stop_queue(dev);
654 r6040_down(dev);
655 spin_unlock_irq(&lp->lock);
656
657 dbg(DBG_EXIT, "EXIT\n");
658 return 0;
659 }
660
661 /* Status of PHY CHIP. Returns 0x8000 for full duplex, 0 for half duplex */
662 STATIC int phy_mode_chk(struct net_device *dev)
663 {
664 struct r6040_private *lp = netdev_priv(dev);
665 void __iomem *ioaddr = lp->base;
666 int phy_dat;
667
668 /* PHY Link Status Check */
669 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
670 if (!(phy_dat & 0x4))
671 phy_dat = 0x8000; /* Link Failed, full duplex */
672
673 /* PHY Chip Auto-Negotiation Status */
674 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
675 if (phy_dat & 0x0020) {
676 /* Auto Negotiation Mode */
677 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
678 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
679 if (phy_dat & 0x140)
680 /* Force full duplex */
681 phy_dat = 0x8000;
682 else
683 phy_dat = 0;
684 } else {
685 /* Force Mode */
686 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
687 if (phy_dat & 0x100)
688 phy_dat = 0x8000;
689 else
690 phy_dat = 0x0000;
691 }
692
693 dbg(DBG_PHY, "RETURN x%x\n", phy_dat);
694 return phy_dat;
695 };
696
697 void r6040_set_carrier(struct mii_if_info *mii)
698 {
699 if (phy_mode_chk(mii->dev)) {
700 /* autoneg is off: Link is always assumed to be up */
701 if (!netif_carrier_ok(mii->dev))
702 netif_carrier_on(mii->dev);
703 } else
704 phy_mode_chk(mii->dev);
705 }
706
707 int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
708 {
709 struct r6040_private *lp = netdev_priv(dev);
710 struct mii_ioctl_data *data = if_mii(rq);
711 int rc;
712
713 if (!netif_running(dev))
714 return -EINVAL;
715 spin_lock_irq(&lp->lock);
716 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
717 spin_unlock_irq(&lp->lock);
718 r6040_set_carrier(&lp->mii_if);
719 return rc;
720 }
721
722 int r6040_rx(struct net_device *dev, int limit)
723 {
724 struct r6040_private *priv = netdev_priv(dev);
725 int count=0;
726 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
727 struct sk_buff *skb_ptr, *new_skb;
728 char obuf[2*32+1] __attribute__ ((unused)); /* for debugging */
729
730 while (count < limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) {
731 /* limit not reached and the descriptor belongs to the CPU */
732
733 dbg(DBG_RX_DESCR, "descptr %p status x%x data len x%x\n",
734 descptr, descptr->status, descptr->len);
735
736 /* Check for errors */
737 if (descptr->status & DESC_STATUS_RX_ERR) {
738
739 dev->stats.rx_errors++;
740
741 if (descptr->status & (DESC_STATUS_RX_ERR_DRIBBLE|
742 DESC_STATUS_RX_ERR_BUFLEN|
743 DESC_STATUS_RX_ERR_LONG|
744 DESC_STATUS_RX_ERR_RUNT)) {
745 /* packet too long or too short*/
746 dev->stats.rx_length_errors++;
747 }
748
749 if (descptr->status & DESC_STATUS_RX_ERR_CRC) {
750 dev->stats.rx_crc_errors++;
751 }
752 goto next_descr;
753 }
754
755 /* successful received packet */
756
757 /* first try to allocate new skb. If this fails
758 we drop the packet and leave the old skb there.*/
759 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
760 if (!new_skb) {
761 dev->stats.rx_dropped++;
762 goto next_descr;
763 }
764 skb_ptr = descptr->skb_ptr;
765 skb_ptr->dev = priv->dev;
766 /* Do not count the CRC */
767 skb_put(skb_ptr, descptr->len - 4);
768 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
769 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
770 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
771
772 dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
773 descptr->len,
774 hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
775
776 /* Send to upper layer */
777 netif_receive_skb(skb_ptr);
778 dev->last_rx = jiffies;
779 dev->stats.rx_packets++;
780 dev->stats.rx_bytes += (descptr->len-4);
781
782 /* put new skb into descriptor */
783 descptr->skb_ptr = new_skb;
784 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
785 descptr->skb_ptr->data,
786 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
787
788 next_descr:
789 /* put the descriptor back to the MAC */
790 descptr->status = DESC_STATUS_OWNER_MAC;
791 descptr = descptr->vndescp;
792 count++; /* shall we count errors and dropped packets as well? */
793 } /* while (limit && !(descptr->status & DESC_STATUS_OWNER_MAC)) */
794
795 /* remember next descriptor to check for rx */
796 priv->rx_remove_ptr = descptr;
797
798 return count;
799 }
800
801 void r6040_tx(struct net_device *dev)
802 {
803 struct r6040_private *priv = netdev_priv(dev);
804 struct r6040_descriptor *descptr;
805 void __iomem *ioaddr = priv->base;
806 struct sk_buff *skb_ptr;
807 u16 err;
808
809 spin_lock(&priv->lock);
810 descptr = priv->tx_remove_ptr;
811 while (priv->tx_free_desc < TX_DCNT) {
812 /* Check for errors */
813 err = ioread16(ioaddr + MLSR);
814
815 if (err & 0x0200)
816 dev->stats.rx_fifo_errors++;
817 if (err & (0x2000 | 0x4000))
818 dev->stats.tx_carrier_errors++;
819
820 dbg(DBG_TX_DONE, "descptr %p status x%x err x%x jiffies %lu\n",
821 descptr, descptr->status, err, jiffies);
822
823 if (descptr->status & 0x8000)
824 break; /* Not complete */
825 skb_ptr = descptr->skb_ptr;
826 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
827 skb_ptr->len, PCI_DMA_TODEVICE);
828 /* Free buffer */
829 dev_kfree_skb_irq(skb_ptr);
830 descptr->skb_ptr = NULL;
831 /* To next descriptor */
832 descptr = descptr->vndescp;
833 priv->tx_free_desc++;
834 }
835 priv->tx_remove_ptr = descptr;
836
837 if (priv->tx_free_desc)
838 netif_wake_queue(dev);
839 spin_unlock(&priv->lock);
840 }
841
842 int r6040_poll(struct napi_struct *napi, int budget)
843 {
844 struct r6040_private *priv =
845 container_of(napi, struct r6040_private, napi);
846 struct net_device *dev = priv->dev;
847 void __iomem *ioaddr = priv->base;
848 int work_done;
849
850 work_done = r6040_rx(dev, budget);
851
852 dbg(DBG_POLL, "budget x%x done x%x\n", budget, work_done);
853
854 if (work_done < budget) {
855 netif_rx_complete(dev, napi);
856 /* Enable RX interrupt */
857 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
858 }
859 return work_done;
860 }
861
862 /* The RDC interrupt handler. */
863 irqreturn_t r6040_interrupt(int irq, void *dev_id)
864 {
865 struct net_device *dev = dev_id;
866 struct r6040_private *lp = netdev_priv(dev);
867 void __iomem *ioaddr = lp->base;
868 u16 status;
869
870 /* Read MISR status and clear */
871 status = ioread16(ioaddr + MISR);
872
873 dbg(DBG_IRQ, "status x%x jiffies %lu\n", status, jiffies);
874
875 if (status == 0x0000 || status == 0xffff)
876 return IRQ_NONE;
877
878 /* rx early / rx finish interrupt
879 or rx descriptor unavail. */
880 if (status & RX_INTS) {
881 if (status & RX_NO_DESC) {
882 /* rx descriptor unavail. */
883 dev->stats.rx_dropped++;
884 dev->stats.rx_missed_errors++;
885 }
886 /* Mask off RX interrupts */
887 iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
888 netif_rx_schedule(dev, &lp->napi);
889 }
890
891 /* rx FIFO full */
892 if (status & RX_FIFO_FULL) {
893 dev->stats.rx_fifo_errors++;
894 }
895
896 /* TX interrupt request */
897 if (status & 0x10)
898 r6040_tx(dev);
899
900 return IRQ_HANDLED;
901 }
902
903 #ifdef CONFIG_NET_POLL_CONTROLLER
904 void r6040_poll_controller(struct net_device *dev)
905 {
906 disable_irq(dev->irq);
907 r6040_interrupt(dev->irq, dev);
908 enable_irq(dev->irq);
909 }
910 #endif
911
912 /* Init RDC MAC */
913 int r6040_up(struct net_device *dev)
914 {
915 struct r6040_private *lp = netdev_priv(dev);
916 void __iomem *ioaddr = lp->base;
917 int rc;
918
919 dbg(DBG_INIT, "ENTER\n");
920
921 /* Initialise and alloc RX/TX buffers */
922 r6040_init_txbufs(dev);
923 if ((rc=r6040_alloc_rxbufs(dev)))
924 return rc;
925
926 /* Read the PHY ID */
927 lp->switch_sig = phy_read(ioaddr, 0, 2);
928
929 if (lp->switch_sig == ICPLUS_PHY_ID) {
930 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
931 lp->phy_mode = 0x8000;
932 } else {
933 /* PHY Mode Check */
934 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
935 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
936
937 if (PHY_MODE == 0x3100)
938 lp->phy_mode = phy_mode_chk(dev);
939 else
940 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
941 }
942
943 /* configure duplex mode */
944 lp->mcr0 |= lp->phy_mode;
945
946 /* improve performance (by RDC guys) */
947 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
948 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
949 phy_write(ioaddr, 0, 19, 0x0000);
950 phy_write(ioaddr, 0, 30, 0x01F0);
951
952 /* Reset MAC and init all registers */
953 r6040_init_mac_regs(lp);
954
955 return 0;
956 }
957
958 /*
959 A periodic timer routine
960 Polling PHY Chip Link Status
961 */
962 void r6040_timer(unsigned long data)
963 {
964 struct net_device *dev = (struct net_device *)data;
965 struct r6040_private *lp = netdev_priv(dev);
966 void __iomem *ioaddr = lp->base;
967 u16 phy_mode;
968
969 /* Polling PHY Chip Status */
970 if (PHY_MODE == 0x3100)
971 phy_mode = phy_mode_chk(dev);
972 else
973 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
974
975 if (phy_mode != lp->phy_mode) {
976 lp->phy_mode = phy_mode;
977 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
978 iowrite16(lp->mcr0, ioaddr);
979 printk(KERN_INFO "Link Change x%x \n", ioread16(ioaddr));
980 }
981
982 /* Timer active again */
983 mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
984 }
985
986 int r6040_open(struct net_device *dev)
987 {
988 struct r6040_private *lp = netdev_priv(dev);
989 int ret;
990
991 dbg(DBG_OPEN, "ENTER\n");
992 /* Request IRQ and Register interrupt handler */
993 ret = request_irq(dev->irq, &r6040_interrupt,
994 IRQF_SHARED, dev->name, dev);
995 if (ret)
996 return ret;
997
998 dbg(DBG_OPEN, "got irq %d\n", dev->irq);
999
1000 /* Allocate Descriptor memory */
1001 lp->rx_ring =
1002 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
1003 if (!lp->rx_ring)
1004 return -ENOMEM;
1005
1006 dbg(DBG_OPEN, "allocated rx ring\n");
1007
1008 lp->tx_ring =
1009 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
1010 if (!lp->tx_ring) {
1011 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
1012 lp->rx_ring_dma);
1013 return -ENOMEM;
1014 }
1015
1016 dbg(DBG_OPEN, "allocated tx ring\n");
1017
1018 if ((ret=r6040_up(dev))) {
1019 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
1020 lp->tx_ring_dma);
1021 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
1022 lp->rx_ring_dma);
1023 return ret;
1024 }
1025
1026 napi_enable(&lp->napi);
1027 netif_start_queue(dev);
1028
1029 /* set and active a timer process */
1030 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
1031 if (lp->switch_sig != ICPLUS_PHY_ID)
1032 mod_timer(&lp->timer, jiffies + HZ);
1033 return 0;
1034 }
1035
1036 int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
1037 {
1038 struct r6040_private *lp = netdev_priv(dev);
1039 struct r6040_descriptor *descptr;
1040 void __iomem *ioaddr = lp->base;
1041 unsigned long flags;
1042 int ret = NETDEV_TX_OK;
1043
1044 /* Critical Section */
1045 spin_lock_irqsave(&lp->lock, flags);
1046
1047 /* TX resource check */
1048 if (!lp->tx_free_desc) {
1049 spin_unlock_irqrestore(&lp->lock, flags);
1050 netif_stop_queue(dev);
1051 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
1052 ret = NETDEV_TX_BUSY;
1053 return ret;
1054 }
1055
1056 /* Statistic Counter */
1057 dev->stats.tx_packets++;
1058 dev->stats.tx_bytes += skb->len;
1059 /* Set TX descriptor & Transmit it */
1060 lp->tx_free_desc--;
1061 descptr = lp->tx_insert_ptr;
1062 if (skb->len < MISR)
1063 descptr->len = MISR;
1064 else
1065 descptr->len = skb->len;
1066
1067 descptr->skb_ptr = skb;
1068 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
1069 skb->data, skb->len, PCI_DMA_TODEVICE));
1070
1071 dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x jiffies %lu\n",
1072 descptr, descptr->len, descptr->buf, skb->data, skb->len, jiffies);
1073
1074 {
1075 char obuf[2*32+1];
1076 dbg(DBG_TX_DATA, "tx len x%x: %s\n",
1077 descptr->len, hex2str(skb->data, obuf, sizeof(obuf)/2, '\0'));
1078 }
1079
1080 descptr->status = 0x8000;
1081 /* Trigger the MAC to check the TX descriptor */
1082 iowrite16(0x01, ioaddr + MTPR);
1083 lp->tx_insert_ptr = descptr->vndescp;
1084
1085 /* If no tx resource, stop */
1086 if (!lp->tx_free_desc)
1087 netif_stop_queue(dev);
1088
1089 dev->trans_start = jiffies;
1090 spin_unlock_irqrestore(&lp->lock, flags);
1091 return ret;
1092 }
1093
1094 /*! set MAC addresses and promiscous mode */
1095 void r6040_multicast_list(struct net_device *dev)
1096 {
1097 struct r6040_private *lp = netdev_priv(dev);
1098 void __iomem *ioaddr = lp->base;
1099 u16 *adrp;
1100 u16 reg;
1101 unsigned long flags;
1102 struct dev_mc_list *dmi = dev->mc_list;
1103 int i;
1104 char obuf[3*ETH_ALEN] __attribute__ ((unused));
1105
1106 /* MAC Address */
1107 adrp = (u16 *)dev->dev_addr;
1108 iowrite16(adrp[0], ioaddr + MID_0L);
1109 iowrite16(adrp[1], ioaddr + MID_0M);
1110 iowrite16(adrp[2], ioaddr + MID_0H);
1111
1112 dbg(DBG_MAC_ADDR, "%s: set MAC addr %s\n",
1113 dev->name, hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
1114
1115 /* Promiscous Mode */
1116 spin_lock_irqsave(&lp->lock, flags);
1117
1118 /* Clear AMCP & PROM bits */
1119 reg = ioread16(ioaddr) & ~0x0120;
1120 if (dev->flags & IFF_PROMISC) {
1121 reg |= 0x0020;
1122 lp->mcr0 |= 0x0020;
1123 }
1124 /* Too many multicast addresses
1125 * accept all traffic */
1126 else if ((dev->mc_count > MCAST_MAX)
1127 || (dev->flags & IFF_ALLMULTI))
1128 reg |= 0x0020;
1129
1130 iowrite16(reg, ioaddr);
1131 spin_unlock_irqrestore(&lp->lock, flags);
1132
1133 /* Build the hash table */
1134 if (dev->mc_count > MCAST_MAX) {
1135 u16 hash_table[4];
1136 u32 crc;
1137
1138 for (i = 0; i < 4; i++)
1139 hash_table[i] = 0;
1140
1141 for (i = 0; i < dev->mc_count; i++) {
1142 char *addrs = dmi->dmi_addr;
1143
1144 dmi = dmi->next;
1145
1146 if (!(*addrs & 1))
1147 continue;
1148
1149 crc = ether_crc_le(6, addrs);
1150 crc >>= 26;
1151 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1152 }
1153 /* Write the index of the hash table */
1154 for (i = 0; i < 4; i++)
1155 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
1156 /* Fill the MAC hash tables with their values */
1157 iowrite16(hash_table[0], ioaddr + MAR0);
1158 iowrite16(hash_table[1], ioaddr + MAR1);
1159 iowrite16(hash_table[2], ioaddr + MAR2);
1160 iowrite16(hash_table[3], ioaddr + MAR3);
1161 }
1162 /* Multicast Address 1~4 case */
1163 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
1164 adrp = (u16 *)dmi->dmi_addr;
1165 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1166 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1167 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1168 dmi = dmi->next;
1169 }
1170 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1171 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1172 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1173 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1174 }
1175 }
1176
1177 STATIC void netdev_get_drvinfo(struct net_device *dev,
1178 struct ethtool_drvinfo *info)
1179 {
1180 struct r6040_private *rp = netdev_priv(dev);
1181
1182 strcpy(info->driver, DRV_NAME);
1183 strcpy(info->version, DRV_VERSION);
1184 strcpy(info->bus_info, pci_name(rp->pdev));
1185 }
1186
1187 STATIC int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1188 {
1189 struct r6040_private *rp = netdev_priv(dev);
1190 int rc;
1191
1192 spin_lock_irq(&rp->lock);
1193 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1194 spin_unlock_irq(&rp->lock);
1195
1196 return rc;
1197 }
1198
1199 STATIC int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1200 {
1201 struct r6040_private *rp = netdev_priv(dev);
1202 int rc;
1203
1204 spin_lock_irq(&rp->lock);
1205 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1206 spin_unlock_irq(&rp->lock);
1207 r6040_set_carrier(&rp->mii_if);
1208
1209 return rc;
1210 }
1211
1212 STATIC u32 netdev_get_link(struct net_device *dev)
1213 {
1214 struct r6040_private *rp = netdev_priv(dev);
1215
1216 return mii_link_ok(&rp->mii_if);
1217 }
1218
1219 static struct ethtool_ops netdev_ethtool_ops = {
1220 .get_drvinfo = netdev_get_drvinfo,
1221 .get_settings = netdev_get_settings,
1222 .set_settings = netdev_set_settings,
1223 .get_link = netdev_get_link,
1224 };
1225
1226 int __devinit r6040_init_one(struct pci_dev *pdev,
1227 const struct pci_device_id *ent)
1228 {
1229 struct net_device *dev;
1230 struct r6040_private *lp;
1231 void __iomem *ioaddr;
1232 int err, io_size = R6040_IO_SIZE;
1233 static int card_idx = -1;
1234 int bar = 0;
1235 long pioaddr;
1236
1237 printk(KERN_INFO "%s\n", version);
1238 printk(KERN_INFO DRV_NAME ": debug %x\n", debug);
1239
1240 err = pci_enable_device(pdev);
1241 if (err)
1242 return err;
1243
1244 /* this should always be supported */
1245 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1246 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1247 "not supported by the card\n");
1248 return -ENODEV;
1249 }
1250 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1251 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1252 "not supported by the card\n");
1253 return -ENODEV;
1254 }
1255
1256 /* IO Size check */
1257 if (pci_resource_len(pdev, 0) < io_size) {
1258 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1259 return -EIO;
1260 }
1261
1262 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1263 pci_set_master(pdev);
1264
1265 dev = alloc_etherdev(sizeof(struct r6040_private));
1266 if (!dev) {
1267 printk(KERN_ERR "Failed to allocate etherdev\n");
1268 return -ENOMEM;
1269 }
1270 SET_NETDEV_DEV(dev, &pdev->dev);
1271 lp = netdev_priv(dev);
1272
1273 if (pci_request_regions(pdev, DRV_NAME)) {
1274 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1275 err = -ENODEV;
1276 goto err_out_disable;
1277 }
1278
1279 ioaddr = pci_iomap(pdev, bar, io_size);
1280 if (!ioaddr) {
1281 printk(KERN_ERR "ioremap failed for device %s\n",
1282 pci_name(pdev));
1283 return -EIO;
1284 }
1285
1286 /* Init system & device */
1287 lp->base = ioaddr;
1288 dev->irq = pdev->irq;
1289
1290 spin_lock_init(&lp->lock);
1291 pci_set_drvdata(pdev, dev);
1292
1293 card_idx++;
1294
1295 /* Link new device into r6040_root_dev */
1296 lp->pdev = pdev;
1297
1298 lp->dev = dev;
1299
1300 /* Init RDC private data */
1301 lp->mcr0 = 0x1002;
1302 lp->phy_addr = phy_table[card_idx];
1303 lp->switch_sig = 0;
1304
1305 /* The RDC-specific entries in the device structure. */
1306 dev->open = &r6040_open;
1307 dev->hard_start_xmit = &r6040_start_xmit;
1308 dev->stop = &r6040_close;
1309 dev->get_stats = r6040_get_stats;
1310 dev->set_multicast_list = &r6040_multicast_list;
1311 dev->do_ioctl = &r6040_ioctl;
1312 dev->ethtool_ops = &netdev_ethtool_ops;
1313 dev->tx_timeout = &r6040_tx_timeout;
1314 dev->watchdog_timeo = TX_TIMEOUT;
1315
1316 {
1317 /* TODO: fix the setting of the MAC address.
1318 Right now you must either specify a netdevice with "parent=", whose
1319 address is copied or the (default) address of the Sitecom WL-153
1320 bootloader is used */
1321 static const u8 dflt_addr[ETH_ALEN] = {0,0x50,0xfc,2,3,4};
1322 if (parent_dev) {
1323 memcpy(dev->dev_addr, parent_dev->dev_addr, ETH_ALEN);
1324 } else {
1325 printk(KERN_WARNING "%s: no parent - using default mac address\n",
1326 dev->name);
1327 memcpy(dev->dev_addr, dflt_addr, ETH_ALEN);
1328 }
1329 dev->dev_addr[ETH_ALEN-1] += card_idx; /* + 0 or 1 */
1330 }
1331
1332 #ifdef CONFIG_NET_POLL_CONTROLLER
1333 dev->poll_controller = r6040_poll_controller;
1334 #endif
1335 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1336 lp->mii_if.dev = dev;
1337 lp->mii_if.mdio_read = mdio_read;
1338 lp->mii_if.mdio_write = mdio_write;
1339 lp->mii_if.phy_id = lp->phy_addr;
1340 lp->mii_if.phy_id_mask = 0x1f;
1341 lp->mii_if.reg_num_mask = 0x1f;
1342
1343 /* Register net device. After this dev->name assign */
1344 err = register_netdev(dev);
1345 if (err) {
1346 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1347 goto err_out_res;
1348 }
1349
1350 dbg(DBG_INIT, "%s successfully registered\n", dev->name);
1351 return 0;
1352
1353 err_out_res:
1354 pci_release_regions(pdev);
1355 err_out_disable:
1356 pci_disable_device(pdev);
1357 pci_set_drvdata(pdev, NULL);
1358 free_netdev(dev);
1359
1360 return err;
1361 }
1362
1363 void __devexit r6040_remove_one(struct pci_dev *pdev)
1364 {
1365 struct net_device *dev = pci_get_drvdata(pdev);
1366
1367 unregister_netdev(dev);
1368 pci_release_regions(pdev);
1369 free_netdev(dev);
1370 pci_disable_device(pdev);
1371 pci_set_drvdata(pdev, NULL);
1372 }
1373
1374
1375 static struct pci_device_id r6040_pci_tbl[] = {
1376 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1377 { 0 }
1378 };
1379 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1380
1381 static struct pci_driver r6040_driver = {
1382 .name = DRV_NAME,
1383 .id_table = r6040_pci_tbl,
1384 .probe = r6040_init_one,
1385 .remove = __devexit_p(r6040_remove_one),
1386 };
1387
1388
1389 static int __init r6040_init(void)
1390 {
1391 if (parent)
1392 parent_dev = dev_get_by_name(&init_net, parent);
1393
1394 return pci_register_driver(&r6040_driver);
1395 }
1396
1397
1398 static void __exit r6040_cleanup(void)
1399 {
1400 pci_unregister_driver(&r6040_driver);
1401 }
1402
1403 module_init(r6040_init);
1404 module_exit(r6040_cleanup);
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