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lua: Fixed some cross-platform issues for PPC (and probably other architectures)
[openwrt.git] / target / linux / storm / patches / 001-arch.patch
1 --- a/arch/arm/Kconfig
2 +++ b/arch/arm/Kconfig
3 @@ -220,6 +220,9 @@
4 help
5 This enables support for the Cirrus EP93xx series of CPUs.
6
7 +config ARCH_SL2312
8 + bool "SL2312"
9 +
10 config ARCH_FOOTBRIDGE
11 bool "FootBridge"
12 select FOOTBRIDGE
13 @@ -414,6 +417,8 @@
14
15 source "arch/arm/mach-footbridge/Kconfig"
16
17 +source "arch/arm/mach-sl2312/Kconfig"
18 +
19 source "arch/arm/mach-integrator/Kconfig"
20
21 source "arch/arm/mach-iop32x/Kconfig"
22 @@ -549,6 +554,16 @@
23 config PCI_SYSCALL
24 def_bool PCI
25
26 +config SL2312_LPC
27 + bool "LPC Host Support"
28 + depends on ARCH_SL2312
29 + help
30 +
31 +config SL2312_LPC_IT8712
32 + bool "IT8712 Support"
33 + depends on ARCH_SL2312 && SL2312_LPC
34 + help
35 +
36 # Select the host bridge type
37 config PCI_HOST_VIA82C505
38 bool
39 @@ -988,6 +1003,10 @@
40 source "drivers/mtd/Kconfig"
41 endif
42
43 +if ARCH_SL2312
44 +source "drivers/telephony/Kconfig"
45 +endif
46 +
47 source "drivers/parport/Kconfig"
48
49 source "drivers/pnp/Kconfig"
50 @@ -997,7 +1016,7 @@
51 if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \
52 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
53 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
54 - || ARCH_IXP23XX
55 + || ARCH_IXP23XX || ARCH_SL2312
56 source "drivers/ide/Kconfig"
57 endif
58
59 --- a/arch/arm/Makefile
60 +++ b/arch/arm/Makefile
61 @@ -72,6 +72,7 @@
62 tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
63 tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
64 tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
65 +tune-$(CONFIG_CPU_FA52X) :=-mtune=arm9tdmi
66 tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
67 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
68 tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
69 @@ -111,6 +112,7 @@
70 machine-$(CONFIG_ARCH_PXA) := pxa
71 machine-$(CONFIG_ARCH_L7200) := l7200
72 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
73 + machine-$(CONFIG_ARCH_SL2312) := sl2312
74 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
75 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
76 machine-$(CONFIG_ARCH_IOP32X) := iop32x
77 --- a/arch/arm/boot/compressed/Makefile
78 +++ b/arch/arm/boot/compressed/Makefile
79 @@ -19,6 +19,10 @@
80 OBJS += head-shark.o ofw-shark.o
81 endif
82
83 +ifeq ($(CONFIG_ARCH_SL2312),y)
84 +OBJS += head-sl2312.o
85 +endif
86 +
87 ifeq ($(CONFIG_ARCH_L7200),y)
88 OBJS += head-l7200.o
89 endif
90 --- /dev/null
91 +++ b/arch/arm/boot/compressed/head-sl2312.S
92 @@ -0,0 +1,6 @@
93 +#include <asm/mach-types.h>
94 +#include <asm/arch/sl2312.h>
95 +
96 + .section ".start", "ax"
97 + mov r7, #MACH_TYPE_SL2312
98 +
99 --- a/arch/arm/boot/compressed/head.S
100 +++ b/arch/arm/boot/compressed/head.S
101 @@ -57,6 +57,17 @@
102 mov \rb, #0x50000000
103 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
104 .endm
105 +/*****************************************************
106 + * for Storlink SoC
107 + *****************************************************/
108 +#elif defined(CONFIG_ARCH_SL2312)
109 + .macro loadsp, rb
110 + mov \rb, #0x16000000
111 + .endm
112 + .macro writeb, rb
113 + strb \rb, [r3, #0]
114 + .endm
115 +/****************************************************/
116 #else
117 .macro loadsp, rb
118 addruart \rb
119 @@ -116,7 +127,28 @@
120 .rept 8
121 mov r0, r0
122 .endr
123 -
124 +/*****************************************************************************
125 + * for Storlink Soc -- on chip UART
126 + *****************************************************************************/
127 +#ifndef CONFIG_SERIAL_IT8712 // Jason test
128 +@ mov r3, #0x22000000
129 + mov r3, #0x42000000
130 + mov r11, #0x80
131 + strb r11, [r3, #0xc]
132 + mov r11, #0x0
133 + strb r11, [r3, #0x4]
134 +#ifndef CONFIG_SL3516_ASIC
135 + mov r11, #0x9C /*0x9c->19200 0x4E->38400 0x34->57600 */
136 +#else
137 + mov r11, #0x9C /* 0x61 for 30MHz on GeminiA chip*/
138 +#endif
139 + strb r11, [r3, #0x0]
140 + mov r11, #0x03
141 + strb r11, [r3, #0xc]
142 + mov r11, #0xFB
143 + strb r11, [r3, #0x18]
144 +#endif
145 +/*****************************************************************************/
146 b 1f
147 .word 0x016f2818 @ Magic numbers to help the loader
148 .word start @ absolute load/run zImage address
149 @@ -458,6 +490,39 @@
150 mcr p15, 0, r0, c7, c5, 4 @ ISB
151 mov pc, r12
152
153 +/*****************************************************************************
154 + * for Storlink Soc -- CPU cache
155 + *****************************************************************************/
156 +__fa526_cache_on:
157 + mov r12, lr
158 + bl __setup_mmu
159 + mov r0, #0
160 + mcr p15, 0, r0, c7, c6, 0 @ Invalidate D cache
161 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache
162 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
163 + mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
164 + mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
165 + mov r0, #-1
166 + mcr p15, 0, r0, c3, c0, 0 @ load domain access register
167 + mrc p15, 0, r0, c1, c0, 0
168 + mov r0, r0
169 + mov r0, r0
170 +#ifndef CONFIG_CPU_DCACHE_DISABLE
171 + orr r0, r0, #0x0004 @ .... .... .... .1..
172 +#endif
173 +#ifndef CONFIG_CPU_ICACHE_DISABLE
174 + orr r0, r0, #0x1000 @ ...1 .... .... ....
175 +#endif
176 +
177 +#ifndef DEBUG
178 + orr r0, r0, #0x0039 @ Write buffer, mmu
179 +#endif
180 + mcr p15, 0, r0, c1, c0
181 + mov r0, r0
182 + mov r0, r0
183 + mov pc, r12
184 +/********************************************************************************/
185 +
186 __arm6_mmu_cache_on:
187 mov r12, lr
188 bl __setup_mmu
189 @@ -625,6 +690,16 @@
190
191 @ These match on the architecture ID
192
193 +/*****************************************************************************
194 + * for Storlink Soc -- CPU architecture ID
195 + *****************************************************************************/
196 + .word 0x66015261 @ FA526
197 + .word 0xff01fff1
198 + b __fa526_cache_on
199 + b __fa526_cache_off
200 + b __fa526_cache_flush
201 +/*****************************************************************************/
202 +
203 .word 0x00020000 @ ARMv4T
204 .word 0x000f0000
205 b __armv4_mmu_cache_on
206 @@ -712,6 +787,23 @@
207 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
208 mov pc, r12
209
210 +/*****************************************************************************
211 + * for Storlink Soc -- CPU cache
212 + *****************************************************************************/
213 +__fa526_cache_off:
214 + mrc p15, 0, r0, c1, c0
215 + bic r0, r0, #0x000d
216 + mov r1, #0
217 + mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
218 + mcr p15, 0, r1, c7, c10, 4 @ drain WB
219 + mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
220 + mov r0, #0
221 + mcr p15, 0, r0, c7, c5, 0 @ invalidate whole cache v4
222 + mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB v4
223 + mov pc, lr
224 +/*****************************************************************************/
225 +
226 +
227 __arm6_mmu_cache_off:
228 mov r0, #0x00000030 @ ARM6 control reg.
229 b __armv3_mmu_cache_off
230 @@ -759,6 +851,17 @@
231 mcr p15, 0, ip, c7, c10, 4 @ drain WB
232 mov pc, lr
233
234 +/*****************************************************************************
235 + * for Storlink Soc -- CPU cache
236 + *****************************************************************************/
237 +__fa526_cache_flush:
238 + mov r1, #0
239 + mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
240 + mcr p15, 0, r1, c7, c5, 0 @ flush I cache
241 + mcr p15, 0, r1, c7, c10, 4 @ drain WB
242 + mov pc, lr
243 +/*****************************************************************************/
244 +
245
246 __armv6_mmu_cache_flush:
247 mov r1, #0
248 --- /dev/null
249 +++ b/arch/arm/boot/compressed/it8712.h
250 @@ -0,0 +1,25 @@
251 +
252 +#ifndef __IT8712_H__
253 +#define __IT8712_H__
254 +
255 +#include "asm/arch/sl2312.h"
256 +
257 +#define IT8712_IO_BASE SL2312_LPC_IO_BASE
258 +//#define IT8712_IO_BASE 0x27000000
259 +// Device LDN
260 +#define LDN_SERIAL1 0x01
261 +#define LDN_SERIAL2 0x02
262 +#define LDN_PARALLEL 0x03
263 +#define LDN_KEYBOARD 0x05
264 +#define LDN_MOUSE 0x06
265 +#define LDN_GPIO 0x07
266 +
267 +#define IT8712_UART1_PORT 0x3F8
268 +#define IT8712_UART2_PORT 0x2F8
269 +
270 +#define IT8712_GPIO_BASE 0x800 // 0x800-0x804 for GPIO set1-set5
271 +
272 +void LPCSetConfig(char LdnNumber, char Index, char data);
273 +char LPCGetConfig(char LdnNumber, char Index);
274 +
275 +#endif
276 --- a/arch/arm/boot/compressed/misc.c
277 +++ b/arch/arm/boot/compressed/misc.c
278 @@ -30,7 +30,7 @@
279 #include <asm/arch/uncompress.h>
280
281 #ifdef CONFIG_DEBUG_ICEDCC
282 -
283 +#include "it8712.h"
284 #ifdef CONFIG_CPU_V6
285
286 static void icedcc_putc(int ch)
287 @@ -69,6 +69,7 @@
288 #define flush() do { } while (0)
289 #endif
290
291 +#if 0
292 static void putstr(const char *ptr)
293 {
294 char c;
295 @@ -81,11 +82,36 @@
296
297 flush();
298 }
299 +#endif
300
301 #endif
302
303 #define __ptr_t void *
304
305 +#ifdef CONFIG_SERIAL_IT8712
306 +unsigned int it8712_uart_base;
307 +#define UART_RX 0
308 +#define UART_TX 0
309 +#define UART_DLL 0
310 +#define UART_TRG 0
311 +#define UART_DLM 1
312 +#define UART_IER 1
313 +#define UART_FCTR 1
314 +#define UART_IIR 2
315 +#define UART_FCR 2
316 +#define UART_EFR 2
317 +#define UART_LCR 3
318 +#define UART_MCR 4
319 +#define UART_LSR 5
320 +#define UART_MSR 6
321 +#define UART_SCR 7
322 +#define UART_EMSR 7
323 +void LPCEnterMBPnP(void);
324 +void LPCExitMBPnP(void);
325 +int SearchIT8712(void);
326 +int InitLPCInterface(void);
327 +#endif
328 +
329 /*
330 * Optimised C version of memzero for the ARM.
331 */
332 @@ -346,6 +372,9 @@
333 decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p,
334 int arch_id)
335 {
336 +#ifdef CONFIG_SERIAL_IT8712
337 + unsigned char *addr;
338 +#endif
339 output_data = (uch *)output_start; /* Points to kernel start */
340 free_mem_ptr = free_mem_ptr_p;
341 free_mem_ptr_end = free_mem_ptr_end_p;
342 @@ -353,6 +382,33 @@
343
344 arch_decomp_setup();
345
346 +#ifdef CONFIG_SERIAL_IT8712
347 +
348 + InitLPCInterface();
349 + LPCSetConfig(0, 0x02, 0x01);
350 + LPCSetConfig(LDN_SERIAL1, 0x30, 0x1);
351 + LPCSetConfig(LDN_SERIAL1, 0x23, 0x0);
352 + it8712_uart_base = IT8712_IO_BASE;
353 + it8712_uart_base += ((LPCGetConfig(LDN_SERIAL1, 0x60) << 8) + LPCGetConfig(LDN_SERIAL1, 0x61));
354 +
355 + do {
356 + addr = (unsigned char *)(it8712_uart_base + UART_LCR) ;
357 + *addr = 0x80;
358 + // Set Baud Rate
359 + addr = (unsigned char *)(it8712_uart_base+UART_DLL);
360 + *addr = 0x06 ;
361 + addr = (unsigned char *)(it8712_uart_base+UART_DLM);
362 + *addr = 0x00 ;
363 +
364 + addr = (unsigned char *)(it8712_uart_base+UART_LCR); // LCR
365 + *addr = 0x07 ;
366 + addr = (unsigned char *)(it8712_uart_base+UART_MCR); // MCR
367 + *addr = 0x08 ;
368 + addr = (unsigned char *)(it8712_uart_base+UART_FCR); // FCR
369 + *addr = 0x01 ;
370 + } while(0);
371 +#endif
372 +
373 makecrc();
374 putstr("Uncompressing Linux...");
375 gunzip();
376 @@ -374,4 +430,119 @@
377 return 0;
378 }
379 #endif
380 +
381 +#ifdef CONFIG_SERIAL_IT8712
382 +
383 +#define LPC_KEY_ADDR (unsigned char *)(SL2312_LPC_IO_BASE + 0x2e)
384 +#define LPC_DATA_ADDR (unsigned char *)(SL2312_LPC_IO_BASE + 0x2f)
385 +#define LPC_BUS_CTRL *( unsigned char*) (SL2312_LPC_HOST_BASE + 0)
386 +#define LPC_BUS_STATUS *( unsigned char*) (SL2312_LPC_HOST_BASE + 2)
387 +#define LPC_SERIAL_IRQ_CTRL *( unsigned char*) (SL2312_LPC_HOST_BASE + 4)
388 +
389 +char LPCGetConfig(char LdnNumber, char Index)
390 +{
391 + char rtn;
392 + unsigned char *addr ;
393 +
394 + LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
395 +
396 + addr = LPC_KEY_ADDR;
397 + *addr = 0x07 ;
398 +
399 + addr = LPC_DATA_ADDR;
400 + *addr = LdnNumber ;
401 +
402 + addr = LPC_KEY_ADDR;
403 + *addr = Index ;
404 +
405 + addr = LPC_DATA_ADDR ;
406 + rtn = *addr ;
407 +
408 + LPCExitMBPnP();
409 + return rtn;
410 +
411 +}
412 +
413 +void LPCSetConfig(char LdnNumber, char Index, char data)
414 +{
415 + unsigned char *addr;
416 + LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
417 + addr = LPC_KEY_ADDR;
418 + *addr = 0x07;
419 + addr = LPC_DATA_ADDR;
420 + *addr = LdnNumber;
421 + addr = LPC_KEY_ADDR;
422 + *addr = Index;
423 + addr = LPC_DATA_ADDR;
424 + *addr = data;
425 +
426 + LPCExitMBPnP();
427 +}
428 +
429 +//unsigned char key[4] ;
430 +void LPCEnterMBPnP(void)
431 +{
432 + unsigned char *addr;
433 + addr = LPC_KEY_ADDR;
434 + unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
435 +
436 + do {
437 + *addr = key[0];
438 + *addr = key[1];
439 + *addr = key[2];
440 + *addr = key[3];
441 + }while(0);
442 +}
443 +
444 +void LPCExitMBPnP(void)
445 +{
446 + unsigned char *addr;
447 + addr = LPC_KEY_ADDR;
448 + *addr = 0x02 ;
449 +
450 + addr = LPC_DATA_ADDR;
451 + *addr = 0x02 ;
452 +}
453 +
454 +int InitLPCInterface(void)
455 +{
456 + int i;
457 + LPC_BUS_CTRL = 0xc0;
458 + LPC_SERIAL_IRQ_CTRL = 0xc0;
459 +
460 + for(i=0;i<0x2000;i++) ;
461 +
462 + LPC_SERIAL_IRQ_CTRL = 0x80;
463 + if (!SearchIT8712()) ;
464 +// while(1);
465 + return 0;
466 +}
467 +
468 +int SearchIT8712(void)
469 +{
470 + unsigned char Id1, Id2;
471 + unsigned short Id;
472 + unsigned char *addr;
473 +
474 + LPCEnterMBPnP();
475 + addr = LPC_KEY_ADDR;
476 + *addr = 0x20 ;
477 + addr = LPC_DATA_ADDR;
478 + Id1 = *addr ;
479 +
480 + addr = LPC_KEY_ADDR;
481 + *addr = 0x21 ;
482 + addr = LPC_DATA_ADDR;
483 + Id2 = *addr ;
484 +
485 + Id = (Id1 << 8) | Id2;
486 + LPCExitMBPnP();
487 +
488 + if (Id == 0x8712)
489 + return 1;
490 + else
491 + return 0;
492 +}
493 +
494 +#endif
495
496 --- a/arch/arm/kernel/entry-armv.S
497 +++ b/arch/arm/kernel/entry-armv.S
498 @@ -18,6 +18,8 @@
499 #include <asm/memory.h>
500 #include <asm/glue.h>
501 #include <asm/vfpmacros.h>
502 +#include <asm/arch/irqs.h>
503 +#include <asm/hardware.h>
504 #include <asm/arch/entry-macro.S>
505 #include <asm/thread_notify.h>
506
507 --- a/arch/arm/kernel/irq.c
508 +++ b/arch/arm/kernel/irq.c
509 @@ -40,6 +40,8 @@
510 #include <asm/system.h>
511 #include <asm/mach/time.h>
512
513 +extern int fixup_irq(unsigned int irq);
514 +
515 /*
516 * No architecture-specific irq_finish function defined in arm/arch/irqs.h.
517 */
518 @@ -111,8 +113,11 @@
519 asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
520 {
521 struct pt_regs *old_regs = set_irq_regs(regs);
522 - struct irq_desc *desc = irq_desc + irq;
523 +// struct irq_desc *desc = irq_desc + irq;
524 + struct irq_desc *desc;
525
526 + irq = fixup_irq(irq);
527 + desc = irq_desc + irq;
528 /*
529 * Some hardware gives randomly wrong interrupts. Rather
530 * than crashing, do something sensible.
531 --- a/arch/arm/kernel/process.c
532 +++ b/arch/arm/kernel/process.c
533 @@ -117,7 +117,7 @@
534 void (*pm_idle)(void);
535 EXPORT_SYMBOL(pm_idle);
536
537 -void (*pm_power_off)(void);
538 +//void (*pm_power_off)(void);
539 EXPORT_SYMBOL(pm_power_off);
540
541 void (*arm_pm_restart)(char str) = arm_machine_restart;
542 @@ -188,13 +188,37 @@
543
544 void machine_halt(void)
545 {
546 + unsigned int reg_v;
547 +
548 + printk("arch_power_off\n");
549 +
550 + reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
551 + reg_v &= ~0x00000002;
552 + reg_v |= 0x1;
553 + mdelay(5);
554 + // Power off
555 + __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
556 +
557 }
558
559
560 void machine_power_off(void)
561 {
562 - if (pm_power_off)
563 + unsigned int reg_v;
564 +
565 +// if (pm_power_off)
566 + if (&pm_power_off!=NULL)
567 pm_power_off();
568 +
569 + printk("arch_power_off\n");
570 +
571 + reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
572 + reg_v &= ~0x00000002;
573 + reg_v |= 0x1;
574 + mdelay(5);
575 + // Power off
576 + __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
577 +
578 }
579
580 void machine_restart(char * __unused)
581 --- a/arch/arm/kernel/time.c
582 +++ b/arch/arm/kernel/time.c
583 @@ -502,8 +502,13 @@
584
585 device_initcall(timer_init_sysfs);
586
587 +extern unsigned int rtc_get_time_second(void);
588 +
589 void __init time_init(void)
590 {
591 +#ifdef CONFIG_SL2312_RTC
592 + xtime.tv_sec = rtc_get_time_second() ;
593 +#endif
594 #ifndef CONFIG_GENERIC_TIME
595 if (system_timer->offset == NULL)
596 system_timer->offset = dummy_gettimeoffset;
597 --- /dev/null
598 +++ b/arch/arm/mach-sl2312/Kconfig
599 @@ -0,0 +1,33 @@
600 +
601 +menu "SL2312"
602 +
603 +config SL3516_ASIC
604 + bool "SL3516 ASIC version"
605 + depends on ARCH_SL2312
606 + help
607 + This option to select AISC or FPGA
608 +config PCI
609 + bool "SL2312 PCI"
610 + depends on ARCH_SL2312
611 + help
612 + This option to enable Storlink PCI controller
613 +
614 +config SL2312_LPC
615 + bool "SL2312 LPC"
616 + depends on ARCH_SL2312
617 + help
618 + This option to enable Low Pin Count controller
619 +
620 +config SL2312_USB
621 + bool "SL2312 USB"
622 + depends on ARCH_SL2312
623 + help
624 + This option to enable USB OTG host controller
625 +
626 +config GEMINI_IPI
627 + bool "Gemini IPI test"
628 + depends on ARCH_SL2312
629 + help
630 + Enable this option to test dual cpu Inter-Processor-Interrupt
631 +endmenu
632 +
633 --- /dev/null
634 +++ b/arch/arm/mach-sl2312/Makefile
635 @@ -0,0 +1,16 @@
636 +#
637 +# Makefile for the linux kernel.
638 +#
639 +
640 +# Object file lists.
641 +
642 +obj-y := arch.o irq.o mm.o time.o sl3516_device.o
643 +obj-m :=
644 +obj-n :=
645 +
646 +
647 +obj-$(CONFIG_PCI) += pci.o
648 +obj-$(CONFIG_SL2312_LPC) += lpc.o
649 +obj-$(CONFIG_SL2312_USB) += sl2312-otg.o # sl2312-otg-1.o
650 +obj-$(CONFIG_GEMINI_XOR_ACCE) += xor.o
651 +obj-$(CONFIG_GEMINI_IPI) += gemini_ipi.o
652 --- /dev/null
653 +++ b/arch/arm/mach-sl2312/Makefile.boot
654 @@ -0,0 +1,5 @@
655 + zreladdr-y := 0x00008000
656 +params_phys-y := 0x00508100
657 +#params_phys-y := 0x00008100
658 +initrd_phys-y := 0x00800000
659 +
660 --- /dev/null
661 +++ b/arch/arm/mach-sl2312/arch.c
662 @@ -0,0 +1,72 @@
663 +/*
664 + * linux/arch/arm/mach-epxa10db/arch.c
665 + *
666 + * Copyright (C) 2000 Deep Blue Solutions Ltd
667 + * Copyright (C) 2001 Altera Corporation
668 + *
669 + * This program is free software; you can redistribute it and/or modify
670 + * it under the terms of the GNU General Public License as published by
671 + * the Free Software Foundation; either version 2 of the License, or
672 + * (at your option) any later version.
673 + *
674 + * This program is distributed in the hope that it will be useful,
675 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
676 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
677 + * GNU General Public License for more details.
678 + *
679 + * You should have received a copy of the GNU General Public License
680 + * along with this program; if not, write to the Free Software
681 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
682 + */
683 +#include <linux/types.h>
684 +#include <linux/init.h>
685 +
686 +#include <asm/hardware.h>
687 +#include <asm/setup.h>
688 +#include <asm/mach-types.h>
689 +#include <asm/mach/time.h>
690 +#include <asm/mach/arch.h>
691 +
692 +extern void sl2312_map_io(void);
693 +extern void sl2312_init_irq(void);
694 +extern unsigned long sl2312_gettimeoffset (void);
695 +extern void __init sl2312_time_init(void);
696 +
697 +static struct sys_timer sl2312_timer = {
698 + .init = sl2312_time_init,
699 + .offset = sl2312_gettimeoffset,
700 +};
701 +
702 +static void __init
703 +sl2312_fixup(struct machine_desc *desc, struct tag *tags,
704 + char **cmdline, struct meminfo *mi)
705 +{
706 + mi->nr_banks = 1;
707 + mi->bank[0].start = 0;
708 +#ifdef CONFIG_GEMINI_IPI
709 + mi->bank[0].size = (64*1024*1024); // 128M
710 +#else
711 + mi->bank[0].size = (128*1024*1024); // 128M
712 +#endif
713 + mi->bank[0].node = 0;
714 +}
715 +
716 +/* MACHINE_START(SL2312, "GeminiA")
717 + MAINTAINER("Storlink Semi")
718 + BOOT_MEM(0x00000000, 0x90000000, 0xf0000000)
719 + FIXUP(sl2312_fixup)
720 + MAPIO(sl2312_map_io)
721 + INITIRQ(sl2312_init_irq)
722 + .timer = &sl2312_timer,
723 +MACHINE_END */
724 +
725 +MACHINE_START(SL2312, "GeminiA")
726 + /* .phys_ram = 0x00000000, */
727 + .phys_io = 0x7fffc000,
728 + .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
729 + .boot_params = 0x100,
730 + .fixup = sl2312_fixup,
731 + .map_io = sl2312_map_io,
732 + .init_irq = sl2312_init_irq,
733 + .timer = &sl2312_timer,
734 +MACHINE_END
735 --- /dev/null
736 +++ b/arch/arm/mach-sl2312/gemini_ipi.c
737 @@ -0,0 +1,593 @@
738 +/*
739 + * FILE NAME sl_cir.c
740 + *
741 + * BRIEF MODULE DESCRIPTION
742 + * IPI Driver for CPU1.
743 + *
744 + * Author: StorLink, Corp.
745 + * Jason Lee
746 + *
747 + * Copyright 2002~2006 StorLink, Corp.
748 + *
749 + * This program is free software; you can redistribute it and/or modify it
750 + * under the terms of the GNU General Public License as published by the
751 + * Free Software Foundation; either version 2 of the License, or (at your
752 + * option) any later version.
753 + *
754 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
755 + * WARRANTIES, INCLUDING, BUT NOT LIMit8712D TO, THE IMPLIED WARRANTIES OF
756 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
757 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
758 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
759 + * NOT LIMit8712D TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
760 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
761 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
762 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
763 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
764 + *
765 + * You should have received a copy of the GNU General Public License along
766 + * with this program; if not, writ8712 to the Free Software Foundation, Inc.,
767 + * 675 Mass Ave, Cambridge, MA 02139, USA.
768 + */
769 +
770 +#include <linux/module.h>
771 +#include <linux/types.h>
772 +#include <linux/kernel.h>
773 +#include <linux/miscdevice.h>
774 +#include <linux/init.h>
775 +#include <linux/pagemap.h>
776 +#include <asm/uaccess.h>
777 +#include <linux/ioport.h>
778 +#include <linux/sched.h>
779 +#include <linux/delay.h>
780 +#include <linux/fs.h>
781 +#include <linux/interrupt.h>
782 +#include <asm/io.h>
783 +#include <asm/delay.h>
784 +#include <linux/signal.h>
785 +#include <asm/arch/sl2312.h>
786 +#include <asm/arch/int_ctrl.h>
787 +#include <asm/arch/ipi.h>
788 +#include <linux/dma-mapping.h>
789 +
790 +
791 +#include <linux/mm.h>
792 +
793 +#include <linux/bootmem.h>
794 +
795 +#include <asm/hardware.h>
796 +#include <asm/page.h>
797 +#include <asm/setup.h>
798 +#include <asm/pgtable.h>
799 +#include <asm/pgalloc.h>
800 +
801 +#include <asm/mach/map.h>
802 +
803 +
804 +static int sl_ipi_debug = 1 ;
805 +#define DEB(x) if(sl_ipi_debug>=1) x
806 +
807 +#define SRAM_PTR IO_ADDRESS(SL2312_SRAM_BASE)
808 +volatile JSCALE_REQ_T *req=(JSCALE_REQ_T*)SRAM_PTR;
809 +volatile JSCALE_RSP_T *rsp=(JSCALE_RSP_T*)(SRAM_PTR+0x20);
810 +
811 +unsigned int jscale_status=0;
812 +
813 +#define JSCALE_WAIT 0
814 +#define XXXXXX_WAIT 1
815 +#define MAX_WAIT_Q 8
816 +wait_queue_head_t gemini_ipi_wait[MAX_WAIT_Q];
817 +
818 +#define DRAMCTL_DMA_CTL 0X20
819 +#define DRAMCTL_DMA_SA 0X24
820 +#define DRAMCTL_DMA_DA 0X28
821 +#define DRAMCTL_DMA_CNT 0X2C
822 +#define MEMCPY_UNIT 0x40000
823 +int hw_memcpy(const void *to, const void *from, unsigned int bytes)
824 +{
825 + unsigned int reg_a,reg_d;
826 + int count = bytes,i=0;
827 +
828 + consistent_sync((unsigned int *)to, bytes, DMA_BIDIRECTIONAL);
829 + consistent_sync((unsigned int *)from,bytes, DMA_TO_DEVICE);
830 +
831 + DEB(printk("hwmemcpy:count %d\n",count));
832 + while(count>0){
833 + // SA
834 + reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_SA;
835 + reg_d = (unsigned int )__virt_to_phys(from) + i*MEMCPY_UNIT;
836 + DEB(printk("hwmemcpy:from 0x%08x\n",reg_d));
837 + writel(reg_d,reg_a);
838 + // DA
839 + reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_DA;
840 + reg_d = (unsigned int )__virt_to_phys(to) + i*MEMCPY_UNIT;
841 + writel(reg_d,reg_a);
842 + DEB(printk("hwmemcpy:to 0x%08x\n",reg_d));
843 + // byte count
844 + reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CNT;
845 + reg_d = (count>=MEMCPY_UNIT)?MEMCPY_UNIT:count;
846 + writel(reg_d,reg_a);
847 + // start DMA
848 + reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL;
849 + writel(0x80000001,reg_a);
850 +
851 + do{
852 + cond_resched();
853 +// msleep(4);
854 + reg_d = readl(IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL);
855 + }while(reg_d&0x1);
856 +
857 + count -= MEMCPY_UNIT;
858 + i++;
859 + }
860 +
861 + return bytes;
862 +}
863 +
864 +static irqreturn_t ipi_interrupt()
865 +{
866 + unsigned int id=getcpuid(),tmp;
867 +
868 + //dmac_inv_range(__phys_to_virt(SL2312_SRAM_BASE),__phys_to_virt(SHAREADDR)+0x2000);
869 +
870 +
871 + // Clear Interrupt
872 + if(id==CPU0) {
873 + tmp = readl(CPU1_STATUS);
874 + tmp &= ~CPU_IPI_BIT_MASK;
875 + writel(tmp,CPU1_STATUS);
876 + }
877 + else{
878 + tmp = readl(CPU0_STATUS);
879 + tmp &= ~CPU_IPI_BIT_MASK;
880 + writel(tmp,CPU0_STATUS);
881 + }
882 +
883 + //
884 + DEB(printk("ipi interrupt:0x%x\n",rsp->status));
885 + switch(rsp->status){
886 + case JSCALE_STATUS_OK:
887 +
888 + break;
889 + case JSCALE_UNKNOWN_MSG_TYPE:
890 +
891 + break;
892 + case JSCALE_FAILED_FILE_SIZE:
893 +
894 + break;
895 + case JSCALE_FAILED_MALLOC:
896 +
897 + break;
898 + case JSCALE_FAILED_FORMAT:
899 +
900 + break;
901 + case JSCALE_DECODE_ERROR:
902 +
903 + break;
904 +
905 + }
906 + jscale_status = rsp->status;
907 +// wake_up(&gemini_ipi_wait[JSCALE_WAIT]);
908 +
909 + return IRQ_HANDLED;
910 +}
911 +
912 +static int gemini_ipi_open(struct inode *inode, struct file *file)
913 +{
914 + DEB(printk("ipi open\n"));
915 + return 0;
916 +}
917 +
918 +
919 +static int gemini_ipi_release(struct inode *inode, struct file *file)
920 +{
921 + DEB(printk("ipi release\n"));
922 + return 0;
923 +}
924 +
925 +
926 +static int gemini_ipi_ioctl(struct inode *inode, struct file *file,
927 + unsigned int cmd, unsigned long arg)
928 +{
929 + JSCALE_RSP_T tmp;
930 +
931 + switch(cmd) {
932 + case GEMINI_IPI_JSCALE_REQ:
933 + DEB(printk("ipi:ioctl jscale request %dX%d Q:%d\n",req->ScaledImageWidth,req->ScaledImageHeight,req->ScaledImageQuality));
934 + if (copy_from_user(req, (JSCALE_REQ_T *)arg, sizeof(JSCALE_REQ_T)))
935 + return -EFAULT;
936 + req->hdr.type = IPC_JSCALE_REQ_MSG;
937 + req->hdr.length = sizeof(JSCALE_REQ_T);
938 + req->input_location = CPU_1_DATA_OFFSET;
939 + req->output_location = CPU_1_DATA_OFFSET;
940 + break;
941 + case GEMINI_IPI_JSCALE_STAT:
942 + DEB(printk("ipi:ioctl jscale stat \n"));
943 + if(jscale_status==JSCALE_BUSY){ // not yet
944 + tmp.status = JSCALE_BUSY;
945 + if (copy_to_user((JSCALE_RSP_T *)arg,&tmp, sizeof(JSCALE_RSP_T)))
946 + return -EFAULT;
947 + }
948 + else{ // finish or error
949 + if (copy_to_user((JSCALE_RSP_T *)arg,rsp, sizeof(JSCALE_RSP_T)))
950 + return -EFAULT;
951 + }
952 + break;
953 + default:
954 + printk("IPI: Error IOCTL number\n");
955 + return -ENOIOCTLCMD;
956 + }
957 +
958 + return 0;
959 +}
960 +
961 +#define SRAM_SIZE 0x2000
962 +static ssize_t gemini_ipi_write(struct file *file_p, const char *buf, size_t count, loff_t * ppos)
963 +{
964 + int i=0,tmp=0,j;
965 + const char *ptr=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
966 + DEB(printk("ipi:write 0x%x to 0x%x length:%d\n",&buf,ptr,count));
967 + memcpy(ptr,buf,count);
968 + consistent_sync(ptr,count, DMA_TO_DEVICE);
969 + //hw_memcpy(ptr,&buf,count);
970 +
971 +/* if(count>SRAM_SIZE){
972 + for(i=0;i<(count/SRAM_SIZE);i++)
973 + raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,SRAM_SIZE);
974 + if(count%SRAM_SIZE)
975 + raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,count%SRAM_SIZE);
976 + }
977 + else
978 + raid_memcpy(ptr,buf,count);
979 +*/
980 +
981 +/* for(i=0;i<count;i++){
982 + if(buf[i]!=ptr[i])
983 + printk("ipi error:offset %d valud %x[should %x]\n",i,ptr[i],buf[i]);
984 + }
985 +
986 + printk("===========input buf===============\n");
987 + for(i=0;i<64;i+=16){
988 + for(j=0;j<16;j++)
989 + printk("%02x ",buf[i+j]);
990 + printk("\n");
991 + cond_resched();
992 + }
993 + printk("===========output buf==============\n");
994 + for(i=0;i<64;i+=16){
995 + for(j=0;j<16;j++)
996 + printk("%02x ",ptr[i+j]);
997 + printk("\n");
998 + cond_resched();
999 + }
1000 +*/
1001 + // send irq for CPU1
1002 + tmp |= CPU_IPI_BIT_MASK;
1003 + writel(tmp,CPU0_STATUS);
1004 + jscale_status = JSCALE_BUSY;
1005 +
1006 + return count;
1007 +}
1008 +
1009 +static ssize_t gemini_ipi_read(struct file * file_p, char *buf, size_t length, loff_t * ppos)
1010 +{
1011 + int i=0;
1012 + const char *ptr=(unsigned int )__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
1013 +
1014 + consistent_sync(ptr,length, DMA_FROM_DEVICE);
1015 + memcpy(buf,ptr,length);
1016 + DEB(printk("ipi:read 0x%x to 0x%x length:%d\n",ptr,buf,length));
1017 +
1018 + //consistent_sync((unsigned int *)ptr,0x2000, DMA_FROM_DEVICE); // invalid
1019 + //hw_memcpy(buf,ptr,length);
1020 +
1021 + // need encoded file size ********
1022 +/* if(count>SRAM_SIZE){
1023 + for(i=0;i<(count/SRAM_SIZE);i++)
1024 + raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,SRAM_SIZE);
1025 + if(count%0xFFFF)
1026 + raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,length%SRAM_SIZE);
1027 + }
1028 + else
1029 + raid_memcpy(buf,p_mbox->message,length);
1030 +*/
1031 + return length;
1032 +}
1033 +
1034 +void do_mapping_read(struct address_space *mapping,
1035 + struct file_ra_state *_ra,
1036 + struct file *filp,
1037 + loff_t *ppos,
1038 + read_descriptor_t *desc,
1039 + read_actor_t actor)
1040 +{
1041 + struct inode *inode = mapping->host;
1042 + unsigned long index;
1043 + unsigned long end_index;
1044 + unsigned long offset;
1045 + unsigned long last_index;
1046 + unsigned long next_index;
1047 + unsigned long prev_index;
1048 + loff_t isize;
1049 + struct page *cached_page;
1050 + int error;
1051 + struct file_ra_state ra = *_ra;
1052 +
1053 + cached_page = NULL;
1054 + index = *ppos >> PAGE_CACHE_SHIFT;
1055 + next_index = index;
1056 + prev_index = ra.prev_page;
1057 + last_index = (*ppos + desc->count + PAGE_CACHE_SIZE-1) >> PAGE_CACHE_SHIFT;
1058 + offset = *ppos & ~PAGE_CACHE_MASK;
1059 +
1060 + isize = i_size_read(inode);
1061 + if (!isize)
1062 + goto out;
1063 +
1064 + end_index = (isize - 1) >> PAGE_CACHE_SHIFT;
1065 + for (;;) {
1066 + struct page *page;
1067 + unsigned long nr, ret;
1068 +
1069 + /* nr is the maximum number of bytes to copy from this page */
1070 + nr = PAGE_CACHE_SIZE;
1071 + if (index >= end_index) {
1072 + if (index > end_index)
1073 + goto out;
1074 + nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1;
1075 + if (nr <= offset) {
1076 + goto out;
1077 + }
1078 + }
1079 + nr = nr - offset;
1080 +
1081 + cond_resched();
1082 + if (index == next_index)
1083 + next_index = page_cache_readahead(mapping, &ra, filp,
1084 + index, last_index - index);
1085 +
1086 +find_page:
1087 + page = find_get_page(mapping, index);
1088 + if (unlikely(page == NULL)) {
1089 + handle_ra_miss(mapping, &ra, index);
1090 + goto no_cached_page;
1091 + }
1092 + if (!PageUptodate(page))
1093 + goto page_not_up_to_date;
1094 +page_ok:
1095 +
1096 + /* If users can be writing to this page using arbitrary
1097 + * virtual addresses, take care about potential aliasing
1098 + * before reading the page on the kernel side.
1099 + */
1100 + if (mapping_writably_mapped(mapping))
1101 + flush_dcache_page(page);
1102 +
1103 + /*
1104 + * When (part of) the same page is read multiple times
1105 + * in succession, only mark it as accessed the first time.
1106 + */
1107 + if (prev_index != index)
1108 + mark_page_accessed(page);
1109 + prev_index = index;
1110 +
1111 + /*
1112 + * Ok, we have the page, and it's up-to-date, so
1113 + * now we can copy it to user space...
1114 + *
1115 + * The actor routine returns how many bytes were actually used..
1116 + * NOTE! This may not be the same as how much of a user buffer
1117 + * we filled up (we may be padding etc), so we can only update
1118 + * "pos" here (the actor routine has to update the user buffer
1119 + * pointers and the remaining count).
1120 + */
1121 + ret = actor(desc, page, offset, nr);
1122 + offset += ret;
1123 + index += offset >> PAGE_CACHE_SHIFT;
1124 + offset &= ~PAGE_CACHE_MASK;
1125 +
1126 + page_cache_release(page);
1127 + if (ret == nr && desc->count)
1128 + continue;
1129 + goto out;
1130 +
1131 +page_not_up_to_date:
1132 + /* Get exclusive access to the page ... */
1133 + lock_page(page);
1134 +
1135 + /* Did it get unhashed before we got the lock? */
1136 + if (!page->mapping) {
1137 + unlock_page(page);
1138 + page_cache_release(page);
1139 + continue;
1140 + }
1141 +
1142 + /* Did somebody else fill it already? */
1143 + if (PageUptodate(page)) {
1144 + unlock_page(page);
1145 + goto page_ok;
1146 + }
1147 +
1148 +readpage:
1149 + /* Start the actual read. The read will unlock the page. */
1150 + error = mapping->a_ops->readpage(filp, page);
1151 +
1152 + if (unlikely(error))
1153 + goto readpage_error;
1154 +
1155 + if (!PageUptodate(page)) {
1156 + lock_page(page);
1157 + if (!PageUptodate(page)) {
1158 + if (page->mapping == NULL) {
1159 + /*
1160 + * invalidate_inode_pages got it
1161 + */
1162 + unlock_page(page);
1163 + page_cache_release(page);
1164 + goto find_page;
1165 + }
1166 + unlock_page(page);
1167 + error = -EIO;
1168 + goto readpage_error;
1169 + }
1170 + unlock_page(page);
1171 + }
1172 +
1173 + /*
1174 + * i_size must be checked after we have done ->readpage.
1175 + *
1176 + * Checking i_size after the readpage allows us to calculate
1177 + * the correct value for "nr", which means the zero-filled
1178 + * part of the page is not copied back to userspace (unless
1179 + * another truncate extends the file - this is desired though).
1180 + */
1181 + isize = i_size_read(inode);
1182 + end_index = (isize - 1) >> PAGE_CACHE_SHIFT;
1183 + if (unlikely(!isize || index > end_index)) {
1184 + page_cache_release(page);
1185 + goto out;
1186 + }
1187 +
1188 + /* nr is the maximum number of bytes to copy from this page */
1189 + nr = PAGE_CACHE_SIZE;
1190 + if (index == end_index) {
1191 + nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1;
1192 + if (nr <= offset) {
1193 + page_cache_release(page);
1194 + goto out;
1195 + }
1196 + }
1197 + nr = nr - offset;
1198 + goto page_ok;
1199 +
1200 +readpage_error:
1201 + /* UHHUH! A synchronous read error occurred. Report it */
1202 + desc->error = error;
1203 + page_cache_release(page);
1204 + goto out;
1205 +
1206 +no_cached_page:
1207 + /*
1208 + * Ok, it wasn't cached, so we need to create a new
1209 + * page..
1210 + */
1211 + if (!cached_page) {
1212 + cached_page = page_cache_alloc_cold(mapping);
1213 + if (!cached_page) {
1214 + desc->error = -ENOMEM;
1215 + goto out;
1216 + }
1217 + }
1218 + error = add_to_page_cache_lru(cached_page, mapping,
1219 + index, GFP_KERNEL);
1220 + if (error) {
1221 + if (error == -EEXIST)
1222 + goto find_page;
1223 + desc->error = error;
1224 + goto out;
1225 + }
1226 + page = cached_page;
1227 + cached_page = NULL;
1228 + goto readpage;
1229 + }
1230 +
1231 +out:
1232 + *_ra = ra;
1233 +
1234 + *ppos = ((loff_t) index << PAGE_CACHE_SHIFT) + offset;
1235 + if (cached_page)
1236 + page_cache_release(cached_page);
1237 + if (filp)
1238 + file_accessed(filp);
1239 +}
1240 +
1241 +int ipi_send_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size)
1242 +{
1243 + ssize_t written;
1244 + unsigned long count = desc->count;
1245 + struct file *file = desc->arg.data;
1246 + unsigned int *ptr_to=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET) + desc->written;
1247 + void *ptr_from;
1248 +
1249 + if (size > count)
1250 + size = count;
1251 +
1252 + ptr_from = page_address(page)+offset;
1253 + written = memcpy(ptr_to,ptr_from,size);
1254 +
1255 + if (written < 0) {
1256 + desc->error = written;
1257 + written = 0;
1258 + }
1259 + desc->count = count - written;
1260 + desc->written += written;
1261 + return written;
1262 +}
1263 +
1264 +ssize_t gemini_ipi_sendfile(struct file *in_file, loff_t *ppos,
1265 + size_t count, read_actor_t actor, void *TARGET)
1266 +{
1267 + read_descriptor_t desc;
1268 +
1269 + if (!count)
1270 + return 0;
1271 +
1272 + desc.written = 0;
1273 + desc.count = count;
1274 + desc.arg.data = TARGET;
1275 + desc.error = 0;
1276 +
1277 + do_mapping_read(in_file->f_mapping,&in_file->f_ra,in_file, ppos, &desc, ipi_send_actor);
1278 +
1279 + if (desc.written)
1280 + return desc.written;
1281 + return desc.error;
1282 +}
1283 +static struct file_operations gemini_ipi_fops = {
1284 + .owner = THIS_MODULE,
1285 + .ioctl = gemini_ipi_ioctl,
1286 + .open = gemini_ipi_open,
1287 + .release= gemini_ipi_release,
1288 + .write = gemini_ipi_write,
1289 + .read = gemini_ipi_read,
1290 + .sendfile = gemini_ipi_sendfile,
1291 +};
1292 +
1293 +#ifndef STORLINK_IPI
1294 +#define STORLINK_IPI 242 // Documents/devices.txt suggest to use 240~255 for local driver!!
1295 +#endif
1296 +
1297 +static struct miscdevice gemini_ipi_miscdev =
1298 +{
1299 + STORLINK_IPI,
1300 + "slave_ipc",
1301 + &gemini_ipi_fops
1302 +};
1303 +
1304 +int __init sl_ipi_init(void)
1305 +{
1306 +
1307 + printk("Gemini IPI Driver Initialization...\n");
1308 + printk("REQ Head :0x%x(phy:0x%x)\n",(unsigned int)req,(unsigned int)SL2312_SRAM_BASE);
1309 + printk("RSP Head :0x%x(phy:0x%x)\n",(unsigned int)rsp,(unsigned int)SL2312_SRAM_BASE+0x20);
1310 + printk("Data buff:0x%x(phy:0x%x)\n",__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET),CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
1311 +
1312 + misc_register(&gemini_ipi_miscdev);
1313 +
1314 + if (request_irq(IRQ_CPU0_IP_IRQ_OFFSET, ipi_interrupt, SA_INTERRUPT, "ipi", NULL))
1315 + printk("Error: Register IRQ for Storlink IPI failed\n");
1316 +
1317 + return 0;
1318 +}
1319 +
1320 +void __exit sl_ipi_exit(void)
1321 +{
1322 +
1323 +}
1324 +
1325 +module_init(sl_ipi_init);
1326 +module_exit(sl_ipi_exit);
1327 +
1328 +MODULE_AUTHOR("Jason Lee <jason@storlink.com.tw>");
1329 +MODULE_DESCRIPTION("Storlink IPI driver");
1330 +MODULE_LICENSE("GPL");
1331 --- /dev/null
1332 +++ b/arch/arm/mach-sl2312/hw_xor.h
1333 @@ -0,0 +1,573 @@
1334 +/*
1335 +* linux/include/asm-arm/xor.h
1336 +*
1337 +* Copyright (C) 2001 Storlink Semi.
1338 +* Jason Lee <jason@storlink.com.tw>
1339 +*
1340 +*/
1341 +#include <asm/arch/sl2312.h>
1342 +#include <asm/io.h>
1343 +//#include <linux/compatmac.h>
1344 +
1345 +#undef BIG_ENDIAN
1346 +#define CPU 0
1347 +#define DMA 1
1348 +
1349 +#define DESC_NO 8
1350 +#define TX_DESC_NUM DESC_NO
1351 +#define RX_DESC_NUM DESC_NO
1352 +
1353 +#define RAID_BASE_ADDR IO_ADDRESS(SL2312_RAID_BASE)
1354 +
1355 +#define SRAM_PAR_0k 0
1356 +#define SRAM_PAR_4k 1
1357 +#define SRAM_PAR_8k 2
1358 +#define SRAM_PAR_16k 3
1359 +#define SRAM_PAR_SIZE SRAM_PAR_8k
1360 +
1361 +#define RUNNING 0x1
1362 +#define COMPLETE 0x2
1363 +#define ERROR 0x4
1364 +
1365 +#define CMD_XOR 0x0
1366 +#define CMD_FILL 0x1
1367 +#define CMD_CPY 0x3
1368 +#define CMD_CHK 0x4
1369 +
1370 +enum RAID_DMA_REGISTER {
1371 + RAID_DMA_DEVICE_ID = 0xff00,
1372 + RAID_DMA_STATUS = 0xff04,
1373 + RAID_FCHDMA_CTRL = 0xff08,
1374 + RAID_FCHDMA_FIRST_DESC = 0xff0C,
1375 + RAID_FCHDMA_CURR_DESC = 0xff10,
1376 + RAID_STRDMA_CTRL = 0xff14,
1377 + RAID_STRDMA_FIRST_DESC = 0xff18,
1378 + RAID_STRDMA_CURR_DESC = 0xff1C,
1379 + RAID_TX_FLG_REG = 0xff24,
1380 + RAID_RX_FLG_REG = 0xff34,
1381 + RAID_PCR = 0xff50,
1382 + SMC_CMD_REG = 0xff60,
1383 + SMC_STATUS_REG = 0xff64
1384 + };
1385 +
1386 +enum RAID_FUNC_MODE {
1387 + RAID_XOR = 0,
1388 + RAID_MIX = 2,
1389 + RAID_SRAM = 3,
1390 + RAID_ENDIAN = 4,
1391 + RAID_MEM_BLK = 5,
1392 + RAID_MEM2MEM = 7,
1393 + RAID_BUF_SIZE = 8,
1394 + RAID_ERR_TEST = 9,
1395 + RAID_BURST = 10,
1396 + RAID_BUS = 11
1397 + };
1398 +
1399 +typedef struct reg_info {
1400 + int mask;
1401 + char err[32];
1402 + int offset;
1403 +} REG_INFO;
1404 +
1405 +/********************************************************/
1406 +/* the definition of RAID DMA Module Register */
1407 +/********************************************************/
1408 +typedef union
1409 +{
1410 + unsigned int bit32;
1411 + struct bits_ff00
1412 + {
1413 + #ifdef BIG_ENDIAN
1414 + unsigned int : 8;
1415 + unsigned int teytPerr : 4; /* define protocol error under tsPErrI*/
1416 + unsigned int reytPerr : 14; /* define protocol error under rsPErrI */
1417 + unsigned int device_id : 12;
1418 + unsigned int revision_id : 4;
1419 + #else
1420 + unsigned int revision_id : 4;
1421 + unsigned int device_id : 12;
1422 + unsigned int reytPerr : 14; /* define protocol error under rsPErrI */
1423 + unsigned int teytPerr : 4; /* define protocol error under tsPErrI*/
1424 + unsigned int : 8;
1425 + #endif
1426 + } bits;
1427 +} RAID_DMA_DEVICE_ID_T;
1428 +
1429 +typedef union
1430 +{
1431 + unsigned int bits32;
1432 + struct bits_ff04
1433 + {
1434 + #ifdef BIG_ENDIAN
1435 + unsigned int tsFinishI : 1; /* owner bit error interrupt */
1436 + unsigned int tsDErrI : 1; /* AHB bus error interrupt */
1437 + unsigned int tsPErrI : 1; /* RAID XOR fetch descriptor protocol error interrupt */
1438 + unsigned int tsEODI : 1; /* RAID XOR fetch DMA end of descriptor interrupt */
1439 + unsigned int tsEOFI : 1; /* RAID XOR fetch DMA end of frame interrupt */
1440 + unsigned int rsFinishI : 1; /* owner bit error interrupt */
1441 + unsigned int rsDErrI : 1; /* AHB bus error while RAID XOR store interrupt */
1442 + unsigned int rsPErrI : 1; /* RAID XOR store descriptor protocol error interrupt */
1443 + unsigned int rsEODI : 1; /* RAID XOR store DMA end of descriptor interrupt */
1444 + unsigned int rsEOFI : 1; /* RAID XOR store DMA end of frame interrupt */
1445 + unsigned int inter : 8; /* pattern check error interrupt */
1446 + unsigned int : 5;
1447 + unsigned int Loopback : 1; /* loopback */
1448 + unsigned int intEnable : 8; /*pattern check error interrupt enable */
1449 + #else
1450 + unsigned int intEnable : 8; /*pattern check error interrupt enable */
1451 + unsigned int Loopback : 1; /* loopback */
1452 + unsigned int : 5;
1453 + unsigned int inter : 8; /* pattern check error interrupt */
1454 + unsigned int rsEOFI : 1; /* RAID XOR store DMA end of frame interrupt */
1455 + unsigned int rsEODI : 1; /* RAID XOR store DMA end of descriptor interrupt */
1456 + unsigned int rsPErrI : 1; /* RAID XOR store descriptor protocol error interrupt */
1457 + unsigned int rsDErrI : 1; /* AHB bus error while RAID XOR store interrupt */
1458 + unsigned int rsFinishI : 1; /* owner bit error interrupt */
1459 + unsigned int tsEOFI : 1; /* RAID XOR fetch DMA end of frame interrupt */
1460 + unsigned int tsEODI : 1; /* RAID XOR fetch DMA end of descriptor interrupt */
1461 + unsigned int tsPErrI : 1; /* RAID XOR fetch descriptor protocol error interrupt */
1462 + unsigned int tsDErrI : 1; /* AHB bus error interrupt */
1463 + unsigned int tsFinishI : 1; /* owner bit error interrupt */
1464 + #endif
1465 + } bits;
1466 +} RAID_DMA_STATUS_T;
1467 +
1468 +
1469 +typedef union
1470 +{
1471 + unsigned int bits32;
1472 + struct bits_ff08
1473 + {
1474 + #ifdef BIG_ENDIAN
1475 + unsigned int td_start : 1; /* Start DMA transfer */
1476 + unsigned int td_continue : 1; /* Continue DMA operation */
1477 + unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1478 + unsigned int : 1;
1479 + unsigned int td_prot : 4; /* DMA protection control */
1480 + unsigned int td_burst_size : 2; /* DMA max burst size for every AHB request */
1481 + unsigned int td_bus : 2; /* peripheral bus width */
1482 + unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
1483 + unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1484 + unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
1485 + unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1486 + unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
1487 + unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
1488 + unsigned int : 14;
1489 + #else
1490 + unsigned int : 14;
1491 + unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
1492 + unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
1493 + unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1494 + unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
1495 + unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1496 + unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
1497 + unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1498 + unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */
1499 + unsigned int td_prot : 4; /* TxDMA protection control */
1500 + unsigned int : 1;
1501 + unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1502 + unsigned int td_continue : 1; /* Continue DMA operation */
1503 + unsigned int td_start : 1; /* Start DMA transfer */
1504 + #endif
1505 + } bits;
1506 +} RAID_TXDMA_CTRL_T;
1507 +
1508 +typedef union
1509 +{
1510 + unsigned int bits32;
1511 + struct bits_ff0c
1512 + {
1513 + #ifdef BIG_ENDIAN
1514 + unsigned int td_first_des_ptr : 28;/* first descriptor address */
1515 + unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */
1516 + unsigned int : 3;
1517 + #else
1518 + unsigned int : 3;
1519 + unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */
1520 + unsigned int td_first_des_ptr : 28;/* first descriptor address */
1521 + #endif
1522 + } bits;
1523 +} RAID_TXDMA_FIRST_DESC_T;
1524 +
1525 +typedef union
1526 +{
1527 + unsigned int bits32;
1528 + struct bits_ff10
1529 + {
1530 + #ifdef BIG_ENDIAN
1531 + unsigned int ndar : 28; /* next descriptor address */
1532 + unsigned int eofie : 1; /* end of frame interrupt enable */
1533 + unsigned int : 1;
1534 + unsigned int sof_eof : 2;
1535 + #else
1536 + unsigned int sof_eof : 2;
1537 + unsigned int : 1;
1538 + unsigned int eofie : 1; /* end of frame interrupt enable */
1539 + unsigned int ndar : 28; /* next descriptor address */
1540 + #endif
1541 + } bits;
1542 +} RAID_TXDMA_CURR_DESC_T;
1543 +
1544 +typedef union
1545 +{
1546 + unsigned int bits32;
1547 + struct bits_ff14
1548 + {
1549 + #ifdef BIG_ENDIAN
1550 + unsigned int rd_start : 1; /* Start DMA transfer */
1551 + unsigned int rd_continue : 1; /* Continue DMA operation */
1552 + unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1553 + unsigned int : 1;
1554 + unsigned int rd_prot : 4; /* DMA protection control */
1555 + unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */
1556 + unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1557 + unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
1558 + unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1559 + unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
1560 + unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1561 + unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
1562 + unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
1563 + unsigned int : 14;
1564 + #else
1565 + unsigned int : 14;
1566 + unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
1567 + unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
1568 + unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1569 + unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
1570 + unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1571 + unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
1572 + unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1573 + unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */
1574 + unsigned int rd_prot : 4; /* DMA protection control */
1575 + unsigned int : 1;
1576 + unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1577 + unsigned int rd_continue : 1; /* Continue DMA operation */
1578 + unsigned int rd_start : 1; /* Start DMA transfer */
1579 + #endif
1580 + } bits;
1581 +} RAID_RXDMA_CTRL_T;
1582 +
1583 +typedef union
1584 +{
1585 + unsigned int bits32;
1586 + struct bits_ff18
1587 + {
1588 + #ifdef BIG_ENDIAN
1589 + unsigned int rd_first_des_ptr : 28;/* first descriptor address */
1590 + unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */
1591 + unsigned int : 3;
1592 + #else
1593 + unsigned int : 3;
1594 + unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */
1595 + unsigned int rd_first_des_ptr : 28;/* first descriptor address */
1596 + #endif
1597 + } bits;
1598 +} RAID_RXDMA_FIRST_DESC_T;
1599 +
1600 +typedef union
1601 +{
1602 + unsigned int bits32;
1603 + struct bits_ff1c
1604 + {
1605 + #ifdef BIG_ENDIAN
1606 + unsigned int ndar : 28; /* next descriptor address */
1607 + unsigned int eofie : 1; /* end of frame interrupt enable */
1608 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
1609 + unsigned int sof_eof : 2;
1610 + #else
1611 + unsigned int sof_eof : 2;
1612 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
1613 + unsigned int eofie : 1; /* end of frame interrupt enable */
1614 + unsigned int ndar : 28; /* next descriptor address */
1615 + #endif
1616 + } bits;
1617 +} RAID_RXDMA_CURR_DESC_T;
1618 +
1619 +typedef union
1620 +{
1621 + unsigned int bit32;
1622 + struct bits_ff50
1623 + {
1624 + unsigned int pat : 32; /* data for pattern check */
1625 + } bits;
1626 +} RAID_PACR_T;
1627 +
1628 +/******************************************************/
1629 +/* the definition of DMA Descriptor Register */
1630 +/******************************************************/
1631 +typedef struct raid_descriptor_t
1632 +{
1633 + union func_ctrl_t
1634 + {
1635 + unsigned int bit32;
1636 + struct bits_0000
1637 + {
1638 + #ifdef BIG_ENDIAN
1639 + unsigned int own : 1; /* owner bit */
1640 + unsigned int derr : 1; /* data error during processing this descriptor */
1641 + unsigned int perr : 1; /* protocol error during processing this descriptor */
1642 + unsigned int raid_ctrl_status : 7; /* pass RAID XOR fetch/store control status to CPU */
1643 + unsigned int desc_cnt : 6;
1644 + unsigned int buffer_size : 16; /* transfer buffer size associated with current description*/
1645 + #else
1646 + unsigned int buffer_size : 16; /* transfer buffer size associated with current description*/
1647 + unsigned int desc_cnt : 6;
1648 + unsigned int raid_ctrl_status : 7; /* pass RAID XOR fetch/store control status to CPU */
1649 + unsigned int perr : 1; /* protocol error during processing this descriptor */
1650 + unsigned int derr : 1; /* data error during processing this descriptor */
1651 + unsigned int own : 1; /* owner bit */
1652 + #endif
1653 + } bits;
1654 + } func_ctrl;
1655 +
1656 + union flg_status_t
1657 + {
1658 + unsigned int bits32;
1659 + struct bit_004
1660 + {
1661 + #ifdef BIG_ENDIAN
1662 + unsigned int bcc : 16;
1663 + unsigned int : 13
1664 + unsigned int mode : 3;
1665 + #else
1666 + unsigned int mode : 3;
1667 + unsigned int : 13;
1668 + unsigned int bcc : 16;
1669 + #endif
1670 + } bits_cmd_status;
1671 + } flg_status; //Sanders
1672 +
1673 + unsigned int buf_addr;
1674 +
1675 + union next_desc_addr_t
1676 + {
1677 + unsigned int bits32;
1678 + struct bits_000c
1679 + {
1680 + #ifdef BIG_ENDIAN
1681 + unsigned int ndar : 28; /* next descriptor address */
1682 + unsigned int eofie : 1; /* end of frame interrupt enable */
1683 + unsigned int : 1;
1684 + unsigned int sof_eof : 2; /* the position of the descriptor in chain */
1685 + #else
1686 + unsigned int sof_eof : 2; /* the position of the descriptor in chain */
1687 + unsigned int : 1;
1688 + unsigned int eofie : 1; /* end of frame interrupt enable */
1689 + unsigned int ndar : 28; /* next descriptor address */
1690 + #endif
1691 + } bits;
1692 + } next_desc_addr;
1693 +} RAID_DESCRIPTOR_T;
1694 +
1695 +/******************************************************/
1696 +/* the offset of RAID SMC register */
1697 +/******************************************************/
1698 +enum RAID_SMC_REGISTER {
1699 + RAID_SMC_CMD_REG = 0xff60,
1700 + RAID_SMC_STATUS_REG = 0xff64
1701 + };
1702 +
1703 +/******************************************************/
1704 +/* the definition of RAID SMC module register */
1705 +/******************************************************/
1706 +typedef union
1707 +{
1708 + unsigned int bits32;
1709 + struct bits_ff60
1710 + {
1711 + #ifdef BIG_ENDIAN
1712 + unsigned int pat_mode : 2; /* partition mode selection */
1713 + unsigned int : 14;
1714 + unsigned int device_id : 12;
1715 + unsigned int revision_id : 4;
1716 + #else
1717 + unsigned int revision_id : 4;
1718 + unsigned int device_id : 12;
1719 + unsigned int : 14;
1720 + unsigned int pat_mode : 2; /* partition mode selection */
1721 + #endif
1722 + } bits;
1723 +} RAID_SMC_CMD;
1724 +
1725 +typedef union
1726 +{
1727 + unsigned int bits32;
1728 + struct bits_ff64
1729 + {
1730 + #ifdef BIG_ENDIAN
1731 + unsigned int addr_err1 : 1; /* address is out of range for controller 1 */
1732 + unsigned int ahb_err1 : 1; /* AHB bus error for controller 1 */
1733 + unsigned int : 14;
1734 + unsigned int addr_err2 : 1; /* address is out of range for controller 2 */
1735 + unsigned int ahb_err2 : 1; /* AHB bus error for controller 2 */
1736 + unsigned int : 14;
1737 + #else
1738 + unsigned int : 14;
1739 + unsigned int ahb_err2 : 1; /* AHB bus error for controller 2 */
1740 + unsigned int addr_err2 : 1; /* address is out of range for controller 2 */
1741 + unsigned int : 14;
1742 + unsigned int ahb_err1 : 1; /* AHB bus error for controller 1 */
1743 + unsigned int addr_err1 : 1; /* address is out of range for controller 1 */
1744 + #endif
1745 + } bits;
1746 +} RAID_SMC_STATUS;
1747 +
1748 +typedef struct RAID_S
1749 +{
1750 + const char *device_name;
1751 + wait_queue_head_t wait;
1752 + unsigned int busy;
1753 + int irq;
1754 + unsigned int status;
1755 + RAID_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address */
1756 + RAID_DESCRIPTOR_T *rx_desc; /* point ot virtual RX descriptor address */
1757 + RAID_DESCRIPTOR_T *tx_cur_desc; /* current TX descriptor */
1758 + RAID_DESCRIPTOR_T *rx_cur_desc; /* current RX descriptor */
1759 + RAID_DESCRIPTOR_T *tx_finished_desc;
1760 + RAID_DESCRIPTOR_T *rx_finished_desc;
1761 + RAID_DESCRIPTOR_T *tx_first_desc;
1762 + RAID_DESCRIPTOR_T *rx_first_desc;
1763 +
1764 +// unsigned int *tx_buf[TX_DESC_NUM];
1765 + unsigned int *rx_desc_dma; // physical address of rx_descript
1766 + unsigned int *tx_desc_dma; // physical address of tx_descript
1767 + unsigned int *rx_bufs_dma;
1768 + unsigned int *tx_bufs_dma;
1769 +
1770 +} RAID_T;
1771 +
1772 +struct reg_ioctl
1773 +{
1774 + unsigned int reg_addr;
1775 + unsigned int val_in;
1776 + unsigned int val_out;
1777 +};
1778 +
1779 +typedef struct dma_ctrl {
1780 + int sram;
1781 + int prot;
1782 + int burst;
1783 + int bus;
1784 + int endian;
1785 + int mode;
1786 +} DMA_CTRL;
1787 +
1788 +
1789 +#ifdef XOR_SW_FILL_IN
1790 +
1791 +#define __XOR(a1, a2) a1 ^= a2
1792 +
1793 +#define GET_BLOCK_2(dst) \
1794 + __asm__("ldmia %0, {%1, %2}" \
1795 + : "=r" (dst), "=r" (a1), "=r" (a2) \
1796 + : "0" (dst))
1797 +
1798 +#define GET_BLOCK_4(dst) \
1799 + __asm__("ldmia %0, {%1, %2, %3, %4}" \
1800 + : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \
1801 + : "0" (dst))
1802 +
1803 +#define XOR_BLOCK_2(src) \
1804 + __asm__("ldmia %0!, {%1, %2}" \
1805 + : "=r" (src), "=r" (b1), "=r" (b2) \
1806 + : "0" (src)); \
1807 + __XOR(a1, b1); __XOR(a2, b2);
1808 +
1809 +#define XOR_BLOCK_4(src) \
1810 + __asm__("ldmia %0!, {%1, %2, %3, %4}" \
1811 + : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \
1812 + : "0" (src)); \
1813 + __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4)
1814 +
1815 +#define PUT_BLOCK_2(dst) \
1816 + __asm__ __volatile__("stmia %0!, {%2, %3}" \
1817 + : "=r" (dst) \
1818 + : "0" (dst), "r" (a1), "r" (a2))
1819 +
1820 +#define PUT_BLOCK_4(dst) \
1821 + __asm__ __volatile__("stmia %0!, {%2, %3, %4, %5}" \
1822 + : "=r" (dst) \
1823 + : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4))
1824 +
1825 +static void
1826 +xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
1827 +{
1828 + unsigned int lines = bytes / sizeof(unsigned long) / 4;
1829 + register unsigned int a1 __asm__("r4");
1830 + register unsigned int a2 __asm__("r5");
1831 + register unsigned int a3 __asm__("r6");
1832 + register unsigned int a4 __asm__("r7");
1833 + register unsigned int b1 __asm__("r8");
1834 + register unsigned int b2 __asm__("r9");
1835 + register unsigned int b3 __asm__("ip");
1836 + register unsigned int b4 __asm__("lr");
1837 +
1838 + do {
1839 + GET_BLOCK_4(p1);
1840 + XOR_BLOCK_4(p2);
1841 + PUT_BLOCK_4(p1);
1842 + } while (--lines);
1843 +}
1844 +
1845 +static void
1846 +xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1847 + unsigned long *p3)
1848 +{
1849 + unsigned int lines = bytes / sizeof(unsigned long) / 4;
1850 + register unsigned int a1 __asm__("r4");
1851 + register unsigned int a2 __asm__("r5");
1852 + register unsigned int a3 __asm__("r6");
1853 + register unsigned int a4 __asm__("r7");
1854 + register unsigned int b1 __asm__("r8");
1855 + register unsigned int b2 __asm__("r9");
1856 + register unsigned int b3 __asm__("ip");
1857 + register unsigned int b4 __asm__("lr");
1858 +
1859 + do {
1860 + GET_BLOCK_4(p1);
1861 + XOR_BLOCK_4(p2);
1862 + XOR_BLOCK_4(p3);
1863 + PUT_BLOCK_4(p1);
1864 + } while (--lines);
1865 +}
1866 +
1867 +static void
1868 +xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1869 + unsigned long *p3, unsigned long *p4)
1870 +{
1871 + unsigned int lines = bytes / sizeof(unsigned long) / 2;
1872 + register unsigned int a1 __asm__("r8");
1873 + register unsigned int a2 __asm__("r9");
1874 + register unsigned int b1 __asm__("ip");
1875 + register unsigned int b2 __asm__("lr");
1876 +
1877 + do {
1878 + GET_BLOCK_2(p1);
1879 + XOR_BLOCK_2(p2);
1880 + XOR_BLOCK_2(p3);
1881 + XOR_BLOCK_2(p4);
1882 + PUT_BLOCK_2(p1);
1883 + } while (--lines);
1884 +}
1885 +
1886 +static void
1887 +xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1888 + unsigned long *p3, unsigned long *p4, unsigned long *p5)
1889 +{
1890 + unsigned int lines = bytes / sizeof(unsigned long) / 2;
1891 + register unsigned int a1 __asm__("r8");
1892 + register unsigned int a2 __asm__("r9");
1893 + register unsigned int b1 __asm__("ip");
1894 + register unsigned int b2 __asm__("lr");
1895 +
1896 + do {
1897 + GET_BLOCK_2(p1);
1898 + XOR_BLOCK_2(p2);
1899 + XOR_BLOCK_2(p3);
1900 + XOR_BLOCK_2(p4);
1901 + XOR_BLOCK_2(p5);
1902 + PUT_BLOCK_2(p1);
1903 + } while (--lines);
1904 +}
1905 +#endif //XOR_SW_FILL_IN
1906 +
1907 --- /dev/null
1908 +++ b/arch/arm/mach-sl2312/irq.c
1909 @@ -0,0 +1,202 @@
1910 +/*
1911 + * linux/arch/arm/mach-epxa10db/irq.c
1912 + *
1913 + * Copyright (C) 2001 Altera Corporation
1914 + *
1915 + * This program is free software; you can redistribute it and/or modify
1916 + * it under the terms of the GNU General Public License as published by
1917 + * the Free Software Foundation; either version 2 of the License, or
1918 + * (at your option) any later version.
1919 + *
1920 + * This program is distributed in the hope that it will be useful,
1921 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1922 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1923 + * GNU General Public License for more details.
1924 + *
1925 + * You should have received a copy of the GNU General Public License
1926 + * along with this program; if not, write to the Free Software
1927 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1928 + */
1929 +#include <linux/init.h>
1930 +#include <linux/ioport.h>
1931 +#include <linux/stddef.h>
1932 +#include <linux/list.h>
1933 +#include <linux/sched.h>
1934 +#include <asm/hardware.h>
1935 +#include <asm/irq.h>
1936 +#include <asm/io.h>
1937 +#include <asm/mach/irq.h>
1938 +#include <asm/arch/platform.h>
1939 +#include <asm/arch/int_ctrl.h>
1940 +
1941 +#ifdef CONFIG_PCI
1942 +#include <asm/arch/pci.h>
1943 +#endif
1944 +
1945 +int fixup_irq(unsigned int irq)
1946 +{
1947 +#ifdef CONFIG_PCI
1948 + if (irq == IRQ_PCI) {
1949 + return sl2312_pci_get_int_src();
1950 + }
1951 +#endif
1952 + return irq;
1953 +}
1954 +
1955 +static void sl2312_ack_irq(unsigned int irq)
1956 +{
1957 + __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1958 +}
1959 +
1960 +static void sl2312_mask_irq(unsigned int irq)
1961 +{
1962 + unsigned int mask;
1963 +
1964 +#ifdef CONFIG_PCI
1965 + if (irq >= PCI_IRQ_OFFSET)
1966 + {
1967 + mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1968 + mask &= ~IRQ_PCI_MASK ;
1969 + __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1970 + sl2312_pci_mask_irq(irq - PCI_IRQ_OFFSET);
1971 + }
1972 + else
1973 +#endif
1974 + if(irq >= FIQ_OFFSET)
1975 + {
1976 + mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1977 + mask &= ~(1 << (irq - FIQ_OFFSET));
1978 + __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1979 + }
1980 + else
1981 + {
1982 + mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1983 + mask &= ~(1 << irq);
1984 + __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1985 + }
1986 +
1987 +}
1988 +
1989 +static void sl2312_unmask_irq(unsigned int irq)
1990 +{
1991 + unsigned int mask;
1992 +
1993 +#ifdef CONFIG_PCI
1994 + if (irq >= PCI_IRQ_OFFSET)
1995 + {
1996 + mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1997 + mask |= IRQ_PCI_MASK ;
1998 + __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1999 + sl2312_pci_unmask_irq(irq - PCI_IRQ_OFFSET);
2000 + }
2001 + else
2002 +#endif
2003 + if(irq >= FIQ_OFFSET)
2004 + {
2005 + mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2006 + mask |= (1 << (irq - FIQ_OFFSET));
2007 + __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2008 + }
2009 + else
2010 + {
2011 + mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2012 + mask |= (1 << irq);
2013 + __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2014 + }
2015 +}
2016 +
2017 +static struct irq_chip sl2312_level_irq = {
2018 + .ack = sl2312_mask_irq,
2019 + .mask = sl2312_mask_irq,
2020 + .unmask = sl2312_unmask_irq,
2021 +// .set_type = ixp4xx_set_irq_type,
2022 +};
2023 +
2024 +static struct irq_chip sl2312_edge_irq = {
2025 + .ack = sl2312_ack_irq,
2026 + .mask = sl2312_mask_irq,
2027 + .unmask = sl2312_unmask_irq,
2028 +// .set_type = ixp4xx_set_irq_type,
2029 +};
2030 +
2031 +static struct resource irq_resource = {
2032 + .name = "irq_handler",
2033 + .start = IO_ADDRESS(SL2312_INTERRUPT_BASE),
2034 + .end = IO_ADDRESS(FIQ_STATUS(SL2312_INTERRUPT_BASE))+4,
2035 +};
2036 +
2037 +void __init sl2312_init_irq(void)
2038 +{
2039 + unsigned int i, mode, level;
2040 +
2041 + request_resource(&iomem_resource, &irq_resource);
2042 +
2043 + for (i = 0; i < NR_IRQS; i++)
2044 + {
2045 + if((i>=IRQ_TIMER1 && i<=IRQ_TIMER3)||(i>=IRQ_SERIRQ0 && i<=IRQ_SERIRQ_MAX))
2046 + {
2047 + set_irq_chip(i, &sl2312_edge_irq);
2048 + set_irq_handler(i, handle_edge_irq);
2049 + }
2050 + else
2051 + {
2052 + set_irq_chip(i, &sl2312_level_irq);
2053 + set_irq_handler(i,handle_level_irq);
2054 + }
2055 + set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
2056 + }
2057 +
2058 + /* Disable all interrupt */
2059 + __raw_writel(0,IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2060 + __raw_writel(0,FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2061 +
2062 + /* Set interrupt mode */
2063 + /* emac & ipsec type is level trigger and high active */
2064 + mode = __raw_readl(IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2065 + level = __raw_readl(IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2066 +
2067 + mode &= ~IRQ_GMAC0_MASK;
2068 + level &= ~IRQ_GMAC0_MASK;
2069 +
2070 + mode &= ~IRQ_GMAC1_MASK;
2071 + level &= ~IRQ_GMAC1_MASK;
2072 +
2073 + mode &= ~IRQ_IPSEC_MASK;
2074 + level &= ~IRQ_IPSEC_MASK;
2075 +
2076 + // for IDE0,1, high active and level trigger
2077 + mode &= ~IRQ_IDE0_MASK;
2078 + level &= ~IRQ_IDE0_MASK;
2079 + mode &= ~IRQ_IDE1_MASK;
2080 + level &= ~IRQ_IDE1_MASK;
2081 +
2082 +
2083 + // for PCI, high active and level trigger
2084 + mode &= ~IRQ_PCI_MASK;
2085 + level &= ~IRQ_PCI_MASK;
2086 +
2087 + // for USB, high active and level trigger
2088 + mode &= ~IRQ_USB0_MASK;
2089 + level &= ~IRQ_USB0_MASK;
2090 +
2091 + mode &= ~IRQ_USB1_MASK;
2092 + level &= ~IRQ_USB1_MASK;
2093 +
2094 + // for LPC, high active and edge trigger
2095 + mode |= 0xffff0000;
2096 + level &= 0x0000ffff;
2097 +
2098 + // for GPIO, high active and level trigger
2099 + mode &= ~(IRQ_GPIO_MASK);
2100 + level &= ~(IRQ_GPIO_MASK);
2101 +
2102 + mode &= ~(IRQ_GPIO1_MASK);
2103 + level &= ~(IRQ_GPIO1_MASK);
2104 +
2105 + mode &= ~(IRQ_GPIO2_MASK);
2106 + level &= ~(IRQ_GPIO2_MASK);
2107 +
2108 + __raw_writel(mode,IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2109 + __raw_writel(level,IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2110 +
2111 +}
2112 --- /dev/null
2113 +++ b/arch/arm/mach-sl2312/lpc.c
2114 @@ -0,0 +1,125 @@
2115 +/*
2116 + *
2117 + * BRIEF MODULE DESCRIPTION
2118 + * ITE Semi IT8712 Super I/O functions.
2119 + *
2120 + * Copyright 2001 MontaVista Software Inc.
2121 + * Author: MontaVista Software, Inc.
2122 + * ppopov@mvista.com or source@mvista.com
2123 + *
2124 + * This program is free software; you can redistribute it and/or modify it
2125 + * under the terms of the GNU General Public License as published by the
2126 + * Free Software Foundation; either version 2 of the License, or (at your
2127 + * option) any later version.
2128 + *
2129 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2130 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2131 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2132 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2133 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2134 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2135 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2136 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2137 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2138 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2139 + *
2140 + * You should have received a copy of the GNU General Public License along
2141 + * with this program; if not, write to the Free Software Foundation, Inc.,
2142 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2143 + */
2144 +#include <linux/kernel.h>
2145 +#include <linux/delay.h>
2146 +#include <asm/io.h>
2147 +#include <asm/types.h>
2148 +#include <asm/arch/it8712.h>
2149 +#include <linux/init.h>
2150 +#include <asm/arch/hardware.h>
2151 +
2152 +#ifndef TRUE
2153 +#define TRUE 1
2154 +#endif
2155 +
2156 +#ifndef FALSE
2157 +#define FALSE 0
2158 +#endif
2159 +
2160 +
2161 +// MB PnP configuration register
2162 +#define LPC_KEY_ADDR (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2e)
2163 +#define LPC_DATA_ADDR (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2f)
2164 +
2165 +#define LPC_BUS_CTRL *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 0)
2166 +#define LPC_BUS_STATUS *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 2)
2167 +#define LPC_SERIAL_IRQ_CTRL *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 4)
2168 +
2169 +int it8712_exist;
2170 +
2171 +static void LPCEnterMBPnP(void)
2172 +{
2173 + int i;
2174 + unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
2175 +
2176 + for (i = 0; i<4; i++)
2177 + outb(key[i], LPC_KEY_ADDR);
2178 +
2179 +}
2180 +
2181 +static void LPCExitMBPnP(void)
2182 +{
2183 + outb(0x02, LPC_KEY_ADDR);
2184 + outb(0x02, LPC_DATA_ADDR);
2185 +}
2186 +
2187 +void LPCSetConfig(char LdnNumber, char Index, char data)
2188 +{
2189 + LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
2190 + outb(0x07, LPC_KEY_ADDR);
2191 + outb(LdnNumber, LPC_DATA_ADDR);
2192 + outb(Index, LPC_KEY_ADDR);
2193 + outb(data, LPC_DATA_ADDR);
2194 + LPCExitMBPnP();
2195 +}
2196 +
2197 +char LPCGetConfig(char LdnNumber, char Index)
2198 +{
2199 + char rtn;
2200 +
2201 + LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
2202 + outb(0x07, LPC_KEY_ADDR);
2203 + outb(LdnNumber, LPC_DATA_ADDR);
2204 + outb(Index, LPC_KEY_ADDR);
2205 + rtn = inb(LPC_DATA_ADDR);
2206 + LPCExitMBPnP();
2207 + return rtn;
2208 +}
2209 +
2210 +static int SearchIT8712(void)
2211 +{
2212 + unsigned char Id1, Id2;
2213 + unsigned short Id;
2214 +
2215 + LPCEnterMBPnP();
2216 + outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
2217 + Id1 = inb(LPC_DATA_ADDR);
2218 + outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
2219 + Id2 = inb(LPC_DATA_ADDR);
2220 + Id = (Id1 << 8) | Id2;
2221 + LPCExitMBPnP();
2222 + if (Id == 0x8712)
2223 + return TRUE;
2224 + else
2225 + return FALSE;
2226 +}
2227 +
2228 +int InitLPCInterface(void)
2229 +{
2230 + LPC_BUS_CTRL = 0xc0;
2231 + LPC_SERIAL_IRQ_CTRL = 0xc0;
2232 + mdelay(1); // wait for 1 serial IRQ cycle
2233 + LPC_SERIAL_IRQ_CTRL = 0x80;
2234 + it8712_exist = SearchIT8712();
2235 + printk("IT8712 %s exist\n", it8712_exist?"":"doesn't");
2236 + return 0;
2237 +}
2238 +
2239 +//__initcall(InitLPCInterface);
2240 --- /dev/null
2241 +++ b/arch/arm/mach-sl2312/mm.c
2242 @@ -0,0 +1,80 @@
2243 +/*
2244 + * linux/arch/arm/mach-epxa10db/mm.c
2245 + *
2246 + * MM routines for Altera'a Epxa10db board
2247 + *
2248 + * Copyright (C) 2001 Altera Corporation
2249 + *
2250 + * This program is free software; you can redistribute it and/or modify
2251 + * it under the terms of the GNU General Public License as published by
2252 + * the Free Software Foundation; either version 2 of the License, or
2253 + * (at your option) any later version.
2254 + *
2255 + * This program is distributed in the hope that it will be useful,
2256 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2257 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2258 + * GNU General Public License for more details.
2259 + *
2260 + * You should have received a copy of the GNU General Public License
2261 + * along with this program; if not, write to the Free Software
2262 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2263 + */
2264 +#include <linux/sched.h>
2265 +#include <linux/mm.h>
2266 +#include <linux/init.h>
2267 +
2268 +#include <asm/hardware.h>
2269 +#include <asm/io.h>
2270 +#include <asm/pgtable.h>
2271 +#include <asm/page.h>
2272 +#include <asm/sizes.h>
2273 +
2274 +#include <asm/mach/map.h>
2275 +
2276 +/* Page table mapping for I/O region */
2277 +static struct map_desc sl2312_io_desc[] __initdata = {
2278 +#ifdef CONFIG_GEMINI_IPI
2279 +{__phys_to_virt(CPU_1_MEM_BASE), __phys_to_pfn(CPU_1_MEM_BASE), SZ_64M, MT_MEMORY},
2280 +#endif
2281 +{IO_ADDRESS(SL2312_SRAM_BASE), __phys_to_pfn(SL2312_SRAM_BASE), SZ_512K, MT_DEVICE},
2282 +{IO_ADDRESS(SL2312_DRAM_CTRL_BASE), __phys_to_pfn(SL2312_DRAM_CTRL_BASE), SZ_512K, MT_DEVICE},
2283 +{IO_ADDRESS(SL2312_GLOBAL_BASE), __phys_to_pfn(SL2312_GLOBAL_BASE), SZ_512K, MT_DEVICE},
2284 +{IO_ADDRESS(SL2312_WAQTCHDOG_BASE), __phys_to_pfn(SL2312_WAQTCHDOG_BASE), SZ_512K, MT_DEVICE},
2285 +{IO_ADDRESS(SL2312_UART_BASE), __phys_to_pfn(SL2312_UART_BASE), SZ_512K, MT_DEVICE},
2286 +{IO_ADDRESS(SL2312_TIMER_BASE), __phys_to_pfn(SL2312_TIMER_BASE), SZ_512K, MT_DEVICE},
2287 +{IO_ADDRESS(SL2312_LCD_BASE), __phys_to_pfn(SL2312_LCD_BASE), SZ_512K, MT_DEVICE},
2288 +{IO_ADDRESS(SL2312_RTC_BASE), __phys_to_pfn(SL2312_RTC_BASE), SZ_512K, MT_DEVICE},
2289 +{IO_ADDRESS(SL2312_SATA_BASE), __phys_to_pfn(SL2312_SATA_BASE), SZ_512K, MT_DEVICE},
2290 +{IO_ADDRESS(SL2312_LPC_HOST_BASE), __phys_to_pfn(SL2312_LPC_HOST_BASE), SZ_512K, MT_DEVICE},
2291 +{IO_ADDRESS(SL2312_LPC_IO_BASE), __phys_to_pfn(SL2312_LPC_IO_BASE), SZ_512K, MT_DEVICE},
2292 +{IO_ADDRESS(SL2312_INTERRUPT_BASE), __phys_to_pfn(SL2312_INTERRUPT_BASE), SZ_512K, MT_DEVICE},
2293 +{IO_ADDRESS(SL2312_INTERRUPT1_BASE), __phys_to_pfn(SL2312_INTERRUPT1_BASE), SZ_512K, MT_DEVICE},
2294 +{IO_ADDRESS(SL2312_SSP_CTRL_BASE), __phys_to_pfn(SL2312_SSP_CTRL_BASE), SZ_512K, MT_DEVICE},
2295 +{IO_ADDRESS(SL2312_POWER_CTRL_BASE), __phys_to_pfn(SL2312_POWER_CTRL_BASE), SZ_512K, MT_DEVICE},
2296 +{IO_ADDRESS(SL2312_CIR_BASE), __phys_to_pfn(SL2312_CIR_BASE), SZ_512K, MT_DEVICE},
2297 +{IO_ADDRESS(SL2312_GPIO_BASE), __phys_to_pfn(SL2312_GPIO_BASE), SZ_512K, MT_DEVICE},
2298 +{IO_ADDRESS(SL2312_GPIO_BASE1), __phys_to_pfn(SL2312_GPIO_BASE1), SZ_512K, MT_DEVICE},
2299 +{IO_ADDRESS(SL2312_GPIO_BASE2), __phys_to_pfn(SL2312_GPIO_BASE2), SZ_512K, MT_DEVICE},
2300 +{IO_ADDRESS(SL2312_PCI_IO_BASE), __phys_to_pfn(SL2312_PCI_IO_BASE), SZ_512K, MT_DEVICE},
2301 +{IO_ADDRESS(SL2312_PCI_MEM_BASE), __phys_to_pfn(SL2312_PCI_MEM_BASE), SZ_512K, MT_DEVICE},
2302 +#ifdef CONFIG_NET_SL351X
2303 +{IO_ADDRESS(SL2312_TOE_BASE), __phys_to_pfn(SL2312_TOE_BASE) , SZ_512K, MT_DEVICE},
2304 +#endif
2305 +{IO_ADDRESS(SL2312_GMAC0_BASE), __phys_to_pfn(SL2312_GMAC0_BASE), SZ_512K, MT_DEVICE},
2306 +{IO_ADDRESS(SL2312_GMAC1_BASE), __phys_to_pfn(SL2312_GMAC1_BASE), SZ_512K, MT_DEVICE},
2307 +{IO_ADDRESS(SL2312_SECURITY_BASE), __phys_to_pfn(SL2312_SECURITY_BASE), SZ_512K, MT_DEVICE},
2308 +{IO_ADDRESS(SL2312_IDE0_BASE), __phys_to_pfn(SL2312_IDE0_BASE), SZ_512K, MT_DEVICE},
2309 +{IO_ADDRESS(SL2312_IDE1_BASE), __phys_to_pfn(SL2312_IDE1_BASE), SZ_512K, MT_DEVICE},
2310 +{IO_ADDRESS(SL2312_RAID_BASE), __phys_to_pfn(SL2312_RAID_BASE), SZ_512K, MT_DEVICE},
2311 +{IO_ADDRESS(SL2312_FLASH_CTRL_BASE), __phys_to_pfn(SL2312_FLASH_CTRL_BASE), SZ_512K, MT_DEVICE},
2312 +{IO_ADDRESS(SL2312_DRAM_CTRL_BASE), __phys_to_pfn(SL2312_DRAM_CTRL_BASE), SZ_512K, MT_DEVICE},
2313 +{IO_ADDRESS(SL2312_GENERAL_DMA_BASE), __phys_to_pfn(SL2312_GENERAL_DMA_BASE), SZ_512K, MT_DEVICE},
2314 +{IO_ADDRESS(SL2312_USB0_BASE), __phys_to_pfn(SL2312_USB_BASE), SZ_512K, MT_DEVICE},
2315 +{IO_ADDRESS(SL2312_USB1_BASE), __phys_to_pfn(SL2312_USB1_BASE), SZ_512K, MT_DEVICE},
2316 +{FLASH_VADDR(SL2312_FLASH_BASE), __phys_to_pfn(SL2312_FLASH_BASE), SZ_16M, MT_DEVICE},
2317 +};
2318 +
2319 +void __init sl2312_map_io(void)
2320 +{
2321 + iotable_init(sl2312_io_desc, ARRAY_SIZE(sl2312_io_desc));
2322 +}
2323 --- /dev/null
2324 +++ b/arch/arm/mach-sl2312/pci.c
2325 @@ -0,0 +1,359 @@
2326 +/*
2327 + * linux/arch/arm/mach-sl2312/pci_sl2312.c
2328 + *
2329 + * PCI functions for sl2312 host PCI bridge
2330 + *
2331 + * Copyright (C) 2003 StorLink Corp.
2332 + *
2333 + * This program is free software; you can redistribute it and/or modify
2334 + * it under the terms of the GNU General Public License as published by
2335 + * the Free Software Foundation; either version 2 of the License, or
2336 + * (at your option) any later version.
2337 + *
2338 + * This program is distributed in the hope that it will be useful,
2339 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2340 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2341 + * GNU General Public License for more details.
2342 + *
2343 + * You should have received a copy of the GNU General Public License
2344 + * along with this program; if not, write to the Free Software
2345 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2346 + */
2347 +#include <linux/sched.h>
2348 +#include <linux/kernel.h>
2349 +#include <linux/pci.h>
2350 +#include <linux/ptrace.h>
2351 +#include <linux/slab.h>
2352 +#include <linux/ioport.h>
2353 +#include <linux/interrupt.h>
2354 +#include <linux/spinlock.h>
2355 +#include <linux/init.h>
2356 +
2357 +#include <asm/sizes.h>
2358 +#include <asm/hardware.h>
2359 +#include <asm/irq.h>
2360 +#include <asm/system.h>
2361 +#include <asm/mach/pci.h>
2362 +#include <asm/mach/irq.h>
2363 +#include <asm/mach-types.h>
2364 +
2365 +#include <asm/arch/pci.h>
2366 +
2367 +//#define DEBUG
2368 +
2369 +// sl2312 PCI bridge access routines
2370 +
2371 +#define PCI_IOSIZE_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE)))
2372 +#define PCI_PROT_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x04))
2373 +#define PCI_CTRL_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x08))
2374 +#define PCI_SOFTRST_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x10))
2375 +#define PCI_CONFIG_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x28))
2376 +#define PCI_DATA_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x2C))
2377 +
2378 +static spinlock_t sl2312_pci_lock = SPIN_LOCK_UNLOCKED;
2379 +// for initialize PCI devices
2380 +struct resource pci_ioport_resource = {
2381 + .name = "PCI I/O Space",
2382 + .start = IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x100,
2383 + .end = IO_ADDRESS(SL2312_PCI_IO_BASE) + SZ_512K - 1,
2384 + .flags = IORESOURCE_IO,
2385 +};
2386 +struct resource pci_iomem_resource = {
2387 + .name = "PCI Mem Space",
2388 + .start = SL2312_PCI_MEM_BASE,
2389 + .end = SL2312_PCI_MEM_BASE + SZ_128M - 1,
2390 + .flags = IORESOURCE_MEM,
2391 +};
2392 +
2393 +static int sl2312_read_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 *val)
2394 +{
2395 + unsigned long addr,data;
2396 + unsigned long flags;
2397 +
2398 + spin_lock_irqsave(&sl2312_pci_lock, flags);
2399 + addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3);
2400 + PCI_CONFIG_REG = addr;
2401 + data = PCI_DATA_REG;
2402 +
2403 + switch (size) {
2404 + case 1:
2405 + *val = (u8) (data >> ((where & 0x03) * 8));
2406 + break;
2407 + case 2:
2408 + *val = (u16) (data >> ((where & 0x02) * 8));
2409 + break;
2410 + case 4:
2411 + *val = data;
2412 + if ((where >= 0x10) && (where <= 0x24)) {
2413 + if ((*val & 0xfff00000) == SL2312_PCI_IO_BASE) {
2414 + *val &= 0x000fffff;
2415 + *val |= IO_ADDRESS(SL2312_PCI_IO_BASE);
2416 + }
2417 + }
2418 + break;
2419 + }
2420 + spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2421 +// printk("READ==>slot=%d fn=%d where=%d value=%x\n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,*val);
2422 + return PCIBIOS_SUCCESSFUL;
2423 +}
2424 +
2425 +static int sl2312_write_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 val)
2426 +{
2427 + unsigned long addr,data;
2428 + unsigned long flags;
2429 +
2430 + spin_lock_irqsave(&sl2312_pci_lock, flags);
2431 + addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3);
2432 + PCI_CONFIG_REG = addr;
2433 + data = PCI_DATA_REG;
2434 +
2435 + switch (size) {
2436 + case 1:
2437 + data &= ~(0xff << ((where & 0x03) * 8));
2438 + data |= (val << ((where & 0x03) * 8));
2439 + PCI_DATA_REG = data;
2440 + break;
2441 + case 2:
2442 + data &= ~(0xffff << ((where & 0x02) * 8));
2443 + data |= (val << ((where & 0x02) * 8));
2444 + PCI_DATA_REG = data;
2445 + break;
2446 + case 4:
2447 + if ((where >= 0x10) && (where <= 0x24)) {
2448 + if ((val & 0xfff00000) == IO_ADDRESS(SL2312_PCI_IO_BASE)) {
2449 + val &= 0x000fffff;
2450 + val |= SL2312_PCI_IO_BASE;
2451 + }
2452 + }
2453 + PCI_DATA_REG = val;
2454 + break;
2455 + }
2456 + spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2457 +
2458 +// printk("WRITE==> slot=%d fn=%d where=%d value=%x \n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,val);
2459 + return PCIBIOS_SUCCESSFUL;
2460 +}
2461 +
2462 +static struct pci_ops sl2312_pci_ops = {
2463 + .read = sl2312_read_config,
2464 + .write = sl2312_write_config,
2465 +};
2466 +
2467 +
2468 +int __init sl2312_pci_setup_resources(struct resource **resource)
2469 +{
2470 + PCI_IOSIZE_REG = 0; // 1M IO size
2471 + PCI_CTRL_REG = 0x06;
2472 +
2473 + resource[0] = &pci_ioport_resource;
2474 + resource[1] = &pci_iomem_resource;
2475 + resource[2] = NULL;
2476 +
2477 + return 1;
2478 +}
2479 +
2480 +//static int sl2312_pci_fault(unsigned long addr, struct pt_regs *regs)
2481 +//{
2482 +// return 1;
2483 +//}
2484 +
2485 +
2486 +/**********************************************************************
2487 + * MASK(disable) PCI interrupt
2488 + * 0: PCI INTA, 1: PCI INTB, ... // for Linux interrupt routing
2489 + * 16: PERR // for PCI module internal use
2490 + * 17: SERR,.. respect to PCI CTRL2 REG
2491 + **********************************************************************/
2492 +void sl2312_pci_mask_irq(unsigned int irq)
2493 +{
2494 + struct pci_bus bus;
2495 + unsigned int tmp;
2496 +
2497 + bus.number = 0;
2498 + sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2499 + if (irq < 16) { // for linux int routing
2500 + tmp &= ~(1 << (irq + 16 + 6));
2501 + }
2502 + else {
2503 + tmp &= ~(1 << irq);
2504 + }
2505 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2506 +}
2507 +
2508 +/* UNMASK(enable) PCI interrupt */
2509 +void sl2312_pci_unmask_irq(unsigned int irq)
2510 +{
2511 + struct pci_bus bus;
2512 + unsigned int tmp;
2513 +
2514 + bus.number = 0;
2515 + sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2516 + if (irq < 16) { // for linux int routing
2517 + tmp |= (1 << (irq + 16 + 6));
2518 + }
2519 + else {
2520 + tmp |= (1 << irq);
2521 + }
2522 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2523 +}
2524 +
2525 +/* Get PCI interrupt source */
2526 +int sl2312_pci_get_int_src(void)
2527 +{
2528 + struct pci_bus bus;
2529 + unsigned int tmp=0;
2530 +
2531 + bus.number = 0;
2532 + sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2533 + if (tmp & (1 << 28)) { // PCI INTA
2534 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2535 + return IRQ_PCI_INTA;
2536 + }
2537 + if (tmp & (1 << 29)) { // PCI INTB
2538 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2539 + return IRQ_PCI_INTB;
2540 + }
2541 + if (tmp & (1 << 30)) { // PCI INTC
2542 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2543 + return IRQ_PCI_INTC;
2544 + }
2545 + if (tmp & (1 << 31)) { // PCI INTD
2546 + sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2547 + return IRQ_PCI_INTD;
2548 + }
2549 + // otherwise, it should be a PCI error
2550 + return IRQ_PCI;
2551 +}
2552 +
2553 +static irqreturn_t sl2312_pci_irq(int irq, void *devid)
2554 +{
2555 + struct irq_desc *desc;
2556 + struct irqaction *action;
2557 + int retval = 0;
2558 +
2559 + return 1;
2560 +
2561 + irq = sl2312_pci_get_int_src();
2562 + desc = &irq_desc[irq];
2563 + action = desc->action;
2564 + do {
2565 + retval |= action->handler(irq, devid);
2566 + action = action->next;
2567 + } while (action);
2568 +
2569 + return 1;
2570 +}
2571 +
2572 +//extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);
2573 +
2574 +void __init sl2312_pci_preinit(void)
2575 +{
2576 + struct pci_bus bus;
2577 + unsigned long flags;
2578 + unsigned int temp;
2579 + int ret;
2580 +
2581 + /*
2582 + * Hook in our fault handler for PCI errors
2583 + */
2584 +// external_fault = sl2312_pci_fault;
2585 +
2586 + spin_lock_irqsave(&sl2312_pci_lock, flags);
2587 +
2588 + /*
2589 + * Grab the PCI interrupt.
2590 + */
2591 + ret = request_irq(IRQ_PCI, sl2312_pci_irq, 0, "sl2312 pci int", NULL);
2592 + if (ret)
2593 + printk(KERN_ERR "PCI: unable to grab PCI error "
2594 + "interrupt: %d\n", ret);
2595 +
2596 + spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2597 +
2598 + // setup pci bridge
2599 + bus.number = 0; /* device 0, function 0 */
2600 + temp = (SL2312_PCI_DMA_MEM1_BASE & 0xfff00000) | (SL2312_PCI_DMA_MEM1_SIZE << 16);
2601 + sl2312_write_config(&bus, 0, SL2312_PCI_MEM1_BASE_SIZE, 4, temp);
2602 +}
2603 +
2604 +/*
2605 + * No swizzle on SL2312
2606 + */
2607 +static u8 __init sl2312_pci_swizzle(struct pci_dev *dev, u8 *pinp)
2608 +{
2609 + return PCI_SLOT(dev->devfn);
2610 +}
2611 +
2612 +/*
2613 + * map the specified device/slot/pin to an IRQ. This works out such
2614 + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
2615 + */
2616 +static int __init sl2312_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
2617 +{
2618 + int intnr = ((slot + (pin - 1)) & 3) + 4; /* the IRQ number of PCI bridge */
2619 +
2620 + // printk("%s : slot = %d pin = %d \n",__func__,slot,pin);
2621 + switch (slot)
2622 + {
2623 + case 12:
2624 + if (pin==1)
2625 + {
2626 + intnr = 3;
2627 + }
2628 + else
2629 + {
2630 + intnr = 0;
2631 + }
2632 + break;
2633 + case 11:
2634 + intnr = (2 + (pin - 1)) & 3;
2635 + break;
2636 + case 10:
2637 + intnr = (1 + (pin - 1)) & 3;
2638 + break;
2639 + case 9:
2640 + intnr = (pin - 1) & 3;
2641 + break;
2642 + }
2643 +// if (slot == 10)
2644 +// intnr = (1 + (pin - 1)) & 3;
2645 +// else if (slot == 9)
2646 +// intnr = (pin - 1) & 3;
2647 + return (IRQ_PCI_INTA + intnr);
2648 +}
2649 +
2650 +struct pci_bus * __init sl2312_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
2651 +{
2652 + return (pci_scan_bus(0, &sl2312_pci_ops, sysdata));
2653 +
2654 +}
2655 +
2656 +int __init sl2312_pci_setup(int nr, struct pci_sys_data *sys)
2657 +{
2658 + int ret = 0;
2659 +
2660 + if (nr == 0) {
2661 + ret = sl2312_pci_setup_resources(sys->resource);
2662 + }
2663 +
2664 + return ret;
2665 +}
2666 +
2667 +
2668 +struct hw_pci sl2312_pci __initdata = {
2669 + .setup = sl2312_pci_setup,
2670 + .preinit = sl2312_pci_preinit,
2671 + .nr_controllers = 1,
2672 + .swizzle = sl2312_pci_swizzle,
2673 + .map_irq = sl2312_pci_map_irq,
2674 + .scan = sl2312_pci_scan_bus,
2675 +};
2676 +
2677 +static int __init sl2312_pci_init(void)
2678 +{
2679 + if (machine_is_sl2312())
2680 + pci_common_init(&sl2312_pci);
2681 + return 0;
2682 +}
2683 +
2684 +subsys_initcall(sl2312_pci_init);
2685 --- /dev/null
2686 +++ b/arch/arm/mach-sl2312/sl2312-otg-1.c
2687 @@ -0,0 +1,64 @@
2688 +/*
2689 + * linux/arch/arm/mach-pxa/sl2312.c
2690 + *
2691 + * Author: Nicolas Pitre
2692 + * Created: Nov 05, 2002
2693 + * Copyright: MontaVista Software Inc.
2694 + *
2695 + * Code specific to sl2312 aka Bulverde.
2696 + *
2697 + * This program is free software; you can redistribute it and/or modify
2698 + * it under the terms of the GNU General Public License version 2 as
2699 + * published by the Free Software Foundation.
2700 + */
2701 +#include <linux/module.h>
2702 +#include <linux/kernel.h>
2703 +#include <linux/init.h>
2704 +#include <linux/pm.h>
2705 +#include <linux/device.h>
2706 +#include "asm/arch/sl2312.h"
2707 +#include "asm/arch/irqs.h"
2708 +#include <asm/hardware.h>
2709 +#include <asm/irq.h>
2710 +#include <linux/platform_device.h>
2711 +
2712 +/*
2713 + * device registration specific to sl2312.
2714 + */
2715 +
2716 +static u64 sl2312_dmamask_1 = 0xffffffffUL;
2717 +
2718 +static struct resource sl2312_otg_resources_1[] = {
2719 + [0] = {
2720 + .start = 0x69000000,
2721 + .end = 0x69000fff,
2722 + .flags = IORESOURCE_MEM,
2723 + },
2724 + [1] = {
2725 + .start = IRQ_USB1,
2726 + .end = IRQ_USB1,
2727 + .flags = IORESOURCE_IRQ,
2728 + },
2729 +};
2730 +
2731 +static struct platform_device ehci_1_device = {
2732 + .name = "ehci-hcd-FOTG2XX",
2733 + .id = -1,
2734 + .dev = {
2735 + .dma_mask = &sl2312_dmamask_1,
2736 + .coherent_dma_mask = 0xffffffff,
2737 + },
2738 + .num_resources = ARRAY_SIZE(sl2312_otg_resources_1),
2739 + .resource = sl2312_otg_resources_1,
2740 +};
2741 +
2742 +static struct platform_device *devices[] __initdata = {
2743 + &ehci_1_device,
2744 +};
2745 +
2746 +static int __init sl2312_1_init(void)
2747 +{
2748 + return platform_add_devices(devices, ARRAY_SIZE(devices));
2749 +}
2750 +
2751 +subsys_initcall(sl2312_1_init);
2752 --- /dev/null
2753 +++ b/arch/arm/mach-sl2312/sl2312-otg.c
2754 @@ -0,0 +1,87 @@
2755 +/*
2756 + * linux/arch/arm/mach-pxa/sl2312.c
2757 + *
2758 + * Author: Nicolas Pitre
2759 + * Created: Nov 05, 2002
2760 + * Copyright: MontaVista Software Inc.
2761 + *
2762 + * Code specific to sl2312 aka Bulverde.
2763 + *
2764 + * This program is free software; you can redistribute it and/or modify
2765 + * it under the terms of the GNU General Public License version 2 as
2766 + * published by the Free Software Foundation.
2767 + */
2768 +#include <linux/module.h>
2769 +#include <linux/kernel.h>
2770 +#include <linux/init.h>
2771 +#include <linux/pm.h>
2772 +#include <linux/device.h>
2773 +#include "asm/arch/sl2312.h"
2774 +#include "asm/arch/irqs.h"
2775 +#include <asm/hardware.h>
2776 +#include <asm/irq.h>
2777 +#include <linux/platform_device.h>
2778 +
2779 +/*
2780 + * device registration specific to sl2312.
2781 + */
2782 +
2783 +static u64 sl2312_dmamask = 0xffffffffUL;
2784 +
2785 +static struct resource sl2312_otg_resources_1[] = {
2786 + [0] = {
2787 + .start = 0x68000000,
2788 + .end = 0x68000fff,
2789 + .flags = IORESOURCE_MEM,
2790 + },
2791 + [1] = {
2792 + .start = IRQ_USB0,
2793 + .end = IRQ_USB0,
2794 + .flags = IORESOURCE_IRQ,
2795 + },
2796 +};
2797 +static struct resource sl2312_otg_resources_2[] = {
2798 + [2] = {
2799 + .start = 0x69000000,
2800 + .end = 0x69000fff,
2801 + .flags = IORESOURCE_MEM,
2802 + },
2803 + [3] = {
2804 + .start = IRQ_USB1,
2805 + .end = IRQ_USB1,
2806 + .flags = IORESOURCE_IRQ,
2807 + },
2808 +};
2809 +
2810 +static struct platform_device ehci_device_1 = {
2811 + .name = "ehci-hcd-FOTG2XX",
2812 + .id = 1,
2813 + .dev = {
2814 + .dma_mask = &sl2312_dmamask,
2815 + .coherent_dma_mask = 0xffffffff,
2816 + },
2817 + .num_resources = ARRAY_SIZE(sl2312_otg_resources_1),
2818 + .resource = sl2312_otg_resources_1,
2819 +};
2820 +
2821 +static struct platform_device ehci_device_2 = {
2822 + .name = "ehci-hcd-FOTG2XX",
2823 + .id = 2,
2824 + .dev = {
2825 + .dma_mask = &sl2312_dmamask,
2826 + .coherent_dma_mask = 0xffffffff,
2827 + },
2828 + .num_resources = ARRAY_SIZE(sl2312_otg_resources_2),
2829 + .resource = sl2312_otg_resources_2,
2830 +};
2831 +
2832 +static struct platform_device *devices[] __initdata = {
2833 + &ehci_device_1, /* &ehci_device_2, */
2834 +};
2835 +
2836 +static int __init sl2312_init(void)
2837 +{
2838 + return platform_add_devices(devices, ARRAY_SIZE(devices));
2839 +}
2840 +
2841 +subsys_initcall(sl2312_init);
2842 --- /dev/null
2843 +++ b/arch/arm/mach-sl2312/sl3516_device.c
2844 @@ -0,0 +1,89 @@
2845 +/*
2846 + * linux/arch/arm/mach-2312/sl3516_device.c
2847 + *
2848 + * Author: Nicolas Pitre
2849 + * Created: Nov 05, 2002
2850 + * Copyright: MontaVista Software Inc.
2851 + *
2852 + * Code specific to sl2312 aka Bulverde.
2853 + *
2854 + * This program is free software; you can redistribute it and/or modify
2855 + * it under the terms of the GNU General Public License version 2 as
2856 + * published by the Free Software Foundation.
2857 + */
2858 +#include <linux/module.h>
2859 +#include <linux/kernel.h>
2860 +#include <linux/init.h>
2861 +#include <linux/pm.h>
2862 +#include <linux/device.h>
2863 +#include <linux/platform_device.h>
2864 +#include "asm/arch/sl2312.h"
2865 +#include "asm/arch/irqs.h"
2866 +#include <asm/hardware.h>
2867 +#include <asm/irq.h>
2868 +
2869 +/*
2870 + * device registration specific to sl2312.
2871 + */
2872 +
2873 +static u64 sl3516_dmamask = 0xffffffffUL;
2874 +
2875 +static struct resource sl3516_sata_resources[] = {
2876 + [0] = {
2877 + .start = 0x63400000,
2878 + .end = 0x63400040,
2879 + .flags = IORESOURCE_MEM,
2880 + },
2881 + [1] = {
2882 + .start = IRQ_IDE1,
2883 + .end = IRQ_IDE1,
2884 + .flags = IORESOURCE_IRQ,
2885 + },
2886 +};
2887 +
2888 +static struct platform_device sata_device = {
2889 + .name = "lepus-sata",
2890 + .id = -1,
2891 + .dev = {
2892 + .dma_mask = &sl3516_dmamask,
2893 + .coherent_dma_mask = 0xffffffff,
2894 + },
2895 + .num_resources = ARRAY_SIZE(sl3516_sata_resources),
2896 + .resource = sl3516_sata_resources,
2897 +};
2898 +
2899 +static struct resource sl3516_sata0_resources[] = {
2900 + [0] = {
2901 + .start = 0x63000000,
2902 + .end = 0x63000040,
2903 + .flags = IORESOURCE_MEM,
2904 + },
2905 + [1] = {
2906 + .start = IRQ_IDE0,
2907 + .end = IRQ_IDE0,
2908 + .flags = IORESOURCE_IRQ,
2909 + },
2910 +};
2911 +
2912 +static struct platform_device sata0_device = {
2913 + .name = "lepus-sata0",
2914 + .id = -1,
2915 + .dev = {
2916 + .dma_mask = &sl3516_dmamask,
2917 + .coherent_dma_mask = 0xffffffff,
2918 + },
2919 + .num_resources = ARRAY_SIZE(sl3516_sata0_resources),
2920 + .resource = sl3516_sata0_resources,
2921 +};
2922 +
2923 +static struct platform_device *sata_devices[] __initdata = {
2924 + &sata_device,
2925 + &sata0_device,
2926 +};
2927 +
2928 +static int __init sl3516_init(void)
2929 +{
2930 + return platform_add_devices(sata_devices, ARRAY_SIZE(sata_devices));
2931 +}
2932 +
2933 +subsys_initcall(sl3516_init);
2934 --- /dev/null
2935 +++ b/arch/arm/mach-sl2312/time.c
2936 @@ -0,0 +1,134 @@
2937 +/*
2938 + * linux/include/asm-arm/arch-epxa10db/time.h
2939 + *
2940 + * Copyright (C) 2001 Altera Corporation
2941 + *
2942 + * This program is free software; you can redistribute it and/or modify
2943 + * it under the terms of the GNU General Public License as published by
2944 + * the Free Software Foundation; either version 2 of the License, or
2945 + * (at your option) any later version.
2946 + *
2947 + * This program is distributed in the hope that it will be useful,
2948 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2949 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2950 + * GNU General Public License for more details.
2951 + *
2952 + * You should have received a copy of the GNU General Public License
2953 + * along with this program; if not, write to the Free Software
2954 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2955 + */
2956 +#include <linux/interrupt.h>
2957 +#include <linux/irq.h>
2958 +#include <asm/io.h>
2959 +#include <asm/system.h>
2960 +#include <asm/leds.h>
2961 +#include <asm/arch/hardware.h>
2962 +#include <asm/mach/time.h>
2963 +#define TIMER_TYPE (volatile unsigned int*)
2964 +#include <asm/arch/timer.h>
2965 +// #define FIQ_PLUS 1
2966 +
2967 +
2968 +/*
2969 + * IRQ handler for the timer
2970 + */
2971 +static irqreturn_t sl2312_timer_interrupt(int irq, void *dev_id)
2972 +{
2973 +// unsigned int led;
2974 + // ...clear the interrupt
2975 +#ifdef FIQ_PLUS
2976 + *((volatile unsigned int *)FIQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
2977 +#else
2978 + *((volatile unsigned int *)IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
2979 +#endif
2980 +
2981 +#if 0
2982 + if(!(jiffies % HZ))
2983 + {
2984 + led = jiffies / HZ;
2985 +// printk("ticks %x \n", led);
2986 + }
2987 + do_leds();
2988 + do_timer(regs);
2989 + do_profile(regs);
2990 +#endif
2991 + timer_tick();
2992 + return IRQ_HANDLED;
2993 +}
2994 +
2995 +static struct irqaction sl2312_timer_irq = {
2996 + .name = "SL2312 Timer Tick",
2997 + .flags = IRQF_DISABLED | IRQF_TIMER,
2998 + .handler = sl2312_timer_interrupt,
2999 +};
3000 +
3001 +unsigned long sl2312_gettimeoffset (void)
3002 +{
3003 + return 0L;
3004 +}
3005 +
3006 +/*
3007 + * Set up timer interrupt, and return the current time in seconds.
3008 + */
3009 +void __init sl2312_time_init(void)
3010 +{
3011 + // For clock rate adjusting
3012 + unsigned int tick_rate=0;
3013 +
3014 +#ifdef CONFIG_SL3516_ASIC
3015 + unsigned int clock_rate_base = 130000000;
3016 + unsigned int reg_v=0;
3017 +
3018 + //--> Add by jason for clock adjust
3019 + reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_STATUS)));
3020 + reg_v >>= 15;
3021 + tick_rate = (clock_rate_base + (reg_v & 0x07)*10000000);
3022 +
3023 + // FPGA use AHB bus tick rate
3024 + printk("Bus: %dMHz",tick_rate/1000000);
3025 +
3026 + tick_rate /= 6; // APB bus run AHB*(1/6)
3027 +
3028 + switch((reg_v>>3)&3){
3029 + case 0: printk("(1/1)\n") ;
3030 + break;
3031 + case 1: printk("(3/2)\n") ;
3032 + break;
3033 + case 2: printk("(24/13)\n") ;
3034 + break;
3035 + case 3: printk("(2/1)\n") ;
3036 + break;
3037 + }
3038 + //<--
3039 +#else
3040 + printk("Bus: %dMHz(1/1)\n",CLOCK_TICK_RATE/1000000); // FPGA use 20MHz
3041 + tick_rate = CLOCK_TICK_RATE;
3042 +#endif
3043 +
3044 +
3045 + /*
3046 + * Make irqs happen for the system timer
3047 + */
3048 + // initialize timer interrupt
3049 + // low active and edge trigger
3050 +#ifdef FIQ_PLUS
3051 + *((volatile unsigned int *)FIQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
3052 + *((volatile unsigned int *)FIQ_LEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
3053 + setup_irq(IRQ_TIMER1, &sl2312_timer_irq);
3054 + /* Start the timer */
3055 + *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ);
3056 + *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ);
3057 + *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_1_CR_ENABLE_MSK|TIMER_1_CR_INT_MSK);
3058 +#else
3059 + *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
3060 + *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
3061 + setup_irq(IRQ_TIMER2, &sl2312_timer_irq);
3062 + /* Start the timer */
3063 + *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ);
3064 + *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ);
3065 + *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_2_CR_ENABLE_MSK|TIMER_2_CR_INT_MSK);
3066 +#endif
3067 +
3068 +}
3069 +
3070 +
3071 --- /dev/null
3072 +++ b/arch/arm/mach-sl2312/xor.c
3073 @@ -0,0 +1,1200 @@
3074 +/*
3075 + * arch/arm/mach-sl2312/xor.c
3076 + *
3077 + * Support functions for the Gemini Soc. This is
3078 + * a HW XOR unit that is specifically designed for use with RAID5
3079 + * applications. This driver provides an interface that is used by
3080 + * the Linux RAID stack.
3081 + *
3082 + * Original Author: Jason Lee<jason@storlink.com.tw>
3083 + *
3084 + * Contributors:Sanders<sanders@storlink.com.tw>
3085 + Jason Lee<jason@storlink.com.tw>
3086 + *
3087 + *
3088 + * Maintainer: Jason Lee<jason@storlink.com.tw>
3089 + *
3090 + * Copyright (C) 2005 Storlink Corporation
3091 + *
3092 + * This program is free software; you can redistribute it and/or modify
3093 + * it under the terms of the GNU General Public License version 2 as
3094 + * published by the Free Software Foundation.
3095 + *
3096 + *
3097 + * History: (06/25/2005, DJ) Initial Creation
3098 + *
3099 + * Versing 1.0.0 Initial version
3100 + */
3101 +
3102 +#include <linux/types.h>
3103 +#include <linux/init.h>
3104 +#include <linux/sched.h>
3105 +#include <linux/spinlock.h>
3106 +#include <linux/slab.h>
3107 +#include <linux/errno.h>
3108 +#include <linux/interrupt.h>
3109 +#include <linux/sched.h>
3110 +#include <linux/wait.h>
3111 +#include <linux/list.h>
3112 +#include <linux/pci.h>
3113 +#include <linux/delay.h>
3114 +#include <linux/dma-mapping.h>
3115 +#include <linux/mm.h>
3116 +#include <asm/irq.h>
3117 +#include <asm/delay.h>
3118 +#include <asm/uaccess.h>
3119 +#include <asm/cacheflush.h>
3120 +#include <asm/hardware.h>
3121 +#include <asm/arch/xor.h>
3122 +#include <asm/pci.h>
3123 +#include <linux/version.h>
3124 +
3125 +/*
3126 + * pick up local definitions
3127 + */
3128 +#define XOR_SW_FILL_IN
3129 +#include "hw_xor.h"
3130 +
3131 +
3132 +//#define XOR_DEBUG
3133 +//#define XOR_TEST 1
3134 +#ifdef XOR_TEST
3135 +#define TEST_ITERATION 1000
3136 +#define SPIN_WAIT 1
3137 +#endif
3138 +#ifdef XOR_DEBUG
3139 +#define DPRINTK(s, args...) printk("Gemini XOR: " s "\n", ## args)
3140 +#define DENTER() DPRINTK("Entered...\n");
3141 +#define DEXIT() DPRINTK("Exited...\n");
3142 +#else
3143 +#define DPRINTK(s, args...)
3144 +#define DENTER()
3145 +#define DEXIT()
3146 +#endif
3147 +
3148 +//#define SPIN_WAIT
3149 +
3150 +/* globals */
3151 +static RAID_T tp;
3152 +static RAID_TXDMA_CTRL_T txdma_ctrl;
3153 +RAID_RXDMA_CTRL_T rxdma_ctrl;
3154 +
3155 +//#ifndef SPIN_WAIT
3156 +static spinlock_t raid_lock;
3157 +//#endif
3158 +
3159 +static unsigned int tx_desc_virtual_base;
3160 +static unsigned int rx_desc_virtual_base;
3161 +RAID_DESCRIPTOR_T *tx_desc_ptr;
3162 +RAID_DESCRIPTOR_T *rx_desc_ptr;
3163 +
3164 +/* static prototypes */
3165 +#define DMA_MALLOC(size,handle) pci_alloc_consistent(NULL,size,handle)
3166 +#define DMA_MFREE(mem,size,handle) pci_free_consistent(NULL,size,mem,handle)
3167 +
3168 +static int gemini_xor_init_desc(void);
3169 +
3170 +static unsigned int raid_read_reg(unsigned int offset)
3171 +{
3172 + unsigned int reg_val;
3173 +
3174 + reg_val = readl(RAID_BASE_ADDR + offset);
3175 + return (reg_val);
3176 +}
3177 +
3178 +static void raid_write_reg(unsigned int offset,unsigned int data,unsigned int bit_mask)
3179 +{
3180 + unsigned int reg_val;
3181 + unsigned int *addr;
3182 +
3183 + reg_val = ( raid_read_reg(offset) & (~bit_mask) ) | (data & bit_mask);
3184 + addr = (unsigned int *)(RAID_BASE_ADDR + offset);
3185 + writel(reg_val,addr);
3186 + return;
3187 +}
3188 +
3189 +#ifndef SPIN_WAIT
3190 +__inline__ void xor_queue_descriptor(void)
3191 +{
3192 + unsigned int flags,status=1;
3193 +
3194 + DPRINTK("Going to sleep");
3195 +
3196 + while(status){
3197 + yield();
3198 + //schedule();
3199 + spin_lock_irqsave(&raid_lock,flags);
3200 + status = tp.busy;
3201 + spin_unlock_irqrestore(&raid_lock, flags);
3202 + }
3203 +// tp.status = COMPLETE;
3204 + DPRINTK("woken up!");
3205 +
3206 +}
3207 +#endif
3208 +
3209 +#ifdef SPIN_WAIT
3210 +static void gemini_xor_isr(int d_n)
3211 +#else
3212 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3213 +static void gemini_xor_isr(int irq, void *dev_id, struct pt_regs *regs)
3214 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3215 +static irqreturn_t gemini_xor_isr(int irq, void *dev_instance, struct pt_regs *regs)
3216 +#endif
3217 +#endif
3218 +{
3219 +
3220 + unsigned int err;
3221 + RAID_DMA_STATUS_T dma_status;
3222 +// RAID_DESCRIPTOR_T *rdesc,*tdesc;
3223 +// unsigned int *paddr;
3224 +
3225 + dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3226 +#ifdef SPIN_WAIT
3227 + while( (dma_status.bits32& (1<<31) ) ==0 ){
3228 + udelay(1);
3229 + dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3230 + }
3231 +
3232 +/* tdesc = tp.tx_first_desc;
3233 + rdesc = tp.rx_first_desc;
3234 + for(d_n;d_n>0;d_n--){
3235 + if( tdesc->func_ctrl.bits.own == DMA ){
3236 + paddr = tdesc;
3237 + printk("error tx desc:0x%x\n",*paddr++);
3238 + printk("error tx desc:0x%x\n",*paddr++);
3239 + printk("error tx desc:0s%x\n",*paddr++);
3240 + printk("error tx desc:0x%x\n",*paddr);
3241 + while(1);
3242 + }
3243 + tdesc = (RAID_DESCRIPTOR_T *)((tdesc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3244 + }
3245 +
3246 + if( rdesc->func_ctrl.bits.own == DMA ){
3247 + paddr = rdesc;
3248 + printk("error rx desc:0x%x\n",*paddr++);
3249 + printk("error rx desc:0x%x\n",*paddr++);
3250 + printk("error rx desc:0s%x\n",*paddr++);
3251 + printk("error rx desc:0x%x\n",*paddr);
3252 + while(1);
3253 + }
3254 +*/
3255 +#endif
3256 +
3257 + if(dma_status.bits32 & ((1<<31)|(1<<26))){
3258 + // if no bug , we can turn off rx finish interrupt
3259 + dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3260 + err = raid_read_reg(RAID_DMA_DEVICE_ID);
3261 + tp.busy = 0;
3262 +
3263 + if(err&0x00FF0000){
3264 + tp.status = ERROR;
3265 + printk("XOR:<HW>%s error code %x\n",(err&0x00F00000)?"tx":"rx",err);
3266 +
3267 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3268 + return ;
3269 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3270 +#ifndef SPIN_WAIT
3271 + return IRQ_RETVAL(IRQ_HANDLED);
3272 +#endif
3273 +#endif
3274 + }
3275 + // 16~19 rx error code
3276 + // 20~23 tx error codd
3277 +
3278 + dma_status.bits.tsFinishI = 1;
3279 + dma_status.bits.rsFinishI = 1;
3280 + raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0x84000000); // clear INT
3281 +
3282 +// printk("xor %d\n",d_n);
3283 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3284 + return ;
3285 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3286 +#ifndef SPIN_WAIT
3287 + return IRQ_RETVAL(IRQ_HANDLED);
3288 +#endif
3289 +#endif
3290 + }
3291 +
3292 + #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3293 + return ;
3294 + #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3295 + #ifndef SPIN_WAIT
3296 + printk("XOR: DMA status register(0x%8x)\n",dma_status.bits32);
3297 + return IRQ_RETVAL(IRQ_HANDLED);
3298 + #endif
3299 + #endif
3300 +}
3301 +
3302 +void
3303 +xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
3304 +{
3305 + int status=0;
3306 + unsigned int flags;
3307 +
3308 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3309 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3310 + }
3311 +
3312 + spin_lock_irqsave(&raid_lock,flags);
3313 + while(tp.status != COMPLETE){
3314 + spin_unlock_irqrestore(&raid_lock, flags);
3315 + //printk("XOR yield2\n");
3316 +#ifdef XOR_SW_FILL_IN
3317 + xor_arm4regs_2(bytes,p1,p2);
3318 + return ;
3319 +#else
3320 + yield();
3321 +#endif
3322 + }
3323 + spin_unlock_irqrestore(&raid_lock, flags);
3324 + tp.status = RUNNING;
3325 +
3326 + // flush the cache to memory before H/W XOR touches them
3327 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3328 + consistent_sync(p2, bytes, DMA_TO_DEVICE);
3329 +
3330 +
3331 + tp.tx_desc = tp.tx_first_desc;
3332 + tp.rx_desc = tp.rx_first_desc;
3333 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3334 + // prepare tx descript
3335 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3336 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3337 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3338 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript
3339 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3340 + tp.tx_desc->flg_status.bits32 = 0x00020000;
3341 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3342 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3343 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3344 + wmb();
3345 + tp.tx_desc = tp.tx_cur_desc;
3346 + tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address
3347 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3348 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript
3349 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3350 + tp.tx_desc->flg_status.bits32 = 0x00010000;
3351 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3352 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3353 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript
3354 +
3355 + wmb();
3356 + // prepare rx descript
3357 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf);
3358 + tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3359 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3360 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3361 +// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3362 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3363 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3364 +
3365 + }
3366 + else{
3367 + /* no free tx descriptor */
3368 + printk("XOR:no free tx descript");
3369 + return ;
3370 + }
3371 +
3372 + // change status
3373 +// tp.status = RUNNING;
3374 + status = tp.busy = 1;
3375 +
3376 + // start tx DMA
3377 + rxdma_ctrl.bits.rd_start = 1;
3378 + // start rx DMA
3379 + txdma_ctrl.bits.td_start = 1;
3380 +
3381 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3382 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3383 +
3384 +#ifdef SPIN_WAIT
3385 + gemini_xor_isr(2);
3386 +#else
3387 + xor_queue_descriptor();
3388 +#endif
3389 +
3390 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*2) ;
3391 + tp.status = COMPLETE;
3392 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3393 +// tp.rx_desc = tp.rx_first_desc ;
3394 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3395 +
3396 +}
3397 +
3398 +void
3399 +xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3400 + unsigned long *p3)
3401 +{
3402 + int status=0;
3403 + unsigned int flags;
3404 +
3405 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3406 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3407 + }
3408 +
3409 + spin_lock_irqsave(&raid_lock,flags);
3410 + if(tp.status != COMPLETE){
3411 + spin_unlock_irqrestore(&raid_lock, flags);
3412 + //printk("XOR yield3\n");
3413 +#ifdef XOR_SW_FILL_IN
3414 + xor_arm4regs_3(bytes,p1,p2,p3);
3415 + return;
3416 +#else
3417 + yield();
3418 +#endif
3419 + }
3420 + spin_unlock_irqrestore(&raid_lock, flags);
3421 + tp.status = RUNNING;
3422 +
3423 + // flush the cache to memory before H/W XOR touches them
3424 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3425 + consistent_sync(p2, bytes, DMA_TO_DEVICE);
3426 + consistent_sync(p3, bytes, DMA_TO_DEVICE);
3427 +
3428 + tp.tx_desc = tp.tx_first_desc;
3429 + tp.rx_desc = tp.rx_first_desc;
3430 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3431 + // prepare tx descript
3432 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3433 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3434 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3435 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript
3436 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3437 + tp.tx_desc->flg_status.bits32 = 0x00020000;
3438 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3439 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3440 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3441 +
3442 + tp.tx_desc = tp.tx_cur_desc;
3443 + tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address
3444 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3445 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3446 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3447 + tp.tx_desc->flg_status.bits32 = 0x0000000;
3448 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3449 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3450 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3451 +
3452 + tp.tx_desc = tp.tx_cur_desc;
3453 + tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address
3454 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3455 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript
3456 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3457 + tp.tx_desc->flg_status.bits32 = 0x00010000;
3458 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3459 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3460 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript
3461 +
3462 + // prepare rx descript
3463 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf);
3464 + tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3465 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3466 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3467 +// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3468 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3469 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3470 +
3471 + }
3472 + else{
3473 + /* no free tx descriptor */
3474 + printk("XOR:no free tx descript \n");
3475 + return ;
3476 + }
3477 +
3478 + // change status
3479 +// tp.status = RUNNING;
3480 + status = tp.busy = 1;
3481 +
3482 + // start tx DMA
3483 + rxdma_ctrl.bits.rd_start = 1;
3484 + // start rx DMA
3485 + txdma_ctrl.bits.td_start = 1;
3486 + wmb();
3487 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3488 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3489 +
3490 +#ifdef SPIN_WAIT
3491 + gemini_xor_isr(3);
3492 +#else
3493 + xor_queue_descriptor();
3494 +#endif
3495 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*3) | 0x0B;
3496 + tp.status = COMPLETE;
3497 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3498 + //tp.rx_desc = tp.rx_first_desc ;
3499 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3500 +
3501 +}
3502 +
3503 +void
3504 +xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3505 + unsigned long *p3, unsigned long *p4)
3506 +{
3507 + int status=0;
3508 + unsigned int flags;
3509 +
3510 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3511 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3512 + }
3513 +
3514 + spin_lock_irqsave(&raid_lock,flags);
3515 + if(tp.status != COMPLETE){
3516 + spin_unlock_irqrestore(&raid_lock, flags);
3517 + //printk("S\n");
3518 +#ifdef XOR_SW_FILL_IN
3519 + xor_arm4regs_4(bytes,p1,p2,p3,p4);
3520 + return;
3521 +#else
3522 + msleep(1);
3523 + yield();
3524 +#endif
3525 + }
3526 + spin_unlock_irqrestore(&raid_lock, flags);
3527 +
3528 + tp.status = RUNNING;
3529 +
3530 + // flush the cache to memory before H/W XOR touches them
3531 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3532 + consistent_sync(p2, bytes, DMA_TO_DEVICE);
3533 + consistent_sync(p3, bytes, DMA_TO_DEVICE);
3534 + consistent_sync(p4, bytes, DMA_TO_DEVICE);
3535 +
3536 + tp.tx_desc = tp.tx_first_desc;
3537 + tp.rx_desc = tp.rx_first_desc;
3538 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3539 + // prepare tx descript
3540 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3541 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3542 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3543 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript
3544 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3545 + tp.tx_desc->flg_status.bits32 = 0x00020000;
3546 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3547 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3548 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3549 +
3550 + tp.tx_desc = tp.tx_cur_desc;
3551 + tp.tx_cur_desc->buf_addr = (unsigned int)__pa(p2); // pysical address
3552 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3553 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3554 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3555 + tp.tx_desc->flg_status.bits32 = 0x00000000;
3556 + tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3557 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3558 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3559 +
3560 + tp.tx_desc = tp.tx_cur_desc;
3561 + tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address
3562 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3563 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3564 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3565 + tp.tx_desc->flg_status.bits32 = 0x00000000;
3566 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3567 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3568 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3569 +
3570 +
3571 + tp.tx_desc = tp.tx_cur_desc;
3572 + tp.tx_desc->buf_addr = (unsigned int)__pa(p4); // pysical address
3573 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3574 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript
3575 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3576 + tp.tx_desc->flg_status.bits32 = 0x00010000;
3577 +// tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3578 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3579 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3580 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base); // keep last descript
3581 +
3582 + // prepare rx descript
3583 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3584 + tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3585 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3586 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3587 +// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3588 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3589 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3590 +
3591 + }
3592 + else{
3593 + /* no free tx descriptor */
3594 + printk("XOR:no free tx descript");
3595 + return ;
3596 + }
3597 +
3598 + // change status
3599 +// tp.status = RUNNING;
3600 + status = tp.busy = 1;
3601 +
3602 + // start tx DMA
3603 + rxdma_ctrl.bits.rd_start = 1;
3604 + // start rx DMA
3605 + txdma_ctrl.bits.td_start = 1;
3606 + wmb();
3607 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3608 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3609 +
3610 +#ifdef SPIN_WAIT
3611 + gemini_xor_isr(4);
3612 +#else
3613 + xor_queue_descriptor();
3614 +#endif
3615 +
3616 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*4) | 0x0B;
3617 + tp.status = COMPLETE;
3618 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3619 + //tp.rx_desc = tp.rx_first_desc ;
3620 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3621 +
3622 +}
3623 +
3624 +void
3625 +xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3626 + unsigned long *p3, unsigned long *p4, unsigned long *p5)
3627 +{
3628 +
3629 + int status=0;
3630 + unsigned int flags;
3631 +
3632 +
3633 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3634 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3635 + }
3636 +
3637 + spin_lock_irqsave(&raid_lock,flags);
3638 + while(tp.status != COMPLETE){
3639 + spin_unlock_irqrestore(&raid_lock, flags);
3640 + //printk("XOR yield5\n");
3641 +#ifdef XOR_SW_FILL_IN
3642 + xor_arm4regs_5(bytes,p1,p2,p3,p4,p5);
3643 + return;
3644 +#else
3645 + msleep(1);
3646 + yield();
3647 +#endif
3648 + }
3649 + spin_unlock_irqrestore(&raid_lock, flags);
3650 + tp.status = RUNNING;
3651 +
3652 + // flush the cache to memory before H/W XOR touches them
3653 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3654 + consistent_sync(p2, bytes, DMA_TO_DEVICE);
3655 + consistent_sync(p3, bytes, DMA_TO_DEVICE);
3656 + consistent_sync(p4, bytes, DMA_TO_DEVICE);
3657 + consistent_sync(p5, bytes, DMA_TO_DEVICE);
3658 +
3659 + tp.tx_desc = tp.tx_first_desc;
3660 + tp.rx_desc = tp.rx_first_desc;
3661 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3662 + // prepare tx descript
3663 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3664 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3665 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3666 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 2; // first descript
3667 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3668 + tp.tx_desc->flg_status.bits32 = 0x00020000;
3669 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3670 + wmb();
3671 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3672 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3673 +
3674 + tp.tx_desc = tp.tx_cur_desc;
3675 + tp.tx_desc->buf_addr = (unsigned int)__pa(p2); // pysical address
3676 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3677 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3678 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3679 + tp.tx_desc->flg_status.bits32 = 0x00000000;
3680 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3681 + wmb();
3682 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3683 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3684 +
3685 + tp.tx_desc = tp.tx_cur_desc;
3686 + tp.tx_desc->buf_addr = (unsigned int)__pa(p3); // pysical address
3687 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3688 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3689 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3690 + tp.tx_desc->flg_status.bits32 = 0x00000000;
3691 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3692 + wmb();
3693 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3694 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3695 +
3696 + tp.tx_desc = tp.tx_cur_desc;
3697 + tp.tx_desc->buf_addr = (unsigned int)__pa(p4); // pysical address
3698 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3699 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 0; // first descript
3700 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3701 + tp.tx_desc->flg_status.bits32 = 0x00000000;
3702 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3703 + wmb();
3704 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3705 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3706 +
3707 +
3708 + tp.tx_desc = tp.tx_cur_desc;
3709 + tp.tx_desc->buf_addr = (unsigned int)__pa(p5); // pysical address
3710 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3711 +// tp.tx_desc->flg_status.bits_cmd_status.bcc = 1; // last descript
3712 +// tp.tx_desc->flg_status.bits_cmd_status.mode = 0; // only support XOR command
3713 +// tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3714 + tp.tx_desc->flg_status.bits32 = 0x00010000;
3715 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3716 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3717 + tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3718 + tp.tx_finished_desc = tp.tx_desc; // keep last descript
3719 +
3720 + // prepare rx descript
3721 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3722 + tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3723 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3724 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3725 +// tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3726 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3727 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3728 +
3729 + }
3730 + else{
3731 + /* no free tx descriptor */
3732 + printk("XOR:no free tx descript");
3733 + return ;
3734 + }
3735 +
3736 + // change status
3737 +// tp.status = RUNNING;
3738 + status = tp.busy = 1;
3739 +
3740 + // start tx DMA
3741 + rxdma_ctrl.bits.rd_start = 1;
3742 + // start rx DMA
3743 + txdma_ctrl.bits.td_start = 1;
3744 + wmb();
3745 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3746 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3747 +
3748 +#ifdef SPIN_WAIT
3749 + gemini_xor_isr(5);
3750 +#else
3751 + xor_queue_descriptor();
3752 +#endif
3753 +
3754 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*5) | 0x0B;
3755 + tp.status = COMPLETE;
3756 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3757 + //tp.rx_desc = tp.rx_first_desc ;
3758 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3759 +
3760 +}
3761 +
3762 +#ifdef XOR_TEST
3763 +void
3764 +raid_memset(unsigned int *p1, unsigned int pattern, unsigned int bytes)
3765 +{
3766 + int status=0,i;
3767 +
3768 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3769 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3770 + }
3771 +
3772 + *p1 = pattern;
3773 +
3774 + // flush the cache to memory before H/W XOR touches them
3775 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3776 +
3777 + while(tp.status != COMPLETE){
3778 + DPRINTK("XOR yield\n");
3779 + //schedule();
3780 + yield();
3781 + }
3782 + tp.status = RUNNING;
3783 +
3784 + tp.tx_desc = tp.tx_first_desc;
3785 + tp.rx_desc = tp.rx_first_desc;
3786 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3787 + // prepare tx descript
3788 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
3789 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3790 + tp.tx_desc->func_ctrl.bits.buffer_size = 4; /* total frame byte count */
3791 + tp.tx_desc->flg_status.bits_cmd_status.bcc = bytes; // bytes to fill
3792 + tp.tx_desc->flg_status.bits_cmd_status.mode = CMD_FILL; // only support memory FILL command
3793 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3794 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3795 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
3796 +// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
3797 +
3798 + // prepare rx descript
3799 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3800 + tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3801 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3802 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3803 + tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3804 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3805 +// tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base);
3806 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3807 + tp.rx_finished_desc = tp.rx_desc;
3808 +
3809 + }
3810 + else{
3811 + /* no free tx descriptor */
3812 + printk("XOR:no free tx descript");
3813 + return ;
3814 + }
3815 +
3816 + // change status
3817 + //tp.status = RUNNING;
3818 + status = tp.busy = 1;
3819 +
3820 + // start tx DMA
3821 + rxdma_ctrl.bits.rd_start = 1;
3822 + // start rx DMA
3823 + txdma_ctrl.bits.td_start = 1;
3824 +
3825 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3826 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3827 +
3828 +#ifdef SPIN_WAIT
3829 + gemini_xor_isr(2);
3830 +#else
3831 + xor_queue_descriptor();
3832 +#endif
3833 +
3834 + for(i=1; i<(bytes/sizeof(int)); i++) {
3835 + if(p1[0]!=p1[i]){
3836 + printk("pattern set error!\n");
3837 + while(1);
3838 + }
3839 + }
3840 +
3841 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3842 + tp.status = COMPLETE;
3843 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3844 + //tp.rx_desc = tp.rx_first_desc ;
3845 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3846 +
3847 +}
3848 +#endif
3849 +
3850 +void
3851 +raid_memcpy(unsigned int *to, unsigned int *from, unsigned int bytes)
3852 +{
3853 + int status=0,i;
3854 +
3855 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3856 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3857 + }
3858 +
3859 + // flush the cache to memory before H/W XOR touches them
3860 + consistent_sync(to, bytes, DMA_BIDIRECTIONAL);
3861 + consistent_sync(from,bytes, DMA_TO_DEVICE);
3862 +
3863 + while(tp.status != COMPLETE){
3864 + DPRINTK("XOR yield\n");
3865 + //schedule();
3866 + yield();
3867 + }
3868 + tp.status = RUNNING;
3869 +
3870 + tp.tx_desc = tp.tx_first_desc;
3871 + tp.rx_desc = tp.rx_first_desc;
3872 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3873 + // prepare tx descript
3874 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
3875 + tp.tx_desc->buf_addr = (unsigned int)__pa(from); // physical address
3876 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3877 + tp.tx_desc->flg_status.bits32 = CMD_CPY; // only support memory FILL command
3878 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3879 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3880 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
3881 +// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
3882 +
3883 + // prepare rx descript
3884 + raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3885 + tp.rx_desc->buf_addr = (unsigned int)__pa(to);
3886 + tp.rx_desc->func_ctrl.bits.buffer_size = bytes; /* total frame byte count */
3887 + tp.rx_desc->flg_status.bits32 = 0; // link data from XOR
3888 + tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3889 + tp.rx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3890 +// tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base);
3891 + tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3892 +
3893 + }
3894 + else{
3895 + /* no free tx descriptor */
3896 + printk("XOR:no free tx descript");
3897 + return ;
3898 + }
3899 +
3900 + // change status
3901 + //tp.status = RUNNING;
3902 + status = tp.busy = 1;
3903 +
3904 + // start tx DMA
3905 + rxdma_ctrl.bits.rd_start = 1;
3906 + // start rx DMA
3907 + txdma_ctrl.bits.td_start = 1;
3908 +
3909 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3910 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3911 +
3912 +#ifdef SPIN_WAIT
3913 + gemini_xor_isr(2);
3914 +#else
3915 + xor_queue_descriptor();
3916 +#endif
3917 +
3918 +#ifdef XOR_TEST
3919 + for(i=1; i<(bytes/sizeof(int)); i++) {
3920 + if(to[i]!=from[i]){
3921 + printk("pattern check error!\n");
3922 + printk("offset=0x%x p1=%x p2=%x\n",i*4,to[i],from[i]);
3923 + while(1);
3924 + }
3925 + }
3926 +#endif
3927 +
3928 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3929 + tp.status = COMPLETE;
3930 +// tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3931 + //tp.rx_desc = tp.rx_first_desc ;
3932 +// tp.rx_desc->func_ctrl.bits.own = DMA;
3933 +
3934 +}
3935 +EXPORT_SYMBOL(raid_memcpy);
3936 +
3937 +#ifdef XOR_TEST
3938 +int
3939 +raid_memchk(unsigned int *p1, unsigned int pattern, unsigned int bytes)
3940 +{
3941 + int status=0;
3942 + RAID_DMA_STATUS_T dma_status;
3943 +
3944 + if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3945 + printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3946 + }
3947 +
3948 + status = ((pattern&0xFFFF)%bytes )/4;
3949 + p1[status] = pattern;
3950 +
3951 + while(tp.status != COMPLETE){
3952 + DPRINTK("XOR yield\n");
3953 + //schedule();
3954 + yield();
3955 + }
3956 + tp.status = RUNNING;
3957 +
3958 + // flush the cache to memory before H/W XOR touches them
3959 + consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3960 +
3961 + tp.tx_desc = tp.tx_first_desc;
3962 + if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3963 + // prepare tx descript
3964 + raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
3965 + tp.tx_desc->buf_addr = (unsigned int)__pa(p1); // physical address
3966 + tp.tx_desc->func_ctrl.bits.raid_ctrl_status = 0;
3967 + tp.tx_desc->func_ctrl.bits.buffer_size = bytes ; /* total frame byte count */
3968 + tp.tx_desc->flg_status.bits32 = CMD_CHK; // only support memory FILL command
3969 + tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03; /*only one descriptor*/
3970 + tp.tx_desc->func_ctrl.bits.own = DMA; /* set owner bit */
3971 + tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
3972 +// tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
3973 +
3974 + }
3975 + else{
3976 + /* no free tx descriptor */
3977 + printk("XOR:no free tx descript");
3978 + return -1;
3979 + }
3980 +
3981 + // change status
3982 + //tp.status = RUNNING;
3983 + status = tp.busy = 1;
3984 +
3985 + // start tx DMA
3986 + txdma_ctrl.bits.td_start = 1;
3987 +
3988 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3989 +// raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3990 +
3991 +#ifdef SPIN_WAIT
3992 + gemini_xor_isr(2);
3993 +#else
3994 + xor_queue_descriptor();
3995 +#endif
3996 +
3997 +// dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3998 +// if (dma_status.bits32 & (1<<15)) {
3999 +
4000 + if((tp.tx_first_desc->func_ctrl.bits.raid_ctrl_status & 0x2)) {
4001 + status = 1;
4002 +// raid_write_reg(RAID_DMA_STATUS,0x00008000,0x00080000);
4003 + }
4004 + else{
4005 + status = 0;
4006 + }
4007 +
4008 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
4009 + tp.status = COMPLETE;
4010 +// tp.rx_desc->func_ctrl.bits.own = DMA;
4011 + return status ;
4012 +}
4013 +#endif
4014 +
4015 +int __init gemini_xor_init(void)
4016 +{
4017 + unsigned int res;
4018 + unsigned int *paddr1,*paddr2,*paddr3,i;
4019 + unsigned volatile char *charact;
4020 + unsigned volatile short *two_char;
4021 + unsigned volatile int *four_char;
4022 +
4023 + // init descript
4024 + res = gemini_xor_init_desc();
4025 + if(res) {
4026 + printk("Init RAID Descript Fail!!\n");
4027 + return -res;
4028 + }
4029 +
4030 + tp.device_name = "Gemini XOR Acceleration";
4031 +
4032 + // request irq
4033 +#ifndef SPIN_WAIT
4034 + res = request_irq(IRQ_RAID, gemini_xor_isr, SA_INTERRUPT, tp.device_name, NULL);
4035 +#endif
4036 + if(res){
4037 + printk(KERN_ERR "%s: unable to request IRQ %d for "
4038 + "HW XOR %d\n", tp.device_name, IRQ_RAID, res);
4039 + return -EBUSY;
4040 + }
4041 +
4042 +#ifdef XOR_TEST
4043 +
4044 +RETEST:
4045 + paddr1 = kmalloc(0x1000,GFP_KERNEL);
4046 + paddr2 = kmalloc(0x1000,GFP_KERNEL);
4047 + paddr3 = kmalloc(0x1000,GFP_KERNEL);
4048 + for(i=0;i<TEST_ITERATION;i++) {
4049 + printk("XOR test round %d\n",i);
4050 + for(res=0;res<(0x1000)/sizeof(int);res++){ // prepare data pattern
4051 + paddr1[res]= readl(0xf62000ac);
4052 + paddr2[res]= readl(0xf62000ac);
4053 + }
4054 + for(res=0;res<0x1000/sizeof(int);res++){ // calculate xor by software
4055 + paddr3[res] = paddr1[res]^paddr2[res];
4056 + }
4057 + xor_gemini_2(0x1000,paddr1,paddr2); // calculate xor by hw
4058 + for(res=0;res<0x1000/sizeof(int);res++){ // check error
4059 + if(paddr1[res]!=paddr3[res]){
4060 + printk("XOR ERROR\n");
4061 + printk("[%d][0x%x]=0x%x should be %x\n",res,&paddr1[res],paddr1[res],paddr3[res]);
4062 + while(1);
4063 + }
4064 + }
4065 + }
4066 + kfree(paddr1);
4067 + kfree(paddr2);
4068 + kfree(paddr3);
4069 +
4070 +
4071 + // memcpy test
4072 + paddr1 = kmalloc(0x4000,GFP_KERNEL);
4073 + for(i=0;i<TEST_ITERATION;i++) {
4074 + for(res=0;res<(0x4000)/sizeof(int);res++)
4075 + paddr1[res]= readl(0xf62000ac);
4076 +
4077 + printk("MEMCOPY round %d\n",i);
4078 + paddr2 = kmalloc(0x4000,GFP_KERNEL);
4079 + raid_memcpy(paddr2,paddr1,0x4000);
4080 + kfree(paddr2);
4081 + }
4082 + kfree(paddr1);
4083 +
4084 + // memset test
4085 + for(i=0;i<TEST_ITERATION;i++) {
4086 + raid_memset(paddr1,0xFFFFFFFF,0x4000);
4087 + res = readl(0xf62000ac);
4088 + printk("MEMFILL fill 0x%x round %d\n",res,i);
4089 + paddr1 = kmalloc(0x4000,GFP_KERNEL);
4090 + raid_memset(paddr1,res,0x4000);
4091 + raid_memset(paddr1,0x0,0x4000);
4092 + kfree(paddr1);
4093 + }
4094 +
4095 + paddr1 = kmalloc(0x4000,GFP_KERNEL);
4096 + for(i=0;i<TEST_ITERATION;i++){
4097 + raid_memset(paddr1, i,0x4000);
4098 + printk("Pattern check same ? ");
4099 + res = raid_memchk(paddr1, i,0x4000);
4100 + printk("%s\n",res?"Fail":"OK");
4101 + if(res) while(1);
4102 +
4103 + printk("Pattern check diff ? ");
4104 + res = raid_memchk(paddr1,readl(0xf62000ac),0x4000);
4105 + printk("%s\n",res?"OK":"Fail");
4106 + if(!res) while(1);
4107 + }
4108 + kfree(paddr1);
4109 +
4110 + // SRAM test
4111 + raid_write_reg(RAID_PCR, 0,0x00000003);
4112 + for(i=0;i<TEST_ITERATION;i++) {
4113 + printk("SRAM test %d\n",i);
4114 + charact = 0xF7000000;
4115 + two_char = 0xF7000000;
4116 + four_char = 0xF7000000;
4117 + for(res=0;res<(16*1024)/sizeof(char);res++) { // 8-bit access
4118 + *charact++ = (unsigned char)res;
4119 + }
4120 + charact = 0xF7000000;
4121 + for(res=0;res<(16*1024)/sizeof(char);res++) {
4122 + if(*charact++ != (unsigned char)res){
4123 + printk("SRAM data error(8)\n");
4124 + while(1);
4125 + }
4126 + }
4127 +
4128 + for(res=0;res<(16*1024)/sizeof(short);res++) { // 16-bit access
4129 + *two_char++ = (unsigned short)res;
4130 + }
4131 + two_char = 0xF7000000;
4132 + for(res=0;res<(16*1024)/sizeof(short);res++) {
4133 + if(*two_char++ != (unsigned short)res){
4134 + printk("SRAM data error(16)\n");
4135 + while(1);
4136 + }
4137 + }
4138 +
4139 + for(res=0;res<(16*1024)/sizeof(int);res++) { // 32-bit access
4140 + *four_char++ = (unsigned int)res;
4141 + }
4142 + four_char = 0xF7000000;
4143 + for(res=0;res<(16*1024)/sizeof(int);res++) {
4144 + if(*four_char++ != (unsigned int)res){
4145 + printk("SRAM data error(32)\n");
4146 + while(1);
4147 + }
4148 + }
4149 + }
4150 + raid_write_reg(RAID_PCR, SRAM_PAR_SIZE,0x00000003);
4151 +
4152 +#endif
4153 + return 0;
4154 +}
4155 +
4156 +void __exit gemini_xor_exit(void)
4157 +{
4158 + DMA_MFREE(tp.tx_desc, TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(unsigned int)tp.tx_desc_dma);
4159 + DMA_MFREE(tp.rx_desc, RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(unsigned int)tp.rx_desc_dma);
4160 + free_irq(IRQ_RAID, NULL);
4161 +}
4162 +
4163 +
4164 +static int gemini_xor_init_desc(void)
4165 +{
4166 + unsigned int i;
4167 + dma_addr_t tx_first_desc_dma;
4168 + dma_addr_t rx_first_desc_dma;
4169 + RAID_DMA_STATUS_T dma_status;
4170 +
4171 + printk("Initial RAID Descripter...\n");
4172 +
4173 + tp.tx_desc = (RAID_DESCRIPTOR_T*)DMA_MALLOC(TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t *)&tp.tx_desc_dma);
4174 + tx_desc_virtual_base = (unsigned int)tp.tx_desc - (unsigned int)tp.tx_desc_dma;
4175 + memset(tp.tx_desc,0x00,TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T));
4176 +
4177 + tp.rx_desc = (RAID_DESCRIPTOR_T*)DMA_MALLOC(RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t *)&tp.rx_desc_dma);
4178 + rx_desc_virtual_base = (unsigned int)tp.rx_desc - (unsigned int)tp.rx_desc_dma;
4179 + memset(tp.rx_desc,0x00,RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T));
4180 + printk("XOR:tx_desc = %08x\n",(unsigned int)tp.tx_desc);
4181 + printk("XOR:rx_desc = %08x\n",(unsigned int)tp.rx_desc);
4182 + printk("XOR:tx_desc_dma = %08x\n",(unsigned int)tp.tx_desc_dma);
4183 + printk("XOR:rx_desc_dma = %08x\n",(unsigned int)tp.rx_desc_dma);
4184 +
4185 + if ((tp.tx_desc == NULL) || (tp.rx_desc == NULL)) {
4186 + if (tp.tx_desc)
4187 + DMA_MFREE(tp.tx_desc, TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t)tp.tx_desc_dma);
4188 + if (tp.rx_desc)
4189 + DMA_MFREE(tp.rx_desc, RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t)tp.rx_desc_dma);
4190 + return -ENOMEM;
4191 + }
4192 +
4193 + tp.tx_cur_desc = tp.tx_desc; /* virtual address */
4194 + tp.tx_finished_desc = tp.tx_desc; /* virtual address */
4195 + tx_first_desc_dma = (dma_addr_t)tp.tx_desc_dma; /* physical address */
4196 + for (i = 1; i < TX_DESC_NUM; i++) {
4197 + tp.tx_desc->func_ctrl.bits.own = CPU;
4198 + tp.tx_desc->func_ctrl.bits.buffer_size = 0;
4199 + tp.tx_desc_dma = tp.tx_desc_dma + sizeof(RAID_DESCRIPTOR_T);
4200 +// tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tp.tx_desc_dma | 0x0B;
4201 + tp.tx_desc->next_desc_addr.bits32 = ((unsigned int)tx_first_desc_dma | 0x0B) + i*0x10;
4202 + tp.tx_desc = &tp.tx_desc[1];
4203 + }
4204 + tp.tx_desc->func_ctrl.bits.own = DMA;
4205 + tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tx_first_desc_dma|0x0b;
4206 + tp.tx_desc = tp.tx_cur_desc;
4207 + tp.tx_desc_dma = (unsigned int*)tx_first_desc_dma;
4208 + tp.tx_first_desc = tp.tx_desc ;
4209 +
4210 + tp.rx_cur_desc = tp.rx_desc; /* virtual address */
4211 + tp.rx_finished_desc = tp.rx_desc; /* virtual address */
4212 + rx_first_desc_dma = (dma_addr_t)tp.rx_desc_dma; /* physical address */
4213 + for (i = 1; i < RX_DESC_NUM; i++) {
4214 + tp.rx_desc->func_ctrl.bits.own = DMA;
4215 + tp.rx_desc->func_ctrl.bits.buffer_size = 0;
4216 + tp.rx_desc_dma = tp.rx_desc_dma + sizeof(RAID_DESCRIPTOR_T);
4217 +// tp.rx_desc->next_desc_addr.bits32 = (unsigned int)tp.rx_desc_dma | 0x0B;
4218 + tp.rx_desc->next_desc_addr.bits32 = ((unsigned int)rx_first_desc_dma | 0x0B) + i*0x10;
4219 + tp.rx_desc = &tp.rx_desc[1];
4220 + }
4221 + tp.rx_desc->func_ctrl.bits.own = DMA;
4222 + tp.rx_desc->next_desc_addr.bits32 = rx_first_desc_dma|0x0b;
4223 + tp.rx_desc = tp.rx_cur_desc;
4224 + tp.rx_desc_dma = (unsigned int*)rx_first_desc_dma;
4225 + tp.rx_first_desc = tp.rx_desc ;
4226 + tp.busy = 0;
4227 + tp.status = COMPLETE;
4228 +
4229 + // Partition SRAM size
4230 + raid_write_reg(RAID_PCR, SRAM_PAR_SIZE,0x00000003);
4231 +
4232 + // config tx DMA controler
4233 + txdma_ctrl.bits32 = 0;
4234 + txdma_ctrl.bits.td_start = 0;
4235 + txdma_ctrl.bits.td_continue = 1;
4236 + txdma_ctrl.bits.td_chain_mode = 1;
4237 + txdma_ctrl.bits.td_prot = 0;
4238 + txdma_ctrl.bits.td_burst_size = 1;
4239 + txdma_ctrl.bits.td_bus = 3;
4240 + txdma_ctrl.bits.td_endian = 0;
4241 + txdma_ctrl.bits.td_finish_en = 1;
4242 + txdma_ctrl.bits.td_fail_en = 1;
4243 + txdma_ctrl.bits.td_perr_en = 1;
4244 + txdma_ctrl.bits.td_eod_en = 0; // enable tx descript
4245 + txdma_ctrl.bits.td_eof_en = 0;
4246 + raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0xFFFFFFFF);
4247 +
4248 + // config rx DMA controler
4249 + rxdma_ctrl.bits32 = 0;
4250 + rxdma_ctrl.bits.rd_start = 0;
4251 + rxdma_ctrl.bits.rd_continue = 1;
4252 + rxdma_ctrl.bits.rd_chain_mode = 1;
4253 + rxdma_ctrl.bits.rd_prot = 0;
4254 + rxdma_ctrl.bits.rd_burst_size = 1;
4255 + rxdma_ctrl.bits.rd_bus = 3;
4256 + rxdma_ctrl.bits.rd_endian = 0;
4257 + rxdma_ctrl.bits.rd_finish_en = 0;
4258 + rxdma_ctrl.bits.rd_fail_en = 1;
4259 + rxdma_ctrl.bits.rd_perr_en = 1;
4260 + rxdma_ctrl.bits.rd_eod_en = 0;
4261 + rxdma_ctrl.bits.rd_eof_en = 0;
4262 + raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0xFFFFFFFF);
4263 +
4264 + // enable interrupt
4265 + dma_status.bits32 = 3; // enable RpInt
4266 + raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0xFFFFFFFF);
4267 +
4268 + return 0;
4269 +}
4270 +
4271 +module_init(gemini_xor_init);
4272 +module_exit(gemini_xor_exit);
4273 +
4274 --- a/arch/arm/mm/Kconfig
4275 +++ b/arch/arm/mm/Kconfig
4276 @@ -187,6 +187,26 @@
4277 Say Y if you want support for the ARM926T processor.
4278 Otherwise, say N.
4279
4280 +###### for Storlink SoC ######
4281 +config CPU_FA526
4282 + bool "FA526 processor"
4283 + depends on ARCH_SL2312
4284 + default y
4285 + select CPU_32v4
4286 + select CPU_ABRT_EV4
4287 + select CPU_CACHE_FA
4288 + select CPU_CACHE_VIVT
4289 + select CPU_CP15_MMU
4290 + select CPU_COPY_FA
4291 + select CPU_TLB_FA
4292 + select CPU_FA_BTB
4293 + help
4294 + The FA526 is a version of the ARM9 compatible processor, but with smaller
4295 + instruction and data caches. It is used in Storlink Sword device family.
4296 +
4297 + Say Y if you want support for the FA526 processor.
4298 + Otherwise, say N.
4299 +
4300 # ARM940T
4301 config CPU_ARM940T
4302 bool "Support ARM940T processor" if ARCH_INTEGRATOR
4303 @@ -461,6 +481,9 @@
4304 config CPU_CACHE_VIPT
4305 bool
4306
4307 +config CPU_CACHE_FA
4308 + bool
4309 +
4310 if MMU
4311 # The copy-page model
4312 config CPU_COPY_V3
4313 @@ -475,6 +498,12 @@
4314 config CPU_COPY_V6
4315 bool
4316
4317 +config CPU_COPY_FA
4318 + bool
4319 +
4320 +config CPU_FA_BTB
4321 + bool
4322 +
4323 # This selects the TLB model
4324 config CPU_TLB_V3
4325 bool
4326 @@ -534,6 +563,14 @@
4327 config IO_36
4328 bool
4329
4330 +config CPU_TLB_FA
4331 + bool
4332 + help
4333 + //TODO
4334 + Faraday ARM FA526 architecture, unified TLB with writeback cache
4335 + and invalidate instruction cache entry. Branch target buffer is also
4336 + supported.
4337 +
4338 comment "Processor Features"
4339
4340 config ARM_THUMB
4341 @@ -600,7 +637,7 @@
4342
4343 config CPU_DCACHE_WRITETHROUGH
4344 bool "Force write through D-cache"
4345 - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
4346 + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
4347 default y if CPU_ARM925T
4348 help
4349 Say Y here to use the data cache in writethrough mode. Unless you
4350 --- a/arch/arm/mm/Makefile
4351 +++ b/arch/arm/mm/Makefile
4352 @@ -32,6 +32,7 @@
4353 obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
4354 obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o
4355 obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o
4356 +obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
4357
4358 obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
4359 obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
4360 @@ -40,6 +41,7 @@
4361 obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o
4362 obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
4363 obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
4364 +obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
4365
4366 obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
4367 obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
4368 @@ -47,6 +49,7 @@
4369 obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
4370 obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o
4371 obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
4372 +obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o
4373
4374 obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
4375 obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
4376 @@ -60,6 +63,7 @@
4377 obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o
4378 obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o
4379 obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o
4380 +obj-$(CONFIG_CPU_FA526) += proc-fa526.o
4381 obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o
4382 obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o
4383 obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o
4384 --- /dev/null
4385 +++ b/arch/arm/mm/cache-fa.S
4386 @@ -0,0 +1,400 @@
4387 +/*
4388 + * linux/arch/arm/mm/cache-fa.S
4389 + *
4390 + * Copyright (C) 2005 Faraday Corp.
4391 + *
4392 + * This program is free software; you can redistribute it and/or modify
4393 + * it under the terms of the GNU General Public License version 2 as
4394 + * published by the Free Software Foundation.
4395 + *
4396 + * Processors: FA520 FA526 FA626
4397 + * 03/31/2005 : Luke Lee created, modified from cache-v4wb.S
4398 + * 04/06/2005 : 1. Read CR0-1 and determine the cache size dynamically,
4399 + * to suit all Faraday CPU series
4400 + * 2. Fixed all functions
4401 + * 04/08/2005 : insert CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE
4402 + * 04/12/2005 : TODO: make this processor dependent or a self-modifying code to
4403 + * inline cache len/size info into the instructions, as reading cache
4404 + * size and len info in memory could cause another cache miss.
4405 + * 05/05/2005 : Modify fa_flush_user_cache_range to comply APCS.
4406 + * 05/19/2005 : Adjust for boundary conditions.
4407 + */
4408 +#include <linux/linkage.h>
4409 +#include <linux/init.h>
4410 +#include <asm/hardware.h>
4411 +#include <asm/page.h>
4412 +#include "proc-macros.S"
4413 +
4414 +#define CACHE_DLINESIZE 16
4415 +#ifdef CONFIG_SL3516_ASIC
4416 +#define CACHE_DSIZE 8192
4417 +#else
4418 +#define CACHE_DSIZE 16384
4419 +#endif
4420 +#define CACHE_ILINESIZE 16
4421 +#define CACHE_ISIZE 16384
4422 +
4423 +/* Luke Lee 04/06/2005 ins begin */
4424 +/*
4425 + * initialize_cache_info()
4426 + *
4427 + * Automatic detection of DSIZE, DLEN, ISIZE, ILEN variables according to
4428 + * system register CR0-1
4429 + * Destroyed register: r0, r1, r2, r3, ip
4430 + */
4431 + .align
4432 +ENTRY(fa_initialize_cache_info)
4433 + mov r3, #1 @ r3 always = 1
4434 + adr ip, __fa_cache_ilen
4435 +
4436 + mrc p15, 0, r0, c0, c0, 1
4437 + /* ILEN */
4438 + and r1, r0, #3 @ bits [1:0]
4439 + add r1, r1, #3 @ cache line size is at least 8 bytes (2^3)
4440 + mov r2, r3, lsl r1 @ r2 = 1<<r1
4441 + str r2, [ip], #4
4442 + /* ISIZE */
4443 + mov r1, r0, lsr #6 @ bits [8:6]
4444 + and r1, r1, #7
4445 + add r1, r1, #9 @ cache size is at least 512 bytes (2^9)
4446 + mov r2, r3, lsl r1
4447 + str r2, [ip], #4
4448 + /* DLEN */
4449 + mov r1, r0, lsr #12
4450 + and r1, r1, #3 @ bits [13:12]
4451 + add r1, r1, #3 @ cache line size is at least 8 bytes (2^3)
4452 + mov r2, r3, lsl r1 @ r2 = 1<<r1
4453 + str r2, [ip], #4
4454 + /* DSIZE */
4455 + mov r1, r0, lsr #18 @ bits [20:18]
4456 + and r1, r1, #7
4457 + add r1, r1, #9 @ cache size is at least 512 bytes (2^9)
4458 + mov r2, r3, lsl r1
4459 + str r2, [ip]
4460 + mov pc, lr
4461 +
4462 + /* Warning : Do not change the order ! Successive codes depends on this */
4463 + .align
4464 + .globl __fa_cache_ilen, __fa_cache_isize, __fa_cache_dlen, __fa_cache_dsize
4465 +__fa_cache_ilen:
4466 + .word 0 @ instruction cache line length
4467 +__fa_cache_isize:
4468 + .word 0 @ instruction cache size
4469 +__fa_cache_dlen:
4470 + .word 0 @ data cahce line length
4471 +__fa_cache_dsize:
4472 + .word 0 @ data cache size
4473 +
4474 +/* Luke Lee 04/06/2005 ins end */
4475 +
4476 +/*
4477 + * flush_user_cache_all()
4478 + *
4479 + * Clean and invalidate all cache entries in a particular address
4480 + * space.
4481 + */
4482 +ENTRY(fa_flush_user_cache_all)
4483 + /* FALLTHROUGH */
4484 +/*
4485 + * flush_kern_cache_all()
4486 + *
4487 + * Clean and invalidate the entire cache.
4488 + */
4489 +ENTRY(fa_flush_kern_cache_all)
4490 +/* Luke Lee 04/06/2005 mod ok */
4491 + mov ip, #0
4492 +
4493 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4494 + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
4495 +#endif
4496 +
4497 +__flush_whole_cache:
4498 +
4499 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4500 + mov ip, #0
4501 +# ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4502 + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
4503 +# else
4504 + mcr p15, 0, ip, c7,c14, 0 @ clean/invalidate D cache
4505 +# endif
4506 +#endif /*CONFIG_CPU_DCACHE_DISABLE*/
4507 +
4508 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4509 + mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
4510 +#endif
4511 +
4512 +#ifdef CONFIG_CPU_FA_BTB
4513 + mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB
4514 + nop
4515 + nop
4516 +#endif
4517 +
4518 +/* Luke Lee 04/06/2005 que todo tofix : should iscratchpad and dscratchpad be invalidated ? */
4519 + mov pc, lr
4520 +
4521 +/*
4522 + * flush_user_cache_range(start, end, flags)
4523 + *
4524 + * Invalidate a range of cache entries in the specified
4525 + * address space.
4526 + *
4527 + * - start - start address (inclusive, page aligned)
4528 + * - end - end address (exclusive, page aligned)
4529 + * - flags - vma_area_struct flags describing address space
4530 + */
4531 +ENTRY(fa_flush_user_cache_range)
4532 +
4533 +/* Luke Lee 04/06/2005 mod ok */
4534 + /* Luke Lee 04/07/2005 ins 1 */
4535 + mov ip, #0
4536 + sub r3, r1, r0 @ calculate total size
4537 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4538 + tst r2, #VM_EXEC @ executable region?
4539 + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
4540 +#endif
4541 +
4542 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4543 + /* Luke Lee 04/06/2005 ins 2 mod 1 */
4544 + cmp r3, #CACHE_DSIZE @ total size >= limit?
4545 + bhs __flush_whole_cache @ flush whole D cache
4546 +
4547 + //debug_Aaron
4548 + bic r0, r0, #CACHE_DLINESIZE-1
4549 + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate boundary D entry
4550 + bic r1, r1, #CACHE_DLINESIZE-1
4551 + mcr p15, 0, r1, c7, c14, 1 @ clean and invalidate boundary D entry
4552 +
4553 +
4554 +1: /* Luke Lee 04/06/2005 del 2 ins 5 */
4555 +
4556 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4557 + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
4558 +#else
4559 + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
4560 +#endif
4561 + /* Luke Lee 04/06/2005 mod 1 */
4562 + add r0, r0, #CACHE_DLINESIZE
4563 + cmp r0, r1
4564 + bls 1b @ Luke Lee 05/19/2005
4565 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4566 +
4567 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4568 + tst r2, #VM_EXEC
4569 + /* Luke Lee 04/06/2005 mod 1 tofix todo : ne->eq */
4570 + mcreq p15, 0, r4, c7, c10, 4 @ drain write buffer
4571 +#endif
4572 +
4573 + /* Luke Lee 04/06/2005 ins block */
4574 +#ifdef CONFIG_CPU_FA_BTB
4575 + tst r2, #VM_EXEC
4576 + mov ip, #0
4577 + mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
4578 + nop
4579 + nop
4580 +#endif
4581 + mov pc, lr
4582 +
4583 +/*
4584 + * flush_kern_dcache_page(void *page)
4585 + *
4586 + * Ensure no D cache aliasing occurs, either with itself or
4587 + * the I cache
4588 + *
4589 + * - addr - page aligned address
4590 + */
4591 +ENTRY(fa_flush_kern_dcache_page)
4592 + add r1, r0, #PAGE_SZ
4593 + /* fall through */
4594 +
4595 +/*
4596 + * coherent_kern_range(start, end)
4597 + *
4598 + * Ensure coherency between the Icache and the Dcache in the
4599 + * region described by start. If you have non-snooping
4600 + * Harvard caches, you need to implement this function.
4601 + *
4602 + * - start - virtual start address
4603 + * - end - virtual end address
4604 + */
4605 +ENTRY(fa_coherent_kern_range)
4606 + /* fall through */
4607 +
4608 +/*
4609 + * coherent_user_range(start, end)
4610 + *
4611 + * Ensure coherency between the Icache and the Dcache in the
4612 + * region described by start. If you have non-snooping
4613 + * Harvard caches, you need to implement this function.
4614 + *
4615 + * - start - virtual start address
4616 + * - end - virtual end address
4617 + */
4618 +ENTRY(fa_coherent_user_range)
4619 +
4620 +/* Luke Lee 04/06/2005 mod ok */
4621 + /* Luke Lee 04/06/2005 ins 3 mod 1 */
4622 + bic r0, r0, #CACHE_DLINESIZE-1
4623 +
4624 + //debug_Aaron
4625 + bic r0, r0, #CACHE_DLINESIZE-1
4626 + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate boundary D entry
4627 + bic r1, r1, #CACHE_DLINESIZE-1
4628 + mcr p15, 0, r1, c7, c14, 1 @ clean and invalidate boundary D entry
4629 +
4630 +#if !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE))
4631 +1: /* Luke Lee 04/06/2005 del 2 ins 5 mod 1 */
4632 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4633 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4634 + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
4635 +#else
4636 + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
4637 +#endif
4638 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4639 +
4640 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4641 + mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
4642 +#endif
4643 + add r0, r0, #CACHE_DLINESIZE
4644 + cmp r0, r1
4645 + bls 1b @ Luke Lee 05/19/2005 blo->bls
4646 +#endif /* !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) */
4647 +
4648 + mov ip, #0
4649 +#ifdef CONFIG_CPU_FA_BTB
4650 + mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB
4651 + nop
4652 + nop
4653 +#endif
4654 +
4655 +/* Luke Lee 04/08/2005 ins 1 skp 1 ins 1 */
4656 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4657 + mcr p15, 0, ip, c7, c10, 4 @ drain WB
4658 +#endif
4659 +
4660 + mov pc, lr
4661 +
4662 +/*
4663 + * dma_inv_range(start, end)
4664 + *
4665 + * Invalidate (discard) the specified virtual address range.
4666 + * May not write back any entries. If 'start' or 'end'
4667 + * are not cache line aligned, those lines must be written
4668 + * back.
4669 + *
4670 + * - start - virtual start address
4671 + * - end - virtual end address
4672 + */
4673 +ENTRY(fa_dma_inv_range)
4674 +
4675 +/* Luke Lee 04/06/2005 mod ok */
4676 +
4677 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4678 +
4679 + //debug_Aaron
4680 + bic r0, r0, #CACHE_DLINESIZE-1
4681 + mcr p15, 0, r0, c7, c6, 1 @ invalidate boundary D entry
4682 + bic r1, r1, #CACHE_DLINESIZE-1
4683 + mcr p15, 0, r1, c7, c6, 1 @ invalidate boundary D entry
4684 +
4685 + /* Luke Lee 04/06/2005 ins 4 mod 2 */
4686 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
4687 + tst r0, #CACHE_DLINESIZE -1
4688 + bic r0, r0, #CACHE_DLINESIZE -1
4689 +
4690 +//debug_Aaron
4691 + //mcrne p15, 0, r0, c7, c10, 1 @ clean boundary D entry
4692 +
4693 + /* Luke Lee 04/06/2005 mod 1 */
4694 + /* Luke Lee 05/19/2005 always clean the end-point boundary mcrne->mcr */
4695 + ////tst r1, #CACHE_DLINESIZE -1
4696 + //mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry
4697 + /* Luke Lee 04/06/2005 ins 1 */
4698 +#else
4699 + bic r0, r0, #CACHE_DLINESIZE -1
4700 +#endif
4701 +
4702 +//debug_Aaron
4703 +1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
4704 +//1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
4705 +
4706 + /* Luke Lee 04/06/2005 mod 1 */
4707 + add r0, r0, #CACHE_DLINESIZE
4708 + cmp r0, r1
4709 + bls 1b @ Luke Lee 05/19/2005 blo->bls
4710 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4711 +
4712 + /* Luke Lee 04/06/2005 ins 1 */
4713 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4714 + mov r0, #0
4715 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
4716 +#endif
4717 +
4718 + mov pc, lr
4719 +
4720 +/*
4721 + * dma_clean_range(start, end)
4722 + *
4723 + * Clean (write back) the specified virtual address range.
4724 + *
4725 + * - start - virtual start address
4726 + * - end - virtual end address
4727 + */
4728 +ENTRY(fa_dma_clean_range)
4729 +
4730 +/* Luke Lee 04/06/2005 mod ok */
4731 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4732 +
4733 + //debug_Aaron
4734 + bic r0, r0, #CACHE_DLINESIZE-1
4735 + mcr p15, 0, r0, c7, c10, 1 @ clean boundary D entry
4736 + bic r1, r1, #CACHE_DLINESIZE-1
4737 + mcr p15, 0, r1, c7, c10, 1 @ clean boundary D entry
4738 +
4739 + /* Luke Lee 04/06/2005 ins 4 mod 2 */
4740 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
4741 + bic r0, r0, #CACHE_DLINESIZE - 1
4742 +
4743 +//debug_Aaron
4744 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
4745 +//1: mcr p15, 0, r0, c7, c14, 1 @ clean D entry
4746 + add r0, r0, #CACHE_DLINESIZE
4747 + cmp r0, r1
4748 + bls 1b @ Luke Lee 05/19/2005 blo->bls
4749 + /* Luke Lee 04/06/2005 ins 2 */
4750 +#endif
4751 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4752 +
4753 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4754 + mov r0, #0
4755 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
4756 +#endif
4757 +
4758 + mov pc, lr
4759 +
4760 +/*
4761 + * dma_flush_range(start, end)
4762 + *
4763 + * Clean and invalidate the specified virtual address range.
4764 + *
4765 + * - start - virtual start address
4766 + * - end - virtual end address
4767 + *
4768 + * This is actually the same as fa_coherent_kern_range()
4769 + */
4770 + .globl fa_dma_flush_range
4771 + .set fa_dma_flush_range, fa_coherent_kern_range
4772 +
4773 + __INITDATA
4774 +
4775 + .type fa_cache_fns, #object
4776 +ENTRY(fa_cache_fns)
4777 + .long fa_flush_kern_cache_all
4778 + .long fa_flush_user_cache_all
4779 + .long fa_flush_user_cache_range
4780 + .long fa_coherent_kern_range
4781 + .long fa_coherent_user_range
4782 + .long fa_flush_kern_dcache_page
4783 + .long fa_dma_inv_range
4784 + .long fa_dma_clean_range
4785 + .long fa_dma_flush_range
4786 + .size fa_cache_fns, . - fa_cache_fns
4787 --- /dev/null
4788 +++ b/arch/arm/mm/copypage-fa.S
4789 @@ -0,0 +1,106 @@
4790 +/*
4791 + * linux/arch/arm/lib/copypage-fa.S
4792 + *
4793 + * Copyright (C) 2005 Faraday Corp.
4794 + *
4795 + * This program is free software; you can redistribute it and/or modify
4796 + * it under the terms of the GNU General Public License version 2 as
4797 + * published by the Free Software Foundation.
4798 + *
4799 + * ASM optimised string functions
4800 + * 05/18/2005 : Luke Lee created, modified from copypage-v4wb.S
4801 + */
4802 +#include <linux/linkage.h>
4803 +#include <linux/init.h>
4804 +#include <asm/asm-offsets.h>
4805 +
4806 + .text
4807 +/*
4808 + * ARMv4 optimised copy_user_page for Faraday processors
4809 + *
4810 + * We flush the destination cache lines just before we write the data into the
4811 + * corresponding address. Since the Dcache is read-allocate, this removes the
4812 + * Dcache aliasing issue. The writes will be forwarded to the write buffer,
4813 + * and merged as appropriate.
4814 + *
4815 + * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
4816 + * instruction. If your processor does not supply this, you have to write your
4817 + * own copy_user_page that does the right thing.
4818 + *
4819 + * copy_user_page(to,from,vaddr)
4820 + */
4821 + .align 4
4822 +ENTRY(fa_copy_user_page)
4823 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4824 + /* Write through */
4825 + stmfd sp!, {r4, lr} @ 2
4826 + mov r2, #PAGE_SZ/32 @ 1
4827 +
4828 + ldmia r1!, {r3, r4, ip, lr} @ 4
4829 +1: stmia r0!, {r3, r4, ip, lr} @ 4
4830 + ldmia r1!, {r3, r4, ip, lr} @ 4+1
4831 + subs r2, r2, #1 @ 1
4832 + stmia r0!, {r3, r4, ip, lr} @ 4
4833 + ldmneia r1!, {r3, r4, ip, lr} @ 4
4834 + bne 1b @ 1
4835 +
4836 + mcr p15, 0, r2, c7, c7, 0 @ flush ID cache
4837 + ldmfd sp!, {r4, pc} @ 3
4838 +#else
4839 + /* Write back */
4840 + stmfd sp!, {r4, lr} @ 2
4841 + mov r2, #PAGE_SZ/32 @ 1
4842 +
4843 +1: ldmia r1!, {r3, r4, ip, lr} @ 4
4844 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
4845 + stmia r0!, {r3, r4, ip, lr} @ 4
4846 + ldmia r1!, {r3, r4, ip, lr} @ 4
4847 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
4848 + stmia r0!, {r3, r4, ip, lr} @ 4
4849 + subs r2, r2, #1 @ 1
4850 + bne 1b
4851 + mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB
4852 + ldmfd sp!, {r4, pc} @ 3
4853 +#endif
4854 +
4855 +/*
4856 + * ARMv4 optimised clear_user_page
4857 + *
4858 + * Same story as above.
4859 + */
4860 + .align 4
4861 +ENTRY(fa_clear_user_page)
4862 + str lr, [sp, #-4]!
4863 + mov r1, #PAGE_SZ/32 @ 1
4864 + mov r2, #0 @ 1
4865 + mov r3, #0 @ 1
4866 + mov ip, #0 @ 1
4867 + mov lr, #0 @ 1
4868 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4869 + /* Write through */
4870 +1: stmia r0!, {r2, r3, ip, lr} @ 4
4871 + stmia r0!, {r2, r3, ip, lr} @ 4
4872 + subs r1, r1, #1 @ 1
4873 + bne 1b @ 1
4874 +
4875 + mcr p15, 0, r1, c7, c7, 0 @ flush ID cache
4876 + ldr pc, [sp], #4
4877 +#else
4878 + /* Write back */
4879 +1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
4880 + stmia r0!, {r2, r3, ip, lr} @ 4
4881 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
4882 + stmia r0!, {r2, r3, ip, lr} @ 4
4883 + subs r1, r1, #1 @ 1
4884 + bne 1b @ 1
4885 + mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
4886 + ldr pc, [sp], #4
4887 +#endif
4888 +
4889 + __INITDATA
4890 +
4891 + .type fa_user_fns, #object
4892 +ENTRY(fa_user_fns)
4893 + .long fa_clear_user_page
4894 + .long fa_copy_user_page
4895 + .size fa_user_fns, . - fa_user_fns
4896 --- a/arch/arm/mm/init.c
4897 +++ b/arch/arm/mm/init.c
4898 @@ -23,6 +23,7 @@
4899
4900 #include <asm/mach/arch.h>
4901 #include <asm/mach/map.h>
4902 +#include <asm/arch/ipi.h>
4903
4904 #include "mm.h"
4905
4906 @@ -252,6 +253,11 @@
4907 initrd_end = initrd_start + phys_initrd_size;
4908 }
4909 #endif
4910 +#ifdef CONFIG_GEMINI_IPI
4911 + printk("CPU ID:%d\n",getcpuid());
4912 +// reserve_bootmem_node(NODE_DATA(0), 0x400000, 0x400000); //CPU0 space
4913 +// reserve_bootmem_node(NODE_DATA(0), SHAREADDR, SHARE_MEM_SIZE); //share memory
4914 +#endif
4915
4916 /*
4917 * Finally, reserve any node zero regions.
4918 --- /dev/null
4919 +++ b/arch/arm/mm/proc-fa526.S
4920 @@ -0,0 +1,407 @@
4921 +/*
4922 + * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
4923 + *
4924 + * Copyright (C) 2005 Faraday Corp.
4925 + *
4926 + * This program is free software; you can redistribute it and/or modify
4927 + * it under the terms of the GNU General Public License as published by
4928 + * the Free Software Foundation; either version 2 of the License, or
4929 + * (at your option) any later version.
4930 + *
4931 + * This program is distributed in the hope that it will be useful,
4932 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4933 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4934 + * GNU General Public License for more details.
4935 + *
4936 + * You should have received a copy of the GNU General Public License
4937 + * along with this program; if not, write to the Free Software
4938 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4939 + *
4940 + *
4941 + * These are the low level assembler for performing cache and TLB
4942 + * functions on the fa526.
4943 + *
4944 + * Written by : Luke Lee
4945 + */
4946 +#include <linux/linkage.h>
4947 +#include <linux/init.h>
4948 +#include <asm/assembler.h>
4949 +#include <asm/pgtable.h>
4950 +#include <asm/pgtable-hwdef.h>
4951 +#include <asm/elf.h>
4952 +#include <asm/hardware.h>
4953 +#include <asm/page.h>
4954 +#include <asm/ptrace.h>
4955 +#include <asm/system.h>
4956 +#include "proc-macros.S"
4957 +
4958 +#define CACHE_DLINESIZE 16
4959 +
4960 + .text
4961 +/*
4962 + * cpu_fa526_proc_init()
4963 + */
4964 +ENTRY(cpu_fa526_proc_init)
4965 + /* MMU is already ON here, ICACHE, DCACHE conditionally disabled */
4966 +
4967 + mov r0, #1
4968 + nop
4969 + nop
4970 + mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
4971 + nop
4972 + nop
4973 +
4974 + mrc p15, 0, r0, c1, c0, 0 @ read ctrl register
4975 +
4976 +#ifdef CONFIG_CPU_FA_BTB
4977 + orr r0, r0, #CR_Z
4978 +#else
4979 + bic r0, r0, #CR_Z
4980 +#endif
4981 +#ifdef CONFIG_CPU_FA_WB_DISABLE
4982 + mov r1, #0
4983 + mcr p15, 0, r1, c7, c10, 4 @ drain write buffer
4984 + nop
4985 + nop
4986 + bic r0, r0, #CR_W
4987 +#else
4988 + orr r0, r0, #CR_W
4989 +#endif
4990 +#ifdef CONFIG_CPU_DCACHE_DISABLE
4991 + bic r0, r0, #CR_C
4992 +#else
4993 + orr r0, r0, #CR_C
4994 +#endif
4995 +#ifdef CONFIG_CPU_ICACHE_DISABLE
4996 + bic r0, r0, #CR_I
4997 +#else
4998 + orr r0, r0, #CR_I
4999 +#endif
5000 +
5001 + nop
5002 + nop
5003 + mcr p15, 0, r0, c1, c0, 0
5004 + nop
5005 + nop
5006 +
5007 + mov r5, lr
5008 + bl fa_initialize_cache_info @ destroy r0~r4
5009 + mov pc, r5 @ return
5010 +
5011 +
5012 +/*
5013 + * cpu_fa526_proc_fin()
5014 + */
5015 +ENTRY(cpu_fa526_proc_fin)
5016 + stmfd sp!, {lr}
5017 + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
5018 + msr cpsr_c, ip
5019 +
5020 + bl fa_flush_kern_cache_all
5021 + mrc p15, 0, r0, c1, c0, 0 @ ctrl register
5022 + bic r0, r0, #0x1000 @ ...i............
5023 + bic r0, r0, #0x000e @ ............wca.
5024 + mcr p15, 0, r0, c1, c0, 0 @ disable caches
5025 +
5026 + nop
5027 + nop
5028 + ldmfd sp!, {pc}
5029 +
5030 +/*
5031 + * cpu_fa526_reset(loc)
5032 + *
5033 + * Perform a soft reset of the system. Put the CPU into the
5034 + * same state as it would be if it had been reset, and branch
5035 + * to what would be the reset vector.
5036 + *
5037 + * loc: location to jump to for soft reset
5038 + */
5039 + .align 4
5040 +ENTRY(cpu_fa526_reset)
5041 + mov ip, #0
5042 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
5043 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5044 + mcr p15, 0, ip, c7, c10, 4 @ drain WB
5045 +#endif
5046 + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
5047 + mrc p15, 0, ip, c1, c0, 0 @ ctrl register
5048 + bic ip, ip, #0x000f @ ............wcam
5049 + bic ip, ip, #0x1100 @ ...i...s........
5050 +
5051 + bic ip, ip, #0x0800 @ BTB off
5052 + mcr p15, 0, ip, c1, c0, 0 @ ctrl register
5053 + nop
5054 + nop
5055 + mov pc, r0
5056 +
5057 +/*
5058 + * cpu_fa526_do_idle()
5059 + */
5060 + .align 4
5061 +ENTRY(cpu_fa526_do_idle)
5062 +
5063 +#ifdef CONFIG_CPU_FA_IDLE
5064 + nop
5065 + nop
5066 + mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt (IDLE mode)
5067 +#endif
5068 + mov pc, lr
5069 +
5070 +
5071 +ENTRY(cpu_fa526_dcache_clean_area)
5072 +
5073 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5074 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
5075 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
5076 + add r0, r0, #CACHE_DLINESIZE
5077 + subs r1, r1, #CACHE_DLINESIZE
5078 + bhi 1b
5079 +#endif
5080 +#endif
5081 + mov pc, lr
5082 +
5083 +
5084 +/* =============================== PageTable ============================== */
5085 +
5086 +/*
5087 + * cpu_fa526_switch_mm(pgd)
5088 + *
5089 + * Set the translation base pointer to be as described by pgd.
5090 + *
5091 + * pgd: new page tables
5092 + */
5093 + .align 4
5094 +
5095 + .globl fault_address
5096 +fault_address:
5097 + .long 0
5098 +
5099 +ENTRY(cpu_fa526_switch_mm)
5100 +
5101 + mov ip, #0
5102 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5103 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5104 + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
5105 +#else
5106 + mcr p15, 0, ip, c7, c14, 0 @ Clean and invalidate whole DCache
5107 +#endif
5108 +#endif /*CONFIG_CPU_DCACHE_DISABLE*/
5109 +
5110 +#ifndef CONFIG_CPU_ICACHE_DISABLE
5111 + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
5112 +#endif
5113 +
5114 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5115 + mcr p15, 0, ip, c7, c10, 4 @ drain WB
5116 +#endif
5117 +
5118 +#ifdef CONFIG_CPU_FA_BTB
5119 + mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
5120 + nop
5121 + nop
5122 +#endif
5123 + bic r0, r0, #0xff @ clear bits [7:0]
5124 + bic r0, r0, #0x3f00 @ clear bits [13:8]
5125 + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
5126 + mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
5127 + nop
5128 + nop
5129 + mov pc, lr
5130 +
5131 +/*
5132 + * cpu_fa526_set_pte_ext(ptep, pte, ext)
5133 + *
5134 + * Set a PTE and flush it out
5135 + */
5136 + .align 4
5137 +ENTRY(cpu_fa526_set_pte_ext)
5138 + str r1, [r0], #-2048 @ linux version
5139 +
5140 + eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
5141 +
5142 + bic r2, r1, #PTE_SMALL_AP_MASK
5143 + bic r2, r2, #PTE_TYPE_MASK
5144 + orr r2, r2, #PTE_TYPE_SMALL
5145 +
5146 + tst r1, #L_PTE_USER @ User?
5147 + orrne r2, r2, #PTE_SMALL_AP_URO_SRW
5148 +
5149 + tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
5150 + orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
5151 +
5152 + tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
5153 + movne r2, #0
5154 +
5155 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5156 + eor r3, r2, #0x0a @ C & small page? 1010
5157 + tst r3, #0x0b @ 1011
5158 + biceq r2, r2, #4
5159 +#endif
5160 + str r2, [r0] @ hardware version
5161 +
5162 + mov r2, #0
5163 + mcr p15, 0, r2, c7, c10, 0 @ clean D cache all
5164 +
5165 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5166 + mcr p15, 0, r2, c7, c10, 4 @ drain WB
5167 +#endif
5168 +#ifdef CONFIG_CPU_FA_BTB
5169 + mcr p15, 0, r2, c7, c5, 6 @ invalidate BTB
5170 + nop
5171 + nop
5172 +#endif
5173 + mov pc, lr
5174 +
5175 + __INIT
5176 +
5177 + .type __fa526_setup, #function
5178 +__fa526_setup:
5179 + /* On return of this routine, r0 must carry correct flags for CFG register */
5180 + mov r0, #0
5181 + mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
5182 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
5183 + mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
5184 +
5185 + mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
5186 +
5187 + mov r0, #1
5188 + mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
5189 +
5190 + mrc p15, 0, r0, c9, c1, 0 @ DScratchpad
5191 + bic r0, r0, #1
5192 + mcr p15, 0, r0, c9, c1, 0
5193 + mrc p15, 0, r0, c9, c1, 1 @ IScratchpad
5194 + bic r0, r0, #1
5195 + mcr p15, 0, r0, c9, c1, 1
5196 +
5197 + mov r0, #0
5198 + mcr p15, 0, r0, c1, c1, 0 @ turn-off ECR
5199 +
5200 +#ifdef CONFIG_CPU_FA_BTB
5201 + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
5202 + nop
5203 + nop
5204 +#endif
5205 +
5206 + mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
5207 + mcr p15, 0, r0, c3, c0 @ load domain access register
5208 +
5209 + mrc p15, 0, r0, c1, c0 @ get control register v4
5210 + ldr r5, fa526_cr1_clear
5211 + bic r0, r0, r5
5212 + ldr r5, fa526_cr1_set
5213 + orr r0, r0, r5
5214 +
5215 +#ifdef CONFIG_CPU_FA_BTB
5216 + orr r0, r0, #CR_Z
5217 +#else
5218 + bic r0, r0, #CR_Z
5219 +#endif
5220 +#ifdef CONFIG_CPU_FA_WB_DISABLE
5221 + mov r12, #0
5222 + mcr p15, 0, r12, c7, c10, 4 @ drain write buffer
5223 + nop
5224 + nop
5225 + bic r0, r0, #CR_W @ .... .... .... 1...
5226 +#else
5227 + orr r0, r0, #CR_W
5228 +#endif
5229 +
5230 + mov pc, lr
5231 + .size __fa526_setup, . - __fa526_setup
5232 +
5233 + /*
5234 + * .RVI ZFRS BLDP WCAM
5235 + * ..11 0001 .111 1101
5236 + *
5237 + */
5238 + .type fa526_cr1_clear, #object
5239 + .type fa526_cr1_set, #object
5240 +fa526_cr1_clear:
5241 + .word 0x3f3f
5242 +fa526_cr1_set:
5243 + .word 0x317D
5244 +
5245 + __INITDATA
5246 +
5247 +/*
5248 + * Purpose : Function pointers used to access above functions - all calls
5249 + * come through these
5250 + */
5251 + .type fa526_processor_functions, #object
5252 +fa526_processor_functions:
5253 + .word v4_early_abort
5254 + .word cpu_fa526_proc_init
5255 + .word cpu_fa526_proc_fin
5256 + .word cpu_fa526_reset
5257 + .word cpu_fa526_do_idle
5258 + .word cpu_fa526_dcache_clean_area
5259 + .word cpu_fa526_switch_mm
5260 + .word cpu_fa526_set_pte_ext
5261 + .size fa526_processor_functions, . - fa526_processor_functions
5262 +
5263 + .section ".rodata"
5264 +
5265 + .type cpu_arch_name, #object
5266 +cpu_arch_name:
5267 + .asciz "armv4"
5268 + .size cpu_arch_name, . - cpu_arch_name
5269 +
5270 + .type cpu_elf_name, #object
5271 +cpu_elf_name:
5272 + .asciz "v4"
5273 + .size cpu_elf_name, . - cpu_elf_name
5274 +
5275 + .type cpu_fa526_name, #object
5276 +cpu_fa526_name:
5277 + .ascii "FA526"
5278 +#ifndef CONFIG_CPU_ICACHE_DISABLE
5279 + .ascii "i"
5280 +#endif
5281 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5282 + .ascii "d"
5283 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5284 + .ascii "(wt)"
5285 +#else
5286 + .ascii "(wb)"
5287 +#endif
5288 +#endif
5289 + .ascii "\0"
5290 + .size cpu_fa526_name, . - cpu_fa526_name
5291 +
5292 + .align
5293 +
5294 + .section ".proc.info.init", #alloc, #execinstr
5295 +
5296 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5297 +#define __PMD_SECT_BUFFERABLE 0
5298 +#else
5299 +#define __PMD_SECT_BUFFERABLE PMD_SECT_BUFFERABLE
5300 +#endif
5301 +
5302 + .type __fa526_proc_info,#object
5303 +__fa526_proc_info:
5304 + .long 0x66015261
5305 + .long 0xff01fff1
5306 + .long PMD_TYPE_SECT | \
5307 + __PMD_SECT_BUFFERABLE | \
5308 + PMD_SECT_CACHEABLE | \
5309 + PMD_BIT4 | \
5310 + PMD_SECT_AP_WRITE | \
5311 + PMD_SECT_AP_READ
5312 + .long PMD_TYPE_SECT | \
5313 + PMD_BIT4 | \
5314 + PMD_SECT_AP_WRITE | \
5315 + PMD_SECT_AP_READ
5316 + b __fa526_setup
5317 + .long cpu_arch_name
5318 + .long cpu_elf_name
5319 + .long HWCAP_SWP | HWCAP_HALF
5320 + .long cpu_fa526_name
5321 + .long fa526_processor_functions
5322 + .long fa_tlb_fns
5323 + .long fa_user_fns
5324 + .long fa_cache_fns
5325 + .size __fa526_proc_info, . - __fa526_proc_info
5326 +
5327 +
5328 --- /dev/null
5329 +++ b/arch/arm/mm/tlb-fa.S
5330 @@ -0,0 +1,96 @@
5331 +/*
5332 + * linux/arch/arm/mm/tlb-fa.S
5333 + *
5334 + * Copyright (C) 2005 Faraday Corp.
5335 + *
5336 + * This program is free software; you can redistribute it and/or modify
5337 + * it under the terms of the GNU General Public License version 2 as
5338 + * published by the Free Software Foundation.
5339 + *
5340 + * ARM architecture version 4, Faraday variation.
5341 + * This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
5342 + *
5343 + * Processors: FA520 FA526 FA626
5344 + * 03/31/2005 : Created by Luke Lee, modified from tlb-v4wbi.S
5345 + * 05/06/2005 : Fixed buggy CPU versions that did not invalidate the associated
5346 + * data cache entries when invalidating TLB entries.
5347 + */
5348 +#include <linux/linkage.h>
5349 +#include <linux/init.h>
5350 +#include <asm/asm-offsets.h>
5351 +#include <asm/tlbflush.h>
5352 +#include "proc-macros.S"
5353 +
5354 +
5355 +/*
5356 + * flush_user_tlb_range(start, end, mm)
5357 + *
5358 + * Invalidate a range of TLB entries in the specified address space.
5359 + *
5360 + * - start - range start address
5361 + * - end - range end address
5362 + * - mm - mm_struct describing address space
5363 + */
5364 + .align 4
5365 +ENTRY(fa_flush_user_tlb_range)
5366 +
5367 + vma_vm_mm ip, r2
5368 + act_mm r3 @ get current->active_mm
5369 + eors r3, ip, r3 @ == mm ?
5370 + movne pc, lr @ no, we dont do anything
5371 + mov r3, #0
5372 +
5373 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5374 + mcr p15, 0, r3, c7, c10, 4 @ drain WB
5375 +#endif
5376 +
5377 + vma_vm_flags r2, r2
5378 + bic r0, r0, #0x0ff
5379 + bic r0, r0, #0xf00
5380 +
5381 +1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
5382 + add r0, r0, #PAGE_SZ
5383 + cmp r0, r1
5384 + bls 1b @ Luke Lee 05/19/2005 blo -> bls
5385 +
5386 +#ifdef CONFIG_CPU_FA_BTB
5387 + mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
5388 + nop
5389 + nop
5390 +#endif
5391 + mov pc, lr
5392 +
5393 +
5394 +ENTRY(fa_flush_kern_tlb_range)
5395 + mov r3, #0
5396 +
5397 + mcr p15, 0, r3, c7, c10, 0 @ clean Dcache all 06/03/2005
5398 +
5399 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5400 + mcr p15, 0, r3, c7, c10, 4 @ drain WB
5401 +#endif
5402 +
5403 + bic r0, r0, #0x0ff
5404 + bic r0, r0, #0xf00
5405 +1:
5406 + mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
5407 + add r0, r0, #PAGE_SZ
5408 + cmp r0, r1
5409 + bls 1b @ Luke Lee 05/19/2005 blo -> bls
5410 +
5411 +#ifdef CONFIG_CPU_FA_BTB
5412 + mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
5413 + nop
5414 + nop
5415 +#endif
5416 + mov pc, lr
5417 +
5418 +
5419 + __INITDATA
5420 +
5421 + .type fa_tlb_fns, #object
5422 +ENTRY(fa_tlb_fns)
5423 + .long fa_flush_user_tlb_range
5424 + .long fa_flush_kern_tlb_range
5425 + .long fa_tlb_flags
5426 + .size fa_tlb_fns, . - fa_tlb_fns
5427 --- a/arch/arm/tools/mach-types
5428 +++ b/arch/arm/tools/mach-types
5429 @@ -208,7 +208,8 @@
5430 fester SA1100_FESTER FESTER 191
5431 gpi ARCH_GPI GPI 192
5432 smdk2410 ARCH_SMDK2410 SMDK2410 193
5433 -i519 ARCH_I519 I519 194
5434 +#i519 ARCH_I519 I519 194
5435 +sl2312 ARCH_SL2312 SL2312 194
5436 nexio SA1100_NEXIO NEXIO 195
5437 bitbox SA1100_BITBOX BITBOX 196
5438 g200 SA1100_G200 G200 197
5439 --- /dev/null
5440 +++ b/include/asm-arm/arch-sl2312/SL_gpio.h
5441 @@ -0,0 +1,59 @@
5442 +#define GPIO_MINOR_LAST 31
5443 +#define GPIO_MAJOR 120 // Experiemental
5444 +
5445 +#define GPIO_IRQ_NBR 12
5446 +
5447 +#define GPIOBASEADDR (IO_ADDRESS(0x021000000))
5448 +
5449 +#define GPIODATAOUTOFF 0x00
5450 +#define GPIODATAINOFF 0x04
5451 +#define GPIOPINDIROFF 0x08
5452 +#define GPIOPINBYPASSOFF 0x0C
5453 +#define GPIODATASETOFF 0x10
5454 +#define GPIODATACLEAROFF 0x14
5455 +#define GPIOPINPULLENBOFF 0x18
5456 +#define GPIOPINPULLTPOFF 0x1C
5457 +#define GPIOINTRENBOFF 0x20
5458 +#define GPIOINTRRAWSOFF 0x24
5459 +#define GPIOINTRMASKEDSTATEOFF 0x28
5460 +#define GPIOINTRMASKOFF 0x2C
5461 +#define GPIOINTRCLEAROFF 0x30
5462 +#define GPIOINTRTRIGGEROFF 0x34
5463 +#define GPIOINTRBOTHOFF 0x38
5464 +#define GPIOINTRRISENEGOFF 0x3C
5465 +#define GPIOBNCEENBOFF 0x40
5466 +#define GPIOBNCEPRESOFF 0x44
5467 +
5468 +#define GPIO_IOCTRL_SETDIR 0x20
5469 +#define GPIO_IOCTRL_SET 0x40
5470 +#define GPIO_IOCTRL_CLEAR 0x50
5471 +#define GPIO_IOCTRL_ENBINT 0x60
5472 +#define GPIO_IOCTRL_MASKINT 0x70
5473 +#define GPIO_IOCTRL_LVLTRIG 0x75
5474 +#define GPIO_IOCTRL_EDGINT 0x77
5475 +#define GPIO_IOCTRL_EDGPOLINT 0x78
5476 +#define GPIO_IOCTRL_BYPASS 0x30
5477 +#define GPIO_IOCTRL_PRESCLK 0x80
5478 +#define GPIO_IOCTRL_CLKVAL 0x90
5479 +#define GPIO_IOCTRL_PULLENB 0xA0
5480 +#define GPIO_IOCTRL_PULLTYPE 0xA8
5481 +
5482 +
5483 +#define GPIO_MAJOR 120 /* experimental MAJOR number */
5484 + // Minor - 0 : 31 gpio pins
5485 +
5486 +#define GPIO_SET 0x01
5487 +#define GPIO_CLEAR 0x01
5488 +
5489 +#define GPIO_INPUT 0
5490 +#define GPIO_OUTPUT 1
5491 +#define GPIO_EDGEINTR 0
5492 +#define GPIO_EDGESINGL 0
5493 +#define GPIO_EDGEBOTH 1
5494 +#define GPIO_POSITIVE 0
5495 +#define GPIO_ENBINT 1
5496 +#define GPIO_DISABLEMASK 1
5497 +#define GPIO_PULLDOWN 0
5498 +#define GPIO_PULLUP 1
5499 +#define GPIO_ENABLEPULL 1
5500 +#define GPIO_DISABLEPULL 0
5501 --- /dev/null
5502 +++ b/include/asm-arm/arch-sl2312/debug-macro.S
5503 @@ -0,0 +1,20 @@
5504 +/* linux/include/asm-arm/arch-ebsa110/debug-macro.S
5505 + *
5506 + * Debugging macro include header
5507 + *
5508 + * Copyright (C) 1994-1999 Russell King
5509 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
5510 + *
5511 + * This program is free software; you can redistribute it and/or modify
5512 + * it under the terms of the GNU General Public License version 2 as
5513 + * published by the Free Software Foundation.
5514 + *
5515 +**/
5516 +
5517 + .macro addruart,rx
5518 + mov \rx, #0x42000000
5519 + .endm
5520 +
5521 +#define UART_SHIFT 2
5522 +#define FLOW_CONTROL
5523 +#include <asm/hardware/debug-8250.S>
5524 --- /dev/null
5525 +++ b/include/asm-arm/arch-sl2312/dma.h
5526 @@ -0,0 +1,28 @@
5527 +/*
5528 + * linux/include/asm-arm/arch-camelot/dma.h
5529 + *
5530 + * Copyright (C) 1997,1998 Russell King
5531 + *
5532 + * This program is free software; you can redistribute it and/or modify
5533 + * it under the terms of the GNU General Public License as published by
5534 + * the Free Software Foundation; either version 2 of the License, or
5535 + * (at your option) any later version.
5536 + *
5537 + * This program is distributed in the hope that it will be useful,
5538 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5539 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5540 + * GNU General Public License for more details.
5541 + *
5542 + * You should have received a copy of the GNU General Public License
5543 + * along with this program; if not, write to the Free Software
5544 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5545 + */
5546 +#ifndef __ASM_ARCH_DMA_H
5547 +#define __ASM_ARCH_DMA_H
5548 +
5549 +#define MAX_DMA_ADDRESS 0xffffffff
5550 +
5551 +#define MAX_DMA_CHANNELS 0
5552 +
5553 +#endif /* _ASM_ARCH_DMA_H */
5554 +
5555 --- /dev/null
5556 +++ b/include/asm-arm/arch-sl2312/entry-macro.S
5557 @@ -0,0 +1,42 @@
5558 +/*
5559 + * include/asm-arm/arch-arm/entry-macro.S
5560 + *
5561 + * Low-level IRQ helper macros for ebsa110 platform.
5562 + *
5563 + * This file is licensed under the terms of the GNU General Public
5564 + * License version 2. This program is licensed "as is" without any
5565 + * warranty of any kind, whether express or implied.
5566 + */
5567 +#include <asm/arch/platform.h>
5568 +#include <asm/arch/int_ctrl.h>
5569 +
5570 +
5571 + .macro disable_fiq
5572 + .endm
5573 +
5574 + .macro get_irqnr_preamble, base, tmp
5575 + .endm
5576 +
5577 + .macro arch_ret_to_user, tmp1, tmp2
5578 + .endm
5579 +
5580 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
5581 + ldr \irqstat, =IRQ_STATUS(IO_ADDRESS(SL2312_INTERRUPT_BASE))
5582 + ldr \irqnr,[\irqstat]
5583 + cmp \irqnr,#0
5584 + beq 2313f
5585 + mov \tmp,\irqnr
5586 + mov \irqnr,#0
5587 +2312:
5588 + tst \tmp, #1
5589 + bne 2313f
5590 + add \irqnr, \irqnr, #1
5591 + mov \tmp, \tmp, lsr #1
5592 + cmp \irqnr, #31
5593 + bcc 2312b
5594 +2313:
5595 + .endm
5596 +
5597 + .macro irq_prio_table
5598 + .endm
5599 +
5600 --- /dev/null
5601 +++ b/include/asm-arm/arch-sl2312/flash.h
5602 @@ -0,0 +1,83 @@
5603 +#ifndef __ASM_ARM_ARCH_FLASH_H
5604 +#define __ASM_ARM_ARCH_FLASH_H
5605 +
5606 +#define FLASH_START SL2312_FLASH_BASE
5607 +#define SFLASH_SIZE 0x00400000
5608 +#define SPAGE_SIZE 0x200
5609 +#define BLOCK_ERASE 0x50
5610 +#define BUFFER1_READ 0x54
5611 +#define BUFFER2_READ 0x56
5612 +#define PAGE_ERASE 0x81
5613 +#define MAIN_MEMORY_PAGE_READ 0x52
5614 +#define MAIN_MEMORY_PROGRAM_BUFFER1 0x82
5615 +#define MAIN_MEMORY_PROGRAM_BUFFER2 0x85
5616 +#define BUFFER1_TO_MAIN_MEMORY 0x83
5617 +#define BUFFER2_TO_MAIN_MEMORY 0x86
5618 +#define MAIN_MEMORY_TO_BUFFER1 0x53
5619 +#define MAIN_MEMORY_TO_BUFFER2 0x55
5620 +#define BUFFER1_WRITE 0x84
5621 +#define BUFFER2_WRITE 0x87
5622 +#define AUTO_PAGE_REWRITE_BUFFER1 0x58
5623 +#define AUTO_PAGE_REWRITE_BUFFER2 0x59
5624 +#define READ_STATUS 0x57
5625 +
5626 +#define MAIN_MEMORY_PAGE_READ_SPI 0xD2
5627 +#define BUFFER1_READ_SPI 0xD4
5628 +#define BUFFER2_READ_SPI 0xD6
5629 +#define READ_STATUS_SPI 0xD7
5630 +
5631 +#define FLASH_ACCESS_OFFSET 0x00000010
5632 +#define FLASH_ADDRESS_OFFSET 0x00000014
5633 +#define FLASH_WRITE_DATA_OFFSET 0x00000018
5634 +#define FLASH_READ_DATA_OFFSET 0x00000018
5635 +#define SERIAL_FLASH_CHIP1_EN 0x00010000 // 16th bit = 1
5636 +#define SERIAL_FLASH_CHIP0_EN 0x00000000 // 16th bit = 0
5637 +#define AT45DB321_PAGE_SHIFT 0xa
5638 +#define AT45DB642_PAGE_SHIFT 0xb
5639 +#define CONTINUOUS_MODE 0x00008000
5640 +
5641 +#define FLASH_ACCESS_ACTION_OPCODE 0x0000
5642 +#define FLASH_ACCESS_ACTION_OPCODE_DATA 0x0100
5643 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS 0x0200
5644 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA 0x0300
5645 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA 0x0400
5646 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_2X_DATA 0x0500
5647 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_3X_DATA 0x0600
5648 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA 0x0700
5649 +//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA 0x0600
5650 +//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA 0x0700
5651 +
5652 +#define M25P80_PAGE_SIZE 0x100
5653 +#define M25P80_SECTOR_SIZE 0x10000
5654 +
5655 +
5656 +//#define M25P80_BULK_ERASE 1
5657 +//#define M25P80_SECTOR_ERASE 2
5658 +//#define M25P80_SECTOR_SIZE 0x10000
5659 +
5660 +#define M25P80_WRITE_ENABLE 0x06
5661 +#define M25P80_WRITE_DISABLE 0x04
5662 +#define M25P80_READ_STATUS 0x05
5663 +#define M25P80_WRITE_STATUS 0x01
5664 +#define M25P80_READ 0x03
5665 +#define M25P80_FAST_READ 0x0B
5666 +#define M25P80_PAGE_PROGRAM 0x02
5667 +#define M25P80_SECTOR_ERASE 0xD8
5668 +#define M25P80_BULK_ERASE 0xC7
5669 +#define FLASH_ERR_OK 0x0
5670 +
5671 +extern void address_to_page(__u32, __u16 *, __u16 *);
5672 +extern void main_memory_page_read(__u8, __u16, __u16, __u8 *);
5673 +extern void buffer_to_main_memory(__u8, __u16);
5674 +extern void main_memory_to_buffer(__u8, __u16);
5675 +extern void main_memory_page_program(__u8, __u16, __u16, __u8);
5676 +extern void atmel_flash_read_page(__u32, __u8 *, __u32);
5677 +extern void atmel_erase_page(__u8, __u16);
5678 +extern void atmel_read_status(__u8, __u8 *);
5679 +extern void atmel_flash_program_page(__u32, __u8 *, __u32);
5680 +extern void atmel_buffer_write(__u8, __u16, __u8);
5681 +extern void flash_delay(void);
5682 +
5683 +extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
5684 +
5685 +#endif
5686 --- /dev/null
5687 +++ b/include/asm-arm/arch-sl2312/gemini_cir.h
5688 @@ -0,0 +1,102 @@
5689 +#ifndef _ASM_ARCH_CIR_H
5690 +#define _ASM_ARCH_CIR_H
5691 +#include <linux/ioctl.h>
5692 +
5693 +#define VCR_KEY_POWER 0x613E609F
5694 +#define TV1_KEY_POWER 0x40040100
5695 +#define TV1_KEY_POWER_EXT 0xBCBD
5696 +#define RC5_KER_POWER 0x0CF3
5697 +
5698 +#define VCC_H_ACT_PER (16-1)
5699 +#define VCC_L_ACT_PER (8-1)
5700 +#define VCC_DATA_LEN (32-1)
5701 +#define TV1_H_ACT_PER (8-1)
5702 +#define TV1_L_ACT_PER (4-1)
5703 +#define TV1_DATA_LEN (48-1)
5704 +
5705 +#define VCC_BAUD 540
5706 +#define TV1_BAUD 430
5707 +#ifdef CONFIG_SL3516_ASIC
5708 +#define EXT_CLK 60
5709 +#else
5710 +#define EXT_CLK 20
5711 +#endif
5712 +
5713 +#define NEC_PROTOCOL 0x0
5714 +#define RC5_PROTOCOL 0x1
5715 +#define VCC_PROTOCOL 0x0
5716 +#define TV1_PROTOCOL 0x01
5717 +
5718 +#ifndef SL2312_CIR_BASE
5719 +#define SL2312_CIR_BASE 0x4C000000
5720 +#endif
5721 +#define CIR_BASE_ADDR IO_ADDRESS(SL2312_CIR_BASE)
5722 +#define STORLINK_CIR_ID 0x00010400
5723 +
5724 +#define CIR_IP_ID *(volatile unsigned int *)(CIR_BASE_ADDR + 0x00)
5725 +#define CIR_CTR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x04)
5726 +#define CIR_STATUS_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x08)
5727 +#define CIR_RX_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x0C)
5728 +#define CIR_RX_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x10)
5729 +#define CIR_PWR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x14)
5730 +#define CIR_PWR_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x18)
5731 +#define CIR_TX_CTR_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x1C)
5732 +#define CIR_TX_FEQ_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x20)
5733 +#define CIR_TX_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x24)
5734 +#define CIR_TX_EXT_REG *(volatile unsigned int *)(CIR_BASE_ADDR + 0x28)
5735 +
5736 +
5737 +#ifndef SL2312_POWER_CTRL_BASE
5738 +#define SL2312_POWER_CTRL_BASE 0x4B000000
5739 +#endif
5740 +
5741 +#ifndef PWR_BASE_ADDR
5742 +#define PWR_BASE_ADDR IO_ADDRESS(SL2312_POWER_CTRL_BASE)
5743 +#endif
5744 +#define PWR_CTRL_ID *(unsigned int*)(PWR_BASE_ADDR+0x00)
5745 +#define PWR_CTRL_REG *(unsigned int*)(PWR_BASE_ADDR+0x04)
5746 +#define PWR_STATUS_REG *(unsigned int*)(PWR_BASE_ADDR+0x08)
5747 +
5748 +
5749 +#define BIT(x) (1<<x)
5750 +#define TX_STATUS BIT(3)
5751 +
5752 +#define PWR_STAT_CIR 0x10
5753 +#define PWR_STAT_RTC 0x20
5754 +#define PWR_STAT_PUSH 0x40
5755 +#define PWR_SHUTDOWN 0x01
5756 +
5757 +#define CARR_FREQ 38000
5758 +
5759 +struct cir_ioctl_data {
5760 + __u32 data;
5761 +};
5762 +struct cir_ioctl_data48 {
5763 + __u32 timeout;
5764 + __u32 length;
5765 + __u8 ret;
5766 + __u32 data;
5767 + __u32 data_ext;
5768 +};
5769 +#define OLD_DATA 0
5770 +#define NEW_RECEIVE 1
5771 +
5772 +#define CIR_IOCTL_BASE ('I'|'R')
5773 +#define CIR_SET_BAUDRATE _IOW (CIR_IOCTL_BASE, 0, struct cir_ioctl_data)
5774 +#define CIR_SET_HIGH_PERIOD _IOW (CIR_IOCTL_BASE, 1, struct cir_ioctl_data)
5775 +#define CIR_SET_LOW_PERIOD _IOW (CIR_IOCTL_BASE, 2, struct cir_ioctl_data)
5776 +#define CIR_SET_PROTOCOL _IOW (CIR_IOCTL_BASE, 3, struct cir_ioctl_data)
5777 +#define CIR_SET_ENABLE_COMPARE _IOW (CIR_IOCTL_BASE, 4, struct cir_ioctl_data)
5778 +#define CIR_SET_ENABLE_DEMOD _IOW (CIR_IOCTL_BASE, 5, struct cir_ioctl_data)
5779 +#define CIR_SET_POWER_KEY _IOW (CIR_IOCTL_BASE, 6, struct cir_ioctl_data)
5780 +#define CIR_GET_BAUDRATE _IOR (CIR_IOCTL_BASE, 7, struct cir_ioctl_data)
5781 +#define CIR_GET_HIGH_PERIOD _IOR (CIR_IOCTL_BASE, 8 ,struct cir_ioctl_data)
5782 +#define CIR_GET_LOW_PERIOD _IOR (CIR_IOCTL_BASE, 9 ,struct cir_ioctl_data)
5783 +#define CIR_GET_PROTOCOL _IOR (CIR_IOCTL_BASE, 10, struct cir_ioctl_data)
5784 +#define CIR_GET_ENABLE_COMPARE _IOR (CIR_IOCTL_BASE, 11, struct cir_ioctl_data)
5785 +#define CIR_GET_ENABLE_DEMOD _IOR (CIR_IOCTL_BASE, 12, struct cir_ioctl_data)
5786 +#define CIR_GET_POWER_KEY _IOR (CIR_IOCTL_BASE, 13, struct cir_ioctl_data)
5787 +#define CIR_GET_DATA _IOWR (CIR_IOCTL_BASE, 14, struct cir_ioctl_data48)
5788 +#define CIR_WAIT_INT_DATA _IOWR (CIR_IOCTL_BASE, 15, struct cir_ioctl_data48)
5789 +
5790 +#endif //_ASM_ARCH_CIR_H
5791 --- /dev/null
5792 +++ b/include/asm-arm/arch-sl2312/gemini_gpio.h
5793 @@ -0,0 +1,77 @@
5794 +/*
5795 + * FILE NAME gemini_gpio.h
5796 + *
5797 + * BRIEF MODULE DESCRIPTION
5798 + * Generic Gemini GPIO
5799 + *
5800 + * Author: Storlink Software [Device driver]
5801 + * Jason Lee <jason@storlink.com.tw>
5802 + *
5803 + * Copyright 2005 Storlink Inc.
5804 + *
5805 + * This program is free software; you can redistribute it and/or modify it
5806 + * under the terms of the GNU General Public License as published by the
5807 + * Free Software Foundation; either version 2 of the License, or (at your
5808 + * option) any later version.
5809 + *
5810 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5811 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5812 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5813 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5814 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5815 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5816 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5817 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5818 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5819 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5820 + *
5821 + * You should have received a copy of the GNU General Public License along
5822 + * with this program; if not, write to the Free Software Foundation, Inc.,
5823 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5824 + */
5825 +
5826 +#ifndef __GEMINI_GPIO_H
5827 +#define __GEMINI_GPIO_H
5828 +
5829 +#include <linux/ioctl.h>
5830 +
5831 +#define STATUS_HIGH 1
5832 +#define STATUS_LOW 0
5833 +#define DIRECT_OUT 1
5834 +#define DIRECT_IN 0
5835 +
5836 +#define EDGE_TRIG 0
5837 +#define RISING_EDGE 0
5838 +#define FALL_EDGE 1
5839 +#define SINGLE_EDGE 0
5840 +#define BOTH_EDGE 1
5841 +
5842 +#define LEVEL_TRIG 1
5843 +#define HIGH_ACTIVE 0
5844 +#define LOW_ACTIVE 1
5845 +
5846 +struct gemini_gpio_ioctl_data {
5847 + __u32 pin;
5848 + __u8 status; // status or pin direction
5849 + // 0: status low or Input
5850 + // 1: status high or Output
5851 +
5852 + /* these member are used to config GPIO interrupt parameter */
5853 + __u8 use_default; // if not sure ,set this argument 1
5854 + __u8 trig_type; // 0/1:edge/level triger ?
5855 + __u8 trig_polar; // 0/1:rising/falling high/low active ?
5856 + __u8 trig_both; // 0/1:single/both detect both ?
5857 +};
5858 +
5859 +#define GEMINI_GPIO_IOCTL_BASE 'Z'
5860 +
5861 +#define GEMINI_SET_GPIO_PIN_DIR _IOW (GEMINI_GPIO_IOCTL_BASE,16, struct gemini_gpio_ioctl_data)
5862 +#define GEMINI_SET_GPIO_PIN_STATUS _IOW (GEMINI_GPIO_IOCTL_BASE,17, struct gemini_gpio_ioctl_data)
5863 +#define GEMINI_GET_GPIO_PIN_STATUS _IOWR(GEMINI_GPIO_IOCTL_BASE,18, struct gemini_gpio_ioctl_data)
5864 +#define GEMINI_WAIT_GPIO_PIN_INT _IOWR(GEMINI_GPIO_IOCTL_BASE,19, struct gemini_gpio_ioctl_data)
5865 +
5866 +
5867 +extern void init_gpio_int(__u32 pin,__u8 trig_type,__u8 trig_polar,__u8 trig_both);
5868 +extern int request_gpio_irq(int bit,void (*handler)(int),char level,char high,char both);
5869 +extern int free_gpio_irq(int bit);
5870 +#endif
5871 --- /dev/null
5872 +++ b/include/asm-arm/arch-sl2312/gemini_i2s.h
5873 @@ -0,0 +1,169 @@
5874 +#ifndef __GEMINI_I2S_H__
5875 +#define __GEMINI_I2S_H__
5876 +#include <linux/ioctl.h>
5877 +#include <linux/types.h>
5878 +#include <asm/arch-sl2312/irqs.h>
5879 +
5880 +typedef __u16 UINT16;
5881 +typedef __u32 UINT32;
5882 +typedef __u8 UINT8;
5883 +typedef __u8 BOOL;
5884 +
5885 +/***************************************/
5886 +/* define GPIO module base address */
5887 +/***************************************/
5888 +#define DMA_CONTROL_PHY_BASE (IO_ADDRESS(SL2312_GENERAL_DMA_BASE))
5889 +#define DMA_CONTROL_SSP_BASE (IO_ADDRESS(SL2312_SSP_CTRL_BASE))
5890 +#define SSP_INT IRQ_SSP
5891 +#define GPIO_BASE_ADDR (IO_ADDRESS(SL2312_GPIO_BASE))
5892 +#define GPIO_BASE_ADDR1 (IO_ADDRESS(SL2312_GPIO_BASE1))
5893 +#define GLOBAL_BASE (IO_ADDRESS(SL2312_GLOBAL_BASE))
5894 +
5895 +/* define read/write register utility */
5896 +#define READ_SSP_REG(offset) (__raw_readl(offset+DMA_CONTROL_SSP_BASE))
5897 +#define WRITE_SSP_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE))
5898 +
5899 +#define READ_GPIO_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR))
5900 +#define WRITE_GPIO_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR))
5901 +
5902 +#define READ_GPIO1_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR1))
5903 +#define WRITE_GPIO1_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR1))
5904 +
5905 +#define READ_DMA_REG(offset) (__raw_readl(offset+DMA_CONTROL_PHY_BASE))
5906 +#define WRITE_DMA_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE))
5907 +
5908 +#define READ_GLOBAL_REG(offset) (__raw_readl(offset+GLOBAL_BASE))
5909 +#define WRITE_GLOBAL_REG(offset,val) (__raw_writel(val,offset+GLOBAL_BASE))
5910 +
5911 +#define SSP_GPIO_INT IRQ_GPIO
5912 +
5913 +#ifndef CONFIG_SL3516_ASIC
5914 +#define SSP_GPIO_INT_BIT 0x00000400 //GPIO[10] : SLIC interrupt pin
5915 +
5916 +#define GPIO_EECK 0x00000040 /* SCK: GPIO[06] */
5917 +#define GPIO_EECS 0x00000080 /* SCS: GPIO[07] */
5918 +#define GPIO_MISO 0x00000200 /* SDO: GPIO[09] receive from 6996*/
5919 +#define GPIO_MOSI 0x00000100 /* SDI: GPIO[08] send to 6996*/
5920 +#define GPIO_MISO_BIT 9
5921 +#else
5922 +#define SSP_GPIO_INT_BIT 0x00000001 //GPIO[0] : SLIC interrupt pin
5923 +
5924 +//#if 0
5925 +//#define GPIO_EECK 0x80000000 /* SCK: GPIO1[31] */
5926 +//#define GPIO_EECS 0x40000000 /* SCS: GPIO1[30] */
5927 +//#define GPIO_MISO 0x20000000 /* SDO: GPIO1[29] receive from 6996*/
5928 +//#define GPIO_MOSI 0x10000000 /* SDI: GPIO1[28] send to 6996*/
5929 +//#define GPIO_MISO_BIT 29
5930 +//#else
5931 +//#define GPIO_EECK 0x00000100 /* SCK: GPIO1[08] */
5932 +//#define GPIO_EECS 0x08000000 /* SCS: GPIO1[27] */
5933 +//#define GPIO_MISO 0x00000080 /* SDO: GPIO1[07] receive from 6996*/
5934 +//#define GPIO_MOSI 0x00000200 /* SDI: GPIO1[09] send to 6996*/
5935 +//#define GPIO_MISO_BIT 7
5936 +//#endif
5937 +#endif
5938 +
5939 +
5940 +enum GPIO_REG
5941 +{
5942 + GPIO_DATA_OUT = 0x00,
5943 + GPIO_DATA_IN = 0x04,
5944 + GPIO_PIN_DIR = 0x08,
5945 + GPIO_BY_PASS = 0x0c,
5946 + GPIO_DATA_SET = 0x10,
5947 + GPIO_DATA_CLEAR = 0x14,
5948 + GPIO_INT_ENABLE = 0x20,
5949 + GPIO_INT_RAWSTATE = 0x24,
5950 + GPIO_INT_MASKSTATE = 0x28,
5951 + GPIO_INT_MASK = 0x2C,
5952 + GPIO_INT_CLEAR = 0x30,
5953 + GPIO_INT_TRIGGER = 0x34,
5954 + GPIO_INT_BOTH = 0x38,
5955 + GPIO_INT_POLARITY = 0x3C
5956 +};
5957 +
5958 +typedef struct
5959 +{
5960 + UINT32 src_addr;
5961 + UINT32 dst_addr;
5962 + UINT32 llp;
5963 + UINT32 ctrl_size;
5964 + UINT32 owner;
5965 +}DMA_LLP_t;
5966 +
5967 +typedef struct
5968 +{
5969 + UINT32 owner;
5970 + UINT32 src_addr;
5971 + UINT32 ctrl_size;
5972 +}IOCTL_LLP_t;
5973 +
5974 +typedef unsigned char byte;
5975 +typedef unsigned short word;
5976 +typedef unsigned long dword;
5977 +
5978 +/* DMA Registers */
5979 +#define DMA_INT 0x00000000
5980 +#define DMA_INT_TC 0x00000004
5981 +#define DMA_CFG 0x00000024
5982 +#define DMA_INT_TC_CLR 0x00000008
5983 +#define DMA_TC 0x00000014
5984 +#define DMA_CSR 0x00000024
5985 +#define DMA_SYNC 0x00000028
5986 +
5987 +#define DMA_CH2_CSR 0x00000140
5988 +#define DMA_CH2_CFG 0x00000144
5989 +#define DMA_CH2_SRC_ADDR 0x00000148
5990 +#define DMA_CH2_DST_ADDR 0x0000014c
5991 +#define DMA_CH2_LLP 0x00000150
5992 +#define DMA_CH2_SIZE 0x00000154
5993 +
5994 +#define DMA_CH3_CSR 0x00000160
5995 +#define DMA_CH3_CFG 0x00000164
5996 +#define DMA_CH3_SRC_ADDR 0x00000168
5997 +#define DMA_CH3_DST_ADDR 0x0000016c
5998 +#define DMA_CH3_LLP 0x00000170
5999 +#define DMA_CH3_SIZE 0x00000174
6000 +
6001 +#define SSP_DEVICE_ID 0x00
6002 +#define SSP_CTRL_STATUS 0x04
6003 +#define SSP_FRAME_CTRL 0x08
6004 +#define SSP_BAUD_RATE 0x0c
6005 +#define SSP_FRAME_CTRL2 0x10
6006 +#define SSP_FIFO_CTRL 0x14
6007 +#define SSP_TX_SLOT_VALID0 0x18
6008 +#define SSP_TX_SLOT_VALID1 0x1c
6009 +#define SSP_TX_SLOT_VALID2 0x20
6010 +#define SSP_TX_SLOT_VALID3 0x24
6011 +#define SSP_RX_SLOT_VALID0 0x28
6012 +#define SSP_RX_SLOT_VALID1 0x2c
6013 +#define SSP_RX_SLOT_VALID2 0x30
6014 +#define SSP_RX_SLOT_VALID3 0x34
6015 +#define SSP_SLOT_SIZE0 0x38
6016 +#define SSP_SLOT_SIZE1 0x3c
6017 +#define SSP_SLOT_SIZE2 0x40
6018 +#define SSP_SLOT_SIZE3 0x44
6019 +#define SSP_READ_PORT 0x48
6020 +#define SSP_WRITE_PORT 0x4c
6021 +
6022 +
6023 +
6024 +#define SSP_I2S_INIT_BUF _IO ('q', 0x00)
6025 +#define SSP_I2S_STOP_DMA _IO ('q', 0x01)
6026 +#define SSP_I2S_FILE_LEN _IOW ('q', 0x2, int)
6027 +/*
6028 +#define SSP_GET_HOOK_STATUS _IOR ('q', 0xC0, int)
6029 +#define SSP_GET_LINEFEED _IOR ('q', 0xC1, int)
6030 +#define SSP_SET_LINEFEED _IOW ('q', 0xC2, int)
6031 +#define SSP_GET_REG _IOWR ('q', 0xC3, struct Ssp_reg *)
6032 +#define SSP_SET_REG _IOWR ('q', 0xC4, struct Ssp_reg *)
6033 +#define SSP_GEN_OFFHOOK_TONE _IO ('q', 0xC5)
6034 +#define SSP_GEN_BUSY_TONE _IO ('q', 0xC6)
6035 +#define SSP_GEN_RINGBACK_TONE _IO ('q', 0xC7)
6036 +#define SSP_GEN_CONGESTION_TONE _IO ('q', 0xC8)
6037 +#define SSP_DISABLE_DIALTONE _IO ('q', 0xC9)
6038 +#define SSP_PHONE_RING_START _IO ('q', 0xCA)
6039 +*/
6040 +
6041 +
6042 +#endif //__GEMINI_I2S_H__
6043 --- /dev/null
6044 +++ b/include/asm-arm/arch-sl2312/gemini_ssp.h
6045 @@ -0,0 +1,263 @@
6046 +/******************************************************************************
6047 + * gemini_ssp.h
6048 + *
6049 + *
6050 + *****************************************************************************/
6051 +
6052 +#include <linux/types.h>
6053 +#include <asm/arch-sl2312/irqs.h>
6054 +#include <linux/phonedev.h>
6055 +#include <linux/telephony.h>
6056 +//#include "proslic.h"
6057 +
6058 +typedef __u16 UINT16;
6059 +typedef __u32 UINT32;
6060 +typedef __u8 UINT8;
6061 +typedef __u8 BOOL;
6062 +
6063 +#define TRUE 1
6064 +#define FALSE 0
6065 +
6066 +/***************************************/
6067 +/* define GPIO module base address */
6068 +/***************************************/
6069 +#define DMA_CONTROL_PHY_BASE (IO_ADDRESS(SL2312_GENERAL_DMA_BASE))
6070 +#define DMA_CONTROL_SSP_BASE (IO_ADDRESS(SL2312_SSP_CTRL_BASE))
6071 +#define SSP_INT IRQ_SSP
6072 +#define GPIO_BASE_ADDR (IO_ADDRESS(SL2312_GPIO_BASE))
6073 +#define GPIO_BASE_ADDR1 (IO_ADDRESS(SL2312_GPIO_BASE1))
6074 +#define GLOBAL_BASE (IO_ADDRESS(SL2312_GLOBAL_BASE))
6075 +
6076 +/* define read/write register utility */
6077 +#define READ_SSP_REG(offset) (__raw_readl(offset+DMA_CONTROL_SSP_BASE))
6078 +#define WRITE_SSP_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE))
6079 +
6080 +#define READ_GPIO_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR))
6081 +#define WRITE_GPIO_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR))
6082 +
6083 +#define READ_GPIO1_REG(offset) (__raw_readl(offset+GPIO_BASE_ADDR1))
6084 +#define WRITE_GPIO1_REG(offset,val) (__raw_writel(val,offset+GPIO_BASE_ADDR1))
6085 +
6086 +#define READ_DMA_REG(offset) (__raw_readl(offset+DMA_CONTROL_PHY_BASE))
6087 +#define WRITE_DMA_REG(offset,val) (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE))
6088 +
6089 +#define READ_GLOBAL_REG(offset) (__raw_readl(offset+GLOBAL_BASE))
6090 +#define WRITE_GLOBAL_REG(offset,val) (__raw_writel(val,offset+GLOBAL_BASE))
6091 +
6092 +
6093 +#define SSP_GPIO_INT IRQ_GPIO
6094 +
6095 +#ifndef CONFIG_SL3516_ASIC
6096 +#define SSP_GPIO_INT_BIT 0x00000400 //GPIO[10] : SLIC interrupt pin
6097 +
6098 +#define GPIO_EECK 0x00000040 /* SCK: GPIO[06] */
6099 +#define GPIO_EECS 0x00000080 /* SCS: GPIO[07] */
6100 +#define GPIO_MISO 0x00000200 /* SDO: GPIO[09] receive from 6996*/
6101 +#define GPIO_MOSI 0x00000100 /* SDI: GPIO[08] send to 6996*/
6102 +#define GPIO_MISO_BIT 9
6103 +#else
6104 +#define SSP_GPIO_INT_BIT 0x00000001 //GPIO[0] : SLIC interrupt pin
6105 +
6106 +//#if 0
6107 +//#define GPIO_EECK 0x80000000 /* SCK: GPIO1[31] */
6108 +//#define GPIO_EECS 0x40000000 /* SCS: GPIO1[30] */
6109 +//#define GPIO_MISO 0x20000000 /* SDO: GPIO1[29] receive from 6996*/
6110 +//#define GPIO_MOSI 0x10000000 /* SDI: GPIO1[28] send to 6996*/
6111 +//#define GPIO_MISO_BIT 29
6112 +//#else
6113 +//#define GPIO_EECK 0x00000100 /* SCK: GPIO1[08] */
6114 +//#define GPIO_EECS 0x08000000 /* SCS: GPIO1[27] */
6115 +//#define GPIO_MISO 0x00000080 /* SDO: GPIO1[07] receive from 6996*/
6116 +//#define GPIO_MOSI 0x00000200 /* SDI: GPIO1[09] send to 6996*/
6117 +//#define GPIO_MISO_BIT 7
6118 +//#endif
6119 +#endif
6120 +
6121 +
6122 +enum GPIO_REG
6123 +{
6124 + GPIO_DATA_OUT = 0x00,
6125 + GPIO_DATA_IN = 0x04,
6126 + GPIO_PIN_DIR = 0x08,
6127 + GPIO_BY_PASS = 0x0c,
6128 + GPIO_DATA_SET = 0x10,
6129 + GPIO_DATA_CLEAR = 0x14,
6130 + GPIO_INT_ENABLE = 0x20,
6131 + GPIO_INT_RAWSTATE = 0x24,
6132 + GPIO_INT_MASKSTATE = 0x28,
6133 + GPIO_INT_MASK = 0x2C,
6134 + GPIO_INT_CLEAR = 0x30,
6135 + GPIO_INT_TRIGGER = 0x34,
6136 + GPIO_INT_BOTH = 0x38,
6137 + GPIO_INT_POLARITY = 0x3C
6138 +};
6139 +
6140 +
6141 +#define SPI_ADD_LEN 7 // bits of Address
6142 +#define SPI_DAT_LEN 8 // bits of Data
6143 +
6144 +
6145 +
6146 +//#ifdef MIDWAY_DIAG
6147 +#define DAISY_MODE 1
6148 +#if (DAISY_MODE==1)
6149 +#define NUMBER_OF_CHAN 2
6150 +#else
6151 +#define NUMBER_OF_CHAN 1
6152 +#endif
6153 +#define LLP_SIZE 8
6154 +#define SBUF_SIZE 512 //0xff0 //2560
6155 +#define DBUF_SIZE SBUF_SIZE*NUMBER_OF_CHAN //0xff0 //2560
6156 +#define TBUF_SIZE (LLP_SIZE)*DBUF_SIZE
6157 +#define DESC_NUM 1
6158 +#define DTMF_NUM 20
6159 +
6160 +/* define owner bit of SSP */
6161 +//data into SSP and transfer to AP==> SSP_Rx
6162 +//data out of SSP and transfer to SLIC==> SSP_Tx
6163 +#define CPU 0
6164 +#define DMA 1
6165 +
6166 +#define DMA_DEMO 0
6167 +#define DMA_NDEMO 1
6168 +//#define DMA_NONE 2
6169 +
6170 +enum exceptions {
6171 + PROSLICiNSANE,
6172 + TIMEoUTpOWERuP,
6173 + TIMEoUTpOWERdOWN,
6174 + POWERlEAK,
6175 + TIPoRrINGgROUNDsHORT,
6176 + POWERaLARMQ1,
6177 + POWERaLARMQ2,
6178 + POWERaLARMQ3,
6179 + POWERaLARMQ4,
6180 + POWERaLARMQ5,
6181 + OWERaLARMQ6,
6182 + CM_CAL_ERR
6183 +};
6184 +
6185 +typedef struct
6186 +{
6187 + UINT32 src_addr;
6188 + UINT32 dst_addr;
6189 + UINT32 llp;
6190 + UINT32 ctrl_size;
6191 +}DMA_LLP_t;
6192 +
6193 +typedef struct {
6194 + unsigned int own ;
6195 + char *tbuf;
6196 + //UINT32 *LinkAddrT;
6197 + DMA_LLP_t LLPT[LLP_SIZE];
6198 +}DMA_Tx_t;
6199 +
6200 +typedef struct {
6201 + unsigned int own ;
6202 + char *rbuf;
6203 + //UINT32 *LinkAddrR;
6204 + DMA_LLP_t LLPR[LLP_SIZE];
6205 +}DMA_Rx_t;
6206 +
6207 +//typedef struct {
6208 +// //UINT32 init_stat;
6209 +// struct chipStruct chipData ; /* Represents a proslics state, cached information, and timers */
6210 +// struct phone_device p;
6211 +//
6212 +//
6213 +//}SSP_SLIC;
6214 +
6215 +
6216 +
6217 +/* DMA Registers */
6218 +#define DMA_INT 0x00000000
6219 +#define DMA_INT_TC 0x00000004
6220 +#define DMA_CFG 0x00000024
6221 +#define DMA_INT_TC_CLR 0x00000008
6222 +#define DMA_TC 0x00000014
6223 +#define DMA_CSR 0x00000024
6224 +#define DMA_SYNC 0x00000028
6225 +
6226 +#define DMA_CH2_CSR 0x00000140
6227 +#define DMA_CH2_CFG 0x00000144
6228 +#define DMA_CH2_SRC_ADDR 0x00000148
6229 +#define DMA_CH2_DST_ADDR 0x0000014c
6230 +#define DMA_CH2_LLP 0x00000150
6231 +#define DMA_CH2_SIZE 0x00000154
6232 +
6233 +#define DMA_CH3_CSR 0x00000160
6234 +#define DMA_CH3_CFG 0x00000164
6235 +#define DMA_CH3_SRC_ADDR 0x00000168
6236 +#define DMA_CH3_DST_ADDR 0x0000016c
6237 +#define DMA_CH3_LLP 0x00000170
6238 +#define DMA_CH3_SIZE 0x00000174
6239 +
6240 +#define SSP_DEVICE_ID 0x00
6241 +#define SSP_CTRL_STATUS 0x04
6242 +#define SSP_FRAME_CTRL 0x08
6243 +#define SSP_BAUD_RATE 0x0c
6244 +#define SSP_FRAME_CTRL2 0x10
6245 +#define SSP_FIFO_CTRL 0x14
6246 +#define SSP_TX_SLOT_VALID0 0x18
6247 +#define SSP_TX_SLOT_VALID1 0x1c
6248 +#define SSP_TX_SLOT_VALID2 0x20
6249 +#define SSP_TX_SLOT_VALID3 0x24
6250 +#define SSP_RX_SLOT_VALID0 0x28
6251 +#define SSP_RX_SLOT_VALID1 0x2c
6252 +#define SSP_RX_SLOT_VALID2 0x30
6253 +#define SSP_RX_SLOT_VALID3 0x34
6254 +#define SSP_SLOT_SIZE0 0x38
6255 +#define SSP_SLOT_SIZE1 0x3c
6256 +#define SSP_SLOT_SIZE2 0x40
6257 +#define SSP_SLOT_SIZE3 0x44
6258 +#define SSP_READ_PORT 0x48
6259 +#define SSP_WRITE_PORT 0x4c
6260 +
6261 +
6262 +void printFreq_Revision(int num);
6263 +void SLIC_SPI_write(int num, UINT8 ,UINT8);
6264 +UINT8 SLIC_SPI_read(int num, UINT8);
6265 +void SLIC_SPI_write_bit(char);
6266 +void SLIC_SPI_ind_write(int num, UINT8, UINT16);
6267 +UINT16 SLIC_SPI_ind_read(int num, UINT8);
6268 +void SLIC_SPI_CS_enable(UINT8);
6269 +unsigned int SLIC_SPI_read_bit(void);
6270 +void SLIC_SPI_pre_st(void);
6271 +UINT32 ssp_init(void);
6272 +UINT16 SLIC_SPI_get_identifier(int num);
6273 +int selfTest(int num);
6274 +void exception (int num, enum exceptions e);
6275 +int SLIC_init(int num);
6276 +UINT8 version(int num);
6277 +UINT8 chipType (int num);
6278 +void SLIC_init_ind_reg_set(int num);
6279 +UINT8 powerUp(int num);
6280 +UINT8 powerLeakTest(int num);
6281 +void SLIC_init_reg_set(int num);
6282 +int calibrate(int num);
6283 +void goActive(int num);
6284 +void clearInterrupts(int num);
6285 +void setState(int num, int);
6286 +UINT8 loopStatus(int num);
6287 +int verifyIndirectRegisters(int num);
6288 +int verifyIndirectReg(int num, UINT8 , UINT16);
6289 +void sendProSLICID(int num);
6290 +void disableOscillators(int num);
6291 +UINT8 checkSum(int num, char * string );
6292 +void fskInitialization (int num);
6293 +void fskByte(int num, UINT8 c);
6294 +void waitForInterrupt (int num);
6295 +//void findNumber(void);
6296 +UINT8 dtmfAction(int num);
6297 +UINT8 digit(int num);
6298 +void interrupt_init(void);
6299 +//void gemini_slic_isr (int );
6300 +int groundShort(int num);
6301 +void clearAlarmBits(int num);
6302 +void stopRinging(int num);
6303 +void activateRinging(int num);
6304 +void initializeLoopDebounceReg(int num);
6305 +void busyJapan(int num) ;
6306 +void ringBackJapan(int num) ;
6307 +void stateMachine(int num);
6308 +
6309 --- /dev/null
6310 +++ b/include/asm-arm/arch-sl2312/hardware.h
6311 @@ -0,0 +1,47 @@
6312 +/*
6313 + * linux/include/asm-arm/arch-epxa10/hardware.h
6314 + *
6315 + * This file contains the hardware definitions of the Integrator.
6316 + *
6317 + * Copyright (C) 1999 ARM Limited.
6318 + * Copyright (C) 2001 Altera Corporation
6319 + *
6320 + * This program is free software; you can redistribute it and/or modify
6321 + * it under the terms of the GNU General Public License as published by
6322 + * the Free Software Foundation; either version 2 of the License, or
6323 + * (at your option) any later version.
6324 + *
6325 + * This program is distributed in the hope that it will be useful,
6326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6328 + * GNU General Public License for more details.
6329 + *
6330 + * You should have received a copy of the GNU General Public License
6331 + * along with this program; if not, write to the Free Software
6332 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6333 + */
6334 +#ifndef __ASM_ARCH_HARDWARE_H
6335 +#define __ASM_ARCH_HARDWARE_H
6336 +
6337 +#include <asm/arch/platform.h>
6338 +
6339 +#define pcibios_assign_all_busses() 1
6340 +
6341 +/*
6342 + * Where in virtual memory the IO devices (timers, system controllers
6343 + * and so on)
6344 + *
6345 + * macro to get at IO space when running virtually
6346 +*/
6347 +
6348 +#define IO_ADDRESS(x) (((x&0xfff00000)>>4)|(x & 0x000fffff)|0xF0000000)
6349 +#define FLASH_VBASE 0xFE000000
6350 +#define FLASH_SIZE 0x1000000// 8M
6351 +#define FLASH_START SL2312_FLASH_BASE
6352 +#define FLASH_VADDR(x) ((x & 0x00ffffff)|0xFE000000) // flash virtual address
6353 +
6354 +#define PCIBIOS_MIN_IO 0x100 // 0x000-0x100 AHB reg and PCI config, data
6355 +#define PCIBIOS_MIN_MEM 0
6356 +
6357 +#endif
6358 +
6359 --- /dev/null
6360 +++ b/include/asm-arm/arch-sl2312/int_ctrl.h
6361 @@ -0,0 +1,171 @@
6362 +/*
6363 + *
6364 + * This file contains the register definitions for the Excalibur
6365 + * Timer TIMER00.
6366 + *
6367 + * Copyright (C) 2001 Altera Corporation
6368 + *
6369 + * This program is free software; you can redistribute it and/or modify
6370 + * it under the terms of the GNU General Public License as published by
6371 + * the Free Software Foundation; either version 2 of the License, or
6372 + * (at your option) any later version.
6373 + *
6374 + * This program is distributed in the hope that it will be useful,
6375 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6376 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6377 + * GNU General Public License for more details.
6378 + *
6379 + * You should have received a copy of the GNU General Public License
6380 + * along with this program; if not, write to the Free Software
6381 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6382 + */
6383 +
6384 +#ifndef __INT_CTRL_H
6385 +#define __INT_CTRL_H
6386 +
6387 +#define PCI_IRQ_OFFSET 64 /* PCI start IRQ number */
6388 +#define FIQ_OFFSET 32
6389 +
6390 +#define IRQ_SOURCE(base_addr) (INT_CTRL_TYPE(base_addr + 0x00))
6391 +#define IRQ_MASK(base_addr) (INT_CTRL_TYPE (base_addr + 0x04 ))
6392 +#define IRQ_CLEAR(base_addr) (INT_CTRL_TYPE (base_addr + 0x08 ))
6393 +#define IRQ_TMODE(base_addr) (INT_CTRL_TYPE (base_addr + 0x0C ))
6394 +#define IRQ_TLEVEL(base_addr) (INT_CTRL_TYPE (base_addr + 0x10 ))
6395 +#define IRQ_STATUS(base_addr) (INT_CTRL_TYPE (base_addr + 0x14 ))
6396 +#define FIQ_SOURCE(base_addr) (INT_CTRL_TYPE (base_addr + 0x20 ))
6397 +#define FIQ_MASK(base_addr) (INT_CTRL_TYPE (base_addr + 0x24 ))
6398 +#define FIQ_CLEAR(base_addr) (INT_CTRL_TYPE (base_addr + 0x28 ))
6399 +#define FIQ_TMODE(base_addr) (INT_CTRL_TYPE (base_addr + 0x2C ))
6400 +#define FIQ_LEVEL(base_addr) (INT_CTRL_TYPE (base_addr + 0x30 ))
6401 +#define FIQ_STATUS(base_addr) (INT_CTRL_TYPE (base_addr + 0x34 ))
6402 +
6403 +#ifdef CONFIG_SL3516_ASIC
6404 +#define IRQ_SERIRQ0_OFFSET 30
6405 +#define IRQ_PCID_OFFSET 29
6406 +#define IRQ_PCIC_OFFSET 28
6407 +#define IRQ_PCIB_OFFSET 27
6408 +#define IRQ_PWR_OFFSET 26
6409 +#define IRQ_CIR_OFFSET 25
6410 +#define IRQ_GPIO2_OFFSET 24
6411 +#define IRQ_GPIO1_OFFSET 23
6412 +#define IRQ_GPIO_OFFSET 22
6413 +#define IRQ_SSP_OFFSET 21
6414 +#define IRQ_LPC_OFFSET 20
6415 +#define IRQ_LCD_OFFSET 19
6416 +#define IRQ_UART_OFFSET 18
6417 +#define IRQ_RTC_OFFSET 17
6418 +#define IRQ_TIMER3_OFFSET 16
6419 +#define IRQ_TIMER2_OFFSET 15
6420 +#define IRQ_TIMER1_OFFSET 14
6421 +#define IRQ_FLASH_OFFSET 12
6422 +#define IRQ_USB1_OFFSET 11
6423 +#define IRQ_USB0_OFFSET 10
6424 +#define IRQ_DMA_OFFSET 9
6425 +#define IRQ_PCI_OFFSET 8
6426 +#define IRQ_IPSEC_OFFSET 7
6427 +#define IRQ_RAID_OFFSET 6
6428 +#define IRQ_IDE1_OFFSET 5
6429 +#define IRQ_IDE0_OFFSET 4
6430 +#define IRQ_WATCHDOG_OFFSET 3
6431 +#define IRQ_GMAC1_OFFSET 2
6432 +#define IRQ_GMAC0_OFFSET 1
6433 +#define IRQ_CPU0_IP_IRQ_OFFSET 0
6434 +
6435 +#define IRQ_SERIRQ0_MASK (1<<30)
6436 +#define IRQ_PCID_MASK (1<<29)
6437 +#define IRQ_PCIC_MASK (1<<28)
6438 +#define IRQ_PCIB_MASK (1<<27)
6439 +#define IRQ_PWR_MASK (1<<26)
6440 +#define IRQ_CIR_MASK (1<<25)
6441 +#define IRQ_GPIO2_MASK (1<<24)
6442 +#define IRQ_GPIO1_MASK (1<<23)
6443 +#define IRQ_GPIO_MASK (1<<22)
6444 +#define IRQ_SSP_MASK (1<<21)
6445 +#define IRQ_LPC_MASK (1<<20)
6446 +#define IRQ_LCD_MASK (1<<19)
6447 +#define IRQ_UART_MASK (1<<18)
6448 +#define IRQ_RTC_MASK (1<<17)
6449 +#define IRQ_TIMER3_MASK (1<<16)
6450 +#define IRQ_TIMER2_MASK (1<<15)
6451 +#define IRQ_TIMER1_MASK (1<<14)
6452 +#define IRQ_FLASH_MASK (1<<12)
6453 +#define IRQ_USB1_MASK (1<<11)
6454 +#define IRQ_USB0_MASK (1<<10)
6455 +#define IRQ_DMA_MASK (1<< 9)
6456 +#define IRQ_PCI_MASK (1<< 8)
6457 +#define IRQ_IPSEC_MASK (1<< 7)
6458 +#define IRQ_RAID_MASK (1<< 6)
6459 +#define IRQ_IDE1_MASK (1<< 5)
6460 +#define IRQ_IDE0_MASK (1<< 4)
6461 +#define IRQ_WATCHDOG_MASK (1<< 3)
6462 +#define IRQ_GMAC1_MASK (1<< 2)
6463 +#define IRQ_GMAC0_MASK (1<< 1)
6464 +#define IRQ_CPU0_IP_IRQ_MASK (1<< 0)
6465 +#else
6466 +#define IRQ_SERIRQ0_OFFSET 30
6467 +#define IRQ_PCID_OFFSET 29
6468 +#define IRQ_PCIC_OFFSET 28
6469 +#define IRQ_PCIB_OFFSET 27
6470 +#define IRQ_PWR_OFFSET 26
6471 +#define IRQ_CIR_OFFSET 25
6472 +#define IRQ_GPIO2_OFFSET 24
6473 +#define IRQ_GPIO1_OFFSET 23
6474 +#define IRQ_GPIO_OFFSET 22
6475 +#define IRQ_SSP_OFFSET 21
6476 +#define IRQ_LPC_OFFSET 20
6477 +#define IRQ_LCD_OFFSET 19
6478 +#define IRQ_UART_OFFSET 18
6479 +#define IRQ_RTC_OFFSET 17
6480 +#define IRQ_TIMER3_OFFSET 16
6481 +#define IRQ_TIMER2_OFFSET 15
6482 +#define IRQ_TIMER1_OFFSET 14
6483 +#define IRQ_FLASH_OFFSET 12
6484 +#define IRQ_USB1_OFFSET 11
6485 +#define IRQ_USB0_OFFSET 10
6486 +#define IRQ_DMA_OFFSET 9
6487 +#define IRQ_PCI_OFFSET 8
6488 +#define IRQ_IPSEC_OFFSET 7
6489 +#define IRQ_RAID_OFFSET 6
6490 +#define IRQ_IDE1_OFFSET 5
6491 +#define IRQ_IDE0_OFFSET 4
6492 +#define IRQ_WATCHDOG_OFFSET 3
6493 +#define IRQ_GMAC1_OFFSET 2
6494 +#define IRQ_GMAC0_OFFSET 1
6495 +#define IRQ_CPU0_IP_IRQ_OFFSET 0
6496 +
6497 +#define IRQ_SERIRQ0_MASK (1<<30)
6498 +#define IRQ_PCID_MASK (1<<29)
6499 +#define IRQ_PCIC_MASK (1<<28)
6500 +#define IRQ_PCIB_MASK (1<<27)
6501 +#define IRQ_PWR_MASK (1<<26)
6502 +#define IRQ_CIR_MASK (1<<25)
6503 +#define IRQ_GPIO2_MASK (1<<24)
6504 +#define IRQ_GPIO1_MASK (1<<23)
6505 +#define IRQ_GPIO_MASK (1<<22)
6506 +#define IRQ_SSP_MASK (1<<21)
6507 +#define IRQ_LPC_MASK (1<<20)
6508 +#define IRQ_LCD_MASK (1<<19)
6509 +#define IRQ_UART_MASK (1<<18)
6510 +#define IRQ_RTC_MASK (1<<17)
6511 +#define IRQ_TIMER3_MASK (1<<16)
6512 +#define IRQ_TIMER2_MASK (1<<15)
6513 +#define IRQ_TIMER1_MASK (1<<14)
6514 +#define IRQ_FLASH_MASK (1<<12)
6515 +#define IRQ_USB1_MASK (1<<11)
6516 +#define IRQ_USB0_MASK (1<<10)
6517 +#define IRQ_DMA_MASK (1<< 9)
6518 +#define IRQ_PCI_MASK (1<< 8)
6519 +#define IRQ_IPSEC_MASK (1<< 7)
6520 +#define IRQ_RAID_MASK (1<< 6)
6521 +#define IRQ_IDE1_MASK (1<< 5)
6522 +#define IRQ_IDE0_MASK (1<< 4)
6523 +#define IRQ_WATCHDOG_MASK (1<< 3)
6524 +#define IRQ_GMAC1_MASK (1<< 2)
6525 +#define IRQ_GMAC0_MASK (1<< 1)
6526 +#define IRQ_CPU0_IP_IRQ_MASK (1<< 0)
6527 +#endif
6528 +
6529 +
6530 +#endif /* __INT_CTRL_H */
6531 +
6532 +
6533 --- /dev/null
6534 +++ b/include/asm-arm/arch-sl2312/io.h
6535 @@ -0,0 +1,50 @@
6536 +/*
6537 + * linux/include/asm-arm/arch-epxa10db/io.h
6538 + *
6539 + * Copyright (C) 1999 ARM Limited
6540 + *
6541 + * This program is free software; you can redistribute it and/or modify
6542 + * it under the terms of the GNU General Public License as published by
6543 + * the Free Software Foundation; either version 2 of the License, or
6544 + * (at your option) any later version.
6545 + *
6546 + * This program is distributed in the hope that it will be useful,
6547 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6548 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6549 + * GNU General Public License for more details.
6550 + *
6551 + * You should have received a copy of the GNU General Public License
6552 + * along with this program; if not, write to the Free Software
6553 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6554 + */
6555 +#ifndef __ASM_ARM_ARCH_IO_H
6556 +#define __ASM_ARM_ARCH_IO_H
6557 +
6558 +#define IO_SPACE_LIMIT 0xffffffff
6559 +
6560 +
6561 +/*
6562 + * Generic virtual read/write
6563 + */
6564 +/*
6565 +#define __arch_getw(a) (*(volatile unsigned short *)(a))
6566 +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
6567 +*/
6568 +/*#define outsw __arch_writesw
6569 +#define outsl __arch_writesl
6570 +#define outsb __arch_writesb
6571 +#define insb __arch_readsb
6572 +#define insw __arch_readsw
6573 +#define insl __arch_readsl*/
6574 +
6575 +#define __io(a) (a)
6576 +#define __mem_pci(a) (a)
6577 +/*
6578 +#define __arch_getw(a) (*(volatile unsigned short *)(a))
6579 +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
6580 +*/
6581 +#define iomem_valid_addr(off,size) (1)
6582 +#define iomem_to_phys(off) (off)
6583 +
6584 +
6585 +#endif
6586 --- /dev/null
6587 +++ b/include/asm-arm/arch-sl2312/ipi.h
6588 @@ -0,0 +1,189 @@
6589 +/*
6590 + * linux/include/asm-arm/arch-sl2312/system.h
6591 + *
6592 + * Copyright (C) 1999 ARM Limited
6593 + * Copyright (C) 2000 Deep Blue Solutions Ltd
6594 + * Copyright (C) 2001 Altera Corporation
6595 + *
6596 + * This program is free software; you can redistribute it and/or modify
6597 + * it under the terms of the GNU General Public License as published by
6598 + * the Free Software Foundation; either version 2 of the License, or
6599 + * (at your option) any later version.
6600 + *
6601 + * This program is distributed in the hope that it will be useful,
6602 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6603 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6604 + * GNU General Public License for more details.
6605 + *
6606 + * You should have received a copy of the GNU General Public License
6607 + * along with this program; if not, write to the Free Software
6608 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6609 + */
6610 +#ifndef __ASM_ARCH_IPI_H
6611 +#define __ASM_ARCH_IPI_H
6612 +#include <asm/io.h>
6613 +
6614 +//#define spin_lock(x) spin_lock_dt(x)
6615 +//#define spin_unlock(x) spin_unlock_dt(x)
6616 +
6617 +#define SWAP_OFFSET 0x400000
6618 +#define SWAP_SIZE 0x400000
6619 +
6620 +#define SHARE_MEM_ADDR 0x2000000
6621 +#define SHARE_MEM_SIZE 1024*1024
6622 +
6623 +
6624 +//--> Add by jason for IPI testing
6625 +// memory layout for maste & slave bin
6626 +#define MASTERTEXT 0x8000
6627 +#define SLAVETEXT 0x108000
6628 +#define SHARESIZE 0x4000
6629 +#define SHAREADDR SHARE_MEM_ADDR // starting 8M
6630 +
6631 +// CPU1 reset release
6632 +#define GLOBAL_BASE IO_ADDRESS(0x40000000)
6633 +#define GLOBAL_SOFTRESET (GLOBAL_BASE + 0x0C)
6634 +#define CPU1_RESET_BIT_MASK 0x40000000
6635 +
6636 +// IPI , need to redefine the folliwing, bug
6637 +#define CPU0_STATUS (GLOBAL_BASE + 0x0038)
6638 +#define CPU1_STATUS (GLOBAL_BASE + 0x003C)
6639 +#define CPU_IPI_BIT_MASK 0x80000000
6640 +
6641 +/* Your basic SMP spinlocks, allowing only a single CPU anywhere
6642 +*/
6643 +typedef struct {
6644 + volatile unsigned int lock;
6645 +} spinlock_dt;
6646 +
6647 +
6648 +#define MASTER_BIT 0x01
6649 +#define SLAVE_BIT 0x02
6650 +#define HEART_BIT 0x04
6651 +#define IPI0_IRQ_BIT 0x08
6652 +#define IPI0_FIQ_BIT 0x10
6653 +#define IPI1_IRQ_BIT 0x20
6654 +#define IPI1_FIQ_BIT 0x40
6655 +
6656 +#define IRQ 0
6657 +#define FIQ 1
6658 +#define DONE 0xff
6659 +
6660 +#define CPU0 0x0
6661 +#define CPU1 0x1
6662 +
6663 +#define MAXCHAR 128*1024
6664 +typedef struct {
6665 + int flag;
6666 + int uart_flag;
6667 + int cnt;
6668 + spinlock_dt lk;
6669 + char message[MAXCHAR];
6670 +}s_mailbox;
6671 +
6672 +// JScale proj definition
6673 +typedef struct {
6674 + u16 type; // message Type
6675 + u16 length; // message length, including message header
6676 +} IPC_MSG_HDR_T;
6677 +
6678 +typedef struct{
6679 + IPC_MSG_HDR_T hdr;
6680 + u32 input_location;
6681 + u32 input_size;
6682 + u32 output_location;
6683 + u16 ScaledImageWidth;
6684 + u16 ScaledImageHeight;
6685 + u8 ScaledImageQuality;
6686 + u8 MaintainResultionRatio;
6687 + u8 TwoStepScaling;
6688 + u8 InputFormat;
6689 + u8 verbose;
6690 + u8 reserved[3];
6691 +} JSCALE_REQ_T;
6692 +
6693 +typedef struct{
6694 + IPC_MSG_HDR_T hdr;
6695 + u32 status;
6696 + u32 code;
6697 + u32 output_size;
6698 +} JSCALE_RSP_T;
6699 +
6700 +#define IPC_JSCALE_REQ_MSG 0 // JScale request from CPU-0 to CPU-1
6701 +#define IPC_JSCALE_RSP_MSG 1 // JScale response from CPU-1 to CPU-0
6702 +
6703 +enum {
6704 + JSCALE_STATUS_OK = 0,
6705 + JSCALE_UNKNOWN_MSG_TYPE,
6706 + JSCALE_FAILED_FILE_SIZE,
6707 + JSCALE_FAILED_MALLOC,
6708 + JSCALE_FAILED_FORMAT,
6709 + JSCALE_DECODE_ERROR,
6710 + JSCALE_BUSY,
6711 +};
6712 +// <-- JScale
6713 +
6714 +#define GEMINI_IPI_IOCTL_BASE 'Z'
6715 +#define GEMINI_IPI_JSCALE_REQ _IOW (GEMINI_IPI_IOCTL_BASE,0,JSCALE_REQ_T)
6716 +#define GEMINI_IPI_JSCALE_STAT _IOR (GEMINI_IPI_IOCTL_BASE,1,JSCALE_RSP_T)
6717 +
6718 +
6719 +/*
6720 +* Simple spin lock operations.
6721 +*
6722 +*/
6723 +
6724 +#define spin_is_locked_dt(x)((x)->lock != 0)
6725 +
6726 +static inline int test_and_set_dt(spinlock_dt *lock)
6727 +{
6728 +unsigned long tmp;
6729 +__asm__ __volatile__(
6730 +"swp %0, %2, [%1]\n"
6731 +: "=&r" (tmp)
6732 +: "r" (&lock->lock), "r" (1)
6733 +: "cc", "memory");
6734 +
6735 +return tmp;
6736 +}
6737 +
6738 +static inline void spin_lock_dt(spinlock_dt *lock)
6739 +{
6740 +
6741 +unsigned long tmp;
6742 +__asm__ __volatile__(
6743 +"1: ldr %0, [%1]\n"
6744 +"teq %0, #0\n"
6745 +"swpeq %0, %2, [%1]\n"
6746 +" teqeq %0, #0\n"
6747 +" bne 1b"
6748 + : "=&r" (tmp)
6749 + : "r" (&lock->lock), "r" (1)
6750 + : "cc", "memory");
6751 +}
6752 +
6753 +static inline void spin_unlock_dt(spinlock_dt *lock)
6754 +{
6755 + __asm__ __volatile__(
6756 +" str %1, [%0]"
6757 + :
6758 + : "r" (&lock->lock), "r" (0)
6759 + : "cc", "memory");
6760 +}
6761 +
6762 +static inline int getcpuid(void)
6763 +{
6764 + int cpuid;
6765 +
6766 + __asm__(
6767 +"mrc p8, 0, r0, c0, c0, 0\n"
6768 +"mov %0, r0"
6769 + :"=r"(cpuid)
6770 + :
6771 + :"r0");
6772 + return (cpuid & 0x07);
6773 +}
6774 +
6775 +
6776 +
6777 +#endif
6778 --- /dev/null
6779 +++ b/include/asm-arm/arch-sl2312/irq.h
6780 @@ -0,0 +1,23 @@
6781 +/*
6782 + * linux/include/asm-arm/arch-sl2312/irq.h
6783 + *
6784 + * Copyright (C) 1999 ARM Limited
6785 + *
6786 + * This program is free software; you can redistribute it and/or modify
6787 + * it under the terms of the GNU General Public License as published by
6788 + * the Free Software Foundation; either version 2 of the License, or
6789 + * (at your option) any later version.
6790 + *
6791 + * This program is distributed in the hope that it will be useful,
6792 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6793 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6794 + * GNU General Public License for more details.
6795 + *
6796 + * You should have received a copy of the GNU General Public License
6797 + * along with this program; if not, write to the Free Software
6798 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6799 + */
6800 +
6801 + // Since we have PCI interrupt which the interrupt line is pseudo
6802 + // we need do some fixup
6803 +int fixup_irq(int irq);
6804 --- /dev/null
6805 +++ b/include/asm-arm/arch-sl2312/irqs.h
6806 @@ -0,0 +1,102 @@
6807 +/*
6808 + * linux/include/asm-arm/arch-camelot/irqs.h
6809 + *
6810 + * Copyright (C) 2001 Altera Corporation
6811 + *
6812 + * This program is free software; you can redistribute it and/or modify
6813 + * it under the terms of the GNU General Public License as published by
6814 + * the Free Software Foundation; either version 2 of the License, or
6815 + * (at your option) any later version.
6816 + *
6817 + * This program is distributed in the hope that it will be useful,
6818 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6819 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6820 + * GNU General Public License for more details.
6821 + *
6822 + * You should have received a copy of the GNU General Public License
6823 + * along with this program; if not, write to the Free Software
6824 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6825 + */
6826 +
6827 +/* Use the Excalibur chip definitions */
6828 +#define INT_CTRL_TYPE
6829 +#include "asm/arch/int_ctrl.h"
6830 +
6831 +#ifdef CONFIG_SL3516_ASIC
6832 +#define IRQ_SERIRQ_MAX 31
6833 +#define IRQ_SERIRQ1 31
6834 +#define IRQ_SERIRQ0 30
6835 +#define IRQ_PCID 29
6836 +#define IRQ_PCIC 28
6837 +#define IRQ_PCIB 27
6838 +#define IRQ_PWR 26
6839 +#define IRQ_CIR 25
6840 +#define IRQ_GPIO2 24
6841 +#define IRQ_GPIO1 23
6842 +#define IRQ_GPIO 22
6843 +#define IRQ_SSP 21
6844 +#define IRQ_LPC 20
6845 +#define IRQ_LCD 19
6846 +#define IRQ_UART 18
6847 +#define IRQ_RTC 17
6848 +#define IRQ_TIMER3 16
6849 +#define IRQ_TIMER2 15
6850 +#define IRQ_TIMER1 14
6851 +#define IRQ_FLASH 12
6852 +#define IRQ_USB1 11
6853 +#define IRQ_USB0 10
6854 +#define IRQ_DMA 9
6855 +#define IRQ_PCI 8
6856 +#define IRQ_IPSEC 7
6857 +#define IRQ_RAID 6
6858 +#define IRQ_IDE1 5
6859 +#define IRQ_IDE0 4
6860 +#define IRQ_WATCHDOG 3
6861 +#define IRQ_GMAC1 2
6862 +#define IRQ_GMAC0 1
6863 +#define IRQ_CPU0_IP_IRQ 0
6864 +#else
6865 +#define IRQ_SERIRQ_MAX 31
6866 +#define IRQ_SERIRQ1 31
6867 +#define IRQ_SERIRQ0 30
6868 +#define IRQ_PCID 29
6869 +#define IRQ_PCIC 28
6870 +#define IRQ_PCIB 27
6871 +#define IRQ_PWR 26
6872 +#define IRQ_CIR 25
6873 +#define IRQ_GPIO2 24
6874 +#define IRQ_GPIO1 23
6875 +#define IRQ_GPIO 22
6876 +#define IRQ_SSP 21
6877 +#define IRQ_LPC 20
6878 +#define IRQ_LCD 19
6879 +#define IRQ_UART 18
6880 +#define IRQ_RTC 17
6881 +#define IRQ_TIMER3 16
6882 +#define IRQ_TIMER2 15
6883 +#define IRQ_TIMER1 14
6884 +#define IRQ_FLASH 12
6885 +#define IRQ_USB1 11
6886 +#define IRQ_USB0 10
6887 +#define IRQ_DMA 9
6888 +#define IRQ_PCI 8
6889 +#define IRQ_IPSEC 7
6890 +#define IRQ_RAID 6
6891 +#define IRQ_IDE1 5
6892 +#define IRQ_IDE0 4
6893 +#define IRQ_WATCHDOG 3
6894 +#define IRQ_GMAC1 2
6895 +#define IRQ_GMAC0 1
6896 +#endif
6897 +
6898 +#define ARCH_TIMER_IRQ IRQ_TIMER2 /* for MV 4.0 */
6899 +
6900 +#define IRQ_PCI_INTA PCI_IRQ_OFFSET + 0
6901 +#define IRQ_PCI_INTB PCI_IRQ_OFFSET + 1
6902 +#define IRQ_PCI_INTC PCI_IRQ_OFFSET + 2
6903 +#define IRQ_PCI_INTD PCI_IRQ_OFFSET + 3
6904 +
6905 +#define NR_IRQS (IRQ_PCI_INTD + 4)
6906 +
6907 +
6908 +
6909 --- /dev/null
6910 +++ b/include/asm-arm/arch-sl2312/it8712.h
6911 @@ -0,0 +1,24 @@
6912 +
6913 +#ifndef __IT8712_H__
6914 +#define __IT8712_H__
6915 +
6916 +#include "asm/arch/sl2312.h"
6917 +
6918 +#define IT8712_IO_BASE SL2312_LPC_IO_BASE
6919 +// Device LDN
6920 +#define LDN_SERIAL1 0x01
6921 +#define LDN_SERIAL2 0x02
6922 +#define LDN_PARALLEL 0x03
6923 +#define LDN_KEYBOARD 0x05
6924 +#define LDN_MOUSE 0x06
6925 +#define LDN_GPIO 0x07
6926 +
6927 +#define IT8712_UART1_PORT 0x3F8
6928 +#define IT8712_UART2_PORT 0x2F8
6929 +
6930 +#define IT8712_GPIO_BASE 0x800 // 0x800-0x804 for GPIO set1-set5
6931 +
6932 +void LPCSetConfig(char LdnNumber, char Index, char data);
6933 +char LPCGetConfig(char LdnNumber, char Index);
6934 +
6935 +#endif
6936 --- /dev/null
6937 +++ b/include/asm-arm/arch-sl2312/memory.h
6938 @@ -0,0 +1,38 @@
6939 +/*
6940 + * linux/include/asm-arm/arch-sl2312/memory.h
6941 + *
6942 + * Copyright (C) 2001 Altera Corporation
6943 + *
6944 + * This program is free software; you can redistribute it and/or modify
6945 + * it under the terms of the GNU General Public License as published by
6946 + * the Free Software Foundation; either version 2 of the License, or
6947 + * (at your option) any later version.
6948 + *
6949 + * This program is distributed in the hope that it will be useful,
6950 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6951 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6952 + * GNU General Public License for more details.
6953 + *
6954 + * You should have received a copy of the GNU General Public License
6955 + * along with this program; if not, write to the Free Software
6956 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6957 + */
6958 +#ifndef __ASM_ARCH_MMU_H
6959 +#define __ASM_ARCH_MMU_H
6960 +
6961 +/*
6962 + * Physical DRAM offset.
6963 + */
6964 +#define PHYS_OFFSET UL(0x00000000)
6965 +
6966 +/*
6967 + * Virtual view <-> DMA view memory address translations
6968 + * virt_to_bus: Used to translate the virtual address to an
6969 + * address suitable to be passed to set_dma_addr
6970 + * bus_to_virt: Used to convert an address for DMA operations
6971 + * to an address that the kernel can use.
6972 + */
6973 +#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
6974 +#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
6975 +
6976 +#endif
6977 --- /dev/null
6978 +++ b/include/asm-arm/arch-sl2312/param.h
6979 @@ -0,0 +1,20 @@
6980 +/*
6981 + * linux/include/asm-arm/arch-epxa10db/param.h
6982 + *
6983 + * Copyright (C) 1999 ARM Limited
6984 + *
6985 + * This program is free software; you can redistribute it and/or modify
6986 + * it under the terms of the GNU General Public License as published by
6987 + * the Free Software Foundation; either version 2 of the License, or
6988 + * (at your option) any later version.
6989 + *
6990 + * This program is distributed in the hope that it will be useful,
6991 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6992 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6993 + * GNU General Public License for more details.
6994 + *
6995 + * You should have received a copy of the GNU General Public License
6996 + * along with this program; if not, write to the Free Software
6997 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6998 + */
6999 +
7000 --- /dev/null
7001 +++ b/include/asm-arm/arch-sl2312/pci.h
7002 @@ -0,0 +1,18 @@
7003 +
7004 +#ifndef __SL2312_PCI_H__
7005 +#define __SL2312_PCI_H__
7006 +
7007 +#define SL2312_PCI_PMC 0x40
7008 +#define SL2312_PCI_PMCSR 0x44
7009 +#define SL2312_PCI_CTRL1 0x48
7010 +#define SL2312_PCI_CTRL2 0x4c
7011 +#define SL2312_PCI_MEM1_BASE_SIZE 0x50
7012 +#define SL2312_PCI_MEM2_BASE_SIZE 0x54
7013 +#define SL2312_PCI_MEM3_BASE_SIZE 0x58
7014 +
7015 +
7016 +void sl2312_pci_mask_irq(unsigned int irq);
7017 +void sl2312_pci_unmask_irq(unsigned int irq);
7018 +int sl2312_pci_get_int_src(void);
7019 +
7020 +#endif
7021 --- /dev/null
7022 +++ b/include/asm-arm/arch-sl2312/platform.h
7023 @@ -0,0 +1,7 @@
7024 +#ifndef PLATFORM_H
7025 +#define PLATFORM_H
7026 +#include "sl2312.h"
7027 +
7028 +#define MAXIRQNUM 68
7029 +#endif
7030 +
7031 --- /dev/null
7032 +++ b/include/asm-arm/arch-sl2312/preempt.h
7033 @@ -0,0 +1,63 @@
7034 +/*
7035 + * include/asm-arm/arch-sl2312/preempt.h
7036 + *
7037 + * Timing support for preempt-stats, kfi, ilatency patches
7038 + *
7039 + * Author: dsingleton <dsingleton@mvista.com>
7040 + *
7041 + * 2001-2004 (c) MontaVista Software, Inc. This file is licensed under
7042 + * the terms of the GNU General Public License version 2. This program
7043 + * is licensed "as is" without any warranty of any kind, whether express
7044 + * or implied.
7045 + */
7046 +
7047 +#ifndef _ASM_ARCH_PREEMT_H
7048 +#define _ASM_ARCH_PREEMT_H
7049 +
7050 +#include <asm/arch/hardware.h>
7051 +#include <asm/arch/sl2312.h>
7052 +
7053 +static inline unsigned long clock_diff(unsigned long start, unsigned long stop)
7054 +{
7055 + return (start - stop);
7056 +}
7057 +
7058 +static inline unsigned int readclock(void)
7059 +{
7060 + unsigned int x;
7061 +
7062 + x = readl(IO_ADDRESS(SL2312_TIMER2_BASE));
7063 + return x;
7064 +}
7065 +
7066 +static inline unsigned __ticks_per_usec(void)
7067 +{
7068 +#ifdef CONFIG_SL3516_ASIC
7069 + unsigned int ahb_clock_rate_base=130; /* unit = MHz*/
7070 + unsigned int reg_v=0;
7071 + unsigned int ticks_usec;
7072 +
7073 + reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+4)));
7074 + reg_v >>=15;
7075 + ticks_usec = (ahb_clock_rate_base + (reg_v & 0x07)*10)>>2;
7076 +
7077 +#else
7078 + unsigned int ticks_usec=20;
7079 +#endif
7080 +
7081 + return ticks_usec;
7082 +}
7083 +
7084 +/*
7085 + * timer 1 runs @ 6Mhz 6 ticks = 1 microsecond
7086 + * and is configed as a count down timer.
7087 + */
7088 +#define TICKS_PER_USEC __ticks_per_usec()
7089 +#define ARCH_PREDEFINES_TICKS_PER_USEC
7090 +
7091 +#define clock_to_usecs(x) ((x) / TICKS_PER_USEC)
7092 +
7093 +#define INTERRUPTS_ENABLED(x) (!(x & PSR_I_BIT))
7094 +
7095 +#endif
7096 +
7097 --- /dev/null
7098 +++ b/include/asm-arm/arch-sl2312/sl2312.h
7099 @@ -0,0 +1,254 @@
7100 +#ifndef __sl2312_h
7101 +#define __sl2312_h
7102 +
7103 +/****************************************************************************
7104 + * Copyright Storlink Corp 2002-2003. All rights reserved. *
7105 + *--------------------------------------------------------------------------*
7106 + * Name:board.s *
7107 + * Description: SL231x specfic define *
7108 + * Author: Plus Chen *
7109 + * Version: 0.9 Create
7110 + ****************************************************************************/
7111 +
7112 +/*
7113 + CPE address map;
7114 +
7115 + +====================================================
7116 + 0x00000000 | FLASH
7117 + 0x0FFFFFFF |
7118 + |====================================================
7119 + 0x10000000 | SDRAM
7120 + 0x1FFFFFFF |
7121 + |====================================================
7122 + 0x20000000 | Global Registers 0x20000000-0x20FFFFFF
7123 + | EMAC and DMA 0x21000000-0x21FFFFFF
7124 + | UART Module 0x22000000-0x22FFFFFF
7125 + | Timer Module 0x23000000-0x23FFFFFF
7126 + | Interrupt Module 0x24000000-0x24FFFFFF
7127 + | RTC Module 0x25000000-0x25FFFFFF
7128 + | LPC Host Controller 0x26000000-0x26FFFFFF
7129 + | LPC Peripherial IO 0x27000000-0x27FFFFFF
7130 + | WatchDog Timer 0x28000000-0x28FFFFFF
7131 + 0x2FFFFFFF | Reserved 0x29000000-0x29FFFFFF
7132 + |=====================================================
7133 + 0x30000000 | PCI IO, Configuration Registers
7134 + 0x3FFFFFFF |
7135 + |=====================================================
7136 + 0x40000000 | PCI Memory
7137 + 0x4FFFFFFF |
7138 + |=====================================================
7139 + 0x50000000 | Ethernet MAC and DMA 0x50000000-0x50FFFFFF
7140 + | Security and DMA 0x51000000-0x51FFFFFF
7141 + | IDE Channel 0 Register 0x52000000-0x527FFFFF
7142 + | IDE Channel 1 Register 0x52800000-0x52FFFFFF
7143 + | USB Register 0x53000000-0x53FFFFFF
7144 + | Flash Controller 0x54000000-0x54FFFFFF
7145 + | DRAM Controller 0x55000000-0x55FFFFFF
7146 + 0x5FFFFFFF | Reserved 0x56000000-0x5FFFFFFF
7147 + |=====================================================
7148 + 0x60000000 | Reserved
7149 + 0x6FFFFFFF |
7150 + |=====================================================
7151 + 0x70000000 | FLASH shadow Memory
7152 + 0x7FFFFFFF |
7153 + |=====================================================
7154 + 0x80000000 | Big Endian of memory 0x00000000-0x7FFFFFFF
7155 + 0xFFFFFFFF |
7156 + +=====================================================
7157 +*/
7158 +
7159 +
7160 +
7161 +/*-------------------------------------------------------------------------------
7162 + Memory Map definitions
7163 +-------------------------------------------------------------------------------- */
7164 +#define TEST 1
7165 +#if 0
7166 +
7167 +static inline int GETCPUID()
7168 +{
7169 + int cpuid;
7170 + __asm__(
7171 +"mrc p8, 0, r0, c0, c0, 0\n"
7172 +"mov %0, r0"
7173 + :"=r"(cpuid)
7174 + :
7175 + :"r0");
7176 + return (cpuid & 0x07);
7177 +}
7178 +#endif
7179 +#define SL2312_SRAM_BASE 0x70000000 // SRAM base after remap
7180 +#define SL2312_DRAM_BASE 0x00000000 // DRAM base after remap
7181 +#define SL2312_RAM_BASE 0x10000000 // RAM code base before remap
7182 +#define SL2312_FLASH_BASE 0x30000000
7183 +#define SL2312_ROM_BASE 0x30000000
7184 +#define SL2312_GLOBAL_BASE 0x40000000
7185 +#define SL2312_WAQTCHDOG_BASE 0x41000000
7186 +#define SL2312_UART_BASE 0x42000000
7187 +#define SL2312_TIMER_BASE 0x43000000
7188 +#define SL2312_LCD_BASE 0x44000000
7189 +#define SL2312_RTC_BASE 0x45000000
7190 +#define SL2312_SATA_BASE 0x46000000
7191 +#define SL2312_LPC_HOST_BASE 0x47000000
7192 +#define SL2312_LPC_IO_BASE 0x47800000
7193 +// #define SL2312_INTERRUPT_BASE 0x48000000
7194 +#define SL2312_INTERRUPT0_BASE 0x48000000
7195 +#define SL2312_INTERRUPT1_BASE 0x49000000
7196 +//#define SL2312_INTERRUPT_BASE ((getcpuid()==0)?SL2312_INTERRUPT0_BASE:SL2312_INTERRUPT1_BASE)
7197 +#define SL2312_INTERRUPT_BASE 0x48000000
7198 +#define SL2312_SSP_CTRL_BASE 0x4A000000
7199 +#define SL2312_POWER_CTRL_BASE 0x4B000000
7200 +#define SL2312_CIR_BASE 0x4C000000
7201 +#define SL2312_GPIO_BASE 0x4D000000
7202 +#define SL2312_GPIO_BASE1 0x4E000000
7203 +#define SL2312_GPIO_BASE2 0x4F000000
7204 +#define SL2312_PCI_IO_BASE 0x50000000
7205 +#define SL2312_PCI_MEM_BASE 0x58000000
7206 +#ifdef CONFIG_NET_SL351X
7207 +#define SL2312_TOE_BASE 0x60000000
7208 +#define SL2312_GMAC0_BASE 0x6000A000
7209 +#define SL2312_GMAC1_BASE 0x6000E000
7210 +#else
7211 +#define SL2312_GMAC0_BASE 0x60000000
7212 +#define SL2312_GMAC1_BASE 0x61000000
7213 +#endif
7214 +#define SL2312_SECURITY_BASE 0x62000000
7215 +#define SL2312_IDE0_BASE 0x63000000
7216 +#define SL2312_IDE1_BASE 0x63400000
7217 +#define SL2312_RAID_BASE 0x64000000
7218 +#define SL2312_FLASH_CTRL_BASE 0x65000000
7219 +#define SL2312_DRAM_CTRL_BASE 0x66000000
7220 +#define SL2312_GENERAL_DMA_BASE 0x67000000
7221 +#define SL2312_USB_BASE 0x68000000
7222 +#define SL2312_USB0_BASE 0x68000000
7223 +#define SL2312_USB1_BASE 0x69000000
7224 +#define SL2312_FLASH_SHADOW 0x30000000
7225 +#define SL2312_BIG_ENDIAN_BASE 0x80000000
7226 +
7227 +#ifdef CONFIG_GEMINI_IPI
7228 +#define CPU_1_MEM_BASE 0x4000000 // 64 MB
7229 +#define CPU_1_DATA_OFFSET 0x4000000-0x300000 // Offset 61 MB
7230 +#endif
7231 +
7232 +#define SL2312_TIMER1_BASE SL2312_TIMER_BASE
7233 +#define SL2312_TIMER2_BASE (SL2312_TIMER_BASE + 0x10)
7234 +#define SL2312_TIMER3_BASE (SL2312_TIMER_BASE + 0x20)
7235 +
7236 +#define SL2312_PCI_DMA_MEM1_BASE 0x00000000
7237 +#define SL2312_PCI_DMA_MEM2_BASE 0x00000000
7238 +#define SL2312_PCI_DMA_MEM3_BASE 0x00000000
7239 +#define SL2312_PCI_DMA_MEM1_SIZE 7
7240 +#define SL2312_PCI_DMA_MEM2_SIZE 6
7241 +#define SL2312_PCI_DMA_MEM3_SIZE 6
7242 +
7243 +/*-------------------------------------------------------------------------------
7244 + Global Module
7245 +---------------------------------------------------------------------------------*/
7246 +#define GLOBAL_ID 0x00
7247 +#define GLOBAL_CHIP_ID 0x002311
7248 +#define GLOBAL_CHIP_REV 0xA0
7249 +#define GLOBAL_STATUS 0x04
7250 +#define GLOBAL_CONTROL 0x1C
7251 +#define GLOBAL_REMAP_BIT 0x01
7252 +#define GLOBAL_RESET_REG 0x0C
7253 +#define GLOBAL_MISC_REG 0x30
7254 +#define PFLASH_SHARE_BIT 0x02
7255 +
7256 +#define GLOBAL_RESET (1<<31)
7257 +#define RESET_CPU1 (1<<30)
7258 +#define RESET_SATA1 (1<<27)
7259 +#define RESET_SATA0 (1<<26)
7260 +#define RESET_CIR (1<<25)
7261 +#define RESET_EXT_DEV (1<<24)
7262 +#define RESET_WD (1<<23)
7263 +#define RESET_GPIO2 (1<<22)
7264 +#define RESET_GPIO1 (1<<21)
7265 +#define RESET_GPIO0 (1<<20)
7266 +#define RESET_SSP (1<<19)
7267 +#define RESET_UART (1<<18)
7268 +#define RESET_TIMER (1<<17)
7269 +#define RESET_RTC (1<<16)
7270 +#define RESET_INT0 (1<<15)
7271 +#define RESET_INT1 (1<<14)
7272 +#define RESET_LCD (1<<13)
7273 +#define RESET_LPC (1<<12)
7274 +#define RESET_APB (1<<11)
7275 +#define RESET_DMA (1<<10)
7276 +#define RESET_USB1 (1<<9 )
7277 +#define RESET_USB0 (1<<8 )
7278 +#define RESET_PCI (1<<7 )
7279 +#define RESET_GMAC1 (1<<6 )
7280 +#define RESET_GMAC0 (1<<5 )
7281 +#define RESET_IPSEC (1<<4 )
7282 +#define RESET_RAID (1<<3 )
7283 +#define RESET_IDE (1<<2 )
7284 +#define RESET_FLASH (1<<1 )
7285 +#define RESET_DRAM (1<<0 )
7286 +
7287 +
7288 +
7289 +
7290 +
7291 +
7292 +
7293 +
7294 +/*-------------------------------------------------------------------------------
7295 + DRAM Module
7296 +---------------------------------------------------------------------------------*/
7297 +#define DRAM_SIZE_32M 0x2000000
7298 +#define DRAM_SIZE_64M 0x4000000
7299 +#define DRAM_SIZE_128M 0x8000000
7300 +
7301 +#define DRAM_SIZE DRAM_SIZE_128M
7302 +
7303 +#define DRAM_SDRMR 0x00
7304 +#define SDRMR_DISABLE_DLL 0x80010000
7305 +
7306 +/*------------------------------------------------------------------------------
7307 + Share Pin Flag
7308 +--------------------------------------------------------------------------------*/
7309 +#ifdef CONFIG_SL2312_SHARE_PIN
7310 +#define FLASH_SHARE_BIT 0
7311 +#define UART_SHARE_BIT 1
7312 +#define EMAC_SHARE_BIT 2
7313 +#define IDE_RW_SHARE_BIT 3
7314 +#define IDE_CMD_SHARE_BIT 4
7315 +#endif
7316 +/*-------------------------------------------------------------------------------
7317 + System Clock
7318 +---------------------------------------------------------------------------------*/
7319 +
7320 +#ifndef SYS_CLK
7321 +#ifdef CONFIG_SL3516_ASIC
7322 +#define SYS_CLK 150000000
7323 +#else
7324 +#define SYS_CLK 20000000
7325 +#endif
7326 +#endif
7327 +
7328 +#define AHB_CLK SYS_CLK
7329 +#define MAX_TIMER 3
7330 +#ifndef APB_CLK
7331 +#ifdef CONFIG_SL3516_ASIC
7332 +#define APB_CLK (SYS_CLK / 6)
7333 +#else
7334 +#define APB_CLK SYS_CLK
7335 +#endif
7336 +#endif
7337 +
7338 +#ifdef CONFIG_SL3516_ASIC
7339 +#define UART_CLK 48000000 // 30000000 for GeminiA chip, else 48000000
7340 +#else
7341 +#define UART_CLK 48000000
7342 +#endif
7343 +
7344 +#define SL2312_BAUD_115200 (UART_CLK / 1843200)
7345 +#define SL2312_BAUD_57600 (UART_CLK / 921600)
7346 +#define SL2312_BAUD_38400 (UART_CLK / 614400)
7347 +#define SL2312_BAUD_19200 (UART_CLK / 307200)
7348 +#define SL2312_BAUD_14400 (UART_CLK / 230400)
7349 +#define SL2312_BAUD_9600 (UART_CLK / 153600)
7350 +
7351 +#endif
7352 +
7353 +
7354 --- /dev/null
7355 +++ b/include/asm-arm/arch-sl2312/sl2312_ipsec.h
7356 @@ -0,0 +1,684 @@
7357 +#ifndef _IPSEC_DIAG_H
7358 +#define _IPSEC_DIAG_H
7359 +
7360 +#include <linux/scatterlist.h>
7361 +
7362 +#define BIG_ENDIAN 0
7363 +
7364 +#define IPSEC_TEST 0
7365 +#define ZERO_COPY 1
7366 +
7367 +#define UINT unsigned int
7368 +#define BYTE unsigned char
7369 +
7370 +/* define cipher algorithm */
7371 +enum CIPHER {
7372 + DES_ECB_E =20,
7373 + TDES_ECB_E =21,
7374 + AES_ECB_E =22,
7375 + DES_CBC_E =24,
7376 + TDES_CBC_E =25,
7377 + AES_CBC_E =26,
7378 +
7379 + DES_ECB_D =27,
7380 + TDES_ECB_D =28,
7381 + AES_ECB_D =29,
7382 + DES_CBC_D =31,
7383 + TDES_CBC_D =32,
7384 + AES_CBC_D =33,
7385 + A_SHA1 =12,
7386 + A_HMAC_SHA1 =13,
7387 + A_MD5 =14,
7388 + A_HMAC_MD5 =15,
7389 +};
7390 +
7391 +// opMode
7392 +#define CIPHER_ENC 0x1
7393 +#define CIPHER_DEC 0x3
7394 +#define AUTH 0x4
7395 +#define ENC_AUTH 0x5
7396 +#define AUTH_DEC 0x7
7397 +
7398 +// cipherAlgorithm
7399 +#define CBC_DES 0x4
7400 +#define CBC_3DES 0x5
7401 +#define CBC_AES 0x6
7402 +#define ECB_DES 0x0
7403 +#define ECB_3DES 0x1
7404 +#define ECB_AES 0x2
7405 +
7406 +// authAlgorithm
7407 +#define SHA1 0
7408 +#define MD5 1
7409 +#define HMAC_SHA1 2
7410 +#define HMAC_MD5 3
7411 +#define FCS 4
7412 +
7413 +//cipher mode
7414 +#define ECB 0
7415 +#define CBC 1
7416 +
7417 +// authMode
7418 +#define AUTH_APPEND 0
7419 +#define AUTH_CHKVAL 1
7420 +
7421 +/******************************************************/
7422 +/* the offset of IPSEC DMA register */
7423 +/******************************************************/
7424 +enum IPSEC_DMA_REGISTER {
7425 + IPSEC_DMA_DEVICE_ID = 0xff00,
7426 + IPSEC_DMA_STATUS = 0xff04,
7427 + IPSEC_TXDMA_CTRL = 0xff08,
7428 + IPSEC_TXDMA_FIRST_DESC = 0xff0c,
7429 + IPSEC_TXDMA_CURR_DESC = 0xff10,
7430 + IPSEC_RXDMA_CTRL = 0xff14,
7431 + IPSEC_RXDMA_FIRST_DESC = 0xff18,
7432 + IPSEC_RXDMA_CURR_DESC = 0xff1c,
7433 + IPSEC_TXDMA_BUF_ADDR = 0xff28,
7434 + IPSEC_RXDMA_BUF_ADDR = 0xff38,
7435 + IPSEC_RXDMA_BUF_SIZE = 0xff30,
7436 +};
7437 +
7438 +#define IPSEC_STATUS_REG 0x00a8
7439 +#define IPSEC_RAND_NUM_REG 0x00ac
7440 +
7441 +/******************************************************/
7442 +/* the field definition of IPSEC DMA Module Register */
7443 +/******************************************************/
7444 +typedef union
7445 +{
7446 + unsigned int bits32;
7447 + struct bit2_ff00
7448 + {
7449 +#if (BIG_ENDIAN==1)
7450 + unsigned int p_wclk : 4; /* DMA_APB write clock period */
7451 + unsigned int p_rclk : 4; /* DMA_APB read clock period */
7452 + unsigned int : 8;
7453 + unsigned int device_id : 12;
7454 + unsigned int revision_id : 4;
7455 +#else
7456 + unsigned int revision_id : 4;
7457 + unsigned int device_id : 12;
7458 + unsigned int : 8;
7459 + unsigned int p_rclk : 4; /* DMA_APB read clock period */
7460 + unsigned int p_wclk : 4; /* DMA_APB write clock period */
7461 +#endif
7462 + } bits;
7463 +} IPSEC_DMA_DEVICE_ID_T;
7464 +
7465 +typedef union
7466 +{
7467 + unsigned int bits32;
7468 + struct bit2_ff04
7469 + {
7470 +#if (BIG_ENDIAN==1)
7471 + unsigned int ts_finish : 1; /* finished tx interrupt */
7472 + unsigned int ts_derr : 1; /* AHB Bus Error while tx */
7473 + unsigned int ts_perr : 1; /* Tx Descriptor protocol error */
7474 + unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */
7475 + unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */
7476 + unsigned int rs_finish : 1; /* finished rx interrupt */
7477 + unsigned int rs_derr : 1; /* AHB Bus Error while rx */
7478 + unsigned int rs_perr : 1; /* Rx Descriptor protocol error */
7479 + unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */
7480 + unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */
7481 + unsigned int intr : 8; /* Peripheral interrupt */
7482 + unsigned int dma_reset : 1; /* write 1 to this bit will cause DMA HClk domain soft reset */
7483 + unsigned int peri_reset : 1; /* write 1 to this bit will cause DMA PClk domain soft reset */
7484 + unsigned int : 3;
7485 + unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */
7486 + unsigned int intr_enable : 8; /* Peripheral Interrupt Enable */
7487 +#else
7488 + unsigned int intr_enable : 8; /* Peripheral Interrupt Enable */
7489 + unsigned int loop_back : 1; /* loopback TxDMA to RxDMA */
7490 + unsigned int : 3;
7491 + unsigned int peri_reset : 1; /* write 1 to this bit will cause DMA PClk domain soft reset */
7492 + unsigned int dma_reset : 1; /* write 1 to this bit will cause DMA HClk domain soft reset */
7493 + unsigned int intr : 8; /* Peripheral interrupt */
7494 + unsigned int rs_eofi : 1; /* RxDMA end of frame interrupt */
7495 + unsigned int rs_eodi : 1; /* RxDMA end of descriptor interrupt */
7496 + unsigned int rs_perr : 1; /* Rx Descriptor protocol error */
7497 + unsigned int rs_derr : 1; /* AHB Bus Error while rx */
7498 + unsigned int rs_finish : 1; /* finished rx interrupt */
7499 + unsigned int ts_eofi : 1; /* TxDMA end of frame interrupt */
7500 + unsigned int ts_eodi : 1; /* TxDMA end of descriptor interrupt */
7501 + unsigned int ts_perr : 1; /* Tx Descriptor protocol error */
7502 + unsigned int ts_derr : 1; /* AHB Bus Error while tx */
7503 + unsigned int ts_finish : 1; /* finished tx interrupt */
7504 +#endif
7505 + } bits;
7506 +} IPSEC_DMA_STATUS_T;
7507 +
7508 +typedef union
7509 +{
7510 + unsigned int bits32;
7511 + struct bit2_ff08
7512 + {
7513 +#if (BIG_ENDIAN==1)
7514 + unsigned int td_start : 1; /* Start DMA transfer */
7515 + unsigned int td_continue : 1; /* Continue DMA operation */
7516 + unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7517 + unsigned int : 1;
7518 + unsigned int td_prot : 4; /* TxDMA protection control */
7519 + unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */
7520 + unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7521 + unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
7522 + unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7523 + unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
7524 + unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7525 + unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
7526 + unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
7527 + unsigned int : 14;
7528 +#else
7529 + unsigned int : 14;
7530 + unsigned int td_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
7531 + unsigned int td_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
7532 + unsigned int td_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7533 + unsigned int td_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
7534 + unsigned int td_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7535 + unsigned int td_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
7536 + unsigned int td_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7537 + unsigned int td_burst_size : 2; /* TxDMA max burst size for every AHB request */
7538 + unsigned int td_prot : 4; /* TxDMA protection control */
7539 + unsigned int : 1;
7540 + unsigned int td_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7541 + unsigned int td_continue : 1; /* Continue DMA operation */
7542 + unsigned int td_start : 1; /* Start DMA transfer */
7543 +#endif
7544 + } bits;
7545 +} IPSEC_TXDMA_CTRL_T;
7546 +
7547 +typedef union
7548 +{
7549 + unsigned int bits32;
7550 + struct bit2_ff0c
7551 + {
7552 +#if (BIG_ENDIAN==1)
7553 + unsigned int td_first_des_ptr : 28;/* first descriptor address */
7554 + unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */
7555 + unsigned int : 3;
7556 +#else
7557 + unsigned int : 3;
7558 + unsigned int td_busy : 1;/* 1-TxDMA busy; 0-TxDMA idle */
7559 + unsigned int td_first_des_ptr : 28;/* first descriptor address */
7560 +#endif
7561 + } bits;
7562 +} IPSEC_TXDMA_FIRST_DESC_T;
7563 +
7564 +typedef union
7565 +{
7566 + unsigned int bits32;
7567 + struct bit2_ff10
7568 + {
7569 +#if (BIG_ENDIAN==1)
7570 + unsigned int ndar : 28; /* next descriptor address */
7571 + unsigned int eofie : 1; /* end of frame interrupt enable */
7572 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
7573 + unsigned int sof_eof : 2;
7574 +#else
7575 + unsigned int sof_eof : 2;
7576 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
7577 + unsigned int eofie : 1; /* end of frame interrupt enable */
7578 + unsigned int ndar : 28; /* next descriptor address */
7579 +#endif
7580 + } bits;
7581 +} IPSEC_TXDMA_CURR_DESC_T;
7582 +
7583 +
7584 +typedef union
7585 +{
7586 + unsigned int bits32;
7587 + struct bit2_ff14
7588 + {
7589 +#if (BIG_ENDIAN==1)
7590 + unsigned int rd_start : 1; /* Start DMA transfer */
7591 + unsigned int rd_continue : 1; /* Continue DMA operation */
7592 + unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7593 + unsigned int : 1;
7594 + unsigned int rd_prot : 4; /* DMA protection control */
7595 + unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */
7596 + unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7597 + unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
7598 + unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7599 + unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
7600 + unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7601 + unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
7602 + unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
7603 + unsigned int : 14;
7604 +#else
7605 + unsigned int : 14;
7606 + unsigned int rd_eof_en : 1; /* End of frame interrupt Enable;1-enable;0-mask */
7607 + unsigned int rd_eod_en : 1; /* End of Descriptor interrupt Enable;1-enable;0-mask */
7608 + unsigned int rd_perr_en : 1; /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7609 + unsigned int rd_fail_en : 1; /* DMA Fail Interrupt Enable;1-enable;0-mask */
7610 + unsigned int rd_finish_en : 1; /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7611 + unsigned int rd_endian : 1; /* AHB Endian. 0-little endian; 1-big endian */
7612 + unsigned int rd_bus : 2; /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7613 + unsigned int rd_burst_size : 2; /* DMA max burst size for every AHB request */
7614 + unsigned int rd_prot : 4; /* DMA protection control */
7615 + unsigned int : 1;
7616 + unsigned int rd_chain_mode : 1; /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7617 + unsigned int rd_continue : 1; /* Continue DMA operation */
7618 + unsigned int rd_start : 1; /* Start DMA transfer */
7619 +#endif
7620 + } bits;
7621 +} IPSEC_RXDMA_CTRL_T;
7622 +
7623 +typedef union
7624 +{
7625 + unsigned int bits32;
7626 + struct bit2_ff18
7627 + {
7628 +#if (BIG_ENDIAN==1)
7629 + unsigned int rd_first_des_ptr : 28;/* first descriptor address */
7630 + unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */
7631 + unsigned int : 3;
7632 +#else
7633 + unsigned int : 3;
7634 + unsigned int rd_busy : 1;/* 1-RxDMA busy; 0-RxDMA idle */
7635 + unsigned int rd_first_des_ptr : 28;/* first descriptor address */
7636 +#endif
7637 + } bits;
7638 +} IPSEC_RXDMA_FIRST_DESC_T;
7639 +
7640 +typedef union
7641 +{
7642 + unsigned int bits32;
7643 + struct bit2_ff1c
7644 + {
7645 +#if (BIG_ENDIAN==1)
7646 + unsigned int ndar : 28; /* next descriptor address */
7647 + unsigned int eofie : 1; /* end of frame interrupt enable */
7648 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
7649 + unsigned int sof_eof : 2;
7650 +#else
7651 + unsigned int sof_eof : 2;
7652 + unsigned int dec : 1; /* AHB bus address increment(0)/decrement(1) */
7653 + unsigned int eofie : 1; /* end of frame interrupt enable */
7654 + unsigned int ndar : 28; /* next descriptor address */
7655 +#endif
7656 + } bits;
7657 +} IPSEC_RXDMA_CURR_DESC_T;
7658 +
7659 +
7660 +
7661 +/******************************************************/
7662 +/* the field definition of IPSEC module Register */
7663 +/******************************************************/
7664 +typedef union
7665 +{
7666 + unsigned int id;
7667 + struct bit_0000
7668 + {
7669 +#if (BIG_ENDIAN==1)
7670 + unsigned int device_id : 28;
7671 + unsigned int revision_id : 4;
7672 +#else
7673 + unsigned int revision_id : 4;
7674 + unsigned int device_id : 28;
7675 +#endif
7676 + } bits;
7677 +} IPSEC_ID_T;
7678 +
7679 +typedef union
7680 +{
7681 + unsigned int control;
7682 + struct bit_0004
7683 + {
7684 +#if (BIG_ENDIAN==1)
7685 + unsigned int op_mode : 4; /* Operation Mode for the IPSec Module */
7686 + unsigned int : 1;
7687 + unsigned int cipher_algorithm : 3;
7688 + unsigned int aesnk : 4; /* AES Key Size */
7689 + unsigned int mix_key_sel : 1; /* 0:use rCipherKey0-3 1:use Key Mixer */
7690 + unsigned int : 2;
7691 + unsigned int fcs_stream_copy : 1; /* enable authentication stream copy */
7692 + unsigned int auth_mode : 1; /* 0-Append or 1-Check Authentication Result */
7693 + unsigned int auth_algorithm : 3;
7694 + unsigned int : 1;
7695 + unsigned int auth_check_len : 3; /* Number of 32-bit words to be check or appended */
7696 + /* by the authentication module */
7697 + unsigned int process_id : 8; /* Used to identify process.This number will be */
7698 + /* copied to the descriptor status of received packet*/
7699 +#else
7700 + unsigned int process_id : 8; /* Used to identify process.This number will be */
7701 + /* copied to the descriptor status of received packet*/
7702 + unsigned int auth_check_len : 3; /* Number of 32-bit words to be check or appended */
7703 + /* by the authentication module */
7704 + unsigned int : 1;
7705 + unsigned int auth_algorithm : 3;
7706 + unsigned int auth_mode : 1; /* 0-Append or 1-Check Authentication Result */
7707 + unsigned int fcs_stream_copy : 1; /* enable authentication stream copy */
7708 + unsigned int : 2;
7709 + unsigned int mix_key_sel : 1; /* 0:use rCipherKey0-3 1:use Key Mixer */
7710 + unsigned int aesnk : 4; /* AES Key Size */
7711 + unsigned int cipher_algorithm : 3;
7712 + unsigned int : 1;
7713 + unsigned int op_mode : 4; /* Operation Mode for the IPSec Module */
7714 +#endif
7715 + } bits;
7716 +} IPSEC_CONTROL_T;
7717 +
7718 +
7719 +typedef union
7720 +{
7721 + unsigned int cipher_packet;
7722 + struct bit_0008
7723 + {
7724 +#if (BIG_ENDIAN==1)
7725 + unsigned int cipher_header_len : 16; /* The header length to be skipped by the cipher */
7726 + unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */
7727 +#else
7728 + unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */
7729 + unsigned int cipher_header_len : 16; /* The header length to be skipped by the cipher */
7730 +#endif
7731 + } bits;
7732 +} IPSEC_CIPHER_PACKET_T;
7733 +
7734 +typedef union
7735 +{
7736 + unsigned int auth_packet;
7737 + struct bit_000c
7738 + {
7739 +#if (BIG_ENDIAN==1)
7740 + unsigned int auth_header_len : 16; /* The header length that is to be skipped by the authenticator */
7741 + unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */
7742 +#else
7743 + unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */
7744 + unsigned int auth_header_len : 16; /* The header length that is to be skipped by the authenticator */
7745 +#endif
7746 + } bits;
7747 +} IPSEC_AUTH_PACKET_T;
7748 +
7749 +typedef union
7750 +{
7751 + unsigned int status;
7752 + struct bit_00a8
7753 + {
7754 +#if (BIG_ENDIAN==1)
7755 + unsigned int auth_cmp_rslt : 1; /* Authentication Compare result */
7756 + unsigned int wep_crc_ok : 1; /* WEP ICV compare result */
7757 + unsigned int tkip_mic_ok : 1; /* TKIP Mic compare result */
7758 + unsigned int ccm_mic_ok : 1; /* CCM Mic compare result */
7759 + unsigned int : 16;
7760 + unsigned int parser_err_code: 4; /* Authentication Compare result */
7761 + unsigned int auth_err_code : 4; /* Authentication module error code */
7762 + unsigned int cipher_err_code: 4; /* Cipher module erroe code */
7763 +#else
7764 + unsigned int cipher_err_code: 4; /* Cipher module erroe code */
7765 + unsigned int auth_err_code : 4; /* Authentication module error code */
7766 + unsigned int parser_err_code: 4; /* Authentication Compare result */
7767 + unsigned int : 16;
7768 + unsigned int ccm_mic_ok : 1; /* CCM Mic compare result */
7769 + unsigned int tkip_mic_ok : 1; /* TKIP Mic compare result */
7770 + unsigned int wep_crc_ok : 1; /* WEP ICV compare result */
7771 + unsigned int auth_cmp_rslt : 1; /* Authentication Compare result */
7772 +#endif
7773 + } bits;
7774 +} IPSEC_STATUS_T;
7775 +
7776 +
7777 +
7778 +/************************************************************************/
7779 +/* IPSec Descriptor Format */
7780 +/************************************************************************/
7781 +typedef struct descriptor_t
7782 +{
7783 + union frame_control_t
7784 + {
7785 + unsigned int bits32;
7786 + struct bits_0000
7787 + {
7788 +#if (BIG_ENDIAN==1)
7789 + unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */
7790 + unsigned int derr : 1; /* data error during processing this descriptor */
7791 + unsigned int perr : 1; /* protocol error during processing this descriptor */
7792 + unsigned int : 1; /* authentication compare result */
7793 + unsigned int : 6; /* checksum[15:8] */
7794 + unsigned int desc_count : 6; /* number of descriptors used for the current frame */
7795 + unsigned int buffer_size:16; /* transfer buffer size associated with current description*/
7796 +#else
7797 + unsigned int buffer_size:16; /* transfer buffer size associated with current description*/
7798 + unsigned int desc_count : 6; /* number of descriptors used for the current frame */
7799 + unsigned int : 6; /* checksum[15:8] */
7800 + unsigned int : 1; /* authentication compare result */
7801 + unsigned int perr : 1; /* protocol error during processing this descriptor */
7802 + unsigned int derr : 1; /* data error during processing this descriptor */
7803 + unsigned int own : 1; /* owner bit. 0-CPU, 1-DMA */
7804 +#endif
7805 + } bits;
7806 + } frame_ctrl;
7807 +
7808 + union flag_status_t
7809 + {
7810 + unsigned int bits32;
7811 + struct bits_0004
7812 + {
7813 +#if (BIG_ENDIAN==1)
7814 +// unsigned int checksum : 8; /* checksum[7:0] */
7815 + unsigned int : 4;
7816 + unsigned int auth_result: 1;
7817 + unsigned int wep_crc_ok : 1;
7818 + unsigned int tkip_mic_ok: 1;
7819 + unsigned int ccmp_mic_ok: 1;
7820 + unsigned int process_id : 8;
7821 + unsigned int frame_count:16;
7822 +#else
7823 + unsigned int frame_count:16;
7824 + unsigned int process_id : 8;
7825 + unsigned int ccmp_mic_ok: 1;
7826 + unsigned int tkip_mic_ok: 1;
7827 + unsigned int wep_crc_ok : 1;
7828 + unsigned int auth_result: 1;
7829 + unsigned int : 4;
7830 +// unsigned int checksum : 8; /* checksum[7:0] */
7831 +#endif
7832 + } bits_rx_status;
7833 +
7834 + struct bits_0005
7835 + {
7836 +#if (BIG_ENDIAN==1)
7837 + unsigned int : 8;
7838 + unsigned int process_id : 8;
7839 + unsigned int frame_count:16;
7840 +#else
7841 + unsigned int frame_count:16;
7842 + unsigned int process_id : 8;
7843 + unsigned int : 8;
7844 +#endif
7845 + } bits_tx_status;
7846 +
7847 + struct bits_0006
7848 + {
7849 +#if (BIG_ENDIAN==1)
7850 + unsigned int :22;
7851 + unsigned int tqflag :10;
7852 +#else
7853 + unsigned int tqflag :10;
7854 + unsigned int :22;
7855 +#endif
7856 + } bits_tx_flag;
7857 + } flag_status;
7858 +
7859 + unsigned int buf_adr; /* data buffer address */
7860 +
7861 + union next_desc_t
7862 + {
7863 + unsigned int next_descriptor;
7864 + struct bits_000c
7865 + {
7866 +#if (BIG_ENDIAN==1)
7867 + unsigned int ndar :28; /* next descriptor address */
7868 + unsigned int eofie : 1; /* end of frame interrupt enable */
7869 + unsigned int dec : 1; /* AHB bus address. 0-increment; 1-decrement */
7870 + unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/
7871 + /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/
7872 +#else
7873 + unsigned int sof_eof : 2; /* 00-the linking descriptor 01-the last descriptor of a frame*/
7874 + /* 10-the first descriptor of a frame 11-only one descriptor for a frame*/
7875 + unsigned int dec : 1; /* AHB bus address. 0-increment; 1-decrement */
7876 + unsigned int eofie : 1; /* end of frame interrupt enable */
7877 + unsigned int ndar :28; /* next descriptor address */
7878 +#endif
7879 + } bits;
7880 + } next_desc;
7881 +} IPSEC_DESCRIPTOR_T;
7882 +
7883 +
7884 +typedef struct IPSEC_S
7885 +{
7886 + unsigned char *tx_bufs;
7887 + unsigned char *rx_bufs;
7888 + IPSEC_DESCRIPTOR_T *tx_desc; /* point to virtual TX descriptor address*/
7889 + IPSEC_DESCRIPTOR_T *rx_desc; /* point to virtual RX descriptor address*/
7890 + IPSEC_DESCRIPTOR_T *tx_cur_desc; /* point to current TX descriptor */
7891 + IPSEC_DESCRIPTOR_T *rx_cur_desc; /* point to current RX descriptor */
7892 + IPSEC_DESCRIPTOR_T *tx_finished_desc;
7893 + IPSEC_DESCRIPTOR_T *rx_finished_desc;
7894 + dma_addr_t rx_desc_dma; /* physical RX descriptor address */
7895 + dma_addr_t tx_desc_dma; /* physical TX descriptor address */
7896 + dma_addr_t rx_bufs_dma; /* physical RX descriptor address */
7897 + dma_addr_t tx_bufs_dma; /* physical TX descriptor address */
7898 +} IPSEC_T;
7899 +
7900 +
7901 +/*=====================================================================================================*/
7902 +/* Data Structure of IPSEC Control Packet */
7903 +/*=====================================================================================================*/
7904 +typedef struct IPSEC_ECB_AUTH_S
7905 +{
7906 + IPSEC_CONTROL_T control; /* control parameter */
7907 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7908 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */
7909 + unsigned char cipher_key[8*4];
7910 + unsigned char auth_check_val[5*4];
7911 +} IPSEC_ECB_AUTH_T;
7912 +
7913 +typedef struct IPSEC_CBC_AUTH_S
7914 +{
7915 + IPSEC_CONTROL_T control; /* control parameter */
7916 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7917 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */
7918 + unsigned char cipher_iv[4*4];
7919 + unsigned char cipher_key[8*4];
7920 + unsigned char auth_check_val[5*4];
7921 +} IPSEC_CBC_AUTH_T;
7922 +
7923 +typedef struct IPSEC_ECB_HMAC_AUTH_S
7924 +{
7925 + IPSEC_CONTROL_T control; /* control parameter */
7926 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7927 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */
7928 + unsigned char cipher_key[8*4];
7929 + unsigned char auth_key[16*4];
7930 + unsigned char auth_check_val[5*4];
7931 +} IPSEC_ECB_AUTH_HMAC_T;
7932 +
7933 +typedef struct IPSEC_CBC_HMAC_AUTH_S
7934 +{
7935 + IPSEC_CONTROL_T control; /* control parameter */
7936 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7937 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */
7938 + unsigned char cipher_iv[4*4];
7939 + unsigned char cipher_key[8*4];
7940 + unsigned char auth_key[16*4];
7941 + unsigned char auth_check_val[5*4];
7942 +} IPSEC_CBC_AUTH_HMAC_T;
7943 +
7944 +typedef struct IPSEC_HMAC_AUTH_S
7945 +{
7946 + IPSEC_CONTROL_T control; /* control parameter */
7947 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter */
7948 + unsigned char auth_key[16*4];
7949 + unsigned char auth_check_val[5*4];
7950 +} IPSEC_HMAC_AUTH_T;
7951 +
7952 +typedef union
7953 +{
7954 + unsigned char auth_pkt[28];
7955 +
7956 + struct IPSEC_AUTH_S
7957 + {
7958 + IPSEC_CONTROL_T control; /* control parameter(4-byte) */
7959 + IPSEC_AUTH_PACKET_T auth; /* authentication packet parameter(4-byte) */
7960 + unsigned char auth_check_val[5*4];
7961 + } var;
7962 +} IPSEC_AUTH_T;
7963 +
7964 +typedef struct IPSEC_CIPHER_CBC_S
7965 +{
7966 + IPSEC_CONTROL_T control; /* control parameter */
7967 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7968 + unsigned char cipher_iv[4*4];
7969 + unsigned char cipher_key[8*4];
7970 +} IPSEC_CIPHER_CBC_T;
7971 +
7972 +typedef struct IPSEC_CIPHER_ECB_S
7973 +{
7974 + IPSEC_CONTROL_T control; /* control parameter */
7975 + IPSEC_CIPHER_PACKET_T cipher; /* cipher packet parameter */
7976 + unsigned char cipher_key[8*4];
7977 +} IPSEC_CIPHER_ECB_T;
7978 +
7979 +
7980 +/****************************************************************************
7981 + * Structure Definition *
7982 + ****************************************************************************/
7983 +struct IPSEC_PACKET_S
7984 +{
7985 + unsigned int op_mode; /* CIPHER_ENC(1),CIPHER_DEC(3),AUTH(4),ENC_AUTH(5),AUTH_DEC(7) */
7986 + unsigned int cipher_algorithm; /* ECB_DES(0),ECB_3DES(1),ECB_AES(2),CBC_DES(4),CBC_3DES(5),CBC_AES(6) */
7987 + unsigned int auth_algorithm; /* SHA1(0),MD5(1),HMAC_SHA1(2),HMAC_MD5(3),FCS(4) */
7988 + unsigned int auth_result_mode; /* AUTH_APPEND(0),AUTH_CHKVAL(1) */
7989 + unsigned int process_id; /* Used to identify the process */
7990 + unsigned int auth_header_len; /* Header length to be skipped by the authenticator */
7991 + unsigned int auth_algorithm_len; /* Length of message body that is to be authenticated */
7992 + unsigned int cipher_header_len; /* Header length to be skipped by the cipher */
7993 + unsigned int cipher_algorithm_len; /* Length of message body to be encrypted or decrypted */
7994 + unsigned char iv[16]; /* Initial vector used for DES,3DES,AES */
7995 + unsigned int iv_size; /* Initial vector size */
7996 + unsigned char auth_key[64]; /* authentication key */
7997 + unsigned int auth_key_size; /* authentication key size */
7998 + unsigned char cipher_key[32]; /* cipher key */
7999 + unsigned int cipher_key_size; /* cipher key size */
8000 + struct scatterlist *in_packet; /* input_packet buffer pointer */
8001 + //unsigned char *in_packet; /* input_packet buffer pointer */
8002 + unsigned int pkt_len; /* input total packet length */
8003 + unsigned char auth_checkval[20]; /* Authentication check value/FCS check value */
8004 + struct IPSEC_PACKET_S *next,*prev; /* pointer to next/previous operation to perform on buffer */
8005 + void (*callback)(struct IPSEC_PACKET_S *); /* function to call when done authentication/cipher */
8006 + unsigned char *out_packet; /* output_packet buffer pointer */
8007 + //struct scatterlist *out_packet; /* output_packet buffer pointer */
8008 + unsigned int out_pkt_len; /* output total packet length */
8009 + unsigned int auth_cmp_result; /* authentication compare result */
8010 + unsigned int checksum; /* checksum value */
8011 + unsigned int status; /* ipsec return status. 0:success, others:fail */
8012 +#if (IPSEC_TEST == 1)
8013 + unsigned char *sw_packet; /* for test only */
8014 + unsigned int sw_pkt_len; /* for test only */
8015 +#endif
8016 +} ;
8017 +
8018 +/*****************************************************************************
8019 + * Function : ipsec_crypto_hw_process
8020 + * Description : This function processes H/W authentication and cipher.
8021 + * Input : op_info - the authentication and cipher information for IPSec module.
8022 + * Output : none.
8023 + * Return : 0 - success, others - failure.
8024 + *****************************************************************************/
8025 +int ipsec_crypto_hw_process(struct IPSEC_PACKET_S *op_info);
8026 +
8027 +int ipsec_get_cipher_algorithm(unsigned char *alg_name,unsigned int alg_mode);
8028 +int ipsec_get_auth_algorithm(unsigned char *alg_name,unsigned int alg_mode);
8029 +#if 0
8030 +void ipsec_sw_authentication(char *data,unsigned int data_len,char *authkey,char authAlgorithm,char *auth_result);
8031 +void ipsec_sw_cipher(unsigned char *pt,unsigned int pt_len, unsigned char *cipher_key, unsigned int key_size,
8032 + unsigned char *iv,unsigned int cipherAlgorithm,unsigned char *ct);
8033 +void ipsec_sw_auth_cipher(unsigned int op_mode,char *data,unsigned int data_len,
8034 + BYTE *auth_key,char authAlgorithm,char *auth_result,
8035 + char *pt, unsigned int pt_len,char *cipher_key, int key_size,
8036 + char *iv, char cipherAlgorithm,char *ct);
8037 +#endif
8038 +
8039 +
8040 +#endif
8041 --- /dev/null
8042 +++ b/include/asm-arm/arch-sl2312/sl_random.h
8043 @@ -0,0 +1,2 @@
8044 +#define RANDOM_ADD (IO_ADDRESS (0x051000000) + 0x0AC)
8045 +
8046 --- /dev/null
8047 +++ b/include/asm-arm/arch-sl2312/system.h
8048 @@ -0,0 +1,54 @@
8049 +/*
8050 + * linux/include/asm-arm/arch-sl2312/system.h
8051 + *
8052 + * Copyright (C) 1999 ARM Limited
8053 + * Copyright (C) 2000 Deep Blue Solutions Ltd
8054 + * Copyright (C) 2001 Altera Corporation
8055 + *
8056 + * This program is free software; you can redistribute it and/or modify
8057 + * it under the terms of the GNU General Public License as published by
8058 + * the Free Software Foundation; either version 2 of the License, or
8059 + * (at your option) any later version.
8060 + *
8061 + * This program is distributed in the hope that it will be useful,
8062 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8063 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8064 + * GNU General Public License for more details.
8065 + *
8066 + * You should have received a copy of the GNU General Public License
8067 + * along with this program; if not, write to the Free Software
8068 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8069 + */
8070 +#ifndef __ASM_ARCH_SYSTEM_H
8071 +#define __ASM_ARCH_SYSTEM_H
8072 +
8073 +#include <asm/arch/platform.h>
8074 +#include <asm/arch/hardware.h>
8075 +#include <asm/arch/it8712.h>
8076 +#include <asm/io.h>
8077 +
8078 +static void arch_idle(void)
8079 +{
8080 + /*
8081 + * This should do all the clock switching
8082 + * and wait for interrupt tricks
8083 + */
8084 + cpu_do_idle();
8085 +}
8086 +
8087 +extern __inline__ void arch_reset(char mode)
8088 +{
8089 + __raw_writel( (int) GLOBAL_RESET|RESET_CPU1, IO_ADDRESS(SL2312_GLOBAL_BASE) + GLOBAL_RESET_REG);
8090 +}
8091 +
8092 +
8093 +void (*pm_power_off)(void);
8094 +//{
8095 +// printk("arch_power_off\n");
8096 +
8097 + // Power off
8098 +// __raw_writel( (int) 0x00000001, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
8099 +
8100 +//}
8101 +
8102 +#endif
8103 --- /dev/null
8104 +++ b/include/asm-arm/arch-sl2312/timer.h
8105 @@ -0,0 +1,53 @@
8106 +/*
8107 + *
8108 + * This file contains the register definitions for the Excalibur
8109 + * Timer TIMER00.
8110 + *
8111 + * Copyright (C) 2001 Altera Corporation
8112 + *
8113 + * This program is free software; you can redistribute it and/or modify
8114 + * it under the terms of the GNU General Public License as published by
8115 + * the Free Software Foundation; either version 2 of the License, or
8116 + * (at your option) any later version.
8117 + *
8118 + * This program is distributed in the hope that it will be useful,
8119 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8120 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8121 + * GNU General Public License for more details.
8122 + *
8123 + * You should have received a copy of the GNU General Public License
8124 + * along with this program; if not, write to the Free Software
8125 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8126 + */
8127 +#ifndef __TIMER_H
8128 +#define __TIMER_H
8129 +
8130 +/*
8131 + * Register definitions for the timers
8132 + */
8133 +
8134 +#define TIMER_COUNT(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x00 ))
8135 +#define TIMER_LOAD(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x04 ))
8136 +#define TIMER_MATCH1(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x08 ))
8137 +#define TIMER_MATCH2(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x0C ))
8138 +#define TIMER_CR(BASE_ADDR) (TIMER_TYPE (BASE_ADDR + 0x30 ))
8139 +#define TIMER_1_CR_ENABLE_MSK (0x00000001)
8140 +#define TIMER_1_CR_ENABLE_OFST (0)
8141 +#define TIMER_1_CR_CLOCK_MSK (0x00000002)
8142 +#define TIMER_1_CR_CLOCK_OFST (1)
8143 +#define TIMER_1_CR_INT_MSK (0x00000004)
8144 +#define TIMER_1_CR_INT_OFST (2)
8145 +#define TIMER_2_CR_ENABLE_MSK (0x00000008)
8146 +#define TIMER_2_CR_ENABLE_OFST (3)
8147 +#define TIMER_2_CR_CLOCK_MSK (0x00000010)
8148 +#define TIMER_2_CR_CLOCK_OFST (4)
8149 +#define TIMER_2_CR_INT_MSK (0x00000020)
8150 +#define TIMER_2_CR_INT_OFST (5)
8151 +#define TIMER_3_CR_ENABLE_MSK (0x00000040)
8152 +#define TIMER_3_CR_ENABLE_OFST (6)
8153 +#define TIMER_3_CR_CLOCK_MSK (0x00000080)
8154 +#define TIMER_3_CR_CLOCK_OFST (7)
8155 +#define TIMER_3_CR_INT_MSK (0x00000100)
8156 +#define TIMER_3_CR_INT_OFST (8)
8157 +
8158 +#endif /* __TIMER00_H */
8159 --- /dev/null
8160 +++ b/include/asm-arm/arch-sl2312/timex.h
8161 @@ -0,0 +1,29 @@
8162 +/*
8163 + * linux/include/asm-arm/arch-epxa10db/timex.h
8164 + *
8165 + * Excalibur timex specifications
8166 + *
8167 + * Copyright (C) 2001 Altera Corporation
8168 + *
8169 + * This program is free software; you can redistribute it and/or modify
8170 + * it under the terms of the GNU General Public License as published by
8171 + * the Free Software Foundation; either version 2 of the License, or
8172 + * (at your option) any later version.
8173 + *
8174 + * This program is distributed in the hope that it will be useful,
8175 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8176 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8177 + * GNU General Public License for more details.
8178 + *
8179 + * You should have received a copy of the GNU General Public License
8180 + * along with this program; if not, write to the Free Software
8181 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8182 + */
8183 +
8184 +/*
8185 + * ??
8186 + */
8187 +#include <asm/arch/sl2312.h>
8188 +
8189 +#define CLOCK_TICK_RATE APB_CLK
8190 +
8191 --- /dev/null
8192 +++ b/include/asm-arm/arch-sl2312/uart.h
8193 @@ -0,0 +1,100 @@
8194 +/* *
8195 + * Copyright (C) 2001 Altera Corporation
8196 + *
8197 + * This program is free software; you can redistribute it and/or modify
8198 + * it under the terms of the GNU General Public License as published by
8199 + * the Free Software Foundation; either version 2 of the License, or
8200 + * (at your option) any later version.
8201 + *
8202 + * This program is distributed in the hope that it will be useful,
8203 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8204 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8205 + * GNU General Public License for more details.
8206 + *
8207 + * You should have received a copy of the GNU General Public License
8208 + * along with this program; if not, write to the Free Software
8209 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8210 + */
8211 +#ifndef __UART_H
8212 +#define __UART_H
8213 +
8214 +/*
8215 + * Register definitions for the UART
8216 + */
8217 +
8218 +#define UART_TX_FIFO_SIZE (15)
8219 +
8220 +#define UART_RBR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x00)) // read
8221 +#define UART_THR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x00)) // write
8222 +#define UART_IER(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x04))
8223 +#define UART_IER_MS (0x08)
8224 +#define UART_IER_RLS (0x04)
8225 +#define UART_IER_TE (0x02)
8226 +#define UART_IER_DR (0x01)
8227 +#define UART_IIR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x08)) // read
8228 +#define UART_IIR_NONE (0x01) /* No interrupt pending */
8229 +#define UART_IIR_RLS (0x06) /* Receive Line Status */
8230 +#define UART_IIR_DR (0x04) /* Receive Data Ready */
8231 +#define UART_IIR_TIMEOUT (0x0c) /* Receive Time Out */
8232 +#define UART_IIR_TE (0x02) /* THR Empty */
8233 +#define UART_IIR_MODEM (0x00) /* Modem Status */
8234 +#define UART_FCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x08)) // write
8235 +#define UART_FCR_FE (0x01) /* FIFO Enable */
8236 +#define UART_FCR_RXFR (0x02) /* Rx FIFO Reset */
8237 +#define UART_FCR_TXFR (0x04) /* Tx FIFO Reset */
8238 +#define UART_FCR_FIFO_1C (0x00)
8239 +#define UART_FCR_FIFO_4C (0x40)
8240 +#define UART_FCR_FIFO_8C (0x80)
8241 +#define UART_FCR_FIFO_14C (0xC0)
8242 +#define UART_LCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x0C))
8243 +#define UART_LCR_MSK (0x03)
8244 +#define UART_LCR_LEN5 (0x00)
8245 +#define UART_LCR_LEN6 (0x01)
8246 +#define UART_LCR_LEN7 (0x02)
8247 +#define UART_LCR_LEN8 (0x03)
8248 +#define UART_LCR_STOP (0x04)
8249 +#define UART_LCR_EVEN (0x18) /* Even Parity */
8250 +#define UART_LCR_ODD (0x08) /* Odd Parity */
8251 +#define UART_LCR_PE (0x08) /* Parity Enable */
8252 +#define UART_LCR_SETBREAK (0x40) /* Set Break condition */
8253 +#define UART_LCR_STICKPARITY (0x20) /* Stick Parity Enable */
8254 +#define UART_LCR_DLAB (0x80) /* Divisor Latch Access Bit */
8255 +#define UART_MCR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x10))
8256 +#define UART_MCR_DTR (0x1) /* Data Terminal Ready */
8257 +#define UART_MCR_RTS (0x2) /* Request to Send */
8258 +#define UART_MCR_OUT1 (0x4) /* output 1 */
8259 +#define UART_MCR_OUT2 (0x8) /* output2 or global interrupt enable */
8260 +#define UART_MCR_LPBK (0x10) /* loopback mode */
8261 +#define UART_MCR_MASK (0xE3)
8262 +#define UART_LSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x14))
8263 +#define UART_LSR_DR (0x01) /* Data Ready */
8264 +#define UART_LSR_OE (0x02) /* Overrun Error */
8265 +#define UART_LSR_PE (0x04) /* Parity Error */
8266 +#define UART_LSR_FE (0x08) /* Framing Error */
8267 +#define UART_LSR_BI (0x10) /* Break Interrupt */
8268 +#define UART_LSR_THRE (0x20) /* THR Empty */
8269 +#define UART_LSR_TE (0x40) /* Transmitte Empty */
8270 +#define UART_LSR_DE (0x80) /* FIFO Data Error */
8271 +#define UART_MSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x18))
8272 +#define UART_MSR_DELTACTS (0x01) /* Delta CTS */
8273 +#define UART_MSR_DELTADSR (0x02) /* Delta DSR */
8274 +#define UART_MSR_TERI (0x04) /* Trailing Edge RI */
8275 +#define UART_MSR_DELTACD (0x08) /* Delta CD */
8276 +#define UART_MSR_CTS (0x10) /* Clear To Send */
8277 +#define UART_MSR_DSR (0x20) /* Data Set Ready */
8278 +#define UART_MSR_RI (0x40) /* Ring Indicator */
8279 +#define UART_MSR_DCD (0x80) /* Data Carrier Detect */
8280 +#define UART_SPR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x1C))
8281 +#define UART_DIV_LO(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x0))
8282 +#define UART_DIV_HI(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x4))
8283 +#define UART_PSR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x8))
8284 +#define UART_MDR(BASE_ADDR) (UART_TYPE (BASE_ADDR + 0x20))
8285 +#define UART_MDR_SERIAL (0x0)
8286 +
8287 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
8288 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
8289 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
8290 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
8291 +
8292 +
8293 +#endif /* __UART_H */
8294 --- /dev/null
8295 +++ b/include/asm-arm/arch-sl2312/uncompress.h
8296 @@ -0,0 +1,94 @@
8297 +/*
8298 + * linux/include/asm-arm/arch-epxa10db/uncompress.h
8299 + *
8300 + * Copyright (C) 1999 ARM Limited
8301 + * Copyright (C) 2001 Altera Corporation
8302 + *
8303 + * This program is free software; you can redistribute it and/or modify
8304 + * it under the terms of the GNU General Public License as published by
8305 + * the Free Software Foundation; either version 2 of the License, or
8306 + * (at your option) any later version.
8307 + *
8308 + * This program is distributed in the hope that it will be useful,
8309 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8310 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8311 + * GNU General Public License for more details.
8312 + *
8313 + * You should have received a copy of the GNU General Public License
8314 + * along with this program; if not, write to the Free Software
8315 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8316 + */
8317 +#include "asm/arch/platform.h"
8318 +#include "asm/arch/hardware.h"
8319 +#define UART_TYPE (volatile unsigned int*)
8320 +#ifndef CONFIG_SERIAL_IT8712
8321 +#include "asm/arch/uart.h"
8322 +#endif
8323 +extern unsigned int it8712_uart_base;
8324 +
8325 +/*
8326 + * This does not append a newline
8327 + */
8328 +static void putstr(const char *s)
8329 +{
8330 +
8331 +#ifdef CONFIG_SERIAL_IT8712
8332 +
8333 + unsigned char *base,*status,stat;
8334 + int i ;
8335 +
8336 + status = (unsigned char*)it8712_uart_base + 5;
8337 + base = (unsigned char*)it8712_uart_base ;
8338 +
8339 + while (*s) {
8340 +
8341 + stat = *status;
8342 + while (!(stat&0x20)) { // check status
8343 + for(i=0;i<0x10;i++) ;
8344 + status = (unsigned char*)it8712_uart_base + 5;
8345 + stat = *status ;
8346 + }
8347 +
8348 + *base = *s;
8349 + barrier();
8350 +
8351 + if (*s == '\n') {
8352 + stat = *status;
8353 + while (!(stat&0x20)) { // check status
8354 + for(i=0;i<0x10;i++) ;
8355 + status = (unsigned char*)it8712_uart_base + 5;
8356 + stat = *status ;
8357 + }
8358 +
8359 + barrier();
8360 + *base = '\r';
8361 + }
8362 + s++;
8363 + }
8364 +
8365 +#else
8366 + while (*s) {
8367 + while (!(*UART_LSR(SL2312_UART_BASE) &
8368 + UART_LSR_THRE));
8369 + barrier();
8370 +
8371 + *UART_THR(SL2312_UART_BASE) = *s;
8372 +
8373 + if (*s == '\n') {
8374 + while (!(*UART_LSR(SL2312_UART_BASE) &
8375 + UART_LSR_THRE));
8376 + barrier();
8377 +
8378 + *UART_THR(SL2312_UART_BASE) = '\r';
8379 + }
8380 + s++;
8381 + }
8382 +#endif
8383 +}
8384 +
8385 +/*
8386 + * nothing to do
8387 + */
8388 +#define arch_decomp_setup()
8389 +
8390 +#define arch_decomp_wdog()
8391 --- /dev/null
8392 +++ b/include/asm-arm/arch-sl2312/vmalloc.h
8393 @@ -0,0 +1,36 @@
8394 +/*
8395 + * linux/include/asm-arm/arch-epxa10db/vmalloc.h
8396 + *
8397 + * Copyright (C) 2000 Russell King.
8398 + *
8399 + * This program is free software; you can redistribute it and/or modify
8400 + * it under the terms of the GNU General Public License as published by
8401 + * the Free Software Foundation; either version 2 of the License, or
8402 + * (at your option) any later version.
8403 + *
8404 + * This program is distributed in the hope that it will be useful,
8405 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8406 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8407 + * GNU General Public License for more details.
8408 + *
8409 + * You should have received a copy of the GNU General Public License
8410 + * along with this program; if not, write to the Free Software
8411 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8412 + */
8413 +
8414 +/*
8415 + * Just any arbitrary offset to the start of the vmalloc VM area: the
8416 + * current 8MB value just means that there will be a 8MB "hole" after the
8417 + * physical memory until the kernel virtual memory starts. That means that
8418 + * any out-of-bounds memory accesses will hopefully be caught.
8419 + * The vmalloc() routines leaves a hole of 4kB between each vmalloced
8420 + * area for the same reason. ;)
8421 + */
8422 +#define VMALLOC_OFFSET (8*1024*1024)
8423 +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
8424 +#define VMALLOC_VMADDR(x) ((unsigned long)(x))
8425 +#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
8426 +
8427 +//#define MODULE_START (PAGE_OFFSET - 16*1048576)
8428 +//#define MODULE_END (PAGE_OFFSET)
8429 +
8430 --- /dev/null
8431 +++ b/include/asm-arm/arch-sl2312/watchdog.h
8432 @@ -0,0 +1,58 @@
8433 +#ifndef __WATCHDOG_H
8434 +#define __WATCHDOG_H
8435 +
8436 +#define WATCHDOG_BASE (IO_ADDRESS (SL2312_WAQTCHDOG_BASE))
8437 +#define WATCHDOG_COUNTER (WATCHDOG_BASE + 0x00)
8438 +#define WATCHDOG_LOAD (WATCHDOG_BASE + 0x04)
8439 +#define WATCHDOG_RESTART (WATCHDOG_BASE + 0x08)
8440 +#define WATCHDOG_CR (WATCHDOG_BASE + 0x0C)
8441 +#define WATCHDOG_STATUS (WATCHDOG_BASE + 0x10)
8442 +#define WATCHDOG_CLEAR (WATCHDOG_BASE + 0x14)
8443 +#define WATCHDOG_INTRLEN (WATCHDOG_BASE + 0x18)
8444 +
8445 +#define WATCHDOG_WDENABLE_MSK (0x00000001)
8446 +#define WATCHDOG_WDENABLE_OFST (0)
8447 +#define WATCHDOG_WDRST_MSK (0x00000002)
8448 +#define WATCHDOG_WDRST_OFST (1)
8449 +#define WATCHDOG_WDINTR_MSK (0x00000004)
8450 +#define WATCHDOG_WDINTR_OFST (2)
8451 +#define WATCHDOG_WDEXT_MSK (0x00000008)
8452 +#define WATCHDOG_WDEXT_OFST (3)
8453 +#define WATCHDOG_WDCLOCK_MSK (0x00000010)
8454 +#define WATCHDOG_WDCLOCK_OFST (4)
8455 +#define WATCHDOG_CR_MASK (0x0000001F)
8456 +
8457 +#define WATCHDOG_CLEAR_STATUS 0x1
8458 +#define WATCHDOG_ENABLE 1
8459 +#define WATCHDOG_DISABLE 0
8460 +#define WATCHDOG_RESTART_VALUE 0x5AB9
8461 +
8462 +#define WATCHDOG_MINOR 130
8463 +
8464 +#define WATCHDOG_IOCTRL_DISABLE 0x01
8465 +#define WATCHDOG_IOCTRL_SETTIME 0x02
8466 +#define WATCHDOG_IOCTRL_ENABLE 0x03
8467 +#define WATCHDOG_IOCTRL_RESTART 0x04
8468 +
8469 +#define WATCHDOG_TIMEOUT_SCALE APB_CLK
8470 +#define WATCHDOG_TIMEOUT_MARGIN 30
8471 +#define WATCHDOG_DRIVER_OPEN 1
8472 +#define WATCHDOG_DRIVER_CLOSE 0
8473 +
8474 +
8475 +static void watchdog_disable(void);
8476 +static void watchdog_enable(void);
8477 +static int watchdog_open(struct inode *, struct file *);
8478 +static int watchdog_release(struct inode *, struct file *);
8479 +static ssize_t watchdog_read(struct file *, char *, size_t, loff_t *);
8480 +static ssize_t watchdog_write(struct file *, const char *, size_t, loff_t *);
8481 +static int watchdog_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
8482 +#ifdef WATCHDOG_TEST
8483 +static void watchdog_fire(int, void *, struct pt_regs *);
8484 +#endif
8485 +
8486 +
8487 +
8488 +
8489 +
8490 +#endif
8491 --- /dev/null
8492 +++ b/include/asm-arm/arch-sl2312/xor.h
8493 @@ -0,0 +1,29 @@
8494 +/*
8495 + * include/asm-arm/arch-sl2312/xor.h
8496 + *
8497 + * Copyright (C) 2005 Storlink Corp.
8498 + *
8499 + * This program is free software; you can redistribute it and/or modify
8500 + * it under the terms of the GNU General Public License version 2 as
8501 + * published by the Free Software Foundation.
8502 + */
8503 +
8504 +#ifndef _ASM_ARCH_XOR_H
8505 +#define _ASM_ARCH_XOR_H
8506 +
8507 +/*
8508 + * Function prototypes
8509 + */
8510 +void xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2);
8511 +
8512 +void xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8513 + unsigned long *p3);
8514 +
8515 +void xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8516 + unsigned long *p3, unsigned long *p4);
8517 +
8518 +void xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8519 + unsigned long *p3, unsigned long *p4, unsigned long *p5);
8520 +
8521 +#endif /* _ASM_ARCH_XOR_H */
8522 +
8523 --- a/include/asm-arm/cacheflush.h
8524 +++ b/include/asm-arm/cacheflush.h
8525 @@ -46,6 +46,18 @@
8526 # define MULTI_CACHE 1
8527 #endif
8528
8529 +/***********************************************************************
8530 + * Storlink SoC -- Cache
8531 + ***********************************************************************/
8532 +#if defined(CONFIG_CPU_FA526)
8533 +# ifdef _CACHE
8534 +# define MULTI_CACHE 1
8535 +# else
8536 +# define _CACHE fa
8537 +# endif
8538 +#endif
8539 +/***********************************************************************/
8540 +
8541 #if defined(CONFIG_CPU_ARM926T)
8542 # ifdef _CACHE
8543 # define MULTI_CACHE 1
8544 --- a/include/asm-arm/page.h
8545 +++ b/include/asm-arm/page.h
8546 @@ -74,6 +74,18 @@
8547 # endif
8548 #endif
8549
8550 +/***********************************************************************
8551 + * Storlink SoC -- flash
8552 + ***********************************************************************/
8553 +#ifdef CONFIG_CPU_COPY_FA
8554 +# ifdef _USER
8555 +# define MULTI_USER 1
8556 +# else
8557 +# define _USER fa
8558 +# endif
8559 +#endif
8560 +/***********************************************************************/
8561 +
8562 #ifdef CONFIG_CPU_SA1100
8563 # ifdef _USER
8564 # define MULTI_USER 1
8565 --- a/include/asm-arm/proc-fns.h
8566 +++ b/include/asm-arm/proc-fns.h
8567 @@ -89,6 +89,14 @@
8568 # define CPU_NAME cpu_arm922
8569 # endif
8570 # endif
8571 +# ifdef CONFIG_CPU_FA526
8572 +# ifdef CPU_NAME
8573 +# undef MULTI_CPU
8574 +# define MULTI_CPU
8575 +# else
8576 +# define CPU_NAME cpu_fa526
8577 +# endif
8578 +# endif
8579 # ifdef CONFIG_CPU_ARM925T
8580 # ifdef CPU_NAME
8581 # undef MULTI_CPU
8582 --- a/include/asm-arm/tlbflush.h
8583 +++ b/include/asm-arm/tlbflush.h
8584 @@ -39,6 +39,8 @@
8585 #define TLB_V6_D_ASID (1 << 17)
8586 #define TLB_V6_I_ASID (1 << 18)
8587
8588 +#define TLB_DINVAL (1 << 28)
8589 +#define TLB_BTB (1 << 29)
8590 #define TLB_DCLEAN (1 << 30)
8591 #define TLB_WB (1 << 31)
8592
8593 @@ -52,6 +54,7 @@
8594 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
8595 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
8596 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
8597 + * fa - ARMv4 with write buffer with UTLB and branch target buffer (BTB)
8598 */
8599 #undef _TLB
8600 #undef MULTI_TLB
8601 @@ -86,6 +89,44 @@
8602 # define v4_always_flags (-1UL)
8603 #endif
8604
8605 +#ifdef CONFIG_CPU_FA_BTB
8606 +#define __TLB_BTB TLB_BTB
8607 +#else
8608 +#define __TLB_BTB 0
8609 +#endif
8610 +
8611 +#ifdef CONFIG_CPU_FA_WB_DISABLE
8612 +#define __TLB_WB 0
8613 +#else
8614 +#define __TLB_WB TLB_WB
8615 +#endif
8616 +
8617 +/* Fix buggy CPU which doesn't invalidate Dcache properly */
8618 +#ifdef CONFIG_CPU_FA520
8619 +#define __TLB_DINVAL TLB_DINVAL
8620 +#elif defined(CONFIG_CPU_FA526)
8621 +//#define __TLB_DINVAL TLB_DINVAL
8622 +#define __TLB_DINVAL 0
8623 +#else
8624 +#define __TLB_DINVAL 0
8625 +#endif
8626 +
8627 +#define fa_tlb_flags (__TLB_WB | __TLB_BTB | __TLB_DINVAL | TLB_DCLEAN | \
8628 + TLB_V4_U_FULL | TLB_V4_U_PAGE)
8629 +
8630 +#ifdef CONFIG_CPU_TLB_FA
8631 +# define fa_possible_flags fa_tlb_flags
8632 +# define fa_always_flags fa_tlb_flags
8633 +# ifdef _TLB
8634 +# define MULTI_TLB 1
8635 +# else
8636 +# define _TLB fa
8637 +# endif
8638 +#else
8639 +# define fa_possible_flags 0
8640 +# define fa_always_flags (-1UL)
8641 +#endif
8642 +
8643 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
8644 TLB_V4_I_FULL | TLB_V4_D_FULL | \
8645 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
8646 @@ -246,12 +287,14 @@
8647 v4_possible_flags | \
8648 v4wbi_possible_flags | \
8649 v4wb_possible_flags | \
8650 + fa_possible_flags | \
8651 v6wbi_possible_flags)
8652
8653 #define always_tlb_flags (v3_always_flags & \
8654 v4_always_flags & \
8655 v4wbi_always_flags & \
8656 v4wb_always_flags & \
8657 + fa_always_flags & \
8658 v6wbi_always_flags)
8659
8660 #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
8661 @@ -261,6 +304,9 @@
8662 const int zero = 0;
8663 const unsigned int __tlb_flag = __cpu_tlb_flags;
8664
8665 + if (tlb_flag(TLB_DINVAL))
8666 + asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8667 +
8668 if (tlb_flag(TLB_WB))
8669 dsb();
8670
8671 @@ -281,6 +327,13 @@
8672 dsb();
8673 isb();
8674 }
8675 +
8676 + if (tlb_flag(TLB_BTB))
8677 + {
8678 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8679 + asm("mov r0, r0" : : );
8680 + asm("mov r0, r0" : : );
8681 + }
8682 }
8683
8684 static inline void local_flush_tlb_mm(struct mm_struct *mm)
8685 @@ -289,6 +342,9 @@
8686 const int asid = ASID(mm);
8687 const unsigned int __tlb_flag = __cpu_tlb_flags;
8688
8689 + if (tlb_flag(TLB_DINVAL))
8690 + asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8691 +
8692 if (tlb_flag(TLB_WB))
8693 dsb();
8694
8695 @@ -317,6 +373,14 @@
8696 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
8697 dsb();
8698 }
8699 +
8700 + if (tlb_flag(TLB_BTB))
8701 + {
8702 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8703 + asm("mov r0, r0" : : );
8704 + asm("mov r0, r0" : : );
8705 + }
8706 +
8707 }
8708
8709 static inline void
8710 @@ -327,6 +391,9 @@
8711
8712 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
8713
8714 + if (tlb_flag(TLB_DINVAL))
8715 + asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); // clean & invalidate data cache all
8716 +
8717 if (tlb_flag(TLB_WB))
8718 dsb();
8719
8720 @@ -357,6 +424,13 @@
8721 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
8722 dsb();
8723 }
8724 +
8725 + if (tlb_flag(TLB_BTB))
8726 + {
8727 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8728 + asm("mov r0, r0" : : );
8729 + asm("mov r0, r0" : : );
8730 + }
8731 }
8732
8733 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
8734 @@ -366,6 +440,9 @@
8735
8736 kaddr &= PAGE_MASK;
8737
8738 + if (tlb_flag(TLB_DINVAL))
8739 + asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8740 +
8741 if (tlb_flag(TLB_WB))
8742 dsb();
8743
8744 @@ -386,6 +463,12 @@
8745 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
8746 if (tlb_flag(TLB_V6_I_PAGE))
8747 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
8748 + if (tlb_flag(TLB_BTB))
8749 + {
8750 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8751 + asm("mov r0, r0" : : );
8752 + asm("mov r0, r0" : : );
8753 + }
8754
8755 if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
8756 TLB_V6_I_PAGE | TLB_V6_D_PAGE |
8757 @@ -412,6 +495,7 @@
8758 */
8759 static inline void flush_pmd_entry(pmd_t *pmd)
8760 {
8761 + const unsigned int zero = 0;
8762 const unsigned int __tlb_flag = __cpu_tlb_flags;
8763
8764 if (tlb_flag(TLB_DCLEAN))
8765 @@ -419,15 +503,30 @@
8766 : : "r" (pmd) : "cc");
8767 if (tlb_flag(TLB_WB))
8768 dsb();
8769 +
8770 + if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005
8771 + {
8772 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8773 + asm("mov r0, r0" : : );
8774 + asm("mov r0, r0" : : );
8775 + }
8776 }
8777
8778 static inline void clean_pmd_entry(pmd_t *pmd)
8779 {
8780 + const unsigned int zero = 0; // Luke Lee 05/16/2005 ins 1
8781 const unsigned int __tlb_flag = __cpu_tlb_flags;
8782
8783 if (tlb_flag(TLB_DCLEAN))
8784 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
8785 : : "r" (pmd) : "cc");
8786 +
8787 + if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005
8788 + {
8789 + asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8790 + asm("mov r0, r0" : : );
8791 + asm("mov r0, r0" : : );
8792 + }
8793 }
8794
8795 #undef tlb_flag
8796 --- a/include/asm-arm/xor.h
8797 +++ b/include/asm-arm/xor.h
8798 @@ -139,3 +139,18 @@
8799 xor_speed(&xor_block_8regs); \
8800 xor_speed(&xor_block_32regs); \
8801 } while (0)
8802 +
8803 +#ifdef CONFIG_GEMINI_XOR_ACCE
8804 +#include <asm/arch/xor.h>
8805 +static struct xor_block_template xor_block_gemini = {
8806 + .name = "gemini xor acceleration",
8807 + .do_2 = xor_gemini_2,
8808 + .do_3 = xor_gemini_3,
8809 + .do_4 = xor_gemini_4,
8810 + .do_5 = xor_gemini_5,};
8811 +#undef XOR_TRY_TEMPLATES
8812 +#define XOR_TRY_TEMPLATES \
8813 + do { \
8814 + xor_speed(&xor_block_gemini); \
8815 + } while (0)
8816 +#endif
8817 --- a/include/linux/apm_bios.h
8818 +++ b/include/linux/apm_bios.h
8819 @@ -217,4 +217,24 @@
8820 #define APM_IOC_STANDBY _IO('A', 1)
8821 #define APM_IOC_SUSPEND _IO('A', 2)
8822
8823 +// add by jason for power control
8824 +struct pwc_ioctl_data {
8825 + unsigned int action; // sword struct
8826 + unsigned int data; // stand shutdown time for PWC_SET_SHUT_TIME
8827 + // stand shutdown source for PWC_WAIT_BTN
8828 +};
8829 +
8830 +#define POWEROFF 0x01
8831 +#define RESTORE_DEFAULT 0x02
8832 +#define SYSTEM_REBOOT 0x04
8833 +
8834 +#define PWR_SRC_CIR 0x10
8835 +#define PWR_SRC_RTC 0x20
8836 +#define PWR_SRC_BTN 0x40
8837 +
8838 +#define PWC_IOCTL_BASE 'A' // use linux APM ioctl
8839 +#define PWC_SET_SHUT_TIME _IOW('A', 16, struct pwc_ioctl_data)
8840 +#define PWC_WAIT_BTN _IOR('A', 17, struct pwc_ioctl_data)
8841 +#define PWC_SHUTDOWN _IO ('A', 18)
8842 +
8843 #endif /* LINUX_APM_H */
8844 --- a/kernel/time.c
8845 +++ b/kernel/time.c
8846 @@ -76,6 +76,7 @@
8847 * why not move it into the appropriate arch directory (for those
8848 * architectures that need it).
8849 */
8850 +extern void rtc_set_time_second(unsigned int second);
8851
8852 asmlinkage long sys_stime(time_t __user *tptr)
8853 {
8854 @@ -87,6 +88,10 @@
8855
8856 tv.tv_nsec = 0;
8857
8858 +#ifdef CONFIG_SL2312_RTC
8859 + rtc_set_time_second(tv.tv_sec);
8860 +#endif
8861 +
8862 err = security_settime(&tv, NULL);
8863 if (err)
8864 return err;
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