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ae3b50bba5714bc71e0a039f9a81c344452f7757
[openwrt.git] / target / linux / generic-2.6 / patches-2.6.27 / 978-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -1,10 +1,11 @@
4 -menu "Sonics Silicon Backplane"
5 -
6 config SSB_POSSIBLE
7 bool
8 depends on HAS_IOMEM && HAS_DMA
9 default y
10
11 +menu "Sonics Silicon Backplane"
12 + depends on SSB_POSSIBLE
13 +
14 config SSB
15 tristate "Sonics Silicon Backplane support"
16 depends on SSB_POSSIBLE
17 @@ -52,11 +53,11 @@ config SSB_B43_PCI_BRIDGE
18
19 config SSB_PCMCIAHOST_POSSIBLE
20 bool
21 - depends on SSB && (PCMCIA = y || PCMCIA = SSB) && EXPERIMENTAL
22 + depends on SSB && (PCMCIA = y || PCMCIA = SSB)
23 default y
24
25 config SSB_PCMCIAHOST
26 - bool "Support for SSB on PCMCIA-bus host (EXPERIMENTAL)"
27 + bool "Support for SSB on PCMCIA-bus host"
28 depends on SSB_PCMCIAHOST_POSSIBLE
29 select SSB_SPROM
30 help
31 @@ -106,14 +107,14 @@ config SSB_DRIVER_PCICORE
32 If unsure, say Y
33
34 config SSB_PCICORE_HOSTMODE
35 - bool "Hostmode support for SSB PCI core (EXPERIMENTAL)"
36 - depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS && EXPERIMENTAL
37 + bool "Hostmode support for SSB PCI core"
38 + depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS
39 help
40 PCIcore hostmode operation (external PCI bus).
41
42 config SSB_DRIVER_MIPS
43 - bool "SSB Broadcom MIPS core driver (EXPERIMENTAL)"
44 - depends on SSB && MIPS && EXPERIMENTAL
45 + bool "SSB Broadcom MIPS core driver"
46 + depends on SSB && MIPS
47 select SSB_SERIAL
48 help
49 Driver for the Sonics Silicon Backplane attached
50 @@ -125,11 +126,13 @@ config SSB_DRIVER_MIPS
51 config SSB_EMBEDDED
52 bool
53 depends on SSB_DRIVER_MIPS
54 + select USB_EHCI_HCD_SSB if USB_EHCI_HCD
55 + select USB_OHCI_HCD_SSB if USB_OHCI_HCD
56 default y
57
58 config SSB_DRIVER_EXTIF
59 - bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
60 - depends on SSB_DRIVER_MIPS && EXPERIMENTAL
61 + bool "SSB Broadcom EXTIF core driver"
62 + depends on SSB_DRIVER_MIPS
63 help
64 Driver for the Sonics Silicon Backplane attached
65 Broadcom EXTIF core.
66 --- a/drivers/ssb/Makefile
67 +++ b/drivers/ssb/Makefile
68 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
69
70 # built-in drivers
71 ssb-y += driver_chipcommon.o
72 +ssb-y += driver_chipcommon_pmu.o
73 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
74 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
75 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
76 --- a/drivers/ssb/b43_pci_bridge.c
77 +++ b/drivers/ssb/b43_pci_bridge.c
78 @@ -18,9 +18,11 @@
79
80 static const struct pci_device_id b43_pci_bridge_tbl[] = {
81 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4301) },
82 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4306) },
83 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
84 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
85 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
86 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
87 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
88 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
89 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
90 @@ -29,6 +31,7 @@ static const struct pci_device_id b43_pc
91 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
92 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
93 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
94 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
95 { 0, },
96 };
97 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
98 --- a/drivers/ssb/driver_chipcommon.c
99 +++ b/drivers/ssb/driver_chipcommon.c
100 @@ -26,19 +26,6 @@ enum ssb_clksrc {
101 };
102
103
104 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
105 - u16 offset)
106 -{
107 - return ssb_read32(cc->dev, offset);
108 -}
109 -
110 -static inline void chipco_write32(struct ssb_chipcommon *cc,
111 - u16 offset,
112 - u32 value)
113 -{
114 - ssb_write32(cc->dev, offset, value);
115 -}
116 -
117 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
118 u32 mask, u32 value)
119 {
120 --- a/drivers/ssb/main.c
121 +++ b/drivers/ssb/main.c
122 @@ -473,6 +473,8 @@ static int ssb_devices_register(struct s
123 case SSB_BUSTYPE_SSB:
124 dev->dma_mask = &dev->coherent_dma_mask;
125 break;
126 + default:
127 + break;
128 }
129
130 sdev->dev = dev;
131 @@ -1359,8 +1361,10 @@ static int __init ssb_modinit(void)
132 ssb_buses_lock();
133 err = ssb_attach_queued_buses();
134 ssb_buses_unlock();
135 - if (err)
136 + if (err) {
137 bus_unregister(&ssb_bustype);
138 + goto out;
139 + }
140
141 err = b43_pci_ssb_bridge_init();
142 if (err) {
143 @@ -1376,7 +1380,7 @@ static int __init ssb_modinit(void)
144 /* don't fail SSB init because of this */
145 err = 0;
146 }
147 -
148 +out:
149 return err;
150 }
151 /* ssb must be initialized after PCI but before the ssb drivers.
152 --- a/drivers/ssb/pci.c
153 +++ b/drivers/ssb/pci.c
154 @@ -169,8 +169,14 @@ err_pci:
155 /* Get the word-offset for a SSB_SPROM_XXX define. */
156 #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
157 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
158 -#define SPEX(_outvar, _offset, _mask, _shift) \
159 +#define SPEX16(_outvar, _offset, _mask, _shift) \
160 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
161 +#define SPEX32(_outvar, _offset, _mask, _shift) \
162 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
163 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
164 +#define SPEX(_outvar, _offset, _mask, _shift) \
165 + SPEX16(_outvar, _offset, _mask, _shift)
166 +
167
168 static inline u8 ssb_crc8(u8 crc, u8 data)
169 {
170 @@ -327,11 +333,9 @@ static void sprom_extract_r123(struct ss
171 s8 gain;
172 u16 loc[3];
173
174 - if (out->revision == 3) { /* rev 3 moved MAC */
175 + if (out->revision == 3) /* rev 3 moved MAC */
176 loc[0] = SSB_SPROM3_IL0MAC;
177 - loc[1] = SSB_SPROM3_ET0MAC;
178 - loc[2] = SSB_SPROM3_ET1MAC;
179 - } else {
180 + else {
181 loc[0] = SSB_SPROM1_IL0MAC;
182 loc[1] = SSB_SPROM1_ET0MAC;
183 loc[2] = SSB_SPROM1_ET1MAC;
184 @@ -340,13 +344,15 @@ static void sprom_extract_r123(struct ss
185 v = in[SPOFF(loc[0]) + i];
186 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
187 }
188 - for (i = 0; i < 3; i++) {
189 - v = in[SPOFF(loc[1]) + i];
190 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
191 - }
192 - for (i = 0; i < 3; i++) {
193 - v = in[SPOFF(loc[2]) + i];
194 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
195 + if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
196 + for (i = 0; i < 3; i++) {
197 + v = in[SPOFF(loc[1]) + i];
198 + *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
199 + }
200 + for (i = 0; i < 3; i++) {
201 + v = in[SPOFF(loc[2]) + i];
202 + *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
203 + }
204 }
205 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
206 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
207 @@ -399,30 +405,33 @@ static void sprom_extract_r123(struct ss
208 out->antenna_gain.ghz5.a3 = gain;
209 }
210
211 -static void sprom_extract_r4(struct ssb_sprom *out, const u16 *in)
212 +static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
213 {
214 int i;
215 u16 v;
216 + u16 il0mac_offset;
217
218 - /* extract the equivalent of the r1 variables */
219 + if (out->revision == 4)
220 + il0mac_offset = SSB_SPROM4_IL0MAC;
221 + else
222 + il0mac_offset = SSB_SPROM5_IL0MAC;
223 + /* extract the MAC address */
224 for (i = 0; i < 3; i++) {
225 - v = in[SPOFF(SSB_SPROM4_IL0MAC) + i];
226 + v = in[SPOFF(il0mac_offset) + i];
227 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
228 }
229 - for (i = 0; i < 3; i++) {
230 - v = in[SPOFF(SSB_SPROM4_ET0MAC) + i];
231 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
232 - }
233 - for (i = 0; i < 3; i++) {
234 - v = in[SPOFF(SSB_SPROM4_ET1MAC) + i];
235 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
236 - }
237 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
238 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
239 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
240 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
241 - SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
242 - SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
243 + if (out->revision == 4) {
244 + SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
245 + SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
246 + SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
247 + } else {
248 + SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
249 + SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
250 + SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
251 + }
252 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
253 SSB_SPROM4_ANTAVAIL_A_SHIFT);
254 SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
255 @@ -433,12 +442,21 @@ static void sprom_extract_r4(struct ssb_
256 SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
257 SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
258 SSB_SPROM4_ITSSI_A_SHIFT);
259 - SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
260 - SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
261 - SSB_SPROM4_GPIOA_P1_SHIFT);
262 - SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
263 - SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
264 - SSB_SPROM4_GPIOB_P3_SHIFT);
265 + if (out->revision == 4) {
266 + SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
267 + SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
268 + SSB_SPROM4_GPIOA_P1_SHIFT);
269 + SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
270 + SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
271 + SSB_SPROM4_GPIOB_P3_SHIFT);
272 + } else {
273 + SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
274 + SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
275 + SSB_SPROM5_GPIOA_P1_SHIFT);
276 + SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
277 + SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
278 + SSB_SPROM5_GPIOB_P3_SHIFT);
279 + }
280
281 /* Extract the antenna gain values. */
282 SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
283 @@ -455,6 +473,96 @@ static void sprom_extract_r4(struct ssb_
284 /* TODO - get remaining rev 4 stuff needed */
285 }
286
287 +static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
288 +{
289 + int i;
290 + u16 v;
291 +
292 + /* extract the MAC address */
293 + for (i = 0; i < 3; i++) {
294 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
295 + *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
296 + }
297 + SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
298 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
299 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
300 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
301 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
302 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
303 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
304 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
305 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
306 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
307 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
308 + SSB_SPROM8_ITSSI_BG_SHIFT);
309 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
310 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
311 + SSB_SPROM8_ITSSI_A_SHIFT);
312 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
313 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
314 + SSB_SPROM8_MAXP_AL_SHIFT);
315 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
316 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
317 + SSB_SPROM8_GPIOA_P1_SHIFT);
318 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
319 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
320 + SSB_SPROM8_GPIOB_P3_SHIFT);
321 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
322 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
323 + SSB_SPROM8_TRI5G_SHIFT);
324 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
325 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
326 + SSB_SPROM8_TRI5GH_SHIFT);
327 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
328 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
329 + SSB_SPROM8_RXPO5G_SHIFT);
330 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
331 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
332 + SSB_SPROM8_RSSISMC2G_SHIFT);
333 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
334 + SSB_SPROM8_RSSISAV2G_SHIFT);
335 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
336 + SSB_SPROM8_BXA2G_SHIFT);
337 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
338 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
339 + SSB_SPROM8_RSSISMC5G_SHIFT);
340 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
341 + SSB_SPROM8_RSSISAV5G_SHIFT);
342 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
343 + SSB_SPROM8_BXA5G_SHIFT);
344 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
345 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
346 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
347 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
348 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
349 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
350 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
351 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
352 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
353 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
354 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
355 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
356 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
357 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
358 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
359 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
360 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
361 +
362 + /* Extract the antenna gain values. */
363 + SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
364 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
365 + SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
366 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
367 + SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
368 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
369 + SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
370 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
371 + memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
372 + sizeof(out->antenna_gain.ghz5));
373 +
374 + /* TODO - get remaining rev 8 stuff needed */
375 +}
376 +
377 static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
378 const u16 *in, u16 size)
379 {
380 @@ -462,6 +570,8 @@ static int sprom_extract(struct ssb_bus
381
382 out->revision = in[size - 1] & 0x00FF;
383 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
384 + memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
385 + memset(out->et1mac, 0xFF, 6);
386 if ((bus->chip_id & 0xFF00) == 0x4400) {
387 /* Workaround: The BCM44XX chip has a stupid revision
388 * number stored in the SPROM.
389 @@ -471,17 +581,28 @@ static int sprom_extract(struct ssb_bus
390 } else if (bus->chip_id == 0x4321) {
391 /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
392 out->revision = 4;
393 - sprom_extract_r4(out, in);
394 + sprom_extract_r45(out, in);
395 } else {
396 - if (out->revision == 0)
397 - goto unsupported;
398 - if (out->revision >= 1 && out->revision <= 3) {
399 + switch (out->revision) {
400 + case 1:
401 + case 2:
402 + case 3:
403 + sprom_extract_r123(out, in);
404 + break;
405 + case 4:
406 + case 5:
407 + sprom_extract_r45(out, in);
408 + break;
409 + case 8:
410 + sprom_extract_r8(out, in);
411 + break;
412 + default:
413 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
414 + " revision %d detected. Will extract"
415 + " v1\n", out->revision);
416 + out->revision = 1;
417 sprom_extract_r123(out, in);
418 }
419 - if (out->revision == 4)
420 - sprom_extract_r4(out, in);
421 - if (out->revision >= 5)
422 - goto unsupported;
423 }
424
425 if (out->boardflags_lo == 0xFFFF)
426 @@ -490,11 +611,6 @@ static int sprom_extract(struct ssb_bus
427 out->boardflags_hi = 0; /* per specs */
428
429 return 0;
430 -unsupported:
431 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
432 - "detected. Will extract v1\n", out->revision);
433 - sprom_extract_r123(out, in);
434 - return 0;
435 }
436
437 static int ssb_pci_sprom_get(struct ssb_bus *bus,
438 --- a/drivers/ssb/pcmcia.c
439 +++ b/drivers/ssb/pcmcia.c
440 @@ -80,7 +80,7 @@ static int ssb_pcmcia_cfg_write(struct s
441 reg.Action = CS_WRITE;
442 reg.Value = value;
443 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
444 - if (unlikely(res != CS_SUCCESS))
445 + if (unlikely(res != 0))
446 return -EBUSY;
447
448 return 0;
449 @@ -96,7 +96,7 @@ static int ssb_pcmcia_cfg_read(struct ss
450 reg.Offset = offset;
451 reg.Action = CS_READ;
452 res = pcmcia_access_configuration_register(bus->host_pcmcia, &reg);
453 - if (unlikely(res != CS_SUCCESS))
454 + if (unlikely(res != 0))
455 return -EBUSY;
456 *value = reg.Value;
457
458 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
459 ssb_printk(".");
460 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
461 if (err) {
462 - ssb_printk("\n" KERN_NOTICE PFX
463 + ssb_printk(KERN_NOTICE PFX
464 "Failed to write to SPROM.\n");
465 failed = 1;
466 break;
467 @@ -591,7 +591,7 @@ static int ssb_pcmcia_sprom_write_all(st
468 }
469 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
470 if (err) {
471 - ssb_printk("\n" KERN_NOTICE PFX
472 + ssb_printk(KERN_NOTICE PFX
473 "Could not disable SPROM write access.\n");
474 failed = 1;
475 }
476 @@ -638,17 +638,17 @@ int ssb_pcmcia_get_invariants(struct ssb
477 tuple.TupleData = buf;
478 tuple.TupleDataMax = sizeof(buf);
479 res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
480 - GOTO_ERROR_ON(res != CS_SUCCESS, "MAC first tpl");
481 + GOTO_ERROR_ON(res != 0, "MAC first tpl");
482 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
483 - GOTO_ERROR_ON(res != CS_SUCCESS, "MAC first tpl data");
484 + GOTO_ERROR_ON(res != 0, "MAC first tpl data");
485 while (1) {
486 GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
487 if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
488 break;
489 res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
490 - GOTO_ERROR_ON(res != CS_SUCCESS, "MAC next tpl");
491 + GOTO_ERROR_ON(res != 0, "MAC next tpl");
492 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
493 - GOTO_ERROR_ON(res != CS_SUCCESS, "MAC next tpl data");
494 + GOTO_ERROR_ON(res != 0, "MAC next tpl data");
495 }
496 GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
497 memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
498 @@ -659,9 +659,9 @@ int ssb_pcmcia_get_invariants(struct ssb
499 tuple.TupleData = buf;
500 tuple.TupleDataMax = sizeof(buf);
501 res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
502 - GOTO_ERROR_ON(res != CS_SUCCESS, "VEN first tpl");
503 + GOTO_ERROR_ON(res != 0, "VEN first tpl");
504 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
505 - GOTO_ERROR_ON(res != CS_SUCCESS, "VEN first tpl data");
506 + GOTO_ERROR_ON(res != 0, "VEN first tpl data");
507 while (1) {
508 GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
509 switch (tuple.TupleData[0]) {
510 @@ -678,7 +678,8 @@ int ssb_pcmcia_get_invariants(struct ssb
511 sprom->board_rev = tuple.TupleData[1];
512 break;
513 case SSB_PCMCIA_CIS_PA:
514 - GOTO_ERROR_ON(tuple.TupleDataLen != 9,
515 + GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
516 + (tuple.TupleDataLen != 10),
517 "pa tpl size");
518 sprom->pa0b0 = tuple.TupleData[1] |
519 ((u16)tuple.TupleData[2] << 8);
520 @@ -718,7 +719,8 @@ int ssb_pcmcia_get_invariants(struct ssb
521 sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
522 break;
523 case SSB_PCMCIA_CIS_BFLAGS:
524 - GOTO_ERROR_ON(tuple.TupleDataLen != 3,
525 + GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
526 + (tuple.TupleDataLen != 5),
527 "bfl tpl size");
528 sprom->boardflags_lo = tuple.TupleData[1] |
529 ((u16)tuple.TupleData[2] << 8);
530 @@ -733,11 +735,11 @@ int ssb_pcmcia_get_invariants(struct ssb
531 break;
532 }
533 res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
534 - if (res == CS_NO_MORE_ITEMS)
535 + if (res == -ENOSPC)
536 break;
537 - GOTO_ERROR_ON(res != CS_SUCCESS, "VEN next tpl");
538 + GOTO_ERROR_ON(res != 0, "VEN next tpl");
539 res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
540 - GOTO_ERROR_ON(res != CS_SUCCESS, "VEN next tpl data");
541 + GOTO_ERROR_ON(res != 0, "VEN next tpl data");
542 }
543
544 return 0;
545 --- a/drivers/ssb/scan.c
546 +++ b/drivers/ssb/scan.c
547 @@ -175,6 +175,8 @@ static u32 scan_read32(struct ssb_bus *b
548 } else
549 ssb_pcmcia_switch_segment(bus, 0);
550 break;
551 + default:
552 + break;
553 }
554 return readl(bus->mmio + offset);
555 }
556 @@ -188,6 +190,8 @@ static int scan_switchcore(struct ssb_bu
557 return ssb_pci_switch_coreidx(bus, coreidx);
558 case SSB_BUSTYPE_PCMCIA:
559 return ssb_pcmcia_switch_coreidx(bus, coreidx);
560 + default:
561 + break;
562 }
563 return 0;
564 }
565 @@ -206,6 +210,8 @@ void ssb_iounmap(struct ssb_bus *bus)
566 SSB_BUG_ON(1); /* Can't reach this code. */
567 #endif
568 break;
569 + default:
570 + break;
571 }
572 bus->mmio = NULL;
573 bus->mapped_device = NULL;
574 @@ -230,6 +236,8 @@ static void __iomem *ssb_ioremap(struct
575 SSB_BUG_ON(1); /* Can't reach this code. */
576 #endif
577 break;
578 + default:
579 + break;
580 }
581
582 return mmio;
583 --- a/include/linux/ssb/ssb.h
584 +++ b/include/linux/ssb/ssb.h
585 @@ -27,24 +27,54 @@ struct ssb_sprom {
586 u8 et1mdcport; /* MDIO for enet1 */
587 u8 board_rev; /* Board revision number from SPROM. */
588 u8 country_code; /* Country Code */
589 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
590 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
591 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
592 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
593 u16 pa0b0;
594 u16 pa0b1;
595 u16 pa0b2;
596 u16 pa1b0;
597 u16 pa1b1;
598 u16 pa1b2;
599 + u16 pa1lob0;
600 + u16 pa1lob1;
601 + u16 pa1lob2;
602 + u16 pa1hib0;
603 + u16 pa1hib1;
604 + u16 pa1hib2;
605 u8 gpio0; /* GPIO pin 0 */
606 u8 gpio1; /* GPIO pin 1 */
607 u8 gpio2; /* GPIO pin 2 */
608 u8 gpio3; /* GPIO pin 3 */
609 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
610 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
611 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
612 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
613 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
614 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
615 u8 itssi_a; /* Idle TSSI Target for A-PHY */
616 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
617 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
618 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
619 + u8 tri2g; /* 2.4GHz TX isolation */
620 + u8 tri5gl; /* 5.2GHz TX isolation */
621 + u8 tri5g; /* 5.3GHz TX isolation */
622 + u8 tri5gh; /* 5.8GHz TX isolation */
623 + u8 rxpo2g; /* 2GHz RX power offset */
624 + u8 rxpo5g; /* 5GHz RX power offset */
625 + u8 rssisav2g; /* 2GHz RSSI params */
626 + u8 rssismc2g;
627 + u8 rssismf2g;
628 + u8 bxa2g; /* 2GHz BX arch */
629 + u8 rssisav5g; /* 5GHz RSSI params */
630 + u8 rssismc5g;
631 + u8 rssismf5g;
632 + u8 bxa5g; /* 5GHz BX arch */
633 + u16 cck2gpo; /* CCK power offset */
634 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
635 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
636 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
637 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
638 + u16 boardflags_lo; /* Board flags (bits 0-15) */
639 + u16 boardflags_hi; /* Board flags (bits 16-31) */
640 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
641 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
642 + /* TODO store board flags in a single u64 */
643
644 /* Antenna gain values for up to 4 antennas
645 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
646 @@ -58,7 +88,7 @@ struct ssb_sprom {
647 } ghz5; /* 5GHz band */
648 } antenna_gain;
649
650 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
651 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
652 };
653
654 /* Information about the PCB the circuitry is soldered on. */
655 @@ -208,6 +238,7 @@ enum ssb_bustype {
656 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
657 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
658 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
659 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
660 };
661
662 /* board_vendor */
663 @@ -240,8 +271,12 @@ struct ssb_bus {
664
665 /* The core in the basic address register window. (PCI bus only) */
666 struct ssb_device *mapped_device;
667 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
668 - u8 mapped_pcmcia_seg;
669 + union {
670 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
671 + u8 mapped_pcmcia_seg;
672 + /* Current SSB base address window for SDIO. */
673 + u32 sdio_sbaddr;
674 + };
675 /* Lock for core and segment switching.
676 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
677 spinlock_t bar_lock;
678 @@ -252,6 +287,11 @@ struct ssb_bus {
679 struct pci_dev *host_pci;
680 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
681 struct pcmcia_device *host_pcmcia;
682 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
683 + struct sdio_func *host_sdio;
684 +
685 + /* See enum ssb_quirks */
686 + unsigned int quirks;
687
688 #ifdef CONFIG_SSB_SPROM
689 /* Mutex to protect the SPROM writing. */
690 @@ -306,6 +346,11 @@ struct ssb_bus {
691 #endif /* DEBUG */
692 };
693
694 +enum ssb_quirks {
695 + /* SDIO connected card requires performing a read after writing a 32-bit value */
696 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
697 +};
698 +
699 /* The initialization-invariants. */
700 struct ssb_init_invariants {
701 /* Versioning information about the PCB. */
702 @@ -431,12 +476,16 @@ static inline int ssb_dma_mapping_error(
703 {
704 switch (dev->bus->bustype) {
705 case SSB_BUSTYPE_PCI:
706 +#ifdef CONFIG_SSB_PCIHOST
707 return pci_dma_mapping_error(dev->bus->host_pci, addr);
708 +#endif
709 + break;
710 case SSB_BUSTYPE_SSB:
711 return dma_mapping_error(dev->dev, addr);
712 default:
713 - __ssb_dma_not_implemented(dev);
714 + break;
715 }
716 + __ssb_dma_not_implemented(dev);
717 return -ENOSYS;
718 }
719
720 @@ -445,12 +494,16 @@ static inline dma_addr_t ssb_dma_map_sin
721 {
722 switch (dev->bus->bustype) {
723 case SSB_BUSTYPE_PCI:
724 +#ifdef CONFIG_SSB_PCIHOST
725 return pci_map_single(dev->bus->host_pci, p, size, dir);
726 +#endif
727 + break;
728 case SSB_BUSTYPE_SSB:
729 return dma_map_single(dev->dev, p, size, dir);
730 default:
731 - __ssb_dma_not_implemented(dev);
732 + break;
733 }
734 + __ssb_dma_not_implemented(dev);
735 return 0;
736 }
737
738 @@ -459,14 +512,18 @@ static inline void ssb_dma_unmap_single(
739 {
740 switch (dev->bus->bustype) {
741 case SSB_BUSTYPE_PCI:
742 +#ifdef CONFIG_SSB_PCIHOST
743 pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
744 return;
745 +#endif
746 + break;
747 case SSB_BUSTYPE_SSB:
748 dma_unmap_single(dev->dev, dma_addr, size, dir);
749 return;
750 default:
751 - __ssb_dma_not_implemented(dev);
752 + break;
753 }
754 + __ssb_dma_not_implemented(dev);
755 }
756
757 static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
758 @@ -476,15 +533,19 @@ static inline void ssb_dma_sync_single_f
759 {
760 switch (dev->bus->bustype) {
761 case SSB_BUSTYPE_PCI:
762 +#ifdef CONFIG_SSB_PCIHOST
763 pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
764 size, dir);
765 return;
766 +#endif
767 + break;
768 case SSB_BUSTYPE_SSB:
769 dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
770 return;
771 default:
772 - __ssb_dma_not_implemented(dev);
773 + break;
774 }
775 + __ssb_dma_not_implemented(dev);
776 }
777
778 static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
779 @@ -494,15 +555,19 @@ static inline void ssb_dma_sync_single_f
780 {
781 switch (dev->bus->bustype) {
782 case SSB_BUSTYPE_PCI:
783 +#ifdef CONFIG_SSB_PCIHOST
784 pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
785 size, dir);
786 return;
787 +#endif
788 + break;
789 case SSB_BUSTYPE_SSB:
790 dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
791 return;
792 default:
793 - __ssb_dma_not_implemented(dev);
794 + break;
795 }
796 + __ssb_dma_not_implemented(dev);
797 }
798
799 static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
800 @@ -513,17 +578,21 @@ static inline void ssb_dma_sync_single_r
801 {
802 switch (dev->bus->bustype) {
803 case SSB_BUSTYPE_PCI:
804 +#ifdef CONFIG_SSB_PCIHOST
805 /* Just sync everything. That's all the PCI API can do. */
806 pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
807 offset + size, dir);
808 return;
809 +#endif
810 + break;
811 case SSB_BUSTYPE_SSB:
812 dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
813 size, dir);
814 return;
815 default:
816 - __ssb_dma_not_implemented(dev);
817 + break;
818 }
819 + __ssb_dma_not_implemented(dev);
820 }
821
822 static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
823 @@ -534,17 +603,21 @@ static inline void ssb_dma_sync_single_r
824 {
825 switch (dev->bus->bustype) {
826 case SSB_BUSTYPE_PCI:
827 +#ifdef CONFIG_SSB_PCIHOST
828 /* Just sync everything. That's all the PCI API can do. */
829 pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
830 offset + size, dir);
831 return;
832 +#endif
833 + break;
834 case SSB_BUSTYPE_SSB:
835 dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
836 size, dir);
837 return;
838 default:
839 - __ssb_dma_not_implemented(dev);
840 + break;
841 }
842 + __ssb_dma_not_implemented(dev);
843 }
844
845
846 --- a/include/linux/ssb/ssb_driver_chipcommon.h
847 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
848 @@ -181,6 +181,16 @@
849 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
850 #define SSB_CHIPCO_FLASH_CFG 0x0128
851 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
852 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
853 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
854 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
855 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
856 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
857 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
858 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
859 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
860 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
861 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
862 #define SSB_CHIPCO_UART0_DATA 0x0300
863 #define SSB_CHIPCO_UART0_IMR 0x0304
864 #define SSB_CHIPCO_UART0_FCR 0x0308
865 @@ -197,6 +207,196 @@
866 #define SSB_CHIPCO_UART1_LSR 0x0414
867 #define SSB_CHIPCO_UART1_MSR 0x0418
868 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
869 +/* PMU registers (rev >= 20) */
870 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
871 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
872 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
873 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
874 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
875 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
876 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
877 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
878 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
879 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
880 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
881 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
882 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
883 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
884 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
885 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
886 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
887 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
888 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
889 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
890 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
891 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
892 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
893 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
894 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
895 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
896 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
897 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
898 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
899 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
900 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
901 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
902 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
903 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
904 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
905 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
906 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
907 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
908 +
909 +
910 +
911 +/** PMU PLL registers */
912 +
913 +/* PMU rev 0 PLL registers */
914 +#define SSB_PMU0_PLLCTL0 0
915 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
916 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
917 +#define SSB_PMU0_PLLCTL1 1
918 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
919 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
920 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
921 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
922 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
923 +#define SSB_PMU0_PLLCTL2 2
924 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
925 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
926 +
927 +/* PMU rev 1 PLL registers */
928 +#define SSB_PMU1_PLLCTL0 0
929 +#define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
930 +#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20
931 +#define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
932 +#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24
933 +#define SSB_PMU1_PLLCTL1 1
934 +#define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
935 +#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
936 +#define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
937 +#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8
938 +#define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
939 +#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16
940 +#define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
941 +#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24
942 +#define SSB_PMU1_PLLCTL2 2
943 +#define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
944 +#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
945 +#define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
946 +#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8
947 +#define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
948 +#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17
949 +#define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
950 +#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20
951 +#define SSB_PMU1_PLLCTL3 3
952 +#define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
953 +#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
954 +#define SSB_PMU1_PLLCTL4 4
955 +#define SSB_PMU1_PLLCTL5 5
956 +#define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
957 +#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8
958 +
959 +/* BCM4312 PLL resource numbers. */
960 +#define SSB_PMURES_4312_SWITCHER_BURST 0
961 +#define SSB_PMURES_4312_SWITCHER_PWM 1
962 +#define SSB_PMURES_4312_PA_REF_LDO 2
963 +#define SSB_PMURES_4312_CORE_LDO_BURST 3
964 +#define SSB_PMURES_4312_CORE_LDO_PWM 4
965 +#define SSB_PMURES_4312_RADIO_LDO 5
966 +#define SSB_PMURES_4312_ILP_REQUEST 6
967 +#define SSB_PMURES_4312_BG_FILTBYP 7
968 +#define SSB_PMURES_4312_TX_FILTBYP 8
969 +#define SSB_PMURES_4312_RX_FILTBYP 9
970 +#define SSB_PMURES_4312_XTAL_PU 10
971 +#define SSB_PMURES_4312_ALP_AVAIL 11
972 +#define SSB_PMURES_4312_BB_PLL_FILTBYP 12
973 +#define SSB_PMURES_4312_RF_PLL_FILTBYP 13
974 +#define SSB_PMURES_4312_HT_AVAIL 14
975 +
976 +/* BCM4325 PLL resource numbers. */
977 +#define SSB_PMURES_4325_BUCK_BOOST_BURST 0
978 +#define SSB_PMURES_4325_CBUCK_BURST 1
979 +#define SSB_PMURES_4325_CBUCK_PWM 2
980 +#define SSB_PMURES_4325_CLDO_CBUCK_BURST 3
981 +#define SSB_PMURES_4325_CLDO_CBUCK_PWM 4
982 +#define SSB_PMURES_4325_BUCK_BOOST_PWM 5
983 +#define SSB_PMURES_4325_ILP_REQUEST 6
984 +#define SSB_PMURES_4325_ABUCK_BURST 7
985 +#define SSB_PMURES_4325_ABUCK_PWM 8
986 +#define SSB_PMURES_4325_LNLDO1_PU 9
987 +#define SSB_PMURES_4325_LNLDO2_PU 10
988 +#define SSB_PMURES_4325_LNLDO3_PU 11
989 +#define SSB_PMURES_4325_LNLDO4_PU 12
990 +#define SSB_PMURES_4325_XTAL_PU 13
991 +#define SSB_PMURES_4325_ALP_AVAIL 14
992 +#define SSB_PMURES_4325_RX_PWRSW_PU 15
993 +#define SSB_PMURES_4325_TX_PWRSW_PU 16
994 +#define SSB_PMURES_4325_RFPLL_PWRSW_PU 17
995 +#define SSB_PMURES_4325_LOGEN_PWRSW_PU 18
996 +#define SSB_PMURES_4325_AFE_PWRSW_PU 19
997 +#define SSB_PMURES_4325_BBPLL_PWRSW_PU 20
998 +#define SSB_PMURES_4325_HT_AVAIL 21
999 +
1000 +/* BCM4328 PLL resource numbers. */
1001 +#define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
1002 +#define SSB_PMURES_4328_BB_SWITCHER_PWM 1
1003 +#define SSB_PMURES_4328_BB_SWITCHER_BURST 2
1004 +#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
1005 +#define SSB_PMURES_4328_ILP_REQUEST 4
1006 +#define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5
1007 +#define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6
1008 +#define SSB_PMURES_4328_ROM_SWITCH 7
1009 +#define SSB_PMURES_4328_PA_REF_LDO 8
1010 +#define SSB_PMURES_4328_RADIO_LDO 9
1011 +#define SSB_PMURES_4328_AFE_LDO 10
1012 +#define SSB_PMURES_4328_PLL_LDO 11
1013 +#define SSB_PMURES_4328_BG_FILTBYP 12
1014 +#define SSB_PMURES_4328_TX_FILTBYP 13
1015 +#define SSB_PMURES_4328_RX_FILTBYP 14
1016 +#define SSB_PMURES_4328_XTAL_PU 15
1017 +#define SSB_PMURES_4328_XTAL_EN 16
1018 +#define SSB_PMURES_4328_BB_PLL_FILTBYP 17
1019 +#define SSB_PMURES_4328_RF_PLL_FILTBYP 18
1020 +#define SSB_PMURES_4328_BB_PLL_PU 19
1021 +
1022 +/* BCM5354 PLL resource numbers. */
1023 +#define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
1024 +#define SSB_PMURES_5354_BB_SWITCHER_PWM 1
1025 +#define SSB_PMURES_5354_BB_SWITCHER_BURST 2
1026 +#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
1027 +#define SSB_PMURES_5354_ILP_REQUEST 4
1028 +#define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5
1029 +#define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6
1030 +#define SSB_PMURES_5354_ROM_SWITCH 7
1031 +#define SSB_PMURES_5354_PA_REF_LDO 8
1032 +#define SSB_PMURES_5354_RADIO_LDO 9
1033 +#define SSB_PMURES_5354_AFE_LDO 10
1034 +#define SSB_PMURES_5354_PLL_LDO 11
1035 +#define SSB_PMURES_5354_BG_FILTBYP 12
1036 +#define SSB_PMURES_5354_TX_FILTBYP 13
1037 +#define SSB_PMURES_5354_RX_FILTBYP 14
1038 +#define SSB_PMURES_5354_XTAL_PU 15
1039 +#define SSB_PMURES_5354_XTAL_EN 16
1040 +#define SSB_PMURES_5354_BB_PLL_FILTBYP 17
1041 +#define SSB_PMURES_5354_RF_PLL_FILTBYP 18
1042 +#define SSB_PMURES_5354_BB_PLL_PU 19
1043 +
1044 +
1045 +
1046 +/** Chip specific Chip-Status register contents. */
1047 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
1048 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
1049 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
1050 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
1051 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
1052 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
1053 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
1054 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
1055 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
1056 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
1057 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
1058 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
1059
1060
1061
1062 @@ -353,11 +553,20 @@
1063 struct ssb_device;
1064 struct ssb_serial_port;
1065
1066 +/* Data for the PMU, if available.
1067 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
1068 + */
1069 +struct ssb_chipcommon_pmu {
1070 + u8 rev; /* PMU revision */
1071 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
1072 +};
1073 +
1074 struct ssb_chipcommon {
1075 struct ssb_device *dev;
1076 u32 capabilities;
1077 /* Fast Powerup Delay constant */
1078 u16 fast_pwrup_delay;
1079 + struct ssb_chipcommon_pmu pmu;
1080 };
1081
1082 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
1083 @@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
1084 return (cc->dev != NULL);
1085 }
1086
1087 +/* Register access */
1088 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
1089 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
1090 +
1091 +#define chipco_mask32(cc, offset, mask) \
1092 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
1093 +#define chipco_set32(cc, offset, set) \
1094 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
1095 +#define chipco_maskset32(cc, offset, mask, set) \
1096 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
1097 +
1098 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
1099
1100 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
1101 @@ -406,4 +626,18 @@ extern int ssb_chipco_serial_init(struct
1102 struct ssb_serial_port *ports);
1103 #endif /* CONFIG_SSB_SERIAL */
1104
1105 +/* PMU support */
1106 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
1107 +
1108 +enum ssb_pmu_ldo_volt_id {
1109 + LDO_PAREF = 0,
1110 + LDO_VOLT1,
1111 + LDO_VOLT2,
1112 + LDO_VOLT3,
1113 +};
1114 +
1115 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
1116 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
1117 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
1118 +
1119 #endif /* LINUX_SSB_CHIPCO_H_ */
1120 --- a/include/linux/ssb/ssb_regs.h
1121 +++ b/include/linux/ssb/ssb_regs.h
1122 @@ -162,7 +162,7 @@
1123
1124 /* SPROM shadow area. If not otherwise noted, fields are
1125 * two bytes wide. Note that the SPROM can _only_ be read
1126 - * in two-byte quantinies.
1127 + * in two-byte quantities.
1128 */
1129 #define SSB_SPROMSIZE_WORDS 64
1130 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
1131 @@ -245,8 +245,6 @@
1132
1133 /* SPROM Revision 3 (inherits most data from rev 2) */
1134 #define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
1135 -#define SSB_SPROM3_ET0MAC 0x1050 /* 6 bytes MAC address for Ethernet ?? */
1136 -#define SSB_SPROM3_ET1MAC 0x1050 /* 6 bytes MAC address for 802.11a ?? */
1137 #define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
1138 #define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
1139 #define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
1140 @@ -267,8 +265,6 @@
1141
1142 /* SPROM Revision 4 */
1143 #define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
1144 -#define SSB_SPROM4_ET0MAC 0x1018 /* 6 bytes MAC address for Ethernet ?? */
1145 -#define SSB_SPROM4_ET1MAC 0x1018 /* 6 bytes MAC address for 802.11a ?? */
1146 #define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
1147 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
1148 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1149 @@ -316,6 +312,109 @@
1150 #define SSB_SPROM4_PA1B1 0x1090
1151 #define SSB_SPROM4_PA1B2 0x1092
1152
1153 +/* SPROM Revision 5 (inherits most data from rev 4) */
1154 +#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1155 +#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1156 +#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1157 +#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1158 +#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1159 +#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1160 +#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1161 +#define SSB_SPROM5_GPIOA_P1_SHIFT 8
1162 +#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1163 +#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1164 +#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1165 +#define SSB_SPROM5_GPIOB_P3_SHIFT 8
1166 +
1167 +/* SPROM Revision 8 */
1168 +#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1169 +#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1170 +#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1171 +#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1172 +#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1173 +#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1174 +#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1175 +#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1176 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1177 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1178 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1179 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1180 +#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1181 +#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1182 +#define SSB_SPROM8_AGAIN0_SHIFT 0
1183 +#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1184 +#define SSB_SPROM8_AGAIN1_SHIFT 8
1185 +#define SSB_SPROM8_AGAIN23 0x10A0
1186 +#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1187 +#define SSB_SPROM8_AGAIN2_SHIFT 0
1188 +#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1189 +#define SSB_SPROM8_AGAIN3_SHIFT 8
1190 +#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1191 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1192 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1193 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1194 +#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1195 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1196 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1197 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1198 +#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1199 +#define SSB_SPROM8_RSSISMF2G 0x000F
1200 +#define SSB_SPROM8_RSSISMC2G 0x00F0
1201 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
1202 +#define SSB_SPROM8_RSSISAV2G 0x0700
1203 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
1204 +#define SSB_SPROM8_BXA2G 0x1800
1205 +#define SSB_SPROM8_BXA2G_SHIFT 11
1206 +#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1207 +#define SSB_SPROM8_RSSISMF5G 0x000F
1208 +#define SSB_SPROM8_RSSISMC5G 0x00F0
1209 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
1210 +#define SSB_SPROM8_RSSISAV5G 0x0700
1211 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
1212 +#define SSB_SPROM8_BXA5G 0x1800
1213 +#define SSB_SPROM8_BXA5G_SHIFT 11
1214 +#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1215 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1216 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1217 +#define SSB_SPROM8_TRI5G_SHIFT 8
1218 +#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1219 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1220 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1221 +#define SSB_SPROM8_TRI5GH_SHIFT 8
1222 +#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1223 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1224 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1225 +#define SSB_SPROM8_RXPO5G_SHIFT 8
1226 +#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1227 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1228 +#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1229 +#define SSB_SPROM8_ITSSI_BG_SHIFT 8
1230 +#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1231 +#define SSB_SPROM8_PA0B1 0x10C4
1232 +#define SSB_SPROM8_PA0B2 0x10C6
1233 +#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1234 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1235 +#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1236 +#define SSB_SPROM8_ITSSI_A_SHIFT 8
1237 +#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1238 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1239 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1240 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
1241 +#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1242 +#define SSB_SPROM8_PA1B1 0x10CE
1243 +#define SSB_SPROM8_PA1B2 0x10D0
1244 +#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1245 +#define SSB_SPROM8_PA1LOB1 0x10D4
1246 +#define SSB_SPROM8_PA1LOB2 0x10D6
1247 +#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1248 +#define SSB_SPROM8_PA1HIB1 0x10DA
1249 +#define SSB_SPROM8_PA1HIB2 0x10DC
1250 +#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1251 +#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1252 +#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1253 +#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1254 +#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1255 +
1256 /* Values for SSB_SPROM1_BINF_CCODE */
1257 enum {
1258 SSB_SPROM1CCODE_WORLD = 0,
1259 --- /dev/null
1260 +++ b/drivers/ssb/driver_chipcommon_pmu.c
1261 @@ -0,0 +1,602 @@
1262 +/*
1263 + * Sonics Silicon Backplane
1264 + * Broadcom ChipCommon Power Management Unit driver
1265 + *
1266 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
1267 + * Copyright 2007, Broadcom Corporation
1268 + *
1269 + * Licensed under the GNU/GPL. See COPYING for details.
1270 + */
1271 +
1272 +#include <linux/ssb/ssb.h>
1273 +#include <linux/ssb/ssb_regs.h>
1274 +#include <linux/ssb/ssb_driver_chipcommon.h>
1275 +#include <linux/delay.h>
1276 +
1277 +#include "ssb_private.h"
1278 +
1279 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
1280 +{
1281 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
1282 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
1283 +}
1284 +
1285 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
1286 + u32 offset, u32 value)
1287 +{
1288 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
1289 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
1290 +}
1291 +
1292 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
1293 + u32 offset, u32 mask, u32 set)
1294 +{
1295 + u32 value;
1296 +
1297 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
1298 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
1299 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
1300 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
1301 + value &= mask;
1302 + value |= set;
1303 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
1304 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
1305 +}
1306 +
1307 +struct pmu0_plltab_entry {
1308 + u16 freq; /* Crystal frequency in kHz.*/
1309 + u8 xf; /* Crystal frequency value for PMU control */
1310 + u8 wb_int;
1311 + u32 wb_frac;
1312 +};
1313 +
1314 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
1315 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
1316 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
1317 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
1318 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
1319 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
1320 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
1321 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
1322 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
1323 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
1324 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
1325 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
1326 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
1327 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
1328 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
1329 +};
1330 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
1331 +
1332 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
1333 +{
1334 + const struct pmu0_plltab_entry *e;
1335 + unsigned int i;
1336 +
1337 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
1338 + e = &pmu0_plltab[i];
1339 + if (e->freq == crystalfreq)
1340 + return e;
1341 + }
1342 +
1343 + return NULL;
1344 +}
1345 +
1346 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
1347 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
1348 + u32 crystalfreq)
1349 +{
1350 + struct ssb_bus *bus = cc->dev->bus;
1351 + const struct pmu0_plltab_entry *e = NULL;
1352 + u32 pmuctl, tmp, pllctl;
1353 + unsigned int i;
1354 +
1355 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
1356 + /* The 5354 crystal freq is 25MHz */
1357 + crystalfreq = 25000;
1358 + }
1359 + if (crystalfreq)
1360 + e = pmu0_plltab_find_entry(crystalfreq);
1361 + if (!e)
1362 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
1363 + BUG_ON(!e);
1364 + crystalfreq = e->freq;
1365 + cc->pmu.crystalfreq = e->freq;
1366 +
1367 + /* Check if the PLL already is programmed to this frequency. */
1368 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
1369 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
1370 + /* We're already there... */
1371 + return;
1372 + }
1373 +
1374 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
1375 + (crystalfreq / 1000), (crystalfreq % 1000));
1376 +
1377 + /* First turn the PLL off. */
1378 + switch (bus->chip_id) {
1379 + case 0x4328:
1380 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
1381 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
1382 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
1383 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
1384 + break;
1385 + case 0x5354:
1386 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
1387 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
1388 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
1389 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
1390 + break;
1391 + default:
1392 + SSB_WARN_ON(1);
1393 + }
1394 + for (i = 1500; i; i--) {
1395 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
1396 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
1397 + break;
1398 + udelay(10);
1399 + }
1400 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
1401 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
1402 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
1403 +
1404 + /* Set PDIV in PLL control 0. */
1405 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
1406 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
1407 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
1408 + else
1409 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
1410 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
1411 +
1412 + /* Set WILD in PLL control 1. */
1413 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
1414 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
1415 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
1416 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
1417 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
1418 + if (e->wb_frac == 0)
1419 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
1420 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
1421 +
1422 + /* Set WILD in PLL control 2. */
1423 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
1424 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
1425 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
1426 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
1427 +
1428 + /* Set the crystalfrequency and the divisor. */
1429 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
1430 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
1431 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
1432 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
1433 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
1434 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
1435 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
1436 +}
1437 +
1438 +struct pmu1_plltab_entry {
1439 + u16 freq; /* Crystal frequency in kHz.*/
1440 + u8 xf; /* Crystal frequency value for PMU control */
1441 + u8 ndiv_int;
1442 + u32 ndiv_frac;
1443 + u8 p1div;
1444 + u8 p2div;
1445 +};
1446 +
1447 +static const struct pmu1_plltab_entry pmu1_plltab[] = {
1448 + { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
1449 + { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
1450 + { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
1451 + { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
1452 + { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
1453 + { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
1454 + { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
1455 + { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
1456 + { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
1457 + { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
1458 + { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
1459 + { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
1460 + { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
1461 + { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
1462 + { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
1463 +};
1464 +
1465 +#define SSB_PMU1_DEFAULT_XTALFREQ 15360
1466 +
1467 +static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
1468 +{
1469 + const struct pmu1_plltab_entry *e;
1470 + unsigned int i;
1471 +
1472 + for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
1473 + e = &pmu1_plltab[i];
1474 + if (e->freq == crystalfreq)
1475 + return e;
1476 + }
1477 +
1478 + return NULL;
1479 +}
1480 +
1481 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
1482 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
1483 + u32 crystalfreq)
1484 +{
1485 + struct ssb_bus *bus = cc->dev->bus;
1486 + const struct pmu1_plltab_entry *e = NULL;
1487 + u32 buffer_strength = 0;
1488 + u32 tmp, pllctl, pmuctl;
1489 + unsigned int i;
1490 +
1491 + if (bus->chip_id == 0x4312) {
1492 + /* We do not touch the BCM4312 PLL and assume
1493 + * the default crystal settings work out-of-the-box. */
1494 + cc->pmu.crystalfreq = 20000;
1495 + return;
1496 + }
1497 +
1498 + if (crystalfreq)
1499 + e = pmu1_plltab_find_entry(crystalfreq);
1500 + if (!e)
1501 + e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
1502 + BUG_ON(!e);
1503 + crystalfreq = e->freq;
1504 + cc->pmu.crystalfreq = e->freq;
1505 +
1506 + /* Check if the PLL already is programmed to this frequency. */
1507 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
1508 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
1509 + /* We're already there... */
1510 + return;
1511 + }
1512 +
1513 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
1514 + (crystalfreq / 1000), (crystalfreq % 1000));
1515 +
1516 + /* First turn the PLL off. */
1517 + switch (bus->chip_id) {
1518 + case 0x4325:
1519 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
1520 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
1521 + (1 << SSB_PMURES_4325_HT_AVAIL)));
1522 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
1523 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
1524 + (1 << SSB_PMURES_4325_HT_AVAIL)));
1525 + /* Adjust the BBPLL to 2 on all channels later. */
1526 + buffer_strength = 0x222222;
1527 + break;
1528 + default:
1529 + SSB_WARN_ON(1);
1530 + }
1531 + for (i = 1500; i; i--) {
1532 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
1533 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
1534 + break;
1535 + udelay(10);
1536 + }
1537 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
1538 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
1539 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
1540 +
1541 + /* Set p1div and p2div. */
1542 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
1543 + pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
1544 + pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
1545 + pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
1546 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
1547 +
1548 + /* Set ndiv int and ndiv mode */
1549 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
1550 + pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
1551 + pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
1552 + pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
1553 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
1554 +
1555 + /* Set ndiv frac */
1556 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
1557 + pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
1558 + pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
1559 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
1560 +
1561 + /* Change the drive strength, if required. */
1562 + if (buffer_strength) {
1563 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
1564 + pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
1565 + pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
1566 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
1567 + }
1568 +
1569 + /* Tune the crystalfreq and the divisor. */
1570 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
1571 + pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
1572 + pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
1573 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
1574 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
1575 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
1576 +}
1577 +
1578 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
1579 +{
1580 + struct ssb_bus *bus = cc->dev->bus;
1581 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
1582 +
1583 + if (bus->bustype == SSB_BUSTYPE_SSB) {
1584 + /* TODO: The user may override the crystal frequency. */
1585 + }
1586 +
1587 + switch (bus->chip_id) {
1588 + case 0x4312:
1589 + case 0x4325:
1590 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
1591 + break;
1592 + case 0x4328:
1593 + case 0x5354:
1594 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
1595 + break;
1596 + default:
1597 + ssb_printk(KERN_ERR PFX
1598 + "ERROR: PLL init unknown for device %04X\n",
1599 + bus->chip_id);
1600 + }
1601 +}
1602 +
1603 +struct pmu_res_updown_tab_entry {
1604 + u8 resource; /* The resource number */
1605 + u16 updown; /* The updown value */
1606 +};
1607 +
1608 +enum pmu_res_depend_tab_task {
1609 + PMU_RES_DEP_SET = 1,
1610 + PMU_RES_DEP_ADD,
1611 + PMU_RES_DEP_REMOVE,
1612 +};
1613 +
1614 +struct pmu_res_depend_tab_entry {
1615 + u8 resource; /* The resource number */
1616 + u8 task; /* SET | ADD | REMOVE */
1617 + u32 depend; /* The depend mask */
1618 +};
1619 +
1620 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
1621 + { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
1622 + { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
1623 + { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
1624 + { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
1625 + { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
1626 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
1627 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
1628 + { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
1629 + { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
1630 + { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
1631 + { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
1632 + { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
1633 + { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
1634 + { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
1635 + { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
1636 + { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
1637 + { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
1638 + { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
1639 + { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
1640 + { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
1641 +};
1642 +
1643 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
1644 + {
1645 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
1646 + .resource = SSB_PMURES_4328_ILP_REQUEST,
1647 + .task = PMU_RES_DEP_SET,
1648 + .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
1649 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
1650 + },
1651 +};
1652 +
1653 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
1654 + { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
1655 +};
1656 +
1657 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
1658 + {
1659 + /* Adjust HT-Available dependencies. */
1660 + .resource = SSB_PMURES_4325_HT_AVAIL,
1661 + .task = PMU_RES_DEP_ADD,
1662 + .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
1663 + (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
1664 + (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
1665 + (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
1666 + },
1667 +};
1668 +
1669 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
1670 +{
1671 + struct ssb_bus *bus = cc->dev->bus;
1672 + u32 min_msk = 0, max_msk = 0;
1673 + unsigned int i;
1674 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
1675 + unsigned int updown_tab_size;
1676 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
1677 + unsigned int depend_tab_size;
1678 +
1679 + switch (bus->chip_id) {
1680 + case 0x4312:
1681 + /* We keep the default settings:
1682 + * min_msk = 0xCBB
1683 + * max_msk = 0x7FFFF
1684 + */
1685 + break;
1686 + case 0x4325:
1687 + /* Power OTP down later. */
1688 + min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
1689 + (1 << SSB_PMURES_4325_LNLDO2_PU);
1690 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
1691 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
1692 + min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
1693 + /* The PLL may turn on, if it decides so. */
1694 + max_msk = 0xFFFFF;
1695 + updown_tab = pmu_res_updown_tab_4325a0;
1696 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
1697 + depend_tab = pmu_res_depend_tab_4325a0;
1698 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
1699 + break;
1700 + case 0x4328:
1701 + min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
1702 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
1703 + (1 << SSB_PMURES_4328_XTAL_EN);
1704 + /* The PLL may turn on, if it decides so. */
1705 + max_msk = 0xFFFFF;
1706 + updown_tab = pmu_res_updown_tab_4328a0;
1707 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
1708 + depend_tab = pmu_res_depend_tab_4328a0;
1709 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
1710 + break;
1711 + case 0x5354:
1712 + /* The PLL may turn on, if it decides so. */
1713 + max_msk = 0xFFFFF;
1714 + break;
1715 + default:
1716 + ssb_printk(KERN_ERR PFX
1717 + "ERROR: PMU resource config unknown for device %04X\n",
1718 + bus->chip_id);
1719 + }
1720 +
1721 + if (updown_tab) {
1722 + for (i = 0; i < updown_tab_size; i++) {
1723 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
1724 + updown_tab[i].resource);
1725 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
1726 + updown_tab[i].updown);
1727 + }
1728 + }
1729 + if (depend_tab) {
1730 + for (i = 0; i < depend_tab_size; i++) {
1731 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
1732 + depend_tab[i].resource);
1733 + switch (depend_tab[i].task) {
1734 + case PMU_RES_DEP_SET:
1735 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
1736 + depend_tab[i].depend);
1737 + break;
1738 + case PMU_RES_DEP_ADD:
1739 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
1740 + depend_tab[i].depend);
1741 + break;
1742 + case PMU_RES_DEP_REMOVE:
1743 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
1744 + ~(depend_tab[i].depend));
1745 + break;
1746 + default:
1747 + SSB_WARN_ON(1);
1748 + }
1749 + }
1750 + }
1751 +
1752 + /* Set the resource masks. */
1753 + if (min_msk)
1754 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
1755 + if (max_msk)
1756 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
1757 +}
1758 +
1759 +void ssb_pmu_init(struct ssb_chipcommon *cc)
1760 +{
1761 + struct ssb_bus *bus = cc->dev->bus;
1762 + u32 pmucap;
1763 +
1764 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
1765 + return;
1766 +
1767 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
1768 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
1769 +
1770 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
1771 + cc->pmu.rev, pmucap);
1772 +
1773 + if (cc->pmu.rev >= 1) {
1774 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
1775 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
1776 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
1777 + } else {
1778 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
1779 + SSB_CHIPCO_PMU_CTL_NOILPONW);
1780 + }
1781 + }
1782 + ssb_pmu_pll_init(cc);
1783 + ssb_pmu_resources_init(cc);
1784 +}
1785 +
1786 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
1787 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
1788 +{
1789 + struct ssb_bus *bus = cc->dev->bus;
1790 + u32 addr, shift, mask;
1791 +
1792 + switch (bus->chip_id) {
1793 + case 0x4328:
1794 + case 0x5354:
1795 + switch (id) {
1796 + case LDO_VOLT1:
1797 + addr = 2;
1798 + shift = 25;
1799 + mask = 0xF;
1800 + break;
1801 + case LDO_VOLT2:
1802 + addr = 3;
1803 + shift = 1;
1804 + mask = 0xF;
1805 + break;
1806 + case LDO_VOLT3:
1807 + addr = 3;
1808 + shift = 9;
1809 + mask = 0xF;
1810 + break;
1811 + case LDO_PAREF:
1812 + addr = 3;
1813 + shift = 17;
1814 + mask = 0x3F;
1815 + break;
1816 + default:
1817 + SSB_WARN_ON(1);
1818 + return;
1819 + }
1820 + break;
1821 + case 0x4312:
1822 + if (SSB_WARN_ON(id != LDO_PAREF))
1823 + return;
1824 + addr = 0;
1825 + shift = 21;
1826 + mask = 0x3F;
1827 + break;
1828 + default:
1829 + return;
1830 + }
1831 +
1832 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
1833 + (voltage & mask) << shift);
1834 +}
1835 +
1836 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
1837 +{
1838 + struct ssb_bus *bus = cc->dev->bus;
1839 + int ldo;
1840 +
1841 + switch (bus->chip_id) {
1842 + case 0x4312:
1843 + ldo = SSB_PMURES_4312_PA_REF_LDO;
1844 + break;
1845 + case 0x4328:
1846 + ldo = SSB_PMURES_4328_PA_REF_LDO;
1847 + break;
1848 + case 0x5354:
1849 + ldo = SSB_PMURES_5354_PA_REF_LDO;
1850 + break;
1851 + default:
1852 + return;
1853 + }
1854 +
1855 + if (on)
1856 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
1857 + else
1858 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
1859 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
1860 +}
1861 +
1862 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
1863 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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