2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * 2009 Florian Fainelli <florian@openwrt.org>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/cpu.h>
13 #include <bcm63xx_cpu.h>
14 #include <bcm63xx_regs.h>
15 #include <bcm63xx_io.h>
16 #include <bcm63xx_irq.h>
18 const unsigned long *bcm63xx_regs_base
;
19 EXPORT_SYMBOL(bcm63xx_regs_base
);
21 const int *bcm63xx_irqs
;
22 EXPORT_SYMBOL(bcm63xx_irqs
);
24 const unsigned long *bcm63xx_regs_spi
;
25 EXPORT_SYMBOL(bcm63xx_regs_spi
);
27 static u16 bcm63xx_cpu_id
;
28 static u16 bcm63xx_cpu_rev
;
29 static unsigned int bcm63xx_cpu_freq
;
30 static unsigned int bcm63xx_memory_size
;
33 * 6338 register sets and irqs
36 static const unsigned long bcm96338_regs_base
[] = {
37 [RSET_PERF
] = BCM_6338_PERF_BASE
,
38 [RSET_TIMER
] = BCM_6338_TIMER_BASE
,
39 [RSET_WDT
] = BCM_6338_WDT_BASE
,
40 [RSET_UART0
] = BCM_6338_UART0_BASE
,
41 [RSET_GPIO
] = BCM_6338_GPIO_BASE
,
42 [RSET_SPI
] = BCM_6338_SPI_BASE
,
43 [RSET_MEMC
] = BCM_6338_MEMC_BASE
,
46 static const int bcm96338_irqs
[] = {
47 [IRQ_TIMER
] = BCM_6338_TIMER_IRQ
,
48 [IRQ_UART0
] = BCM_6338_UART0_IRQ
,
49 [IRQ_DSL
] = BCM_6338_DSL_IRQ
,
50 [IRQ_ENET0
] = BCM_6338_ENET0_IRQ
,
51 [IRQ_ENET_PHY
] = BCM_6338_ENET_PHY_IRQ
,
52 [IRQ_ENET0_RXDMA
] = BCM_6338_ENET0_RXDMA_IRQ
,
53 [IRQ_ENET0_TXDMA
] = BCM_6338_ENET0_TXDMA_IRQ
,
56 static const unsigned long bcm96338_regs_spi
[] = {
57 [SPI_CMD
] = SPI_BCM_6338_SPI_CMD
,
58 [SPI_INT_STATUS
] = SPI_BCM_6338_SPI_INT_STATUS
,
59 [SPI_INT_MASK_ST
] = SPI_BCM_6338_SPI_MASK_INT_ST
,
60 [SPI_INT_MASK
] = SPI_BCM_6338_SPI_INT_MASK
,
61 [SPI_ST
] = SPI_BCM_6338_SPI_ST
,
62 [SPI_CLK_CFG
] = SPI_BCM_6338_SPI_CLK_CFG
,
63 [SPI_FILL_BYTE
] = SPI_BCM_6338_SPI_FILL_BYTE
,
64 [SPI_MSG_TAIL
] = SPI_BCM_6338_SPI_MSG_TAIL
,
65 [SPI_RX_TAIL
] = SPI_BCM_6338_SPI_RX_TAIL
,
66 [SPI_MSG_CTL
] = SPI_BCM_6338_SPI_MSG_CTL
,
67 [SPI_MSG_DATA
] = SPI_BCM_6338_SPI_MSG_DATA
,
68 [SPI_RX_DATA
] = SPI_BCM_6338_SPI_RX_DATA
,
72 * 6348 register sets and irqs
74 static const unsigned long bcm96348_regs_base
[] = {
75 [RSET_DSL_LMEM
] = BCM_6348_DSL_LMEM_BASE
,
76 [RSET_PERF
] = BCM_6348_PERF_BASE
,
77 [RSET_TIMER
] = BCM_6348_TIMER_BASE
,
78 [RSET_WDT
] = BCM_6348_WDT_BASE
,
79 [RSET_UART0
] = BCM_6348_UART0_BASE
,
80 [RSET_GPIO
] = BCM_6348_GPIO_BASE
,
81 [RSET_SPI
] = BCM_6348_SPI_BASE
,
82 [RSET_OHCI0
] = BCM_6348_OHCI0_BASE
,
83 [RSET_OHCI_PRIV
] = BCM_6348_OHCI_PRIV_BASE
,
84 [RSET_USBH_PRIV
] = BCM_6348_USBH_PRIV_BASE
,
85 [RSET_MPI
] = BCM_6348_MPI_BASE
,
86 [RSET_PCMCIA
] = BCM_6348_PCMCIA_BASE
,
87 [RSET_SDRAM
] = BCM_6348_SDRAM_BASE
,
88 [RSET_DSL
] = BCM_6348_DSL_BASE
,
89 [RSET_ENET0
] = BCM_6348_ENET0_BASE
,
90 [RSET_ENET1
] = BCM_6348_ENET1_BASE
,
91 [RSET_ENETDMA
] = BCM_6348_ENETDMA_BASE
,
92 [RSET_MEMC
] = BCM_6348_MEMC_BASE
,
93 [RSET_DDR
] = BCM_6348_DDR_BASE
,
96 static const int bcm96348_irqs
[] = {
97 [IRQ_TIMER
] = BCM_6348_TIMER_IRQ
,
98 [IRQ_UART0
] = BCM_6348_UART0_IRQ
,
99 [IRQ_DSL
] = BCM_6348_DSL_IRQ
,
100 [IRQ_ENET0
] = BCM_6348_ENET0_IRQ
,
101 [IRQ_ENET1
] = BCM_6348_ENET1_IRQ
,
102 [IRQ_ENET_PHY
] = BCM_6348_ENET_PHY_IRQ
,
103 [IRQ_OHCI0
] = BCM_6348_OHCI0_IRQ
,
104 [IRQ_PCMCIA
] = BCM_6348_PCMCIA_IRQ
,
105 [IRQ_ENET0_RXDMA
] = BCM_6348_ENET0_RXDMA_IRQ
,
106 [IRQ_ENET0_TXDMA
] = BCM_6348_ENET0_TXDMA_IRQ
,
107 [IRQ_ENET1_RXDMA
] = BCM_6348_ENET1_RXDMA_IRQ
,
108 [IRQ_ENET1_TXDMA
] = BCM_6348_ENET1_TXDMA_IRQ
,
109 [IRQ_PCI
] = BCM_6348_PCI_IRQ
,
112 static const unsigned long bcm96348_regs_spi
[] = {
113 [SPI_CMD
] = SPI_BCM_6348_SPI_CMD
,
114 [SPI_INT_STATUS
] = SPI_BCM_6348_SPI_INT_STATUS
,
115 [SPI_INT_MASK_ST
] = SPI_BCM_6348_SPI_MASK_INT_ST
,
116 [SPI_INT_MASK
] = SPI_BCM_6348_SPI_INT_MASK
,
117 [SPI_ST
] = SPI_BCM_6348_SPI_ST
,
118 [SPI_CLK_CFG
] = SPI_BCM_6348_SPI_CLK_CFG
,
119 [SPI_FILL_BYTE
] = SPI_BCM_6348_SPI_FILL_BYTE
,
120 [SPI_MSG_TAIL
] = SPI_BCM_6348_SPI_MSG_TAIL
,
121 [SPI_RX_TAIL
] = SPI_BCM_6348_SPI_RX_TAIL
,
122 [SPI_MSG_CTL
] = SPI_BCM_6348_SPI_MSG_CTL
,
123 [SPI_MSG_DATA
] = SPI_BCM_6348_SPI_MSG_DATA
,
124 [SPI_RX_DATA
] = SPI_BCM_6348_SPI_RX_DATA
,
128 * 6358 register sets and irqs
130 static const unsigned long bcm96358_regs_base
[] = {
131 [RSET_DSL_LMEM
] = BCM_6358_DSL_LMEM_BASE
,
132 [RSET_PERF
] = BCM_6358_PERF_BASE
,
133 [RSET_TIMER
] = BCM_6358_TIMER_BASE
,
134 [RSET_WDT
] = BCM_6358_WDT_BASE
,
135 [RSET_UART0
] = BCM_6358_UART0_BASE
,
136 [RSET_GPIO
] = BCM_6358_GPIO_BASE
,
137 [RSET_SPI
] = BCM_6358_SPI_BASE
,
138 [RSET_OHCI0
] = BCM_6358_OHCI0_BASE
,
139 [RSET_EHCI0
] = BCM_6358_EHCI0_BASE
,
140 [RSET_OHCI_PRIV
] = BCM_6358_OHCI_PRIV_BASE
,
141 [RSET_USBH_PRIV
] = BCM_6358_USBH_PRIV_BASE
,
142 [RSET_MPI
] = BCM_6358_MPI_BASE
,
143 [RSET_PCMCIA
] = BCM_6358_PCMCIA_BASE
,
144 [RSET_SDRAM
] = BCM_6358_SDRAM_BASE
,
145 [RSET_DSL
] = BCM_6358_DSL_BASE
,
146 [RSET_ENET0
] = BCM_6358_ENET0_BASE
,
147 [RSET_ENET1
] = BCM_6358_ENET1_BASE
,
148 [RSET_ENETDMA
] = BCM_6358_ENETDMA_BASE
,
149 [RSET_MEMC
] = BCM_6358_MEMC_BASE
,
150 [RSET_DDR
] = BCM_6358_DDR_BASE
,
153 static const int bcm96358_irqs
[] = {
154 [IRQ_TIMER
] = BCM_6358_TIMER_IRQ
,
155 [IRQ_UART0
] = BCM_6358_UART0_IRQ
,
156 [IRQ_DSL
] = BCM_6358_DSL_IRQ
,
157 [IRQ_ENET0
] = BCM_6358_ENET0_IRQ
,
158 [IRQ_ENET1
] = BCM_6358_ENET1_IRQ
,
159 [IRQ_ENET_PHY
] = BCM_6358_ENET_PHY_IRQ
,
160 [IRQ_OHCI0
] = BCM_6358_OHCI0_IRQ
,
161 [IRQ_EHCI0
] = BCM_6358_EHCI0_IRQ
,
162 [IRQ_PCMCIA
] = BCM_6358_PCMCIA_IRQ
,
163 [IRQ_ENET0_RXDMA
] = BCM_6358_ENET0_RXDMA_IRQ
,
164 [IRQ_ENET0_TXDMA
] = BCM_6358_ENET0_TXDMA_IRQ
,
165 [IRQ_ENET1_RXDMA
] = BCM_6358_ENET1_RXDMA_IRQ
,
166 [IRQ_ENET1_TXDMA
] = BCM_6358_ENET1_TXDMA_IRQ
,
167 [IRQ_PCI
] = BCM_6358_PCI_IRQ
,
170 static const unsigned long bcm96358_regs_spi
[] = {
171 [SPI_CMD
] = SPI_BCM_6358_SPI_CMD
,
172 [SPI_INT_STATUS
] = SPI_BCM_6358_SPI_INT_STATUS
,
173 [SPI_INT_MASK_ST
] = SPI_BCM_6358_SPI_MASK_INT_ST
,
174 [SPI_INT_MASK
] = SPI_BCM_6358_SPI_INT_MASK
,
175 [SPI_ST
] = SPI_BCM_6358_SPI_STATUS
,
176 [SPI_CLK_CFG
] = SPI_BCM_6358_SPI_CLK_CFG
,
177 [SPI_FILL_BYTE
] = SPI_BCM_6358_SPI_FILL_BYTE
,
178 [SPI_MSG_TAIL
] = SPI_BCM_6358_SPI_MSG_TAIL
,
179 [SPI_RX_TAIL
] = SPI_BCM_6358_SPI_RX_TAIL
,
180 [SPI_MSG_CTL
] = SPI_BCM_6358_MSG_CTL
,
181 [SPI_MSG_DATA
] = SPI_BCM_6358_SPI_MSG_DATA
,
182 [SPI_RX_DATA
] = SPI_BCM_6358_SPI_RX_DATA
,
185 u16
__bcm63xx_get_cpu_id(void)
187 return bcm63xx_cpu_id
;
190 EXPORT_SYMBOL(__bcm63xx_get_cpu_id
);
192 u16
bcm63xx_get_cpu_rev(void)
194 return bcm63xx_cpu_rev
;
197 EXPORT_SYMBOL(bcm63xx_get_cpu_rev
);
199 unsigned int bcm63xx_get_cpu_freq(void)
201 return bcm63xx_cpu_freq
;
204 unsigned int bcm63xx_get_memory_size(void)
206 return bcm63xx_memory_size
;
209 static unsigned int detect_cpu_clock(void)
211 unsigned int tmp
, n1
= 0, n2
= 0, m1
= 0;
213 if (BCMCPU_IS_6338()) {
218 * frequency depends on PLL configuration:
220 if (BCMCPU_IS_6348()) {
221 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
222 tmp
= bcm_perf_readl(PERF_MIPSPLLCTL_REG
);
223 n1
= (tmp
& MIPSPLLCTL_N1_MASK
) >> MIPSPLLCTL_N1_SHIFT
;
224 n2
= (tmp
& MIPSPLLCTL_N2_MASK
) >> MIPSPLLCTL_N2_SHIFT
;
225 m1
= (tmp
& MIPSPLLCTL_M1CPU_MASK
) >> MIPSPLLCTL_M1CPU_SHIFT
;
231 if (BCMCPU_IS_6358()) {
232 /* 16MHz * N1 * N2 / M1_CPU */
233 tmp
= bcm_ddr_readl(DDR_DMIPSPLLCFG_REG
);
234 n1
= (tmp
& DMIPSPLLCFG_N1_MASK
) >> DMIPSPLLCFG_N1_SHIFT
;
235 n2
= (tmp
& DMIPSPLLCFG_N2_MASK
) >> DMIPSPLLCFG_N2_SHIFT
;
236 m1
= (tmp
& DMIPSPLLCFG_M1_MASK
) >> DMIPSPLLCFG_M1_SHIFT
;
239 return (16 * 1000000 * n1
* n2
) / m1
;
243 * attempt to detect the amount of memory installed
245 static unsigned int detect_memory_size(void)
247 unsigned int cols
= 0, rows
= 0, is_32bits
= 0, banks
= 0;
250 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
251 val
= bcm_sdram_readl(SDRAM_CFG_REG
);
252 rows
= (val
& SDRAM_CFG_ROW_MASK
) >> SDRAM_CFG_ROW_SHIFT
;
253 cols
= (val
& SDRAM_CFG_COL_MASK
) >> SDRAM_CFG_COL_SHIFT
;
254 is_32bits
= (val
& SDRAM_CFG_32B_MASK
) ? 1 : 0;
255 banks
= (val
& SDRAM_CFG_BANK_MASK
) ? 2 : 1;
258 if (BCMCPU_IS_6358()) {
259 val
= bcm_memc_readl(MEMC_CFG_REG
);
260 rows
= (val
& MEMC_CFG_ROW_MASK
) >> MEMC_CFG_ROW_SHIFT
;
261 cols
= (val
& MEMC_CFG_COL_MASK
) >> MEMC_CFG_COL_SHIFT
;
262 is_32bits
= (val
& MEMC_CFG_32B_MASK
) ? 0 : 1;
266 /* 0 => 11 address bits ... 2 => 13 address bits */
269 /* 0 => 8 address bits ... 2 => 10 address bits */
272 return 1 << (cols
+ rows
+ (is_32bits
+ 1) + banks
);
275 void __init
bcm63xx_cpu_init(void)
277 unsigned int tmp
, expected_cpu_id
;
278 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
280 /* soc registers location depends on cpu type */
283 switch (c
->cputype
) {
285 expected_cpu_id
= BCM6338_CPU_ID
;
286 bcm63xx_regs_base
= bcm96338_regs_base
;
287 bcm63xx_irqs
= bcm96338_irqs
;
288 bcm63xx_regs_spi
= bcm96338_regs_spi
;
291 expected_cpu_id
= BCM6348_CPU_ID
;
292 bcm63xx_regs_base
= bcm96348_regs_base
;
293 bcm63xx_irqs
= bcm96348_irqs
;
294 bcm63xx_regs_spi
= bcm96348_regs_spi
;
297 expected_cpu_id
= BCM6358_CPU_ID
;
298 bcm63xx_regs_base
= bcm96358_regs_base
;
299 bcm63xx_irqs
= bcm96358_irqs
;
300 bcm63xx_regs_spi
= bcm96358_regs_spi
;
304 /* really early to panic, but delaying panic would not help
305 * since we will never get any working console */
306 if (!expected_cpu_id
)
307 panic("unsupported Broadcom CPU");
310 * bcm63xx_regs_base is set, we can access soc registers
313 /* double check CPU type */
314 tmp
= bcm_perf_readl(PERF_REV_REG
);
315 bcm63xx_cpu_id
= (tmp
& REV_CHIPID_MASK
) >> REV_CHIPID_SHIFT
;
316 bcm63xx_cpu_rev
= (tmp
& REV_REVID_MASK
) >> REV_REVID_SHIFT
;
318 if (bcm63xx_cpu_id
!= expected_cpu_id
)
319 panic("bcm63xx CPU id mismatch");
321 bcm63xx_cpu_freq
= detect_cpu_clock();
322 bcm63xx_memory_size
= detect_memory_size();
324 printk(KERN_INFO
"Detected Broadcom 0x%04x CPU revision %02x\n",
325 bcm63xx_cpu_id
, bcm63xx_cpu_rev
);
326 printk(KERN_INFO
"CPU frequency is %u Hz\n",
328 printk(KERN_INFO
"%uMB of RAM installed\n",
329 bcm63xx_memory_size
>> 20);