projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
upgrade AVR32 to 2.6.22.1
[openwrt.git] / target / linux / avr32-2.6 / patches / 100-git_sync.patch
1 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atngw100/setup.c linux-avr32.git/arch/avr32/boards/atngw100/setup.c
2 --- linux-2.6.22.1/arch/avr32/boards/atngw100/setup.c 2007-07-10 20:56:30.000000000 +0200
3 +++ linux-avr32.git/arch/avr32/boards/atngw100/setup.c 2007-07-12 13:59:49.000000000 +0200
4 @@ -13,6 +13,7 @@
5 #include <linux/linkage.h>
6 #include <linux/platform_device.h>
7 #include <linux/types.h>
8 +#include <linux/leds.h>
9 #include <linux/spi/spi.h>
10
11 #include <asm/io.h>
12 @@ -21,6 +22,7 @@
13 #include <asm/arch/at32ap7000.h>
14 #include <asm/arch/board.h>
15 #include <asm/arch/init.h>
16 +#include <asm/arch/portmux.h>
17
18 /* Initialized by bootloader-specific startup code. */
19 struct tag *bootloader_tags __initdata;
20 @@ -39,6 +41,11 @@
21 },
22 };
23
24 +static struct mci_platform_data __initdata mci0_data = {
25 + .detect_pin = GPIO_PIN_PC(25),
26 + .wp_pin = GPIO_PIN_PE(0),
27 +};
28 +
29 /*
30 * The next two functions should go away as the boot loader is
31 * supposed to initialize the macb address registers with a valid
32 @@ -100,8 +107,31 @@
33 at32_setup_serial_console(0);
34 }
35
36 +static const struct gpio_led ngw_leds[] = {
37 + { .name = "sys", .gpio = GPIO_PIN_PA(16), .active_low = 1,
38 + .default_trigger = "heartbeat",
39 + },
40 + { .name = "a", .gpio = GPIO_PIN_PA(19), .active_low = 1, },
41 + { .name = "b", .gpio = GPIO_PIN_PE(19), .active_low = 1, },
42 +};
43 +
44 +static const struct gpio_led_platform_data ngw_led_data = {
45 + .num_leds = ARRAY_SIZE(ngw_leds),
46 + .leds = (void *) ngw_leds,
47 +};
48 +
49 +static struct platform_device ngw_gpio_leds = {
50 + .name = "leds-gpio",
51 + .id = -1,
52 + .dev = {
53 + .platform_data = (void *) &ngw_led_data,
54 + }
55 +};
56 +
57 static int __init atngw100_init(void)
58 {
59 + unsigned i;
60 +
61 /*
62 * ATNGW100 uses 16-bit SDRAM interface, so we don't need to
63 * reserve any pins for it.
64 @@ -115,6 +145,14 @@
65 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
66
67 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
68 + at32_add_device_mci(0, &mci0_data);
69 + at32_add_device_usba(0, NULL);
70 +
71 + for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
72 + at32_select_gpio(ngw_leds[i].gpio,
73 + AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
74 + }
75 + platform_device_register(&ngw_gpio_leds);
76
77 return 0;
78 }
79 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atstk1000/atstk1002.c linux-avr32.git/arch/avr32/boards/atstk1000/atstk1002.c
80 --- linux-2.6.22.1/arch/avr32/boards/atstk1000/atstk1002.c 2007-07-10 20:56:30.000000000 +0200
81 +++ linux-avr32.git/arch/avr32/boards/atstk1000/atstk1002.c 2007-07-12 13:59:49.000000000 +0200
82 @@ -11,6 +11,7 @@
83 #include <linux/etherdevice.h>
84 #include <linux/init.h>
85 #include <linux/kernel.h>
86 +#include <linux/leds.h>
87 #include <linux/platform_device.h>
88 #include <linux/string.h>
89 #include <linux/types.h>
90 @@ -27,7 +28,6 @@
91
92 #include "atstk1000.h"
93
94 -#define SW2_DEFAULT /* MMCI and UART_A available */
95
96 struct eth_addr {
97 u8 addr[6];
98 @@ -36,6 +36,7 @@
99 static struct eth_addr __initdata hw_addr[2];
100 static struct eth_platform_data __initdata eth_data[2];
101
102 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
103 static struct spi_board_info spi0_board_info[] __initdata = {
104 {
105 /* QVGA display */
106 @@ -45,6 +46,18 @@
107 .mode = SPI_MODE_3,
108 },
109 };
110 +#endif
111 +
112 +#ifdef CONFIG_BOARD_ATSTK1002_SPI1
113 +static struct spi_board_info spi1_board_info[] __initdata = { {
114 + /* patch in custom entries here */
115 +} };
116 +#endif
117 +
118 +static struct mci_platform_data __initdata mci0_data = {
119 + .detect_pin = GPIO_PIN_NONE,
120 + .wp_pin = GPIO_PIN_NONE,
121 +};
122
123 /*
124 * The next two functions should go away as the boot loader is
125 @@ -101,12 +114,71 @@
126 clk_put(pclk);
127 }
128
129 -void __init setup_board(void)
130 +#ifdef CONFIG_BOARD_ATSTK1002_J2_LED
131 +
132 +static struct gpio_led stk_j2_led[] = {
133 +#ifdef CONFIG_BOARD_ATSTK1002_J2_LED8
134 +#define LEDSTRING "J2 jumpered to LED8"
135 + { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
136 + { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
137 + { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
138 + { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
139 + { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
140 + { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
141 + { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
142 + { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
143 + .default_trigger = "heartbeat", },
144 +#else /* RGB */
145 +#define LEDSTRING "J2 jumpered to RGB LEDs"
146 + { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
147 + { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
148 + { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
149 +
150 + { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
151 + .default_trigger = "heartbeat", },
152 + { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
153 + { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
154 + .default_trigger = "heartbeat", },
155 + /* PB16, PB30 unused */
156 +#endif
157 +};
158 +
159 +static struct gpio_led_platform_data stk_j2_led_data = {
160 + .num_leds = ARRAY_SIZE(stk_j2_led),
161 + .leds = stk_j2_led,
162 +};
163 +
164 +static struct platform_device stk_j2_led_dev = {
165 + .name = "leds-gpio",
166 + .id = 2, /* gpio block J2 */
167 + .dev = {
168 + .platform_data = &stk_j2_led_data,
169 + },
170 +};
171 +
172 +static void setup_j2_leds(void)
173 {
174 -#ifdef SW2_DEFAULT
175 - at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
176 + unsigned i;
177 +
178 + for (i = 0; i < ARRAY_SIZE(stk_j2_led); i++)
179 + at32_select_gpio(stk_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
180 +
181 + printk("STK1002: " LEDSTRING "\n");
182 + platform_device_register(&stk_j2_led_dev);
183 +}
184 +
185 #else
186 +static void setup_j2_leds(void)
187 +{
188 +}
189 +#endif
190 +
191 +void __init setup_board(void)
192 +{
193 +#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
194 at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
195 +#else
196 + at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
197 #endif
198 /* USART 2/unused: expansion connector */
199 at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
200 @@ -140,18 +212,40 @@
201
202 at32_add_system_devices();
203
204 -#ifdef SW2_DEFAULT
205 - at32_add_device_usart(0);
206 -#else
207 +#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
208 at32_add_device_usart(1);
209 +#else
210 + at32_add_device_usart(0);
211 #endif
212 at32_add_device_usart(2);
213
214 +#ifndef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
215 set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
216 -
217 - at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
218 +#endif
219 +#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
220 + set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
221 +#else
222 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
223 fbmem_start, fbmem_size);
224 +#endif
225 +
226 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
227 + at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
228 +#endif
229 +#ifdef CONFIG_BOARD_ATSTK1002_SPI1
230 + at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
231 +#endif
232 + at32_add_device_twi(0);
233 +#ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
234 + at32_add_device_mci(0, &mci0_data);
235 +#endif
236 + at32_add_device_usba(0, NULL);
237 + at32_add_device_abdac(0);
238 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
239 + at32_add_device_ssc(0, ATMEL_SSC_TX);
240 +#endif
241 +
242 + setup_j2_leds();
243
244 return 0;
245 }
246 diff -x .git -Nur linux-2.6.22.1/arch/avr32/boards/atstk1000/Kconfig linux-avr32.git/arch/avr32/boards/atstk1000/Kconfig
247 --- linux-2.6.22.1/arch/avr32/boards/atstk1000/Kconfig 1970-01-01 01:00:00.000000000 +0100
248 +++ linux-avr32.git/arch/avr32/boards/atstk1000/Kconfig 2007-07-12 13:59:49.000000000 +0200
249 @@ -0,0 +1,79 @@
250 +# STK1000 customization
251 +
252 +if BOARD_ATSTK1002
253 +
254 +config BOARD_ATSTK1002_CUSTOM
255 + bool "Non-default STK-1002 jumper settings"
256 + help
257 + You will normally leave the jumpers on the CPU card at their
258 + default settings. If you need to use certain peripherals,
259 + you will need to change some of those jumpers.
260 +
261 +if BOARD_ATSTK1002_CUSTOM
262 +
263 +config BOARD_ATSTK1002_SW1_CUSTOM
264 + bool "SW1: use SSC1 (not SPI0)"
265 + help
266 + This also prevents using the external DAC as an audio interface,
267 + and means you can't initialize the on-board QVGA display.
268 +
269 +config BOARD_ATSTK1002_SW2_CUSTOM
270 + bool "SW2: use IRDA or TIMER0 (not UART-A, MMC/SD, and PS2-A)"
271 + help
272 + If you change this you'll want an updated boot loader putting
273 + the console on UART-C not UART-A.
274 +
275 +config BOARD_ATSTK1002_SW3_CUSTOM
276 + bool "SW3: use TIMER1 (not SSC0 and GCLK)"
277 + help
278 + This also prevents using the external DAC as an audio interface.
279 +
280 +config BOARD_ATSTK1002_SW4_CUSTOM
281 + bool "SW4: use ISI/Camera (not GPIOs, SPI1, and PS2-B)"
282 + help
283 + To use the camera interface you'll need a custom card (on the
284 + PCI-format connector) connect a video sensor.
285 +
286 +config BOARD_ATSTK1002_SW5_CUSTOM
287 + bool "SW5: use MACB1 (not LCDC)"
288 +
289 +config BOARD_ATSTK1002_SW6_CUSTOM
290 + bool "SW6: more GPIOs (not MACB0)"
291 +
292 +endif # custom
293 +
294 +config BOARD_ATSTK1002_SPI1
295 + bool "Configure SPI1 controller"
296 + depends on !BOARD_ATSTK1002_SW4_CUSTOM
297 + help
298 + All the signals for the second SPI controller are available on
299 + GPIO lines and accessed through the J1 jumper block. Say "y"
300 + here to configure that SPI controller.
301 +
302 +config BOARD_ATSTK1002_J2_LED
303 + bool
304 + default BOARD_ATSTK1002_J2_LED8 || BOARD_ATSTK1002_J2_RGB
305 +
306 +choice
307 + prompt "LEDs connected to J2:"
308 + depends on LEDS_GPIO && !BOARD_ATSTK1002_SW4_CUSTOM
309 + optional
310 + help
311 + Select this if you have jumpered the J2 jumper block to the
312 + LED0..LED7 amber leds, or to the RGB leds, using a ten-pin
313 + IDC cable. A default "heartbeat" trigger is provided, but
314 + you can of course override this.
315 +
316 +config BOARD_ATSTK1002_J2_LED8
317 + bool "LED0..LED7"
318 + help
319 + Select this if J2 is jumpered to LED0..LED7 amber leds.
320 +
321 +config BOARD_ATSTK1002_J2_RGB
322 + bool "RGB leds"
323 + help
324 + Select this if J2 is jumpered to the RGB leds.
325 +
326 +endchoice
327 +
328 +endif # stk 1002
329 diff -x .git -Nur linux-2.6.22.1/arch/avr32/configs/atngw100_defconfig linux-avr32.git/arch/avr32/configs/atngw100_defconfig
330 --- linux-2.6.22.1/arch/avr32/configs/atngw100_defconfig 2007-07-10 20:56:30.000000000 +0200
331 +++ linux-avr32.git/arch/avr32/configs/atngw100_defconfig 2007-07-12 13:59:49.000000000 +0200
332 @@ -712,7 +712,21 @@
333 #
334 # LED devices
335 #
336 -# CONFIG_NEW_LEDS is not set
337 +CONFIG_NEW_LEDS=y
338 +CONFIG_LEDS_CLASS=y
339 +
340 +#
341 +# LED drivers
342 +#
343 +CONFIG_LEDS_GPIO=y
344 +
345 +#
346 +# LED Triggers
347 +#
348 +CONFIG_LEDS_TRIGGERS=y
349 +CONFIG_LEDS_TRIGGER_TIMER=y
350 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
351 +
352
353 #
354 # LED drivers
355 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/dw-dmac.c linux-avr32.git/arch/avr32/drivers/dw-dmac.c
356 --- linux-2.6.22.1/arch/avr32/drivers/dw-dmac.c 1970-01-01 01:00:00.000000000 +0100
357 +++ linux-avr32.git/arch/avr32/drivers/dw-dmac.c 2007-06-06 11:33:46.000000000 +0200
358 @@ -0,0 +1,761 @@
359 +/*
360 + * Driver for the Synopsys DesignWare DMA Controller
361 + *
362 + * Copyright (C) 2005-2006 Atmel Corporation
363 + *
364 + * This program is free software; you can redistribute it and/or modify
365 + * it under the terms of the GNU General Public License version 2 as
366 + * published by the Free Software Foundation.
367 + */
368 +#include <linux/clk.h>
369 +#include <linux/device.h>
370 +#include <linux/dma-mapping.h>
371 +#include <linux/dmapool.h>
372 +#include <linux/init.h>
373 +#include <linux/interrupt.h>
374 +#include <linux/module.h>
375 +#include <linux/platform_device.h>
376 +
377 +#include <asm/dma-controller.h>
378 +#include <asm/io.h>
379 +
380 +#include "dw-dmac.h"
381 +
382 +#define DMAC_NR_CHANNELS 3
383 +#define DMAC_MAX_BLOCKSIZE 4095
384 +
385 +enum {
386 + CH_STATE_FREE = 0,
387 + CH_STATE_ALLOCATED,
388 + CH_STATE_BUSY,
389 +};
390 +
391 +struct dw_dma_lli {
392 + dma_addr_t sar;
393 + dma_addr_t dar;
394 + dma_addr_t llp;
395 + u32 ctllo;
396 + u32 ctlhi;
397 + u32 sstat;
398 + u32 dstat;
399 +};
400 +
401 +struct dw_dma_block {
402 + struct dw_dma_lli *lli_vaddr;
403 + dma_addr_t lli_dma_addr;
404 +};
405 +
406 +struct dw_dma_channel {
407 + unsigned int state;
408 + int is_cyclic;
409 + struct dma_request_sg *req_sg;
410 + struct dma_request_cyclic *req_cyclic;
411 + unsigned int nr_blocks;
412 + int direction;
413 + struct dw_dma_block *block;
414 +};
415 +
416 +struct dw_dma_controller {
417 + spinlock_t lock;
418 + void * __iomem regs;
419 + struct dma_pool *lli_pool;
420 + struct clk *hclk;
421 + struct dma_controller dma;
422 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
423 +};
424 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
425 +
426 +#define dmac_writel_hi(dmac, reg, value) \
427 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
428 +#define dmac_readl_hi(dmac, reg) \
429 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
430 +#define dmac_writel_lo(dmac, reg, value) \
431 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
432 +#define dmac_readl_lo(dmac, reg) \
433 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
434 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
435 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
436 + + DW_DMAC_CHAN_##reg + 4))
437 +#define dmac_chan_readl_hi(dmac, chan, reg) \
438 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
439 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
440 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
441 +#define dmac_chan_readl_lo(dmac, chan, reg) \
442 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
443 +#define set_channel_bit(dmac, reg, chan) \
444 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
445 +#define clear_channel_bit(dmac, reg, chan) \
446 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
447 +
448 +static int dmac_alloc_channel(struct dma_controller *_dmac)
449 +{
450 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
451 + struct dw_dma_channel *chan;
452 + unsigned long flags;
453 + int i;
454 +
455 + spin_lock_irqsave(&dmac->lock, flags);
456 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
457 + if (dmac->channel[i].state == CH_STATE_FREE)
458 + break;
459 +
460 + if (i < DMAC_NR_CHANNELS) {
461 + chan = &dmac->channel[i];
462 + chan->state = CH_STATE_ALLOCATED;
463 + } else {
464 + i = -EBUSY;
465 + }
466 +
467 + spin_unlock_irqrestore(&dmac->lock, flags);
468 +
469 + return i;
470 +}
471 +
472 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
473 +{
474 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
475 +
476 + BUG_ON(channel >= DMAC_NR_CHANNELS
477 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
478 +
479 + dmac->channel[channel].state = CH_STATE_FREE;
480 +}
481 +
482 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
483 + unsigned int nr_blocks)
484 +{
485 + struct dw_dma_block *block;
486 + void *p;
487 + unsigned int i;
488 +
489 + block = kmalloc(nr_blocks * sizeof(*block),
490 + GFP_KERNEL);
491 + if (unlikely(!block))
492 + return NULL;
493 +
494 + for (i = 0; i < nr_blocks; i++) {
495 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
496 + &block[i].lli_dma_addr);
497 + block[i].lli_vaddr = p;
498 + if (unlikely(!p))
499 + goto fail;
500 + }
501 +
502 + return block;
503 +
504 +fail:
505 + for (i = 0; i < nr_blocks; i++) {
506 + if (!block[i].lli_vaddr)
507 + break;
508 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
509 + block[i].lli_dma_addr);
510 + }
511 + kfree(block);
512 + return NULL;
513 +}
514 +
515 +static void cleanup_channel(struct dw_dma_controller *dmac,
516 + struct dw_dma_channel *chan)
517 +{
518 + unsigned int i;
519 +
520 + if (chan->nr_blocks > 1) {
521 + for (i = 0; i < chan->nr_blocks; i++)
522 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
523 + chan->block[i].lli_dma_addr);
524 + kfree(chan->block);
525 + }
526 +
527 + chan->state = CH_STATE_ALLOCATED;
528 +}
529 +
530 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
531 + struct dma_request_sg *req)
532 +{
533 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
534 + struct dw_dma_channel *chan;
535 + unsigned long ctlhi, ctllo, cfghi, cfglo;
536 + unsigned long block_size;
537 + unsigned int nr_blocks;
538 + int ret, i, direction;
539 + unsigned long flags;
540 +
541 + spin_lock_irqsave(&dmac->lock, flags);
542 +
543 + ret = -EINVAL;
544 + if (req->req.channel >= DMAC_NR_CHANNELS
545 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
546 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
547 + spin_unlock_irqrestore(&dmac->lock, flags);
548 + return -EINVAL;
549 + }
550 +
551 + chan = &dmac->channel[req->req.channel];
552 + chan->state = CH_STATE_BUSY;
553 + chan->req_sg = req;
554 + chan->is_cyclic = 0;
555 +
556 + /*
557 + * We have marked the channel as busy, so no need to keep the
558 + * lock as long as we only touch the channel-specific
559 + * registers
560 + */
561 + spin_unlock_irqrestore(&dmac->lock, flags);
562 +
563 + /*
564 + * There may be limitations in the driver and/or the DMA
565 + * controller that prevents us from sending a whole
566 + * scatterlist item in one go. Taking this into account,
567 + * calculate the number of block transfers we need to set up.
568 + *
569 + * FIXME: Let the peripheral driver know about the maximum
570 + * block size we support. We really don't want to use a
571 + * different block size than what was suggested by the
572 + * peripheral.
573 + *
574 + * Each block will get its own Linked List Item (LLI) below.
575 + */
576 + block_size = req->block_size;
577 + nr_blocks = req->nr_blocks;
578 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
579 + block_size, nr_blocks, req->nr_sg);
580 +
581 + BUG_ON(nr_blocks == 0);
582 + chan->nr_blocks = nr_blocks;
583 +
584 + ret = -EINVAL;
585 + cfglo = cfghi = 0;
586 + switch (req->direction) {
587 + case DMA_DIR_MEM_TO_PERIPH:
588 + direction = DMA_TO_DEVICE;
589 + cfghi = req->periph_id << (43 - 32);
590 + break;
591 +
592 + case DMA_DIR_PERIPH_TO_MEM:
593 + direction = DMA_FROM_DEVICE;
594 + cfghi = req->periph_id << (39 - 32);
595 + break;
596 + default:
597 + goto out_unclaim_channel;
598 + }
599 +
600 + chan->direction = direction;
601 +
602 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
603 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
604 +
605 + ctlhi = block_size >> req->width;
606 + ctllo = ((req->direction << 20)
607 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
608 + | (req->width << 4) | (req->width << 1)
609 + | (1 << 0)); // interrupt enable
610 +
611 + if (nr_blocks == 1) {
612 + /* Only one block: No need to use block chaining */
613 + if (direction == DMA_TO_DEVICE) {
614 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
615 + req->sg->dma_address);
616 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
617 + req->data_reg);
618 + ctllo |= 2 << 7; // no dst increment
619 + } else {
620 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
621 + req->data_reg);
622 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
623 + req->sg->dma_address);
624 + ctllo |= 2 << 9; // no src increment
625 + }
626 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
627 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
628 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
629 + } else {
630 + struct dw_dma_lli *lli, *lli_prev = NULL;
631 + int j = 0, offset = 0;
632 +
633 + ret = -ENOMEM;
634 + chan->block = allocate_blocks(dmac, nr_blocks);
635 + if (!chan->block)
636 + goto out_unclaim_channel;
637 +
638 + if (direction == DMA_TO_DEVICE)
639 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
640 + else
641 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
642 +
643 + /*
644 + * Map scatterlist items to blocks. One scatterlist
645 + * item may need more than one block for the reasons
646 + * mentioned above.
647 + */
648 + for (i = 0; i < nr_blocks; i++) {
649 + lli = chan->block[i].lli_vaddr;
650 + if (lli_prev) {
651 + lli_prev->llp = chan->block[i].lli_dma_addr;
652 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
653 + i - 1, chan->block[i - 1].lli_vaddr,
654 + chan->block[i - 1].lli_dma_addr,
655 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
656 + lli_prev->ctllo, lli_prev->ctlhi);
657 + }
658 + lli->llp = 0;
659 + lli->ctllo = ctllo;
660 + lli->ctlhi = ctlhi;
661 + if (direction == DMA_TO_DEVICE) {
662 + lli->sar = req->sg[j].dma_address + offset;
663 + lli->dar = req->data_reg;
664 + } else {
665 + lli->sar = req->data_reg;
666 + lli->dar = req->sg[j].dma_address + offset;
667 + }
668 + lli_prev = lli;
669 +
670 + offset += block_size;
671 + if (offset > req->sg[j].length) {
672 + j++;
673 + offset = 0;
674 + }
675 + }
676 +
677 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
678 + i - 1, chan->block[i - 1].lli_vaddr,
679 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
680 + lli_prev->dar, lli_prev->llp,
681 + lli_prev->ctllo, lli_prev->ctlhi);
682 +
683 + /*
684 + * SAR, DAR and CTL are initialized from the LLI. We
685 + * only have to enable the LLI bits in CTL.
686 + */
687 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
688 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
689 + chan->block[0].lli_dma_addr);
690 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
691 + }
692 +
693 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
694 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
695 + if (req->req.block_complete)
696 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
697 + else
698 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
699 +
700 + return 0;
701 +
702 +out_unclaim_channel:
703 + chan->state = CH_STATE_ALLOCATED;
704 + return ret;
705 +}
706 +
707 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
708 + struct dma_request_cyclic *req)
709 +{
710 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
711 + struct dw_dma_channel *chan;
712 + unsigned long ctlhi, ctllo, cfghi, cfglo;
713 + unsigned long block_size;
714 + int ret, i, direction;
715 + unsigned long flags;
716 +
717 + spin_lock_irqsave(&dmac->lock, flags);
718 +
719 + block_size = (req->buffer_size/req->periods) >> req->width;
720 +
721 + ret = -EINVAL;
722 + if (req->req.channel >= DMAC_NR_CHANNELS
723 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
724 + || (req->periods == 0)
725 + || block_size > DMAC_MAX_BLOCKSIZE) {
726 + spin_unlock_irqrestore(&dmac->lock, flags);
727 + return -EINVAL;
728 + }
729 +
730 + chan = &dmac->channel[req->req.channel];
731 + chan->state = CH_STATE_BUSY;
732 + chan->is_cyclic = 1;
733 + chan->req_cyclic = req;
734 +
735 + /*
736 + * We have marked the channel as busy, so no need to keep the
737 + * lock as long as we only touch the channel-specific
738 + * registers
739 + */
740 + spin_unlock_irqrestore(&dmac->lock, flags);
741 +
742 + /*
743 + Setup
744 + */
745 + BUG_ON(req->buffer_size % req->periods);
746 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
747 +
748 + chan->nr_blocks = req->periods;
749 +
750 + ret = -EINVAL;
751 + cfglo = cfghi = 0;
752 + switch (req->direction) {
753 + case DMA_DIR_MEM_TO_PERIPH:
754 + direction = DMA_TO_DEVICE;
755 + cfghi = req->periph_id << (43 - 32);
756 + break;
757 +
758 + case DMA_DIR_PERIPH_TO_MEM:
759 + direction = DMA_FROM_DEVICE;
760 + cfghi = req->periph_id << (39 - 32);
761 + break;
762 + default:
763 + goto out_unclaim_channel;
764 + }
765 +
766 + chan->direction = direction;
767 +
768 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
769 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
770 +
771 + ctlhi = block_size;
772 + ctllo = ((req->direction << 20)
773 + | (req->width << 4) | (req->width << 1)
774 + | (1 << 0)); // interrupt enable
775 +
776 + {
777 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
778 +
779 + ret = -ENOMEM;
780 + chan->block = allocate_blocks(dmac, req->periods);
781 + if (!chan->block)
782 + goto out_unclaim_channel;
783 +
784 + if (direction == DMA_TO_DEVICE)
785 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
786 + else
787 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
788 +
789 + /*
790 + * Set up a linked list items where each period gets
791 + * an item. The linked list item for the last period
792 + * points back to the star of the buffer making a
793 + * cyclic buffer.
794 + */
795 + for (i = 0; i < req->periods; i++) {
796 + lli = chan->block[i].lli_vaddr;
797 + if (lli_prev) {
798 + lli_prev->llp = chan->block[i].lli_dma_addr;
799 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
800 + i - 1, chan->block[i - 1].lli_vaddr,
801 + chan->block[i - 1].lli_dma_addr,
802 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
803 + lli_prev->ctllo, lli_prev->ctlhi);*/
804 + }
805 + lli->llp = 0;
806 + lli->ctllo = ctllo;
807 + lli->ctlhi = ctlhi;
808 + if (direction == DMA_TO_DEVICE) {
809 + lli->sar = req->buffer_start + i*(block_size << req->width);
810 + lli->dar = req->data_reg;
811 + } else {
812 + lli->sar = req->data_reg;
813 + lli->dar = req->buffer_start + i*(block_size << req->width);
814 + }
815 + lli_prev = lli;
816 + }
817 + lli->llp = chan->block[0].lli_dma_addr;
818 +
819 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
820 + i - 1, chan->block[i - 1].lli_vaddr,
821 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
822 + lli_prev->dar, lli_prev->llp,
823 + lli_prev->ctllo, lli_prev->ctlhi); */
824 +
825 + /*
826 + * SAR, DAR and CTL are initialized from the LLI. We
827 + * only have to enable the LLI bits in CTL.
828 + */
829 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
830 + chan->block[0].lli_dma_addr);
831 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
832 + }
833 +
834 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
835 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
836 + if (req->req.block_complete)
837 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
838 + else
839 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
840 +
841 + return 0;
842 +
843 +out_unclaim_channel:
844 + chan->state = CH_STATE_ALLOCATED;
845 + return ret;
846 +}
847 +
848 +static int dmac_start_request(struct dma_controller *_dmac,
849 + unsigned int channel)
850 +{
851 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
852 +
853 + BUG_ON(channel >= DMAC_NR_CHANNELS);
854 +
855 + set_channel_bit(dmac, CH_EN, channel);
856 +
857 + return 0;
858 +}
859 +
860 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
861 + unsigned int channel)
862 +{
863 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
864 + struct dw_dma_channel *chan;
865 + dma_addr_t current_pos;
866 +
867 + BUG_ON(channel >= DMAC_NR_CHANNELS);
868 +
869 + chan = &dmac->channel[channel];
870 +
871 + switch (chan->direction) {
872 + case DMA_TO_DEVICE:
873 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
874 + break;
875 + case DMA_FROM_DEVICE:
876 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
877 + break;
878 + default:
879 + return 0;
880 + }
881 +
882 +
883 + if (!current_pos) {
884 + if (chan->is_cyclic) {
885 + current_pos = chan->req_cyclic->buffer_start;
886 + } else {
887 + current_pos = chan->req_sg->sg->dma_address;
888 + }
889 + }
890 +
891 + return current_pos;
892 +}
893 +
894 +
895 +static int dmac_stop_request(struct dma_controller *_dmac,
896 + unsigned int channel)
897 +{
898 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
899 + struct dw_dma_channel *chan;
900 +
901 + BUG_ON(channel >= DMAC_NR_CHANNELS);
902 +
903 + chan = &dmac->channel[channel];
904 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
905 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
906 + dmac_chan_readl_lo(dmac, channel, DAR),
907 + dmac_chan_readl_lo(dmac, channel, LLP),
908 + dmac_chan_readl_hi(dmac, channel, CTL),
909 + dmac_chan_readl_lo(dmac, channel, CTL));
910 +
911 + if (chan->state == CH_STATE_BUSY) {
912 + clear_channel_bit(dmac, CH_EN, channel);
913 + cleanup_channel(dmac, &dmac->channel[channel]);
914 + }
915 +
916 + return 0;
917 +}
918 +
919 +
920 +static void dmac_block_complete(struct dw_dma_controller *dmac)
921 +{
922 + struct dw_dma_channel *chan;
923 + unsigned long status, chanid;
924 +
925 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
926 +
927 + while (status) {
928 + struct dma_request *req;
929 + chanid = __ffs(status);
930 + chan = &dmac->channel[chanid];
931 +
932 + if (chan->is_cyclic) {
933 + BUG_ON(!chan->req_cyclic
934 + || !chan->req_cyclic->req.block_complete);
935 + req = &chan->req_cyclic->req;
936 + } else {
937 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
938 + req = &chan->req_sg->req;
939 + }
940 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
941 + req->block_complete(req);
942 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
943 + }
944 +}
945 +
946 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
947 +{
948 + struct dw_dma_channel *chan;
949 + struct dma_request *req;
950 + unsigned long status, chanid;
951 +
952 + status = dmac_readl_lo(dmac, STATUS_XFER);
953 +
954 + while (status) {
955 + chanid = __ffs(status);
956 + chan = &dmac->channel[chanid];
957 +
958 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
959 +
960 + req = &chan->req_sg->req;
961 + BUG_ON(!req);
962 + cleanup_channel(dmac, chan);
963 + if (req->xfer_complete)
964 + req->xfer_complete(req);
965 +
966 + status = dmac_readl_lo(dmac, STATUS_XFER);
967 + }
968 +}
969 +
970 +static void dmac_error(struct dw_dma_controller *dmac)
971 +{
972 + struct dw_dma_channel *chan;
973 + unsigned long status, chanid;
974 +
975 + status = dmac_readl_lo(dmac, STATUS_ERROR);
976 +
977 + while (status) {
978 + struct dma_request *req;
979 +
980 + chanid = __ffs(status);
981 + chan = &dmac->channel[chanid];
982 +
983 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
984 + clear_channel_bit(dmac, CH_EN, chanid);
985 +
986 + if (chan->is_cyclic) {
987 + BUG_ON(!chan->req_cyclic);
988 + req = &chan->req_cyclic->req;
989 + } else {
990 + BUG_ON(!chan->req_sg);
991 + req = &chan->req_sg->req;
992 + }
993 +
994 + cleanup_channel(dmac, chan);
995 + if (req->error)
996 + req->error(req);
997 +
998 + status = dmac_readl_lo(dmac, STATUS_XFER);
999 + }
1000 +}
1001 +
1002 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
1003 +{
1004 + struct dw_dma_controller *dmac = dev_id;
1005 + unsigned long status;
1006 + int ret = IRQ_NONE;
1007 +
1008 + spin_lock(&dmac->lock);
1009 +
1010 + status = dmac_readl_lo(dmac, STATUS_INT);
1011 +
1012 + while (status) {
1013 + ret = IRQ_HANDLED;
1014 + if (status & 0x10)
1015 + dmac_error(dmac);
1016 + if (status & 0x02)
1017 + dmac_block_complete(dmac);
1018 + if (status & 0x01)
1019 + dmac_xfer_complete(dmac);
1020 +
1021 + status = dmac_readl_lo(dmac, STATUS_INT);
1022 + }
1023 +
1024 + spin_unlock(&dmac->lock);
1025 + return ret;
1026 +}
1027 +
1028 +static int __devinit dmac_probe(struct platform_device *pdev)
1029 +{
1030 + struct dw_dma_controller *dmac;
1031 + struct resource *regs;
1032 + int ret;
1033 +
1034 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035 + if (!regs)
1036 + return -ENXIO;
1037 +
1038 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
1039 + if (!dmac)
1040 + return -ENOMEM;
1041 + memset(dmac, 0, sizeof(*dmac));
1042 +
1043 + dmac->hclk = clk_get(&pdev->dev, "hclk");
1044 + if (IS_ERR(dmac->hclk)) {
1045 + ret = PTR_ERR(dmac->hclk);
1046 + goto out_free_dmac;
1047 + }
1048 + clk_enable(dmac->hclk);
1049 +
1050 + ret = -ENOMEM;
1051 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
1052 + sizeof(struct dw_dma_lli), 4, 0);
1053 + if (!dmac->lli_pool)
1054 + goto out_disable_clk;
1055 +
1056 + spin_lock_init(&dmac->lock);
1057 + dmac->dma.dev = &pdev->dev;
1058 + dmac->dma.alloc_channel = dmac_alloc_channel;
1059 + dmac->dma.release_channel = dmac_release_channel;
1060 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
1061 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
1062 + dmac->dma.start_request = dmac_start_request;
1063 + dmac->dma.stop_request = dmac_stop_request;
1064 + dmac->dma.get_current_pos = dmac_get_current_pos;
1065 +
1066 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
1067 + if (!dmac->regs)
1068 + goto out_free_pool;
1069 +
1070 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
1071 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
1072 + if (ret)
1073 + goto out_unmap_regs;
1074 +
1075 + /* Enable the DMA controller */
1076 + dmac_writel_lo(dmac, CFG, 1);
1077 +
1078 + register_dma_controller(&dmac->dma);
1079 +
1080 + printk(KERN_INFO
1081 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
1082 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
1083 +
1084 + return 0;
1085 +
1086 +out_unmap_regs:
1087 + iounmap(dmac->regs);
1088 +out_free_pool:
1089 + dma_pool_destroy(dmac->lli_pool);
1090 +out_disable_clk:
1091 + clk_disable(dmac->hclk);
1092 + clk_put(dmac->hclk);
1093 +out_free_dmac:
1094 + kfree(dmac);
1095 + return ret;
1096 +}
1097 +
1098 +static struct platform_driver dmac_driver = {
1099 + .probe = dmac_probe,
1100 + .driver = {
1101 + .name = "dmaca",
1102 + },
1103 +};
1104 +
1105 +static int __init dmac_init(void)
1106 +{
1107 + return platform_driver_register(&dmac_driver);
1108 +}
1109 +subsys_initcall(dmac_init);
1110 +
1111 +static void __exit dmac_exit(void)
1112 +{
1113 + platform_driver_unregister(&dmac_driver);
1114 +}
1115 +module_exit(dmac_exit);
1116 +
1117 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1118 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
1119 +MODULE_LICENSE("GPL");
1120 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/dw-dmac.h linux-avr32.git/arch/avr32/drivers/dw-dmac.h
1121 --- linux-2.6.22.1/arch/avr32/drivers/dw-dmac.h 1970-01-01 01:00:00.000000000 +0100
1122 +++ linux-avr32.git/arch/avr32/drivers/dw-dmac.h 2007-06-06 11:33:46.000000000 +0200
1123 @@ -0,0 +1,42 @@
1124 +/*
1125 + * Driver for the Synopsys DesignWare DMA Controller
1126 + *
1127 + * Copyright (C) 2005-2006 Atmel Corporation
1128 + *
1129 + * This program is free software; you can redistribute it and/or modify
1130 + * it under the terms of the GNU General Public License version 2 as
1131 + * published by the Free Software Foundation.
1132 + */
1133 +#ifndef __AVR32_DW_DMAC_H__
1134 +#define __AVR32_DW_DMAC_H__
1135 +
1136 +#define DW_DMAC_CFG 0x398
1137 +#define DW_DMAC_CH_EN 0x3a0
1138 +
1139 +#define DW_DMAC_STATUS_XFER 0x2e8
1140 +#define DW_DMAC_STATUS_BLOCK 0x2f0
1141 +#define DW_DMAC_STATUS_ERROR 0x308
1142 +
1143 +#define DW_DMAC_MASK_XFER 0x310
1144 +#define DW_DMAC_MASK_BLOCK 0x318
1145 +#define DW_DMAC_MASK_ERROR 0x330
1146 +
1147 +#define DW_DMAC_CLEAR_XFER 0x338
1148 +#define DW_DMAC_CLEAR_BLOCK 0x340
1149 +#define DW_DMAC_CLEAR_ERROR 0x358
1150 +
1151 +#define DW_DMAC_STATUS_INT 0x360
1152 +
1153 +#define DW_DMAC_CHAN_SAR 0x000
1154 +#define DW_DMAC_CHAN_DAR 0x008
1155 +#define DW_DMAC_CHAN_LLP 0x010
1156 +#define DW_DMAC_CHAN_CTL 0x018
1157 +#define DW_DMAC_CHAN_SSTAT 0x020
1158 +#define DW_DMAC_CHAN_DSTAT 0x028
1159 +#define DW_DMAC_CHAN_SSTATAR 0x030
1160 +#define DW_DMAC_CHAN_DSTATAR 0x038
1161 +#define DW_DMAC_CHAN_CFG 0x040
1162 +#define DW_DMAC_CHAN_SGR 0x048
1163 +#define DW_DMAC_CHAN_DSR 0x050
1164 +
1165 +#endif /* __AVR32_DW_DMAC_H__ */
1166 diff -x .git -Nur linux-2.6.22.1/arch/avr32/drivers/Makefile linux-avr32.git/arch/avr32/drivers/Makefile
1167 --- linux-2.6.22.1/arch/avr32/drivers/Makefile 1970-01-01 01:00:00.000000000 +0100
1168 +++ linux-avr32.git/arch/avr32/drivers/Makefile 2007-06-06 11:33:46.000000000 +0200
1169 @@ -0,0 +1 @@
1170 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
1171 diff -x .git -Nur linux-2.6.22.1/arch/avr32/Kconfig linux-avr32.git/arch/avr32/Kconfig
1172 --- linux-2.6.22.1/arch/avr32/Kconfig 2007-07-10 20:56:30.000000000 +0200
1173 +++ linux-avr32.git/arch/avr32/Kconfig 2007-07-12 13:59:49.000000000 +0200
1174 @@ -113,6 +113,10 @@
1175 bool "ATNGW100 Network Gateway"
1176 endchoice
1177
1178 +if BOARD_ATSTK1000
1179 +source "arch/avr32/boards/atstk1000/Kconfig"
1180 +endif
1181 +
1182 choice
1183 prompt "Boot loader type"
1184 default LOADER_U_BOOT
1185 @@ -171,6 +175,10 @@
1186 enabling Nexus-compliant debuggers to keep track of the PID of the
1187 currently executing task.
1188
1189 +config DW_DMAC
1190 + tristate "Synopsys DesignWare DMA Controller support"
1191 + default y if CPU_AT32AP7000
1192 +
1193 # FPU emulation goes here
1194
1195 source "kernel/Kconfig.hz"
1196 @@ -185,6 +193,27 @@
1197
1198 endmenu
1199
1200 +menu "Power managment options"
1201 +
1202 +menu "CPU Frequency scaling"
1203 +
1204 +source "drivers/cpufreq/Kconfig"
1205 +
1206 +config CPU_FREQ_AT32AP
1207 + bool "CPU frequency driver for AT32AP"
1208 + depends on CPU_FREQ && PLATFORM_AT32AP
1209 + default n
1210 + help
1211 + This enables the CPU frequency driver for AT32AP processors.
1212 +
1213 + For details, take a look in <file:Documentation/cpu-freq>.
1214 +
1215 + If in doubt, say N.
1216 +
1217 +endmenu
1218 +
1219 +endmenu
1220 +
1221 menu "Bus options"
1222
1223 config PCI
1224 diff -x .git -Nur linux-2.6.22.1/arch/avr32/kernel/dma-controller.c linux-avr32.git/arch/avr32/kernel/dma-controller.c
1225 --- linux-2.6.22.1/arch/avr32/kernel/dma-controller.c 1970-01-01 01:00:00.000000000 +0100
1226 +++ linux-avr32.git/arch/avr32/kernel/dma-controller.c 2007-06-06 11:33:46.000000000 +0200
1227 @@ -0,0 +1,34 @@
1228 +/*
1229 + * Preliminary DMA controller framework for AVR32
1230 + *
1231 + * Copyright (C) 2005-2006 Atmel Corporation
1232 + *
1233 + * This program is free software; you can redistribute it and/or modify
1234 + * it under the terms of the GNU General Public License version 2 as
1235 + * published by the Free Software Foundation.
1236 + */
1237 +#include <asm/dma-controller.h>
1238 +
1239 +static LIST_HEAD(controllers);
1240 +
1241 +int register_dma_controller(struct dma_controller *dmac)
1242 +{
1243 + static int next_id;
1244 +
1245 + dmac->id = next_id++;
1246 + list_add_tail(&dmac->list, &controllers);
1247 +
1248 + return 0;
1249 +}
1250 +EXPORT_SYMBOL(register_dma_controller);
1251 +
1252 +struct dma_controller *find_dma_controller(int id)
1253 +{
1254 + struct dma_controller *dmac;
1255 +
1256 + list_for_each_entry(dmac, &controllers, list)
1257 + if (dmac->id == id)
1258 + return dmac;
1259 + return NULL;
1260 +}
1261 +EXPORT_SYMBOL(find_dma_controller);
1262 diff -x .git -Nur linux-2.6.22.1/arch/avr32/kernel/Makefile linux-avr32.git/arch/avr32/kernel/Makefile
1263 --- linux-2.6.22.1/arch/avr32/kernel/Makefile 2007-07-10 20:56:30.000000000 +0200
1264 +++ linux-avr32.git/arch/avr32/kernel/Makefile 2007-06-06 11:33:46.000000000 +0200
1265 @@ -9,6 +9,7 @@
1266 obj-y += setup.o traps.o semaphore.o ptrace.o
1267 obj-y += signal.o sys_avr32.o process.o time.o
1268 obj-y += init_task.o switch_to.o cpu.o
1269 +obj-y += dma-controller.o
1270 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
1271 obj-$(CONFIG_KPROBES) += kprobes.o
1272
1273 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap7000.c linux-avr32.git/arch/avr32/mach-at32ap/at32ap7000.c
1274 --- linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap7000.c 2007-07-10 20:56:30.000000000 +0200
1275 +++ linux-avr32.git/arch/avr32/mach-at32ap/at32ap7000.c 2007-07-12 13:59:49.000000000 +0200
1276 @@ -17,14 +17,20 @@
1277 #include <asm/arch/at32ap7000.h>
1278 #include <asm/arch/board.h>
1279 #include <asm/arch/portmux.h>
1280 -#include <asm/arch/sm.h>
1281
1282 #include <video/atmel_lcdc.h>
1283
1284 #include "clock.h"
1285 #include "hmatrix.h"
1286 #include "pio.h"
1287 -#include "sm.h"
1288 +#include "pm.h"
1289 +
1290 +/*
1291 + * We can reduce the code size a bit by using a constant here. Since
1292 + * this file is completely chip-specific, it's safe to not use
1293 + * ioremap. Generic drivers should of course never do this.
1294 + */
1295 +#define AT32_PM_BASE 0xfff00000
1296
1297 #define PBMEM(base) \
1298 { \
1299 @@ -88,6 +94,8 @@
1300 .index = _index, \
1301 }
1302
1303 +static DEFINE_SPINLOCK(pm_lock);
1304 +
1305 unsigned long at32ap7000_osc_rates[3] = {
1306 [0] = 32768,
1307 /* FIXME: these are ATSTK1002-specific */
1308 @@ -104,11 +112,11 @@
1309 {
1310 unsigned long div, mul, rate;
1311
1312 - if (!(control & SM_BIT(PLLEN)))
1313 + if (!(control & PM_BIT(PLLEN)))
1314 return 0;
1315
1316 - div = SM_BFEXT(PLLDIV, control) + 1;
1317 - mul = SM_BFEXT(PLLMUL, control) + 1;
1318 + div = PM_BFEXT(PLLDIV, control) + 1;
1319 + mul = PM_BFEXT(PLLMUL, control) + 1;
1320
1321 rate = clk->parent->get_rate(clk->parent);
1322 rate = (rate + div / 2) / div;
1323 @@ -121,7 +129,7 @@
1324 {
1325 u32 control;
1326
1327 - control = sm_readl(&system_manager, PM_PLL0);
1328 + control = pm_readl(PLL0);
1329
1330 return pll_get_rate(clk, control);
1331 }
1332 @@ -130,7 +138,7 @@
1333 {
1334 u32 control;
1335
1336 - control = sm_readl(&system_manager, PM_PLL1);
1337 + control = pm_readl(PLL1);
1338
1339 return pll_get_rate(clk, control);
1340 }
1341 @@ -187,108 +195,139 @@
1342
1343 static void cpu_clk_mode(struct clk *clk, int enabled)
1344 {
1345 - struct at32_sm *sm = &system_manager;
1346 unsigned long flags;
1347 u32 mask;
1348
1349 - spin_lock_irqsave(&sm->lock, flags);
1350 - mask = sm_readl(sm, PM_CPU_MASK);
1351 + spin_lock_irqsave(&pm_lock, flags);
1352 + mask = pm_readl(CPU_MASK);
1353 if (enabled)
1354 mask |= 1 << clk->index;
1355 else
1356 mask &= ~(1 << clk->index);
1357 - sm_writel(sm, PM_CPU_MASK, mask);
1358 - spin_unlock_irqrestore(&sm->lock, flags);
1359 + pm_writel(CPU_MASK, mask);
1360 + spin_unlock_irqrestore(&pm_lock, flags);
1361 }
1362
1363 static unsigned long cpu_clk_get_rate(struct clk *clk)
1364 {
1365 unsigned long cksel, shift = 0;
1366
1367 - cksel = sm_readl(&system_manager, PM_CKSEL);
1368 - if (cksel & SM_BIT(CPUDIV))
1369 - shift = SM_BFEXT(CPUSEL, cksel) + 1;
1370 + cksel = pm_readl(CKSEL);
1371 + if (cksel & PM_BIT(CPUDIV))
1372 + shift = PM_BFEXT(CPUSEL, cksel) + 1;
1373
1374 return bus_clk_get_rate(clk, shift);
1375 }
1376
1377 +static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
1378 +{
1379 + u32 control;
1380 + unsigned long parent_rate, child_div, actual_rate, div;
1381 +
1382 + parent_rate = clk->parent->get_rate(clk->parent);
1383 + control = pm_readl(CKSEL);
1384 +
1385 + if (control & PM_BIT(HSBDIV))
1386 + child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
1387 + else
1388 + child_div = 1;
1389 +
1390 + if (rate > 3 * (parent_rate / 4) || child_div == 1) {
1391 + actual_rate = parent_rate;
1392 + control &= ~PM_BIT(CPUDIV);
1393 + } else {
1394 + unsigned int cpusel;
1395 + div = (parent_rate + rate / 2) / rate;
1396 + if (div > child_div)
1397 + div = child_div;
1398 + cpusel = (div > 1) ? (fls(div) - 2) : 0;
1399 + control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
1400 + actual_rate = parent_rate / (1 << (cpusel + 1));
1401 + }
1402 +
1403 + pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
1404 + clk->name, rate, actual_rate);
1405 +
1406 + if (apply)
1407 + pm_writel(CKSEL, control);
1408 +
1409 + return actual_rate;
1410 +}
1411 +
1412 static void hsb_clk_mode(struct clk *clk, int enabled)
1413 {
1414 - struct at32_sm *sm = &system_manager;
1415 unsigned long flags;
1416 u32 mask;
1417
1418 - spin_lock_irqsave(&sm->lock, flags);
1419 - mask = sm_readl(sm, PM_HSB_MASK);
1420 + spin_lock_irqsave(&pm_lock, flags);
1421 + mask = pm_readl(HSB_MASK);
1422 if (enabled)
1423 mask |= 1 << clk->index;
1424 else
1425 mask &= ~(1 << clk->index);
1426 - sm_writel(sm, PM_HSB_MASK, mask);
1427 - spin_unlock_irqrestore(&sm->lock, flags);
1428 + pm_writel(HSB_MASK, mask);
1429 + spin_unlock_irqrestore(&pm_lock, flags);
1430 }
1431
1432 static unsigned long hsb_clk_get_rate(struct clk *clk)
1433 {
1434 unsigned long cksel, shift = 0;
1435
1436 - cksel = sm_readl(&system_manager, PM_CKSEL);
1437 - if (cksel & SM_BIT(HSBDIV))
1438 - shift = SM_BFEXT(HSBSEL, cksel) + 1;
1439 + cksel = pm_readl(CKSEL);
1440 + if (cksel & PM_BIT(HSBDIV))
1441 + shift = PM_BFEXT(HSBSEL, cksel) + 1;
1442
1443 return bus_clk_get_rate(clk, shift);
1444 }
1445
1446 static void pba_clk_mode(struct clk *clk, int enabled)
1447 {
1448 - struct at32_sm *sm = &system_manager;
1449 unsigned long flags;
1450 u32 mask;
1451
1452 - spin_lock_irqsave(&sm->lock, flags);
1453 - mask = sm_readl(sm, PM_PBA_MASK);
1454 + spin_lock_irqsave(&pm_lock, flags);
1455 + mask = pm_readl(PBA_MASK);
1456 if (enabled)
1457 mask |= 1 << clk->index;
1458 else
1459 mask &= ~(1 << clk->index);
1460 - sm_writel(sm, PM_PBA_MASK, mask);
1461 - spin_unlock_irqrestore(&sm->lock, flags);
1462 + pm_writel(PBA_MASK, mask);
1463 + spin_unlock_irqrestore(&pm_lock, flags);
1464 }
1465
1466 static unsigned long pba_clk_get_rate(struct clk *clk)
1467 {
1468 unsigned long cksel, shift = 0;
1469
1470 - cksel = sm_readl(&system_manager, PM_CKSEL);
1471 - if (cksel & SM_BIT(PBADIV))
1472 - shift = SM_BFEXT(PBASEL, cksel) + 1;
1473 + cksel = pm_readl(CKSEL);
1474 + if (cksel & PM_BIT(PBADIV))
1475 + shift = PM_BFEXT(PBASEL, cksel) + 1;
1476
1477 return bus_clk_get_rate(clk, shift);
1478 }
1479
1480 static void pbb_clk_mode(struct clk *clk, int enabled)
1481 {
1482 - struct at32_sm *sm = &system_manager;
1483 unsigned long flags;
1484 u32 mask;
1485
1486 - spin_lock_irqsave(&sm->lock, flags);
1487 - mask = sm_readl(sm, PM_PBB_MASK);
1488 + spin_lock_irqsave(&pm_lock, flags);
1489 + mask = pm_readl(PBB_MASK);
1490 if (enabled)
1491 mask |= 1 << clk->index;
1492 else
1493 mask &= ~(1 << clk->index);
1494 - sm_writel(sm, PM_PBB_MASK, mask);
1495 - spin_unlock_irqrestore(&sm->lock, flags);
1496 + pm_writel(PBB_MASK, mask);
1497 + spin_unlock_irqrestore(&pm_lock, flags);
1498 }
1499
1500 static unsigned long pbb_clk_get_rate(struct clk *clk)
1501 {
1502 unsigned long cksel, shift = 0;
1503
1504 - cksel = sm_readl(&system_manager, PM_CKSEL);
1505 - if (cksel & SM_BIT(PBBDIV))
1506 - shift = SM_BFEXT(PBBSEL, cksel) + 1;
1507 + cksel = pm_readl(CKSEL);
1508 + if (cksel & PM_BIT(PBBDIV))
1509 + shift = PM_BFEXT(PBBSEL, cksel) + 1;
1510
1511 return bus_clk_get_rate(clk, shift);
1512 }
1513 @@ -296,6 +335,7 @@
1514 static struct clk cpu_clk = {
1515 .name = "cpu",
1516 .get_rate = cpu_clk_get_rate,
1517 + .set_rate = cpu_clk_set_rate,
1518 .users = 1,
1519 };
1520 static struct clk hsb_clk = {
1521 @@ -327,12 +367,12 @@
1522 {
1523 u32 control;
1524
1525 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
1526 + control = pm_readl(GCCTRL(clk->index));
1527 if (enabled)
1528 - control |= SM_BIT(CEN);
1529 + control |= PM_BIT(CEN);
1530 else
1531 - control &= ~SM_BIT(CEN);
1532 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
1533 + control &= ~PM_BIT(CEN);
1534 + pm_writel(GCCTRL(clk->index), control);
1535 }
1536
1537 static unsigned long genclk_get_rate(struct clk *clk)
1538 @@ -340,9 +380,9 @@
1539 u32 control;
1540 unsigned long div = 1;
1541
1542 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
1543 - if (control & SM_BIT(DIVEN))
1544 - div = 2 * (SM_BFEXT(DIV, control) + 1);
1545 + control = pm_readl(GCCTRL(clk->index));
1546 + if (control & PM_BIT(DIVEN))
1547 + div = 2 * (PM_BFEXT(DIV, control) + 1);
1548
1549 return clk->parent->get_rate(clk->parent) / div;
1550 }
1551 @@ -353,23 +393,22 @@
1552 unsigned long parent_rate, actual_rate, div;
1553
1554 parent_rate = clk->parent->get_rate(clk->parent);
1555 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
1556 + control = pm_readl(GCCTRL(clk->index));
1557
1558 if (rate > 3 * parent_rate / 4) {
1559 actual_rate = parent_rate;
1560 - control &= ~SM_BIT(DIVEN);
1561 + control &= ~PM_BIT(DIVEN);
1562 } else {
1563 div = (parent_rate + rate) / (2 * rate) - 1;
1564 - control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
1565 + control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
1566 actual_rate = parent_rate / (2 * (div + 1));
1567 }
1568
1569 - printk("clk %s: new rate %lu (actual rate %lu)\n",
1570 - clk->name, rate, actual_rate);
1571 + dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
1572 + clk->name, rate, actual_rate);
1573
1574 if (apply)
1575 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
1576 - control);
1577 + pm_writel(GCCTRL(clk->index), control);
1578
1579 return actual_rate;
1580 }
1581 @@ -378,24 +417,24 @@
1582 {
1583 u32 control;
1584
1585 - printk("clk %s: new parent %s (was %s)\n",
1586 - clk->name, parent->name, clk->parent->name);
1587 + dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
1588 + clk->name, parent->name, clk->parent->name);
1589
1590 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
1591 + control = pm_readl(GCCTRL(clk->index));
1592
1593 if (parent == &osc1 || parent == &pll1)
1594 - control |= SM_BIT(OSCSEL);
1595 + control |= PM_BIT(OSCSEL);
1596 else if (parent == &osc0 || parent == &pll0)
1597 - control &= ~SM_BIT(OSCSEL);
1598 + control &= ~PM_BIT(OSCSEL);
1599 else
1600 return -EINVAL;
1601
1602 if (parent == &pll0 || parent == &pll1)
1603 - control |= SM_BIT(PLLSEL);
1604 + control |= PM_BIT(PLLSEL);
1605 else
1606 - control &= ~SM_BIT(PLLSEL);
1607 + control &= ~PM_BIT(PLLSEL);
1608
1609 - sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
1610 + pm_writel(GCCTRL(clk->index), control);
1611 clk->parent = parent;
1612
1613 return 0;
1614 @@ -408,11 +447,11 @@
1615
1616 BUG_ON(clk->index > 7);
1617
1618 - control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
1619 - if (control & SM_BIT(OSCSEL))
1620 - parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
1621 + control = pm_readl(GCCTRL(clk->index));
1622 + if (control & PM_BIT(OSCSEL))
1623 + parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
1624 else
1625 - parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
1626 + parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
1627
1628 clk->parent = parent;
1629 }
1630 @@ -420,21 +459,53 @@
1631 /* --------------------------------------------------------------------
1632 * System peripherals
1633 * -------------------------------------------------------------------- */
1634 -static struct resource sm_resource[] = {
1635 - PBMEM(0xfff00000),
1636 - NAMED_IRQ(19, "eim"),
1637 - NAMED_IRQ(20, "pm"),
1638 - NAMED_IRQ(21, "rtc"),
1639 +static struct resource at32_pm0_resource[] = {
1640 + {
1641 + .start = 0xfff00000,
1642 + .end = 0xfff0007f,
1643 + .flags = IORESOURCE_MEM,
1644 + },
1645 + IRQ(20),
1646 };
1647 -struct platform_device at32_sm_device = {
1648 - .name = "sm",
1649 - .id = 0,
1650 - .resource = sm_resource,
1651 - .num_resources = ARRAY_SIZE(sm_resource),
1652 +
1653 +static struct resource at32ap700x_rtc0_resource[] = {
1654 + {
1655 + .start = 0xfff00080,
1656 + .end = 0xfff000af,
1657 + .flags = IORESOURCE_MEM,
1658 + },
1659 + IRQ(21),
1660 +};
1661 +
1662 +static struct resource at32_wdt0_resource[] = {
1663 + {
1664 + .start = 0xfff000b0,
1665 + .end = 0xfff000bf,
1666 + .flags = IORESOURCE_MEM,
1667 + },
1668 +};
1669 +
1670 +static struct resource at32_eic0_resource[] = {
1671 + {
1672 + .start = 0xfff00100,
1673 + .end = 0xfff0013f,
1674 + .flags = IORESOURCE_MEM,
1675 + },
1676 + IRQ(19),
1677 };
1678 -static struct clk at32_sm_pclk = {
1679 +
1680 +DEFINE_DEV(at32_pm, 0);
1681 +DEFINE_DEV(at32ap700x_rtc, 0);
1682 +DEFINE_DEV(at32_wdt, 0);
1683 +DEFINE_DEV(at32_eic, 0);
1684 +
1685 +/*
1686 + * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
1687 + * is always running.
1688 + */
1689 +static struct clk at32_pm_pclk = {
1690 .name = "pclk",
1691 - .dev = &at32_sm_device.dev,
1692 + .dev = &at32_pm0_device.dev,
1693 .parent = &pbb_clk,
1694 .mode = pbb_clk_mode,
1695 .get_rate = pbb_clk_get_rate,
1696 @@ -491,6 +562,17 @@
1697 .users = 1,
1698 };
1699
1700 +static struct resource dmaca0_resource[] = {
1701 + {
1702 + .start = 0xff200000,
1703 + .end = 0xff20ffff,
1704 + .flags = IORESOURCE_MEM,
1705 + },
1706 + IRQ(2),
1707 +};
1708 +DEFINE_DEV(dmaca, 0);
1709 +DEV_CLK(hclk, dmaca0, hsb, 10);
1710 +
1711 /* --------------------------------------------------------------------
1712 * HMATRIX
1713 * -------------------------------------------------------------------- */
1714 @@ -583,12 +665,14 @@
1715
1716 void __init at32_add_system_devices(void)
1717 {
1718 - system_manager.eim_first_irq = EIM_IRQ_BASE;
1719 -
1720 - platform_device_register(&at32_sm_device);
1721 + platform_device_register(&at32_pm0_device);
1722 platform_device_register(&at32_intc0_device);
1723 + platform_device_register(&at32ap700x_rtc0_device);
1724 + platform_device_register(&at32_wdt0_device);
1725 + platform_device_register(&at32_eic0_device);
1726 platform_device_register(&smc0_device);
1727 platform_device_register(&pdc_device);
1728 + platform_device_register(&dmaca0_device);
1729
1730 platform_device_register(&at32_systc0_device);
1731
1732 @@ -894,6 +978,83 @@
1733 }
1734
1735 /* --------------------------------------------------------------------
1736 + * TWI
1737 + * -------------------------------------------------------------------- */
1738 +
1739 +static struct resource atmel_twi0_resource[] = {
1740 + PBMEM(0xffe00800),
1741 + IRQ(5),
1742 +};
1743 +DEFINE_DEV(atmel_twi, 0);
1744 +DEV_CLK(pclk,atmel_twi0,pba,2);
1745 +
1746 +struct platform_device *__init
1747 +at32_add_device_twi(unsigned int id)
1748 +{
1749 + struct platform_device *pdev;
1750 +
1751 + switch (id) {
1752 + case 0:
1753 + pdev = &atmel_twi0_device;
1754 + select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1755 + select_peripheral(PA(7), PERIPH_A, 0); /* SCL */
1756 + break;
1757 +
1758 + default:
1759 + return NULL;
1760 + }
1761 +
1762 + platform_device_register(pdev);
1763 + return pdev;
1764 +}
1765 +
1766 +/* --------------------------------------------------------------------
1767 + * MMC
1768 + * -------------------------------------------------------------------- */
1769 +static struct mci_platform_data atmel_mci0_data = {
1770 + .detect_pin = GPIO_PIN_NONE,
1771 + .wp_pin = GPIO_PIN_NONE,
1772 +};
1773 +static struct resource atmel_mci0_resource[] = {
1774 + PBMEM(0xfff02400),
1775 + IRQ(28),
1776 +};
1777 +DEFINE_DEV_DATA(atmel_mci, 0);
1778 +DEV_CLK(mci_clk, atmel_mci0, pbb, 9);
1779 +
1780 +struct platform_device *__init
1781 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1782 +{
1783 + struct platform_device *pdev;
1784 +
1785 + switch (id) {
1786 + case 0:
1787 + pdev = &atmel_mci0_device;
1788 + select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1789 + select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1790 + select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1791 + select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1792 + select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1793 + select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1794 + break;
1795 + default:
1796 + return NULL;
1797 + }
1798 +
1799 + if (data) {
1800 + if (data->detect_pin != GPIO_PIN_NONE)
1801 + at32_select_gpio(data->detect_pin, 0);
1802 + if (data->wp_pin != GPIO_PIN_NONE)
1803 + at32_select_gpio(data->wp_pin, 0);
1804 + memcpy(pdev->dev.platform_data, data,
1805 + sizeof(struct mci_platform_data));
1806 + }
1807 +
1808 + platform_device_register(pdev);
1809 + return pdev;
1810 +}
1811 +
1812 +/* --------------------------------------------------------------------
1813 * LCDC
1814 * -------------------------------------------------------------------- */
1815 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1816 @@ -1013,6 +1174,228 @@
1817 }
1818
1819 /* --------------------------------------------------------------------
1820 + * USB Device Controller
1821 + * -------------------------------------------------------------------- */
1822 +static struct resource usba0_resource[] __initdata = {
1823 + {
1824 + .name = "fifo",
1825 + .start = 0xff300000,
1826 + .end = 0xff3fffff,
1827 + .flags = IORESOURCE_MEM,
1828 + }, {
1829 + .name = "regs",
1830 + .start = 0xfff03000,
1831 + .end = 0xfff033ff,
1832 + .flags = IORESOURCE_MEM,
1833 + },
1834 + IRQ(31),
1835 +};
1836 +static struct clk usba0_pclk = {
1837 + .name = "pclk",
1838 + .parent = &pbb_clk,
1839 + .mode = pbb_clk_mode,
1840 + .get_rate = pbb_clk_get_rate,
1841 + .index = 12,
1842 +};
1843 +static struct clk usba0_hclk = {
1844 + .name = "hclk",
1845 + .parent = &hsb_clk,
1846 + .mode = hsb_clk_mode,
1847 + .get_rate = hsb_clk_get_rate,
1848 + .index = 6,
1849 +};
1850 +
1851 +struct platform_device *__init
1852 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1853 +{
1854 + struct platform_device *pdev;
1855 +
1856 + if (id != 0)
1857 + return NULL;
1858 +
1859 + pdev = platform_device_alloc("atmel_usba_udc", 0);
1860 + if (!pdev)
1861 + return NULL;
1862 +
1863 + if (platform_device_add_resources(pdev, usba0_resource,
1864 + ARRAY_SIZE(usba0_resource)))
1865 + goto out_free_pdev;
1866 +
1867 + if (data) {
1868 + if (platform_device_add_data(pdev, data, sizeof(*data)))
1869 + goto out_free_pdev;
1870 +
1871 + if (data->vbus_pin != GPIO_PIN_NONE)
1872 + at32_select_gpio(data->vbus_pin, 0);
1873 + }
1874 +
1875 + usba0_pclk.dev = &pdev->dev;
1876 + usba0_hclk.dev = &pdev->dev;
1877 +
1878 + platform_device_add(pdev);
1879 +
1880 + return pdev;
1881 +
1882 +out_free_pdev:
1883 + platform_device_put(pdev);
1884 + return NULL;
1885 +}
1886 +
1887 +/* --------------------------------------------------------------------
1888 + * SSC
1889 + * -------------------------------------------------------------------- */
1890 +static struct resource ssc0_resource[] = {
1891 + PBMEM(0xffe01c00),
1892 + IRQ(10),
1893 +};
1894 +DEFINE_DEV(ssc, 0);
1895 +DEV_CLK(pclk, ssc0, pba, 7);
1896 +
1897 +static struct resource ssc1_resource[] = {
1898 + PBMEM(0xffe02000),
1899 + IRQ(11),
1900 +};
1901 +DEFINE_DEV(ssc, 1);
1902 +DEV_CLK(pclk, ssc1, pba, 8);
1903 +
1904 +static struct resource ssc2_resource[] = {
1905 + PBMEM(0xffe02400),
1906 + IRQ(12),
1907 +};
1908 +DEFINE_DEV(ssc, 2);
1909 +DEV_CLK(pclk, ssc2, pba, 9);
1910 +
1911 +struct platform_device *__init
1912 +at32_add_device_ssc(unsigned int id, unsigned int flags)
1913 +{
1914 + struct platform_device *pdev;
1915 +
1916 + switch (id) {
1917 + case 0:
1918 + pdev = &ssc0_device;
1919 + if (flags & ATMEL_SSC_RF)
1920 + select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1921 + if (flags & ATMEL_SSC_RK)
1922 + select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1923 + if (flags & ATMEL_SSC_TK)
1924 + select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1925 + if (flags & ATMEL_SSC_TF)
1926 + select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1927 + if (flags & ATMEL_SSC_TD)
1928 + select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1929 + if (flags & ATMEL_SSC_RD)
1930 + select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1931 + break;
1932 + case 1:
1933 + pdev = &ssc1_device;
1934 + if (flags & ATMEL_SSC_RF)
1935 + select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1936 + if (flags & ATMEL_SSC_RK)
1937 + select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1938 + if (flags & ATMEL_SSC_TK)
1939 + select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1940 + if (flags & ATMEL_SSC_TF)
1941 + select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1942 + if (flags & ATMEL_SSC_TD)
1943 + select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1944 + if (flags & ATMEL_SSC_RD)
1945 + select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1946 + break;
1947 + case 2:
1948 + pdev = &ssc2_device;
1949 + if (flags & ATMEL_SSC_TD)
1950 + select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1951 + if (flags & ATMEL_SSC_RD)
1952 + select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1953 + if (flags & ATMEL_SSC_TK)
1954 + select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1955 + if (flags & ATMEL_SSC_TF)
1956 + select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1957 + if (flags & ATMEL_SSC_RF)
1958 + select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1959 + if (flags & ATMEL_SSC_RK)
1960 + select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1961 + break;
1962 + default:
1963 + return NULL;
1964 + }
1965 +
1966 + platform_device_register(pdev);
1967 + return pdev;
1968 +}
1969 +
1970 +/* --------------------------------------------------------------------
1971 + * AC97C
1972 + * -------------------------------------------------------------------- */
1973 +static struct resource atmel_ac97c0_resource[] = {
1974 + PBMEM(0xfff02800),
1975 + IRQ(29),
1976 +};
1977 +DEFINE_DEV(atmel_ac97c, 0);
1978 +DEV_CLK(pclk, atmel_ac97c0, pbb, 10);
1979 +
1980 +struct platform_device *__init
1981 +at32_add_device_ac97c(unsigned int id)
1982 +{
1983 + struct platform_device *pdev;
1984 +
1985 + switch (id) {
1986 + case 0:
1987 + pdev = &atmel_ac97c0_device;
1988 + select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1989 + select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1990 + select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1991 + select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1992 + break;
1993 + default:
1994 + return NULL;
1995 + }
1996 +
1997 + platform_device_register(pdev);
1998 + return pdev;
1999 +}
2000 +
2001 +/* --------------------------------------------------------------------
2002 + * DAC
2003 + * -------------------------------------------------------------------- */
2004 +static struct resource abdac0_resource[] = {
2005 + PBMEM(0xfff02000),
2006 + IRQ(27),
2007 +};
2008 +DEFINE_DEV(abdac, 0);
2009 +DEV_CLK(pclk, abdac0, pbb, 8);
2010 +static struct clk abdac0_sample_clk = {
2011 + .name = "sample_clk",
2012 + .dev = &abdac0_device.dev,
2013 + .mode = genclk_mode,
2014 + .get_rate = genclk_get_rate,
2015 + .set_rate = genclk_set_rate,
2016 + .set_parent = genclk_set_parent,
2017 + .index = 6,
2018 +};
2019 +
2020 +struct platform_device *__init
2021 +at32_add_device_abdac(unsigned int id)
2022 +{
2023 + struct platform_device *pdev;
2024 +
2025 + switch (id) {
2026 + case 0:
2027 + pdev = &abdac0_device;
2028 + select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
2029 + select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
2030 + select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
2031 + select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
2032 + break;
2033 + default:
2034 + return NULL;
2035 + }
2036 +
2037 + platform_device_register(pdev);
2038 + return pdev;
2039 +}
2040 +
2041 +/* --------------------------------------------------------------------
2042 * GCLK
2043 * -------------------------------------------------------------------- */
2044 static struct clk gclk0 = {
2045 @@ -1066,7 +1449,7 @@
2046 &hsb_clk,
2047 &pba_clk,
2048 &pbb_clk,
2049 - &at32_sm_pclk,
2050 + &at32_pm_pclk,
2051 &at32_intc0_pclk,
2052 &hmatrix_clk,
2053 &ebi_clk,
2054 @@ -1075,6 +1458,7 @@
2055 &smc0_mck,
2056 &pdc_hclk,
2057 &pdc_pclk,
2058 + &dmaca0_hclk,
2059 &pico_clk,
2060 &pio0_mck,
2061 &pio1_mck,
2062 @@ -1092,8 +1476,18 @@
2063 &macb1_pclk,
2064 &atmel_spi0_spi_clk,
2065 &atmel_spi1_spi_clk,
2066 + &atmel_twi0_pclk,
2067 + &atmel_mci0_mci_clk,
2068 &atmel_lcdfb0_hck1,
2069 &atmel_lcdfb0_pixclk,
2070 + &usba0_pclk,
2071 + &usba0_hclk,
2072 + &ssc0_pclk,
2073 + &ssc1_pclk,
2074 + &ssc2_pclk,
2075 + &atmel_ac97c0_pclk,
2076 + &abdac0_pclk,
2077 + &abdac0_sample_clk,
2078 &gclk0,
2079 &gclk1,
2080 &gclk2,
2081 @@ -1113,18 +1507,20 @@
2082
2083 void __init at32_clock_init(void)
2084 {
2085 - struct at32_sm *sm = &system_manager;
2086 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2087 int i;
2088
2089 - if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
2090 + if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2091 main_clock = &pll0;
2092 - else
2093 + cpu_clk.parent = &pll0;
2094 + } else {
2095 main_clock = &osc0;
2096 + cpu_clk.parent = &osc0;
2097 + }
2098
2099 - if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
2100 + if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2101 pll0.parent = &osc1;
2102 - if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
2103 + if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2104 pll1.parent = &osc1;
2105
2106 genclk_init_parent(&gclk0);
2107 @@ -1133,6 +1529,7 @@
2108 genclk_init_parent(&gclk3);
2109 genclk_init_parent(&gclk4);
2110 genclk_init_parent(&atmel_lcdfb0_pixclk);
2111 + genclk_init_parent(&abdac0_sample_clk);
2112
2113 /*
2114 * Turn on all clocks that have at least one user already, and
2115 @@ -1157,8 +1554,8 @@
2116 pbb_mask |= 1 << clk->index;
2117 }
2118
2119 - sm_writel(sm, PM_CPU_MASK, cpu_mask);
2120 - sm_writel(sm, PM_HSB_MASK, hsb_mask);
2121 - sm_writel(sm, PM_PBA_MASK, pba_mask);
2122 - sm_writel(sm, PM_PBB_MASK, pbb_mask);
2123 + pm_writel(CPU_MASK, cpu_mask);
2124 + pm_writel(HSB_MASK, hsb_mask);
2125 + pm_writel(PBA_MASK, pba_mask);
2126 + pm_writel(PBB_MASK, pbb_mask);
2127 }
2128 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap.c linux-avr32.git/arch/avr32/mach-at32ap/at32ap.c
2129 --- linux-2.6.22.1/arch/avr32/mach-at32ap/at32ap.c 2007-07-10 20:56:30.000000000 +0200
2130 +++ linux-avr32.git/arch/avr32/mach-at32ap/at32ap.c 2007-07-12 13:59:49.000000000 +0200
2131 @@ -11,41 +11,10 @@
2132 #include <linux/init.h>
2133 #include <linux/platform_device.h>
2134
2135 -#include <asm/io.h>
2136 -
2137 #include <asm/arch/init.h>
2138 -#include <asm/arch/sm.h>
2139 -
2140 -struct at32_sm system_manager;
2141 -
2142 -static int __init at32_sm_init(void)
2143 -{
2144 - struct resource *regs;
2145 - struct at32_sm *sm = &system_manager;
2146 - int ret = -ENXIO;
2147 -
2148 - regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
2149 - if (!regs)
2150 - goto fail;
2151 -
2152 - spin_lock_init(&sm->lock);
2153 - sm->pdev = &at32_sm_device;
2154 -
2155 - ret = -ENOMEM;
2156 - sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
2157 - if (!sm->regs)
2158 - goto fail;
2159 -
2160 - return 0;
2161 -
2162 -fail:
2163 - printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
2164 - return ret;
2165 -}
2166
2167 void __init setup_platform(void)
2168 {
2169 - at32_sm_init();
2170 at32_clock_init();
2171 at32_portmux_init();
2172 }
2173 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/cpufreq.c linux-avr32.git/arch/avr32/mach-at32ap/cpufreq.c
2174 --- linux-2.6.22.1/arch/avr32/mach-at32ap/cpufreq.c 1970-01-01 01:00:00.000000000 +0100
2175 +++ linux-avr32.git/arch/avr32/mach-at32ap/cpufreq.c 2007-07-12 13:59:49.000000000 +0200
2176 @@ -0,0 +1,112 @@
2177 +/*
2178 + * Copyright (C) 2004-2007 Atmel Corporation
2179 + *
2180 + * Based on MIPS implementation arch/mips/kernel/time.c
2181 + * Copyright 2001 MontaVista Software Inc.
2182 + *
2183 + * This program is free software; you can redistribute it and/or modify
2184 + * it under the terms of the GNU General Public License version 2 as
2185 + * published by the Free Software Foundation.
2186 + */
2187 +
2188 +/*#define DEBUG*/
2189 +
2190 +#include <linux/kernel.h>
2191 +#include <linux/types.h>
2192 +#include <linux/init.h>
2193 +#include <linux/cpufreq.h>
2194 +#include <linux/io.h>
2195 +#include <linux/clk.h>
2196 +#include <linux/err.h>
2197 +#include <asm/system.h>
2198 +
2199 +static struct clk *cpuclk;
2200 +
2201 +static int at32_verify_speed(struct cpufreq_policy *policy)
2202 +{
2203 + if (policy->cpu != 0)
2204 + return -EINVAL;
2205 +
2206 + cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2207 + policy->cpuinfo.max_freq);
2208 + return 0;
2209 +}
2210 +
2211 +static unsigned int at32_get_speed(unsigned int cpu)
2212 +{
2213 + /* No SMP support */
2214 + if (cpu)
2215 + return 0;
2216 + return (unsigned int)((clk_get_rate(cpuclk) + 500) / 1000);
2217 +}
2218 +
2219 +static int at32_set_target(struct cpufreq_policy *policy,
2220 + unsigned int target_freq,
2221 + unsigned int relation)
2222 +{
2223 + struct cpufreq_freqs freqs;
2224 + long freq;
2225 +
2226 + /* Convert target_freq from kHz to Hz */
2227 + freq = clk_round_rate(cpuclk, target_freq * 1000);
2228 +
2229 + /* Check if policy->min <= new_freq <= policy->max */
2230 + if(freq < (policy->min * 1000) || freq > (policy->max * 1000))
2231 + return -EINVAL;
2232 +
2233 + pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
2234 +
2235 + freqs.old = at32_get_speed(0);
2236 + freqs.new = (freq + 500) / 1000;
2237 + freqs.cpu = 0;
2238 + freqs.flags = 0;
2239 +
2240 + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
2241 + clk_set_rate(cpuclk, freq);
2242 + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
2243 +
2244 + pr_debug("cpufreq: set frequency %lu Hz\n", freq);
2245 +
2246 + return 0;
2247 +}
2248 +
2249 +static int __init at32_cpufreq_driver_init(struct cpufreq_policy *policy)
2250 +{
2251 + if (policy->cpu != 0)
2252 + return -EINVAL;
2253 +
2254 + cpuclk = clk_get(NULL, "cpu");
2255 + if (IS_ERR(cpuclk)) {
2256 + pr_debug("cpufreq: could not get CPU clk\n");
2257 + return PTR_ERR(cpuclk);
2258 + }
2259 +
2260 + policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000;
2261 + policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
2262 + policy->cpuinfo.transition_latency = 0;
2263 + policy->cur = at32_get_speed(0);
2264 + policy->min = policy->cpuinfo.min_freq;
2265 + policy->max = policy->cpuinfo.max_freq;
2266 + policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
2267 +
2268 + printk("cpufreq: AT32AP CPU frequency driver\n");
2269 +
2270 + return 0;
2271 +}
2272 +
2273 +static struct cpufreq_driver at32_driver = {
2274 + .name = "at32ap",
2275 + .owner = THIS_MODULE,
2276 + .init = at32_cpufreq_driver_init,
2277 + .verify = at32_verify_speed,
2278 + .target = at32_set_target,
2279 + .get = at32_get_speed,
2280 + .flags = CPUFREQ_STICKY,
2281 +};
2282 +
2283 +static int __init at32_cpufreq_init(void)
2284 +{
2285 + return cpufreq_register_driver(&at32_driver);
2286 +}
2287 +
2288 +arch_initcall(at32_cpufreq_init);
2289 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/extint.c linux-avr32.git/arch/avr32/mach-at32ap/extint.c
2290 --- linux-2.6.22.1/arch/avr32/mach-at32ap/extint.c 2007-07-10 20:56:30.000000000 +0200
2291 +++ linux-avr32.git/arch/avr32/mach-at32ap/extint.c 2007-07-12 13:59:49.000000000 +0200
2292 @@ -17,42 +17,83 @@
2293
2294 #include <asm/io.h>
2295
2296 -#include <asm/arch/sm.h>
2297 -
2298 -#include "sm.h"
2299 +/* EIC register offsets */
2300 +#define EIC_IER 0x0000
2301 +#define EIC_IDR 0x0004
2302 +#define EIC_IMR 0x0008
2303 +#define EIC_ISR 0x000c
2304 +#define EIC_ICR 0x0010
2305 +#define EIC_MODE 0x0014
2306 +#define EIC_EDGE 0x0018
2307 +#define EIC_LEVEL 0x001c
2308 +#define EIC_TEST 0x0020
2309 +#define EIC_NMIC 0x0024
2310 +
2311 +/* Bitfields in TEST */
2312 +#define EIC_TESTEN_OFFSET 31
2313 +#define EIC_TESTEN_SIZE 1
2314 +
2315 +/* Bitfields in NMIC */
2316 +#define EIC_EN_OFFSET 0
2317 +#define EIC_EN_SIZE 1
2318 +
2319 +/* Bit manipulation macros */
2320 +#define EIC_BIT(name) \
2321 + (1 << EIC_##name##_OFFSET)
2322 +#define EIC_BF(name,value) \
2323 + (((value) & ((1 << EIC_##name##_SIZE) - 1)) \
2324 + << EIC_##name##_OFFSET)
2325 +#define EIC_BFEXT(name,value) \
2326 + (((value) >> EIC_##name##_OFFSET) \
2327 + & ((1 << EIC_##name##_SIZE) - 1))
2328 +#define EIC_BFINS(name,value,old) \
2329 + (((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
2330 + << EIC_##name##_OFFSET)) \
2331 + | EIC_BF(name,value))
2332 +
2333 +/* Register access macros */
2334 +#define eic_readl(port,reg) \
2335 + __raw_readl((port)->regs + EIC_##reg)
2336 +#define eic_writel(port,reg,value) \
2337 + __raw_writel((value), (port)->regs + EIC_##reg)
2338 +
2339 +struct eic {
2340 + void __iomem *regs;
2341 + struct irq_chip *chip;
2342 + unsigned int first_irq;
2343 +};
2344
2345 -static void eim_ack_irq(unsigned int irq)
2346 +static void eic_ack_irq(unsigned int irq)
2347 {
2348 - struct at32_sm *sm = get_irq_chip_data(irq);
2349 - sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
2350 + struct eic *eic = get_irq_chip_data(irq);
2351 + eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
2352 }
2353
2354 -static void eim_mask_irq(unsigned int irq)
2355 +static void eic_mask_irq(unsigned int irq)
2356 {
2357 - struct at32_sm *sm = get_irq_chip_data(irq);
2358 - sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
2359 + struct eic *eic = get_irq_chip_data(irq);
2360 + eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
2361 }
2362
2363 -static void eim_mask_ack_irq(unsigned int irq)
2364 +static void eic_mask_ack_irq(unsigned int irq)
2365 {
2366 - struct at32_sm *sm = get_irq_chip_data(irq);
2367 - sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
2368 - sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
2369 + struct eic *eic = get_irq_chip_data(irq);
2370 + eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
2371 + eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
2372 }
2373
2374 -static void eim_unmask_irq(unsigned int irq)
2375 +static void eic_unmask_irq(unsigned int irq)
2376 {
2377 - struct at32_sm *sm = get_irq_chip_data(irq);
2378 - sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
2379 + struct eic *eic = get_irq_chip_data(irq);
2380 + eic_writel(eic, IER, 1 << (irq - eic->first_irq));
2381 }
2382
2383 -static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
2384 +static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
2385 {
2386 - struct at32_sm *sm = get_irq_chip_data(irq);
2387 + struct eic *eic = get_irq_chip_data(irq);
2388 struct irq_desc *desc;
2389 - unsigned int i = irq - sm->eim_first_irq;
2390 + unsigned int i = irq - eic->first_irq;
2391 u32 mode, edge, level;
2392 - unsigned long flags;
2393 int ret = 0;
2394
2395 flow_type &= IRQ_TYPE_SENSE_MASK;
2396 @@ -60,11 +101,10 @@
2397 flow_type = IRQ_TYPE_LEVEL_LOW;
2398
2399 desc = &irq_desc[irq];
2400 - spin_lock_irqsave(&sm->lock, flags);
2401
2402 - mode = sm_readl(sm, EIM_MODE);
2403 - edge = sm_readl(sm, EIM_EDGE);
2404 - level = sm_readl(sm, EIM_LEVEL);
2405 + mode = eic_readl(eic, MODE);
2406 + edge = eic_readl(eic, EDGE);
2407 + level = eic_readl(eic, LEVEL);
2408
2409 switch (flow_type) {
2410 case IRQ_TYPE_LEVEL_LOW:
2411 @@ -89,9 +129,9 @@
2412 }
2413
2414 if (ret == 0) {
2415 - sm_writel(sm, EIM_MODE, mode);
2416 - sm_writel(sm, EIM_EDGE, edge);
2417 - sm_writel(sm, EIM_LEVEL, level);
2418 + eic_writel(eic, MODE, mode);
2419 + eic_writel(eic, EDGE, edge);
2420 + eic_writel(eic, LEVEL, level);
2421
2422 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
2423 flow_type |= IRQ_LEVEL;
2424 @@ -99,35 +139,33 @@
2425 desc->status |= flow_type;
2426 }
2427
2428 - spin_unlock_irqrestore(&sm->lock, flags);
2429 -
2430 return ret;
2431 }
2432
2433 -struct irq_chip eim_chip = {
2434 - .name = "eim",
2435 - .ack = eim_ack_irq,
2436 - .mask = eim_mask_irq,
2437 - .mask_ack = eim_mask_ack_irq,
2438 - .unmask = eim_unmask_irq,
2439 - .set_type = eim_set_irq_type,
2440 +struct irq_chip eic_chip = {
2441 + .name = "eic",
2442 + .ack = eic_ack_irq,
2443 + .mask = eic_mask_irq,
2444 + .mask_ack = eic_mask_ack_irq,
2445 + .unmask = eic_unmask_irq,
2446 + .set_type = eic_set_irq_type,
2447 };
2448
2449 -static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
2450 +static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
2451 {
2452 - struct at32_sm *sm = desc->handler_data;
2453 + struct eic *eic = desc->handler_data;
2454 struct irq_desc *ext_desc;
2455 unsigned long status, pending;
2456 unsigned int i, ext_irq;
2457
2458 - status = sm_readl(sm, EIM_ISR);
2459 - pending = status & sm_readl(sm, EIM_IMR);
2460 + status = eic_readl(eic, ISR);
2461 + pending = status & eic_readl(eic, IMR);
2462
2463 while (pending) {
2464 i = fls(pending) - 1;
2465 pending &= ~(1 << i);
2466
2467 - ext_irq = i + sm->eim_first_irq;
2468 + ext_irq = i + eic->first_irq;
2469 ext_desc = irq_desc + ext_irq;
2470 if (ext_desc->status & IRQ_LEVEL)
2471 handle_level_irq(ext_irq, ext_desc);
2472 @@ -136,51 +174,85 @@
2473 }
2474 }
2475
2476 -static int __init eim_init(void)
2477 +static int __init eic_probe(struct platform_device *pdev)
2478 {
2479 - struct at32_sm *sm = &system_manager;
2480 + struct eic *eic;
2481 + struct resource *regs;
2482 unsigned int i;
2483 unsigned int nr_irqs;
2484 unsigned int int_irq;
2485 + int ret;
2486 u32 pattern;
2487
2488 - /*
2489 - * The EIM is really the same module as SM, so register
2490 - * mapping, etc. has been taken care of already.
2491 - */
2492 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2493 + int_irq = platform_get_irq(pdev, 0);
2494 + if (!regs || !int_irq) {
2495 + dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
2496 + return -ENXIO;
2497 + }
2498 +
2499 + ret = -ENOMEM;
2500 + eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
2501 + if (!eic) {
2502 + dev_dbg(&pdev->dev, "no memory for eic structure\n");
2503 + goto err_kzalloc;
2504 + }
2505 +
2506 + eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
2507 + eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
2508 + if (!eic->regs) {
2509 + dev_dbg(&pdev->dev, "failed to map regs\n");
2510 + goto err_ioremap;
2511 + }
2512
2513 /*
2514 * Find out how many interrupt lines that are actually
2515 * implemented in hardware.
2516 */
2517 - sm_writel(sm, EIM_IDR, ~0UL);
2518 - sm_writel(sm, EIM_MODE, ~0UL);
2519 - pattern = sm_readl(sm, EIM_MODE);
2520 + eic_writel(eic, IDR, ~0UL);
2521 + eic_writel(eic, MODE, ~0UL);
2522 + pattern = eic_readl(eic, MODE);
2523 nr_irqs = fls(pattern);
2524
2525 /* Trigger on falling edge unless overridden by driver */
2526 - sm_writel(sm, EIM_MODE, 0UL);
2527 - sm_writel(sm, EIM_EDGE, 0UL);
2528 + eic_writel(eic, MODE, 0UL);
2529 + eic_writel(eic, EDGE, 0UL);
2530
2531 - sm->eim_chip = &eim_chip;
2532 + eic->chip = &eic_chip;
2533
2534 for (i = 0; i < nr_irqs; i++) {
2535 /* NOTE the handler we set here is ignored by the demux */
2536 - set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
2537 + set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
2538 handle_level_irq);
2539 - set_irq_chip_data(sm->eim_first_irq + i, sm);
2540 + set_irq_chip_data(eic->first_irq + i, eic);
2541 }
2542
2543 - int_irq = platform_get_irq_byname(sm->pdev, "eim");
2544 -
2545 - set_irq_chained_handler(int_irq, demux_eim_irq);
2546 - set_irq_data(int_irq, sm);
2547 + set_irq_chained_handler(int_irq, demux_eic_irq);
2548 + set_irq_data(int_irq, eic);
2549
2550 - printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
2551 - sm->regs, int_irq);
2552 - printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
2553 - nr_irqs, sm->eim_first_irq);
2554 + dev_info(&pdev->dev,
2555 + "External Interrupt Controller at 0x%p, IRQ %u\n",
2556 + eic->regs, int_irq);
2557 + dev_info(&pdev->dev,
2558 + "Handling %u external IRQs, starting with IRQ %u\n",
2559 + nr_irqs, eic->first_irq);
2560
2561 return 0;
2562 +
2563 +err_ioremap:
2564 + kfree(eic);
2565 +err_kzalloc:
2566 + return ret;
2567 +}
2568 +
2569 +static struct platform_driver eic_driver = {
2570 + .driver = {
2571 + .name = "at32_eic",
2572 + },
2573 +};
2574 +
2575 +static int __init eic_init(void)
2576 +{
2577 + return platform_driver_probe(&eic_driver, eic_probe);
2578 }
2579 -arch_initcall(eim_init);
2580 +arch_initcall(eic_init);
2581 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/gpio-dev.c linux-avr32.git/arch/avr32/mach-at32ap/gpio-dev.c
2582 --- linux-2.6.22.1/arch/avr32/mach-at32ap/gpio-dev.c 1970-01-01 01:00:00.000000000 +0100
2583 +++ linux-avr32.git/arch/avr32/mach-at32ap/gpio-dev.c 2007-07-12 13:59:49.000000000 +0200
2584 @@ -0,0 +1,570 @@
2585 +/*
2586 + * GPIO /dev and configfs interface
2587 + *
2588 + * Copyright (C) 2006-2007 Atmel Corporation
2589 + *
2590 + * This program is free software; you can redistribute it and/or modify
2591 + * it under the terms of the GNU General Public License version 2 as
2592 + * published by the Free Software Foundation.
2593 + */
2594 +#include <linux/configfs.h>
2595 +#include <linux/cdev.h>
2596 +#include <linux/fs.h>
2597 +#include <linux/interrupt.h>
2598 +#include <linux/poll.h>
2599 +#include <linux/uaccess.h>
2600 +#include <linux/wait.h>
2601 +
2602 +#include <asm/gpio.h>
2603 +#include <asm/arch/portmux.h>
2604 +
2605 +#define GPIO_DEV_MAX 8
2606 +
2607 +static struct class *gpio_dev_class;
2608 +static dev_t gpio_devt;
2609 +
2610 +struct gpio_item {
2611 + spinlock_t lock;
2612 +
2613 + int enabled;
2614 + int initialized;
2615 + int port;
2616 + u32 pin_mask;
2617 + u32 oe_mask;
2618 +
2619 + /* Pin state last time we read it (for blocking reads) */
2620 + u32 pin_state;
2621 + int changed;
2622 +
2623 + wait_queue_head_t change_wq;
2624 + struct fasync_struct *async_queue;
2625 +
2626 + int id;
2627 + struct class_device *gpio_dev;
2628 + struct cdev char_dev;
2629 + struct config_item item;
2630 +};
2631 +
2632 +struct gpio_attribute {
2633 + struct configfs_attribute attr;
2634 + ssize_t (*show)(struct gpio_item *, char *);
2635 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
2636 +};
2637 +
2638 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
2639 +{
2640 + struct gpio_item *gpio = dev_id;
2641 + u32 old_state, new_state;
2642 +
2643 + old_state = gpio->pin_state;
2644 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
2645 + gpio->pin_state = new_state;
2646 +
2647 + if (new_state != old_state) {
2648 + gpio->changed = 1;
2649 + wake_up_interruptible(&gpio->change_wq);
2650 +
2651 + if (gpio->async_queue)
2652 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
2653 + }
2654 +
2655 + return IRQ_HANDLED;
2656 +}
2657 +
2658 +static int gpio_dev_open(struct inode *inode, struct file *file)
2659 +{
2660 + struct gpio_item *gpio = container_of(inode->i_cdev,
2661 + struct gpio_item,
2662 + char_dev);
2663 + unsigned int irq;
2664 + unsigned int i;
2665 + int ret;
2666 +
2667 + nonseekable_open(inode, file);
2668 + config_item_get(&gpio->item);
2669 + file->private_data = gpio;
2670 +
2671 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
2672 + gpio->pin_mask);
2673 + gpio->changed = 1;
2674 +
2675 + for (i = 0; i < 32; i++) {
2676 + if (gpio->pin_mask & (1 << i)) {
2677 + irq = gpio_to_irq(32 * gpio->port + i);
2678 + ret = request_irq(irq, gpio_dev_interrupt, 0,
2679 + "gpio-dev", gpio);
2680 + if (ret)
2681 + goto err_irq;
2682 + }
2683 + }
2684 +
2685 + return 0;
2686 +
2687 +err_irq:
2688 + while (i--) {
2689 + if (gpio->pin_mask & (1 << i)) {
2690 + irq = gpio_to_irq(32 * gpio->port + i);
2691 + free_irq(irq, gpio);
2692 + }
2693 + }
2694 +
2695 + config_item_put(&gpio->item);
2696 +
2697 + return ret;
2698 +}
2699 +
2700 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
2701 +{
2702 + struct gpio_item *gpio = file->private_data;
2703 +
2704 + return fasync_helper(fd, file, mode, &gpio->async_queue);
2705 +}
2706 +
2707 +static int gpio_dev_release(struct inode *inode, struct file *file)
2708 +{
2709 + struct gpio_item *gpio = file->private_data;
2710 + unsigned int irq;
2711 + unsigned int i;
2712 +
2713 + gpio_dev_fasync(-1, file, 0);
2714 +
2715 + for (i = 0; i < 32; i++) {
2716 + if (gpio->pin_mask & (1 << i)) {
2717 + irq = gpio_to_irq(32 * gpio->port + i);
2718 + free_irq(irq, gpio);
2719 + }
2720 + }
2721 +
2722 + config_item_put(&gpio->item);
2723 +
2724 + return 0;
2725 +}
2726 +
2727 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
2728 +{
2729 + struct gpio_item *gpio = file->private_data;
2730 + unsigned int mask = 0;
2731 +
2732 + poll_wait(file, &gpio->change_wq, wait);
2733 + if (gpio->changed)
2734 + mask |= POLLIN | POLLRDNORM;
2735 +
2736 + return mask;
2737 +}
2738 +
2739 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
2740 + size_t count, loff_t *offset)
2741 +{
2742 + struct gpio_item *gpio = file->private_data;
2743 + u32 value;
2744 +
2745 + spin_lock_irq(&gpio->lock);
2746 + while (!gpio->changed) {
2747 + spin_unlock_irq(&gpio->lock);
2748 +
2749 + if (file->f_flags & O_NONBLOCK)
2750 + return -EAGAIN;
2751 +
2752 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
2753 + return -ERESTARTSYS;
2754 +
2755 + spin_lock_irq(&gpio->lock);
2756 + }
2757 +
2758 + gpio->changed = 0;
2759 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
2760 +
2761 + spin_unlock_irq(&gpio->lock);
2762 +
2763 + count = min(count, (size_t)4);
2764 + if (copy_to_user(buf, &value, count))
2765 + return -EFAULT;
2766 +
2767 + return count;
2768 +}
2769 +
2770 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
2771 + size_t count, loff_t *offset)
2772 +{
2773 + struct gpio_item *gpio = file->private_data;
2774 + u32 value = 0;
2775 + u32 mask = ~0UL;
2776 +
2777 + count = min(count, (size_t)4);
2778 + if (copy_from_user(&value, buf, count))
2779 + return -EFAULT;
2780 +
2781 + /* Assuming big endian */
2782 + mask <<= (4 - count) * 8;
2783 + mask &= gpio->pin_mask;
2784 +
2785 + at32_gpio_set_value_multiple(gpio->port, value, mask);
2786 +
2787 + return count;
2788 +}
2789 +
2790 +static struct file_operations gpio_dev_fops = {
2791 + .owner = THIS_MODULE,
2792 + .llseek = no_llseek,
2793 + .open = gpio_dev_open,
2794 + .release = gpio_dev_release,
2795 + .fasync = gpio_dev_fasync,
2796 + .poll = gpio_dev_poll,
2797 + .read = gpio_dev_read,
2798 + .write = gpio_dev_write,
2799 +};
2800 +
2801 +static struct gpio_item *to_gpio_item(struct config_item *item)
2802 +{
2803 + return item ? container_of(item, struct gpio_item, item) : NULL;
2804 +}
2805 +
2806 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
2807 +{
2808 + return sprintf(page, "%d\n", gpio->port);
2809 +}
2810 +
2811 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
2812 + const char *page, size_t count)
2813 +{
2814 + unsigned long id;
2815 + char *p = (char *)page;
2816 + ssize_t ret = -EINVAL;
2817 +
2818 + id = simple_strtoul(p, &p, 0);
2819 + if (!p || (*p && (*p != '\n')))
2820 + return -EINVAL;
2821 +
2822 + /* Switching PIO is not allowed when live... */
2823 + spin_lock(&gpio->lock);
2824 + if (!gpio->enabled) {
2825 + ret = -ENXIO;
2826 + if (at32_gpio_port_is_valid(id)) {
2827 + gpio->port = id;
2828 + ret = count;
2829 + }
2830 + }
2831 + spin_unlock(&gpio->lock);
2832 +
2833 + return ret;
2834 +}
2835 +
2836 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
2837 +{
2838 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
2839 +}
2840 +
2841 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
2842 + const char *page, size_t count)
2843 +{
2844 + u32 new_mask;
2845 + char *p = (char *)page;
2846 + ssize_t ret = -EINVAL;
2847 +
2848 + new_mask = simple_strtoul(p, &p, 0);
2849 + if (!p || (*p && (*p != '\n')))
2850 + return -EINVAL;
2851 +
2852 + /* Can't update the pin mask while live. */
2853 + spin_lock(&gpio->lock);
2854 + if (!gpio->enabled) {
2855 + gpio->oe_mask &= new_mask;
2856 + gpio->pin_mask = new_mask;
2857 + ret = count;
2858 + }
2859 + spin_unlock(&gpio->lock);
2860 +
2861 + return ret;
2862 +}
2863 +
2864 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
2865 +{
2866 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
2867 +}
2868 +
2869 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
2870 + const char *page, size_t count)
2871 +{
2872 + u32 mask;
2873 + char *p = (char *)page;
2874 + ssize_t ret = -EINVAL;
2875 +
2876 + mask = simple_strtoul(p, &p, 0);
2877 + if (!p || (*p && (*p != '\n')))
2878 + return -EINVAL;
2879 +
2880 + spin_lock(&gpio->lock);
2881 + if (!gpio->enabled) {
2882 + gpio->oe_mask = mask & gpio->pin_mask;
2883 + ret = count;
2884 + }
2885 + spin_unlock(&gpio->lock);
2886 +
2887 + return ret;
2888 +}
2889 +
2890 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
2891 +{
2892 + return sprintf(page, "%d\n", gpio->enabled);
2893 +}
2894 +
2895 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
2896 + const char *page, size_t count)
2897 +{
2898 + char *p = (char *)page;
2899 + int enabled;
2900 + int ret;
2901 +
2902 + enabled = simple_strtoul(p, &p, 0);
2903 + if (!p || (*p && (*p != '\n')))
2904 + return -EINVAL;
2905 +
2906 + /* make it a boolean value */
2907 + enabled = !!enabled;
2908 +
2909 + if (gpio->enabled == enabled)
2910 + /* No change; do nothing. */
2911 + return count;
2912 +
2913 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
2914 +
2915 + if (!enabled) {
2916 + class_device_unregister(gpio->gpio_dev);
2917 + cdev_del(&gpio->char_dev);
2918 + at32_deselect_pins(gpio->port, gpio->pin_mask);
2919 + gpio->initialized = 0;
2920 + } else {
2921 + if (gpio->port < 0 || !gpio->pin_mask)
2922 + return -ENODEV;
2923 + }
2924 +
2925 + /* Disallow any updates to gpio_id or pin_mask */
2926 + spin_lock(&gpio->lock);
2927 + gpio->enabled = enabled;
2928 + spin_unlock(&gpio->lock);
2929 +
2930 + if (!enabled)
2931 + return count;
2932 +
2933 + /* Now, try to allocate the pins */
2934 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
2935 + if (ret)
2936 + goto err_alloc_pins;
2937 +
2938 + gpio->initialized = 1;
2939 +
2940 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
2941 + gpio->char_dev.owner = THIS_MODULE;
2942 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
2943 + if (ret < 0)
2944 + goto err_cdev_add;
2945 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
2946 + MKDEV(MAJOR(gpio_devt), gpio->id),
2947 + NULL,
2948 + "gpio%d", gpio->id);
2949 + if (IS_ERR(gpio->gpio_dev)) {
2950 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
2951 + ret = PTR_ERR(gpio->gpio_dev);
2952 + goto err_class_dev;
2953 + }
2954 +
2955 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
2956 + gpio->id, gpio->port, gpio->pin_mask,
2957 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
2958 +
2959 + return 0;
2960 +
2961 +err_class_dev:
2962 + cdev_del(&gpio->char_dev);
2963 +err_cdev_add:
2964 + at32_deselect_pins(gpio->port, gpio->pin_mask);
2965 + gpio->initialized = 0;
2966 +err_alloc_pins:
2967 + spin_lock(&gpio->lock);
2968 + gpio->enabled = 0;
2969 + spin_unlock(&gpio->lock);
2970 +
2971 + return ret;
2972 +}
2973 +
2974 +static struct gpio_attribute gpio_item_attr_gpio_id = {
2975 + .attr = {
2976 + .ca_owner = THIS_MODULE,
2977 + .ca_name = "gpio_id",
2978 + .ca_mode = S_IRUGO | S_IWUSR,
2979 + },
2980 + .show = gpio_show_gpio_id,
2981 + .store = gpio_store_gpio_id,
2982 +};
2983 +static struct gpio_attribute gpio_item_attr_pin_mask = {
2984 + .attr = {
2985 + .ca_owner = THIS_MODULE,
2986 + .ca_name = "pin_mask",
2987 + .ca_mode = S_IRUGO | S_IWUSR,
2988 + },
2989 + .show = gpio_show_pin_mask,
2990 + .store = gpio_store_pin_mask,
2991 +};
2992 +static struct gpio_attribute gpio_item_attr_oe_mask = {
2993 + .attr = {
2994 + .ca_owner = THIS_MODULE,
2995 + .ca_name = "oe_mask",
2996 + .ca_mode = S_IRUGO | S_IWUSR,
2997 + },
2998 + .show = gpio_show_oe_mask,
2999 + .store = gpio_store_oe_mask,
3000 +};
3001 +static struct gpio_attribute gpio_item_attr_enabled = {
3002 + .attr = {
3003 + .ca_owner = THIS_MODULE,
3004 + .ca_name = "enabled",
3005 + .ca_mode = S_IRUGO | S_IWUSR,
3006 + },
3007 + .show = gpio_show_enabled,
3008 + .store = gpio_store_enabled,
3009 +};
3010 +
3011 +static struct configfs_attribute *gpio_item_attrs[] = {
3012 + &gpio_item_attr_gpio_id.attr,
3013 + &gpio_item_attr_pin_mask.attr,
3014 + &gpio_item_attr_oe_mask.attr,
3015 + &gpio_item_attr_enabled.attr,
3016 + NULL,
3017 +};
3018 +
3019 +static ssize_t gpio_show_attr(struct config_item *item,
3020 + struct configfs_attribute *attr,
3021 + char *page)
3022 +{
3023 + struct gpio_item *gpio_item = to_gpio_item(item);
3024 + struct gpio_attribute *gpio_attr
3025 + = container_of(attr, struct gpio_attribute, attr);
3026 + ssize_t ret = 0;
3027 +
3028 + if (gpio_attr->show)
3029 + ret = gpio_attr->show(gpio_item, page);
3030 + return ret;
3031 +}
3032 +
3033 +static ssize_t gpio_store_attr(struct config_item *item,
3034 + struct configfs_attribute *attr,
3035 + const char *page, size_t count)
3036 +{
3037 + struct gpio_item *gpio_item = to_gpio_item(item);
3038 + struct gpio_attribute *gpio_attr
3039 + = container_of(attr, struct gpio_attribute, attr);
3040 + ssize_t ret = -EINVAL;
3041 +
3042 + if (gpio_attr->store)
3043 + ret = gpio_attr->store(gpio_item, page, count);
3044 + return ret;
3045 +}
3046 +
3047 +static void gpio_release(struct config_item *item)
3048 +{
3049 + kfree(to_gpio_item(item));
3050 +}
3051 +
3052 +static struct configfs_item_operations gpio_item_ops = {
3053 + .release = gpio_release,
3054 + .show_attribute = gpio_show_attr,
3055 + .store_attribute = gpio_store_attr,
3056 +};
3057 +
3058 +static struct config_item_type gpio_item_type = {
3059 + .ct_item_ops = &gpio_item_ops,
3060 + .ct_attrs = gpio_item_attrs,
3061 + .ct_owner = THIS_MODULE,
3062 +};
3063 +
3064 +static struct config_item *gpio_make_item(struct config_group *group,
3065 + const char *name)
3066 +{
3067 + static int next_id;
3068 + struct gpio_item *gpio;
3069 +
3070 + if (next_id >= GPIO_DEV_MAX)
3071 + return NULL;
3072 +
3073 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
3074 + if (!gpio)
3075 + return NULL;
3076 +
3077 + gpio->id = next_id++;
3078 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
3079 + spin_lock_init(&gpio->lock);
3080 + init_waitqueue_head(&gpio->change_wq);
3081 +
3082 + return &gpio->item;
3083 +}
3084 +
3085 +static void gpio_drop_item(struct config_group *group,
3086 + struct config_item *item)
3087 +{
3088 + struct gpio_item *gpio = to_gpio_item(item);
3089 +
3090 + spin_lock(&gpio->lock);
3091 + if (gpio->enabled) {
3092 + class_device_unregister(gpio->gpio_dev);
3093 + cdev_del(&gpio->char_dev);
3094 + }
3095 +
3096 + if (gpio->initialized) {
3097 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3098 + gpio->initialized = 0;
3099 + gpio->enabled = 0;
3100 + }
3101 + spin_unlock(&gpio->lock);
3102 +}
3103 +
3104 +static struct configfs_group_operations gpio_group_ops = {
3105 + .make_item = gpio_make_item,
3106 + .drop_item = gpio_drop_item,
3107 +};
3108 +
3109 +static struct config_item_type gpio_group_type = {
3110 + .ct_group_ops = &gpio_group_ops,
3111 + .ct_owner = THIS_MODULE,
3112 +};
3113 +
3114 +static struct configfs_subsystem gpio_subsys = {
3115 + .su_group = {
3116 + .cg_item = {
3117 + .ci_namebuf = "gpio",
3118 + .ci_type = &gpio_group_type,
3119 + },
3120 + },
3121 +};
3122 +
3123 +static int __init gpio_dev_init(void)
3124 +{
3125 + int err;
3126 +
3127 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
3128 + if (IS_ERR(gpio_dev_class)) {
3129 + err = PTR_ERR(gpio_dev_class);
3130 + goto err_class_create;
3131 + }
3132 +
3133 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
3134 + if (err < 0)
3135 + goto err_alloc_chrdev;
3136 +
3137 + /* Configfs initialization */
3138 + config_group_init(&gpio_subsys.su_group);
3139 + init_MUTEX(&gpio_subsys.su_sem);
3140 + err = configfs_register_subsystem(&gpio_subsys);
3141 + if (err)
3142 + goto err_register_subsys;
3143 +
3144 + return 0;
3145 +
3146 +err_register_subsys:
3147 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
3148 +err_alloc_chrdev:
3149 + class_destroy(gpio_dev_class);
3150 +err_class_create:
3151 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
3152 + return err;
3153 +}
3154 +late_initcall(gpio_dev_init);
3155 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/Kconfig linux-avr32.git/arch/avr32/mach-at32ap/Kconfig
3156 --- linux-2.6.22.1/arch/avr32/mach-at32ap/Kconfig 2007-07-10 20:56:30.000000000 +0200
3157 +++ linux-avr32.git/arch/avr32/mach-at32ap/Kconfig 2007-07-12 13:59:49.000000000 +0200
3158 @@ -26,6 +26,13 @@
3159
3160 endchoice
3161
3162 +config GPIO_DEV
3163 + bool "GPIO /dev interface"
3164 + select CONFIGFS_FS
3165 + default n
3166 + help
3167 + Say `Y' to enable a /dev interface to the GPIO pins.
3168 +
3169 endmenu
3170
3171 endif # PLATFORM_AT32AP
3172 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/Makefile linux-avr32.git/arch/avr32/mach-at32ap/Makefile
3173 --- linux-2.6.22.1/arch/avr32/mach-at32ap/Makefile 2007-07-10 20:56:30.000000000 +0200
3174 +++ linux-avr32.git/arch/avr32/mach-at32ap/Makefile 2007-07-12 13:59:49.000000000 +0200
3175 @@ -1,3 +1,5 @@
3176 obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
3177 obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
3178 obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
3179 +obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
3180 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
3181 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/pio.c linux-avr32.git/arch/avr32/mach-at32ap/pio.c
3182 --- linux-2.6.22.1/arch/avr32/mach-at32ap/pio.c 2007-07-10 20:56:30.000000000 +0200
3183 +++ linux-avr32.git/arch/avr32/mach-at32ap/pio.c 2007-07-12 13:59:49.000000000 +0200
3184 @@ -158,6 +158,82 @@
3185 dump_stack();
3186 }
3187
3188 +#ifdef CONFIG_GPIO_DEV
3189 +
3190 +/* Gang allocators and accessors; used by the GPIO /dev driver */
3191 +int at32_gpio_port_is_valid(unsigned int port)
3192 +{
3193 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
3194 +}
3195 +
3196 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
3197 +{
3198 + struct pio_device *pio;
3199 + u32 old, new;
3200 +
3201 + pio = &pio_dev[port];
3202 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
3203 +
3204 + /* Try to allocate the pins */
3205 + do {
3206 + old = pio->pinmux_mask;
3207 + if (old & pins)
3208 + return -EBUSY;
3209 +
3210 + new = old | pins;
3211 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
3212 +
3213 + /* That went well, now configure the port */
3214 + pio_writel(pio, OER, oe_mask);
3215 + pio_writel(pio, PER, pins);
3216 +
3217 + return 0;
3218 +}
3219 +
3220 +void at32_deselect_pins(unsigned int port, u32 pins)
3221 +{
3222 + struct pio_device *pio;
3223 + u32 old, new;
3224 +
3225 + pio = &pio_dev[port];
3226 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3227 +
3228 + /* Return to a "safe" mux configuration */
3229 + pio_writel(pio, PUER, pins);
3230 + pio_writel(pio, ODR, pins);
3231 +
3232 + /* Deallocate the pins */
3233 + do {
3234 + old = pio->pinmux_mask;
3235 + new = old & ~pins;
3236 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
3237 +}
3238 +
3239 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
3240 +{
3241 + struct pio_device *pio;
3242 +
3243 + pio = &pio_dev[port];
3244 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3245 +
3246 + return pio_readl(pio, PDSR) & pins;
3247 +}
3248 +
3249 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
3250 +{
3251 + struct pio_device *pio;
3252 +
3253 + pio = &pio_dev[port];
3254 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3255 +
3256 + /* No atomic updates for now... */
3257 + pio_writel(pio, CODR, ~value & mask);
3258 + pio_writel(pio, SODR, value & mask);
3259 +}
3260 +
3261 +#endif /* CONFIG_GPIO_DEV */
3262 +
3263 +
3264 /*--------------------------------------------------------------------------*/
3265
3266 /* GPIO API */
3267 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/pm.h linux-avr32.git/arch/avr32/mach-at32ap/pm.h
3268 --- linux-2.6.22.1/arch/avr32/mach-at32ap/pm.h 1970-01-01 01:00:00.000000000 +0100
3269 +++ linux-avr32.git/arch/avr32/mach-at32ap/pm.h 2007-07-12 13:59:49.000000000 +0200
3270 @@ -0,0 +1,112 @@
3271 +/*
3272 + * Register definitions for the Power Manager (PM)
3273 + */
3274 +#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
3275 +#define __ARCH_AVR32_MACH_AT32AP_PM_H__
3276 +
3277 +/* PM register offsets */
3278 +#define PM_MCCTRL 0x0000
3279 +#define PM_CKSEL 0x0004
3280 +#define PM_CPU_MASK 0x0008
3281 +#define PM_HSB_MASK 0x000c
3282 +#define PM_PBA_MASK 0x0010
3283 +#define PM_PBB_MASK 0x0014
3284 +#define PM_PLL0 0x0020
3285 +#define PM_PLL1 0x0024
3286 +#define PM_IER 0x0040
3287 +#define PM_IDR 0x0044
3288 +#define PM_IMR 0x0048
3289 +#define PM_ISR 0x004c
3290 +#define PM_ICR 0x0050
3291 +#define PM_GCCTRL(x) (0x0060 + 4 * (x))
3292 +#define PM_RCAUSE 0x00c0
3293 +
3294 +/* Bitfields in CKSEL */
3295 +#define PM_CPUSEL_OFFSET 0
3296 +#define PM_CPUSEL_SIZE 3
3297 +#define PM_CPUDIV_OFFSET 7
3298 +#define PM_CPUDIV_SIZE 1
3299 +#define PM_HSBSEL_OFFSET 8
3300 +#define PM_HSBSEL_SIZE 3
3301 +#define PM_HSBDIV_OFFSET 15
3302 +#define PM_HSBDIV_SIZE 1
3303 +#define PM_PBASEL_OFFSET 16
3304 +#define PM_PBASEL_SIZE 3
3305 +#define PM_PBADIV_OFFSET 23
3306 +#define PM_PBADIV_SIZE 1
3307 +#define PM_PBBSEL_OFFSET 24
3308 +#define PM_PBBSEL_SIZE 3
3309 +#define PM_PBBDIV_OFFSET 31
3310 +#define PM_PBBDIV_SIZE 1
3311 +
3312 +/* Bitfields in PLL0 */
3313 +#define PM_PLLEN_OFFSET 0
3314 +#define PM_PLLEN_SIZE 1
3315 +#define PM_PLLOSC_OFFSET 1
3316 +#define PM_PLLOSC_SIZE 1
3317 +#define PM_PLLOPT_OFFSET 2
3318 +#define PM_PLLOPT_SIZE 3
3319 +#define PM_PLLDIV_OFFSET 8
3320 +#define PM_PLLDIV_SIZE 8
3321 +#define PM_PLLMUL_OFFSET 16
3322 +#define PM_PLLMUL_SIZE 8
3323 +#define PM_PLLCOUNT_OFFSET 24
3324 +#define PM_PLLCOUNT_SIZE 6
3325 +#define PM_PLLTEST_OFFSET 31
3326 +#define PM_PLLTEST_SIZE 1
3327 +
3328 +/* Bitfields in ICR */
3329 +#define PM_LOCK0_OFFSET 0
3330 +#define PM_LOCK0_SIZE 1
3331 +#define PM_LOCK1_OFFSET 1
3332 +#define PM_LOCK1_SIZE 1
3333 +#define PM_WAKE_OFFSET 2
3334 +#define PM_WAKE_SIZE 1
3335 +#define PM_CKRDY_OFFSET 5
3336 +#define PM_CKRDY_SIZE 1
3337 +#define PM_MSKRDY_OFFSET 6
3338 +#define PM_MSKRDY_SIZE 1
3339 +
3340 +/* Bitfields in GCCTRL0 */
3341 +#define PM_OSCSEL_OFFSET 0
3342 +#define PM_OSCSEL_SIZE 1
3343 +#define PM_PLLSEL_OFFSET 1
3344 +#define PM_PLLSEL_SIZE 1
3345 +#define PM_CEN_OFFSET 2
3346 +#define PM_CEN_SIZE 1
3347 +#define PM_DIVEN_OFFSET 4
3348 +#define PM_DIVEN_SIZE 1
3349 +#define PM_DIV_OFFSET 8
3350 +#define PM_DIV_SIZE 8
3351 +
3352 +/* Bitfields in RCAUSE */
3353 +#define PM_POR_OFFSET 0
3354 +#define PM_POR_SIZE 1
3355 +#define PM_EXT_OFFSET 2
3356 +#define PM_EXT_SIZE 1
3357 +#define PM_WDT_OFFSET 3
3358 +#define PM_WDT_SIZE 1
3359 +#define PM_NTAE_OFFSET 4
3360 +#define PM_NTAE_SIZE 1
3361 +
3362 +/* Bit manipulation macros */
3363 +#define PM_BIT(name) \
3364 + (1 << PM_##name##_OFFSET)
3365 +#define PM_BF(name,value) \
3366 + (((value) & ((1 << PM_##name##_SIZE) - 1)) \
3367 + << PM_##name##_OFFSET)
3368 +#define PM_BFEXT(name,value) \
3369 + (((value) >> PM_##name##_OFFSET) \
3370 + & ((1 << PM_##name##_SIZE) - 1))
3371 +#define PM_BFINS(name,value,old)\
3372 + (((old) & ~(((1 << PM_##name##_SIZE) - 1) \
3373 + << PM_##name##_OFFSET)) \
3374 + | PM_BF(name,value))
3375 +
3376 +/* Register access macros */
3377 +#define pm_readl(reg) \
3378 + __raw_readl((void __iomem *)AT32_PM_BASE + PM_##reg)
3379 +#define pm_writel(reg,value) \
3380 + __raw_writel((value), (void __iomem *)AT32_PM_BASE + PM_##reg)
3381 +
3382 +#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
3383 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mach-at32ap/sm.h linux-avr32.git/arch/avr32/mach-at32ap/sm.h
3384 --- linux-2.6.22.1/arch/avr32/mach-at32ap/sm.h 2007-07-10 20:56:30.000000000 +0200
3385 +++ linux-avr32.git/arch/avr32/mach-at32ap/sm.h 1970-01-01 01:00:00.000000000 +0100
3386 @@ -1,242 +0,0 @@
3387 -/*
3388 - * Register definitions for SM
3389 - *
3390 - * System Manager
3391 - */
3392 -#ifndef __ASM_AVR32_SM_H__
3393 -#define __ASM_AVR32_SM_H__
3394 -
3395 -/* SM register offsets */
3396 -#define SM_PM_MCCTRL 0x0000
3397 -#define SM_PM_CKSEL 0x0004
3398 -#define SM_PM_CPU_MASK 0x0008
3399 -#define SM_PM_HSB_MASK 0x000c
3400 -#define SM_PM_PBA_MASK 0x0010
3401 -#define SM_PM_PBB_MASK 0x0014
3402 -#define SM_PM_PLL0 0x0020
3403 -#define SM_PM_PLL1 0x0024
3404 -#define SM_PM_VCTRL 0x0030
3405 -#define SM_PM_VMREF 0x0034
3406 -#define SM_PM_VMV 0x0038
3407 -#define SM_PM_IER 0x0040
3408 -#define SM_PM_IDR 0x0044
3409 -#define SM_PM_IMR 0x0048
3410 -#define SM_PM_ISR 0x004c
3411 -#define SM_PM_ICR 0x0050
3412 -#define SM_PM_GCCTRL 0x0060
3413 -#define SM_RTC_CTRL 0x0080
3414 -#define SM_RTC_VAL 0x0084
3415 -#define SM_RTC_TOP 0x0088
3416 -#define SM_RTC_IER 0x0090
3417 -#define SM_RTC_IDR 0x0094
3418 -#define SM_RTC_IMR 0x0098
3419 -#define SM_RTC_ISR 0x009c
3420 -#define SM_RTC_ICR 0x00a0
3421 -#define SM_WDT_CTRL 0x00b0
3422 -#define SM_WDT_CLR 0x00b4
3423 -#define SM_WDT_EXT 0x00b8
3424 -#define SM_RC_RCAUSE 0x00c0
3425 -#define SM_EIM_IER 0x0100
3426 -#define SM_EIM_IDR 0x0104
3427 -#define SM_EIM_IMR 0x0108
3428 -#define SM_EIM_ISR 0x010c
3429 -#define SM_EIM_ICR 0x0110
3430 -#define SM_EIM_MODE 0x0114
3431 -#define SM_EIM_EDGE 0x0118
3432 -#define SM_EIM_LEVEL 0x011c
3433 -#define SM_EIM_TEST 0x0120
3434 -#define SM_EIM_NMIC 0x0124
3435 -
3436 -/* Bitfields in PM_MCCTRL */
3437 -
3438 -/* Bitfields in PM_CKSEL */
3439 -#define SM_CPUSEL_OFFSET 0
3440 -#define SM_CPUSEL_SIZE 3
3441 -#define SM_CPUDIV_OFFSET 7
3442 -#define SM_CPUDIV_SIZE 1
3443 -#define SM_HSBSEL_OFFSET 8
3444 -#define SM_HSBSEL_SIZE 3
3445 -#define SM_HSBDIV_OFFSET 15
3446 -#define SM_HSBDIV_SIZE 1
3447 -#define SM_PBASEL_OFFSET 16
3448 -#define SM_PBASEL_SIZE 3
3449 -#define SM_PBADIV_OFFSET 23
3450 -#define SM_PBADIV_SIZE 1
3451 -#define SM_PBBSEL_OFFSET 24
3452 -#define SM_PBBSEL_SIZE 3
3453 -#define SM_PBBDIV_OFFSET 31
3454 -#define SM_PBBDIV_SIZE 1
3455 -
3456 -/* Bitfields in PM_CPU_MASK */
3457 -
3458 -/* Bitfields in PM_HSB_MASK */
3459 -
3460 -/* Bitfields in PM_PBA_MASK */
3461 -
3462 -/* Bitfields in PM_PBB_MASK */
3463 -
3464 -/* Bitfields in PM_PLL0 */
3465 -#define SM_PLLEN_OFFSET 0
3466 -#define SM_PLLEN_SIZE 1
3467 -#define SM_PLLOSC_OFFSET 1
3468 -#define SM_PLLOSC_SIZE 1
3469 -#define SM_PLLOPT_OFFSET 2
3470 -#define SM_PLLOPT_SIZE 3
3471 -#define SM_PLLDIV_OFFSET 8
3472 -#define SM_PLLDIV_SIZE 8
3473 -#define SM_PLLMUL_OFFSET 16
3474 -#define SM_PLLMUL_SIZE 8
3475 -#define SM_PLLCOUNT_OFFSET 24
3476 -#define SM_PLLCOUNT_SIZE 6
3477 -#define SM_PLLTEST_OFFSET 31
3478 -#define SM_PLLTEST_SIZE 1
3479 -
3480 -/* Bitfields in PM_PLL1 */
3481 -
3482 -/* Bitfields in PM_VCTRL */
3483 -#define SM_VAUTO_OFFSET 0
3484 -#define SM_VAUTO_SIZE 1
3485 -#define SM_PM_VCTRL_VAL_OFFSET 8
3486 -#define SM_PM_VCTRL_VAL_SIZE 7
3487 -
3488 -/* Bitfields in PM_VMREF */
3489 -#define SM_REFSEL_OFFSET 0
3490 -#define SM_REFSEL_SIZE 4
3491 -
3492 -/* Bitfields in PM_VMV */
3493 -#define SM_PM_VMV_VAL_OFFSET 0
3494 -#define SM_PM_VMV_VAL_SIZE 8
3495 -
3496 -/* Bitfields in PM_IER */
3497 -
3498 -/* Bitfields in PM_IDR */
3499 -
3500 -/* Bitfields in PM_IMR */
3501 -
3502 -/* Bitfields in PM_ISR */
3503 -
3504 -/* Bitfields in PM_ICR */
3505 -#define SM_LOCK0_OFFSET 0
3506 -#define SM_LOCK0_SIZE 1
3507 -#define SM_LOCK1_OFFSET 1
3508 -#define SM_LOCK1_SIZE 1
3509 -#define SM_WAKE_OFFSET 2
3510 -#define SM_WAKE_SIZE 1
3511 -#define SM_VOK_OFFSET 3
3512 -#define SM_VOK_SIZE 1
3513 -#define SM_VMRDY_OFFSET 4
3514 -#define SM_VMRDY_SIZE 1
3515 -#define SM_CKRDY_OFFSET 5
3516 -#define SM_CKRDY_SIZE 1
3517 -
3518 -/* Bitfields in PM_GCCTRL */
3519 -#define SM_OSCSEL_OFFSET 0
3520 -#define SM_OSCSEL_SIZE 1
3521 -#define SM_PLLSEL_OFFSET 1
3522 -#define SM_PLLSEL_SIZE 1
3523 -#define SM_CEN_OFFSET 2
3524 -#define SM_CEN_SIZE 1
3525 -#define SM_CPC_OFFSET 3
3526 -#define SM_CPC_SIZE 1
3527 -#define SM_DIVEN_OFFSET 4
3528 -#define SM_DIVEN_SIZE 1
3529 -#define SM_DIV_OFFSET 8
3530 -#define SM_DIV_SIZE 8
3531 -
3532 -/* Bitfields in RTC_CTRL */
3533 -#define SM_PCLR_OFFSET 1
3534 -#define SM_PCLR_SIZE 1
3535 -#define SM_TOPEN_OFFSET 2
3536 -#define SM_TOPEN_SIZE 1
3537 -#define SM_CLKEN_OFFSET 3
3538 -#define SM_CLKEN_SIZE 1
3539 -#define SM_PSEL_OFFSET 8
3540 -#define SM_PSEL_SIZE 16
3541 -
3542 -/* Bitfields in RTC_VAL */
3543 -#define SM_RTC_VAL_VAL_OFFSET 0
3544 -#define SM_RTC_VAL_VAL_SIZE 31
3545 -
3546 -/* Bitfields in RTC_TOP */
3547 -#define SM_RTC_TOP_VAL_OFFSET 0
3548 -#define SM_RTC_TOP_VAL_SIZE 32
3549 -
3550 -/* Bitfields in RTC_IER */
3551 -
3552 -/* Bitfields in RTC_IDR */
3553 -
3554 -/* Bitfields in RTC_IMR */
3555 -
3556 -/* Bitfields in RTC_ISR */
3557 -
3558 -/* Bitfields in RTC_ICR */
3559 -#define SM_TOPI_OFFSET 0
3560 -#define SM_TOPI_SIZE 1
3561 -
3562 -/* Bitfields in WDT_CTRL */
3563 -#define SM_KEY_OFFSET 24
3564 -#define SM_KEY_SIZE 8
3565 -
3566 -/* Bitfields in WDT_CLR */
3567 -
3568 -/* Bitfields in WDT_EXT */
3569 -
3570 -/* Bitfields in RC_RCAUSE */
3571 -#define SM_POR_OFFSET 0
3572 -#define SM_POR_SIZE 1
3573 -#define SM_BOD_OFFSET 1
3574 -#define SM_BOD_SIZE 1
3575 -#define SM_EXT_OFFSET 2
3576 -#define SM_EXT_SIZE 1
3577 -#define SM_WDT_OFFSET 3
3578 -#define SM_WDT_SIZE 1
3579 -#define SM_NTAE_OFFSET 4
3580 -#define SM_NTAE_SIZE 1
3581 -#define SM_SERP_OFFSET 5
3582 -#define SM_SERP_SIZE 1
3583 -
3584 -/* Bitfields in EIM_IER */
3585 -
3586 -/* Bitfields in EIM_IDR */
3587 -
3588 -/* Bitfields in EIM_IMR */
3589 -
3590 -/* Bitfields in EIM_ISR */
3591 -
3592 -/* Bitfields in EIM_ICR */
3593 -
3594 -/* Bitfields in EIM_MODE */
3595 -
3596 -/* Bitfields in EIM_EDGE */
3597 -#define SM_INT0_OFFSET 0
3598 -#define SM_INT0_SIZE 1
3599 -#define SM_INT1_OFFSET 1
3600 -#define SM_INT1_SIZE 1
3601 -#define SM_INT2_OFFSET 2
3602 -#define SM_INT2_SIZE 1
3603 -#define SM_INT3_OFFSET 3
3604 -#define SM_INT3_SIZE 1
3605 -
3606 -/* Bitfields in EIM_LEVEL */
3607 -
3608 -/* Bitfields in EIM_TEST */
3609 -#define SM_TESTEN_OFFSET 31
3610 -#define SM_TESTEN_SIZE 1
3611 -
3612 -/* Bitfields in EIM_NMIC */
3613 -#define SM_EN_OFFSET 0
3614 -#define SM_EN_SIZE 1
3615 -
3616 -/* Bit manipulation macros */
3617 -#define SM_BIT(name) (1 << SM_##name##_OFFSET)
3618 -#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
3619 -#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
3620 -#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
3621 -
3622 -/* Register access macros */
3623 -#define sm_readl(port,reg) \
3624 - __raw_readl((port)->regs + SM_##reg)
3625 -#define sm_writel(port,reg,value) \
3626 - __raw_writel((value), (port)->regs + SM_##reg)
3627 -
3628 -#endif /* __ASM_AVR32_SM_H__ */
3629 diff -x .git -Nur linux-2.6.22.1/arch/avr32/Makefile linux-avr32.git/arch/avr32/Makefile
3630 --- linux-2.6.22.1/arch/avr32/Makefile 2007-07-10 20:56:30.000000000 +0200
3631 +++ linux-avr32.git/arch/avr32/Makefile 2007-06-06 11:33:46.000000000 +0200
3632 @@ -31,6 +31,7 @@
3633 core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
3634 core-y += arch/avr32/kernel/
3635 core-y += arch/avr32/mm/
3636 +drivers-y += arch/avr32/drivers/
3637 libs-y += arch/avr32/lib/
3638
3639 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
3640 diff -x .git -Nur linux-2.6.22.1/arch/avr32/mm/dma-coherent.c linux-avr32.git/arch/avr32/mm/dma-coherent.c
3641 --- linux-2.6.22.1/arch/avr32/mm/dma-coherent.c 2007-07-10 20:56:30.000000000 +0200
3642 +++ linux-avr32.git/arch/avr32/mm/dma-coherent.c 2007-07-12 13:59:49.000000000 +0200
3643 @@ -41,6 +41,13 @@
3644 struct page *page, *free, *end;
3645 int order;
3646
3647 + /* Following is a work-around (a.k.a. hack) to prevent pages
3648 + * with __GFP_COMP being passed to split_page() which cannot
3649 + * handle them. The real problem is that this flag probably
3650 + * should be 0 on AVR32 as it is not supported on this
3651 + * platform--see CONFIG_HUGETLB_PAGE. */
3652 + gfp &= ~(__GFP_COMP);
3653 +
3654 size = PAGE_ALIGN(size);
3655 order = get_order(size);
3656
3657 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/at32ap700x_wdt.c linux-avr32.git/drivers/char/watchdog/at32ap700x_wdt.c
3658 --- linux-2.6.22.1/drivers/char/watchdog/at32ap700x_wdt.c 1970-01-01 01:00:00.000000000 +0100
3659 +++ linux-avr32.git/drivers/char/watchdog/at32ap700x_wdt.c 2007-07-12 13:59:59.000000000 +0200
3660 @@ -0,0 +1,325 @@
3661 +/*
3662 + * Watchdog driver for Atmel AT32AP700X devices
3663 + *
3664 + * Copyright (C) 2005-2006 Atmel Corporation
3665 + *
3666 + * This program is free software; you can redistribute it and/or modify
3667 + * it under the terms of the GNU General Public License version 2 as
3668 + * published by the Free Software Foundation.
3669 + */
3670 +
3671 +#include <linux/init.h>
3672 +#include <linux/kernel.h>
3673 +#include <linux/module.h>
3674 +#include <linux/moduleparam.h>
3675 +#include <linux/miscdevice.h>
3676 +#include <linux/fs.h>
3677 +#include <linux/platform_device.h>
3678 +#include <linux/watchdog.h>
3679 +#include <linux/uaccess.h>
3680 +#include <linux/io.h>
3681 +
3682 +#define TIMEOUT_MIN 1
3683 +#define TIMEOUT_DEFAULT CONFIG_AT32AP700X_WDT_TIMEOUT
3684 +#define TIMEOUT_MAX 2
3685 +
3686 +/* Watchdog registers and write/read macro */
3687 +#define WDT_CTRL 0x00
3688 +#define WDT_CTRL_EN 0
3689 +#define WDT_CTRL_PSEL 8
3690 +#define WDT_CTRL_KEY 24
3691 +
3692 +#define WDT_CLR 0x04
3693 +
3694 +#define WDT_BIT(name) (1 << WDT_##name)
3695 +#define WDT_BF(name,value) ((value) << WDT_##name)
3696 +
3697 +#define wdt_readl(dev,reg) \
3698 + __raw_readl((dev)->regs + WDT_##reg)
3699 +#define wdt_writel(dev,reg,value) \
3700 + __raw_writel((value), (dev)->regs + WDT_##reg)
3701 +
3702 +struct wdt_at32ap700x {
3703 + void __iomem *regs;
3704 + int timeout;
3705 + int users;
3706 + struct miscdevice miscdev;
3707 +};
3708 +
3709 +static struct wdt_at32ap700x *wdt;
3710 +
3711 +/*
3712 + * Disable the watchdog.
3713 + */
3714 +static void inline at32_wdt_stop(void)
3715 +{
3716 + unsigned long psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
3717 + wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
3718 + wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
3719 +}
3720 +
3721 +/*
3722 + * Enable and reset the watchdog.
3723 + */
3724 +static void inline at32_wdt_start(void)
3725 +{
3726 + /* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
3727 + unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
3728 +
3729 + wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
3730 + | WDT_BF(CTRL_PSEL, psel)
3731 + | WDT_BF(CTRL_KEY, 0x55));
3732 + wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
3733 + | WDT_BF(CTRL_PSEL, psel)
3734 + | WDT_BF(CTRL_KEY, 0xaa));
3735 +}
3736 +
3737 +/*
3738 + * Pat the watchdog timer.
3739 + */
3740 +static void inline at32_wdt_pat(void)
3741 +{
3742 + wdt_writel(wdt, CLR, 0x42);
3743 +}
3744 +
3745 +/*
3746 + * Watchdog device is opened, and watchdog starts running.
3747 + */
3748 +static int at32_wdt_open(struct inode *inode, struct file *file)
3749 +{
3750 + if (test_and_set_bit(1, &wdt->users))
3751 + return -EBUSY;
3752 +
3753 + at32_wdt_start();
3754 + return nonseekable_open(inode, file);
3755 +}
3756 +
3757 +/*
3758 + * Close the watchdog device. If CONFIG_WATCHDOG_NOWAYOUT is _not_ defined then
3759 + * the watchdog is also disabled.
3760 + */
3761 +static int at32_wdt_close(struct inode *inode, struct file *file)
3762 +{
3763 +#ifndef CONFIG_WATCHDOG_NOWAYOUT
3764 + at32_wdt_stop();
3765 +#endif
3766 + clear_bit(1, &wdt->users);
3767 + return 0;
3768 +}
3769 +
3770 +/*
3771 + * Change the watchdog time interval.
3772 + */
3773 +static int at32_wdt_settimeout(int time)
3774 +{
3775 + /*
3776 + * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
3777 + * 2 ^ 16 allowing up to 2 seconds timeout.
3778 + */
3779 + if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
3780 + return -EINVAL;
3781 +
3782 + /*
3783 + * Set new watchdog time. It will be used when at32_wdt_start() is
3784 + * called.
3785 + */
3786 + wdt->timeout = time;
3787 + return 0;
3788 +}
3789 +
3790 +static struct watchdog_info at32_wdt_info = {
3791 + .identity = "at32ap700x watchdog",
3792 + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
3793 +};
3794 +
3795 +/*
3796 + * Handle commands from user-space.
3797 + */
3798 +static int at32_wdt_ioctl(struct inode *inode, struct file *file,
3799 + unsigned int cmd, unsigned long arg)
3800 +{
3801 + int ret = -ENOTTY;
3802 + int time;
3803 + void __user *argp = (void __user *)arg;
3804 + int __user *p = argp;
3805 +
3806 + switch (cmd) {
3807 + case WDIOC_KEEPALIVE:
3808 + at32_wdt_pat();
3809 + ret = 0;
3810 + break;
3811 + case WDIOC_GETSUPPORT:
3812 + ret = copy_to_user(argp, &at32_wdt_info,
3813 + sizeof(at32_wdt_info)) ? -EFAULT : 0;
3814 + break;
3815 + case WDIOC_SETTIMEOUT:
3816 + ret = get_user(time, p);
3817 + if (ret)
3818 + break;
3819 + ret = at32_wdt_settimeout(time);
3820 + if (ret)
3821 + break;
3822 + /* Enable new time value */
3823 + at32_wdt_start();
3824 + /* fall through */
3825 + case WDIOC_GETTIMEOUT:
3826 + ret = put_user(wdt->timeout, p);
3827 + break;
3828 + case WDIOC_GETSTATUS: /* fall through */
3829 + case WDIOC_GETBOOTSTATUS:
3830 + ret = put_user(0, p);
3831 + break;
3832 + case WDIOC_SETOPTIONS:
3833 + ret = get_user(time, p);
3834 + if (ret)
3835 + break;
3836 + if (time & WDIOS_DISABLECARD)
3837 + at32_wdt_stop();
3838 + if (time & WDIOS_ENABLECARD)
3839 + at32_wdt_start();
3840 + ret = 0;
3841 + break;
3842 + }
3843 +
3844 + return ret;
3845 +}
3846 +
3847 +static ssize_t at32_wdt_write(struct file *file, const char *data, size_t len,
3848 + loff_t *ppos)
3849 +{
3850 + at32_wdt_pat();
3851 + return len;
3852 +}
3853 +
3854 +static const struct file_operations at32_wdt_fops = {
3855 + .owner = THIS_MODULE,
3856 + .llseek = no_llseek,
3857 + .ioctl = at32_wdt_ioctl,
3858 + .open = at32_wdt_open,
3859 + .release = at32_wdt_close,
3860 + .write = at32_wdt_write,
3861 +};
3862 +
3863 +static int __init at32_wdt_probe(struct platform_device *pdev)
3864 +{
3865 + struct resource *regs;
3866 + int ret;
3867 +
3868 + if (wdt) {
3869 + dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
3870 + return -EBUSY;
3871 + }
3872 +
3873 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3874 + if (!regs) {
3875 + dev_dbg(&pdev->dev, "missing mmio resource\n");
3876 + return -ENXIO;
3877 + }
3878 +
3879 + wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
3880 + if (!wdt) {
3881 + dev_dbg(&pdev->dev, "no memory for wdt structure\n");
3882 + return -ENOMEM;
3883 + }
3884 +
3885 + wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
3886 + if (!wdt->regs) {
3887 + ret = -ENOMEM;
3888 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
3889 + goto err_free;
3890 + }
3891 + wdt->users = 0;
3892 + wdt->miscdev.minor = WATCHDOG_MINOR;
3893 + wdt->miscdev.name = "watchdog";
3894 + wdt->miscdev.fops = &at32_wdt_fops;
3895 +
3896 + if (at32_wdt_settimeout(TIMEOUT_DEFAULT)) {
3897 + at32_wdt_settimeout(TIMEOUT_MAX);
3898 + dev_dbg(&pdev->dev,
3899 + "default timeout invalid, set to %d sec.\n",
3900 + TIMEOUT_MAX);
3901 + }
3902 +
3903 + ret = misc_register(&wdt->miscdev);
3904 + if (ret) {
3905 + dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
3906 + goto err_iounmap;
3907 + }
3908 +
3909 + platform_set_drvdata(pdev, wdt);
3910 + wdt->miscdev.parent = &pdev->dev;
3911 + dev_info(&pdev->dev, "AT32AP700X WDT at 0x%p\n", wdt->regs);
3912 +
3913 + return 0;
3914 +
3915 +err_iounmap:
3916 + iounmap(wdt->regs);
3917 +err_free:
3918 + kfree(wdt);
3919 + wdt = NULL;
3920 + return ret;
3921 +}
3922 +
3923 +static int __exit at32_wdt_remove(struct platform_device *pdev)
3924 +{
3925 + if (wdt && platform_get_drvdata(pdev) == wdt) {
3926 + misc_deregister(&wdt->miscdev);
3927 + iounmap(wdt->regs);
3928 + kfree(wdt);
3929 + wdt = NULL;
3930 + platform_set_drvdata(pdev, NULL);
3931 + }
3932 +
3933 + return 0;
3934 +}
3935 +
3936 +static void at32_wdt_shutdown(struct platform_device *pdev)
3937 +{
3938 + at32_wdt_stop();
3939 +}
3940 +
3941 +#ifdef CONFIG_PM
3942 +static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
3943 +{
3944 + at32_wdt_stop();
3945 + return 0;
3946 +}
3947 +
3948 +static int at32_wdt_resume(struct platform_device *pdev)
3949 +{
3950 + if (wdt->users)
3951 + at32_wdt_start();
3952 + return 0;
3953 +}
3954 +#else
3955 +#define at32_wdt_suspend NULL
3956 +#define at32_wdt_resume NULL
3957 +#endif
3958 +
3959 +static struct platform_driver at32_wdt_driver = {
3960 + .remove = __exit_p(at32_wdt_remove),
3961 + .suspend = at32_wdt_suspend,
3962 + .resume = at32_wdt_resume,
3963 + .driver = {
3964 + .name = "at32_wdt",
3965 + .owner = THIS_MODULE,
3966 + },
3967 + .shutdown = at32_wdt_shutdown,
3968 +};
3969 +
3970 +static int __init at32_wdt_init(void)
3971 +{
3972 + return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
3973 +}
3974 +module_init(at32_wdt_init);
3975 +
3976 +static void __exit at32_wdt_exit(void)
3977 +{
3978 + platform_driver_unregister(&at32_wdt_driver);
3979 +}
3980 +module_exit(at32_wdt_exit);
3981 +
3982 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
3983 +MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
3984 +MODULE_LICENSE("GPL");
3985 +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
3986 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/Kconfig linux-avr32.git/drivers/char/watchdog/Kconfig
3987 --- linux-2.6.22.1/drivers/char/watchdog/Kconfig 2007-07-10 20:56:30.000000000 +0200
3988 +++ linux-avr32.git/drivers/char/watchdog/Kconfig 2007-07-12 13:59:59.000000000 +0200
3989 @@ -187,6 +187,26 @@
3990
3991 Say N if you are unsure.
3992
3993 +# AVR32 Architecture
3994 +
3995 +config AT32AP700X_WDT
3996 + tristate "AT32AP700x watchdog"
3997 + depends on WATCHDOG && CPU_AT32AP7000
3998 + help
3999 + Watchdog timer embedded into AT32AP700x devices. This will reboot
4000 + your system when the timeout is reached.
4001 +
4002 +config AT32AP700X_WDT_TIMEOUT
4003 + int "Timeout value for AT32AP700x watchdog"
4004 + depends on AT32AP700X_WDT
4005 + default "2"
4006 + range 1 2
4007 + help
4008 + Sets the timeout value for the watchdog in AT32AP700x devices.
4009 + Limited by hardware to be 1 or 2 seconds.
4010 +
4011 + Set to 2 seconds by default.
4012 +
4013 # X86 (i386 + ia64 + x86_64) Architecture
4014
4015 config ACQUIRE_WDT
4016 diff -x .git -Nur linux-2.6.22.1/drivers/char/watchdog/Makefile linux-avr32.git/drivers/char/watchdog/Makefile
4017 --- linux-2.6.22.1/drivers/char/watchdog/Makefile 2007-07-10 20:56:30.000000000 +0200
4018 +++ linux-avr32.git/drivers/char/watchdog/Makefile 2007-07-12 13:59:59.000000000 +0200
4019 @@ -36,6 +36,9 @@
4020 obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
4021 obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
4022
4023 +# AVR32 Architecture
4024 +obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
4025 +
4026 # X86 (i386 + ia64 + x86_64) Architecture
4027 obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4028 obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4029 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/atmeltwi.h linux-avr32.git/drivers/i2c/busses/atmeltwi.h
4030 --- linux-2.6.22.1/drivers/i2c/busses/atmeltwi.h 1970-01-01 01:00:00.000000000 +0100
4031 +++ linux-avr32.git/drivers/i2c/busses/atmeltwi.h 2007-06-06 11:33:51.000000000 +0200
4032 @@ -0,0 +1,117 @@
4033 +/*
4034 + * Register definitions for the Atmel Two-Wire Interface
4035 + */
4036 +
4037 +#ifndef __ASM_AVR32_TWI_H__
4038 +#define __ASM_AVR32_TWI_H__
4039 +
4040 +/* TWI register offsets */
4041 +#define TWI_CR 0x0000
4042 +#define TWI_MMR 0x0004
4043 +#define TWI_SMR 0x0008
4044 +#define TWI_IADR 0x000c
4045 +#define TWI_CWGR 0x0010
4046 +#define TWI_SR 0x0020
4047 +#define TWI_IER 0x0024
4048 +#define TWI_IDR 0x0028
4049 +#define TWI_IMR 0x002c
4050 +#define TWI_RHR 0x0030
4051 +#define TWI_THR 0x0034
4052 +
4053 +/* Bitfields in CR */
4054 +#define TWI_START_OFFSET 0
4055 +#define TWI_START_SIZE 1
4056 +#define TWI_STOP_OFFSET 1
4057 +#define TWI_STOP_SIZE 1
4058 +#define TWI_MSEN_OFFSET 2
4059 +#define TWI_MSEN_SIZE 1
4060 +#define TWI_MSDIS_OFFSET 3
4061 +#define TWI_MSDIS_SIZE 1
4062 +#define TWI_SVEN_OFFSET 4
4063 +#define TWI_SVEN_SIZE 1
4064 +#define TWI_SVDIS_OFFSET 5
4065 +#define TWI_SVDIS_SIZE 1
4066 +#define TWI_SWRST_OFFSET 7
4067 +#define TWI_SWRST_SIZE 1
4068 +
4069 +/* Bitfields in MMR */
4070 +#define TWI_IADRSZ_OFFSET 8
4071 +#define TWI_IADRSZ_SIZE 2
4072 +#define TWI_MREAD_OFFSET 12
4073 +#define TWI_MREAD_SIZE 1
4074 +#define TWI_DADR_OFFSET 16
4075 +#define TWI_DADR_SIZE 7
4076 +
4077 +/* Bitfields in SMR */
4078 +#define TWI_SADR_OFFSET 16
4079 +#define TWI_SADR_SIZE 7
4080 +
4081 +/* Bitfields in IADR */
4082 +#define TWI_IADR_OFFSET 0
4083 +#define TWI_IADR_SIZE 24
4084 +
4085 +/* Bitfields in CWGR */
4086 +#define TWI_CLDIV_OFFSET 0
4087 +#define TWI_CLDIV_SIZE 8
4088 +#define TWI_CHDIV_OFFSET 8
4089 +#define TWI_CHDIV_SIZE 8
4090 +#define TWI_CKDIV_OFFSET 16
4091 +#define TWI_CKDIV_SIZE 3
4092 +
4093 +/* Bitfields in SR */
4094 +#define TWI_TXCOMP_OFFSET 0
4095 +#define TWI_TXCOMP_SIZE 1
4096 +#define TWI_RXRDY_OFFSET 1
4097 +#define TWI_RXRDY_SIZE 1
4098 +#define TWI_TXRDY_OFFSET 2
4099 +#define TWI_TXRDY_SIZE 1
4100 +#define TWI_SVDIR_OFFSET 3
4101 +#define TWI_SVDIR_SIZE 1
4102 +#define TWI_SVACC_OFFSET 4
4103 +#define TWI_SVACC_SIZE 1
4104 +#define TWI_GCACC_OFFSET 5
4105 +#define TWI_GCACC_SIZE 1
4106 +#define TWI_OVRE_OFFSET 6
4107 +#define TWI_OVRE_SIZE 1
4108 +#define TWI_UNRE_OFFSET 7
4109 +#define TWI_UNRE_SIZE 1
4110 +#define TWI_NACK_OFFSET 8
4111 +#define TWI_NACK_SIZE 1
4112 +#define TWI_ARBLST_OFFSET 9
4113 +#define TWI_ARBLST_SIZE 1
4114 +
4115 +/* Bitfields in RHR */
4116 +#define TWI_RXDATA_OFFSET 0
4117 +#define TWI_RXDATA_SIZE 8
4118 +
4119 +/* Bitfields in THR */
4120 +#define TWI_TXDATA_OFFSET 0
4121 +#define TWI_TXDATA_SIZE 8
4122 +
4123 +/* Constants for IADRSZ */
4124 +#define TWI_IADRSZ_NO_ADDR 0
4125 +#define TWI_IADRSZ_ONE_BYTE 1
4126 +#define TWI_IADRSZ_TWO_BYTES 2
4127 +#define TWI_IADRSZ_THREE_BYTES 3
4128 +
4129 +/* Bit manipulation macros */
4130 +#define TWI_BIT(name) \
4131 + (1 << TWI_##name##_OFFSET)
4132 +#define TWI_BF(name,value) \
4133 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
4134 + << TWI_##name##_OFFSET)
4135 +#define TWI_BFEXT(name,value) \
4136 + (((value) >> TWI_##name##_OFFSET) \
4137 + & ((1 << TWI_##name##_SIZE) - 1))
4138 +#define TWI_BFINS(name,value,old) \
4139 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
4140 + << TWI_##name##_OFFSET)) \
4141 + | TWI_BF(name,value))
4142 +
4143 +/* Register access macros */
4144 +#define twi_readl(port,reg) \
4145 + __raw_readl((port)->regs + TWI_##reg)
4146 +#define twi_writel(port,reg,value) \
4147 + __raw_writel((value), (port)->regs + TWI_##reg)
4148 +
4149 +#endif /* __ASM_AVR32_TWI_H__ */
4150 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/i2c-atmeltwi.c linux-avr32.git/drivers/i2c/busses/i2c-atmeltwi.c
4151 --- linux-2.6.22.1/drivers/i2c/busses/i2c-atmeltwi.c 1970-01-01 01:00:00.000000000 +0100
4152 +++ linux-avr32.git/drivers/i2c/busses/i2c-atmeltwi.c 2007-07-12 13:59:59.000000000 +0200
4153 @@ -0,0 +1,348 @@
4154 +/*
4155 + * i2c Support for Atmel's Two-Wire Interface (TWI)
4156 + *
4157 + * Based on the work of Copyright (C) 2004 Rick Bronson
4158 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
4159 + * Ported to AVR32 and heavily modified by Espen Krangnes <ekrangnes at atmel.com>
4160 + *
4161 + * Copyright (C) 2006 Atmel Corporation
4162 + *
4163 + * Borrowed heavily from the original work by:
4164 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
4165 + *
4166 + * This program is free software; you can redistribute it and/or modify
4167 + * it under the terms of the GNU General Public License as published by
4168 + * the Free Software Foundation; either version 2 of the License, or
4169 + * (at your option) any later version.
4170 + */
4171 +
4172 +
4173 +#include <linux/err.h>
4174 +#include <linux/module.h>
4175 +#include <linux/kernel.h>
4176 +#include <linux/slab.h>
4177 +#include <linux/types.h>
4178 +#include <linux/delay.h>
4179 +#include <linux/i2c.h>
4180 +#include <linux/init.h>
4181 +#include <linux/clk.h>
4182 +#include <linux/interrupt.h>
4183 +#include <linux/irq.h>
4184 +#include <linux/platform_device.h>
4185 +#include <linux/completion.h>
4186 +#include <asm/io.h>
4187 +#include <linux/time.h>
4188 +#include "atmeltwi.h"
4189 +
4190 +static unsigned int baudrate = CONFIG_I2C_ATMELTWI_BAUDRATE;
4191 +module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
4192 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
4193 +
4194 +
4195 +struct atmel_twi {
4196 + void __iomem *regs;
4197 + struct i2c_adapter adapter;
4198 + struct clk *pclk;
4199 + spinlock_t lock;
4200 + struct completion comp;
4201 + u32 intmask;
4202 + u8 *buf;
4203 + u8 len;
4204 + u8 acks_left;
4205 + unsigned int irq;
4206 +
4207 +};
4208 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
4209 +
4210 +/*
4211 + * Initialize the TWI hardware registers.
4212 + */
4213 +static int __devinit twi_hwinit(struct atmel_twi *twi)
4214 +{
4215 + unsigned long cdiv, ckdiv=0;
4216 +
4217 + twi_writel(twi, IDR, ~0UL);
4218 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
4219 + twi_readl(twi, SR);
4220 +
4221 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
4222 +
4223 + while (cdiv > 255) {
4224 + ckdiv++;
4225 + cdiv = cdiv >> 1;
4226 + }
4227 +
4228 + if (ckdiv > 7)
4229 + return -EINVAL;
4230 + else
4231 + twi_writel(twi, CWGR, (TWI_BF(CKDIV, ckdiv)
4232 + | TWI_BF(CHDIV, cdiv)
4233 + | TWI_BF(CLDIV, cdiv)));
4234 + return 0;
4235 +}
4236 +
4237 +/*
4238 + * Waits for the i2c status register to set the specified bitmask
4239 + * Returns 0 if timed out (~100ms).
4240 + */
4241 +static short twi_wait_for_completion(struct atmel_twi *twi,
4242 + u32 mask)
4243 +{
4244 + int timeout = msecs_to_jiffies(100);
4245 +
4246 + twi->intmask = mask;
4247 + init_completion(&twi->comp);
4248 +
4249 + twi_writel(twi, IER, mask);
4250 +
4251 + if(!wait_for_completion_timeout(&twi->comp, timeout))
4252 + return -ETIMEDOUT;
4253 +
4254 + return 0;
4255 +}
4256 +
4257 +/*
4258 + * Generic i2c master transfer entrypoint.
4259 + */
4260 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
4261 +{
4262 + struct atmel_twi *twi = to_atmel_twi(adap);
4263 + struct i2c_msg *pmsg;
4264 + int i;
4265 +
4266 + /* get first message */
4267 + pmsg = msgs;
4268 +
4269 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
4270 +
4271 + for (i = 0; i < num; i++, pmsg++) {
4272 +
4273 + twi->len = pmsg->len;
4274 + twi->buf = pmsg->buf;
4275 + twi->acks_left = pmsg->len;
4276 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
4277 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
4278 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
4279 +
4280 + dev_dbg(&adap->dev,"#%d: internal addr %d %s byte%s %s 0x%02x\n",
4281 + i,pmsg->len, pmsg->flags & I2C_M_RD ? "reading" : "writing",
4282 + pmsg->len > 1 ? "s" : "",
4283 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
4284 +
4285 + /* enable */
4286 + twi_writel(twi, CR, TWI_BIT(MSEN));
4287 +
4288 + if (pmsg->flags & I2C_M_RD) {
4289 + twi_writel(twi, CR, TWI_BIT(START));
4290 + if ( twi_wait_for_completion(twi,TWI_BIT(RXRDY))==-ETIMEDOUT ) {
4291 + dev_dbg(&adap->dev, "RXRDY timeout. Stopped with %d bytes left\n",
4292 + twi->acks_left);
4293 + return -ETIMEDOUT;
4294 + }
4295 +
4296 + /* Send Stop, and Wait until transfer is finished */
4297 + if ( twi_wait_for_completion(twi,TWI_BIT(TXCOMP))==-ETIMEDOUT ) {
4298 + dev_dbg(&adap->dev, "TXCOMP timeout\n");
4299 + return -ETIMEDOUT;
4300 + }
4301 +
4302 + } else {
4303 + twi_writel(twi, THR, twi->buf[0]);
4304 + if ( twi_wait_for_completion(twi,TWI_BIT(TXRDY))==-ETIMEDOUT ) {
4305 + dev_dbg(&adap->dev, "TXRDY timeout. Stopped with %d bytes left\n",
4306 + twi->acks_left);
4307 + return -ETIMEDOUT;
4308 + }
4309 + }
4310 +
4311 + /* Disable TWI interface */
4312 + twi_writel(twi, CR, TWI_BIT(MSDIS));
4313 +
4314 + } /* end cur msg */
4315 +
4316 + return i;
4317 +}
4318 +
4319 +
4320 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
4321 +{
4322 + struct atmel_twi *twi = dev_id;
4323 + int status = twi_readl(twi, SR);
4324 +
4325 + if (twi->intmask & status){
4326 + if (twi->intmask & TWI_BIT(NACK)) {
4327 + goto nack;
4328 + } else if (twi->intmask & TWI_BIT(RXRDY)){
4329 + twi->buf[twi->len - twi->acks_left] = twi_readl(twi,RHR);
4330 + if(--twi->acks_left==1)
4331 + twi_writel(twi, CR, TWI_BIT(STOP));
4332 + if (twi->acks_left==0)
4333 + goto complete;
4334 + } else if (twi->intmask & TWI_BIT(TXRDY)) {
4335 + twi->acks_left--;
4336 + if (twi->acks_left==0) {
4337 + twi->intmask = TWI_BIT(TXCOMP);
4338 + twi_writel(twi, IER, TWI_BIT(TXCOMP));
4339 + } else
4340 + twi_writel(twi, THR, twi->buf[twi->len - twi->acks_left]);
4341 + } else if (twi->intmask & TWI_BIT(TXCOMP)) {
4342 + goto complete;
4343 + }
4344 + }
4345 +
4346 + return IRQ_HANDLED;
4347 +
4348 +nack:
4349 + printk(KERN_INFO "NACK received!\n");
4350 +
4351 +complete:
4352 + twi_writel(twi, IDR, ~0UL);
4353 + complete(&twi->comp);
4354 +
4355 + return IRQ_HANDLED;
4356 +
4357 +}
4358 +
4359 +
4360 +/*
4361 + * Return list of supported functionality.
4362 + */
4363 +static u32 twi_func(struct i2c_adapter *adapter)
4364 +{
4365 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4366 +}
4367 +
4368 +/* For now, we only handle combined mode (smbus) */
4369 +static struct i2c_algorithm twi_algorithm = {
4370 + .master_xfer = twi_xfer,
4371 + .functionality = twi_func,
4372 +};
4373 +
4374 +/*
4375 + * Main initialization routine.
4376 + */
4377 +static int __devinit twi_probe(struct platform_device *pdev)
4378 +{
4379 + struct atmel_twi *twi;
4380 + struct resource *regs;
4381 + struct clk *pclk;
4382 + struct i2c_adapter *adapter;
4383 + int rc, irq;
4384 +
4385 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4386 + if (!regs)
4387 + return -ENXIO;
4388 +
4389 + pclk = clk_get(&pdev->dev, "pclk");
4390 + if (IS_ERR(pclk))
4391 + return PTR_ERR(pclk);
4392 + clk_enable(pclk);
4393 +
4394 + rc = -ENOMEM;
4395 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
4396 + if (!twi) {
4397 + dev_err(&pdev->dev, "can't allocate interface!\n");
4398 + goto err_alloc_twi;
4399 + }
4400 +
4401 + twi->pclk = pclk;
4402 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
4403 + if (!twi->regs)
4404 + goto err_ioremap;
4405 +
4406 + irq = platform_get_irq(pdev,0);
4407 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
4408 + if (rc) {
4409 + dev_err(&pdev->dev, "can't bind irq!\n");
4410 + goto err_irq;
4411 + }
4412 + twi->irq = irq;
4413 +
4414 + rc = twi_hwinit(twi);
4415 + if (rc) {
4416 + dev_err(&pdev->dev, "Unable to set baudrate\n");
4417 + goto err_hw_init;
4418 + }
4419 +
4420 + adapter = &twi->adapter;
4421 + sprintf(adapter->name, "TWI");
4422 + adapter->algo = &twi_algorithm;
4423 + adapter->class = I2C_CLASS_HWMON;
4424 + adapter->dev.parent = &pdev->dev;
4425 +
4426 + platform_set_drvdata(pdev, twi);
4427 +
4428 + rc = i2c_add_adapter(adapter);
4429 + if (rc) {
4430 + dev_err(&pdev->dev, "Adapter %s registration failed\n",
4431 + adapter->name);
4432 + goto err_register;
4433 + }
4434 +
4435 + dev_info(&pdev->dev, "Atmel TWI i2c bus device (baudrate %dk) at 0x%08lx.\n",
4436 + baudrate/1000, (unsigned long)regs->start);
4437 +
4438 + return 0;
4439 +
4440 +
4441 +err_register:
4442 + platform_set_drvdata(pdev, NULL);
4443 +
4444 +err_hw_init:
4445 + free_irq(irq, twi);
4446 +
4447 +err_irq:
4448 + iounmap(twi->regs);
4449 +
4450 +err_ioremap:
4451 + kfree(twi);
4452 +
4453 +err_alloc_twi:
4454 + clk_disable(pclk);
4455 + clk_put(pclk);
4456 +
4457 + return rc;
4458 +}
4459 +
4460 +static int __devexit twi_remove(struct platform_device *pdev)
4461 +{
4462 + struct atmel_twi *twi = platform_get_drvdata(pdev);
4463 + int res;
4464 +
4465 + platform_set_drvdata(pdev, NULL);
4466 + res = i2c_del_adapter(&twi->adapter);
4467 + twi_writel(twi, CR, TWI_BIT(MSDIS));
4468 + iounmap(twi->regs);
4469 + clk_disable(twi->pclk);
4470 + clk_put(twi->pclk);
4471 + free_irq(twi->irq, twi);
4472 + kfree(twi);
4473 +
4474 + return res;
4475 +}
4476 +
4477 +static struct platform_driver twi_driver = {
4478 + .probe = twi_probe,
4479 + .remove = __devexit_p(twi_remove),
4480 + .driver = {
4481 + .name = "atmel_twi",
4482 + .owner = THIS_MODULE,
4483 + },
4484 +};
4485 +
4486 +static int __init atmel_twi_init(void)
4487 +{
4488 + return platform_driver_register(&twi_driver);
4489 +}
4490 +
4491 +static void __exit atmel_twi_exit(void)
4492 +{
4493 + platform_driver_unregister(&twi_driver);
4494 +}
4495 +
4496 +module_init(atmel_twi_init);
4497 +module_exit(atmel_twi_exit);
4498 +
4499 +MODULE_AUTHOR("Espen Krangnes");
4500 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
4501 +MODULE_LICENSE("GPL");
4502 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/Kconfig linux-avr32.git/drivers/i2c/busses/Kconfig
4503 --- linux-2.6.22.1/drivers/i2c/busses/Kconfig 2007-07-10 20:56:30.000000000 +0200
4504 +++ linux-avr32.git/drivers/i2c/busses/Kconfig 2007-07-12 13:59:59.000000000 +0200
4505 @@ -4,6 +4,26 @@
4506
4507 menu "I2C Hardware Bus support"
4508
4509 +config I2C_ATMELTWI
4510 + tristate "Atmel TWI/I2C"
4511 + depends on I2C
4512 + help
4513 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
4514 + AT91-based device and want to use its built-in TWI
4515 + functionality. Atmel's TWI is compatible with Philips' I2C
4516 + protocol. If in doubt, say NO
4517 +
4518 +config I2C_ATMELTWI_BAUDRATE
4519 + prompt "Atmel TWI baudrate"
4520 + depends on I2C_ATMELTWI
4521 + int
4522 + default 100000
4523 + help
4524 + Set the TWI/I2C baudrate. This will alter the default value. A
4525 + different baudrate can be set by using a module parameter as well. If
4526 + no parameter is provided when loading, this is the value that will be
4527 + used.
4528 +
4529 config I2C_ALI1535
4530 tristate "ALI 1535"
4531 depends on PCI
4532 diff -x .git -Nur linux-2.6.22.1/drivers/i2c/busses/Makefile linux-avr32.git/drivers/i2c/busses/Makefile
4533 --- linux-2.6.22.1/drivers/i2c/busses/Makefile 2007-07-10 20:56:30.000000000 +0200
4534 +++ linux-avr32.git/drivers/i2c/busses/Makefile 2007-07-12 13:59:59.000000000 +0200
4535 @@ -52,6 +52,7 @@
4536 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
4537 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
4538 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
4539 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
4540
4541 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
4542 EXTRA_CFLAGS += -DDEBUG
4543 diff -x .git -Nur linux-2.6.22.1/drivers/leds/Kconfig linux-avr32.git/drivers/leds/Kconfig
4544 --- linux-2.6.22.1/drivers/leds/Kconfig 2007-07-10 20:56:30.000000000 +0200
4545 +++ linux-avr32.git/drivers/leds/Kconfig 2007-07-12 14:00:02.000000000 +0200
4546 @@ -95,6 +95,14 @@
4547 help
4548 This option enables support for the front LED on Cobalt Server
4549
4550 +config LEDS_GPIO
4551 + tristate "LED Support for GPIO connected LEDs"
4552 + depends on LEDS_CLASS && GENERIC_GPIO
4553 + help
4554 + This option enables support for the LEDs connected to GPIO
4555 + outputs. To be useful the particular board must have LEDs
4556 + and they must be connected to the GPIO lines.
4557 +
4558 comment "LED Triggers"
4559
4560 config LEDS_TRIGGERS
4561 diff -x .git -Nur linux-2.6.22.1/drivers/leds/leds-gpio.c linux-avr32.git/drivers/leds/leds-gpio.c
4562 --- linux-2.6.22.1/drivers/leds/leds-gpio.c 1970-01-01 01:00:00.000000000 +0100
4563 +++ linux-avr32.git/drivers/leds/leds-gpio.c 2007-07-12 14:00:02.000000000 +0200
4564 @@ -0,0 +1,199 @@
4565 +/*
4566 + * LEDs driver for GPIOs
4567 + *
4568 + * Copyright (C) 2007 8D Technologies inc.
4569 + * Raphael Assenat <raph@8d.com>
4570 + *
4571 + * This program is free software; you can redistribute it and/or modify
4572 + * it under the terms of the GNU General Public License version 2 as
4573 + * published by the Free Software Foundation.
4574 + *
4575 + */
4576 +#include <linux/kernel.h>
4577 +#include <linux/init.h>
4578 +#include <linux/platform_device.h>
4579 +#include <linux/leds.h>
4580 +#include <linux/workqueue.h>
4581 +
4582 +#include <asm/gpio.h>
4583 +
4584 +struct gpio_led_data {
4585 + struct led_classdev cdev;
4586 + unsigned gpio;
4587 + struct work_struct work;
4588 + u8 new_level;
4589 + u8 can_sleep;
4590 + u8 active_low;
4591 +};
4592 +
4593 +static void gpio_led_work(struct work_struct *work)
4594 +{
4595 + struct gpio_led_data *led_dat =
4596 + container_of(work, struct gpio_led_data, work);
4597 +
4598 + gpio_set_value_cansleep(led_dat->gpio, led_dat->new_level);
4599 +}
4600 +
4601 +static void gpio_led_set(struct led_classdev *led_cdev,
4602 + enum led_brightness value)
4603 +{
4604 + struct gpio_led_data *led_dat =
4605 + container_of(led_cdev, struct gpio_led_data, cdev);
4606 + int level;
4607 +
4608 + if (value == LED_OFF)
4609 + level = 0;
4610 + else
4611 + level = 1;
4612 +
4613 + if (led_dat->active_low)
4614 + level = !level;
4615 +
4616 + /* setting GPIOs with I2C/etc requires a preemptible task context */
4617 + if (led_dat->can_sleep) {
4618 + if (preempt_count()) {
4619 + led_dat->new_level = level;
4620 + schedule_work(&led_dat->work);
4621 + } else
4622 + gpio_set_value_cansleep(led_dat->gpio, level);
4623 + } else
4624 + gpio_set_value(led_dat->gpio, level);
4625 +}
4626 +
4627 +static int __init gpio_led_probe(struct platform_device *pdev)
4628 +{
4629 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
4630 + struct gpio_led *cur_led;
4631 + struct gpio_led_data *leds_data, *led_dat;
4632 + int i, ret = 0;
4633 +
4634 + if (!pdata)
4635 + return -EBUSY;
4636 +
4637 + leds_data = kzalloc(sizeof(struct gpio_led_data) * pdata->num_leds,
4638 + GFP_KERNEL);
4639 + if (!leds_data)
4640 + return -ENOMEM;
4641 +
4642 + for (i = 0; i < pdata->num_leds; i++) {
4643 + cur_led = &pdata->leds[i];
4644 + led_dat = &leds_data[i];
4645 +
4646 + led_dat->cdev.name = cur_led->name;
4647 + led_dat->cdev.default_trigger = cur_led->default_trigger;
4648 + led_dat->gpio = cur_led->gpio;
4649 + led_dat->can_sleep = gpio_cansleep(cur_led->gpio);
4650 + led_dat->active_low = cur_led->active_low;
4651 + led_dat->cdev.brightness_set = gpio_led_set;
4652 + led_dat->cdev.brightness = cur_led->active_low ? LED_FULL : LED_OFF;
4653 +
4654 + ret = gpio_request(led_dat->gpio, led_dat->cdev.name);
4655 + if (ret < 0)
4656 + goto err;
4657 +
4658 + gpio_direction_output(led_dat->gpio, led_dat->active_low);
4659 +
4660 + ret = led_classdev_register(&pdev->dev, &led_dat->cdev);
4661 + if (ret < 0) {
4662 + gpio_free(led_dat->gpio);
4663 + goto err;
4664 + }
4665 +
4666 + INIT_WORK(&led_dat->work, gpio_led_work);
4667 + }
4668 +
4669 + platform_set_drvdata(pdev, leds_data);
4670 +
4671 + return 0;
4672 +
4673 +err:
4674 + if (i > 0) {
4675 + for (i = i - 1; i >= 0; i--) {
4676 + led_classdev_unregister(&leds_data[i].cdev);
4677 + gpio_free(leds_data[i].gpio);
4678 + }
4679 + }
4680 +
4681 + flush_scheduled_work();
4682 + kfree(leds_data);
4683 +
4684 + return ret;
4685 +}
4686 +
4687 +static int __exit gpio_led_remove(struct platform_device *pdev)
4688 +{
4689 + int i;
4690 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
4691 + struct gpio_led_data *leds_data;
4692 +
4693 + leds_data = platform_get_drvdata(pdev);
4694 +
4695 + for (i = 0; i < pdata->num_leds; i++) {
4696 + led_classdev_unregister(&leds_data[i].cdev);
4697 + gpio_free(leds_data[i].gpio);
4698 + }
4699 +
4700 + kfree(leds_data);
4701 +
4702 + return 0;
4703 +}
4704 +
4705 +#ifdef CONFIG_PM
4706 +static int gpio_led_suspend(struct platform_device *pdev, pm_message_t state)
4707 +{
4708 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
4709 + struct gpio_led_data *leds_data;
4710 + int i;
4711 +
4712 + leds_data = platform_get_drvdata(pdev);
4713 +
4714 + for (i = 0; i < pdata->num_leds; i++)
4715 + led_classdev_suspend(&leds_data[i].cdev);
4716 +
4717 + return 0;
4718 +}
4719 +
4720 +static int gpio_led_resume(struct platform_device *pdev)
4721 +{
4722 + struct gpio_led_platform_data *pdata = pdev->dev.platform_data;
4723 + struct gpio_led_data *leds_data;
4724 + int i;
4725 +
4726 + leds_data = platform_get_drvdata(pdev);
4727 +
4728 + for (i = 0; i < pdata->num_leds; i++)
4729 + led_classdev_resume(&leds_data[i].cdev);
4730 +
4731 + return 0;
4732 +}
4733 +#else
4734 +#define gpio_led_suspend NULL
4735 +#define gpio_led_resume NULL
4736 +#endif
4737 +
4738 +static struct platform_driver gpio_led_driver = {
4739 + .remove = __exit_p(gpio_led_remove),
4740 + .suspend = gpio_led_suspend,
4741 + .resume = gpio_led_resume,
4742 + .driver = {
4743 + .name = "leds-gpio",
4744 + .owner = THIS_MODULE,
4745 + },
4746 +};
4747 +
4748 +static int __init gpio_led_init(void)
4749 +{
4750 + return platform_driver_probe(&gpio_led_driver, gpio_led_probe);
4751 +}
4752 +
4753 +static void __exit gpio_led_exit(void)
4754 +{
4755 + platform_driver_unregister(&gpio_led_driver);
4756 +}
4757 +
4758 +module_init(gpio_led_init);
4759 +module_exit(gpio_led_exit);
4760 +
4761 +MODULE_AUTHOR("Raphael Assenat <raph@8d.com>");
4762 +MODULE_DESCRIPTION("GPIO LED driver");
4763 +MODULE_LICENSE("GPL");
4764 diff -x .git -Nur linux-2.6.22.1/drivers/leds/Makefile linux-avr32.git/drivers/leds/Makefile
4765 --- linux-2.6.22.1/drivers/leds/Makefile 2007-07-10 20:56:30.000000000 +0200
4766 +++ linux-avr32.git/drivers/leds/Makefile 2007-07-12 14:00:02.000000000 +0200
4767 @@ -16,6 +16,7 @@
4768 obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
4769 obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
4770 obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o
4771 +obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
4772
4773 # LED Triggers
4774 obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
4775 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/atmel-mci.c linux-avr32.git/drivers/mmc/host/atmel-mci.c
4776 --- linux-2.6.22.1/drivers/mmc/host/atmel-mci.c 1970-01-01 01:00:00.000000000 +0100
4777 +++ linux-avr32.git/drivers/mmc/host/atmel-mci.c 2007-07-12 14:00:03.000000000 +0200
4778 @@ -0,0 +1,1217 @@
4779 +/*
4780 + * Atmel MultiMedia Card Interface driver
4781 + *
4782 + * Copyright (C) 2004-2006 Atmel Corporation
4783 + *
4784 + * This program is free software; you can redistribute it and/or modify
4785 + * it under the terms of the GNU General Public License version 2 as
4786 + * published by the Free Software Foundation.
4787 + */
4788 +#include <linux/blkdev.h>
4789 +#include <linux/clk.h>
4790 +#include <linux/device.h>
4791 +#include <linux/dma-mapping.h>
4792 +#include <linux/init.h>
4793 +#include <linux/interrupt.h>
4794 +#include <linux/ioport.h>
4795 +#include <linux/module.h>
4796 +#include <linux/platform_device.h>
4797 +
4798 +#include <linux/mmc/host.h>
4799 +
4800 +#include <asm/dma-controller.h>
4801 +#include <asm/io.h>
4802 +#include <asm/arch/board.h>
4803 +#include <asm/arch/gpio.h>
4804 +
4805 +#include "atmel-mci.h"
4806 +
4807 +#define DRIVER_NAME "atmel_mci"
4808 +
4809 +#define MCI_CMD_ERROR_FLAGS (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | \
4810 + MCI_BIT(RCRCE) | MCI_BIT(RENDE) | \
4811 + MCI_BIT(RTOE))
4812 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
4813 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
4814 +
4815 +enum {
4816 + EVENT_CMD_COMPLETE = 0,
4817 + EVENT_CMD_ERROR,
4818 + EVENT_DATA_COMPLETE,
4819 + EVENT_DATA_ERROR,
4820 + EVENT_STOP_SENT,
4821 + EVENT_STOP_COMPLETE,
4822 + EVENT_STOP_ERROR,
4823 + EVENT_DMA_ERROR,
4824 + EVENT_CARD_DETECT,
4825 +};
4826 +
4827 +struct atmel_mci_dma {
4828 + struct dma_request_sg req;
4829 + unsigned short rx_periph_id;
4830 + unsigned short tx_periph_id;
4831 +};
4832 +
4833 +struct atmel_mci {
4834 + struct mmc_host *mmc;
4835 + void __iomem *regs;
4836 + struct atmel_mci_dma dma;
4837 +
4838 + struct mmc_request *mrq;
4839 + struct mmc_command *cmd;
4840 + struct mmc_data *data;
4841 +
4842 + u32 stop_cmdr;
4843 + u32 stop_iflags;
4844 +
4845 + struct tasklet_struct tasklet;
4846 + unsigned long pending_events;
4847 + unsigned long completed_events;
4848 + u32 error_status;
4849 +
4850 + int present;
4851 + int detect_pin;
4852 + int wp_pin;
4853 +
4854 + unsigned long bus_hz;
4855 + unsigned long mapbase;
4856 + struct clk *mck;
4857 + struct platform_device *pdev;
4858 +
4859 +#ifdef CONFIG_DEBUG_FS
4860 + struct dentry *debugfs_root;
4861 + struct dentry *debugfs_regs;
4862 + struct dentry *debugfs_req;
4863 + struct dentry *debugfs_pending_events;
4864 + struct dentry *debugfs_completed_events;
4865 +#endif
4866 +};
4867 +
4868 +/* Those printks take an awful lot of time... */
4869 +#ifndef DEBUG
4870 +static unsigned int fmax = 15000000U;
4871 +#else
4872 +static unsigned int fmax = 1000000U;
4873 +#endif
4874 +module_param(fmax, uint, 0444);
4875 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
4876 +
4877 +/* Test bit macros for completed events */
4878 +#define mci_cmd_is_complete(host) \
4879 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4880 +#define mci_cmd_error_is_complete(host) \
4881 + test_bit(EVENT_CMD_ERROR, &host->completed_events)
4882 +#define mci_data_is_complete(host) \
4883 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4884 +#define mci_data_error_is_complete(host) \
4885 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
4886 +#define mci_stop_sent_is_complete(host) \
4887 + test_bit(EVENT_STOP_SENT, &host->completed_events)
4888 +#define mci_stop_is_complete(host) \
4889 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4890 +#define mci_stop_error_is_complete(host) \
4891 + test_bit(EVENT_STOP_ERROR, &host->completed_events)
4892 +#define mci_dma_error_is_complete(host) \
4893 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
4894 +#define mci_card_detect_is_complete(host) \
4895 + test_bit(EVENT_CARD_DETECT, &host->completed_events)
4896 +
4897 +/* Test and clear bit macros for pending events */
4898 +#define mci_clear_cmd_is_pending(host) \
4899 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4900 +#define mci_clear_cmd_error_is_pending(host) \
4901 + test_and_clear_bit(EVENT_CMD_ERROR, &host->pending_events)
4902 +#define mci_clear_data_is_pending(host) \
4903 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4904 +#define mci_clear_data_error_is_pending(host) \
4905 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
4906 +#define mci_clear_stop_sent_is_pending(host) \
4907 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
4908 +#define mci_clear_stop_is_pending(host) \
4909 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4910 +#define mci_clear_stop_error_is_pending(host) \
4911 + test_and_clear_bit(EVENT_STOP_ERROR, &host->pending_events)
4912 +#define mci_clear_dma_error_is_pending(host) \
4913 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
4914 +#define mci_clear_card_detect_is_pending(host) \
4915 + test_and_clear_bit(EVENT_CARD_DETECT, &host->pending_events)
4916 +
4917 +/* Test and set bit macros for completed events */
4918 +#define mci_set_cmd_is_completed(host) \
4919 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4920 +#define mci_set_cmd_error_is_completed(host) \
4921 + test_and_set_bit(EVENT_CMD_ERROR, &host->completed_events)
4922 +#define mci_set_data_is_completed(host) \
4923 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4924 +#define mci_set_data_error_is_completed(host) \
4925 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
4926 +#define mci_set_stop_sent_is_completed(host) \
4927 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
4928 +#define mci_set_stop_is_completed(host) \
4929 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4930 +#define mci_set_stop_error_is_completed(host) \
4931 + test_and_set_bit(EVENT_STOP_ERROR, &host->completed_events)
4932 +#define mci_set_dma_error_is_completed(host) \
4933 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
4934 +#define mci_set_card_detect_is_completed(host) \
4935 + test_and_set_bit(EVENT_CARD_DETECT, &host->completed_events)
4936 +
4937 +/* Set bit macros for completed events */
4938 +#define mci_set_cmd_complete(host) \
4939 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4940 +#define mci_set_cmd_error_complete(host) \
4941 + set_bit(EVENT_CMD_ERROR, &host->completed_events)
4942 +#define mci_set_data_complete(host) \
4943 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4944 +#define mci_set_data_error_complete(host) \
4945 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
4946 +#define mci_set_stop_sent_complete(host) \
4947 + set_bit(EVENT_STOP_SENT, &host->completed_events)
4948 +#define mci_set_stop_complete(host) \
4949 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4950 +#define mci_set_stop_error_complete(host) \
4951 + set_bit(EVENT_STOP_ERROR, &host->completed_events)
4952 +#define mci_set_dma_error_complete(host) \
4953 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
4954 +#define mci_set_card_detect_complete(host) \
4955 + set_bit(EVENT_CARD_DETECT, &host->completed_events)
4956 +
4957 +/* Set bit macros for pending events */
4958 +#define mci_set_cmd_pending(host) \
4959 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4960 +#define mci_set_cmd_error_pending(host) \
4961 + set_bit(EVENT_CMD_ERROR, &host->pending_events)
4962 +#define mci_set_data_pending(host) \
4963 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4964 +#define mci_set_data_error_pending(host) \
4965 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
4966 +#define mci_set_stop_sent_pending(host) \
4967 + set_bit(EVENT_STOP_SENT, &host->pending_events)
4968 +#define mci_set_stop_pending(host) \
4969 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4970 +#define mci_set_stop_error_pending(host) \
4971 + set_bit(EVENT_STOP_ERROR, &host->pending_events)
4972 +#define mci_set_dma_error_pending(host) \
4973 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
4974 +#define mci_set_card_detect_pending(host) \
4975 + set_bit(EVENT_CARD_DETECT, &host->pending_events)
4976 +
4977 +/* Clear bit macros for pending events */
4978 +#define mci_clear_cmd_pending(host) \
4979 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4980 +#define mci_clear_cmd_error_pending(host) \
4981 + clear_bit(EVENT_CMD_ERROR, &host->pending_events)
4982 +#define mci_clear_data_pending(host) \
4983 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4984 +#define mci_clear_data_error_pending(host) \
4985 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
4986 +#define mci_clear_stop_sent_pending(host) \
4987 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
4988 +#define mci_clear_stop_pending(host) \
4989 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4990 +#define mci_clear_stop_error_pending(host) \
4991 + clear_bit(EVENT_STOP_ERROR, &host->pending_events)
4992 +#define mci_clear_dma_error_pending(host) \
4993 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
4994 +#define mci_clear_card_detect_pending(host) \
4995 + clear_bit(EVENT_CARD_DETECT, &host->pending_events)
4996 +
4997 +
4998 +#ifdef CONFIG_DEBUG_FS
4999 +#include <linux/debugfs.h>
5000 +
5001 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
5002 +
5003 +struct req_dbg_data {
5004 + unsigned int nbytes;
5005 + char str[DBG_REQ_BUF_SIZE];
5006 +};
5007 +
5008 +static int req_dbg_open(struct inode *inode, struct file *file)
5009 +{
5010 + struct atmel_mci *host;
5011 + struct mmc_request *mrq;
5012 + struct mmc_command *cmd, *stop;
5013 + struct mmc_data *data;
5014 + struct req_dbg_data *priv;
5015 + char *str;
5016 + unsigned long n = 0;
5017 +
5018 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
5019 + if (!priv)
5020 + return -ENOMEM;
5021 + str = priv->str;
5022 +
5023 + mutex_lock(&inode->i_mutex);
5024 + host = inode->i_private;
5025 +
5026 + spin_lock_irq(&host->mmc->lock);
5027 + mrq = host->mrq;
5028 + if (mrq) {
5029 + cmd = mrq->cmd;
5030 + data = mrq->data;
5031 + stop = mrq->stop;
5032 + n = snprintf(str, DBG_REQ_BUF_SIZE,
5033 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
5034 + cmd->opcode, cmd->arg, cmd->flags,
5035 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
5036 + cmd->resp[3], cmd->error);
5037 + if (n < DBG_REQ_BUF_SIZE && data)
5038 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
5039 + "DATA %u * %u (%u) %x (err %u)\n",
5040 + data->blocks, data->blksz,
5041 + data->bytes_xfered, data->flags,
5042 + data->error);
5043 + if (n < DBG_REQ_BUF_SIZE && stop)
5044 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
5045 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
5046 + stop->opcode, stop->arg, stop->flags,
5047 + stop->resp[0], stop->resp[1],
5048 + stop->resp[2], stop->resp[3],
5049 + stop->error);
5050 + }
5051 + spin_unlock_irq(&host->mmc->lock);
5052 + mutex_unlock(&inode->i_mutex);
5053 +
5054 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
5055 + file->private_data = priv;
5056 +
5057 + return 0;
5058 +}
5059 +
5060 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
5061 + size_t nbytes, loff_t *ppos)
5062 +{
5063 + struct req_dbg_data *priv = file->private_data;
5064 +
5065 + return simple_read_from_buffer(buf, nbytes, ppos,
5066 + priv->str, priv->nbytes);
5067 +}
5068 +
5069 +static int req_dbg_release(struct inode *inode, struct file *file)
5070 +{
5071 + kfree(file->private_data);
5072 + return 0;
5073 +}
5074 +
5075 +static const struct file_operations req_dbg_fops = {
5076 + .owner = THIS_MODULE,
5077 + .open = req_dbg_open,
5078 + .llseek = no_llseek,
5079 + .read = req_dbg_read,
5080 + .release = req_dbg_release,
5081 +};
5082 +
5083 +static int regs_dbg_open(struct inode *inode, struct file *file)
5084 +{
5085 + struct atmel_mci *host;
5086 + unsigned int i;
5087 + u32 *data;
5088 + int ret = -ENOMEM;
5089 +
5090 + mutex_lock(&inode->i_mutex);
5091 + host = inode->i_private;
5092 + data = kmalloc(inode->i_size, GFP_KERNEL);
5093 + if (!data)
5094 + goto out;
5095 +
5096 + spin_lock_irq(&host->mmc->lock);
5097 + for (i = 0; i < inode->i_size / 4; i++)
5098 + data[i] = __raw_readl(host->regs + i * 4);
5099 + spin_unlock_irq(&host->mmc->lock);
5100 +
5101 + file->private_data = data;
5102 + ret = 0;
5103 +
5104 +out:
5105 + mutex_unlock(&inode->i_mutex);
5106 +
5107 + return ret;
5108 +}
5109 +
5110 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
5111 + size_t nbytes, loff_t *ppos)
5112 +{
5113 + struct inode *inode = file->f_dentry->d_inode;
5114 + int ret;
5115 +
5116 + mutex_lock(&inode->i_mutex);
5117 + ret = simple_read_from_buffer(buf, nbytes, ppos,
5118 + file->private_data,
5119 + file->f_dentry->d_inode->i_size);
5120 + mutex_unlock(&inode->i_mutex);
5121 +
5122 + return ret;
5123 +}
5124 +
5125 +static int regs_dbg_release(struct inode *inode, struct file *file)
5126 +{
5127 + kfree(file->private_data);
5128 + return 0;
5129 +}
5130 +
5131 +static const struct file_operations regs_dbg_fops = {
5132 + .owner = THIS_MODULE,
5133 + .open = regs_dbg_open,
5134 + .llseek = generic_file_llseek,
5135 + .read = regs_dbg_read,
5136 + .release = regs_dbg_release,
5137 +};
5138 +
5139 +static void atmci_init_debugfs(struct atmel_mci *host)
5140 +{
5141 + struct mmc_host *mmc;
5142 + struct dentry *root, *regs;
5143 + struct resource *res;
5144 +
5145 + mmc = host->mmc;
5146 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
5147 + if (IS_ERR(root) || !root)
5148 + goto err_root;
5149 + host->debugfs_root = root;
5150 +
5151 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
5152 + if (!regs)
5153 + goto err_regs;
5154 +
5155 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
5156 + regs->d_inode->i_size = res->end - res->start + 1;
5157 + host->debugfs_regs = regs;
5158 +
5159 + host->debugfs_req = debugfs_create_file("req", 0400, root,
5160 + host, &req_dbg_fops);
5161 + if (!host->debugfs_req)
5162 + goto err_req;
5163 +
5164 + host->debugfs_pending_events
5165 + = debugfs_create_u32("pending_events", 0400, root,
5166 + (u32 *)&host->pending_events);
5167 + if (!host->debugfs_pending_events)
5168 + goto err_pending_events;
5169 +
5170 + host->debugfs_completed_events
5171 + = debugfs_create_u32("completed_events", 0400, root,
5172 + (u32 *)&host->completed_events);
5173 + if (!host->debugfs_completed_events)
5174 + goto err_completed_events;
5175 +
5176 + return;
5177 +
5178 +err_completed_events:
5179 + debugfs_remove(host->debugfs_pending_events);
5180 +err_pending_events:
5181 + debugfs_remove(host->debugfs_req);
5182 +err_req:
5183 + debugfs_remove(host->debugfs_regs);
5184 +err_regs:
5185 + debugfs_remove(host->debugfs_root);
5186 +err_root:
5187 + host->debugfs_root = NULL;
5188 + dev_err(&host->pdev->dev,
5189 + "failed to initialize debugfs for %s\n",
5190 + mmc_hostname(mmc));
5191 +}
5192 +
5193 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
5194 +{
5195 + if (host->debugfs_root) {
5196 + debugfs_remove(host->debugfs_completed_events);
5197 + debugfs_remove(host->debugfs_pending_events);
5198 + debugfs_remove(host->debugfs_req);
5199 + debugfs_remove(host->debugfs_regs);
5200 + debugfs_remove(host->debugfs_root);
5201 + host->debugfs_root = NULL;
5202 + }
5203 +}
5204 +#else
5205 +static inline void atmci_init_debugfs(struct atmel_mci *host)
5206 +{
5207 +
5208 +}
5209 +
5210 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
5211 +{
5212 +
5213 +}
5214 +#endif /* CONFIG_DEBUG_FS */
5215 +
5216 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
5217 + unsigned int ns)
5218 +{
5219 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
5220 +}
5221 +
5222 +static void atmci_set_timeout(struct atmel_mci *host,
5223 + struct mmc_data *data)
5224 +{
5225 + static unsigned dtomul_to_shift[] = {
5226 + 0, 4, 7, 8, 10, 12, 16, 20
5227 + };
5228 + unsigned timeout;
5229 + unsigned dtocyc, dtomul;
5230 +
5231 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
5232 +
5233 + for (dtomul = 0; dtomul < 8; dtomul++) {
5234 + unsigned shift = dtomul_to_shift[dtomul];
5235 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
5236 + if (dtocyc < 15)
5237 + break;
5238 + }
5239 +
5240 + if (dtomul >= 8) {
5241 + dtomul = 7;
5242 + dtocyc = 15;
5243 + }
5244 +
5245 + pr_debug("%s: setting timeout to %u cycles\n",
5246 + mmc_hostname(host->mmc),
5247 + dtocyc << dtomul_to_shift[dtomul]);
5248 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
5249 + | MCI_BF(DTOCYC, dtocyc)));
5250 +}
5251 +
5252 +/*
5253 + * Return mask with interrupt flags to be handled for this command.
5254 + */
5255 +static u32 atmci_prepare_command(struct mmc_host *mmc,
5256 + struct mmc_command *cmd,
5257 + u32 *cmd_flags)
5258 +{
5259 + u32 cmdr;
5260 + u32 iflags;
5261 +
5262 + cmd->error = MMC_ERR_NONE;
5263 +
5264 + cmdr = 0;
5265 + BUG_ON(MCI_BFEXT(CMDNB, cmdr) != 0);
5266 + cmdr = MCI_BFINS(CMDNB, cmd->opcode, cmdr);
5267 +
5268 + if (cmd->flags & MMC_RSP_PRESENT) {
5269 + if (cmd->flags & MMC_RSP_136)
5270 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
5271 + else
5272 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
5273 + }
5274 +
5275 + /*
5276 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
5277 + * it's too difficult to determine whether this is an ACMD or
5278 + * not. Better make it 64.
5279 + */
5280 + cmdr |= MCI_BIT(MAXLAT);
5281 +
5282 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
5283 + cmdr |= MCI_BIT(OPDCMD);
5284 +
5285 + iflags = MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS;
5286 + if (!(cmd->flags & MMC_RSP_CRC))
5287 + iflags &= ~MCI_BIT(RCRCE);
5288 +
5289 + pr_debug("%s: cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
5290 + mmc_hostname(mmc), cmd->opcode, cmd->arg, cmd->flags,
5291 + (unsigned long)cmdr);
5292 +
5293 + *cmd_flags = cmdr;
5294 + return iflags;
5295 +}
5296 +
5297 +static void atmci_start_command(struct atmel_mci *host,
5298 + struct mmc_command *cmd,
5299 + u32 cmd_flags)
5300 +{
5301 + WARN_ON(host->cmd);
5302 + host->cmd = cmd;
5303 +
5304 + mci_writel(host, ARGR, cmd->arg);
5305 + mci_writel(host, CMDR, cmd_flags);
5306 +
5307 + if (cmd->data)
5308 + dma_start_request(host->dma.req.req.dmac,
5309 + host->dma.req.req.channel);
5310 +}
5311 +
5312 +/*
5313 + * Returns a mask of flags to be set in the command register when the
5314 + * command to start the transfer is to be sent.
5315 + */
5316 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
5317 +{
5318 + struct atmel_mci *host = mmc_priv(mmc);
5319 + u32 cmd_flags;
5320 +
5321 + WARN_ON(host->data);
5322 + host->data = data;
5323 +
5324 + atmci_set_timeout(host, data);
5325 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
5326 + | MCI_BF(BLKLEN, data->blksz)));
5327 + host->dma.req.block_size = data->blksz;
5328 + host->dma.req.nr_blocks = data->blocks;
5329 +
5330 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
5331 + if (data->flags & MMC_DATA_STREAM)
5332 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
5333 + else if (data->blocks > 1)
5334 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
5335 + else
5336 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
5337 +
5338 + if (data->flags & MMC_DATA_READ) {
5339 + cmd_flags |= MCI_BIT(TRDIR);
5340 + host->dma.req.nr_sg
5341 + = dma_map_sg(&host->pdev->dev, data->sg,
5342 + data->sg_len, DMA_FROM_DEVICE);
5343 + host->dma.req.periph_id = host->dma.rx_periph_id;
5344 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
5345 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
5346 + } else {
5347 + host->dma.req.nr_sg
5348 + = dma_map_sg(&host->pdev->dev, data->sg,
5349 + data->sg_len, DMA_TO_DEVICE);
5350 + host->dma.req.periph_id = host->dma.tx_periph_id;
5351 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
5352 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
5353 + }
5354 + host->dma.req.sg = data->sg;
5355 +
5356 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
5357 +
5358 + return cmd_flags;
5359 +}
5360 +
5361 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
5362 +{
5363 + struct atmel_mci *host = mmc_priv(mmc);
5364 + struct mmc_data *data = mrq->data;
5365 + u32 iflags;
5366 + u32 cmdflags = 0;
5367 +
5368 + iflags = mci_readl(host, IMR);
5369 + if (iflags)
5370 + printk("WARNING: IMR=0x%08x\n", mci_readl(host, IMR));
5371 +
5372 + WARN_ON(host->mrq != NULL);
5373 + host->mrq = mrq;
5374 + host->pending_events = 0;
5375 + host->completed_events = 0;
5376 +
5377 + iflags = atmci_prepare_command(mmc, mrq->cmd, &cmdflags);
5378 +
5379 + if (mrq->stop) {
5380 + BUG_ON(!data);
5381 +
5382 + host->stop_iflags = atmci_prepare_command(mmc, mrq->stop,
5383 + &host->stop_cmdr);
5384 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
5385 + if (!(data->flags & MMC_DATA_WRITE))
5386 + host->stop_cmdr |= MCI_BIT(TRDIR);
5387 + if (data->flags & MMC_DATA_STREAM)
5388 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
5389 + else
5390 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
5391 + }
5392 + if (data) {
5393 + cmdflags |= atmci_prepare_data(mmc, data);
5394 + iflags |= MCI_DATA_ERROR_FLAGS;
5395 + }
5396 +
5397 + atmci_start_command(host, mrq->cmd, cmdflags);
5398 + mci_writel(host, IER, iflags);
5399 +}
5400 +
5401 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
5402 +{
5403 + struct atmel_mci *host = mmc_priv(mmc);
5404 +
5405 + if (ios->clock) {
5406 + u32 clkdiv;
5407 +
5408 + clkdiv = host->bus_hz / (2 * ios->clock) - 1;
5409 + if (clkdiv > 255)
5410 + clkdiv = 255;
5411 + mci_writel(host, MR, (clkdiv
5412 + | MCI_BIT(WRPROOF)
5413 + | MCI_BIT(RDPROOF)));
5414 + }
5415 +
5416 + switch (ios->bus_width) {
5417 + case MMC_BUS_WIDTH_1:
5418 + mci_writel(host, SDCR, 0);
5419 + break;
5420 + case MMC_BUS_WIDTH_4:
5421 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
5422 + break;
5423 + }
5424 +
5425 + switch (ios->power_mode) {
5426 + case MMC_POWER_OFF:
5427 + mci_writel(host, CR, MCI_BIT(MCIDIS));
5428 + break;
5429 + case MMC_POWER_UP:
5430 + mci_writel(host, CR, MCI_BIT(SWRST));
5431 + break;
5432 + case MMC_POWER_ON:
5433 + mci_writel(host, CR, MCI_BIT(MCIEN));
5434 + break;
5435 + }
5436 +}
5437 +
5438 +static int atmci_get_ro(struct mmc_host *mmc)
5439 +{
5440 + int read_only = 0;
5441 + struct atmel_mci *host = mmc_priv(mmc);
5442 +
5443 + if (host->wp_pin >= 0) {
5444 + read_only = gpio_get_value(host->wp_pin);
5445 + pr_debug("%s: card is %s\n", mmc_hostname(mmc),
5446 + read_only ? "read-only" : "read-write");
5447 + } else {
5448 + pr_debug("%s: no pin for checking read-only switch."
5449 + " Assuming write-enable.\n", mmc_hostname(mmc));
5450 + }
5451 +
5452 + return read_only;
5453 +}
5454 +
5455 +static struct mmc_host_ops atmci_ops = {
5456 + .request = atmci_request,
5457 + .set_ios = atmci_set_ios,
5458 + .get_ro = atmci_get_ro,
5459 +};
5460 +
5461 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
5462 +{
5463 + struct atmel_mci *host = mmc_priv(mmc);
5464 +
5465 + WARN_ON(host->cmd || host->data);
5466 + host->mrq = NULL;
5467 +
5468 + mmc_request_done(mmc, mrq);
5469 +}
5470 +
5471 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
5472 + u32 flags)
5473 +{
5474 + struct atmel_mci *host = mmc_priv(mmc);
5475 +
5476 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
5477 + mci_writel(host, IER, host->stop_iflags);
5478 +}
5479 +
5480 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
5481 +{
5482 + host->data = NULL;
5483 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
5484 + ((data->flags & MMC_DATA_WRITE)
5485 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
5486 +
5487 + /*
5488 + * Data might complete before command for very short transfers
5489 + * (like READ_SCR)
5490 + */
5491 + if (mci_cmd_is_complete(host)
5492 + && (!data->stop || mci_stop_is_complete(host)))
5493 + atmci_request_end(host->mmc, data->mrq);
5494 +}
5495 +
5496 +static void atmci_command_error(struct mmc_host *mmc,
5497 + struct mmc_command *cmd,
5498 + u32 status)
5499 +{
5500 + pr_debug("%s: command error: status=0x%08x\n",
5501 + mmc_hostname(mmc), status);
5502 +
5503 + if (status & MCI_BIT(RTOE))
5504 + cmd->error = MMC_ERR_TIMEOUT;
5505 + else if (status & MCI_BIT(RCRCE))
5506 + cmd->error = MMC_ERR_BADCRC;
5507 + else
5508 + cmd->error = MMC_ERR_FAILED;
5509 +}
5510 +
5511 +static void atmci_tasklet_func(unsigned long priv)
5512 +{
5513 + struct mmc_host *mmc = (struct mmc_host *)priv;
5514 + struct atmel_mci *host = mmc_priv(mmc);
5515 + struct mmc_request *mrq = host->mrq;
5516 + struct mmc_data *data = host->data;
5517 +
5518 + pr_debug("atmci_tasklet: pending/completed/mask %lx/%lx/%x\n",
5519 + host->pending_events, host->completed_events,
5520 + mci_readl(host, IMR));
5521 +
5522 + if (mci_clear_cmd_error_is_pending(host)) {
5523 + struct mmc_command *cmd;
5524 +
5525 + mci_set_cmd_error_complete(host);
5526 + mci_clear_cmd_pending(host);
5527 + cmd = host->mrq->cmd;
5528 +
5529 + if (cmd->data) {
5530 + dma_stop_request(host->dma.req.req.dmac,
5531 + host->dma.req.req.channel);
5532 + host->data = NULL;
5533 + }
5534 +
5535 + atmci_command_error(mmc, cmd, host->error_status);
5536 + atmci_request_end(mmc, cmd->mrq);
5537 + }
5538 + if (mci_clear_stop_error_is_pending(host)) {
5539 + mci_set_stop_error_complete(host);
5540 + mci_clear_stop_pending(host);
5541 + atmci_command_error(mmc, host->mrq->stop,
5542 + host->error_status);
5543 + if (!host->data)
5544 + atmci_request_end(mmc, host->mrq);
5545 + }
5546 + if (mci_clear_cmd_is_pending(host)) {
5547 + mci_set_cmd_complete(host);
5548 + if (!mrq->data || mci_data_is_complete(host)
5549 + || mci_data_error_is_complete(host))
5550 + atmci_request_end(mmc, mrq);
5551 + }
5552 + if (mci_clear_stop_is_pending(host)) {
5553 + mci_set_stop_complete(host);
5554 + if (mci_data_is_complete(host)
5555 + || mci_data_error_is_complete(host))
5556 + atmci_request_end(mmc, mrq);
5557 + }
5558 + if (mci_clear_dma_error_is_pending(host)) {
5559 + mci_set_dma_error_complete(host);
5560 + mci_clear_data_pending(host);
5561 +
5562 + /* DMA controller got bus error => invalid address */
5563 + data->error = MMC_ERR_INVALID;
5564 +
5565 + printk(KERN_DEBUG "%s: dma error after %u bytes xfered\n",
5566 + mmc_hostname(mmc), host->data->bytes_xfered);
5567 +
5568 + if (data->stop
5569 + && !mci_set_stop_sent_is_completed(host))
5570 + /* TODO: Check if card is still present */
5571 + send_stop_cmd(host->mmc, data, 0);
5572 +
5573 + atmci_data_complete(host, data);
5574 + }
5575 + if (mci_clear_data_error_is_pending(host)) {
5576 + u32 status = host->error_status;
5577 +
5578 + mci_set_data_error_complete(host);
5579 + mci_clear_data_pending(host);
5580 +
5581 + dma_stop_request(host->dma.req.req.dmac,
5582 + host->dma.req.req.channel);
5583 +
5584 + printk(KERN_DEBUG "%s: data error: status=0x%08x\n",
5585 + mmc_hostname(host->mmc), status);
5586 +
5587 + if (status & MCI_BIT(DCRCE)) {
5588 + printk(KERN_DEBUG "%s: Data CRC error\n",
5589 + mmc_hostname(host->mmc));
5590 + data->error = MMC_ERR_BADCRC;
5591 + } else if (status & MCI_BIT(DTOE)) {
5592 + printk(KERN_DEBUG "%s: Data Timeout error\n",
5593 + mmc_hostname(host->mmc));
5594 + data->error = MMC_ERR_TIMEOUT;
5595 + } else {
5596 + printk(KERN_DEBUG "%s: Data FIFO error\n",
5597 + mmc_hostname(host->mmc));
5598 + data->error = MMC_ERR_FIFO;
5599 + }
5600 + printk(KERN_DEBUG "%s: Bytes xfered: %u\n",
5601 + mmc_hostname(host->mmc), data->bytes_xfered);
5602 +
5603 + if (data->stop
5604 + && !mci_set_stop_sent_is_completed(host))
5605 + /* TODO: Check if card is still present */
5606 + send_stop_cmd(host->mmc, data, 0);
5607 +
5608 + atmci_data_complete(host, data);
5609 + }
5610 + if (mci_clear_data_is_pending(host)) {
5611 + mci_set_data_complete(host);
5612 + data->bytes_xfered = data->blocks * data->blksz;
5613 + atmci_data_complete(host, data);
5614 + }
5615 + if (mci_clear_card_detect_is_pending(host)) {
5616 + /* Reset controller if card is gone */
5617 + if (!host->present) {
5618 + mci_writel(host, CR, MCI_BIT(SWRST));
5619 + mci_writel(host, IDR, ~0UL);
5620 + mci_writel(host, CR, MCI_BIT(MCIEN));
5621 + }
5622 +
5623 + /* Clean up queue if present */
5624 + if (mrq) {
5625 + if (!mci_cmd_is_complete(host)
5626 + && !mci_cmd_error_is_complete(host)) {
5627 + mrq->cmd->error = MMC_ERR_TIMEOUT;
5628 + }
5629 + if (mrq->data && !mci_data_is_complete(host)
5630 + && !mci_data_error_is_complete(host)) {
5631 + dma_stop_request(host->dma.req.req.dmac,
5632 + host->dma.req.req.channel);
5633 + host->data->error = MMC_ERR_TIMEOUT;
5634 + atmci_data_complete(host, data);
5635 + }
5636 + if (mrq->stop && !mci_stop_is_complete(host)
5637 + && !mci_stop_error_is_complete(host)) {
5638 + mrq->stop->error = MMC_ERR_TIMEOUT;
5639 + }
5640 +
5641 + host->cmd = NULL;
5642 + atmci_request_end(mmc, mrq);
5643 + }
5644 + mmc_detect_change(host->mmc, msecs_to_jiffies(100));
5645 + }
5646 +}
5647 +
5648 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
5649 +{
5650 + struct atmel_mci *host = mmc_priv(mmc);
5651 + struct mmc_command *cmd = host->cmd;
5652 +
5653 + /*
5654 + * Read the response now so that we're free to send a new
5655 + * command immediately.
5656 + */
5657 + cmd->resp[0] = mci_readl(host, RSPR);
5658 + cmd->resp[1] = mci_readl(host, RSPR);
5659 + cmd->resp[2] = mci_readl(host, RSPR);
5660 + cmd->resp[3] = mci_readl(host, RSPR);
5661 +
5662 + mci_writel(host, IDR, MCI_BIT(CMDRDY) | MCI_CMD_ERROR_FLAGS);
5663 + host->cmd = NULL;
5664 +
5665 + if (mci_stop_sent_is_complete(host))
5666 + mci_set_stop_pending(host);
5667 + else
5668 + mci_set_cmd_pending(host);
5669 +
5670 + tasklet_schedule(&host->tasklet);
5671 +}
5672 +
5673 +static void atmci_xfer_complete(struct dma_request *_req)
5674 +{
5675 + struct dma_request_sg *req = to_dma_request_sg(_req);
5676 + struct atmel_mci_dma *dma;
5677 + struct atmel_mci *host;
5678 + struct mmc_data *data;
5679 +
5680 + dma = container_of(req, struct atmel_mci_dma, req);
5681 + host = container_of(dma, struct atmel_mci, dma);
5682 + data = host->data;
5683 +
5684 + if (data->stop && !mci_set_stop_sent_is_completed(host))
5685 + send_stop_cmd(host->mmc, data, 0);
5686 +
5687 + if (data->flags & MMC_DATA_READ) {
5688 + mci_writel(host, IDR, MCI_DATA_ERROR_FLAGS);
5689 + mci_set_data_pending(host);
5690 + tasklet_schedule(&host->tasklet);
5691 + } else {
5692 + /*
5693 + * For the WRITE case, wait for NOTBUSY. This function
5694 + * is called when everything has been written to the
5695 + * controller, not when the card is done programming.
5696 + */
5697 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
5698 + }
5699 +}
5700 +
5701 +static void atmci_dma_error(struct dma_request *_req)
5702 +{
5703 + struct dma_request_sg *req = to_dma_request_sg(_req);
5704 + struct atmel_mci_dma *dma;
5705 + struct atmel_mci *host;
5706 +
5707 + dma = container_of(req, struct atmel_mci_dma, req);
5708 + host = container_of(dma, struct atmel_mci, dma);
5709 +
5710 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5711 + | MCI_DATA_ERROR_FLAGS));
5712 +
5713 + mci_set_dma_error_pending(host);
5714 + tasklet_schedule(&host->tasklet);
5715 +}
5716 +
5717 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
5718 +{
5719 + struct mmc_host *mmc = dev_id;
5720 + struct atmel_mci *host = mmc_priv(mmc);
5721 + u32 status, mask, pending;
5722 +
5723 + spin_lock(&mmc->lock);
5724 +
5725 + status = mci_readl(host, SR);
5726 + mask = mci_readl(host, IMR);
5727 + pending = status & mask;
5728 +
5729 + do {
5730 + if (pending & MCI_CMD_ERROR_FLAGS) {
5731 + mci_writel(host, IDR, (MCI_BIT(CMDRDY)
5732 + | MCI_BIT(NOTBUSY)
5733 + | MCI_CMD_ERROR_FLAGS
5734 + | MCI_DATA_ERROR_FLAGS));
5735 + host->error_status = status;
5736 + host->cmd = NULL;
5737 + if (mci_stop_sent_is_complete(host))
5738 + mci_set_stop_error_pending(host);
5739 + else
5740 + mci_set_cmd_error_pending(host);
5741 + tasklet_schedule(&host->tasklet);
5742 + break;
5743 + }
5744 + if (pending & MCI_DATA_ERROR_FLAGS) {
5745 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5746 + | MCI_DATA_ERROR_FLAGS));
5747 + host->error_status = status;
5748 + mci_set_data_error_pending(host);
5749 + tasklet_schedule(&host->tasklet);
5750 + break;
5751 + }
5752 + if (pending & MCI_BIT(CMDRDY))
5753 + atmci_cmd_interrupt(mmc, status);
5754 + if (pending & MCI_BIT(NOTBUSY)) {
5755 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5756 + | MCI_DATA_ERROR_FLAGS));
5757 + mci_set_data_pending(host);
5758 + tasklet_schedule(&host->tasklet);
5759 + }
5760 +
5761 + status = mci_readl(host, SR);
5762 + mask = mci_readl(host, IMR);
5763 + pending = status & mask;
5764 + } while (pending);
5765 +
5766 + spin_unlock(&mmc->lock);
5767 +
5768 + return IRQ_HANDLED;
5769 +}
5770 +
5771 +static irqreturn_t atmci_detect_change(int irq, void *dev_id)
5772 +{
5773 + struct mmc_host *mmc = dev_id;
5774 + struct atmel_mci *host = mmc_priv(mmc);
5775 +
5776 + int present = !gpio_get_value(irq_to_gpio(irq));
5777 +
5778 + if (present != host->present) {
5779 + pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
5780 + present ? "inserted" : "removed");
5781 + host->present = present;
5782 + mci_set_card_detect_pending(host);
5783 + tasklet_schedule(&host->tasklet);
5784 + }
5785 + return IRQ_HANDLED;
5786 +}
5787 +
5788 +static int __devinit atmci_probe(struct platform_device *pdev)
5789 +{
5790 + struct mci_platform_data *board;
5791 + struct atmel_mci *host;
5792 + struct mmc_host *mmc;
5793 + struct resource *regs;
5794 + int irq;
5795 + int ret;
5796 +
5797 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5798 + if (!regs)
5799 + return -ENXIO;
5800 + irq = platform_get_irq(pdev, 0);
5801 + if (irq < 0)
5802 + return irq;
5803 +
5804 + board = pdev->dev.platform_data;
5805 +
5806 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
5807 + if (!mmc)
5808 + return -ENOMEM;
5809 +
5810 + host = mmc_priv(mmc);
5811 + host->pdev = pdev;
5812 + host->mmc = mmc;
5813 + if (board) {
5814 + host->detect_pin = board->detect_pin;
5815 + host->wp_pin = board->wp_pin;
5816 + } else {
5817 + host->detect_pin = -1;
5818 + host->detect_pin = -1;
5819 + }
5820 +
5821 + host->mck = clk_get(&pdev->dev, "mci_clk");
5822 + if (IS_ERR(host->mck)) {
5823 + ret = PTR_ERR(host->mck);
5824 + goto out_free_host;
5825 + }
5826 + clk_enable(host->mck);
5827 +
5828 + ret = -ENOMEM;
5829 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
5830 + if (!host->regs)
5831 + goto out_disable_clk;
5832 +
5833 + host->bus_hz = clk_get_rate(host->mck);
5834 + host->mapbase = regs->start;
5835 +
5836 + mmc->ops = &atmci_ops;
5837 + mmc->f_min = (host->bus_hz + 511) / 512;
5838 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
5839 + mmc->ocr_avail = 0x00100000;
5840 + mmc->caps |= MMC_CAP_4_BIT_DATA;
5841 +
5842 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
5843 +
5844 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
5845 + if (ret)
5846 + goto out_unmap;
5847 +
5848 + /* Assume card is present if we don't have a detect pin */
5849 + host->present = 1;
5850 + if (host->detect_pin >= 0) {
5851 + if (gpio_request(host->detect_pin, "mmc_detect")) {
5852 + printk(KERN_WARNING "%s: no detect pin available\n",
5853 + mmc_hostname(host->mmc));
5854 + host->detect_pin = -1;
5855 + } else {
5856 + host->present = !gpio_get_value(host->detect_pin);
5857 + }
5858 + }
5859 + if (host->wp_pin >= 0) {
5860 + if (gpio_request(host->wp_pin, "mmc_wp")) {
5861 + printk(KERN_WARNING "%s: no WP pin available\n",
5862 + mmc_hostname(host->mmc));
5863 + host->wp_pin = -1;
5864 + }
5865 + }
5866 +
5867 + /* TODO: Get this information from platform data */
5868 + ret = -ENOMEM;
5869 + host->dma.req.req.dmac = find_dma_controller(0);
5870 + if (!host->dma.req.req.dmac) {
5871 + printk(KERN_ERR
5872 + "mmci: No DMA controller available, aborting\n");
5873 + goto out_free_irq;
5874 + }
5875 + ret = dma_alloc_channel(host->dma.req.req.dmac);
5876 + if (ret < 0) {
5877 + printk(KERN_ERR
5878 + "mmci: Unable to allocate DMA channel, aborting\n");
5879 + goto out_free_irq;
5880 + }
5881 + host->dma.req.req.channel = ret;
5882 + host->dma.req.width = DMA_WIDTH_32BIT;
5883 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
5884 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
5885 + host->dma.req.req.error = atmci_dma_error;
5886 + host->dma.rx_periph_id = 0;
5887 + host->dma.tx_periph_id = 1;
5888 +
5889 + mci_writel(host, CR, MCI_BIT(SWRST));
5890 + mci_writel(host, IDR, ~0UL);
5891 + mci_writel(host, CR, MCI_BIT(MCIEN));
5892 +
5893 + platform_set_drvdata(pdev, host);
5894 +
5895 + mmc_add_host(mmc);
5896 +
5897 + if (host->detect_pin >= 0) {
5898 + ret = request_irq(gpio_to_irq(host->detect_pin),
5899 + atmci_detect_change,
5900 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
5901 + DRIVER_NAME, mmc);
5902 + if (ret) {
5903 + printk(KERN_ERR
5904 + "%s: could not request IRQ %d for detect pin\n",
5905 + mmc_hostname(mmc),
5906 + gpio_to_irq(host->detect_pin));
5907 + gpio_free(host->detect_pin);
5908 + host->detect_pin = -1;
5909 + }
5910 + }
5911 +
5912 + printk(KERN_INFO "%s: Atmel MCI controller at 0x%08lx irq %d\n",
5913 + mmc_hostname(mmc), host->mapbase, irq);
5914 +
5915 + atmci_init_debugfs(host);
5916 +
5917 + return 0;
5918 +
5919 +out_free_irq:
5920 + if (host->detect_pin >= 0)
5921 + gpio_free(host->detect_pin);
5922 + if (host->wp_pin >= 0)
5923 + gpio_free(host->wp_pin);
5924 + free_irq(irq, mmc);
5925 +out_unmap:
5926 + iounmap(host->regs);
5927 +out_disable_clk:
5928 + clk_disable(host->mck);
5929 + clk_put(host->mck);
5930 +out_free_host:
5931 + mmc_free_host(mmc);
5932 + return ret;
5933 +}
5934 +
5935 +static int __devexit atmci_remove(struct platform_device *pdev)
5936 +{
5937 + struct atmel_mci *host = platform_get_drvdata(pdev);
5938 +
5939 + platform_set_drvdata(pdev, NULL);
5940 +
5941 + if (host) {
5942 + atmci_cleanup_debugfs(host);
5943 +
5944 + if (host->detect_pin >= 0) {
5945 + free_irq(gpio_to_irq(host->detect_pin), host->mmc);
5946 + cancel_delayed_work(&host->mmc->detect);
5947 + gpio_free(host->detect_pin);
5948 + }
5949 +
5950 + mmc_remove_host(host->mmc);
5951 +
5952 + mci_writel(host, IDR, ~0UL);
5953 + mci_writel(host, CR, MCI_BIT(MCIDIS));
5954 + mci_readl(host, SR);
5955 +
5956 + dma_release_channel(host->dma.req.req.dmac,
5957 + host->dma.req.req.channel);
5958 +
5959 + if (host->wp_pin >= 0)
5960 + gpio_free(host->wp_pin);
5961 +
5962 + free_irq(platform_get_irq(pdev, 0), host->mmc);
5963 + iounmap(host->regs);
5964 +
5965 + clk_disable(host->mck);
5966 + clk_put(host->mck);
5967 +
5968 + mmc_free_host(host->mmc);
5969 + }
5970 + return 0;
5971 +}
5972 +
5973 +static struct platform_driver atmci_driver = {
5974 + .probe = atmci_probe,
5975 + .remove = __devexit_p(atmci_remove),
5976 + .driver = {
5977 + .name = DRIVER_NAME,
5978 + },
5979 +};
5980 +
5981 +static int __init atmci_init(void)
5982 +{
5983 + return platform_driver_register(&atmci_driver);
5984 +}
5985 +
5986 +static void __exit atmci_exit(void)
5987 +{
5988 + platform_driver_unregister(&atmci_driver);
5989 +}
5990 +
5991 +module_init(atmci_init);
5992 +module_exit(atmci_exit);
5993 +
5994 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
5995 +MODULE_LICENSE("GPL");
5996 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/atmel-mci.h linux-avr32.git/drivers/mmc/host/atmel-mci.h
5997 --- linux-2.6.22.1/drivers/mmc/host/atmel-mci.h 1970-01-01 01:00:00.000000000 +0100
5998 +++ linux-avr32.git/drivers/mmc/host/atmel-mci.h 2007-07-12 14:00:03.000000000 +0200
5999 @@ -0,0 +1,192 @@
6000 +/*
6001 + * Atmel MultiMedia Card Interface driver
6002 + *
6003 + * Copyright (C) 2004-2006 Atmel Corporation
6004 + *
6005 + * This program is free software; you can redistribute it and/or modify
6006 + * it under the terms of the GNU General Public License version 2 as
6007 + * published by the Free Software Foundation.
6008 + */
6009 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
6010 +#define __DRIVERS_MMC_ATMEL_MCI_H__
6011 +
6012 +/* MCI register offsets */
6013 +#define MCI_CR 0x0000
6014 +#define MCI_MR 0x0004
6015 +#define MCI_DTOR 0x0008
6016 +#define MCI_SDCR 0x000c
6017 +#define MCI_ARGR 0x0010
6018 +#define MCI_CMDR 0x0014
6019 +#define MCI_BLKR 0x0018
6020 +#define MCI_RSPR 0x0020
6021 +#define MCI_RSPR1 0x0024
6022 +#define MCI_RSPR2 0x0028
6023 +#define MCI_RSPR3 0x002c
6024 +#define MCI_RDR 0x0030
6025 +#define MCI_TDR 0x0034
6026 +#define MCI_SR 0x0040
6027 +#define MCI_IER 0x0044
6028 +#define MCI_IDR 0x0048
6029 +#define MCI_IMR 0x004c
6030 +
6031 +/* Bitfields in CR */
6032 +#define MCI_MCIEN_OFFSET 0
6033 +#define MCI_MCIEN_SIZE 1
6034 +#define MCI_MCIDIS_OFFSET 1
6035 +#define MCI_MCIDIS_SIZE 1
6036 +#define MCI_PWSEN_OFFSET 2
6037 +#define MCI_PWSEN_SIZE 1
6038 +#define MCI_PWSDIS_OFFSET 3
6039 +#define MCI_PWSDIS_SIZE 1
6040 +#define MCI_SWRST_OFFSET 7
6041 +#define MCI_SWRST_SIZE 1
6042 +
6043 +/* Bitfields in MR */
6044 +#define MCI_CLKDIV_OFFSET 0
6045 +#define MCI_CLKDIV_SIZE 8
6046 +#define MCI_PWSDIV_OFFSET 8
6047 +#define MCI_PWSDIV_SIZE 3
6048 +#define MCI_RDPROOF_OFFSET 11
6049 +#define MCI_RDPROOF_SIZE 1
6050 +#define MCI_WRPROOF_OFFSET 12
6051 +#define MCI_WRPROOF_SIZE 1
6052 +#define MCI_DMAPADV_OFFSET 14
6053 +#define MCI_DMAPADV_SIZE 1
6054 +#define MCI_BLKLEN_OFFSET 16
6055 +#define MCI_BLKLEN_SIZE 16
6056 +
6057 +/* Bitfields in DTOR */
6058 +#define MCI_DTOCYC_OFFSET 0
6059 +#define MCI_DTOCYC_SIZE 4
6060 +#define MCI_DTOMUL_OFFSET 4
6061 +#define MCI_DTOMUL_SIZE 3
6062 +
6063 +/* Bitfields in SDCR */
6064 +#define MCI_SDCSEL_OFFSET 0
6065 +#define MCI_SDCSEL_SIZE 4
6066 +#define MCI_SDCBUS_OFFSET 7
6067 +#define MCI_SDCBUS_SIZE 1
6068 +
6069 +/* Bitfields in ARGR */
6070 +#define MCI_ARG_OFFSET 0
6071 +#define MCI_ARG_SIZE 32
6072 +
6073 +/* Bitfields in CMDR */
6074 +#define MCI_CMDNB_OFFSET 0
6075 +#define MCI_CMDNB_SIZE 6
6076 +#define MCI_RSPTYP_OFFSET 6
6077 +#define MCI_RSPTYP_SIZE 2
6078 +#define MCI_SPCMD_OFFSET 8
6079 +#define MCI_SPCMD_SIZE 3
6080 +#define MCI_OPDCMD_OFFSET 11
6081 +#define MCI_OPDCMD_SIZE 1
6082 +#define MCI_MAXLAT_OFFSET 12
6083 +#define MCI_MAXLAT_SIZE 1
6084 +#define MCI_TRCMD_OFFSET 16
6085 +#define MCI_TRCMD_SIZE 2
6086 +#define MCI_TRDIR_OFFSET 18
6087 +#define MCI_TRDIR_SIZE 1
6088 +#define MCI_TRTYP_OFFSET 19
6089 +#define MCI_TRTYP_SIZE 2
6090 +
6091 +/* Bitfields in BLKR */
6092 +#define MCI_BCNT_OFFSET 0
6093 +#define MCI_BCNT_SIZE 16
6094 +
6095 +/* Bitfields in RSPRn */
6096 +#define MCI_RSP_OFFSET 0
6097 +#define MCI_RSP_SIZE 32
6098 +
6099 +/* Bitfields in SR/IER/IDR/IMR */
6100 +#define MCI_CMDRDY_OFFSET 0
6101 +#define MCI_CMDRDY_SIZE 1
6102 +#define MCI_RXRDY_OFFSET 1
6103 +#define MCI_RXRDY_SIZE 1
6104 +#define MCI_TXRDY_OFFSET 2
6105 +#define MCI_TXRDY_SIZE 1
6106 +#define MCI_BLKE_OFFSET 3
6107 +#define MCI_BLKE_SIZE 1
6108 +#define MCI_DTIP_OFFSET 4
6109 +#define MCI_DTIP_SIZE 1
6110 +#define MCI_NOTBUSY_OFFSET 5
6111 +#define MCI_NOTBUSY_SIZE 1
6112 +#define MCI_ENDRX_OFFSET 6
6113 +#define MCI_ENDRX_SIZE 1
6114 +#define MCI_ENDTX_OFFSET 7
6115 +#define MCI_ENDTX_SIZE 1
6116 +#define MCI_RXBUFF_OFFSET 14
6117 +#define MCI_RXBUFF_SIZE 1
6118 +#define MCI_TXBUFE_OFFSET 15
6119 +#define MCI_TXBUFE_SIZE 1
6120 +#define MCI_RINDE_OFFSET 16
6121 +#define MCI_RINDE_SIZE 1
6122 +#define MCI_RDIRE_OFFSET 17
6123 +#define MCI_RDIRE_SIZE 1
6124 +#define MCI_RCRCE_OFFSET 18
6125 +#define MCI_RCRCE_SIZE 1
6126 +#define MCI_RENDE_OFFSET 19
6127 +#define MCI_RENDE_SIZE 1
6128 +#define MCI_RTOE_OFFSET 20
6129 +#define MCI_RTOE_SIZE 1
6130 +#define MCI_DCRCE_OFFSET 21
6131 +#define MCI_DCRCE_SIZE 1
6132 +#define MCI_DTOE_OFFSET 22
6133 +#define MCI_DTOE_SIZE 1
6134 +#define MCI_OVRE_OFFSET 30
6135 +#define MCI_OVRE_SIZE 1
6136 +#define MCI_UNRE_OFFSET 31
6137 +#define MCI_UNRE_SIZE 1
6138 +
6139 +/* Constants for DTOMUL */
6140 +#define MCI_DTOMUL_1_CYCLE 0
6141 +#define MCI_DTOMUL_16_CYCLES 1
6142 +#define MCI_DTOMUL_128_CYCLES 2
6143 +#define MCI_DTOMUL_256_CYCLES 3
6144 +#define MCI_DTOMUL_1024_CYCLES 4
6145 +#define MCI_DTOMUL_4096_CYCLES 5
6146 +#define MCI_DTOMUL_65536_CYCLES 6
6147 +#define MCI_DTOMUL_1048576_CYCLES 7
6148 +
6149 +/* Constants for RSPTYP */
6150 +#define MCI_RSPTYP_NO_RESP 0
6151 +#define MCI_RSPTYP_48_BIT 1
6152 +#define MCI_RSPTYP_136_BIT 2
6153 +
6154 +/* Constants for SPCMD */
6155 +#define MCI_SPCMD_NO_SPEC_CMD 0
6156 +#define MCI_SPCMD_INIT_CMD 1
6157 +#define MCI_SPCMD_SYNC_CMD 2
6158 +#define MCI_SPCMD_INT_CMD 4
6159 +#define MCI_SPCMD_INT_RESP 5
6160 +
6161 +/* Constants for TRCMD */
6162 +#define MCI_TRCMD_NO_TRANS 0
6163 +#define MCI_TRCMD_START_TRANS 1
6164 +#define MCI_TRCMD_STOP_TRANS 2
6165 +
6166 +/* Constants for TRTYP */
6167 +#define MCI_TRTYP_BLOCK 0
6168 +#define MCI_TRTYP_MULTI_BLOCK 1
6169 +#define MCI_TRTYP_STREAM 2
6170 +
6171 +/* Bit manipulation macros */
6172 +#define MCI_BIT(name) \
6173 + (1 << MCI_##name##_OFFSET)
6174 +#define MCI_BF(name,value) \
6175 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
6176 + << MCI_##name##_OFFSET)
6177 +#define MCI_BFEXT(name,value) \
6178 + (((value) >> MCI_##name##_OFFSET) \
6179 + & ((1 << MCI_##name##_SIZE) - 1))
6180 +#define MCI_BFINS(name,value,old) \
6181 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
6182 + << MCI_##name##_OFFSET)) \
6183 + | MCI_BF(name,value))
6184 +
6185 +/* Register access macros */
6186 +#define mci_readl(port,reg) \
6187 + __raw_readl((port)->regs + MCI_##reg)
6188 +#define mci_writel(port,reg,value) \
6189 + __raw_writel((value), (port)->regs + MCI_##reg)
6190 +
6191 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
6192 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/Kconfig linux-avr32.git/drivers/mmc/host/Kconfig
6193 --- linux-2.6.22.1/drivers/mmc/host/Kconfig 2007-07-10 20:56:30.000000000 +0200
6194 +++ linux-avr32.git/drivers/mmc/host/Kconfig 2007-07-12 14:00:03.000000000 +0200
6195 @@ -74,6 +74,16 @@
6196
6197 If unsure, say N.
6198
6199 +config MMC_ATMELMCI
6200 + tristate "Atmel Multimedia Card Interface support"
6201 + depends on AVR32 && MMC
6202 + help
6203 + This selects the Atmel Multimedia Card Interface. If you have
6204 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
6205 + slot, say Y or M here.
6206 +
6207 + If unsure, say N.
6208 +
6209 config MMC_IMX
6210 tristate "Motorola i.MX Multimedia Card Interface support"
6211 depends on ARCH_IMX
6212 diff -x .git -Nur linux-2.6.22.1/drivers/mmc/host/Makefile linux-avr32.git/drivers/mmc/host/Makefile
6213 --- linux-2.6.22.1/drivers/mmc/host/Makefile 2007-07-10 20:56:30.000000000 +0200
6214 +++ linux-avr32.git/drivers/mmc/host/Makefile 2007-07-12 14:00:03.000000000 +0200
6215 @@ -14,5 +14,6 @@
6216 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
6217 obj-$(CONFIG_MMC_OMAP) += omap.o
6218 obj-$(CONFIG_MMC_AT91) += at91_mci.o
6219 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
6220 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
6221
6222 diff -x .git -Nur linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0001.c linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0001.c
6223 --- linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0001.c 2007-07-10 20:56:30.000000000 +0200
6224 +++ linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0001.c 2007-07-12 14:00:03.000000000 +0200
6225 @@ -50,6 +50,7 @@
6226 #define I82802AC 0x00ac
6227 #define MANUFACTURER_ST 0x0020
6228 #define M50LPW080 0x002F
6229 +#define AT49BV640D 0x02de
6230
6231 static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
6232 static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
6233 @@ -156,6 +157,47 @@
6234 }
6235 #endif
6236
6237 +/* Atmel chips don't use the same PRI format as Intel chips */
6238 +static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
6239 +{
6240 + struct map_info *map = mtd->priv;
6241 + struct cfi_private *cfi = map->fldrv_priv;
6242 + struct cfi_pri_intelext *extp = cfi->cmdset_priv;
6243 + struct cfi_pri_atmel atmel_pri;
6244 + uint32_t features = 0;
6245 +
6246 + /* Reverse byteswapping */
6247 + extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
6248 + extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
6249 + extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
6250 +
6251 + memcpy(&atmel_pri, extp, sizeof(atmel_pri));
6252 + memset((char *)extp + 5, 0, sizeof(*extp) - 5);
6253 +
6254 + printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
6255 +
6256 + if (atmel_pri.Features & 0x01) /* chip erase supported */
6257 + features |= (1<<0);
6258 + if (atmel_pri.Features & 0x02) /* erase suspend supported */
6259 + features |= (1<<1);
6260 + if (atmel_pri.Features & 0x04) /* program suspend supported */
6261 + features |= (1<<2);
6262 + if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
6263 + features |= (1<<9);
6264 + if (atmel_pri.Features & 0x20) /* page mode read supported */
6265 + features |= (1<<7);
6266 + if (atmel_pri.Features & 0x40) /* queued erase supported */
6267 + features |= (1<<4);
6268 + if (atmel_pri.Features & 0x80) /* Protection bits supported */
6269 + features |= (1<<6);
6270 +
6271 + extp->FeatureSupport = features;
6272 +
6273 + /* burst write mode not supported */
6274 + cfi->cfiq->BufWriteTimeoutTyp = 0;
6275 + cfi->cfiq->BufWriteTimeoutMax = 0;
6276 +}
6277 +
6278 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
6279 /* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
6280 static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
6281 @@ -233,6 +275,7 @@
6282 }
6283
6284 static struct cfi_fixup cfi_fixup_table[] = {
6285 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6286 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
6287 { CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
6288 #endif
6289 diff -x .git -Nur linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0002.c linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0002.c
6290 --- linux-2.6.22.1/drivers/mtd/chips/cfi_cmdset_0002.c 2007-07-10 20:56:30.000000000 +0200
6291 +++ linux-avr32.git/drivers/mtd/chips/cfi_cmdset_0002.c 2007-06-06 11:33:56.000000000 +0200
6292 @@ -186,6 +186,10 @@
6293 extp->TopBottom = 2;
6294 else
6295 extp->TopBottom = 3;
6296 +
6297 + /* burst write mode not supported */
6298 + cfi->cfiq->BufWriteTimeoutTyp = 0;
6299 + cfi->cfiq->BufWriteTimeoutMax = 0;
6300 }
6301
6302 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
6303 @@ -218,6 +222,7 @@
6304 }
6305
6306 static struct cfi_fixup cfi_fixup_table[] = {
6307 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6308 #ifdef AMD_BOOTLOC_BUG
6309 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
6310 #endif
6311 @@ -230,7 +235,6 @@
6312 #if !FORCE_WORD_WRITE
6313 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
6314 #endif
6315 - { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6316 { 0, 0, NULL, NULL }
6317 };
6318 static struct cfi_fixup jedec_fixup_table[] = {
6319 diff -x .git -Nur linux-2.6.22.1/drivers/net/Kconfig linux-avr32.git/drivers/net/Kconfig
6320 --- linux-2.6.22.1/drivers/net/Kconfig 2007-07-10 20:56:30.000000000 +0200
6321 +++ linux-avr32.git/drivers/net/Kconfig 2007-07-12 14:00:03.000000000 +0200
6322 @@ -314,7 +314,7 @@
6323 config MACB
6324 tristate "Atmel MACB support"
6325 depends on NET_ETHERNET && (AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263)
6326 - select MII
6327 + select PHYLIB
6328 help
6329 The Atmel MACB ethernet interface is found on many AT32 and AT91
6330 parts. Say Y to include support for the MACB chip.
6331 diff -x .git -Nur linux-2.6.22.1/drivers/net/macb.c linux-avr32.git/drivers/net/macb.c
6332 --- linux-2.6.22.1/drivers/net/macb.c 2007-07-10 20:56:30.000000000 +0200
6333 +++ linux-avr32.git/drivers/net/macb.c 2007-07-12 14:00:04.000000000 +0200
6334 @@ -17,13 +17,14 @@
6335 #include <linux/init.h>
6336 #include <linux/netdevice.h>
6337 #include <linux/etherdevice.h>
6338 -#include <linux/mii.h>
6339 -#include <linux/mutex.h>
6340 #include <linux/dma-mapping.h>
6341 -#include <linux/ethtool.h>
6342 #include <linux/platform_device.h>
6343 +#include <linux/phy.h>
6344
6345 #include <asm/arch/board.h>
6346 +#if defined(CONFIG_ARCH_AT91)
6347 +#include <asm/arch/cpu.h>
6348 +#endif
6349
6350 #include "macb.h"
6351
6352 @@ -85,172 +86,202 @@
6353 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
6354 }
6355
6356 -static void macb_enable_mdio(struct macb *bp)
6357 -{
6358 - unsigned long flags;
6359 - u32 reg;
6360 -
6361 - spin_lock_irqsave(&bp->lock, flags);
6362 - reg = macb_readl(bp, NCR);
6363 - reg |= MACB_BIT(MPE);
6364 - macb_writel(bp, NCR, reg);
6365 - macb_writel(bp, IER, MACB_BIT(MFD));
6366 - spin_unlock_irqrestore(&bp->lock, flags);
6367 -}
6368 -
6369 -static void macb_disable_mdio(struct macb *bp)
6370 -{
6371 - unsigned long flags;
6372 - u32 reg;
6373 -
6374 - spin_lock_irqsave(&bp->lock, flags);
6375 - reg = macb_readl(bp, NCR);
6376 - reg &= ~MACB_BIT(MPE);
6377 - macb_writel(bp, NCR, reg);
6378 - macb_writel(bp, IDR, MACB_BIT(MFD));
6379 - spin_unlock_irqrestore(&bp->lock, flags);
6380 -}
6381 -
6382 -static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
6383 +static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
6384 {
6385 - struct macb *bp = netdev_priv(dev);
6386 + struct macb *bp = bus->priv;
6387 int value;
6388
6389 - mutex_lock(&bp->mdio_mutex);
6390 -
6391 - macb_enable_mdio(bp);
6392 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
6393 | MACB_BF(RW, MACB_MAN_READ)
6394 - | MACB_BF(PHYA, phy_id)
6395 - | MACB_BF(REGA, location)
6396 + | MACB_BF(PHYA, mii_id)
6397 + | MACB_BF(REGA, regnum)
6398 | MACB_BF(CODE, MACB_MAN_CODE)));
6399
6400 - wait_for_completion(&bp->mdio_complete);
6401 + /* wait for end of transfer */
6402 + while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
6403 + cpu_relax();
6404
6405 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
6406 - macb_disable_mdio(bp);
6407 - mutex_unlock(&bp->mdio_mutex);
6408
6409 return value;
6410 }
6411
6412 -static void macb_mdio_write(struct net_device *dev, int phy_id,
6413 - int location, int val)
6414 +static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
6415 + u16 value)
6416 {
6417 - struct macb *bp = netdev_priv(dev);
6418 -
6419 - dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
6420 - phy_id, location, val);
6421 -
6422 - mutex_lock(&bp->mdio_mutex);
6423 - macb_enable_mdio(bp);
6424 + struct macb *bp = bus->priv;
6425
6426 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
6427 | MACB_BF(RW, MACB_MAN_WRITE)
6428 - | MACB_BF(PHYA, phy_id)
6429 - | MACB_BF(REGA, location)
6430 + | MACB_BF(PHYA, mii_id)
6431 + | MACB_BF(REGA, regnum)
6432 | MACB_BF(CODE, MACB_MAN_CODE)
6433 - | MACB_BF(DATA, val)));
6434 + | MACB_BF(DATA, value)));
6435 +
6436 + /* wait for end of transfer */
6437 + while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
6438 + cpu_relax();
6439
6440 - wait_for_completion(&bp->mdio_complete);
6441 + return 0;
6442 +}
6443
6444 - macb_disable_mdio(bp);
6445 - mutex_unlock(&bp->mdio_mutex);
6446 +static int macb_mdio_reset(struct mii_bus *bus)
6447 +{
6448 + return 0;
6449 }
6450
6451 -static int macb_phy_probe(struct macb *bp)
6452 +static void macb_handle_link_change(struct net_device *dev)
6453 {
6454 - int phy_address;
6455 - u16 phyid1, phyid2;
6456 + struct macb *bp = netdev_priv(dev);
6457 + struct phy_device *phydev = bp->phy_dev;
6458 + unsigned long flags;
6459
6460 - for (phy_address = 0; phy_address < 32; phy_address++) {
6461 - phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
6462 - phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
6463 + int status_change = 0;
6464
6465 - if (phyid1 != 0xffff && phyid1 != 0x0000
6466 - && phyid2 != 0xffff && phyid2 != 0x0000)
6467 - break;
6468 + spin_lock_irqsave(&bp->lock, flags);
6469 +
6470 + if (phydev->link) {
6471 + if ((bp->speed != phydev->speed) ||
6472 + (bp->duplex != phydev->duplex)) {
6473 + u32 reg;
6474 +
6475 + reg = macb_readl(bp, NCFGR);
6476 + reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
6477 +
6478 + if (phydev->duplex)
6479 + reg |= MACB_BIT(FD);
6480 + if (phydev->speed)
6481 + reg |= MACB_BIT(SPD);
6482 +
6483 + macb_writel(bp, NCFGR, reg);
6484 +
6485 + bp->speed = phydev->speed;
6486 + bp->duplex = phydev->duplex;
6487 + status_change = 1;
6488 + }
6489 }
6490
6491 - if (phy_address == 32)
6492 - return -ENODEV;
6493 + if (phydev->link != bp->link) {
6494 + if (phydev->link)
6495 + netif_schedule(dev);
6496 + else {
6497 + bp->speed = 0;
6498 + bp->duplex = -1;
6499 + }
6500 + bp->link = phydev->link;
6501
6502 - dev_info(&bp->pdev->dev,
6503 - "detected PHY at address %d (ID %04x:%04x)\n",
6504 - phy_address, phyid1, phyid2);
6505 + status_change = 1;
6506 + }
6507
6508 - bp->mii.phy_id = phy_address;
6509 - return 0;
6510 + spin_unlock_irqrestore(&bp->lock, flags);
6511 +
6512 + if (status_change) {
6513 + if (phydev->link)
6514 + printk(KERN_INFO "%s: link up (%d/%s)\n",
6515 + dev->name, phydev->speed,
6516 + DUPLEX_FULL == phydev->duplex ? "Full":"Half");
6517 + else
6518 + printk(KERN_INFO "%s: link down\n", dev->name);
6519 + }
6520 }
6521
6522 -static void macb_set_media(struct macb *bp, int media)
6523 +/* based on au1000_eth. c*/
6524 +static int macb_mii_probe(struct net_device *dev)
6525 {
6526 - u32 reg;
6527 + struct macb *bp = netdev_priv(dev);
6528 + struct phy_device *phydev = NULL;
6529 + struct eth_platform_data *pdata;
6530 + int phy_addr;
6531
6532 - spin_lock_irq(&bp->lock);
6533 - reg = macb_readl(bp, NCFGR);
6534 - reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
6535 - if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
6536 - reg |= MACB_BIT(SPD);
6537 - if (media & ADVERTISE_FULL)
6538 - reg |= MACB_BIT(FD);
6539 - macb_writel(bp, NCFGR, reg);
6540 - spin_unlock_irq(&bp->lock);
6541 + /* find the first phy */
6542 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
6543 + if (bp->mii_bus.phy_map[phy_addr]) {
6544 + phydev = bp->mii_bus.phy_map[phy_addr];
6545 + break;
6546 + }
6547 + }
6548 +
6549 + if (!phydev) {
6550 + printk (KERN_ERR "%s: no PHY found\n", dev->name);
6551 + return -1;
6552 + }
6553 +
6554 + pdata = bp->pdev->dev.platform_data;
6555 + /* TODO : add pin_irq */
6556 +
6557 + /* attach the mac to the phy */
6558 + if (pdata && pdata->is_rmii) {
6559 + phydev = phy_connect(dev, phydev->dev.bus_id,
6560 + &macb_handle_link_change, 0, PHY_INTERFACE_MODE_RMII);
6561 + } else {
6562 + phydev = phy_connect(dev, phydev->dev.bus_id,
6563 + &macb_handle_link_change, 0, PHY_INTERFACE_MODE_MII);
6564 + }
6565 +
6566 + if (IS_ERR(phydev)) {
6567 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
6568 + return PTR_ERR(phydev);
6569 + }
6570 +
6571 + /* mask with MAC supported features */
6572 + phydev->supported &= PHY_BASIC_FEATURES;
6573 +
6574 + phydev->advertising = phydev->supported;
6575 +
6576 + bp->link = 0;
6577 + bp->speed = 0;
6578 + bp->duplex = -1;
6579 + bp->phy_dev = phydev;
6580 +
6581 + return 0;
6582 }
6583
6584 -static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
6585 +static int macb_mii_init(struct macb *bp)
6586 {
6587 - struct mii_if_info *mii = &bp->mii;
6588 - unsigned int old_carrier, new_carrier;
6589 - int advertise, lpa, media, duplex;
6590 + struct eth_platform_data *pdata;
6591 + int err = -ENXIO, i;
6592
6593 - /* if forced media, go no further */
6594 - if (mii->force_media)
6595 - return;
6596 + /* Enable managment port */
6597 + macb_writel(bp, NCR, MACB_BIT(MPE));
6598
6599 - /* check current and old link status */
6600 - old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
6601 - new_carrier = (unsigned int) mii_link_ok(mii);
6602 + bp->mii_bus.name = "MACB_mii_bus",
6603 + bp->mii_bus.read = &macb_mdio_read,
6604 + bp->mii_bus.write = &macb_mdio_write,
6605 + bp->mii_bus.reset = &macb_mdio_reset,
6606 + bp->mii_bus.id = bp->pdev->id,
6607 + bp->mii_bus.priv = bp,
6608 + bp->mii_bus.dev = &bp->dev->dev;
6609 + pdata = bp->pdev->dev.platform_data;
6610
6611 - /* if carrier state did not change, assume nothing else did */
6612 - if (!init_media && old_carrier == new_carrier)
6613 - return;
6614 + if (pdata)
6615 + bp->mii_bus.phy_mask = pdata->phy_mask;
6616
6617 - /* no carrier, nothing much to do */
6618 - if (!new_carrier) {
6619 - netif_carrier_off(mii->dev);
6620 - printk(KERN_INFO "%s: link down\n", mii->dev->name);
6621 - return;
6622 + bp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
6623 + if (!bp->mii_bus.irq) {
6624 + err = -ENOMEM;
6625 + goto err_out;
6626 }
6627
6628 - /*
6629 - * we have carrier, see who's on the other end
6630 - */
6631 - netif_carrier_on(mii->dev);
6632 + for (i = 0; i < PHY_MAX_ADDR; i++)
6633 + bp->mii_bus.irq[i] = PHY_POLL;
6634
6635 - /* get MII advertise and LPA values */
6636 - if (!init_media && mii->advertising) {
6637 - advertise = mii->advertising;
6638 - } else {
6639 - advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
6640 - mii->advertising = advertise;
6641 - }
6642 - lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
6643 + platform_set_drvdata(bp->dev, &bp->mii_bus);
6644
6645 - /* figure out media and duplex from advertise and LPA values */
6646 - media = mii_nway_result(lpa & advertise);
6647 - duplex = (media & ADVERTISE_FULL) ? 1 : 0;
6648 + if (mdiobus_register(&bp->mii_bus))
6649 + goto err_out_free_mdio_irq;
6650
6651 - if (ok_to_print)
6652 - printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
6653 - mii->dev->name,
6654 - media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
6655 - duplex ? "full" : "half", lpa);
6656 + if (macb_mii_probe(bp->dev) != 0) {
6657 + goto err_out_unregister_bus;
6658 + }
6659
6660 - mii->full_duplex = duplex;
6661 + return 0;
6662
6663 - /* Let the MAC know about the new link state */
6664 - macb_set_media(bp, media);
6665 +err_out_unregister_bus:
6666 + mdiobus_unregister(&bp->mii_bus);
6667 +err_out_free_mdio_irq:
6668 + kfree(bp->mii_bus.irq);
6669 +err_out:
6670 + return err;
6671 }
6672
6673 static void macb_update_stats(struct macb *bp)
6674 @@ -265,16 +296,6 @@
6675 *p += __raw_readl(reg);
6676 }
6677
6678 -static void macb_periodic_task(struct work_struct *work)
6679 -{
6680 - struct macb *bp = container_of(work, struct macb, periodic_task.work);
6681 -
6682 - macb_update_stats(bp);
6683 - macb_check_media(bp, 1, 0);
6684 -
6685 - schedule_delayed_work(&bp->periodic_task, HZ);
6686 -}
6687 -
6688 static void macb_tx(struct macb *bp)
6689 {
6690 unsigned int tail;
6691 @@ -519,9 +540,6 @@
6692 spin_lock(&bp->lock);
6693
6694 while (status) {
6695 - if (status & MACB_BIT(MFD))
6696 - complete(&bp->mdio_complete);
6697 -
6698 /* close possible race with dev_close */
6699 if (unlikely(!netif_running(dev))) {
6700 macb_writel(bp, IDR, ~0UL);
6701 @@ -535,7 +553,8 @@
6702 * until we have processed the buffers
6703 */
6704 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
6705 - dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
6706 + dev_dbg(&bp->pdev->dev,
6707 + "scheduling RX softirq\n");
6708 __netif_rx_schedule(dev);
6709 }
6710 }
6711 @@ -765,7 +784,7 @@
6712 macb_writel(bp, TBQP, bp->tx_ring_dma);
6713
6714 /* Enable TX and RX */
6715 - macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
6716 + macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
6717
6718 /* Enable interrupts */
6719 macb_writel(bp, IER, (MACB_BIT(RCOMP)
6720 @@ -776,18 +795,7 @@
6721 | MACB_BIT(TCOMP)
6722 | MACB_BIT(ISR_ROVR)
6723 | MACB_BIT(HRESP)));
6724 -}
6725 -
6726 -static void macb_init_phy(struct net_device *dev)
6727 -{
6728 - struct macb *bp = netdev_priv(dev);
6729
6730 - /* Set some reasonable default settings */
6731 - macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
6732 - ADVERTISE_CSMA | ADVERTISE_ALL);
6733 - macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
6734 - (BMCR_SPEED100 | BMCR_ANENABLE
6735 - | BMCR_ANRESTART | BMCR_FULLDPLX));
6736 }
6737
6738 static int macb_open(struct net_device *dev)
6739 @@ -797,6 +805,10 @@
6740
6741 dev_dbg(&bp->pdev->dev, "open\n");
6742
6743 + /* if the phy is not yet register, retry later*/
6744 + if (!bp->phy_dev)
6745 + return -EAGAIN;
6746 +
6747 if (!is_valid_ether_addr(dev->dev_addr))
6748 return -EADDRNOTAVAIL;
6749
6750 @@ -810,12 +822,11 @@
6751
6752 macb_init_rings(bp);
6753 macb_init_hw(bp);
6754 - macb_init_phy(dev);
6755
6756 - macb_check_media(bp, 1, 1);
6757 - netif_start_queue(dev);
6758 + /* schedule a link state check */
6759 + phy_start(bp->phy_dev);
6760
6761 - schedule_delayed_work(&bp->periodic_task, HZ);
6762 + netif_start_queue(dev);
6763
6764 return 0;
6765 }
6766 @@ -825,10 +836,11 @@
6767 struct macb *bp = netdev_priv(dev);
6768 unsigned long flags;
6769
6770 - cancel_rearming_delayed_work(&bp->periodic_task);
6771 -
6772 netif_stop_queue(dev);
6773
6774 + if (bp->phy_dev)
6775 + phy_stop(bp->phy_dev);
6776 +
6777 spin_lock_irqsave(&bp->lock, flags);
6778 macb_reset_hw(bp);
6779 netif_carrier_off(dev);
6780 @@ -845,6 +857,9 @@
6781 struct net_device_stats *nstat = &bp->stats;
6782 struct macb_stats *hwstat = &bp->hw_stats;
6783
6784 + /* read stats from hardware */
6785 + macb_update_stats(bp);
6786 +
6787 /* Convert HW stats into netdevice stats */
6788 nstat->rx_errors = (hwstat->rx_fcs_errors +
6789 hwstat->rx_align_errors +
6790 @@ -882,18 +897,27 @@
6791 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6792 {
6793 struct macb *bp = netdev_priv(dev);
6794 + struct phy_device *phydev = bp->phy_dev;
6795
6796 - return mii_ethtool_gset(&bp->mii, cmd);
6797 + if (!phydev)
6798 + return -ENODEV;
6799 +
6800 + return phy_ethtool_gset(phydev, cmd);
6801 }
6802
6803 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6804 {
6805 struct macb *bp = netdev_priv(dev);
6806 + struct phy_device *phydev = bp->phy_dev;
6807 +
6808 + if (!phydev)
6809 + return -ENODEV;
6810
6811 - return mii_ethtool_sset(&bp->mii, cmd);
6812 + return phy_ethtool_sset(phydev, cmd);
6813 }
6814
6815 -static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6816 +static void macb_get_drvinfo(struct net_device *dev,
6817 + struct ethtool_drvinfo *info)
6818 {
6819 struct macb *bp = netdev_priv(dev);
6820
6821 @@ -902,104 +926,34 @@
6822 strcpy(info->bus_info, bp->pdev->dev.bus_id);
6823 }
6824
6825 -static int macb_nway_reset(struct net_device *dev)
6826 -{
6827 - struct macb *bp = netdev_priv(dev);
6828 - return mii_nway_restart(&bp->mii);
6829 -}
6830 -
6831 static struct ethtool_ops macb_ethtool_ops = {
6832 .get_settings = macb_get_settings,
6833 .set_settings = macb_set_settings,
6834 .get_drvinfo = macb_get_drvinfo,
6835 - .nway_reset = macb_nway_reset,
6836 .get_link = ethtool_op_get_link,
6837 };
6838
6839 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6840 {
6841 struct macb *bp = netdev_priv(dev);
6842 + struct phy_device *phydev = bp->phy_dev;
6843
6844 if (!netif_running(dev))
6845 return -EINVAL;
6846
6847 - return generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
6848 -}
6849 -
6850 -static ssize_t macb_mii_show(const struct device *_dev, char *buf,
6851 - unsigned long addr)
6852 -{
6853 - struct net_device *dev = to_net_dev(_dev);
6854 - struct macb *bp = netdev_priv(dev);
6855 - ssize_t ret = -EINVAL;
6856 -
6857 - if (netif_running(dev)) {
6858 - int value;
6859 - value = macb_mdio_read(dev, bp->mii.phy_id, addr);
6860 - ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
6861 - }
6862 -
6863 - return ret;
6864 -}
6865 -
6866 -#define MII_ENTRY(name, addr) \
6867 -static ssize_t show_##name(struct device *_dev, \
6868 - struct device_attribute *attr, \
6869 - char *buf) \
6870 -{ \
6871 - return macb_mii_show(_dev, buf, addr); \
6872 -} \
6873 -static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
6874 -
6875 -MII_ENTRY(bmcr, MII_BMCR);
6876 -MII_ENTRY(bmsr, MII_BMSR);
6877 -MII_ENTRY(physid1, MII_PHYSID1);
6878 -MII_ENTRY(physid2, MII_PHYSID2);
6879 -MII_ENTRY(advertise, MII_ADVERTISE);
6880 -MII_ENTRY(lpa, MII_LPA);
6881 -MII_ENTRY(expansion, MII_EXPANSION);
6882 -
6883 -static struct attribute *macb_mii_attrs[] = {
6884 - &dev_attr_bmcr.attr,
6885 - &dev_attr_bmsr.attr,
6886 - &dev_attr_physid1.attr,
6887 - &dev_attr_physid2.attr,
6888 - &dev_attr_advertise.attr,
6889 - &dev_attr_lpa.attr,
6890 - &dev_attr_expansion.attr,
6891 - NULL,
6892 -};
6893 -
6894 -static struct attribute_group macb_mii_group = {
6895 - .name = "mii",
6896 - .attrs = macb_mii_attrs,
6897 -};
6898 -
6899 -static void macb_unregister_sysfs(struct net_device *net)
6900 -{
6901 - struct device *_dev = &net->dev;
6902 + if (!phydev)
6903 + return -ENODEV;
6904
6905 - sysfs_remove_group(&_dev->kobj, &macb_mii_group);
6906 + return phy_mii_ioctl(phydev, if_mii(rq), cmd);
6907 }
6908
6909 -static int macb_register_sysfs(struct net_device *net)
6910 -{
6911 - struct device *_dev = &net->dev;
6912 - int ret;
6913 -
6914 - ret = sysfs_create_group(&_dev->kobj, &macb_mii_group);
6915 - if (ret)
6916 - printk(KERN_WARNING
6917 - "%s: sysfs mii attribute registration failed: %d\n",
6918 - net->name, ret);
6919 - return ret;
6920 -}
6921 static int __devinit macb_probe(struct platform_device *pdev)
6922 {
6923 struct eth_platform_data *pdata;
6924 struct resource *regs;
6925 struct net_device *dev;
6926 struct macb *bp;
6927 + struct phy_device *phydev;
6928 unsigned long pclk_hz;
6929 u32 config;
6930 int err = -ENXIO;
6931 @@ -1080,10 +1034,6 @@
6932
6933 dev->base_addr = regs->start;
6934
6935 - INIT_DELAYED_WORK(&bp->periodic_task, macb_periodic_task);
6936 - mutex_init(&bp->mdio_mutex);
6937 - init_completion(&bp->mdio_complete);
6938 -
6939 /* Set MII management clock divider */
6940 pclk_hz = clk_get_rate(bp->pclk);
6941 if (pclk_hz <= 20000000)
6942 @@ -1096,20 +1046,9 @@
6943 config = MACB_BF(CLK, MACB_CLK_DIV64);
6944 macb_writel(bp, NCFGR, config);
6945
6946 - bp->mii.dev = dev;
6947 - bp->mii.mdio_read = macb_mdio_read;
6948 - bp->mii.mdio_write = macb_mdio_write;
6949 - bp->mii.phy_id_mask = 0x1f;
6950 - bp->mii.reg_num_mask = 0x1f;
6951 -
6952 macb_get_hwaddr(bp);
6953 - err = macb_phy_probe(bp);
6954 - if (err) {
6955 - dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
6956 - goto err_out_free_irq;
6957 - }
6958 -
6959 pdata = pdev->dev.platform_data;
6960 +
6961 if (pdata && pdata->is_rmii)
6962 #if defined(CONFIG_ARCH_AT91)
6963 macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
6964 @@ -1131,9 +1070,11 @@
6965 goto err_out_free_irq;
6966 }
6967
6968 - platform_set_drvdata(pdev, dev);
6969 + if (macb_mii_init(bp) != 0) {
6970 + goto err_out_unregister_netdev;
6971 + }
6972
6973 - macb_register_sysfs(dev);
6974 + platform_set_drvdata(pdev, dev);
6975
6976 printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
6977 "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
6978 @@ -1141,8 +1082,15 @@
6979 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
6980 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
6981
6982 + phydev = bp->phy_dev;
6983 + printk(KERN_INFO "%s: attached PHY driver [%s] "
6984 + "(mii_bus:phy_addr=%s, irq=%d)\n",
6985 + dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
6986 +
6987 return 0;
6988
6989 +err_out_unregister_netdev:
6990 + unregister_netdev(dev);
6991 err_out_free_irq:
6992 free_irq(dev->irq, dev);
6993 err_out_iounmap:
6994 @@ -1153,7 +1101,9 @@
6995 clk_put(bp->hclk);
6996 #endif
6997 clk_disable(bp->pclk);
6998 +#ifndef CONFIG_ARCH_AT91
6999 err_out_put_pclk:
7000 +#endif
7001 clk_put(bp->pclk);
7002 err_out_free_dev:
7003 free_netdev(dev);
7004 @@ -1171,7 +1121,8 @@
7005
7006 if (dev) {
7007 bp = netdev_priv(dev);
7008 - macb_unregister_sysfs(dev);
7009 + mdiobus_unregister(&bp->mii_bus);
7010 + kfree(bp->mii_bus.irq);
7011 unregister_netdev(dev);
7012 free_irq(dev->irq, dev);
7013 iounmap(bp->regs);
7014 diff -x .git -Nur linux-2.6.22.1/drivers/net/macb.h linux-avr32.git/drivers/net/macb.h
7015 --- linux-2.6.22.1/drivers/net/macb.h 2007-07-10 20:56:30.000000000 +0200
7016 +++ linux-avr32.git/drivers/net/macb.h 2007-07-12 14:00:04.000000000 +0200
7017 @@ -383,11 +383,11 @@
7018
7019 unsigned int rx_pending, tx_pending;
7020
7021 - struct delayed_work periodic_task;
7022 -
7023 - struct mutex mdio_mutex;
7024 - struct completion mdio_complete;
7025 - struct mii_if_info mii;
7026 + struct mii_bus mii_bus;
7027 + struct phy_device *phy_dev;
7028 + unsigned int link;
7029 + unsigned int speed;
7030 + unsigned int duplex;
7031 };
7032
7033 #endif /* _MACB_H */
7034 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/Kconfig linux-avr32.git/drivers/rtc/Kconfig
7035 --- linux-2.6.22.1/drivers/rtc/Kconfig 2007-07-10 20:56:30.000000000 +0200
7036 +++ linux-avr32.git/drivers/rtc/Kconfig 2007-07-12 14:00:13.000000000 +0200
7037 @@ -379,6 +379,13 @@
7038 To compile this driver as a module, choose M here: the
7039 module will be called rtc-pl031.
7040
7041 +config RTC_DRV_AT32AP700X
7042 + tristate "AT32AP700X series RTC"
7043 + depends on RTC_CLASS && PLATFORM_AT32AP
7044 + help
7045 + Driver for the internal RTC (Realtime Clock) on Atmel AVR32
7046 + AT32AP700x family processors.
7047 +
7048 config RTC_DRV_AT91RM9200
7049 tristate "AT91RM9200"
7050 depends on RTC_CLASS && ARCH_AT91RM9200
7051 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/Makefile linux-avr32.git/drivers/rtc/Makefile
7052 --- linux-2.6.22.1/drivers/rtc/Makefile 2007-07-10 20:56:30.000000000 +0200
7053 +++ linux-avr32.git/drivers/rtc/Makefile 2007-07-12 14:00:13.000000000 +0200
7054 @@ -19,6 +19,7 @@
7055 obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
7056 obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
7057 obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
7058 +obj-$(CONFIG_RTC_DRV_AT32AP700X) += rtc-at32ap700x.o
7059 obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o
7060 obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
7061 obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
7062 diff -x .git -Nur linux-2.6.22.1/drivers/rtc/rtc-at32ap700x.c linux-avr32.git/drivers/rtc/rtc-at32ap700x.c
7063 --- linux-2.6.22.1/drivers/rtc/rtc-at32ap700x.c 1970-01-01 01:00:00.000000000 +0100
7064 +++ linux-avr32.git/drivers/rtc/rtc-at32ap700x.c 2007-07-12 14:00:13.000000000 +0200
7065 @@ -0,0 +1,337 @@
7066 +/*
7067 + * An RTC driver for the AVR32 AT32AP700x processor series.
7068 + *
7069 + * Copyright (C) 2007 Atmel Corporation
7070 + *
7071 + * This program is free software; you can redistribute it and/or modify it
7072 + * under the terms of the GNU General Public License version 2 as published
7073 + * by the Free Software Foundation.
7074 + */
7075 +
7076 +#include <linux/module.h>
7077 +#include <linux/kernel.h>
7078 +#include <linux/platform_device.h>
7079 +#include <linux/rtc.h>
7080 +#include <linux/io.h>
7081 +
7082 +/*
7083 + * This is a bare-bones RTC. It runs during most system sleep states, but has
7084 + * no battery backup and gets reset during system restart. It must be
7085 + * initialized from an external clock (network, I2C, etc) before it can be of
7086 + * much use.
7087 + *
7088 + * The alarm functionality is limited by the hardware, not supporting
7089 + * periodic interrupts.
7090 + */
7091 +
7092 +#define RTC_CTRL 0x00
7093 +#define RTC_CTRL_EN 0
7094 +#define RTC_CTRL_PCLR 1
7095 +#define RTC_CTRL_TOPEN 2
7096 +#define RTC_CTRL_PSEL 8
7097 +
7098 +#define RTC_VAL 0x04
7099 +
7100 +#define RTC_TOP 0x08
7101 +
7102 +#define RTC_IER 0x10
7103 +#define RTC_IER_TOPI 0
7104 +
7105 +#define RTC_IDR 0x14
7106 +#define RTC_IDR_TOPI 0
7107 +
7108 +#define RTC_IMR 0x18
7109 +#define RTC_IMR_TOPI 0
7110 +
7111 +#define RTC_ISR 0x1c
7112 +#define RTC_ISR_TOPI 0
7113 +
7114 +#define RTC_ICR 0x20
7115 +#define RTC_ICR_TOPI 0
7116 +
7117 +#define RTC_BIT(name) (1 << RTC_##name)
7118 +#define RTC_BF(name, value) ((value) << RTC_##name)
7119 +
7120 +#define rtc_readl(dev, reg) \
7121 + __raw_readl((dev)->regs + RTC_##reg)
7122 +#define rtc_writel(dev, reg, value) \
7123 + __raw_writel((value), (dev)->regs + RTC_##reg)
7124 +
7125 +struct rtc_at32ap700x {
7126 + struct rtc_device *rtc;
7127 + void __iomem *regs;
7128 + unsigned long alarm_time;
7129 + unsigned long irq;
7130 + /* Protect against concurrent register access. */
7131 + spinlock_t lock;
7132 +};
7133 +
7134 +static int at32_rtc_readtime(struct device *dev, struct rtc_time *tm)
7135 +{
7136 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
7137 + unsigned long now;
7138 +
7139 + now = rtc_readl(rtc, VAL);
7140 + rtc_time_to_tm(now, tm);
7141 +
7142 + return 0;
7143 +}
7144 +
7145 +static int at32_rtc_settime(struct device *dev, struct rtc_time *tm)
7146 +{
7147 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
7148 + unsigned long now;
7149 + int ret;
7150 +
7151 + ret = rtc_tm_to_time(tm, &now);
7152 + if (ret == 0)
7153 + rtc_writel(rtc, VAL, now);
7154 +
7155 + return ret;
7156 +}
7157 +
7158 +static int at32_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
7159 +{
7160 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
7161 +
7162 + rtc_time_to_tm(rtc->alarm_time, &alrm->time);
7163 + alrm->pending = rtc_readl(rtc, IMR) & RTC_BIT(IMR_TOPI) ? 1 : 0;
7164 +
7165 + return 0;
7166 +}
7167 +
7168 +static int at32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
7169 +{
7170 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
7171 + unsigned long rtc_unix_time;
7172 + unsigned long alarm_unix_time;
7173 + int ret;
7174 +
7175 + rtc_unix_time = rtc_readl(rtc, VAL);
7176 +
7177 + /* RTC does only support one alarm time, not periodic */
7178 + if (alrm->time.tm_mday <= 0) {
7179 + struct rtc_time tm;
7180 + unsigned long then;
7181 +
7182 + rtc_time_to_tm(rtc_unix_time, &tm);
7183 +
7184 + alrm->time.tm_mday = tm.tm_mday;
7185 + alrm->time.tm_mon = tm.tm_mon;
7186 + alrm->time.tm_year = tm.tm_year;
7187 +
7188 + rtc_tm_to_time(&alrm->time, &then);
7189 +
7190 + /* check if the alarm wraps into tomorrow */
7191 + if (then < rtc_unix_time) {
7192 + rtc_time_to_tm(rtc_unix_time + 24 * 60 * 60, &tm);
7193 + alrm->time.tm_mday = tm.tm_mday;
7194 + alrm->time.tm_mon = tm.tm_mon;
7195 + alrm->time.tm_year = tm.tm_year;
7196 + }
7197 + }
7198 +
7199 + ret = rtc_tm_to_time(&alrm->time, &alarm_unix_time);
7200 + if (ret)
7201 + return ret;
7202 +
7203 + if (alarm_unix_time < rtc_unix_time)
7204 + return -EINVAL;
7205 +
7206 + spin_lock_irq(&rtc->lock);
7207 + rtc->alarm_time = alarm_unix_time;
7208 + rtc_writel(rtc, TOP, rtc->alarm_time);
7209 + if (alrm->pending)
7210 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
7211 + | RTC_BIT(CTRL_TOPEN));
7212 + else
7213 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
7214 + & ~RTC_BIT(CTRL_TOPEN));
7215 + spin_unlock_irq(&rtc->lock);
7216 +
7217 + return ret;
7218 +}
7219 +
7220 +static int at32_rtc_ioctl(struct device *dev, unsigned int cmd,
7221 + unsigned long arg)
7222 +{
7223 + struct rtc_at32ap700x *rtc = dev_get_drvdata(dev);
7224 + int ret = 0;
7225 +
7226 + spin_lock_irq(&rtc->lock);
7227 +
7228 + switch (cmd) {
7229 + case RTC_AIE_ON:
7230 + if (rtc_readl(rtc, VAL) > rtc->alarm_time) {
7231 + ret = -EINVAL;
7232 + break;
7233 + }
7234 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
7235 + | RTC_BIT(CTRL_TOPEN));
7236 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
7237 + rtc_writel(rtc, IER, RTC_BIT(IER_TOPI));
7238 + break;
7239 + case RTC_AIE_OFF:
7240 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
7241 + & ~RTC_BIT(CTRL_TOPEN));
7242 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
7243 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
7244 + break;
7245 + default:
7246 + ret = -ENOIOCTLCMD;
7247 + break;
7248 + }
7249 +
7250 + spin_unlock_irq(&rtc->lock);
7251 +
7252 + return ret;
7253 +}
7254 +
7255 +static irqreturn_t at32_rtc_interrupt(int irq, void *dev_id)
7256 +{
7257 + struct rtc_at32ap700x *rtc = (struct rtc_at32ap700x *)dev_id;
7258 + unsigned long isr = rtc_readl(rtc, ISR);
7259 + unsigned long events = 0;
7260 + int ret = IRQ_NONE;
7261 +
7262 + spin_lock(&rtc->lock);
7263 +
7264 + if (isr & RTC_BIT(ISR_TOPI)) {
7265 + rtc_writel(rtc, ICR, RTC_BIT(ICR_TOPI));
7266 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
7267 + rtc_writel(rtc, CTRL, rtc_readl(rtc, CTRL)
7268 + & ~RTC_BIT(CTRL_TOPEN));
7269 + rtc_writel(rtc, VAL, rtc->alarm_time);
7270 + events = RTC_AF | RTC_IRQF;
7271 + rtc_update_irq(rtc->rtc, 1, events);
7272 + ret = IRQ_HANDLED;
7273 + }
7274 +
7275 + spin_unlock(&rtc->lock);
7276 +
7277 + return ret;
7278 +}
7279 +
7280 +static struct rtc_class_ops at32_rtc_ops = {
7281 + .ioctl = at32_rtc_ioctl,
7282 + .read_time = at32_rtc_readtime,
7283 + .set_time = at32_rtc_settime,
7284 + .read_alarm = at32_rtc_readalarm,
7285 + .set_alarm = at32_rtc_setalarm,
7286 +};
7287 +
7288 +static int __init at32_rtc_probe(struct platform_device *pdev)
7289 +{
7290 + struct resource *regs;
7291 + struct rtc_at32ap700x *rtc;
7292 + int irq = -1;
7293 + int ret;
7294 +
7295 + rtc = kzalloc(sizeof(struct rtc_at32ap700x), GFP_KERNEL);
7296 + if (!rtc) {
7297 + dev_dbg(&pdev->dev, "out of memory\n");
7298 + return -ENOMEM;
7299 + }
7300 +
7301 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7302 + if (!regs) {
7303 + dev_dbg(&pdev->dev, "no mmio resource defined\n");
7304 + ret = -ENXIO;
7305 + goto out;
7306 + }
7307 +
7308 + irq = platform_get_irq(pdev, 0);
7309 + if (irq < 0) {
7310 + dev_dbg(&pdev->dev, "could not get irq\n");
7311 + ret = -ENXIO;
7312 + goto out;
7313 + }
7314 +
7315 + ret = request_irq(irq, at32_rtc_interrupt, IRQF_SHARED, "rtc", rtc);
7316 + if (ret) {
7317 + dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
7318 + goto out;
7319 + }
7320 +
7321 + rtc->irq = irq;
7322 + rtc->regs = ioremap(regs->start, regs->end - regs->start + 1);
7323 + if (!rtc->regs) {
7324 + ret = -ENOMEM;
7325 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
7326 + goto out_free_irq;
7327 + }
7328 + spin_lock_init(&rtc->lock);
7329 +
7330 + /*
7331 + * Maybe init RTC: count from zero at 1 Hz, disable wrap irq.
7332 + *
7333 + * Do not reset VAL register, as it can hold an old time
7334 + * from last JTAG reset.
7335 + */
7336 + if (!(rtc_readl(rtc, CTRL) & RTC_BIT(CTRL_EN))) {
7337 + rtc_writel(rtc, CTRL, RTC_BIT(CTRL_PCLR));
7338 + rtc_writel(rtc, IDR, RTC_BIT(IDR_TOPI));
7339 + rtc_writel(rtc, CTRL, RTC_BF(CTRL_PSEL, 0xe)
7340 + | RTC_BIT(CTRL_EN));
7341 + }
7342 +
7343 + rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
7344 + &at32_rtc_ops, THIS_MODULE);
7345 + if (IS_ERR(rtc->rtc)) {
7346 + dev_dbg(&pdev->dev, "could not register rtc device\n");
7347 + ret = PTR_ERR(rtc->rtc);
7348 + goto out_iounmap;
7349 + }
7350 +
7351 + platform_set_drvdata(pdev, rtc);
7352 +
7353 + dev_info(&pdev->dev, "Atmel RTC for AT32AP700x at %08lx irq %ld\n",
7354 + (unsigned long)rtc->regs, rtc->irq);
7355 +
7356 + return 0;
7357 +
7358 +out_iounmap:
7359 + iounmap(rtc->regs);
7360 +out_free_irq:
7361 + free_irq(irq, rtc);
7362 +out:
7363 + kfree(rtc);
7364 + return ret;
7365 +}
7366 +
7367 +static int __exit at32_rtc_remove(struct platform_device *pdev)
7368 +{
7369 + struct rtc_at32ap700x *rtc = platform_get_drvdata(pdev);
7370 +
7371 + free_irq(rtc->irq, rtc);
7372 + iounmap(rtc->regs);
7373 + rtc_device_unregister(rtc->rtc);
7374 + kfree(rtc);
7375 + platform_set_drvdata(pdev, NULL);
7376 +
7377 + return 0;
7378 +}
7379 +
7380 +static struct platform_driver at32_rtc_driver = {
7381 + .remove = __exit_p(at32_rtc_remove),
7382 + .driver = {
7383 + .name = "rtc-at32ap700x",
7384 + .owner = THIS_MODULE,
7385 + },
7386 +};
7387 +
7388 +static int __init at32_rtc_init(void)
7389 +{
7390 + return platform_driver_probe(&at32_rtc_driver, at32_rtc_probe);
7391 +}
7392 +module_init(at32_rtc_init);
7393 +
7394 +static void __exit at32_rtc_exit(void)
7395 +{
7396 + platform_driver_unregister(&at32_rtc_driver);
7397 +}
7398 +module_exit(at32_rtc_exit);
7399 +
7400 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
7401 +MODULE_DESCRIPTION("Real time clock for AVR32 AT32AP700x");
7402 +MODULE_LICENSE("GPL");
7403 diff -x .git -Nur linux-2.6.22.1/drivers/serial/atmel_serial.c linux-avr32.git/drivers/serial/atmel_serial.c
7404 --- linux-2.6.22.1/drivers/serial/atmel_serial.c 2007-07-10 20:56:30.000000000 +0200
7405 +++ linux-avr32.git/drivers/serial/atmel_serial.c 2007-06-06 11:33:59.000000000 +0200
7406 @@ -114,6 +114,7 @@
7407 struct uart_port uart; /* uart */
7408 struct clk *clk; /* uart clock */
7409 unsigned short suspended; /* is port suspended? */
7410 + int break_active; /* break being received */
7411 };
7412
7413 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
7414 @@ -252,6 +253,7 @@
7415 */
7416 static void atmel_rx_chars(struct uart_port *port)
7417 {
7418 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
7419 struct tty_struct *tty = port->info->tty;
7420 unsigned int status, ch, flg;
7421
7422 @@ -267,13 +269,29 @@
7423 * note that the error handling code is
7424 * out of the main execution path
7425 */
7426 - if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
7427 + if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
7428 + | ATMEL_US_OVRE | ATMEL_US_RXBRK)
7429 + || atmel_port->break_active)) {
7430 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
7431 - if (status & ATMEL_US_RXBRK) {
7432 + if (status & ATMEL_US_RXBRK
7433 + && !atmel_port->break_active) {
7434 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
7435 port->icount.brk++;
7436 + atmel_port->break_active = 1;
7437 + UART_PUT_IER(port, ATMEL_US_RXBRK);
7438 if (uart_handle_break(port))
7439 goto ignore_char;
7440 + } else {
7441 + /*
7442 + * This is either the end-of-break
7443 + * condition or we've received at
7444 + * least one character without RXBRK
7445 + * being set. In both cases, the next
7446 + * RXBRK will indicate start-of-break.
7447 + */
7448 + UART_PUT_IDR(port, ATMEL_US_RXBRK);
7449 + status &= ~ATMEL_US_RXBRK;
7450 + atmel_port->break_active = 0;
7451 }
7452 if (status & ATMEL_US_PARE)
7453 port->icount.parity++;
7454 @@ -352,6 +370,16 @@
7455 /* Interrupt receive */
7456 if (pending & ATMEL_US_RXRDY)
7457 atmel_rx_chars(port);
7458 + else if (pending & ATMEL_US_RXBRK) {
7459 + /*
7460 + * End of break detected. If it came along
7461 + * with a character, atmel_rx_chars will
7462 + * handle it.
7463 + */
7464 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
7465 + UART_PUT_IDR(port, ATMEL_US_RXBRK);
7466 + atmel_port->break_active = 0;
7467 + }
7468
7469 // TODO: All reads to CSR will clear these interrupts!
7470 if (pending & ATMEL_US_RIIC) port->icount.rng++;
7471 diff -x .git -Nur linux-2.6.22.1/drivers/spi/atmel_spi.c linux-avr32.git/drivers/spi/atmel_spi.c
7472 --- linux-2.6.22.1/drivers/spi/atmel_spi.c 2007-07-10 20:56:30.000000000 +0200
7473 +++ linux-avr32.git/drivers/spi/atmel_spi.c 2007-06-06 11:33:59.000000000 +0200
7474 @@ -412,8 +412,8 @@
7475 csr |= SPI_BIT(NCPHA);
7476
7477 /* TODO: DLYBS and DLYBCT */
7478 - csr |= SPI_BF(DLYBS, 10);
7479 - csr |= SPI_BF(DLYBCT, 10);
7480 + csr |= SPI_BF(DLYBS, 0);
7481 + csr |= SPI_BF(DLYBCT, 0);
7482
7483 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
7484 npcs_pin = (unsigned int)spi->controller_data;
7485 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.c linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.c
7486 --- linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.c 1970-01-01 01:00:00.000000000 +0100
7487 +++ linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.c 2007-07-12 14:00:19.000000000 +0200
7488 @@ -0,0 +1,2072 @@
7489 +/*
7490 + * Driver for the Atmel USBA high speed USB device controller
7491 + *
7492 + * Copyright (C) 2005-2007 Atmel Corporation
7493 + *
7494 + * This program is free software; you can redistribute it and/or modify
7495 + * it under the terms of the GNU General Public License version 2 as
7496 + * published by the Free Software Foundation.
7497 + */
7498 +/* #define DEBUG */
7499 +
7500 +#include <linux/clk.h>
7501 +#include <linux/module.h>
7502 +#include <linux/init.h>
7503 +#include <linux/interrupt.h>
7504 +#include <linux/io.h>
7505 +#include <linux/device.h>
7506 +#include <linux/dma-mapping.h>
7507 +#include <linux/list.h>
7508 +#include <linux/platform_device.h>
7509 +#include <linux/usb/ch9.h>
7510 +#include <linux/usb_gadget.h>
7511 +#include <linux/delay.h>
7512 +
7513 +#include <asm/gpio.h>
7514 +#include <asm/arch/board.h>
7515 +
7516 +#include "atmel_usba_udc.h"
7517 +
7518 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
7519 +
7520 +#define FIFO_IOMEM_ID 0
7521 +#define CTRL_IOMEM_ID 1
7522 +
7523 +#ifdef DEBUG
7524 +#define DBG_ERR 0x0001 /* report all error returns */
7525 +#define DBG_HW 0x0002 /* debug hardware initialization */
7526 +#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
7527 +#define DBG_INT 0x0008 /* interrupts */
7528 +#define DBG_BUS 0x0010 /* report changes in bus state */
7529 +#define DBG_QUEUE 0x0020 /* debug request queue processing */
7530 +#define DBG_FIFO 0x0040 /* debug FIFO contents */
7531 +#define DBG_DMA 0x0080 /* debug DMA handling */
7532 +#define DBG_REQ 0x0100 /* print out queued request length */
7533 +#define DBG_ALL 0xffff
7534 +#define DBG_NONE 0x0000
7535 +
7536 +#define DEBUG_LEVEL (DBG_ERR)
7537 +#define DBG(level, fmt, ...) \
7538 + do { \
7539 + if ((level) & DEBUG_LEVEL) \
7540 + printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
7541 + } while (0)
7542 +#else
7543 +#define DBG(level, fmt...)
7544 +#endif
7545 +
7546 +static struct usba_udc the_udc;
7547 +
7548 +#ifdef CONFIG_DEBUG_FS
7549 +#include <linux/debugfs.h>
7550 +#include <linux/uaccess.h>
7551 +
7552 +static int queue_dbg_open(struct inode *inode, struct file *file)
7553 +{
7554 + struct usba_ep *ep = inode->i_private;
7555 + struct usba_request *req, *req_copy;
7556 + struct list_head *queue_data;
7557 +
7558 + queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
7559 + if (!queue_data)
7560 + return -ENOMEM;
7561 + INIT_LIST_HEAD(queue_data);
7562 +
7563 + spin_lock_irq(&ep->udc->lock);
7564 + list_for_each_entry(req, &ep->queue, queue) {
7565 + req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
7566 + if (!req_copy)
7567 + goto fail;
7568 + memcpy(req_copy, req, sizeof(*req_copy));
7569 + list_add_tail(&req_copy->queue, queue_data);
7570 + }
7571 + spin_unlock_irq(&ep->udc->lock);
7572 +
7573 + file->private_data = queue_data;
7574 + return 0;
7575 +
7576 +fail:
7577 + spin_unlock_irq(&ep->udc->lock);
7578 + list_for_each_entry_safe(req, req_copy, queue_data, queue) {
7579 + list_del(&req->queue);
7580 + kfree(req);
7581 + }
7582 + kfree(queue_data);
7583 + return -ENOMEM;
7584 +}
7585 +
7586 +/*
7587 + * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
7588 + *
7589 + * b: buffer address
7590 + * l: buffer length
7591 + * I/i: interrupt/no interrupt
7592 + * Z/z: zero/no zero
7593 + * S/s: short ok/short not ok
7594 + * s: status
7595 + * n: nr_packets
7596 + * F/f: submitted/not submitted to FIFO
7597 + * D/d: using/not using DMA
7598 + * L/l: last transaction/not last transaction
7599 + */
7600 +static ssize_t queue_dbg_read(struct file *file, char __user *buf,
7601 + size_t nbytes, loff_t *ppos)
7602 +{
7603 + struct list_head *queue = file->private_data;
7604 + struct usba_request *req, *tmp_req;
7605 + size_t len, remaining, actual = 0;
7606 + char tmpbuf[38];
7607 +
7608 + if (!access_ok(VERIFY_WRITE, buf, nbytes))
7609 + return -EFAULT;
7610 +
7611 + mutex_lock(&file->f_dentry->d_inode->i_mutex);
7612 + list_for_each_entry_safe(req, tmp_req, queue, queue) {
7613 + len = snprintf(tmpbuf, sizeof(tmpbuf),
7614 + "%8p %08x %c%c%c %5d %c%c%c\n",
7615 + req->req.buf, req->req.length,
7616 + req->req.no_interrupt ? 'i' : 'I',
7617 + req->req.zero ? 'Z' : 'z',
7618 + req->req.short_not_ok ? 's' : 'S',
7619 + req->req.status,
7620 + req->submitted ? 'F' : 'f',
7621 + req->using_dma ? 'D' : 'd',
7622 + req->last_transaction ? 'L' : 'l');
7623 + len = min(len, sizeof(tmpbuf));
7624 + if (len > nbytes)
7625 + break;
7626 +
7627 + list_del(&req->queue);
7628 + kfree(req);
7629 +
7630 + remaining = __copy_to_user(buf, tmpbuf, len);
7631 + actual += len - remaining;
7632 + if (remaining)
7633 + break;
7634 +
7635 + nbytes -= len;
7636 + buf += len;
7637 + }
7638 + mutex_unlock(&file->f_dentry->d_inode->i_mutex);
7639 +
7640 + return actual;
7641 +}
7642 +
7643 +static int queue_dbg_release(struct inode *inode, struct file *file)
7644 +{
7645 + struct list_head *queue_data = file->private_data;
7646 + struct usba_request *req, *tmp_req;
7647 +
7648 + list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
7649 + list_del(&req->queue);
7650 + kfree(req);
7651 + }
7652 + kfree(queue_data);
7653 + return 0;
7654 +}
7655 +
7656 +static int regs_dbg_open(struct inode *inode, struct file *file)
7657 +{
7658 + struct usba_udc *udc;
7659 + unsigned int i;
7660 + u32 *data;
7661 + int ret = -ENOMEM;
7662 +
7663 + mutex_lock(&inode->i_mutex);
7664 + udc = inode->i_private;
7665 + data = kmalloc(inode->i_size, GFP_KERNEL);
7666 + if (!data)
7667 + goto out;
7668 +
7669 + spin_lock_irq(&udc->lock);
7670 + for (i = 0; i < inode->i_size / 4; i++)
7671 + data[i] = __raw_readl(udc->regs + i * 4);
7672 + spin_unlock_irq(&udc->lock);
7673 +
7674 + file->private_data = data;
7675 + ret = 0;
7676 +
7677 +out:
7678 + mutex_unlock(&inode->i_mutex);
7679 +
7680 + return ret;
7681 +}
7682 +
7683 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
7684 + size_t nbytes, loff_t *ppos)
7685 +{
7686 + struct inode *inode = file->f_dentry->d_inode;
7687 + int ret;
7688 +
7689 + mutex_lock(&inode->i_mutex);
7690 + ret = simple_read_from_buffer(buf, nbytes, ppos,
7691 + file->private_data,
7692 + file->f_dentry->d_inode->i_size);
7693 + mutex_unlock(&inode->i_mutex);
7694 +
7695 + return ret;
7696 +}
7697 +
7698 +static int regs_dbg_release(struct inode *inode, struct file *file)
7699 +{
7700 + kfree(file->private_data);
7701 + return 0;
7702 +}
7703 +
7704 +const struct file_operations queue_dbg_fops = {
7705 + .owner = THIS_MODULE,
7706 + .open = queue_dbg_open,
7707 + .llseek = no_llseek,
7708 + .read = queue_dbg_read,
7709 + .release = queue_dbg_release,
7710 +};
7711 +
7712 +const struct file_operations regs_dbg_fops = {
7713 + .owner = THIS_MODULE,
7714 + .open = regs_dbg_open,
7715 + .llseek = generic_file_llseek,
7716 + .read = regs_dbg_read,
7717 + .release = regs_dbg_release,
7718 +};
7719 +
7720 +static void usba_ep_init_debugfs(struct usba_udc *udc,
7721 + struct usba_ep *ep)
7722 +{
7723 + struct dentry *ep_root;
7724 +
7725 + ep_root = debugfs_create_dir(ep_name(ep), udc->debugfs_root);
7726 + if (!ep_root)
7727 + goto err_root;
7728 + ep->debugfs_dir = ep_root;
7729 +
7730 + ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
7731 + ep, &queue_dbg_fops);
7732 + if (!ep->debugfs_queue)
7733 + goto err_queue;
7734 +
7735 + if (ep_can_dma(ep)) {
7736 + ep->debugfs_dma_status
7737 + = debugfs_create_u32("dma_status", 0400, ep_root,
7738 + &ep->last_dma_status);
7739 + if (!ep->debugfs_dma_status)
7740 + goto err_dma_status;
7741 + }
7742 + if (ep_is_control(ep)) {
7743 + ep->debugfs_state
7744 + = debugfs_create_u32("state", 0400, ep_root,
7745 + &ep->state);
7746 + if (!ep->debugfs_state)
7747 + goto err_state;
7748 + }
7749 +
7750 + return;
7751 +
7752 +err_state:
7753 + if (ep_can_dma(ep))
7754 + debugfs_remove(ep->debugfs_dma_status);
7755 +err_dma_status:
7756 + debugfs_remove(ep->debugfs_queue);
7757 +err_queue:
7758 + debugfs_remove(ep_root);
7759 +err_root:
7760 + dev_err(&ep->udc->pdev->dev,
7761 + "failed to create debugfs directory for %s\n", ep_name(ep));
7762 +}
7763 +
7764 +static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
7765 +{
7766 + debugfs_remove(ep->debugfs_queue);
7767 + debugfs_remove(ep->debugfs_dma_status);
7768 + debugfs_remove(ep->debugfs_state);
7769 + debugfs_remove(ep->debugfs_dir);
7770 + ep->debugfs_dma_status = NULL;
7771 + ep->debugfs_dir = NULL;
7772 +}
7773 +
7774 +static void usba_init_debugfs(struct usba_udc *udc)
7775 +{
7776 + struct dentry *root, *regs;
7777 + struct resource *regs_resource;
7778 +
7779 + root = debugfs_create_dir(udc->gadget.name, NULL);
7780 + if (IS_ERR(root) || !root)
7781 + goto err_root;
7782 + udc->debugfs_root = root;
7783 +
7784 + regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
7785 + if (!regs)
7786 + goto err_regs;
7787 +
7788 + regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
7789 + CTRL_IOMEM_ID);
7790 + regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
7791 + udc->debugfs_regs = regs;
7792 +
7793 + usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
7794 +
7795 + return;
7796 +
7797 +err_regs:
7798 + debugfs_remove(root);
7799 +err_root:
7800 + udc->debugfs_root = NULL;
7801 + dev_err(&udc->pdev->dev, "debugfs is not available\n");
7802 +}
7803 +
7804 +static void usba_cleanup_debugfs(struct usba_udc *udc)
7805 +{
7806 + usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
7807 + debugfs_remove(udc->debugfs_regs);
7808 + debugfs_remove(udc->debugfs_root);
7809 + udc->debugfs_regs = NULL;
7810 + udc->debugfs_root = NULL;
7811 +}
7812 +#else
7813 +static inline void usba_ep_init_debugfs(struct usba_udc *udc,
7814 + struct usba_ep *ep)
7815 +{
7816 +
7817 +}
7818 +
7819 +static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
7820 +{
7821 +
7822 +}
7823 +
7824 +static inline void usba_init_debugfs(struct usba_udc *udc)
7825 +{
7826 +
7827 +}
7828 +
7829 +static inline void usba_cleanup_debugfs(struct usba_udc *udc)
7830 +{
7831 +
7832 +}
7833 +#endif
7834 +
7835 +static int vbus_is_present(struct usba_udc *udc)
7836 +{
7837 + if (udc->vbus_pin != -1)
7838 + return gpio_get_value(udc->vbus_pin);
7839 +
7840 + /* No Vbus detection: Assume always present */
7841 + return 1;
7842 +}
7843 +
7844 +static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
7845 +{
7846 + unsigned long tmp;
7847 +
7848 + DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
7849 + for (; len > 0; len -= 4, buf += 4, fifo += 4) {
7850 + tmp = *(unsigned long *)buf;
7851 + if (len >= 4) {
7852 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
7853 + __raw_writel(tmp, fifo);
7854 + } else {
7855 + do {
7856 + DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
7857 + __raw_writeb(tmp >> 24, fifo);
7858 + fifo++;
7859 + tmp <<= 8;
7860 + } while (--len);
7861 + break;
7862 + }
7863 + }
7864 +}
7865 +
7866 +static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
7867 +{
7868 + union {
7869 + unsigned long *w;
7870 + unsigned char *b;
7871 + } p;
7872 + unsigned long tmp;
7873 +
7874 + DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
7875 + for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
7876 + if (len >= 4) {
7877 + tmp = __raw_readl(fifo);
7878 + *p.w = tmp;
7879 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
7880 + } else {
7881 + do {
7882 + tmp = __raw_readb(fifo);
7883 + *p.b = tmp;
7884 + DBG(DBG_FIFO, " -> %02lx\n", tmp);
7885 + fifo++, p.b++;
7886 + } while (--len);
7887 + }
7888 + }
7889 +}
7890 +
7891 +static void next_fifo_transaction(struct usba_ep *ep,
7892 + struct usba_request *req)
7893 +{
7894 + unsigned int transaction_len;
7895 +
7896 + transaction_len = req->req.length - req->req.actual;
7897 + req->last_transaction = 1;
7898 + if (transaction_len > ep->ep.maxpacket) {
7899 + transaction_len = ep->ep.maxpacket;
7900 + req->last_transaction = 0;
7901 + } else if (transaction_len == ep->ep.maxpacket
7902 + && req->req.zero) {
7903 + req->last_transaction = 0;
7904 + }
7905 + DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
7906 + ep_name(ep), req, transaction_len,
7907 + req->last_transaction ? ", done" : "");
7908 +
7909 + copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
7910 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
7911 + req->req.actual += transaction_len;
7912 +}
7913 +
7914 +static void submit_request(struct usba_ep *ep, struct usba_request *req)
7915 +{
7916 + DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
7917 + ep_name(ep), req, req->req.length);
7918 +
7919 + req->req.actual = 0;
7920 + req->submitted = 1;
7921 +
7922 + if (req->using_dma) {
7923 + if (req->req.length == 0) {
7924 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
7925 + return;
7926 + }
7927 +
7928 + if (req->req.zero)
7929 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(SHORT_PACKET));
7930 + else
7931 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(SHORT_PACKET));
7932 +
7933 + usba_dma_writel(ep, ADDRESS, req->req.dma);
7934 + usba_dma_writel(ep, CONTROL, req->ctrl);
7935 + } else {
7936 + next_fifo_transaction(ep, req);
7937 + if (req->last_transaction) {
7938 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
7939 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
7940 + } else {
7941 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
7942 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
7943 + }
7944 + }
7945 +}
7946 +
7947 +static void submit_next_request(struct usba_ep *ep)
7948 +{
7949 + struct usba_request *req;
7950 +
7951 + if (list_empty(&ep->queue)) {
7952 + usba_ep_writel(ep, CTL_DIS, (USBA_BIT(TX_PK_RDY)
7953 + | USBA_BIT(RX_BK_RDY)));
7954 + return;
7955 + }
7956 +
7957 + req = list_entry(ep->queue.next, struct usba_request, queue);
7958 + if (!req->submitted)
7959 + submit_request(ep, req);
7960 +}
7961 +
7962 +static void send_status(struct usba_udc *udc, struct usba_ep *ep)
7963 +{
7964 + ep->state = STATUS_STAGE_IN;
7965 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
7966 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
7967 +}
7968 +
7969 +static void receive_data(struct usba_ep *ep)
7970 +{
7971 + struct usba_udc *udc = ep->udc;
7972 + struct usba_request *req;
7973 + unsigned long status;
7974 + unsigned int bytecount, nr_busy;
7975 + int is_complete = 0;
7976 +
7977 + status = usba_ep_readl(ep, STA);
7978 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
7979 +
7980 + DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
7981 +
7982 + while (nr_busy > 0) {
7983 + if (list_empty(&ep->queue)) {
7984 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
7985 + break;
7986 + }
7987 + req = list_entry(ep->queue.next,
7988 + struct usba_request, queue);
7989 +
7990 + bytecount = USBA_BFEXT(BYTE_COUNT, status);
7991 +
7992 + if (status & (1 << 31))
7993 + is_complete = 1;
7994 + if (req->req.actual + bytecount >= req->req.length) {
7995 + is_complete = 1;
7996 + bytecount = req->req.length - req->req.actual;
7997 + }
7998 +
7999 + copy_from_fifo(req->req.buf + req->req.actual,
8000 + ep->fifo, bytecount);
8001 + req->req.actual += bytecount;
8002 +
8003 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
8004 +
8005 + if (is_complete) {
8006 + DBG(DBG_QUEUE, "%s: request done\n", ep_name(ep));
8007 + req->req.status = 0;
8008 + list_del_init(&req->queue);
8009 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
8010 + req->req.complete(&ep->ep, &req->req);
8011 + }
8012 +
8013 + status = usba_ep_readl(ep, STA);
8014 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
8015 +
8016 + if (is_complete && ep_is_control(ep)) {
8017 + send_status(udc, ep);
8018 + break;
8019 + }
8020 + }
8021 +}
8022 +
8023 +static void request_complete(struct usba_ep *ep,
8024 + struct usba_request *req,
8025 + int status)
8026 +{
8027 + struct usba_udc *udc = ep->udc;
8028 +
8029 + WARN_ON(!list_empty(&req->queue));
8030 +
8031 + if (req->req.status == -EINPROGRESS)
8032 + req->req.status = status;
8033 +
8034 + if (req->mapped) {
8035 + dma_unmap_single(
8036 + &udc->pdev->dev, req->req.dma, req->req.length,
8037 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
8038 + req->req.dma = DMA_ADDR_INVALID;
8039 + req->mapped = 0;
8040 + }
8041 +
8042 + DBG(DBG_GADGET | DBG_REQ,
8043 + "%s: req %p complete: status %d, actual %u\n",
8044 + ep_name(ep), req, req->req.status, req->req.actual);
8045 + req->req.complete(&ep->ep, &req->req);
8046 +}
8047 +
8048 +static void request_complete_list(struct usba_ep *ep,
8049 + struct list_head *list,
8050 + int status)
8051 +{
8052 + struct usba_request *req, *tmp_req;
8053 +
8054 + list_for_each_entry_safe(req, tmp_req, list, queue) {
8055 + list_del_init(&req->queue);
8056 + request_complete(ep, req, status);
8057 + }
8058 +}
8059 +
8060 +static int usba_ep_enable(struct usb_ep *_ep,
8061 + const struct usb_endpoint_descriptor *desc)
8062 +{
8063 + struct usba_ep *ep = to_usba_ep(_ep);
8064 + struct usba_udc *udc = ep->udc;
8065 + unsigned long flags, ept_cfg, maxpacket;
8066 +
8067 + DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep_name(ep), desc);
8068 +
8069 + maxpacket = le16_to_cpu(desc->wMaxPacketSize);
8070 +
8071 + if (ep->index == 0
8072 + || desc->bDescriptorType != USB_DT_ENDPOINT
8073 + || ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
8074 + != ep->index)
8075 + || maxpacket == 0
8076 + || maxpacket > ep->fifo_size) {
8077 + DBG(DBG_ERR, "ep_enable: Invalid argument");
8078 + return -EINVAL;
8079 + }
8080 +
8081 + ep->is_isoc = 0;
8082 + ep->is_in = 0;
8083 +
8084 + if ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
8085 + == USB_ENDPOINT_XFER_ISOC) {
8086 + if (!ep->can_isoc) {
8087 + DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
8088 + ep_name(ep));
8089 + return -EINVAL;
8090 + }
8091 + ep->is_isoc = 1;
8092 + }
8093 +
8094 + if (maxpacket <= 8)
8095 + ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
8096 + else
8097 + /* LSB is bit 1, not 0 */
8098 + ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
8099 + DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
8100 + ep_name(ep), ept_cfg, maxpacket);
8101 +
8102 + if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
8103 + ep->is_in = 1;
8104 + ept_cfg |= USBA_BIT(EPT_DIR);
8105 + }
8106 +
8107 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
8108 + case USB_ENDPOINT_XFER_CONTROL:
8109 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
8110 + break;
8111 + case USB_ENDPOINT_XFER_ISOC:
8112 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
8113 + break;
8114 + case USB_ENDPOINT_XFER_BULK:
8115 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
8116 + break;
8117 + case USB_ENDPOINT_XFER_INT:
8118 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
8119 + break;
8120 + }
8121 + ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
8122 +
8123 + spin_lock_irqsave(&ep->udc->lock, flags);
8124 +
8125 + if (ep->desc) {
8126 + spin_unlock_irqrestore(&ep->udc->lock, flags);
8127 + DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
8128 + return -EBUSY;
8129 + }
8130 +
8131 + ep->desc = desc;
8132 + ep->ep.maxpacket = maxpacket;
8133 +
8134 + usba_ep_writel(ep, CFG, ept_cfg);
8135 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
8136 +
8137 + if (ep_can_dma(ep)) {
8138 + u32 ctrl;
8139 +
8140 + usba_writel(udc, INT_ENB,
8141 + (usba_readl(udc, INT_ENB)
8142 + | USBA_BF(EPT_INT, 1 << ep->index)
8143 + | USBA_BF(DMA_INT, 1 << ep->index)));
8144 + ctrl = USBA_BIT(AUTO_VALID) | USBA_BIT(INTDIS_DMA);
8145 + usba_ep_writel(ep, CTL_ENB, ctrl);
8146 + } else {
8147 + usba_writel(udc, INT_ENB,
8148 + (usba_readl(udc, INT_ENB)
8149 + | USBA_BF(EPT_INT, 1 << ep->index)));
8150 + }
8151 +
8152 + spin_unlock_irqrestore(&udc->lock, flags);
8153 +
8154 + DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
8155 + (unsigned long)usba_ep_readl(ep, CFG));
8156 + DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
8157 + (unsigned long)usba_readl(udc, INT_ENB));
8158 +
8159 + return 0;
8160 +}
8161 +
8162 +static int usba_ep_disable(struct usb_ep *_ep)
8163 +{
8164 + struct usba_ep *ep = to_usba_ep(_ep);
8165 + struct usba_udc *udc = ep->udc;
8166 + LIST_HEAD(req_list);
8167 + unsigned long flags;
8168 +
8169 + DBG(DBG_GADGET, "ep_disable: %s\n", ep_name(ep));
8170 +
8171 + spin_lock_irqsave(&udc->lock, flags);
8172 +
8173 + if (!ep->desc) {
8174 + spin_unlock_irqrestore(&udc->lock, flags);
8175 + DBG(DBG_ERR, "ep_disable: %s not enabled\n",
8176 + ep_name(ep));
8177 + return -EINVAL;
8178 + }
8179 + ep->desc = NULL;
8180 +
8181 + list_splice_init(&ep->queue, &req_list);
8182 + if (ep_can_dma(ep)) {
8183 + usba_dma_writel(ep, CONTROL, 0);
8184 + usba_dma_writel(ep, ADDRESS, 0);
8185 + usba_dma_readl(ep, STATUS);
8186 + }
8187 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(EPT_ENABLE));
8188 + usba_writel(udc, INT_ENB, (usba_readl(udc, INT_ENB)
8189 + & ~USBA_BF(EPT_INT, 1 << ep->index)));
8190 +
8191 + spin_unlock_irqrestore(&udc->lock, flags);
8192 +
8193 + request_complete_list(ep, &req_list, -ESHUTDOWN);
8194 +
8195 + return 0;
8196 +}
8197 +
8198 +static struct usb_request *
8199 +usba_ep_alloc_request(struct usb_ep *_ep, unsigned gfp_flags)
8200 +{
8201 + struct usba_request *req;
8202 +
8203 + DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
8204 +
8205 + req = kzalloc(sizeof(*req), gfp_flags);
8206 + if (!req)
8207 + return NULL;
8208 +
8209 + INIT_LIST_HEAD(&req->queue);
8210 + req->req.dma = DMA_ADDR_INVALID;
8211 +
8212 + return &req->req;
8213 +}
8214 +
8215 +static void
8216 +usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
8217 +{
8218 + struct usba_request *req = to_usba_req(_req);
8219 +
8220 + DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
8221 +
8222 + kfree(req);
8223 +}
8224 +
8225 +static void *usba_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
8226 + dma_addr_t *dma, unsigned gfp_flags)
8227 +{
8228 + void *buf;
8229 +
8230 + if (bytes < L1_CACHE_BYTES)
8231 + bytes = L1_CACHE_BYTES;
8232 +
8233 + buf = kmalloc(bytes, gfp_flags);
8234 +
8235 + /*
8236 + * Seems like we have to map the buffer any chance we get.
8237 + * ether.c wants us to initialize the dma member of a
8238 + * different request than the one receiving the buffer, so one
8239 + * never knows...
8240 + *
8241 + * Ah, screw it. The ether driver is probably wrong, and this
8242 + * is not the right place to do the mapping. The driver
8243 + * shouldn't mess with our DMA mappings anyway.
8244 + */
8245 + *dma = DMA_ADDR_INVALID;
8246 +
8247 + return buf;
8248 +}
8249 +
8250 +static void usba_ep_free_buffer(struct usb_ep *_ep, void *buf,
8251 + dma_addr_t dma, unsigned bytes)
8252 +{
8253 + DBG(DBG_GADGET, "ep_free_buffer: %s, buf %p (size %u)\n",
8254 + _ep->name, buf, bytes);
8255 + kfree(buf);
8256 +}
8257 +
8258 +static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
8259 + struct usba_request *req, gfp_t gfp_flags)
8260 +{
8261 + unsigned long flags;
8262 + int ret;
8263 +
8264 + DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
8265 + ep_name(ep), req->req.length, req->req.dma,
8266 + req->req.zero ? 'Z' : 'z',
8267 + req->req.short_not_ok ? 'S' : 's',
8268 + req->req.no_interrupt ? 'I' : 'i');
8269 +
8270 + if (req->req.length > 0x10000) {
8271 + /* Lengths from 0 to 65536 (inclusive) are supported */
8272 + DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
8273 + return -EINVAL;
8274 + }
8275 +
8276 + req->using_dma = 1;
8277 +
8278 + if (req->req.dma == DMA_ADDR_INVALID) {
8279 + req->req.dma = dma_map_single(
8280 + &udc->pdev->dev, req->req.buf, req->req.length,
8281 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
8282 + req->mapped = 1;
8283 + } else {
8284 + dma_sync_single_for_device(
8285 + &udc->pdev->dev, req->req.dma, req->req.length,
8286 + ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
8287 + req->mapped = 0;
8288 + }
8289 +
8290 + req->ctrl = (USBA_BF(DMA_BUF_LEN, req->req.length)
8291 + | USBA_BIT(DMA_CH_EN) | USBA_BIT(DMA_END_BUF_IE)
8292 + | USBA_BIT(DMA_END_TR_EN) | USBA_BIT(DMA_END_TR_IE));
8293 +
8294 + if (ep_is_in(ep))
8295 + req->ctrl |= USBA_BIT(DMA_END_BUF_EN);
8296 +
8297 + /*
8298 + * Add this request to the queue and submit for DMA if
8299 + * possible. Check if we're still alive first -- we may have
8300 + * received a reset since last time we checked.
8301 + */
8302 + ret = -ESHUTDOWN;
8303 + spin_lock_irqsave(&udc->lock, flags);
8304 + if (ep->desc) {
8305 + if (list_empty(&ep->queue))
8306 + submit_request(ep, req);
8307 +
8308 + list_add_tail(&req->queue, &ep->queue);
8309 + ret = 0;
8310 + }
8311 + spin_unlock_irqrestore(&udc->lock, flags);
8312 +
8313 + return ret;
8314 +}
8315 +
8316 +static int usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
8317 + gfp_t gfp_flags)
8318 +{
8319 + struct usba_request *req = to_usba_req(_req);
8320 + struct usba_ep *ep = to_usba_ep(_ep);
8321 + struct usba_udc *udc = ep->udc;
8322 + unsigned long flags;
8323 + int ret;
8324 +
8325 + DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ,
8326 + "%s: queue req %p, len %u\n", ep_name(ep), req, _req->length);
8327 +
8328 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN
8329 + || !ep->desc)
8330 + return -ESHUTDOWN;
8331 +
8332 + req->submitted = 0;
8333 + req->using_dma = 0;
8334 + req->last_transaction = 0;
8335 +
8336 + _req->status = -EINPROGRESS;
8337 + _req->actual = 0;
8338 +
8339 + if (ep_can_dma(ep))
8340 + return queue_dma(udc, ep, req, gfp_flags);
8341 +
8342 + /* May have received a reset since last time we checked */
8343 + ret = -ESHUTDOWN;
8344 + spin_lock_irqsave(&udc->lock, flags);
8345 + if (ep->desc) {
8346 + list_add_tail(&req->queue, &ep->queue);
8347 +
8348 + if (ep_is_in(ep)
8349 + || (ep_is_control(ep)
8350 + && (ep->state == DATA_STAGE_IN
8351 + || ep->state == STATUS_STAGE_IN)))
8352 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_PK_RDY));
8353 + else
8354 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(RX_BK_RDY));
8355 + ret = 0;
8356 + }
8357 + spin_unlock_irqrestore(&udc->lock, flags);
8358 +
8359 + return ret;
8360 +}
8361 +
8362 +static void usba_update_req(struct usba_ep *ep, struct usba_request *req,
8363 + u32 status)
8364 +{
8365 + req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
8366 +}
8367 +
8368 +static int stop_dma(struct usba_ep *ep, u32 *pstatus)
8369 +{
8370 + unsigned int timeout;
8371 + u32 status;
8372 +
8373 + /*
8374 + * Stop the DMA controller. When writing both CH_EN
8375 + * and LINK to 0, the other bits are not affected.
8376 + */
8377 + usba_dma_writel(ep, CONTROL, 0);
8378 +
8379 + /* Wait for the FIFO to empty */
8380 + for (timeout = 40; timeout; --timeout) {
8381 + status = usba_dma_readl(ep, STATUS);
8382 + if (!(status & USBA_BIT(DMA_CH_EN)))
8383 + break;
8384 + udelay(1);
8385 + }
8386 +
8387 + if (pstatus)
8388 + *pstatus = status;
8389 +
8390 + if (timeout == 0) {
8391 + dev_err(&ep->udc->pdev->dev,
8392 + "%s: timed out waiting for DMA FIFO to empty\n",
8393 + ep_name(ep));
8394 + return -ETIMEDOUT;
8395 + }
8396 +
8397 + return 0;
8398 +}
8399 +
8400 +static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
8401 +{
8402 + struct usba_ep *ep = to_usba_ep(_ep);
8403 + struct usba_udc *udc = ep->udc;
8404 + struct usba_request *req = to_usba_req(_req);
8405 + unsigned long flags;
8406 + u32 status;
8407 +
8408 + DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
8409 + ep_name(ep), req);
8410 +
8411 + spin_lock_irqsave(&udc->lock, flags);
8412 +
8413 + if (req->using_dma) {
8414 + /*
8415 + * If this request is currently being transferred,
8416 + * stop the DMA controller and reset the FIFO.
8417 + */
8418 + if (ep->queue.next == &req->queue) {
8419 + status = usba_dma_readl(ep, STATUS);
8420 + if (status & USBA_BIT(DMA_CH_EN))
8421 + stop_dma(ep, &status);
8422 +
8423 +#ifdef CONFIG_DEBUG_FS
8424 + ep->last_dma_status = status;
8425 +#endif
8426 +
8427 + usba_writel(udc, EPT_RST,
8428 + 1 << ep_index(ep));
8429 +
8430 + usba_update_req(ep, req, status);
8431 + }
8432 + }
8433 +
8434 + /*
8435 + * Errors should stop the queue from advancing until the
8436 + * completion function returns.
8437 + */
8438 + list_del_init(&req->queue);
8439 + spin_unlock_irqrestore(&udc->lock, flags);
8440 +
8441 + request_complete(ep, req, -ECONNRESET);
8442 +
8443 + /* Process the next request if any */
8444 + spin_lock_irqsave(&udc->lock, flags);
8445 + submit_next_request(ep);
8446 + spin_unlock_irqrestore(&udc->lock, flags);
8447 +
8448 + return 0;
8449 +}
8450 +
8451 +static int usba_ep_set_halt(struct usb_ep *_ep, int value)
8452 +{
8453 + struct usba_ep *ep = to_usba_ep(_ep);
8454 + struct usba_udc *udc = ep->udc;
8455 + unsigned long flags;
8456 + int ret = 0;
8457 +
8458 + DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep_name(ep),
8459 + value ? "set" : "clear");
8460 +
8461 + if (!ep->desc) {
8462 + DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
8463 + ep_name(ep));
8464 + return -ENODEV;
8465 + }
8466 + if (ep_is_isochronous(ep)) {
8467 + DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
8468 + ep_name(ep));
8469 + return -ENOTTY;
8470 + }
8471 +
8472 + spin_lock_irqsave(&udc->lock, flags);
8473 +
8474 + /*
8475 + * We can't halt IN endpoints while there are still data to be
8476 + * transferred
8477 + */
8478 + if (!list_empty(&ep->queue)
8479 + || ((value && ep_is_in(ep)
8480 + && (usba_ep_readl(ep, STA)
8481 + & USBA_BF(BUSY_BANKS, -1L))))) {
8482 + ret = -EAGAIN;
8483 + } else {
8484 + if (value)
8485 + usba_ep_writel(ep, SET_STA, USBA_BIT(FORCE_STALL));
8486 + else
8487 + usba_ep_writel(ep, CLR_STA, (USBA_BIT(FORCE_STALL)
8488 + | USBA_BIT(TOGGLE_SEQ)));
8489 + usba_ep_readl(ep, STA);
8490 + }
8491 +
8492 + spin_unlock_irqrestore(&udc->lock, flags);
8493 +
8494 + return ret;
8495 +}
8496 +
8497 +static int usba_ep_fifo_status(struct usb_ep *_ep)
8498 +{
8499 + struct usba_ep *ep = to_usba_ep(_ep);
8500 +
8501 + return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
8502 +}
8503 +
8504 +static void usba_ep_fifo_flush(struct usb_ep *_ep)
8505 +{
8506 + struct usba_ep *ep = to_usba_ep(_ep);
8507 + struct usba_udc *udc = ep->udc;
8508 +
8509 + usba_writel(udc, EPT_RST, 1 << ep->index);
8510 +}
8511 +
8512 +struct usb_ep_ops usba_ep_ops = {
8513 + .enable = usba_ep_enable,
8514 + .disable = usba_ep_disable,
8515 + .alloc_request = usba_ep_alloc_request,
8516 + .free_request = usba_ep_free_request,
8517 + .alloc_buffer = usba_ep_alloc_buffer,
8518 + .free_buffer = usba_ep_free_buffer,
8519 + .queue = usba_ep_queue,
8520 + .dequeue = usba_ep_dequeue,
8521 + .set_halt = usba_ep_set_halt,
8522 + .fifo_status = usba_ep_fifo_status,
8523 + .fifo_flush = usba_ep_fifo_flush,
8524 +};
8525 +
8526 +static int usba_udc_get_frame(struct usb_gadget *gadget)
8527 +{
8528 + struct usba_udc *udc = to_usba_udc(gadget);
8529 +
8530 + return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
8531 +}
8532 +
8533 +struct usb_gadget_ops usba_udc_ops = {
8534 + .get_frame = usba_udc_get_frame,
8535 +};
8536 +
8537 +#define EP(nam, type, idx, dma, isoc) \
8538 +{ \
8539 + .ep = { \
8540 + .ops = &usba_ep_ops, \
8541 + .name = nam, \
8542 + .maxpacket = type##_FIFO_SIZE, \
8543 + }, \
8544 + .udc = &the_udc, \
8545 + .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
8546 + .fifo_size = type##_FIFO_SIZE, \
8547 + .nr_banks = type##_NR_BANKS, \
8548 + .index = idx, \
8549 + .can_dma = dma, \
8550 + .can_isoc = isoc, \
8551 +}
8552 +
8553 +static struct usba_ep usba_ep[] = {
8554 + EP("ep0", EP0, 0, 0, 0),
8555 + EP("ep1in-bulk", BULK, 1, 1, 0),
8556 + EP("ep2out-bulk", BULK, 2, 1, 0),
8557 + EP("ep3in-iso", ISO, 3, 1, 1),
8558 + EP("ep4out-iso", ISO, 4, 1, 1),
8559 + EP("ep5in-int", INT, 5, 1, 0),
8560 + EP("ep6out-int", INT, 6, 1, 0),
8561 +};
8562 +#undef EP
8563 +
8564 +static struct usb_endpoint_descriptor usba_ep0_desc = {
8565 + .bLength = USB_DT_ENDPOINT_SIZE,
8566 + .bDescriptorType = USB_DT_ENDPOINT,
8567 + .bEndpointAddress = 0,
8568 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
8569 + .wMaxPacketSize = __constant_cpu_to_le16(64),
8570 + /* FIXME: I have no idea what to put here */
8571 + .bInterval = 1,
8572 +};
8573 +
8574 +static void nop_release(struct device *dev)
8575 +{
8576 +
8577 +}
8578 +
8579 +static struct usba_udc the_udc = {
8580 + .gadget = {
8581 + .ops = &usba_udc_ops,
8582 + .ep0 = &usba_ep[0].ep,
8583 + .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
8584 + .is_dualspeed = 1,
8585 + .name = "atmel_usba_udc",
8586 + .dev = {
8587 + .bus_id = "gadget",
8588 + .release = nop_release,
8589 + },
8590 + },
8591 +
8592 + .lock = SPIN_LOCK_UNLOCKED,
8593 +};
8594 +
8595 +/*
8596 + * Called with interrupts disabled and udc->lock held.
8597 + */
8598 +static void reset_all_endpoints(struct usba_udc *udc)
8599 +{
8600 + struct usba_ep *ep;
8601 + struct usba_request *req, *tmp_req;
8602 +
8603 + usba_writel(udc, EPT_RST, ~0UL);
8604 +
8605 + ep = to_usba_ep(udc->gadget.ep0);
8606 + list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
8607 + list_del_init(&req->queue);
8608 + request_complete(ep, req, -ECONNRESET);
8609 + }
8610 +
8611 + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
8612 + if (ep->desc)
8613 + usba_ep_disable(&ep->ep);
8614 + }
8615 +}
8616 +
8617 +static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
8618 +{
8619 + struct usba_ep *ep;
8620 +
8621 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
8622 + return to_usba_ep(udc->gadget.ep0);
8623 +
8624 + list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
8625 + u8 bEndpointAddress;
8626 +
8627 + if (!ep->desc)
8628 + continue;
8629 + bEndpointAddress = ep->desc->bEndpointAddress;
8630 + if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
8631 + continue;
8632 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
8633 + == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
8634 + return ep;
8635 + }
8636 +
8637 + return NULL;
8638 +}
8639 +
8640 +/* Called with interrupts disabled and udc->lock held */
8641 +static inline void set_protocol_stall(struct usba_udc *udc,
8642 + struct usba_ep *ep)
8643 +{
8644 + usba_ep_writel(ep, SET_STA, USBA_BIT(FORCE_STALL));
8645 + ep->state = WAIT_FOR_SETUP;
8646 +}
8647 +
8648 +static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
8649 +{
8650 + if (usba_ep_readl(ep, STA) & USBA_BIT(FORCE_STALL))
8651 + return 1;
8652 + return 0;
8653 +}
8654 +
8655 +static inline void set_address(struct usba_udc *udc, unsigned int addr)
8656 +{
8657 + u32 regval;
8658 +
8659 + DBG(DBG_BUS, "setting address %u...\n", addr);
8660 + regval = usba_readl(udc, CTRL);
8661 + regval = USBA_BFINS(DEV_ADDR, addr, regval);
8662 + usba_writel(udc, CTRL, regval);
8663 +}
8664 +
8665 +static int do_test_mode(struct usba_udc *udc)
8666 +{
8667 + static const char test_packet_buffer[] = {
8668 + /* JKJKJKJK * 9 */
8669 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8670 + /* JJKKJJKK * 8 */
8671 + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
8672 + /* JJKKJJKK * 8 */
8673 + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
8674 + /* JJJJJJJKKKKKKK * 8 */
8675 + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
8676 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
8677 + /* JJJJJJJK * 8 */
8678 + 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
8679 + /* {JKKKKKKK * 10}, JK */
8680 + 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
8681 + };
8682 + struct device *dev = &udc->pdev->dev;
8683 + struct usba_ep *ep;
8684 + int test_mode;
8685 +
8686 + test_mode = udc->test_mode;
8687 +
8688 + /* Start from a clean slate */
8689 + reset_all_endpoints(udc);
8690 +
8691 + switch (test_mode) {
8692 + case 0x0100:
8693 + /* Test_J */
8694 + usba_writel(udc, TST, USBA_BIT(TST_J_MODE));
8695 + dev_info(dev, "Entering Test_J mode...\n");
8696 + break;
8697 + case 0x0200:
8698 + /* Test_K */
8699 + usba_writel(udc, TST, USBA_BIT(TST_K_MODE));
8700 + dev_info(dev, "Entering Test_K mode...\n");
8701 + break;
8702 + case 0x0300:
8703 + /*
8704 + * Test_SE0_NAK: Force high-speed mode and set up ep0
8705 + * for Bulk IN transfers
8706 + */
8707 + ep = &usba_ep[0];
8708 + usba_writel(udc, TST,
8709 + USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
8710 + usba_ep_writel(ep, CFG,
8711 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
8712 + | USBA_BIT(EPT_DIR)
8713 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
8714 + | USBA_BF(BK_NUMBER, 1));
8715 + if (!(usba_ep_readl(ep, CFG) & USBA_BIT(EPT_MAPPED))) {
8716 + set_protocol_stall(udc, ep);
8717 + dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
8718 + } else {
8719 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
8720 + dev_info(dev, "Entering Test_SE0_NAK mode...\n");
8721 + }
8722 + break;
8723 + case 0x0400:
8724 + /* Test_Packet */
8725 + ep = &usba_ep[0];
8726 + usba_ep_writel(ep, CFG,
8727 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
8728 + | USBA_BIT(EPT_DIR)
8729 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
8730 + | USBA_BF(BK_NUMBER, 1));
8731 + if (!(usba_ep_readl(ep, CFG) & USBA_BIT(EPT_MAPPED))) {
8732 + set_protocol_stall(udc, ep);
8733 + dev_err(dev, "Test_Packet: ep0 not mapped\n");
8734 + } else {
8735 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(EPT_ENABLE));
8736 + usba_writel(udc, TST, USBA_BIT(TST_PKT_MODE));
8737 + copy_to_fifo(ep->fifo, test_packet_buffer,
8738 + sizeof(test_packet_buffer));
8739 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
8740 + dev_info(dev, "Entering Test_Packet mode...\n");
8741 + }
8742 + break;
8743 + default:
8744 + dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
8745 + return -EINVAL;
8746 + }
8747 +
8748 + return 0;
8749 +}
8750 +
8751 +/* Avoid overly long expressions */
8752 +static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
8753 +{
8754 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
8755 + return true;
8756 + return false;
8757 +}
8758 +
8759 +static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
8760 +{
8761 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
8762 + return true;
8763 + return false;
8764 +}
8765 +
8766 +static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
8767 +{
8768 + if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
8769 + return true;
8770 + return false;
8771 +}
8772 +
8773 +static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
8774 + struct usb_ctrlrequest *crq)
8775 +{
8776 + switch (crq->bRequest) {
8777 + case USB_REQ_GET_STATUS: {
8778 + u16 status;
8779 +
8780 + if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
8781 + /* Self-powered, no remote wakeup */
8782 + status = __constant_cpu_to_le16(1 << 0);
8783 + } else if (crq->bRequestType
8784 + == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
8785 + status = __constant_cpu_to_le16(0);
8786 + } else if (crq->bRequestType
8787 + == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
8788 + struct usba_ep *target;
8789 +
8790 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
8791 + if (!target)
8792 + goto stall;
8793 +
8794 + status = 0;
8795 + if (is_stalled(udc, target))
8796 + status |= __constant_cpu_to_le16(1);
8797 + } else {
8798 + goto delegate;
8799 + }
8800 +
8801 + /* Write directly to the FIFO. No queueing is done. */
8802 + if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
8803 + goto stall;
8804 + ep->state = DATA_STAGE_IN;
8805 + __raw_writew(status, ep->fifo);
8806 + usba_ep_writel(ep, SET_STA, USBA_BIT(TX_PK_RDY));
8807 + break;
8808 + }
8809 +
8810 + case USB_REQ_CLEAR_FEATURE: {
8811 + if (crq->bRequestType == USB_RECIP_DEVICE) {
8812 + if (feature_is_dev_remote_wakeup(crq)) {
8813 + /* TODO: Handle REMOTE_WAKEUP */
8814 + } else {
8815 + /* Can't CLEAR_FEATURE TEST_MODE */
8816 + goto stall;
8817 + }
8818 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
8819 + struct usba_ep *target;
8820 +
8821 + if (!feature_is_ep_halt(crq)
8822 + || crq->wLength != __constant_cpu_to_le16(0))
8823 + goto stall;
8824 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
8825 + if (!target)
8826 + goto stall;
8827 +
8828 + usba_ep_writel(target, CLR_STA,
8829 + (USBA_BIT(FORCE_STALL)
8830 + | USBA_BIT(TOGGLE_SEQ)));
8831 + } else {
8832 + goto delegate;
8833 + }
8834 +
8835 + send_status(udc, ep);
8836 + break;
8837 + }
8838 +
8839 + case USB_REQ_SET_FEATURE: {
8840 + if (crq->bRequestType == USB_RECIP_DEVICE) {
8841 + if (feature_is_dev_test_mode(crq)) {
8842 + send_status(udc, ep);
8843 + ep->state = STATUS_STAGE_TEST;
8844 + udc->test_mode = le16_to_cpu(crq->wIndex);
8845 + return 0;
8846 + } else if (feature_is_dev_remote_wakeup(crq)) {
8847 + /* TODO: Handle REMOTE_WAKEUP */
8848 + } else {
8849 + goto stall;
8850 + }
8851 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
8852 + struct usba_ep *target;
8853 +
8854 + if (!feature_is_ep_halt(crq)
8855 + || crq->wLength != __constant_cpu_to_le16(0))
8856 + goto stall;
8857 +
8858 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
8859 + if (!target)
8860 + goto stall;
8861 +
8862 + usba_ep_writel(target, SET_STA, USBA_BIT(FORCE_STALL));
8863 + } else
8864 + goto delegate;
8865 +
8866 + send_status(udc, ep);
8867 + break;
8868 + }
8869 +
8870 + case USB_REQ_SET_ADDRESS:
8871 + if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
8872 + goto delegate;
8873 +
8874 + set_address(udc, le16_to_cpu(crq->wValue));
8875 + send_status(udc, ep);
8876 + ep->state = STATUS_STAGE_ADDR;
8877 + break;
8878 +
8879 + default:
8880 +delegate:
8881 + return udc->driver->setup(&udc->gadget, crq);
8882 + }
8883 +
8884 + return 0;
8885 +
8886 +stall:
8887 + printk(KERN_ERR
8888 + "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
8889 + "halting endpoint...\n",
8890 + ep_name(ep), crq->bRequestType, crq->bRequest,
8891 + le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
8892 + le16_to_cpu(crq->wLength));
8893 + set_protocol_stall(udc, ep);
8894 + return -1;
8895 +}
8896 +
8897 +static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
8898 +{
8899 + struct usba_request *req;
8900 + u32 epstatus;
8901 + u32 epctrl;
8902 +
8903 +restart:
8904 + epstatus = usba_ep_readl(ep, STA);
8905 + epctrl = usba_ep_readl(ep, CTL);
8906 +
8907 + DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
8908 + ep_name(ep), ep->state, epstatus, epctrl);
8909 +
8910 + req = NULL;
8911 + if (!list_empty(&ep->queue))
8912 + req = list_entry(ep->queue.next,
8913 + struct usba_request, queue);
8914 +
8915 + if ((epctrl & USBA_BIT(TX_PK_RDY))
8916 + && !(epstatus & USBA_BIT(TX_PK_RDY))) {
8917 + if (req->submitted)
8918 + next_fifo_transaction(ep, req);
8919 + else
8920 + submit_request(ep, req);
8921 +
8922 + if (req->last_transaction) {
8923 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
8924 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(TX_COMPLETE));
8925 + }
8926 + goto restart;
8927 + }
8928 + if ((epstatus & epctrl) & USBA_BIT(TX_COMPLETE)) {
8929 + usba_ep_writel(ep, CLR_STA, USBA_BIT(TX_COMPLETE));
8930 +
8931 + switch (ep->state) {
8932 + case DATA_STAGE_IN:
8933 + usba_ep_writel(ep, CTL_ENB, USBA_BIT(RX_BK_RDY));
8934 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
8935 + ep->state = STATUS_STAGE_OUT;
8936 + break;
8937 + case STATUS_STAGE_ADDR:
8938 + /* Activate our new address */
8939 + usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
8940 + | USBA_BIT(FADDR_EN)));
8941 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
8942 + ep->state = WAIT_FOR_SETUP;
8943 + break;
8944 + case STATUS_STAGE_IN:
8945 + if (req) {
8946 + list_del_init(&req->queue);
8947 + request_complete(ep, req, 0);
8948 + submit_next_request(ep);
8949 + }
8950 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
8951 + ep->state = WAIT_FOR_SETUP;
8952 + break;
8953 + case STATUS_STAGE_TEST:
8954 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_COMPLETE));
8955 + ep->state = WAIT_FOR_SETUP;
8956 + if (do_test_mode(udc))
8957 + set_protocol_stall(udc, ep);
8958 + break;
8959 + default:
8960 + printk(KERN_ERR
8961 + "udc: %s: TXCOMP: Invalid endpoint state %d, "
8962 + "halting endpoint...\n",
8963 + ep_name(ep), ep->state);
8964 + set_protocol_stall(udc, ep);
8965 + break;
8966 + }
8967 +
8968 + goto restart;
8969 + }
8970 + if ((epstatus & epctrl) & USBA_BIT(RX_BK_RDY)) {
8971 + switch (ep->state) {
8972 + case STATUS_STAGE_OUT:
8973 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
8974 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
8975 +
8976 + if (req) {
8977 + list_del_init(&req->queue);
8978 + request_complete(ep, req, 0);
8979 + }
8980 + ep->state = WAIT_FOR_SETUP;
8981 + break;
8982 +
8983 + case DATA_STAGE_OUT:
8984 + receive_data(ep);
8985 + break;
8986 +
8987 + default:
8988 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
8989 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(RX_BK_RDY));
8990 + printk(KERN_ERR
8991 + "udc: %s: RXRDY: Invalid endpoint state %d, "
8992 + "halting endpoint...\n",
8993 + ep_name(ep), ep->state);
8994 + set_protocol_stall(udc, ep);
8995 + break;
8996 + }
8997 +
8998 + goto restart;
8999 + }
9000 + if (epstatus & USBA_BIT(RX_SETUP)) {
9001 + union {
9002 + struct usb_ctrlrequest crq;
9003 + unsigned long data[2];
9004 + } crq;
9005 + unsigned int pkt_len;
9006 + int ret;
9007 +
9008 + if (ep->state != WAIT_FOR_SETUP) {
9009 + /*
9010 + * Didn't expect a SETUP packet at this
9011 + * point. Clean up any pending requests (which
9012 + * may be successful).
9013 + */
9014 + int status = -EPROTO;
9015 +
9016 + /*
9017 + * RXRDY and TXCOMP are dropped when SETUP
9018 + * packets arrive. Just pretend we received
9019 + * the status packet.
9020 + */
9021 + if (ep->state == STATUS_STAGE_OUT
9022 + || ep->state == STATUS_STAGE_IN) {
9023 + usba_ep_writel(ep, CTL_DIS,
9024 + USBA_BIT(RX_BK_RDY));
9025 + status = 0;
9026 + }
9027 +
9028 + if (req) {
9029 + list_del_init(&req->queue);
9030 + request_complete(ep, req, status);
9031 + }
9032 + }
9033 +
9034 + pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
9035 + DBG(DBG_HW, "Packet length: %u\n", pkt_len);
9036 + if (pkt_len != sizeof(crq)) {
9037 + printk(KERN_WARNING
9038 + "udc: Invalid packet length %u (expected %lu)\n",
9039 + pkt_len, sizeof(crq));
9040 + set_protocol_stall(udc, ep);
9041 + return;
9042 + }
9043 +
9044 + DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
9045 + copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
9046 +
9047 + /* Free up one bank in the FIFO so that we can
9048 + * generate or receive a reply right away. */
9049 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_SETUP));
9050 +
9051 + /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
9052 + ep->state, crq.crq.bRequestType,
9053 + crq.crq.bRequest); */
9054 +
9055 + if (crq.crq.bRequestType & USB_DIR_IN) {
9056 + /*
9057 + * The USB 2.0 spec states that "if wLength is
9058 + * zero, there is no data transfer phase."
9059 + * However, testusb #14 seems to actually
9060 + * expect a data phase even if wLength = 0...
9061 + */
9062 + ep->state = DATA_STAGE_IN;
9063 + } else {
9064 + if (crq.crq.wLength != __constant_cpu_to_le16(0))
9065 + ep->state = DATA_STAGE_OUT;
9066 + else
9067 + ep->state = STATUS_STAGE_IN;
9068 + }
9069 +
9070 + ret = -1;
9071 + if (ep->index == 0)
9072 + ret = handle_ep0_setup(udc, ep, &crq.crq);
9073 + else
9074 + ret = udc->driver->setup(&udc->gadget, &crq.crq);
9075 +
9076 + DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
9077 + crq.crq.bRequestType, crq.crq.bRequest,
9078 + le16_to_cpu(crq.crq.wLength), ep->state, ret);
9079 +
9080 + if (ret < 0) {
9081 + /* Let the host know that we failed */
9082 + set_protocol_stall(udc, ep);
9083 + }
9084 + }
9085 +}
9086 +
9087 +static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
9088 +{
9089 + struct usba_request *req;
9090 + u32 epstatus;
9091 + u32 epctrl;
9092 +
9093 + epstatus = usba_ep_readl(ep, STA);
9094 + epctrl = usba_ep_readl(ep, CTL);
9095 +
9096 + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n",
9097 + ep_name(ep), epstatus);
9098 +
9099 + while ((epctrl & USBA_BIT(TX_PK_RDY))
9100 + && !(epstatus & USBA_BIT(TX_PK_RDY))) {
9101 + DBG(DBG_BUS, "%s: TX PK ready\n", ep_name(ep));
9102 +
9103 + if (list_empty(&ep->queue)) {
9104 + dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
9105 + usba_ep_writel(ep, CTL_DIS, USBA_BIT(TX_PK_RDY));
9106 + return;
9107 + }
9108 +
9109 + req = list_entry(ep->queue.next, struct usba_request, queue);
9110 +
9111 + if (req->using_dma) {
9112 + /* Send a zero-length packet */
9113 + usba_ep_writel(ep, SET_STA,
9114 + USBA_BIT(TX_PK_RDY));
9115 + usba_ep_writel(ep, CTL_DIS,
9116 + USBA_BIT(TX_PK_RDY));
9117 + list_del_init(&req->queue);
9118 + submit_next_request(ep);
9119 + request_complete(ep, req, 0);
9120 + } else {
9121 + if (req->submitted)
9122 + next_fifo_transaction(ep, req);
9123 + else
9124 + submit_request(ep, req);
9125 +
9126 + if (req->last_transaction) {
9127 + list_del_init(&req->queue);
9128 + submit_next_request(ep);
9129 + request_complete(ep, req, 0);
9130 + }
9131 + }
9132 +
9133 + epstatus = usba_ep_readl(ep, STA);
9134 + epctrl = usba_ep_readl(ep, CTL);
9135 + }
9136 + if ((epstatus & epctrl) & USBA_BIT(RX_BK_RDY)) {
9137 + DBG(DBG_BUS, "%s: RX data ready\n", ep_name(ep));
9138 + receive_data(ep);
9139 + usba_ep_writel(ep, CLR_STA, USBA_BIT(RX_BK_RDY));
9140 + }
9141 +}
9142 +
9143 +static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
9144 +{
9145 + struct usba_request *req;
9146 + u32 status, control, pending;
9147 +
9148 + status = usba_dma_readl(ep, STATUS);
9149 + control = usba_dma_readl(ep, CONTROL);
9150 +#ifdef CONFIG_DEBUG_FS
9151 + ep->last_dma_status = status;
9152 +#endif
9153 + pending = status & control;
9154 + DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n",
9155 + status, control);
9156 +
9157 + if (status & USBA_BIT(DMA_CH_EN)) {
9158 + dev_err(&udc->pdev->dev,
9159 + "DMA_CH_EN is set after transfer is finished!\n");
9160 + dev_err(&udc->pdev->dev,
9161 + "status=%#08x, pending=%#08x, control=%#08x\n",
9162 + status, pending, control);
9163 +
9164 + /*
9165 + * try to pretend nothing happened. We might have to
9166 + * do something here...
9167 + */
9168 + }
9169 +
9170 + if (list_empty(&ep->queue))
9171 + /* Might happen if a reset comes along at the right moment */
9172 + return;
9173 +
9174 + if (pending & (USBA_BIT(DMA_END_TR_ST) | USBA_BIT(DMA_END_BUF_ST))) {
9175 + req = list_entry(ep->queue.next, struct usba_request, queue);
9176 + usba_update_req(ep, req, status);
9177 +
9178 + list_del_init(&req->queue);
9179 + submit_next_request(ep);
9180 + request_complete(ep, req, 0);
9181 + }
9182 +}
9183 +
9184 +static irqreturn_t usba_udc_irq(int irq, void *devid)
9185 +{
9186 + struct usba_udc *udc = devid;
9187 + u32 status;
9188 + u32 dma_status;
9189 + u32 ep_status;
9190 +
9191 + spin_lock(&udc->lock);
9192 +
9193 + status = usba_readl(udc, INT_STA);
9194 + DBG(DBG_INT, "irq, status=%#08x\n", status);
9195 +
9196 + if (status & USBA_BIT(DET_SUSPEND)) {
9197 + usba_writel(udc, INT_CLR, USBA_BIT(DET_SUSPEND));
9198 + DBG(DBG_BUS, "Suspend detected\n");
9199 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
9200 + && udc->driver && udc->driver->suspend)
9201 + udc->driver->suspend(&udc->gadget);
9202 + }
9203 +
9204 + if (status & USBA_BIT(WAKE_UP)) {
9205 + usba_writel(udc, INT_CLR, USBA_BIT(WAKE_UP));
9206 + DBG(DBG_BUS, "Wake Up CPU detected\n");
9207 + }
9208 +
9209 + if (status & USBA_BIT(END_OF_RESUME)) {
9210 + usba_writel(udc, INT_CLR, USBA_BIT(END_OF_RESUME));
9211 + DBG(DBG_BUS, "Resume detected\n");
9212 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
9213 + && udc->driver && udc->driver->resume)
9214 + udc->driver->resume(&udc->gadget);
9215 + }
9216 +
9217 + dma_status = USBA_BFEXT(DMA_INT, status);
9218 + if (dma_status) {
9219 + int i;
9220 +
9221 + for (i = 1; i < USBA_NR_ENDPOINTS; i++)
9222 + if (dma_status & (1 << i))
9223 + usba_dma_irq(udc, &usba_ep[i]);
9224 + }
9225 +
9226 + ep_status = USBA_BFEXT(EPT_INT, status);
9227 + if (ep_status) {
9228 + int i;
9229 +
9230 + for (i = 0; i < USBA_NR_ENDPOINTS; i++)
9231 + if (ep_status & (1 << i)) {
9232 + if (ep_is_control(&usba_ep[i]))
9233 + usba_control_irq(udc, &usba_ep[i]);
9234 + else
9235 + usba_ep_irq(udc, &usba_ep[i]);
9236 + }
9237 + }
9238 +
9239 + if (status & USBA_BIT(END_OF_RESET)) {
9240 + struct usba_ep *ep0;
9241 +
9242 + usba_writel(udc, INT_CLR, USBA_BIT(END_OF_RESET));
9243 + reset_all_endpoints(udc);
9244 +
9245 + if (status & USBA_BIT(HIGH_SPEED)) {
9246 + DBG(DBG_BUS, "High-speed bus reset detected\n");
9247 + udc->gadget.speed = USB_SPEED_HIGH;
9248 + } else {
9249 + DBG(DBG_BUS, "Full-speed bus reset detected\n");
9250 + udc->gadget.speed = USB_SPEED_FULL;
9251 + }
9252 +
9253 + ep0 = &usba_ep[0];
9254 + ep0->desc = &usba_ep0_desc;
9255 + ep0->state = WAIT_FOR_SETUP;
9256 + usba_ep_writel(ep0, CFG,
9257 + (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
9258 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
9259 + | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
9260 + usba_ep_writel(ep0, CTL_ENB,
9261 + USBA_BIT(EPT_ENABLE) | USBA_BIT(RX_SETUP));
9262 + usba_writel(udc, INT_ENB, (usba_readl(udc, INT_ENB)
9263 + | USBA_BF(EPT_INT, 1)
9264 + | USBA_BIT(DET_SUSPEND)
9265 + | USBA_BIT(END_OF_RESUME)));
9266 +
9267 + if (!(usba_ep_readl(ep0, CFG) & USBA_BIT(EPT_MAPPED)))
9268 + dev_warn(&udc->pdev->dev,
9269 + "WARNING: EP0 configuration is invalid!\n");
9270 + }
9271 +
9272 + spin_unlock(&udc->lock);
9273 +
9274 + return IRQ_HANDLED;
9275 +}
9276 +
9277 +static irqreturn_t usba_vbus_irq(int irq, void *devid)
9278 +{
9279 + struct usba_udc *udc = devid;
9280 + int vbus;
9281 +
9282 + /* debounce */
9283 + udelay(10);
9284 +
9285 + spin_lock(&udc->lock);
9286 + vbus = gpio_get_value(udc->vbus_pin);
9287 + if (vbus != udc->vbus_prev) {
9288 + if (vbus) {
9289 + usba_writel(udc, CTRL, USBA_BIT(EN_USBA));
9290 + usba_writel(udc, INT_ENB, USBA_BIT(END_OF_RESET));
9291 + } else {
9292 + udc->gadget.speed = USB_SPEED_UNKNOWN;
9293 + reset_all_endpoints(udc);
9294 + usba_writel(udc, CTRL, 0);
9295 + if (udc->driver)
9296 + udc->driver->disconnect(&udc->gadget);
9297 + }
9298 + udc->vbus_prev = vbus;
9299 + }
9300 + spin_unlock(&udc->lock);
9301 +
9302 + return IRQ_HANDLED;
9303 +}
9304 +
9305 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
9306 +{
9307 + struct usba_udc *udc = &the_udc;
9308 + unsigned long flags;
9309 + int ret;
9310 +
9311 + if (!udc->pdev)
9312 + return -ENODEV;
9313 +
9314 + spin_lock_irqsave(&udc->lock, flags);
9315 + if (udc->driver) {
9316 + spin_unlock_irqrestore(&udc->lock, flags);
9317 + return -EBUSY;
9318 + }
9319 +
9320 + udc->driver = driver;
9321 + udc->gadget.dev.driver = &driver->driver;
9322 + spin_unlock_irqrestore(&udc->lock, flags);
9323 +
9324 + clk_enable(udc->pclk);
9325 + clk_enable(udc->hclk);
9326 +
9327 + ret = driver->bind(&udc->gadget);
9328 + if (ret) {
9329 + DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
9330 + driver->driver.name, ret);
9331 + goto err_driver_bind;
9332 + }
9333 +
9334 + DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
9335 +
9336 + udc->vbus_prev = 0;
9337 + if (udc->vbus_pin != -1) {
9338 + ret = request_irq(gpio_to_irq(udc->vbus_pin),
9339 + usba_vbus_irq, 0, "atmel_usba_udc", udc);
9340 + if (ret) {
9341 + gpio_free(udc->vbus_pin);
9342 + udc->vbus_pin = -1;
9343 + dev_warn(&udc->pdev->dev,
9344 + "failed to request vbus irq; "
9345 + "assuming always on\n");
9346 + }
9347 + }
9348 +
9349 + /* If Vbus is present, enable the controller and wait for reset */
9350 + spin_lock_irqsave(&udc->lock, flags);
9351 + if (vbus_is_present(udc) && udc->vbus_prev == 0) {
9352 + usba_writel(udc, CTRL, USBA_BIT(EN_USBA));
9353 + usba_writel(udc, INT_ENB, USBA_BIT(END_OF_RESET));
9354 + }
9355 + spin_unlock_irqrestore(&udc->lock, flags);
9356 +
9357 + return 0;
9358 +
9359 +err_driver_bind:
9360 + udc->driver = NULL;
9361 + udc->gadget.dev.driver = NULL;
9362 + return ret;
9363 +}
9364 +EXPORT_SYMBOL(usb_gadget_register_driver);
9365 +
9366 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
9367 +{
9368 + struct usba_udc *udc = &the_udc;
9369 + unsigned long flags;
9370 +
9371 + if (!udc->pdev)
9372 + return -ENODEV;
9373 + if (driver != udc->driver)
9374 + return -EINVAL;
9375 +
9376 + if (udc->vbus_pin != -1)
9377 + free_irq(gpio_to_irq(udc->vbus_pin), udc);
9378 +
9379 + spin_lock_irqsave(&udc->lock, flags);
9380 + udc->gadget.speed = USB_SPEED_UNKNOWN;
9381 + reset_all_endpoints(udc);
9382 + spin_unlock_irqrestore(&udc->lock, flags);
9383 +
9384 + /* This will also disable the DP pullup */
9385 + usba_writel(udc, CTRL, 0);
9386 +
9387 + driver->unbind(&udc->gadget);
9388 + udc->gadget.dev.driver = NULL;
9389 + udc->driver = NULL;
9390 +
9391 + clk_disable(udc->hclk);
9392 + clk_disable(udc->pclk);
9393 +
9394 + DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
9395 +
9396 + return 0;
9397 +}
9398 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
9399 +
9400 +static int __devinit usba_udc_probe(struct platform_device *pdev)
9401 +{
9402 + struct usba_platform_data *pdata = pdev->dev.platform_data;
9403 + struct resource *regs, *fifo;
9404 + struct clk *pclk, *hclk;
9405 + struct usba_udc *udc = &the_udc;
9406 + int irq, ret, i;
9407 +
9408 + regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
9409 + fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
9410 + if (!regs || !fifo)
9411 + return -ENXIO;
9412 +
9413 + irq = platform_get_irq(pdev, 0);
9414 + if (irq < 0)
9415 + return irq;
9416 +
9417 + pclk = clk_get(&pdev->dev, "pclk");
9418 + if (IS_ERR(pclk))
9419 + return PTR_ERR(pclk);
9420 + hclk = clk_get(&pdev->dev, "hclk");
9421 + if (IS_ERR(hclk)) {
9422 + ret = PTR_ERR(hclk);
9423 + goto err_get_hclk;
9424 + }
9425 +
9426 + udc->pdev = pdev;
9427 + udc->pclk = pclk;
9428 + udc->hclk = hclk;
9429 + udc->vbus_pin = -1;
9430 +
9431 + ret = -ENOMEM;
9432 + udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
9433 + if (!udc->regs) {
9434 + dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
9435 + goto err_map_regs;
9436 + }
9437 + dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
9438 + (unsigned long)regs->start, udc->regs);
9439 + udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
9440 + if (!udc->fifo) {
9441 + dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
9442 + goto err_map_fifo;
9443 + }
9444 + dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
9445 + (unsigned long)fifo->start, udc->fifo);
9446 +
9447 + device_initialize(&udc->gadget.dev);
9448 + udc->gadget.dev.parent = &pdev->dev;
9449 + udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
9450 +
9451 + platform_set_drvdata(pdev, udc);
9452 +
9453 + /* Make sure we start from a clean slate */
9454 + clk_enable(pclk);
9455 + usba_writel(udc, CTRL, 0);
9456 + clk_disable(pclk);
9457 +
9458 + INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
9459 + usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
9460 + usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
9461 + usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
9462 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
9463 + struct usba_ep *ep = &usba_ep[i];
9464 +
9465 + ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
9466 + ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
9467 + ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
9468 +
9469 + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
9470 + }
9471 +
9472 + ret = request_irq(irq, usba_udc_irq, IRQF_SAMPLE_RANDOM,
9473 + "atmel_usba_udc", udc);
9474 + if (ret) {
9475 + dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
9476 + irq, ret);
9477 + goto err_request_irq;
9478 + }
9479 + udc->irq = irq;
9480 +
9481 + ret = device_add(&udc->gadget.dev);
9482 + if (ret) {
9483 + dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
9484 + goto err_device_add;
9485 + }
9486 +
9487 + if (pdata && pdata->vbus_pin != GPIO_PIN_NONE)
9488 + if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc"))
9489 + udc->vbus_pin = pdata->vbus_pin;
9490 +
9491 + usba_init_debugfs(udc);
9492 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
9493 + usba_ep_init_debugfs(udc, &usba_ep[i]);
9494 +
9495 + return 0;
9496 +
9497 +err_device_add:
9498 + free_irq(irq, udc);
9499 +err_request_irq:
9500 + iounmap(udc->fifo);
9501 +err_map_fifo:
9502 + iounmap(udc->regs);
9503 +err_map_regs:
9504 + clk_put(hclk);
9505 +err_get_hclk:
9506 + clk_put(pclk);
9507 +
9508 + platform_set_drvdata(pdev, NULL);
9509 +
9510 + return ret;
9511 +}
9512 +
9513 +static int __devexit usba_udc_remove(struct platform_device *pdev)
9514 +{
9515 + struct usba_udc *udc;
9516 + int i;
9517 +
9518 + udc = platform_get_drvdata(pdev);
9519 +
9520 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
9521 + usba_ep_cleanup_debugfs(&usba_ep[i]);
9522 + usba_cleanup_debugfs(udc);
9523 +
9524 + if (udc->vbus_pin != -1)
9525 + gpio_free(udc->vbus_pin);
9526 +
9527 + free_irq(udc->irq, udc);
9528 + iounmap(udc->fifo);
9529 + iounmap(udc->regs);
9530 + clk_put(udc->hclk);
9531 + clk_put(udc->pclk);
9532 +
9533 + device_unregister(&udc->gadget.dev);
9534 +
9535 + return 0;
9536 +}
9537 +
9538 +static struct platform_driver udc_driver = {
9539 + .probe = usba_udc_probe,
9540 + .remove = __devexit_p(usba_udc_remove),
9541 + .driver = {
9542 + .name = "atmel_usba_udc",
9543 + },
9544 +};
9545 +
9546 +static int __init udc_init(void)
9547 +{
9548 + return platform_driver_register(&udc_driver);
9549 +}
9550 +module_init(udc_init);
9551 +
9552 +static void __exit udc_exit(void)
9553 +{
9554 + platform_driver_unregister(&udc_driver);
9555 +}
9556 +module_exit(udc_exit);
9557 +
9558 +MODULE_DESCRIPTION("Atmel USBA UDC driver");
9559 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
9560 +MODULE_LICENSE("GPL");
9561 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.h linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.h
9562 --- linux-2.6.22.1/drivers/usb/gadget/atmel_usba_udc.h 1970-01-01 01:00:00.000000000 +0100
9563 +++ linux-avr32.git/drivers/usb/gadget/atmel_usba_udc.h 2007-07-12 14:00:19.000000000 +0200
9564 @@ -0,0 +1,402 @@
9565 +/*
9566 + * Driver for the Atmel USBA high speed USB device controller
9567 + *
9568 + * Copyright (C) 2005-2007 Atmel Corporation
9569 + *
9570 + * This program is free software; you can redistribute it and/or modify
9571 + * it under the terms of the GNU General Public License version 2 as
9572 + * published by the Free Software Foundation.
9573 + */
9574 +#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
9575 +#define __LINUX_USB_GADGET_USBA_UDC_H__
9576 +
9577 +/* USB register offsets */
9578 +#define USBA_CTRL 0x0000
9579 +#define USBA_FNUM 0x0004
9580 +#define USBA_INT_ENB 0x0010
9581 +#define USBA_INT_STA 0x0014
9582 +#define USBA_INT_CLR 0x0018
9583 +#define USBA_EPT_RST 0x001c
9584 +#define USBA_TST_SOF_CNT 0x00d0
9585 +#define USBA_TST_CNT_A 0x00d4
9586 +#define USBA_TST_CNT_B 0x00d8
9587 +#define USBA_TST_MODE_REG 0x00dc
9588 +#define USBA_TST 0x00e0
9589 +
9590 +/* USB endpoint register offsets */
9591 +#define USBA_EPT_CFG 0x0000
9592 +#define USBA_EPT_CTL_ENB 0x0004
9593 +#define USBA_EPT_CTL_DIS 0x0008
9594 +#define USBA_EPT_CTL 0x000c
9595 +#define USBA_EPT_SET_STA 0x0014
9596 +#define USBA_EPT_CLR_STA 0x0018
9597 +#define USBA_EPT_STA 0x001c
9598 +
9599 +/* USB DMA register offsets */
9600 +#define USBA_DMA_NXT_DSC 0x0000
9601 +#define USBA_DMA_ADDRESS 0x0004
9602 +#define USBA_DMA_CONTROL 0x0008
9603 +#define USBA_DMA_STATUS 0x000c
9604 +
9605 +/* Bitfields in CTRL */
9606 +#define USBA_DEV_ADDR_OFFSET 0
9607 +#define USBA_DEV_ADDR_SIZE 7
9608 +#define USBA_FADDR_EN_OFFSET 7
9609 +#define USBA_FADDR_EN_SIZE 1
9610 +#define USBA_EN_USBA_OFFSET 8
9611 +#define USBA_EN_USBA_SIZE 1
9612 +#define USBA_DETACH_OFFSET 9
9613 +#define USBA_DETACH_SIZE 1
9614 +#define USBA_REMOTE_WAKE_UP_OFFSET 10
9615 +#define USBA_REMOTE_WAKE_UP_SIZE 1
9616 +
9617 +/* Bitfields in FNUM */
9618 +#define USBA_MICRO_FRAME_NUM_OFFSET 0
9619 +#define USBA_MICRO_FRAME_NUM_SIZE 3
9620 +#define USBA_FRAME_NUMBER_OFFSET 3
9621 +#define USBA_FRAME_NUMBER_SIZE 11
9622 +#define USBA_FRAME_NUM_ERROR_OFFSET 31
9623 +#define USBA_FRAME_NUM_ERROR_SIZE 1
9624 +
9625 +/* Bitfields in INT_ENB/INT_STA/INT_CLR */
9626 +#define USBA_HIGH_SPEED_OFFSET 0
9627 +#define USBA_HIGH_SPEED_SIZE 1
9628 +#define USBA_DET_SUSPEND_OFFSET 1
9629 +#define USBA_DET_SUSPEND_SIZE 1
9630 +#define USBA_MICRO_SOF_OFFSET 2
9631 +#define USBA_MICRO_SOF_SIZE 1
9632 +#define USBA_SOF_OFFSET 3
9633 +#define USBA_SOF_SIZE 1
9634 +#define USBA_END_OF_RESET_OFFSET 4
9635 +#define USBA_END_OF_RESET_SIZE 1
9636 +#define USBA_WAKE_UP_OFFSET 5
9637 +#define USBA_WAKE_UP_SIZE 1
9638 +#define USBA_END_OF_RESUME_OFFSET 6
9639 +#define USBA_END_OF_RESUME_SIZE 1
9640 +#define USBA_UPSTREAM_RESUME_OFFSET 7
9641 +#define USBA_UPSTREAM_RESUME_SIZE 1
9642 +#define USBA_EPT_INT_OFFSET 8
9643 +#define USBA_EPT_INT_SIZE 16
9644 +#define USBA_DMA_INT_OFFSET 24
9645 +#define USBA_DMA_INT_SIZE 8
9646 +
9647 +/* Bitfields in EPT_RST */
9648 +#define USBA_RST_OFFSET 0
9649 +#define USBA_RST_SIZE 16
9650 +
9651 +/* Bitfields in TST_SOF_CNT */
9652 +#define USBA_SOF_CNT_MAX_OFFSET 0
9653 +#define USBA_SOF_CNT_MAX_SIZE 7
9654 +#define USBA_SOF_CNT_LOAD_OFFSET 7
9655 +#define USBA_SOF_CNT_LOAD_SIZE 1
9656 +
9657 +/* Bitfields in TST_CNT_A */
9658 +#define USBA_CNT_A_MAX_OFFSET 0
9659 +#define USBA_CNT_A_MAX_SIZE 7
9660 +#define USBA_CNT_A_LOAD_OFFSET 7
9661 +#define USBA_CNT_A_LOAD_SIZE 1
9662 +
9663 +/* Bitfields in TST_CNT_B */
9664 +#define USBA_CNT_B_MAX_OFFSET 0
9665 +#define USBA_CNT_B_MAX_SIZE 7
9666 +#define USBA_CNT_B_LOAD_OFFSET 7
9667 +#define USBA_CNT_B_LOAD_SIZE 1
9668 +
9669 +/* Bitfields in TST_MODE_REG */
9670 +#define USBA_TST_MODE_OFFSET 0
9671 +#define USBA_TST_MODE_SIZE 6
9672 +
9673 +/* Bitfields in USBA_TST */
9674 +#define USBA_SPEED_CFG_OFFSET 0
9675 +#define USBA_SPEED_CFG_SIZE 2
9676 +#define USBA_TST_J_MODE_OFFSET 2
9677 +#define USBA_TST_J_MODE_SIZE 1
9678 +#define USBA_TST_K_MODE_OFFSET 3
9679 +#define USBA_TST_K_MODE_SIZE 1
9680 +#define USBA_TST_PKT_MODE_OFFSET 4
9681 +#define USBA_TST_PKT_MODE_SIZE 1
9682 +#define USBA_OPMODE2_OFFSET 5
9683 +#define USBA_OPMODE2_SIZE 1
9684 +
9685 +/* Bitfields in EPT_CFG */
9686 +#define USBA_EPT_SIZE_OFFSET 0
9687 +#define USBA_EPT_SIZE_SIZE 3
9688 +#define USBA_EPT_DIR_OFFSET 3
9689 +#define USBA_EPT_DIR_SIZE 1
9690 +#define USBA_EPT_TYPE_OFFSET 4
9691 +#define USBA_EPT_TYPE_SIZE 2
9692 +#define USBA_BK_NUMBER_OFFSET 6
9693 +#define USBA_BK_NUMBER_SIZE 2
9694 +#define USBA_NB_TRANS_OFFSET 8
9695 +#define USBA_NB_TRANS_SIZE 2
9696 +#define USBA_EPT_MAPPED_OFFSET 31
9697 +#define USBA_EPT_MAPPED_SIZE 1
9698 +
9699 +/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
9700 +#define USBA_EPT_ENABLE_OFFSET 0
9701 +#define USBA_EPT_ENABLE_SIZE 1
9702 +#define USBA_AUTO_VALID_OFFSET 1
9703 +#define USBA_AUTO_VALID_SIZE 1
9704 +#define USBA_INTDIS_DMA_OFFSET 3
9705 +#define USBA_INTDIS_DMA_SIZE 1
9706 +#define USBA_NYET_DIS_OFFSET 4
9707 +#define USBA_NYET_DIS_SIZE 1
9708 +#define USBA_DATAX_RX_OFFSET 6
9709 +#define USBA_DATAX_RX_SIZE 1
9710 +#define USBA_MDATA_RX_OFFSET 7
9711 +#define USBA_MDATA_RX_SIZE 1
9712 +/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
9713 +#define USBA_BUSY_BANK_IE_OFFSET 18
9714 +#define USBA_BUSY_BANK_IE_SIZE 1
9715 +
9716 +/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
9717 +#define USBA_FORCE_STALL_OFFSET 5
9718 +#define USBA_FORCE_STALL_SIZE 1
9719 +#define USBA_TOGGLE_SEQ_OFFSET 6
9720 +#define USBA_TOGGLE_SEQ_SIZE 2
9721 +#define USBA_ERR_OVFLW_OFFSET 8
9722 +#define USBA_ERR_OVFLW_SIZE 1
9723 +#define USBA_RX_BK_RDY_OFFSET 9
9724 +#define USBA_RX_BK_RDY_SIZE 1
9725 +#define USBA_KILL_BANK_OFFSET 9
9726 +#define USBA_KILL_BANK_SIZE 1
9727 +#define USBA_TX_COMPLETE_OFFSET 10
9728 +#define USBA_TX_COMPLETE_SIZE 1
9729 +#define USBA_TX_PK_RDY_OFFSET 11
9730 +#define USBA_TX_PK_RDY_SIZE 1
9731 +#define USBA_ISO_ERR_TRANS_OFFSET 11
9732 +#define USBA_ISO_ERR_TRANS_SIZE 1
9733 +#define USBA_RX_SETUP_OFFSET 12
9734 +#define USBA_RX_SETUP_SIZE 1
9735 +#define USBA_ISO_ERR_FLOW_OFFSET 12
9736 +#define USBA_ISO_ERR_FLOW_SIZE 1
9737 +#define USBA_STALL_SENT_OFFSET 13
9738 +#define USBA_STALL_SENT_SIZE 1
9739 +#define USBA_ISO_ERR_CRC_OFFSET 13
9740 +#define USBA_ISO_ERR_CRC_SIZE 1
9741 +#define USBA_ISO_ERR_NBTRANS_OFFSET 13
9742 +#define USBA_ISO_ERR_NBTRANS_SIZE 1
9743 +#define USBA_NAK_IN_OFFSET 14
9744 +#define USBA_NAK_IN_SIZE 1
9745 +#define USBA_ISO_ERR_FLUSH_OFFSET 14
9746 +#define USBA_ISO_ERR_FLUSH_SIZE 1
9747 +#define USBA_NAK_OUT_OFFSET 15
9748 +#define USBA_NAK_OUT_SIZE 1
9749 +#define USBA_CURRENT_BANK_OFFSET 16
9750 +#define USBA_CURRENT_BANK_SIZE 2
9751 +#define USBA_BUSY_BANKS_OFFSET 18
9752 +#define USBA_BUSY_BANKS_SIZE 2
9753 +#define USBA_BYTE_COUNT_OFFSET 20
9754 +#define USBA_BYTE_COUNT_SIZE 11
9755 +#define USBA_SHORT_PACKET_OFFSET 31
9756 +#define USBA_SHORT_PACKET_SIZE 1
9757 +
9758 +/* Bitfields in DMA_CONTROL */
9759 +#define USBA_DMA_CH_EN_OFFSET 0
9760 +#define USBA_DMA_CH_EN_SIZE 1
9761 +#define USBA_DMA_LINK_OFFSET 1
9762 +#define USBA_DMA_LINK_SIZE 1
9763 +#define USBA_DMA_END_TR_EN_OFFSET 2
9764 +#define USBA_DMA_END_TR_EN_SIZE 1
9765 +#define USBA_DMA_END_BUF_EN_OFFSET 3
9766 +#define USBA_DMA_END_BUF_EN_SIZE 1
9767 +#define USBA_DMA_END_TR_IE_OFFSET 4
9768 +#define USBA_DMA_END_TR_IE_SIZE 1
9769 +#define USBA_DMA_END_BUF_IE_OFFSET 5
9770 +#define USBA_DMA_END_BUF_IE_SIZE 1
9771 +#define USBA_DMA_DESC_LOAD_IE_OFFSET 6
9772 +#define USBA_DMA_DESC_LOAD_IE_SIZE 1
9773 +#define USBA_DMA_BURST_LOCK_OFFSET 7
9774 +#define USBA_DMA_BURST_LOCK_SIZE 1
9775 +#define USBA_DMA_BUF_LEN_OFFSET 16
9776 +#define USBA_DMA_BUF_LEN_SIZE 16
9777 +
9778 +/* Bitfields in DMA_STATUS */
9779 +#define USBA_DMA_CH_ACTIVE_OFFSET 1
9780 +#define USBA_DMA_CH_ACTIVE_SIZE 1
9781 +#define USBA_DMA_END_TR_ST_OFFSET 4
9782 +#define USBA_DMA_END_TR_ST_SIZE 1
9783 +#define USBA_DMA_END_BUF_ST_OFFSET 5
9784 +#define USBA_DMA_END_BUF_ST_SIZE 1
9785 +#define USBA_DMA_DESC_LOAD_ST_OFFSET 6
9786 +#define USBA_DMA_DESC_LOAD_ST_SIZE 1
9787 +
9788 +/* Constants for SPEED_CFG */
9789 +#define USBA_SPEED_CFG_NORMAL 0
9790 +#define USBA_SPEED_CFG_FORCE_HIGH 2
9791 +#define USBA_SPEED_CFG_FORCE_FULL 3
9792 +
9793 +/* Constants for EPT_SIZE */
9794 +#define USBA_EPT_SIZE_8 0
9795 +#define USBA_EPT_SIZE_16 1
9796 +#define USBA_EPT_SIZE_32 2
9797 +#define USBA_EPT_SIZE_64 3
9798 +#define USBA_EPT_SIZE_128 4
9799 +#define USBA_EPT_SIZE_256 5
9800 +#define USBA_EPT_SIZE_512 6
9801 +#define USBA_EPT_SIZE_1024 7
9802 +
9803 +/* Constants for EPT_TYPE */
9804 +#define USBA_EPT_TYPE_CONTROL 0
9805 +#define USBA_EPT_TYPE_ISO 1
9806 +#define USBA_EPT_TYPE_BULK 2
9807 +#define USBA_EPT_TYPE_INT 3
9808 +
9809 +/* Constants for BK_NUMBER */
9810 +#define USBA_BK_NUMBER_ZERO 0
9811 +#define USBA_BK_NUMBER_ONE 1
9812 +#define USBA_BK_NUMBER_DOUBLE 2
9813 +#define USBA_BK_NUMBER_TRIPLE 3
9814 +
9815 +/* Bit manipulation macros */
9816 +#define USBA_BIT(name) \
9817 + (1 << USBA_##name##_OFFSET)
9818 +#define USBA_BF(name, value) \
9819 + (((value) & ((1 << USBA_##name##_SIZE) - 1)) \
9820 + << USBA_##name##_OFFSET)
9821 +#define USBA_BFEXT(name, value) \
9822 + (((value) >> USBA_##name##_OFFSET) \
9823 + & ((1 << USBA_##name##_SIZE) - 1))
9824 +#define USBA_BFINS(name, value, old) \
9825 + (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
9826 + << USBA_##name##_OFFSET)) \
9827 + | USBA_BF(name, value))
9828 +
9829 +/* Register access macros */
9830 +#define usba_readl(udc, reg) \
9831 + __raw_readl((udc)->regs + USBA_##reg)
9832 +#define usba_writel(udc, reg, value) \
9833 + __raw_writel((value), (udc)->regs + USBA_##reg)
9834 +#define usba_ep_readl(ep, reg) \
9835 + __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
9836 +#define usba_ep_writel(ep, reg, value) \
9837 + __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
9838 +#define usba_dma_readl(ep, reg) \
9839 + __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
9840 +#define usba_dma_writel(ep, reg, value) \
9841 + __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
9842 +
9843 +/* Calculate base address for a given endpoint or DMA controller */
9844 +#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
9845 +#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
9846 +#define USBA_FIFO_BASE(x) ((x) << 16)
9847 +
9848 +/* Synth parameters */
9849 +#define USBA_NR_ENDPOINTS 7
9850 +
9851 +#define EP0_FIFO_SIZE 64
9852 +#define EP0_EPT_SIZE USBA_EPT_SIZE_64
9853 +#define EP0_NR_BANKS 1
9854 +#define BULK_FIFO_SIZE 512
9855 +#define BULK_EPT_SIZE USBA_EPT_SIZE_512
9856 +#define BULK_NR_BANKS 2
9857 +#define ISO_FIFO_SIZE 1024
9858 +#define ISO_EPT_SIZE USBA_EPT_SIZE_1024
9859 +#define ISO_NR_BANKS 3
9860 +#define INT_FIFO_SIZE 64
9861 +#define INT_EPT_SIZE USBA_EPT_SIZE_64
9862 +#define INT_NR_BANKS 3
9863 +
9864 +enum usba_ctrl_state {
9865 + WAIT_FOR_SETUP,
9866 + DATA_STAGE_IN,
9867 + DATA_STAGE_OUT,
9868 + STATUS_STAGE_IN,
9869 + STATUS_STAGE_OUT,
9870 + STATUS_STAGE_ADDR,
9871 + STATUS_STAGE_TEST,
9872 +};
9873 +/*
9874 + EP_STATE_IDLE,
9875 + EP_STATE_SETUP,
9876 + EP_STATE_IN_DATA,
9877 + EP_STATE_OUT_DATA,
9878 + EP_STATE_SET_ADDR_STATUS,
9879 + EP_STATE_RX_STATUS,
9880 + EP_STATE_TX_STATUS,
9881 + EP_STATE_HALT,
9882 +*/
9883 +
9884 +struct usba_dma_desc {
9885 + dma_addr_t next;
9886 + dma_addr_t addr;
9887 + u32 ctrl;
9888 +};
9889 +
9890 +struct usba_ep {
9891 + int state;
9892 + void __iomem *ep_regs;
9893 + void __iomem *dma_regs;
9894 + void __iomem *fifo;
9895 + struct usb_ep ep;
9896 + struct usba_udc *udc;
9897 +
9898 + struct list_head queue;
9899 + const struct usb_endpoint_descriptor *desc;
9900 +
9901 + u16 fifo_size;
9902 + u8 nr_banks;
9903 + u8 index;
9904 + unsigned int can_dma:1;
9905 + unsigned int can_isoc:1;
9906 + unsigned int is_isoc:1;
9907 + unsigned int is_in:1;
9908 +
9909 +#ifdef CONFIG_DEBUG_FS
9910 + u32 last_dma_status;
9911 + struct dentry *debugfs_dir;
9912 + struct dentry *debugfs_queue;
9913 + struct dentry *debugfs_dma_status;
9914 + struct dentry *debugfs_state;
9915 +#endif
9916 +};
9917 +
9918 +struct usba_request {
9919 + struct usb_request req;
9920 + struct list_head queue;
9921 +
9922 + u32 ctrl;
9923 +
9924 + unsigned int submitted:1;
9925 + unsigned int last_transaction:1;
9926 + unsigned int using_dma:1;
9927 + unsigned int mapped:1;
9928 +};
9929 +
9930 +struct usba_udc {
9931 + /* Protect hw registers from concurrent modifications */
9932 + spinlock_t lock;
9933 +
9934 + void __iomem *regs;
9935 + void __iomem *fifo;
9936 +
9937 + struct usb_gadget gadget;
9938 + struct usb_gadget_driver *driver;
9939 + struct platform_device *pdev;
9940 + int irq;
9941 + int vbus_pin;
9942 + struct clk *pclk;
9943 + struct clk *hclk;
9944 +
9945 + int test_mode;
9946 + int vbus_prev;
9947 +
9948 +#ifdef CONFIG_DEBUG_FS
9949 + struct dentry *debugfs_root;
9950 + struct dentry *debugfs_regs;
9951 +#endif
9952 +};
9953 +
9954 +#define to_usba_ep(x) container_of((x), struct usba_ep, ep)
9955 +#define to_usba_req(x) container_of((x), struct usba_request, req)
9956 +#define to_usba_udc(x) container_of((x), struct usba_udc, gadget)
9957 +
9958 +#define ep_index(ep) ((ep)->index)
9959 +#define ep_can_dma(ep) ((ep)->can_dma)
9960 +#define ep_is_in(ep) ((ep)->is_in)
9961 +#define ep_is_isochronous(ep) ((ep)->is_isoc)
9962 +#define ep_is_control(ep) (ep_index(ep) == 0)
9963 +#define ep_name(ep) ((ep)->ep.name)
9964 +#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
9965 +
9966 +#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
9967 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/ether.c linux-avr32.git/drivers/usb/gadget/ether.c
9968 --- linux-2.6.22.1/drivers/usb/gadget/ether.c 2007-07-10 20:56:30.000000000 +0200
9969 +++ linux-avr32.git/drivers/usb/gadget/ether.c 2007-07-12 14:00:19.000000000 +0200
9970 @@ -277,7 +277,7 @@
9971 #define DEV_CONFIG_CDC
9972 #endif
9973
9974 -#ifdef CONFIG_USB_GADGET_HUSB2DEV
9975 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
9976 #define DEV_CONFIG_CDC
9977 #endif
9978
9979 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/gadget_chips.h linux-avr32.git/drivers/usb/gadget/gadget_chips.h
9980 --- linux-2.6.22.1/drivers/usb/gadget/gadget_chips.h 2007-07-10 20:56:30.000000000 +0200
9981 +++ linux-avr32.git/drivers/usb/gadget/gadget_chips.h 2007-07-12 14:00:19.000000000 +0200
9982 @@ -75,10 +75,10 @@
9983 #define gadget_is_pxa27x(g) 0
9984 #endif
9985
9986 -#ifdef CONFIG_USB_GADGET_HUSB2DEV
9987 -#define gadget_is_husb2dev(g) !strcmp("husb2_udc", (g)->name)
9988 +#ifdef CONFIG_USB_GADGET_ATMEL_USBA
9989 +#define gadget_is_atmel_usba(g) !strcmp("atmel_usba_udc", (g)->name)
9990 #else
9991 -#define gadget_is_husb2dev(g) 0
9992 +#define gadget_is_atmel_usba(g) 0
9993 #endif
9994
9995 #ifdef CONFIG_USB_GADGET_S3C2410
9996 @@ -181,7 +181,7 @@
9997 return 0x16;
9998 else if (gadget_is_mpc8272(gadget))
9999 return 0x17;
10000 - else if (gadget_is_husb2dev(gadget))
10001 + else if (gadget_is_atmel_usba(gadget))
10002 return 0x18;
10003 else if (gadget_is_fsl_usb2(gadget))
10004 return 0x19;
10005 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/inode.c linux-avr32.git/drivers/usb/gadget/inode.c
10006 --- linux-2.6.22.1/drivers/usb/gadget/inode.c 2007-07-10 20:56:30.000000000 +0200
10007 +++ linux-avr32.git/drivers/usb/gadget/inode.c 2007-07-12 14:00:19.000000000 +0200
10008 @@ -37,7 +37,7 @@
10009 #include <linux/device.h>
10010 #include <linux/moduleparam.h>
10011
10012 -#include <linux/usb_gadgetfs.h>
10013 +#include <linux/usb/gadgetfs.h>
10014 #include <linux/usb_gadget.h>
10015
10016
10017 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/Kconfig linux-avr32.git/drivers/usb/gadget/Kconfig
10018 --- linux-2.6.22.1/drivers/usb/gadget/Kconfig 2007-07-10 20:56:30.000000000 +0200
10019 +++ linux-avr32.git/drivers/usb/gadget/Kconfig 2007-07-12 14:00:19.000000000 +0200
10020 @@ -175,6 +175,19 @@
10021 default USB_GADGET
10022 select USB_GADGET_SELECTED
10023
10024 +config USB_GADGET_ATMEL_USBA
10025 + boolean "Atmel USBA"
10026 + select USB_GADGET_DUALSPEED
10027 + depends on AVR32
10028 + help
10029 + USBA is the integrated high-speed USB Device controller on
10030 + the AT32AP700x processors from Atmel.
10031 +
10032 +config USB_ATMEL_USBA
10033 + tristate
10034 + depends on USB_GADGET_ATMEL_USBA
10035 + default USB_GADGET
10036 + select USB_GADGET_SELECTED
10037
10038 config USB_GADGET_OMAP
10039 boolean "OMAP USB Device Controller"
10040 diff -x .git -Nur linux-2.6.22.1/drivers/usb/gadget/Makefile linux-avr32.git/drivers/usb/gadget/Makefile
10041 --- linux-2.6.22.1/drivers/usb/gadget/Makefile 2007-07-10 20:56:30.000000000 +0200
10042 +++ linux-avr32.git/drivers/usb/gadget/Makefile 2007-07-12 14:00:19.000000000 +0200
10043 @@ -8,6 +8,7 @@
10044 obj-$(CONFIG_USB_OMAP) += omap_udc.o
10045 obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
10046 obj-$(CONFIG_USB_AT91) += at91_udc.o
10047 +obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
10048 obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
10049
10050 #
10051 diff -x .git -Nur linux-2.6.22.1/drivers/video/atmel_lcdfb.c linux-avr32.git/drivers/video/atmel_lcdfb.c
10052 --- linux-2.6.22.1/drivers/video/atmel_lcdfb.c 2007-07-10 20:56:30.000000000 +0200
10053 +++ linux-avr32.git/drivers/video/atmel_lcdfb.c 2007-07-12 14:00:20.000000000 +0200
10054 @@ -37,7 +37,9 @@
10055 #endif
10056
10057 #if defined(CONFIG_ARCH_AT91)
10058 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
10059 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
10060 + | FBINFO_PARTIAL_PAN_OK \
10061 + | FBINFO_HWACCEL_YPAN)
10062
10063 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
10064 struct fb_var_screeninfo *var)
10065 @@ -74,11 +76,34 @@
10066 .type = FB_TYPE_PACKED_PIXELS,
10067 .visual = FB_VISUAL_TRUECOLOR,
10068 .xpanstep = 0,
10069 - .ypanstep = 0,
10070 + .ypanstep = 1,
10071 .ywrapstep = 0,
10072 .accel = FB_ACCEL_NONE,
10073 };
10074
10075 +static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
10076 +{
10077 + unsigned long value;
10078 +
10079 + if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
10080 + return xres;
10081 +
10082 + value = xres;
10083 + if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
10084 + /* STN display */
10085 + if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
10086 + value *= 3;
10087 + }
10088 + if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
10089 + || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
10090 + && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
10091 + value = DIV_ROUND_UP(value, 4);
10092 + else
10093 + value = DIV_ROUND_UP(value, 8);
10094 + }
10095 +
10096 + return value;
10097 +}
10098
10099 static void atmel_lcdfb_update_dma(struct fb_info *info,
10100 struct fb_var_screeninfo *var)
10101 @@ -181,6 +206,7 @@
10102 var->xoffset = var->yoffset = 0;
10103
10104 switch (var->bits_per_pixel) {
10105 + case 1:
10106 case 2:
10107 case 4:
10108 case 8:
10109 @@ -195,8 +221,11 @@
10110 var->blue.offset = 10;
10111 var->red.length = var->green.length = var->blue.length = 5;
10112 break;
10113 - case 24:
10114 case 32:
10115 + var->transp.offset = 24;
10116 + var->transp.length = 8;
10117 + /* fall through */
10118 + case 24:
10119 var->red.offset = 0;
10120 var->green.offset = 8;
10121 var->blue.offset = 16;
10122 @@ -228,8 +257,10 @@
10123 static int atmel_lcdfb_set_par(struct fb_info *info)
10124 {
10125 struct atmel_lcdfb_info *sinfo = info->par;
10126 + unsigned long hozval_linesz;
10127 unsigned long value;
10128 unsigned long clk_value_khz;
10129 + unsigned long bits_per_line;
10130
10131 dev_dbg(info->device, "%s:\n", __func__);
10132 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
10133 @@ -241,12 +272,15 @@
10134
10135 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
10136
10137 - if (info->var.bits_per_pixel <= 8)
10138 + if (info->var.bits_per_pixel == 1)
10139 + info->fix.visual = FB_VISUAL_MONO01;
10140 + else if (info->var.bits_per_pixel <= 8)
10141 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
10142 else
10143 info->fix.visual = FB_VISUAL_TRUECOLOR;
10144
10145 - info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8);
10146 + bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
10147 + info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
10148
10149 /* Re-initialize the DMA engine... */
10150 dev_dbg(info->device, " * update DMA engine\n");
10151 @@ -262,18 +296,21 @@
10152 /* Set pixel clock */
10153 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
10154
10155 - value = clk_value_khz / PICOS2KHZ(info->var.pixclock);
10156 -
10157 - if (clk_value_khz % PICOS2KHZ(info->var.pixclock))
10158 - value++;
10159 + value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
10160
10161 value = (value / 2) - 1;
10162 + dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", value);
10163
10164 if (value <= 0) {
10165 dev_notice(info->device, "Bypassing pixel clock divider\n");
10166 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
10167 - } else
10168 + } else {
10169 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
10170 + info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
10171 + dev_dbg(info->device, " updated pixclk: %lu KHz\n",
10172 + PICOS2KHZ(info->var.pixclock));
10173 + }
10174 +
10175
10176 /* Initialize control register 2 */
10177 value = sinfo->default_lcdcon2;
10178 @@ -311,9 +348,14 @@
10179 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
10180 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
10181
10182 + /* Horizontal value (aka line size) */
10183 + hozval_linesz = compute_hozval(info->var.xres,
10184 + lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
10185 +
10186 /* Display size */
10187 - value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
10188 + value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
10189 value |= info->var.yres - 1;
10190 + dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
10191 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
10192
10193 /* FIFO Threshold: Use formula from data sheet */
10194 @@ -421,6 +463,15 @@
10195 ret = 0;
10196 }
10197 break;
10198 +
10199 + case FB_VISUAL_MONO01:
10200 + if (regno < 2) {
10201 + val = (regno == 0) ? 0x00 : 0x1F;
10202 + lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
10203 + ret = 0;
10204 + }
10205 + break;
10206 +
10207 }
10208
10209 return ret;
10210 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/Kconfig linux-avr32.git/drivers/video/backlight/Kconfig
10211 --- linux-2.6.22.1/drivers/video/backlight/Kconfig 2007-07-10 20:56:30.000000000 +0200
10212 +++ linux-avr32.git/drivers/video/backlight/Kconfig 2007-07-12 14:00:20.000000000 +0200
10213 @@ -8,26 +8,44 @@
10214 Enable this to be able to choose the drivers for controlling the
10215 backlight and the LCD panel on some platforms, for example on PDAs.
10216
10217 -config BACKLIGHT_CLASS_DEVICE
10218 - tristate "Lowlevel Backlight controls"
10219 +#
10220 +# LCD
10221 +#
10222 +config LCD_CLASS_DEVICE
10223 + tristate "Lowlevel LCD controls"
10224 depends on BACKLIGHT_LCD_SUPPORT
10225 default m
10226 help
10227 - This framework adds support for low-level control of the LCD
10228 - backlight. This includes support for brightness and power.
10229 + This framework adds support for low-level control of LCD.
10230 + Some framebuffer devices connect to platform-specific LCD modules
10231 + in order to have a platform-specific way to control the flat panel
10232 + (contrast and applying power to the LCD (not to the backlight!)).
10233
10234 To have support for your specific LCD panel you will have to
10235 select the proper drivers which depend on this option.
10236
10237 -config LCD_CLASS_DEVICE
10238 - tristate "Lowlevel LCD controls"
10239 +config LCD_LTV350QV
10240 + tristate "Samsung LTV350QV LCD Panel"
10241 + depends on LCD_CLASS_DEVICE && SPI_MASTER
10242 + default n
10243 + help
10244 + If you have a Samsung LTV350QV LCD panel, say y to include a
10245 + power control driver for it. The panel starts up in power
10246 + off state, so you need this driver in order to see any
10247 + output.
10248 +
10249 + The LTV350QV panel is present on all ATSTK1000 boards.
10250 +
10251 +#
10252 +# Backlight
10253 +#
10254 +config BACKLIGHT_CLASS_DEVICE
10255 + tristate "Lowlevel Backlight controls"
10256 depends on BACKLIGHT_LCD_SUPPORT
10257 default m
10258 help
10259 - This framework adds support for low-level control of LCD.
10260 - Some framebuffer devices connect to platform-specific LCD modules
10261 - in order to have a platform-specific way to control the flat panel
10262 - (contrast and applying power to the LCD (not to the backlight!)).
10263 + This framework adds support for low-level control of the LCD
10264 + backlight. This includes support for brightness and power.
10265
10266 To have support for your specific LCD panel you will have to
10267 select the proper drivers which depend on this option.
10268 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/ltv350qv.c linux-avr32.git/drivers/video/backlight/ltv350qv.c
10269 --- linux-2.6.22.1/drivers/video/backlight/ltv350qv.c 1970-01-01 01:00:00.000000000 +0100
10270 +++ linux-avr32.git/drivers/video/backlight/ltv350qv.c 2007-06-06 11:34:00.000000000 +0200
10271 @@ -0,0 +1,340 @@
10272 +/*
10273 + * Power control for Samsung LTV350QV Quarter VGA LCD Panel
10274 + *
10275 + * Copyright (C) 2006, 2007 Atmel Corporation
10276 + *
10277 + * This program is free software; you can redistribute it and/or modify
10278 + * it under the terms of the GNU General Public License version 2 as
10279 + * published by the Free Software Foundation.
10280 + */
10281 +#include <linux/delay.h>
10282 +#include <linux/err.h>
10283 +#include <linux/fb.h>
10284 +#include <linux/init.h>
10285 +#include <linux/lcd.h>
10286 +#include <linux/module.h>
10287 +#include <linux/spi/spi.h>
10288 +
10289 +#include "ltv350qv.h"
10290 +
10291 +#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
10292 +
10293 +struct ltv350qv {
10294 + struct spi_device *spi;
10295 + u8 *buffer;
10296 + int power;
10297 + struct lcd_device *ld;
10298 +};
10299 +
10300 +/*
10301 + * The power-on and power-off sequences are taken from the
10302 + * LTV350QV-F04 data sheet from Samsung. The register definitions are
10303 + * taken from the S6F2002 command list also from Samsung. Both
10304 + * documents are distributed with the AVR32 Linux BSP CD from Atmel.
10305 + *
10306 + * There's still some voodoo going on here, but it's a lot better than
10307 + * in the first incarnation of the driver where all we had was the raw
10308 + * numbers from the initialization sequence.
10309 + */
10310 +static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val)
10311 +{
10312 + struct spi_message msg;
10313 + struct spi_transfer index_xfer = {
10314 + .len = 3,
10315 + .cs_change = 1,
10316 + };
10317 + struct spi_transfer value_xfer = {
10318 + .len = 3,
10319 + .cs_change = 1,
10320 + };
10321 +
10322 + spi_message_init(&msg);
10323 +
10324 + /* register index */
10325 + lcd->buffer[0] = LTV_OPC_INDEX;
10326 + lcd->buffer[1] = 0x00;
10327 + lcd->buffer[2] = reg & 0x7f;
10328 + index_xfer.tx_buf = lcd->buffer;
10329 + spi_message_add_tail(&index_xfer, &msg);
10330 +
10331 + /* register value */
10332 + lcd->buffer[4] = LTV_OPC_DATA;
10333 + lcd->buffer[5] = val >> 8;
10334 + lcd->buffer[6] = val;
10335 + value_xfer.tx_buf = lcd->buffer + 4;
10336 + spi_message_add_tail(&value_xfer, &msg);
10337 +
10338 + return spi_sync(lcd->spi, &msg);
10339 +}
10340 +
10341 +/* The comments are taken straight from the data sheet */
10342 +static int ltv350qv_power_on(struct ltv350qv *lcd)
10343 +{
10344 + int ret;
10345 +
10346 + /* Power On Reset Display off State */
10347 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, 0x0000))
10348 + goto err;
10349 + msleep(15);
10350 +
10351 + /* Power Setting Function 1 */
10352 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE))
10353 + goto err;
10354 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL2, LTV_VCOML_ENABLE))
10355 + goto err_power1;
10356 +
10357 + /* Power Setting Function 2 */
10358 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1,
10359 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
10360 + | LTV_SUPPLY_CURRENT(5)))
10361 + goto err_power2;
10362 +
10363 + msleep(55);
10364 +
10365 + /* Instruction Setting */
10366 + ret = ltv350qv_write_reg(lcd, LTV_IFCTL,
10367 + LTV_NMD | LTV_REV | LTV_NL(0x1d));
10368 + ret |= ltv350qv_write_reg(lcd, LTV_DATACTL,
10369 + LTV_DS_SAME | LTV_CHS_480
10370 + | LTV_DF_RGB | LTV_RGB_BGR);
10371 + ret |= ltv350qv_write_reg(lcd, LTV_ENTRY_MODE,
10372 + LTV_VSPL_ACTIVE_LOW
10373 + | LTV_HSPL_ACTIVE_LOW
10374 + | LTV_DPL_SAMPLE_RISING
10375 + | LTV_EPL_ACTIVE_LOW
10376 + | LTV_SS_RIGHT_TO_LEFT);
10377 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL1, LTV_CLW(3));
10378 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
10379 + LTV_NW_INV_1LINE | LTV_FWI(3));
10380 + ret |= ltv350qv_write_reg(lcd, LTV_VBP, 0x000a);
10381 + ret |= ltv350qv_write_reg(lcd, LTV_HBP, 0x0021);
10382 + ret |= ltv350qv_write_reg(lcd, LTV_SOTCTL, LTV_SDT(3) | LTV_EQ(0));
10383 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(0), 0x0103);
10384 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(1), 0x0301);
10385 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(2), 0x1f0f);
10386 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(3), 0x1f0f);
10387 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(4), 0x0707);
10388 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(5), 0x0307);
10389 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(6), 0x0707);
10390 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(7), 0x0000);
10391 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(8), 0x0004);
10392 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(9), 0x0000);
10393 + if (ret)
10394 + goto err_settings;
10395 +
10396 + /* Wait more than 2 frames */
10397 + msleep(20);
10398 +
10399 + /* Display On Sequence */
10400 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
10401 + LTV_VCOM_DISABLE | LTV_VCOMOUT_ENABLE
10402 + | LTV_POWER_ON | LTV_DRIVE_CURRENT(5)
10403 + | LTV_SUPPLY_CURRENT(5));
10404 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
10405 + LTV_NW_INV_1LINE | LTV_DSC | LTV_FWI(3));
10406 + if (ret)
10407 + goto err_disp_on;
10408 +
10409 + /* Display should now be ON. Phew. */
10410 + return 0;
10411 +
10412 +err_disp_on:
10413 + /*
10414 + * Try to recover. Error handling probably isn't very useful
10415 + * at this point, just make a best effort to switch the panel
10416 + * off.
10417 + */
10418 + ltv350qv_write_reg(lcd, LTV_PWRCTL1,
10419 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
10420 + | LTV_SUPPLY_CURRENT(5));
10421 + ltv350qv_write_reg(lcd, LTV_GATECTL2,
10422 + LTV_NW_INV_1LINE | LTV_FWI(3));
10423 +err_settings:
10424 +err_power2:
10425 +err_power1:
10426 + ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
10427 + msleep(1);
10428 +err:
10429 + ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
10430 + return -EIO;
10431 +}
10432 +
10433 +static int ltv350qv_power_off(struct ltv350qv *lcd)
10434 +{
10435 + int ret;
10436 +
10437 + /* Display Off Sequence */
10438 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
10439 + LTV_VCOM_DISABLE
10440 + | LTV_DRIVE_CURRENT(5)
10441 + | LTV_SUPPLY_CURRENT(5));
10442 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
10443 + LTV_NW_INV_1LINE | LTV_FWI(3));
10444 +
10445 + /* Power down setting 1 */
10446 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
10447 +
10448 + /* Wait at least 1 ms */
10449 + msleep(1);
10450 +
10451 + /* Power down setting 2 */
10452 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
10453 +
10454 + /*
10455 + * No point in trying to recover here. If we can't switch the
10456 + * panel off, what are we supposed to do other than inform the
10457 + * user about the failure?
10458 + */
10459 + if (ret)
10460 + return -EIO;
10461 +
10462 + /* Display power should now be OFF */
10463 + return 0;
10464 +}
10465 +
10466 +static int ltv350qv_power(struct ltv350qv *lcd, int power)
10467 +{
10468 + int ret = 0;
10469 +
10470 + if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
10471 + ret = ltv350qv_power_on(lcd);
10472 + else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
10473 + ret = ltv350qv_power_off(lcd);
10474 +
10475 + if (!ret)
10476 + lcd->power = power;
10477 +
10478 + return ret;
10479 +}
10480 +
10481 +static int ltv350qv_set_power(struct lcd_device *ld, int power)
10482 +{
10483 + struct ltv350qv *lcd;
10484 +
10485 + lcd = class_get_devdata(&ld->class_dev);
10486 + return ltv350qv_power(lcd, power);
10487 +}
10488 +
10489 +static int ltv350qv_get_power(struct lcd_device *ld)
10490 +{
10491 + struct ltv350qv *lcd;
10492 +
10493 + lcd = class_get_devdata(&ld->class_dev);
10494 + return lcd->power;
10495 +}
10496 +
10497 +static struct lcd_ops ltv_ops = {
10498 + .get_power = ltv350qv_get_power,
10499 + .set_power = ltv350qv_set_power,
10500 +};
10501 +
10502 +static int __devinit ltv350qv_probe(struct spi_device *spi)
10503 +{
10504 + struct ltv350qv *lcd;
10505 + struct lcd_device *ld;
10506 + int ret;
10507 +
10508 + lcd = kzalloc(sizeof(struct ltv350qv), GFP_KERNEL);
10509 + if (!lcd)
10510 + return -ENOMEM;
10511 +
10512 + lcd->spi = spi;
10513 + lcd->power = FB_BLANK_POWERDOWN;
10514 + lcd->buffer = kzalloc(8, GFP_KERNEL);
10515 +
10516 + ld = lcd_device_register("ltv350qv", lcd, &ltv_ops);
10517 + if (IS_ERR(ld)) {
10518 + ret = PTR_ERR(ld);
10519 + goto out_free_lcd;
10520 + }
10521 + lcd->ld = ld;
10522 +
10523 + ret = ltv350qv_power(lcd, FB_BLANK_UNBLANK);
10524 + if (ret)
10525 + goto out_unregister;
10526 +
10527 + dev_set_drvdata(&spi->dev, lcd);
10528 +
10529 + return 0;
10530 +
10531 +out_unregister:
10532 + lcd_device_unregister(ld);
10533 +out_free_lcd:
10534 + kfree(lcd);
10535 + return ret;
10536 +}
10537 +
10538 +static int __devexit ltv350qv_remove(struct spi_device *spi)
10539 +{
10540 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
10541 +
10542 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
10543 + lcd_device_unregister(lcd->ld);
10544 + kfree(lcd);
10545 +
10546 + return 0;
10547 +}
10548 +
10549 +#ifdef CONFIG_PM
10550 +static int ltv350qv_suspend(struct spi_device *spi,
10551 + pm_message_t state, u32 level)
10552 +{
10553 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
10554 +
10555 + if (level == SUSPEND_POWER_DOWN)
10556 + return ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
10557 +
10558 + return 0;
10559 +}
10560 +
10561 +static int ltv350qv_resume(struct spi_device *spi, u32 level)
10562 +{
10563 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
10564 +
10565 + if (level == RESUME_POWER_ON)
10566 + return ltv350qv_power(lcd, FB_BLANK_UNBLANK);
10567 +
10568 + return 0;
10569 +}
10570 +#else
10571 +#define ltv350qv_suspend NULL
10572 +#define ltv350qv_resume NULL
10573 +#endif
10574 +
10575 +/* Power down all displays on reboot, poweroff or halt */
10576 +static void ltv350qv_shutdown(struct spi_device *spi)
10577 +{
10578 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
10579 +
10580 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
10581 +}
10582 +
10583 +static struct spi_driver ltv350qv_driver = {
10584 + .driver = {
10585 + .name = "ltv350qv",
10586 + .bus = &spi_bus_type,
10587 + .owner = THIS_MODULE,
10588 + },
10589 +
10590 + .probe = ltv350qv_probe,
10591 + .remove = __devexit_p(ltv350qv_remove),
10592 + .shutdown = ltv350qv_shutdown,
10593 + .suspend = ltv350qv_suspend,
10594 + .resume = ltv350qv_resume,
10595 +};
10596 +
10597 +static int __init ltv350qv_init(void)
10598 +{
10599 + return spi_register_driver(&ltv350qv_driver);
10600 +}
10601 +
10602 +static void __exit ltv350qv_exit(void)
10603 +{
10604 + spi_unregister_driver(&ltv350qv_driver);
10605 +}
10606 +module_init(ltv350qv_init);
10607 +module_exit(ltv350qv_exit);
10608 +
10609 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
10610 +MODULE_DESCRIPTION("Samsung LTV350QV LCD Driver");
10611 +MODULE_LICENSE("GPL");
10612 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/ltv350qv.h linux-avr32.git/drivers/video/backlight/ltv350qv.h
10613 --- linux-2.6.22.1/drivers/video/backlight/ltv350qv.h 1970-01-01 01:00:00.000000000 +0100
10614 +++ linux-avr32.git/drivers/video/backlight/ltv350qv.h 2007-06-06 11:34:00.000000000 +0200
10615 @@ -0,0 +1,95 @@
10616 +/*
10617 + * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel
10618 + *
10619 + * Copyright (C) 2006, 2007 Atmel Corporation
10620 + *
10621 + * This program is free software; you can redistribute it and/or modify
10622 + * it under the terms of the GNU General Public License version 2 as
10623 + * published by the Free Software Foundation.
10624 + */
10625 +#ifndef __LTV350QV_H
10626 +#define __LTV350QV_H
10627 +
10628 +#define LTV_OPC_INDEX 0x74
10629 +#define LTV_OPC_DATA 0x76
10630 +
10631 +#define LTV_ID 0x00 /* ID Read */
10632 +#define LTV_IFCTL 0x01 /* Display Interface Control */
10633 +#define LTV_DATACTL 0x02 /* Display Data Control */
10634 +#define LTV_ENTRY_MODE 0x03 /* Entry Mode */
10635 +#define LTV_GATECTL1 0x04 /* Gate Control 1 */
10636 +#define LTV_GATECTL2 0x05 /* Gate Control 2 */
10637 +#define LTV_VBP 0x06 /* Vertical Back Porch */
10638 +#define LTV_HBP 0x07 /* Horizontal Back Porch */
10639 +#define LTV_SOTCTL 0x08 /* Source Output Timing Control */
10640 +#define LTV_PWRCTL1 0x09 /* Power Control 1 */
10641 +#define LTV_PWRCTL2 0x0a /* Power Control 2 */
10642 +#define LTV_GAMMA(x) (0x10 + (x)) /* Gamma control */
10643 +
10644 +/* Bit definitions for LTV_IFCTL */
10645 +#define LTV_IM (1 << 15)
10646 +#define LTV_NMD (1 << 14)
10647 +#define LTV_SSMD (1 << 13)
10648 +#define LTV_REV (1 << 7)
10649 +#define LTV_NL(x) (((x) & 0x001f) << 0)
10650 +
10651 +/* Bit definitions for LTV_DATACTL */
10652 +#define LTV_DS_SAME (0 << 12)
10653 +#define LTV_DS_D_TO_S (1 << 12)
10654 +#define LTV_DS_S_TO_D (2 << 12)
10655 +#define LTV_CHS_384 (0 << 9)
10656 +#define LTV_CHS_480 (1 << 9)
10657 +#define LTV_CHS_492 (2 << 9)
10658 +#define LTV_DF_RGB (0 << 6)
10659 +#define LTV_DF_RGBX (1 << 6)
10660 +#define LTV_DF_XRGB (2 << 6)
10661 +#define LTV_RGB_RGB (0 << 2)
10662 +#define LTV_RGB_BGR (1 << 2)
10663 +#define LTV_RGB_GRB (2 << 2)
10664 +#define LTV_RGB_RBG (3 << 2)
10665 +
10666 +/* Bit definitions for LTV_ENTRY_MODE */
10667 +#define LTV_VSPL_ACTIVE_LOW (0 << 15)
10668 +#define LTV_VSPL_ACTIVE_HIGH (1 << 15)
10669 +#define LTV_HSPL_ACTIVE_LOW (0 << 14)
10670 +#define LTV_HSPL_ACTIVE_HIGH (1 << 14)
10671 +#define LTV_DPL_SAMPLE_RISING (0 << 13)
10672 +#define LTV_DPL_SAMPLE_FALLING (1 << 13)
10673 +#define LTV_EPL_ACTIVE_LOW (0 << 12)
10674 +#define LTV_EPL_ACTIVE_HIGH (1 << 12)
10675 +#define LTV_SS_LEFT_TO_RIGHT (0 << 8)
10676 +#define LTV_SS_RIGHT_TO_LEFT (1 << 8)
10677 +#define LTV_STB (1 << 1)
10678 +
10679 +/* Bit definitions for LTV_GATECTL1 */
10680 +#define LTV_CLW(x) (((x) & 0x0007) << 12)
10681 +#define LTV_GAON (1 << 5)
10682 +#define LTV_SDR (1 << 3)
10683 +
10684 +/* Bit definitions for LTV_GATECTL2 */
10685 +#define LTV_NW_INV_FRAME (0 << 14)
10686 +#define LTV_NW_INV_1LINE (1 << 14)
10687 +#define LTV_NW_INV_2LINE (2 << 14)
10688 +#define LTV_DSC (1 << 12)
10689 +#define LTV_GIF (1 << 8)
10690 +#define LTV_FHN (1 << 7)
10691 +#define LTV_FTI(x) (((x) & 0x0003) << 4)
10692 +#define LTV_FWI(x) (((x) & 0x0003) << 0)
10693 +
10694 +/* Bit definitions for LTV_SOTCTL */
10695 +#define LTV_SDT(x) (((x) & 0x0007) << 10)
10696 +#define LTV_EQ(x) (((x) & 0x0007) << 2)
10697 +
10698 +/* Bit definitions for LTV_PWRCTL1 */
10699 +#define LTV_VCOM_DISABLE (1 << 14)
10700 +#define LTV_VCOMOUT_ENABLE (1 << 11)
10701 +#define LTV_POWER_ON (1 << 9)
10702 +#define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */
10703 +#define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */
10704 +
10705 +/* Bit definitions for LTV_PWRCTL2 */
10706 +#define LTV_VCOML_ENABLE (1 << 13)
10707 +#define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */
10708 +#define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */
10709 +
10710 +#endif /* __LTV350QV_H */
10711 diff -x .git -Nur linux-2.6.22.1/drivers/video/backlight/Makefile linux-avr32.git/drivers/video/backlight/Makefile
10712 --- linux-2.6.22.1/drivers/video/backlight/Makefile 2007-07-10 20:56:30.000000000 +0200
10713 +++ linux-avr32.git/drivers/video/backlight/Makefile 2007-07-12 14:00:20.000000000 +0200
10714 @@ -1,6 +1,8 @@
10715 # Backlight & LCD drivers
10716
10717 obj-$(CONFIG_LCD_CLASS_DEVICE) += lcd.o
10718 +obj-$(CONFIG_LCD_LTV350QV) += ltv350qv.o
10719 +
10720 obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
10721 obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
10722 obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
10723 diff -x .git -Nur linux-2.6.22.1/drivers/video/Kconfig linux-avr32.git/drivers/video/Kconfig
10724 --- linux-2.6.22.1/drivers/video/Kconfig 2007-07-10 20:56:30.000000000 +0200
10725 +++ linux-avr32.git/drivers/video/Kconfig 2007-07-12 14:00:20.000000000 +0200
10726 @@ -849,6 +849,16 @@
10727 Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
10728 to let frame buffer in external SDRAM.
10729
10730 +config FB_ATMEL_STN
10731 + bool "Use a STN display with AT91/AT32 LCD Controller"
10732 + depends on FB_ATMEL && ARCH_AT91SAM9261
10733 + default n
10734 + help
10735 + Say Y if you want to connect a STN LCD display to the AT91/AT32 LCD
10736 + Controller. Say N if you want to connect a TFT.
10737 +
10738 + If unsure, say N.
10739 +
10740 config FB_NVIDIA
10741 tristate "nVidia Framebuffer Support"
10742 depends on FB && PCI
10743 diff -x .git -Nur linux-2.6.22.1/include/asm-arm/arch-at91/board.h linux-avr32.git/include/asm-arm/arch-at91/board.h
10744 --- linux-2.6.22.1/include/asm-arm/arch-at91/board.h 2007-07-10 20:56:30.000000000 +0200
10745 +++ linux-avr32.git/include/asm-arm/arch-at91/board.h 2007-07-12 14:00:26.000000000 +0200
10746 @@ -64,6 +64,7 @@
10747
10748 /* Ethernet (EMAC & MACB) */
10749 struct at91_eth_data {
10750 + u32 phy_mask;
10751 u8 phy_irq_pin; /* PHY IRQ */
10752 u8 is_rmii; /* using RMII interface? */
10753 };
10754 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/board.h linux-avr32.git/include/asm-avr32/arch-at32ap/board.h
10755 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/board.h 2007-07-10 20:56:30.000000000 +0200
10756 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/board.h 2007-07-12 14:00:26.000000000 +0200
10757 @@ -6,6 +6,8 @@
10758
10759 #include <linux/types.h>
10760
10761 +#define GPIO_PIN_NONE (-1)
10762 +
10763 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
10764 void at32_add_system_devices(void);
10765
10766 @@ -21,6 +23,7 @@
10767 struct platform_device *at32_add_device_usart(unsigned int id);
10768
10769 struct eth_platform_data {
10770 + u32 phy_mask;
10771 u8 is_rmii;
10772 };
10773 struct platform_device *
10774 @@ -30,9 +33,41 @@
10775 struct platform_device *
10776 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
10777
10778 +struct platform_device *at32_add_device_twi(unsigned int id);
10779 +
10780 +struct mci_platform_data {
10781 + int detect_pin;
10782 + int wp_pin;
10783 +};
10784 +struct platform_device *
10785 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
10786 +
10787 +struct usba_platform_data {
10788 + int vbus_pin;
10789 +};
10790 +struct platform_device *
10791 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
10792 +
10793 struct atmel_lcdfb_info;
10794 struct platform_device *
10795 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
10796 unsigned long fbmem_start, unsigned long fbmem_len);
10797
10798 +struct platform_device *at32_add_device_ac97c(unsigned int id);
10799 +struct platform_device *at32_add_device_abdac(unsigned int id);
10800 +
10801 +/* depending on what's hooked up, not all SSC pins will be used */
10802 +#define ATMEL_SSC_TK 0x01
10803 +#define ATMEL_SSC_TF 0x02
10804 +#define ATMEL_SSC_TD 0x04
10805 +#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
10806 +
10807 +#define ATMEL_SSC_RK 0x10
10808 +#define ATMEL_SSC_RF 0x20
10809 +#define ATMEL_SSC_RD 0x40
10810 +#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
10811 +
10812 +struct platform_device *
10813 +at32_add_device_ssc(unsigned int id, unsigned int flags);
10814 +
10815 #endif /* __ASM_ARCH_BOARD_H */
10816 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/portmux.h linux-avr32.git/include/asm-avr32/arch-at32ap/portmux.h
10817 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/portmux.h 2007-07-10 20:56:30.000000000 +0200
10818 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/portmux.h 2007-07-12 14:00:26.000000000 +0200
10819 @@ -25,4 +25,16 @@
10820 void at32_select_gpio(unsigned int pin, unsigned long flags);
10821 void at32_reserve_pin(unsigned int pin);
10822
10823 +#ifdef CONFIG_GPIO_DEV
10824 +
10825 +/* Gang allocators and accessors; used by the GPIO /dev driver */
10826 +int at32_gpio_port_is_valid(unsigned int port);
10827 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
10828 +void at32_deselect_pins(unsigned int port, u32 pins);
10829 +
10830 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
10831 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
10832 +
10833 +#endif /* CONFIG_GPIO_DEV */
10834 +
10835 #endif /* __ASM_ARCH_PORTMUX_H__ */
10836 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/arch-at32ap/sm.h linux-avr32.git/include/asm-avr32/arch-at32ap/sm.h
10837 --- linux-2.6.22.1/include/asm-avr32/arch-at32ap/sm.h 2007-07-10 20:56:30.000000000 +0200
10838 +++ linux-avr32.git/include/asm-avr32/arch-at32ap/sm.h 1970-01-01 01:00:00.000000000 +0100
10839 @@ -1,27 +0,0 @@
10840 -/*
10841 - * AT32 System Manager interface.
10842 - *
10843 - * Copyright (C) 2006 Atmel Corporation
10844 - *
10845 - * This program is free software; you can redistribute it and/or modify
10846 - * it under the terms of the GNU General Public License version 2 as
10847 - * published by the Free Software Foundation.
10848 - */
10849 -#ifndef __ASM_AVR32_AT32_SM_H__
10850 -#define __ASM_AVR32_AT32_SM_H__
10851 -
10852 -struct irq_chip;
10853 -struct platform_device;
10854 -
10855 -struct at32_sm {
10856 - spinlock_t lock;
10857 - void __iomem *regs;
10858 - struct irq_chip *eim_chip;
10859 - unsigned int eim_first_irq;
10860 - struct platform_device *pdev;
10861 -};
10862 -
10863 -extern struct platform_device at32_sm_device;
10864 -extern struct at32_sm system_manager;
10865 -
10866 -#endif /* __ASM_AVR32_AT32_SM_H__ */
10867 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/dma-controller.h linux-avr32.git/include/asm-avr32/dma-controller.h
10868 --- linux-2.6.22.1/include/asm-avr32/dma-controller.h 1970-01-01 01:00:00.000000000 +0100
10869 +++ linux-avr32.git/include/asm-avr32/dma-controller.h 2007-06-06 11:34:11.000000000 +0200
10870 @@ -0,0 +1,166 @@
10871 +/*
10872 + * Copyright (C) 2005-2006 Atmel Corporation
10873 + *
10874 + * This program is free software; you can redistribute it and/or modify
10875 + * it under the terms of the GNU General Public License version 2 as
10876 + * published by the Free Software Foundation.
10877 + */
10878 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
10879 +#define __ASM_AVR32_DMA_CONTROLLER_H
10880 +
10881 +#include <linux/device.h>
10882 +
10883 +#define DMA_DIR_MEM_TO_MEM 0x0000
10884 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
10885 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
10886 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
10887 +
10888 +#define DMA_WIDTH_8BIT 0
10889 +#define DMA_WIDTH_16BIT 1
10890 +#define DMA_WIDTH_32BIT 2
10891 +
10892 +struct dma_request {
10893 + struct dma_controller *dmac;
10894 + struct list_head list;
10895 +
10896 + unsigned short channel;
10897 +
10898 + void (*xfer_complete)(struct dma_request *req);
10899 + void (*block_complete)(struct dma_request *req);
10900 + void (*error)(struct dma_request *req);
10901 +};
10902 +
10903 +struct dma_request_sg {
10904 + struct dma_request req;
10905 +
10906 + int nr_sg;
10907 + struct scatterlist *sg;
10908 + unsigned long block_size;
10909 + unsigned int nr_blocks;
10910 +
10911 + dma_addr_t data_reg;
10912 + unsigned short periph_id;
10913 +
10914 + unsigned char direction;
10915 + unsigned char width;
10916 +};
10917 +#define to_dma_request_sg(_req) \
10918 + container_of(_req, struct dma_request_sg, req)
10919 +
10920 +struct dma_request_cyclic {
10921 + struct dma_request req;
10922 +
10923 + int periods;
10924 + unsigned long buffer_size;
10925 +
10926 + dma_addr_t buffer_start;
10927 + dma_addr_t data_reg;
10928 +
10929 + unsigned short periph_id;
10930 + unsigned char direction;
10931 + unsigned char width;
10932 +
10933 + void *dev_id;
10934 +};
10935 +#define to_dma_request_cyclic(_req) \
10936 + container_of(_req, struct dma_request_cyclic, req)
10937 +
10938 +struct dma_request_memcpy {
10939 + struct dma_request req;
10940 +
10941 + dma_addr_t src_addr;
10942 + unsigned int src_width;
10943 + unsigned int src_stride;
10944 +
10945 + dma_addr_t dst_addr;
10946 + unsigned int dst_width;
10947 + unsigned int dst_stride;
10948 +
10949 + size_t length;
10950 +
10951 + unsigned short src_reverse:1;
10952 + unsigned short dst_reverse:1;
10953 +};
10954 +#define to_dma_request_memcpy(_req) \
10955 + container_of(_req, struct dma_request_memcpy, req)
10956 +
10957 +struct dma_controller {
10958 + struct list_head list;
10959 + int id;
10960 + struct device *dev;
10961 +
10962 + int (*alloc_channel)(struct dma_controller *dmac);
10963 + void (*release_channel)(struct dma_controller *dmac,
10964 + int channel);
10965 + int (*prepare_request_sg)(struct dma_controller *dmac,
10966 + struct dma_request_sg *req);
10967 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
10968 + struct dma_request_cyclic *req);
10969 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
10970 + struct dma_request_memcpy *req);
10971 + int (*start_request)(struct dma_controller *dmac,
10972 + unsigned int channel);
10973 + int (*stop_request)(struct dma_controller *dmac,
10974 + unsigned int channel);
10975 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
10976 + unsigned int channel);
10977 +};
10978 +
10979 +static inline int
10980 +dma_alloc_channel(struct dma_controller *dmac)
10981 +{
10982 + return dmac->alloc_channel(dmac);
10983 +}
10984 +
10985 +static inline void
10986 +dma_release_channel(struct dma_controller *dmac, int chan)
10987 +{
10988 + dmac->release_channel(dmac, chan);
10989 +}
10990 +
10991 +static inline int
10992 +dma_prepare_request_sg(struct dma_controller *dmac,
10993 + struct dma_request_sg *req)
10994 +{
10995 + return dmac->prepare_request_sg(dmac, req);
10996 +}
10997 +
10998 +static inline int
10999 +dma_prepare_request_cyclic(struct dma_controller *dmac,
11000 + struct dma_request_cyclic *req)
11001 +{
11002 + return dmac->prepare_request_cyclic(dmac, req);
11003 +}
11004 +
11005 +static inline int
11006 +dma_prepare_request_memcpy(struct dma_controller *dmac,
11007 + struct dma_request_memcpy *req)
11008 +{
11009 + return dmac->prepare_request_memcpy(dmac, req);
11010 +}
11011 +
11012 +static inline int
11013 +dma_start_request(struct dma_controller *dmac,
11014 + unsigned int channel)
11015 +{
11016 + return dmac->start_request(dmac, channel);
11017 +}
11018 +
11019 +static inline int
11020 +dma_stop_request(struct dma_controller *dmac,
11021 + unsigned int channel)
11022 +{
11023 + return dmac->stop_request(dmac, channel);
11024 +}
11025 +
11026 +static inline dma_addr_t
11027 +dma_get_current_pos(struct dma_controller *dmac,
11028 + unsigned int channel)
11029 +{
11030 + return dmac->get_current_pos(dmac, channel);
11031 +}
11032 +
11033 +extern int register_dma_controller(struct dma_controller *dmac);
11034 +extern struct dma_controller *find_dma_controller(int id);
11035 +
11036 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
11037 diff -x .git -Nur linux-2.6.22.1/include/asm-avr32/unaligned.h linux-avr32.git/include/asm-avr32/unaligned.h
11038 --- linux-2.6.22.1/include/asm-avr32/unaligned.h 2007-07-10 20:56:30.000000000 +0200
11039 +++ linux-avr32.git/include/asm-avr32/unaligned.h 2007-07-12 14:00:26.000000000 +0200
11040 @@ -7,19 +7,10 @@
11041 * words, but halfwords must be halfword-aligned, and doublewords must
11042 * be word-aligned.
11043 *
11044 - * TODO: Make all this CPU-specific and optimize.
11045 + * However, swapped word loads must be word-aligned so we can't
11046 + * optimize word loads in general.
11047 */
11048
11049 -#include <linux/string.h>
11050 -
11051 -/* Use memmove here, so gcc does not insert a __builtin_memcpy. */
11052 -
11053 -#define get_unaligned(ptr) \
11054 - ({ __typeof__(*(ptr)) __tmp; memmove(&__tmp, (ptr), sizeof(*(ptr))); __tmp; })
11055 -
11056 -#define put_unaligned(val, ptr) \
11057 - ({ __typeof__(*(ptr)) __tmp = (val); \
11058 - memmove((ptr), &__tmp, sizeof(*(ptr))); \
11059 - (void)0; })
11060 +#include <asm-generic/unaligned.h>
11061
11062 #endif /* __ASM_AVR32_UNALIGNED_H */
11063 diff -x .git -Nur linux-2.6.22.1/include/linux/leds.h linux-avr32.git/include/linux/leds.h
11064 --- linux-2.6.22.1/include/linux/leds.h 2007-07-10 20:56:30.000000000 +0200
11065 +++ linux-avr32.git/include/linux/leds.h 2007-07-12 14:00:30.000000000 +0200
11066 @@ -110,4 +110,18 @@
11067 #define ledtrig_ide_activity() do {} while(0)
11068 #endif
11069
11070 +/* For the leds-gpio driver */
11071 +struct gpio_led {
11072 + const char *name;
11073 + char *default_trigger;
11074 + unsigned gpio;
11075 + u8 active_low;
11076 +};
11077 +
11078 +struct gpio_led_platform_data {
11079 + int num_leds;
11080 + struct gpio_led *leds;
11081 +};
11082 +
11083 +
11084 #endif /* __LINUX_LEDS_H_INCLUDED */
11085 diff -x .git -Nur linux-2.6.22.1/include/linux/usb/gadgetfs.h linux-avr32.git/include/linux/usb/gadgetfs.h
11086 --- linux-2.6.22.1/include/linux/usb/gadgetfs.h 1970-01-01 01:00:00.000000000 +0100
11087 +++ linux-avr32.git/include/linux/usb/gadgetfs.h 2007-07-12 14:00:31.000000000 +0200
11088 @@ -0,0 +1,81 @@
11089 +#ifndef __LINUX_USB_GADGETFS_H
11090 +#define __LINUX_USB_GADGETFS_H
11091 +
11092 +#include <asm/types.h>
11093 +#include <asm/ioctl.h>
11094 +
11095 +#include <linux/usb/ch9.h>
11096 +
11097 +/*
11098 + * Filesystem based user-mode API to USB Gadget controller hardware
11099 + *
11100 + * Other than ep0 operations, most things are done by read() and write()
11101 + * on endpoint files found in one directory. They are configured by
11102 + * writing descriptors, and then may be used for normal stream style
11103 + * i/o requests. When ep0 is configured, the device can enumerate;
11104 + * when it's closed, the device disconnects from usb. Operations on
11105 + * ep0 require ioctl() operations.
11106 + *
11107 + * Configuration and device descriptors get written to /dev/gadget/$CHIP,
11108 + * which may then be used to read usb_gadgetfs_event structs. The driver
11109 + * may activate endpoints as it handles SET_CONFIGURATION setup events,
11110 + * or earlier; writing endpoint descriptors to /dev/gadget/$ENDPOINT
11111 + * then performing data transfers by reading or writing.
11112 + */
11113 +
11114 +/*
11115 + * Events are delivered on the ep0 file descriptor, when the user mode driver
11116 + * reads from this file descriptor after writing the descriptors. Don't
11117 + * stop polling this descriptor.
11118 + */
11119 +
11120 +enum usb_gadgetfs_event_type {
11121 + GADGETFS_NOP = 0,
11122 +
11123 + GADGETFS_CONNECT,
11124 + GADGETFS_DISCONNECT,
11125 + GADGETFS_SETUP,
11126 + GADGETFS_SUSPEND,
11127 + // and likely more !
11128 +};
11129 +
11130 +/* NOTE: this structure must stay the same size and layout on
11131 + * both 32-bit and 64-bit kernels.
11132 + */
11133 +struct usb_gadgetfs_event {
11134 + union {
11135 + // NOP, DISCONNECT, SUSPEND: nothing
11136 + // ... some hardware can't report disconnection
11137 +
11138 + // CONNECT: just the speed
11139 + enum usb_device_speed speed;
11140 +
11141 + // SETUP: packet; DATA phase i/o precedes next event
11142 + // (setup.bmRequestType & USB_DIR_IN) flags direction
11143 + // ... includes SET_CONFIGURATION, SET_INTERFACE
11144 + struct usb_ctrlrequest setup;
11145 + } u;
11146 + enum usb_gadgetfs_event_type type;
11147 +};
11148 +
11149 +
11150 +/* endpoint ioctls */
11151 +
11152 +/* IN transfers may be reported to the gadget driver as complete
11153 + * when the fifo is loaded, before the host reads the data;
11154 + * OUT transfers may be reported to the host's "client" driver as
11155 + * complete when they're sitting in the FIFO unread.
11156 + * THIS returns how many bytes are "unclaimed" in the endpoint fifo
11157 + * (needed for precise fault handling, when the hardware allows it)
11158 + */
11159 +#define GADGETFS_FIFO_STATUS _IO('g',1)
11160 +
11161 +/* discards any unclaimed data in the fifo. */
11162 +#define GADGETFS_FIFO_FLUSH _IO('g',2)
11163 +
11164 +/* resets endpoint halt+toggle; used to implement set_interface.
11165 + * some hardware (like pxa2xx) can't support this.
11166 + */
11167 +#define GADGETFS_CLEAR_HALT _IO('g',3)
11168 +
11169 +#endif /* __LINUX_USB_GADGETFS_H */
11170 diff -x .git -Nur linux-2.6.22.1/include/linux/usb/Kbuild linux-avr32.git/include/linux/usb/Kbuild
11171 --- linux-2.6.22.1/include/linux/usb/Kbuild 2007-07-10 20:56:30.000000000 +0200
11172 +++ linux-avr32.git/include/linux/usb/Kbuild 2007-07-12 14:00:31.000000000 +0200
11173 @@ -1,5 +1,6 @@
11174 unifdef-y += audio.h
11175 unifdef-y += cdc.h
11176 unifdef-y += ch9.h
11177 +unifdef-y += gadgetfs.h
11178 unifdef-y += midi.h
11179
11180 diff -x .git -Nur linux-2.6.22.1/include/linux/usb_gadgetfs.h linux-avr32.git/include/linux/usb_gadgetfs.h
11181 --- linux-2.6.22.1/include/linux/usb_gadgetfs.h 2007-07-10 20:56:30.000000000 +0200
11182 +++ linux-avr32.git/include/linux/usb_gadgetfs.h 1970-01-01 01:00:00.000000000 +0100
11183 @@ -1,75 +0,0 @@
11184 -
11185 -#include <asm/types.h>
11186 -#include <asm/ioctl.h>
11187 -
11188 -#include <linux/usb/ch9.h>
11189 -
11190 -/*
11191 - * Filesystem based user-mode API to USB Gadget controller hardware
11192 - *
11193 - * Almost everything can be done with only read and write operations,
11194 - * on endpoint files found in one directory. They are configured by
11195 - * writing descriptors, and then may be used for normal stream style
11196 - * i/o requests. When ep0 is configured, the device can enumerate;
11197 - * when it's closed, the device disconnects from usb.
11198 - *
11199 - * Configuration and device descriptors get written to /dev/gadget/$CHIP,
11200 - * which may then be used to read usb_gadgetfs_event structs. The driver
11201 - * may activate endpoints as it handles SET_CONFIGURATION setup events,
11202 - * or earlier; writing endpoint descriptors to /dev/gadget/$ENDPOINT
11203 - * then performing data transfers by reading or writing.
11204 - */
11205 -
11206 -/*
11207 - * Events are delivered on the ep0 file descriptor, if the user mode driver
11208 - * reads from this file descriptor after writing the descriptors. Don't
11209 - * stop polling this descriptor, if you write that kind of driver.
11210 - */
11211 -
11212 -enum usb_gadgetfs_event_type {
11213 - GADGETFS_NOP = 0,
11214 -
11215 - GADGETFS_CONNECT,
11216 - GADGETFS_DISCONNECT,
11217 - GADGETFS_SETUP,
11218 - GADGETFS_SUSPEND,
11219 - // and likely more !
11220 -};
11221 -
11222 -struct usb_gadgetfs_event {
11223 - enum usb_gadgetfs_event_type type;
11224 - union {
11225 - // NOP, DISCONNECT, SUSPEND: nothing
11226 - // ... some hardware can't report disconnection
11227 -
11228 - // CONNECT: just the speed
11229 - enum usb_device_speed speed;
11230 -
11231 - // SETUP: packet; DATA phase i/o precedes next event
11232 - // (setup.bmRequestType & USB_DIR_IN) flags direction
11233 - // ... includes SET_CONFIGURATION, SET_INTERFACE
11234 - struct usb_ctrlrequest setup;
11235 - } u;
11236 -};
11237 -
11238 -
11239 -/* endpoint ioctls */
11240 -
11241 -/* IN transfers may be reported to the gadget driver as complete
11242 - * when the fifo is loaded, before the host reads the data;
11243 - * OUT transfers may be reported to the host's "client" driver as
11244 - * complete when they're sitting in the FIFO unread.
11245 - * THIS returns how many bytes are "unclaimed" in the endpoint fifo
11246 - * (needed for precise fault handling, when the hardware allows it)
11247 - */
11248 -#define GADGETFS_FIFO_STATUS _IO('g',1)
11249 -
11250 -/* discards any unclaimed data in the fifo. */
11251 -#define GADGETFS_FIFO_FLUSH _IO('g',2)
11252 -
11253 -/* resets endpoint halt+toggle; used to implement set_interface.
11254 - * some hardware (like pxa2xx) can't support this.
11255 - */
11256 -#define GADGETFS_CLEAR_HALT _IO('g',3)
11257 -
11258 -
11259 diff -x .git -Nur linux-2.6.22.1/init/do_mounts.c linux-avr32.git/init/do_mounts.c
11260 --- linux-2.6.22.1/init/do_mounts.c 2007-07-10 20:56:30.000000000 +0200
11261 +++ linux-avr32.git/init/do_mounts.c 2007-07-12 14:00:31.000000000 +0200
11262 @@ -25,6 +25,7 @@
11263 int root_mountflags = MS_RDONLY | MS_SILENT;
11264 char * __initdata root_device_name;
11265 static char __initdata saved_root_name[64];
11266 +int __initdata root_wait;
11267
11268 dev_t ROOT_DEV;
11269
11270 @@ -216,6 +217,14 @@
11271
11272 __setup("root=", root_dev_setup);
11273
11274 +static int __init rootwait_setup(char *line)
11275 +{
11276 + root_wait = simple_strtol(line,NULL,0);
11277 + return 1;
11278 +}
11279 +
11280 +__setup("rootwait=", rootwait_setup);
11281 +
11282 static char * __initdata root_mount_data;
11283 static int __init root_data_setup(char *str)
11284 {
11285 @@ -438,11 +447,24 @@
11286 root_device_name += 5;
11287 }
11288
11289 - is_floppy = MAJOR(ROOT_DEV) == FLOPPY_MAJOR;
11290 -
11291 if (initrd_load())
11292 goto out;
11293
11294 + /* wait for any asynchronous scanning to complete */
11295 + if ((ROOT_DEV == 0) && root_wait) {
11296 + printk(KERN_INFO "Waiting for root device %s...\n",
11297 + saved_root_name);
11298 + do {
11299 + while (driver_probe_done() != 0)
11300 + msleep(100);
11301 + ROOT_DEV = name_to_dev_t(saved_root_name);
11302 + if (ROOT_DEV == 0)
11303 + msleep(100);
11304 + } while (ROOT_DEV == 0);
11305 + }
11306 +
11307 + is_floppy = MAJOR(ROOT_DEV) == FLOPPY_MAJOR;
11308 +
11309 if (is_floppy && rd_doload && rd_load_disk(0))
11310 ROOT_DEV = Root_RAM0;
11311
11312 diff -x .git -Nur linux-2.6.22.1/MAINTAINERS linux-avr32.git/MAINTAINERS
11313 --- linux-2.6.22.1/MAINTAINERS 2007-07-10 20:56:30.000000000 +0200
11314 +++ linux-avr32.git/MAINTAINERS 2007-07-12 13:59:48.000000000 +0200
11315 @@ -674,6 +674,13 @@
11316 M: hskinnemoen@atmel.com
11317 S: Supported
11318
11319 +ATMEL USBA UDC DRIVER
11320 +P: Haavard Skinnemoen
11321 +M: hskinnemoen@atmel.com
11322 +L: kernel@avr32linux.org
11323 +W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
11324 +S: Supported
11325 +
11326 ATMEL WIRELESS DRIVER
11327 P: Simon Kelley
11328 M: simon@thekelleys.org.uk
11329 diff -x .git -Nur linux-2.6.22.1/scripts/checkstack.pl linux-avr32.git/scripts/checkstack.pl
11330 --- linux-2.6.22.1/scripts/checkstack.pl 2007-07-10 20:56:30.000000000 +0200
11331 +++ linux-avr32.git/scripts/checkstack.pl 2007-06-06 11:34:14.000000000 +0200
11332 @@ -12,6 +12,7 @@
11333 # sh64 port by Paul Mundt
11334 # Random bits by Matt Mackall <mpm@selenic.com>
11335 # M68k port by Geert Uytterhoeven and Andreas Schwab
11336 +# AVR32 port by Haavard Skinnemoen <hskinnemoen@atmel.com>
11337 #
11338 # Usage:
11339 # objdump -d vmlinux | stackcheck.pl [arch]
11340 @@ -37,6 +38,10 @@
11341 if ($arch eq 'arm') {
11342 #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
11343 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
11344 + } elsif ($arch eq 'avr32') {
11345 + #8000008a: 20 1d sub sp,4
11346 + #80000ca8: fa cd 05 b0 sub sp,sp,1456
11347 + $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
11348 } elsif ($arch =~ /^i[3456]86$/) {
11349 #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
11350 $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
Personal OpenWRT clone
This page took 0.457838 seconds and 5 git commands to generate.