package/mac80211/patches/561-ath9k_optimize_reg_rmw.patch

   1 --- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
   2 +++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
   3 @@ -430,6 +430,17 @@ static void ath9k_regwrite_flush(void *h
   4         mutex_unlock(&priv->wmi->multi_write_mutex);
   5  }
   6
   7 +static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
   8 +{
   9 +       u32 val;
  10 +
  11 +       val = ath9k_regread(hw_priv, reg_offset);
  12 +       val &= ~clr;
  13 +       val |= set;
  14 +       ath9k_regwrite(hw_priv, val, reg_offset);
  15 +       return val;
  16 +}
  17 +
  18  static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  19  {
  20         *csz = L1_CACHE_BYTES >> 2;
  21 @@ -655,6 +666,7 @@ static int ath9k_init_priv(struct ath9k_
  22         ah->reg_ops.write = ath9k_regwrite;
  23         ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
  24         ah->reg_ops.write_flush = ath9k_regwrite_flush;
  25 +       ah->reg_ops.rmw = ath9k_reg_rmw;
  26         priv->ah = ah;
  27
  28         common = ath9k_hw_common(ah);
  29 --- a/drivers/net/wireless/ath/ath.h
  30 +++ b/drivers/net/wireless/ath/ath.h
  31 @@ -119,6 +119,7 @@ struct ath_ops {
  32         void (*write)(void *, u32 val, u32 reg_offset);
  33         void (*enable_write_buffer)(void *);
  34         void (*write_flush) (void *);
  35 +       u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
  36  };
  37
  38  struct ath_common;
  39 --- a/drivers/net/wireless/ath/ath9k/init.c
  40 +++ b/drivers/net/wireless/ath/ath9k/init.c
  41 @@ -196,6 +196,28 @@ static unsigned int ath9k_ioread32(void
  42         return val;
  43  }
  44
  45 +static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
  46 +{
  47 +       struct ath_hw *ah = (struct ath_hw *) hw_priv;
  48 +       struct ath_common *common = ath9k_hw_common(ah);
  49 +       struct ath_softc *sc = (struct ath_softc *) common->priv;
  50 +       unsigned long uninitialized_var(flags);
  51 +       u32 val;
  52 +
  53 +       if (ah->config.serialize_regmode == SER_REG_MODE_ON)
  54 +               spin_lock_irqsave(&sc->sc_serial_rw, flags);
  55 +
  56 +       val = ioread32(sc->mem + reg_offset);
  57 +       val &= ~clr;
  58 +       val |= set;
  59 +       iowrite32(val, sc->mem + reg_offset);
  60 +
  61 +       if (ah->config.serialize_regmode == SER_REG_MODE_ON)
  62 +               spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
  63 +
  64 +       return val;
  65 +}
  66 +
  67  /**************************/
  68  /*     Initialization     */
  69  /**************************/
  70 @@ -548,6 +570,7 @@ static int ath9k_init_softc(u16 devid, s
  71         ah->hw_version.subsysid = subsysid;
  72         ah->reg_ops.read = ath9k_ioread32;
  73         ah->reg_ops.write = ath9k_iowrite32;
  74 +       ah->reg_ops.rmw = ath9k_reg_rmw;
  75         sc->sc_ah = ah;
  76
  77         if (!pdata) {
  78 --- a/drivers/net/wireless/ath/ath9k/hw.h
  79 +++ b/drivers/net/wireless/ath/ath9k/hw.h
  80 @@ -73,6 +73,9 @@
  81  #define REG_READ_MULTI(_ah, _addr, _val, _cnt)         \
  82         (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
  83
  84 +#define REG_RMW(_ah, _reg, _set, _clr) \
  85 +       (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
  86 +
  87  #define ENABLE_REGWRITE_BUFFER(_ah)                                    \
  88         do {                                                            \
  89                 if ((_ah)->reg_ops.enable_write_buffer) \
  90 @@ -87,17 +90,14 @@
  91
  92  #define SM(_v, _f)  (((_v) << _f##_S) & _f)
  93  #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
  94 -#define REG_RMW(_a, _r, _set, _clr)    \
  95 -       REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  96  #define REG_RMW_FIELD(_a, _r, _f, _v) \
  97 -       REG_WRITE(_a, _r, \
  98 -       (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  99 +       REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 100  #define REG_READ_FIELD(_a, _r, _f) \
 101         (((REG_READ(_a, _r) & _f) >> _f##_S))
 102  #define REG_SET_BIT(_a, _r, _f) \
 103 -       REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
 104 +       REG_RMW(_a, _r, (_f), 0)
 105  #define REG_CLR_BIT(_a, _r, _f) \
 106 -       REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
 107 +       REG_RMW(_a, _r, 0, (_f))
 108
 109  #define DO_DELAY(x) do {                                       \
 110                 if (((++(x) % 64) == 0) &&                      \