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export skb_attach symbol (#887)
[openwrt.git] / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2006-10-15 23:29:14.000000000 +0200
4 @@ -0,0 +1,481 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2005, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id$
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <osl.h>
20 +#include <bcmutils.h>
21 +#include <bcmsrom.h>
22 +#include <bcmdevs.h>
23 +#include <bcmendian.h>
24 +#include <pcicfg.h>
25 +#include <sbutils.h>
26 +
27 +#include <proto/ethernet.h> /* for sprom content groking */
28 +
29 +#define VARS_MAX 4096 /* should be reduced */
30 +
31 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
32 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
33 +
34 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
35 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
36 +
37 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
38 +
39 +/*
40 + * Initialize local vars from the right source for this platform.
41 + * Return 0 on success, nonzero on error.
42 + */
43 +int
44 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
45 +{
46 + ASSERT(bustype == BUSTYPE(bustype));
47 + if (vars == NULL || count == NULL)
48 + return (0);
49 +
50 + switch (BUSTYPE(bustype)) {
51 +
52 + case PCI_BUS:
53 + ASSERT(curmap); /* can not be NULL */
54 + return initvars_srom_pci(sbh, curmap, vars, count);
55 +
56 + default:
57 + return 0;
58 + }
59 + return (-1);
60 +}
61 +
62 +/* support only 16-bit word read from srom */
63 +int
64 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
65 +{
66 + void *srom;
67 + uint off, nw;
68 +
69 + ASSERT(bustype == BUSTYPE(bustype));
70 +
71 + /* check input - 16-bit access only */
72 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
73 + return 1;
74 +
75 + off = byteoff / 2;
76 + nw = nbytes / 2;
77 +
78 + if (BUSTYPE(bustype) == PCI_BUS) {
79 + if (!curmap)
80 + return 1;
81 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
82 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
83 + return 1;
84 + } else {
85 + return 1;
86 + }
87 +
88 + return 0;
89 +}
90 +
91 +/* support only 16-bit word write into srom */
92 +int
93 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
94 +{
95 + uint16 *srom;
96 + uint i, off, nw, crc_range;
97 + uint16 image[SPROM_SIZE], *p;
98 + uint8 crc;
99 + volatile uint32 val32;
100 +
101 + ASSERT(bustype == BUSTYPE(bustype));
102 +
103 + /* check input - 16-bit access only */
104 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
105 + return 1;
106 +
107 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
108 +
109 + /* if changes made inside crc cover range */
110 + if (byteoff < crc_range) {
111 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
112 + /* read data including entire first 64 words from srom */
113 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
114 + return 1;
115 + /* make changes */
116 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
117 + /* calculate crc */
118 + htol16_buf(image, crc_range);
119 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
120 + ltoh16_buf(image, crc_range);
121 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
122 + p = image;
123 + off = 0;
124 + } else {
125 + p = buf;
126 + off = byteoff / 2;
127 + nw = nbytes / 2;
128 + }
129 +
130 + if (BUSTYPE(bustype) == PCI_BUS) {
131 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
132 + /* enable writes to the SPROM */
133 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
134 + val32 |= SPROM_WRITEEN;
135 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
136 + bcm_mdelay(WRITE_ENABLE_DELAY);
137 + /* write srom */
138 + for (i = 0; i < nw; i++) {
139 + W_REG(&srom[off + i], p[i]);
140 + bcm_mdelay(WRITE_WORD_DELAY);
141 + }
142 + /* disable writes to the SPROM */
143 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
144 + } else {
145 + return 1;
146 + }
147 +
148 + bcm_mdelay(WRITE_ENABLE_DELAY);
149 + return 0;
150 +}
151 +
152 +
153 +/*
154 + * Read in and validate sprom.
155 + * Return 0 on success, nonzero on error.
156 + */
157 +static int
158 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
159 +{
160 + int err = 0;
161 + uint i;
162 +
163 + /* read the sprom */
164 + for (i = 0; i < nwords; i++)
165 + buf[i] = R_REG(&sprom[wordoff + i]);
166 +
167 + if (check_crc) {
168 + /* fixup the endianness so crc8 will pass */
169 + htol16_buf(buf, nwords * 2);
170 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
171 + err = 1;
172 + /* now correct the endianness of the byte array */
173 + ltoh16_buf(buf, nwords * 2);
174 + }
175 +
176 + return err;
177 +}
178 +
179 +/*
180 +* Create variable table from memory.
181 +* Return 0 on success, nonzero on error.
182 +*/
183 +static int
184 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
185 +{
186 + int c = (int)(end - start);
187 +
188 + /* do it only when there is more than just the null string */
189 + if (c > 1) {
190 + char *vp = MALLOC(osh, c);
191 + ASSERT(vp);
192 + if (!vp)
193 + return BCME_NOMEM;
194 + bcopy(start, vp, c);
195 + *vars = vp;
196 + *count = c;
197 + }
198 + else {
199 + *vars = NULL;
200 + *count = 0;
201 + }
202 +
203 + return 0;
204 +}
205 +
206 +/*
207 + * Initialize nonvolatile variable table from sprom.
208 + * Return 0 on success, nonzero on error.
209 + */
210 +static int
211 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
212 +{
213 + uint16 w, b[64];
214 + uint8 sromrev;
215 + struct ether_addr ea;
216 + char eabuf[32];
217 + uint32 w32;
218 + int woff, i;
219 + char *vp, *base;
220 + osl_t *osh = sb_osh(sbh);
221 + int err;
222 +
223 + /*
224 + * Apply CRC over SROM content regardless SROM is present or not,
225 + * and use variable <devpath>sromrev's existance in flash to decide
226 + * if we should return an error when CRC fails or read SROM variables
227 + * from flash.
228 + */
229 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
230 +
231 + /* top word of sprom contains version and crc8 */
232 + sromrev = b[63] & 0xff;
233 + /* bcm4401 sroms misprogrammed */
234 + if (sromrev == 0x10)
235 + sromrev = 1;
236 +
237 + /* srom version check */
238 + if (sromrev > 3)
239 + return (-2);
240 +
241 + ASSERT(vars);
242 + ASSERT(count);
243 +
244 + base = vp = MALLOC(osh, VARS_MAX);
245 + ASSERT(vp);
246 + if (!vp)
247 + return -2;
248 +
249 + vp += sprintf(vp, "sromrev=%d", sromrev);
250 + vp++;
251 +
252 + if (sromrev >= 3) {
253 + /* New section takes over the 3th hardware function space */
254 +
255 + /* Words 22+23 are 11a (mid) ofdm power offsets */
256 + w32 = ((uint32)b[23] << 16) | b[22];
257 + vp += sprintf(vp, "ofdmapo=%d", w32);
258 + vp++;
259 +
260 + /* Words 24+25 are 11a (low) ofdm power offsets */
261 + w32 = ((uint32)b[25] << 16) | b[24];
262 + vp += sprintf(vp, "ofdmalpo=%d", w32);
263 + vp++;
264 +
265 + /* Words 26+27 are 11a (high) ofdm power offsets */
266 + w32 = ((uint32)b[27] << 16) | b[26];
267 + vp += sprintf(vp, "ofdmahpo=%d", w32);
268 + vp++;
269 +
270 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
271 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
272 + vp += sprintf(vp, "gpiotimerval=%d", w32);
273 +
274 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
275 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
276 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
277 + vp += sprintf(vp, "gpiotimerval=%d", w32);
278 +
279 + vp++;
280 + }
281 +
282 + if (sromrev >= 2) {
283 + /* New section takes over the 4th hardware function space */
284 +
285 + /* Word 29 is max power 11a high/low */
286 + w = b[29];
287 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
288 + vp++;
289 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
290 + vp++;
291 +
292 + /* Words 30-32 set the 11alow pa settings,
293 + * 33-35 are the 11ahigh ones.
294 + */
295 + for (i = 0; i < 3; i++) {
296 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
297 + vp++;
298 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
299 + vp++;
300 + }
301 + w = b[59];
302 + if (w == 0)
303 + vp += sprintf(vp, "ccode=");
304 + else
305 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
306 + vp++;
307 +
308 + }
309 +
310 + /* parameter section of sprom starts at byte offset 72 */
311 + woff = 72/2;
312 +
313 + /* first 6 bytes are il0macaddr */
314 + ea.octet[0] = (b[woff] >> 8) & 0xff;
315 + ea.octet[1] = b[woff] & 0xff;
316 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
317 + ea.octet[3] = b[woff+1] & 0xff;
318 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
319 + ea.octet[5] = b[woff+2] & 0xff;
320 + woff += ETHER_ADDR_LEN/2 ;
321 + bcm_ether_ntoa((uchar*)&ea, eabuf);
322 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
323 + vp++;
324 +
325 + /* next 6 bytes are et0macaddr */
326 + ea.octet[0] = (b[woff] >> 8) & 0xff;
327 + ea.octet[1] = b[woff] & 0xff;
328 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
329 + ea.octet[3] = b[woff+1] & 0xff;
330 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
331 + ea.octet[5] = b[woff+2] & 0xff;
332 + woff += ETHER_ADDR_LEN/2 ;
333 + bcm_ether_ntoa((uchar*)&ea, eabuf);
334 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
335 + vp++;
336 +
337 + /* next 6 bytes are et1macaddr */
338 + ea.octet[0] = (b[woff] >> 8) & 0xff;
339 + ea.octet[1] = b[woff] & 0xff;
340 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
341 + ea.octet[3] = b[woff+1] & 0xff;
342 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
343 + ea.octet[5] = b[woff+2] & 0xff;
344 + woff += ETHER_ADDR_LEN/2 ;
345 + bcm_ether_ntoa((uchar*)&ea, eabuf);
346 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
347 + vp++;
348 +
349 + /*
350 + * Enet phy settings one or two singles or a dual
351 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
352 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
353 + * Bit 14 : Mdio for enet0
354 + * Bit 15 : Mdio for enet1
355 + */
356 + w = b[woff];
357 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
358 + vp++;
359 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
360 + vp++;
361 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
362 + vp++;
363 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
364 + vp++;
365 +
366 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
367 + w = b[46];
368 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
369 + vp++;
370 +
371 + if (sromrev > 1)
372 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
373 + else
374 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
375 + vp++;
376 +
377 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
378 + vp++;
379 +
380 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
381 + vp++;
382 +
383 + /* Words 47-49 set the (wl) pa settings */
384 + woff = 47;
385 +
386 + for (i = 0; i < 3; i++) {
387 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
388 + vp++;
389 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
390 + vp++;
391 + }
392 +
393 + /*
394 + * Words 50-51 set the customer-configured wl led behavior.
395 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
396 + * LED behavior values defined in wlioctl.h .
397 + */
398 + w = b[50];
399 + if ((w != 0) && (w != 0xffff)) {
400 + /* gpio0 */
401 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
402 + vp++;
403 +
404 + /* gpio1 */
405 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
406 + vp++;
407 + }
408 + w = b[51];
409 + if ((w != 0) && (w != 0xffff)) {
410 + /* gpio2 */
411 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
412 + vp++;
413 +
414 + /* gpio3 */
415 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
416 + vp++;
417 + }
418 +
419 + /* Word 52 is max power 0/1 */
420 + w = b[52];
421 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
422 + vp++;
423 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
424 + vp++;
425 +
426 + /* Word 56 is idle tssi target 0/1 */
427 + w = b[56];
428 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
429 + vp++;
430 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
431 + vp++;
432 +
433 + /* Word 57 is boardflags, if not programmed make it zero */
434 + w32 = (uint32)b[57];
435 + if (w32 == 0xffff) w32 = 0;
436 + if (sromrev > 1) {
437 + /* Word 28 is the high bits of boardflags */
438 + w32 |= (uint32)b[28] << 16;
439 + }
440 + vp += sprintf(vp, "boardflags=%d", w32);
441 + vp++;
442 +
443 + /* Word 58 is antenna gain 0/1 */
444 + w = b[58];
445 + vp += sprintf(vp, "ag0=%d", w & 0xff);
446 + vp++;
447 +
448 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
449 + vp++;
450 +
451 + if (sromrev == 1) {
452 + /* set the oem string */
453 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
454 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
455 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
456 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
457 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
458 + vp++;
459 + } else if (sromrev == 2) {
460 + /* Word 60 OFDM tx power offset from CCK level */
461 + /* OFDM Power Offset - opo */
462 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
463 + vp++;
464 + } else {
465 + /* Word 60: cck power offsets */
466 + vp += sprintf(vp, "cckpo=%d", b[60]);
467 + vp++;
468 +
469 + /* Words 61+62: 11g ofdm power offsets */
470 + w32 = ((uint32)b[62] << 16) | b[61];
471 + vp += sprintf(vp, "ofdmgpo=%d", w32);
472 + vp++;
473 + }
474 +
475 + /* final nullbyte terminator */
476 + *vp++ = '\0';
477 +
478 + ASSERT((vp - base) <= VARS_MAX);
479 +
480 + err = initvars_table(osh, base, vp, vars, count);
481 +
482 + MFREE(osh, base, VARS_MAX);
483 + return err;
484 +}
485 +
486 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
487 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
488 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2006-10-15 23:29:14.000000000 +0200
489 @@ -0,0 +1,356 @@
490 +/*
491 + * Misc useful OS-independent routines.
492 + *
493 + * Copyright 2005, Broadcom Corporation
494 + * All Rights Reserved.
495 + *
496 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
497 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
498 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
499 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
500 + * $Id$
501 + */
502 +
503 +#include <typedefs.h>
504 +#include <osl.h>
505 +#include <sbutils.h>
506 +#include <bcmnvram.h>
507 +#include <bcmutils.h>
508 +#include <bcmendian.h>
509 +#include <bcmdevs.h>
510 +
511 +unsigned char bcm_ctype[] = {
512 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
513 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
514 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
515 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
516 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
517 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
518 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
519 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
520 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
521 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
522 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
523 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
524 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
525 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
526 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
527 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
528 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
529 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
530 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
531 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
532 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
533 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
534 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
535 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
536 +};
537 +
538 +uchar
539 +bcm_toupper(uchar c)
540 +{
541 + if (bcm_islower(c))
542 + c -= 'a'-'A';
543 + return (c);
544 +}
545 +
546 +ulong
547 +bcm_strtoul(char *cp, char **endp, uint base)
548 +{
549 + ulong result, value;
550 + bool minus;
551 +
552 + minus = FALSE;
553 +
554 + while (bcm_isspace(*cp))
555 + cp++;
556 +
557 + if (cp[0] == '+')
558 + cp++;
559 + else if (cp[0] == '-') {
560 + minus = TRUE;
561 + cp++;
562 + }
563 +
564 + if (base == 0) {
565 + if (cp[0] == '0') {
566 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
567 + base = 16;
568 + cp = &cp[2];
569 + } else {
570 + base = 8;
571 + cp = &cp[1];
572 + }
573 + } else
574 + base = 10;
575 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
576 + cp = &cp[2];
577 + }
578 +
579 + result = 0;
580 +
581 + while (bcm_isxdigit(*cp) &&
582 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
583 + result = result*base + value;
584 + cp++;
585 + }
586 +
587 + if (minus)
588 + result = (ulong)(result * -1);
589 +
590 + if (endp)
591 + *endp = (char *)cp;
592 +
593 + return (result);
594 +}
595 +
596 +uint
597 +bcm_atoi(char *s)
598 +{
599 + uint n;
600 +
601 + n = 0;
602 +
603 + while (bcm_isdigit(*s))
604 + n = (n * 10) + *s++ - '0';
605 + return (n);
606 +}
607 +
608 +/* return pointer to location of substring 'needle' in 'haystack' */
609 +char*
610 +bcmstrstr(char *haystack, char *needle)
611 +{
612 + int len, nlen;
613 + int i;
614 +
615 + if ((haystack == NULL) || (needle == NULL))
616 + return (haystack);
617 +
618 + nlen = strlen(needle);
619 + len = strlen(haystack) - nlen + 1;
620 +
621 + for (i = 0; i < len; i++)
622 + if (bcmp(needle, &haystack[i], nlen) == 0)
623 + return (&haystack[i]);
624 + return (NULL);
625 +}
626 +
627 +char*
628 +bcmstrcat(char *dest, const char *src)
629 +{
630 + strcpy(&dest[strlen(dest)], src);
631 + return (dest);
632 +}
633 +
634 +
635 +char*
636 +bcm_ether_ntoa(char *ea, char *buf)
637 +{
638 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
639 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
640 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
641 + return (buf);
642 +}
643 +
644 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
645 +int
646 +bcm_ether_atoe(char *p, char *ea)
647 +{
648 + int i = 0;
649 +
650 + for (;;) {
651 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
652 + if (!*p++ || i == 6)
653 + break;
654 + }
655 +
656 + return (i == 6);
657 +}
658 +
659 +void
660 +bcm_mdelay(uint ms)
661 +{
662 + uint i;
663 +
664 + for (i = 0; i < ms; i++) {
665 + OSL_DELAY(1000);
666 + }
667 +}
668 +
669 +/*
670 + * Search the name=value vars for a specific one and return its value.
671 + * Returns NULL if not found.
672 + */
673 +char*
674 +getvar(char *vars, char *name)
675 +{
676 + char *s;
677 + int len;
678 +
679 + len = strlen(name);
680 +
681 + /* first look in vars[] */
682 + for (s = vars; s && *s; ) {
683 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
684 + return (&s[len+1]);
685 +
686 + while (*s++)
687 + ;
688 + }
689 +
690 + /* then query nvram */
691 + return (BCMINIT(nvram_get)(name));
692 +}
693 +
694 +/*
695 + * Search the vars for a specific one and return its value as
696 + * an integer. Returns 0 if not found.
697 + */
698 +int
699 +getintvar(char *vars, char *name)
700 +{
701 + char *val;
702 +
703 + if ((val = getvar(vars, name)) == NULL)
704 + return (0);
705 +
706 + return (bcm_strtoul(val, NULL, 0));
707 +}
708 +
709 +
710 +/* Search for token in comma separated token-string */
711 +static int
712 +findmatch(char *string, char *name)
713 +{
714 + uint len;
715 + char *c;
716 +
717 + len = strlen(name);
718 + while ((c = strchr(string, ',')) != NULL) {
719 + if (len == (uint)(c - string) && !strncmp(string, name, len))
720 + return 1;
721 + string = c + 1;
722 + }
723 +
724 + return (!strcmp(string, name));
725 +}
726 +
727 +/* Return gpio pin number assigned to the named pin */
728 +/*
729 +* Variable should be in format:
730 +*
731 +* gpio<N>=pin_name,pin_name
732 +*
733 +* This format allows multiple features to share the gpio with mutual
734 +* understanding.
735 +*
736 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
737 +* and if def_pin is not used by others.
738 +*/
739 +uint
740 +getgpiopin(char *vars, char *pin_name, uint def_pin)
741 +{
742 + char name[] = "gpioXXXX";
743 + char *val;
744 + uint pin;
745 +
746 + /* Go thru all possibilities till a match in pin name */
747 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
748 + sprintf(name, "gpio%d", pin);
749 + val = getvar(vars, name);
750 + if (val && findmatch(val, pin_name))
751 + return pin;
752 + }
753 +
754 + if (def_pin != GPIO_PIN_NOTDEFINED) {
755 + /* make sure the default pin is not used by someone else */
756 + sprintf(name, "gpio%d", def_pin);
757 + if (getvar(vars, name)) {
758 + def_pin = GPIO_PIN_NOTDEFINED;
759 + }
760 + }
761 +
762 + return def_pin;
763 +}
764 +
765 +
766 +/*******************************************************************************
767 + * crc8
768 + *
769 + * Computes a crc8 over the input data using the polynomial:
770 + *
771 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
772 + *
773 + * The caller provides the initial value (either CRC8_INIT_VALUE
774 + * or the previous returned value) to allow for processing of
775 + * discontiguous blocks of data. When generating the CRC the
776 + * caller is responsible for complementing the final return value
777 + * and inserting it into the byte stream. When checking, a final
778 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
779 + *
780 + * Reference: Dallas Semiconductor Application Note 27
781 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
782 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
783 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
784 + *
785 + ******************************************************************************/
786 +
787 +static uint8 crc8_table[256] = {
788 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
789 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
790 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
791 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
792 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
793 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
794 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
795 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
796 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
797 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
798 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
799 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
800 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
801 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
802 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
803 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
804 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
805 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
806 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
807 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
808 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
809 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
810 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
811 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
812 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
813 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
814 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
815 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
816 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
817 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
818 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
819 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
820 +};
821 +
822 +#define CRC_INNER_LOOP(n, c, x) \
823 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
824 +
825 +uint8
826 +hndcrc8(
827 + uint8 *pdata, /* pointer to array of data to process */
828 + uint nbytes, /* number of input data bytes to process */
829 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
830 +)
831 +{
832 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
833 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
834 + while (nbytes-- > 0)
835 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
836 +
837 + return crc;
838 +}
839 +
840 +#ifdef notdef
841 +#define CLEN 1499
842 +#define CBUFSIZ (CLEN+4)
843 +#define CNBUFS 5
844 +
845 +#endif
846 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
847 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
848 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2006-10-15 23:29:14.000000000 +0200
849 @@ -0,0 +1,234 @@
850 +/*
851 + * NVRAM variable manipulation (Linux kernel half)
852 + *
853 + * Copyright 2001-2003, Broadcom Corporation
854 + * All Rights Reserved.
855 + *
856 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
857 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
858 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
859 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
860 + *
861 + * $Id$
862 + */
863 +
864 +#include <linux/config.h>
865 +#include <linux/init.h>
866 +#include <linux/module.h>
867 +#include <linux/kernel.h>
868 +#include <linux/string.h>
869 +#include <asm/io.h>
870 +#include <asm/uaccess.h>
871 +
872 +#include <typedefs.h>
873 +#include <osl.h>
874 +#include <bcmendian.h>
875 +#include <bcmutils.h>
876 +
877 +#define NVRAM_SIZE (0x1ff0)
878 +static char _nvdata[NVRAM_SIZE] __initdata;
879 +static char _valuestr[256] __initdata;
880 +
881 +/*
882 + * TLV types. These codes are used in the "type-length-value"
883 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
884 + *
885 + * The layout of the flash/nvram is as follows:
886 + *
887 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
888 + *
889 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
890 + * The "length" field marks the length of the data section, not
891 + * including the type and length fields.
892 + *
893 + * Environment variables are stored as follows:
894 + *
895 + * <type_env> <length> <flags> <name> = <value>
896 + *
897 + * If bit 0 (low bit) is set, the length is an 8-bit value.
898 + * If bit 0 (low bit) is clear, the length is a 16-bit value
899 + *
900 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
901 + * indicates the size of the length field.
902 + *
903 + * Flags are from the constants below:
904 + *
905 + */
906 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
907 +#define ENV_LENGTH_8BITS 0x01
908 +
909 +#define ENV_TYPE_USER 0x80
910 +
911 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
912 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
913 +
914 +/*
915 + * The actual TLV types we support
916 + */
917 +
918 +#define ENV_TLV_TYPE_END 0x00
919 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
920 +
921 +/*
922 + * Environment variable flags
923 + */
924 +
925 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
926 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
927 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
928 +
929 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
930 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
931 +
932 +
933 +/* *********************************************************************
934 + * _nvram_read(buffer,offset,length)
935 + *
936 + * Read data from the NVRAM device
937 + *
938 + * Input parameters:
939 + * buffer - destination buffer
940 + * offset - offset of data to read
941 + * length - number of bytes to read
942 + *
943 + * Return value:
944 + * number of bytes read, or <0 if error occured
945 + ********************************************************************* */
946 +static int
947 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
948 +{
949 + int i;
950 + if (offset > NVRAM_SIZE)
951 + return -1;
952 +
953 + for ( i = 0; i < length; i++) {
954 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
955 + }
956 + return length;
957 +}
958 +
959 +
960 +static char*
961 +_strnchr(const char *dest,int c,size_t cnt)
962 +{
963 + while (*dest && (cnt > 0)) {
964 + if (*dest == c) return (char *) dest;
965 + dest++;
966 + cnt--;
967 + }
968 + return NULL;
969 +}
970 +
971 +
972 +
973 +/*
974 + * Core support API: Externally visible.
975 + */
976 +
977 +/*
978 + * Get the value of an NVRAM variable
979 + * @param name name of variable to get
980 + * @return value of variable or NULL if undefined
981 + */
982 +
983 +char*
984 +cfe_env_get(unsigned char *nv_buf, char* name)
985 +{
986 + int size;
987 + unsigned char *buffer;
988 + unsigned char *ptr;
989 + unsigned char *envval;
990 + unsigned int reclen;
991 + unsigned int rectype;
992 + int offset;
993 + int flg;
994 +
995 + size = NVRAM_SIZE;
996 + buffer = &_nvdata[0];
997 +
998 + ptr = buffer;
999 + offset = 0;
1000 +
1001 + /* Read the record type and length */
1002 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1003 + goto error;
1004 + }
1005 +
1006 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1007 +
1008 + /* Adjust pointer for TLV type */
1009 + rectype = *(ptr);
1010 + offset++;
1011 + size--;
1012 +
1013 + /*
1014 + * Read the length. It can be either 1 or 2 bytes
1015 + * depending on the code
1016 + */
1017 + if (rectype & ENV_LENGTH_8BITS) {
1018 + /* Read the record type and length - 8 bits */
1019 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1020 + goto error;
1021 + }
1022 + reclen = *(ptr);
1023 + size--;
1024 + offset++;
1025 + }
1026 + else {
1027 + /* Read the record type and length - 16 bits, MSB first */
1028 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1029 + goto error;
1030 + }
1031 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1032 + size -= 2;
1033 + offset += 2;
1034 + }
1035 +
1036 + if (reclen > size)
1037 + break; /* should not happen, bad NVRAM */
1038 +
1039 + switch (rectype) {
1040 + case ENV_TLV_TYPE_ENV:
1041 + /* Read the TLV data */
1042 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1043 + goto error;
1044 + flg = *ptr++;
1045 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1046 + if (envval) {
1047 + *envval++ = '\0';
1048 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1049 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1050 +#if 0
1051 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1052 +#endif
1053 + if(!strcmp(ptr, name)){
1054 + return _valuestr;
1055 + }
1056 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1057 + return _valuestr;
1058 + }
1059 + break;
1060 +
1061 + default:
1062 + /* Unknown TLV type, skip it. */
1063 + break;
1064 + }
1065 +
1066 + /*
1067 + * Advance to next TLV
1068 + */
1069 +
1070 + size -= (int)reclen;
1071 + offset += reclen;
1072 +
1073 + /* Read the next record type */
1074 + ptr = buffer;
1075 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1076 + goto error;
1077 + }
1078 +
1079 +error:
1080 + return NULL;
1081 +
1082 +}
1083 +
1084 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1085 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1086 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2006-10-15 23:29:14.000000000 +0200
1087 @@ -0,0 +1,102 @@
1088 +/*
1089 + * Linux OS Independent Layer
1090 + *
1091 + * Copyright 2005, Broadcom Corporation
1092 + * All Rights Reserved.
1093 + *
1094 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1095 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1096 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1097 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1098 + *
1099 + * $Id$
1100 + */
1101 +
1102 +#define LINUX_OSL
1103 +
1104 +#include <typedefs.h>
1105 +#include <bcmendian.h>
1106 +#include <linux/module.h>
1107 +#include <linuxver.h>
1108 +#include <osl.h>
1109 +#include <bcmutils.h>
1110 +#include <linux/delay.h>
1111 +#ifdef mips
1112 +#include <asm/paccess.h>
1113 +#endif
1114 +#include <pcicfg.h>
1115 +
1116 +#define PCI_CFG_RETRY 10
1117 +
1118 +#define OS_HANDLE_MAGIC 0x1234abcd
1119 +#define BCM_MEM_FILENAME_LEN 24
1120 +
1121 +typedef struct bcm_mem_link {
1122 + struct bcm_mem_link *prev;
1123 + struct bcm_mem_link *next;
1124 + uint size;
1125 + int line;
1126 + char file[BCM_MEM_FILENAME_LEN];
1127 +} bcm_mem_link_t;
1128 +
1129 +struct os_handle {
1130 + uint magic;
1131 + void *pdev;
1132 + uint malloced;
1133 + uint failed;
1134 + bcm_mem_link_t *dbgmem_list;
1135 +};
1136 +
1137 +uint32
1138 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1139 +{
1140 + uint val;
1141 + uint retry=PCI_CFG_RETRY;
1142 +
1143 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1144 +
1145 + /* only 4byte access supported */
1146 + ASSERT(size == 4);
1147 +
1148 + do {
1149 + pci_read_config_dword(osh->pdev, offset, &val);
1150 + if (val != 0xffffffff)
1151 + break;
1152 + } while (retry--);
1153 +
1154 +
1155 + return (val);
1156 +}
1157 +
1158 +void
1159 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1160 +{
1161 + uint retry=PCI_CFG_RETRY;
1162 +
1163 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1164 +
1165 + /* only 4byte access supported */
1166 + ASSERT(size == 4);
1167 +
1168 + do {
1169 + pci_write_config_dword(osh->pdev, offset, val);
1170 + if (offset!=PCI_BAR0_WIN)
1171 + break;
1172 + if (osl_pci_read_config(osh,offset,size) == val)
1173 + break;
1174 + } while (retry--);
1175 +
1176 +}
1177 +
1178 +void
1179 +osl_delay(uint usec)
1180 +{
1181 + uint d;
1182 +
1183 + while (usec > 0) {
1184 + d = MIN(usec, 1000);
1185 + udelay(d);
1186 + usec -= d;
1187 + }
1188 +}
1189 +
1190 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
1191 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
1192 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2006-10-15 23:29:14.000000000 +0200
1193 @@ -0,0 +1,6 @@
1194 +#
1195 +# Makefile for the BCM47xx specific kernel interface routines
1196 +# under Linux.
1197 +#
1198 +
1199 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
1200 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1201 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2006-10-15 23:29:14.000000000 +0200
1203 @@ -0,0 +1,192 @@
1204 +/*
1205 + * NVRAM variable manipulation (Linux kernel half)
1206 + *
1207 + * Copyright 2005, Broadcom Corporation
1208 + * All Rights Reserved.
1209 + *
1210 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1211 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1212 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1213 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1214 + *
1215 + * $Id$
1216 + */
1217 +
1218 +#include <linux/config.h>
1219 +#include <linux/init.h>
1220 +#include <linux/module.h>
1221 +#include <linux/kernel.h>
1222 +#include <linux/string.h>
1223 +#include <linux/interrupt.h>
1224 +#include <linux/spinlock.h>
1225 +#include <linux/slab.h>
1226 +#include <asm/bootinfo.h>
1227 +#include <asm/addrspace.h>
1228 +#include <asm/io.h>
1229 +#include <asm/uaccess.h>
1230 +
1231 +#include <typedefs.h>
1232 +#include <bcmendian.h>
1233 +#include <bcmnvram.h>
1234 +#include <bcmutils.h>
1235 +#include <sbconfig.h>
1236 +#include <sbchipc.h>
1237 +#include <sbutils.h>
1238 +#include <sbmips.h>
1239 +#include <sflash.h>
1240 +
1241 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1242 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1243 +
1244 +/* Global SB handle */
1245 +extern void *sbh;
1246 +extern spinlock_t bcm947xx_sbh_lock;
1247 +static int cfe_env;
1248 +
1249 +extern char *cfe_env_get(char *nv_buf, const char *name);
1250 +
1251 +
1252 +/* Convenience */
1253 +#define sbh_lock bcm947xx_sbh_lock
1254 +#define KB * 1024
1255 +#define MB * 1024 * 1024
1256 +
1257 +/* Probe for NVRAM header */
1258 +static void __init
1259 +early_nvram_init(void)
1260 +{
1261 + struct nvram_header *header;
1262 + chipcregs_t *cc;
1263 + struct sflash *info = NULL;
1264 + int i;
1265 + uint32 base, off, lim;
1266 + u32 *src, *dst;
1267 +
1268 + cfe_env = 0;
1269 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1270 + base = KSEG1ADDR(SB_FLASH2);
1271 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1272 + case PFLASH:
1273 + lim = SB_FLASH2_SZ;
1274 + break;
1275 +
1276 + case SFLASH_ST:
1277 + case SFLASH_AT:
1278 + if ((info = sflash_init(cc)) == NULL)
1279 + return;
1280 + lim = info->size;
1281 + break;
1282 +
1283 + case FLASH_NONE:
1284 + default:
1285 + return;
1286 + }
1287 + } else {
1288 + /* extif assumed, Stop at 4 MB */
1289 + base = KSEG1ADDR(SB_FLASH1);
1290 + lim = SB_FLASH1_SZ;
1291 + }
1292 +
1293 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1294 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1295 + dst = (u32 *) nvram_buf;
1296 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1297 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1298 +
1299 + for (i = 0; i < 0x1ff0; i++) {
1300 + if (*src == 0xFFFFFFFF)
1301 + break;
1302 + *dst++ = *src++;
1303 + }
1304 + cfe_env = 1;
1305 + return;
1306 + }
1307 +
1308 + off = FLASH_MIN;
1309 + while (off <= lim) {
1310 + /* Windowed flash access */
1311 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1312 + if (header->magic == NVRAM_MAGIC)
1313 + goto found;
1314 + off <<= 1;
1315 + }
1316 +
1317 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1318 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1319 + if (header->magic == NVRAM_MAGIC)
1320 + goto found;
1321 +
1322 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1323 + if (header->magic == NVRAM_MAGIC)
1324 + goto found;
1325 +
1326 + return;
1327 +
1328 +found:
1329 + src = (u32 *) header;
1330 + dst = (u32 *) nvram_buf;
1331 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1332 + *dst++ = *src++;
1333 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1334 + *dst++ = ltoh32(*src++);
1335 +}
1336 +
1337 +/* Early (before mm or mtd) read-only access to NVRAM */
1338 +char * __init early_nvram_get(const char *name)
1339 +{
1340 + char *var, *value, *end, *eq;
1341 +
1342 + if (!name)
1343 + return NULL;
1344 +
1345 + /* Too early? */
1346 + if (sbh == NULL)
1347 + return NULL;
1348 +
1349 + if (!nvram_buf[0])
1350 + early_nvram_init();
1351 +
1352 + if (cfe_env)
1353 + return cfe_env_get(nvram_buf, name);
1354 +
1355 + /* Look for name=value and return value */
1356 + var = &nvram_buf[sizeof(struct nvram_header)];
1357 + end = nvram_buf + sizeof(nvram_buf) - 2;
1358 + end[0] = end[1] = '\0';
1359 + for (; *var; var = value + strlen(value) + 1) {
1360 + if (!(eq = strchr(var, '=')))
1361 + break;
1362 + value = eq + 1;
1363 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1364 + return value;
1365 + }
1366 +
1367 + return NULL;
1368 +}
1369 +
1370 +char *nvram_get(const char *name)
1371 +{
1372 + char *var, *value, *end, *eq;
1373 +
1374 + if (!name)
1375 + return NULL;
1376 +
1377 + if (!nvram_buf[0])
1378 + return NULL;
1379 +
1380 + /* Look for name=value and return value */
1381 + var = &nvram_buf[sizeof(struct nvram_header)];
1382 + end = nvram_buf + sizeof(nvram_buf) - 2;
1383 + end[0] = end[1] = '\0';
1384 + for (; *var; var = value + strlen(value) + 1) {
1385 + if (!(eq = strchr(var, '=')))
1386 + break;
1387 + value = eq + 1;
1388 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1389 + return value;
1390 + }
1391 +
1392 + return NULL;
1393 +}
1394 +
1395 +EXPORT_SYMBOL(nvram_get);
1396 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1397 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1398 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2006-10-15 23:46:15.000000000 +0200
1399 @@ -0,0 +1,1115 @@
1400 +/*
1401 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1402 + *
1403 + * Copyright 2005, Broadcom Corporation
1404 + * All Rights Reserved.
1405 + *
1406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1410 + *
1411 + * $Id$
1412 + */
1413 +
1414 +#include <typedefs.h>
1415 +#include <osl.h>
1416 +#include <sbutils.h>
1417 +#include <bcmdevs.h>
1418 +#include <bcmnvram.h>
1419 +#include <bcmutils.h>
1420 +#include <hndmips.h>
1421 +#include <sbconfig.h>
1422 +#include <sbextif.h>
1423 +#include <sbchipc.h>
1424 +#include <sbmemc.h>
1425 +#include <mipsinc.h>
1426 +#include <sbutils.h>
1427 +
1428 +/*
1429 + * Returns TRUE if an external UART exists at the given base
1430 + * register.
1431 + */
1432 +static bool
1433 +BCMINITFN(serial_exists)(uint8 *regs)
1434 +{
1435 + uint8 save_mcr, status1;
1436 +
1437 + save_mcr = R_REG(&regs[UART_MCR]);
1438 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1439 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1440 + W_REG(&regs[UART_MCR], save_mcr);
1441 +
1442 + return (status1 == 0x90);
1443 +}
1444 +
1445 +/*
1446 + * Initializes UART access. The callback function will be called once
1447 + * per found UART.
1448 + */
1449 +void
1450 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1451 +{
1452 + void *regs;
1453 + ulong base;
1454 + uint irq;
1455 + int i, n;
1456 +
1457 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1458 + extifregs_t *eir = (extifregs_t *) regs;
1459 + sbconfig_t *sb;
1460 +
1461 + /* Determine external UART register base */
1462 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1463 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1464 +
1465 + /* Determine IRQ */
1466 + irq = sb_irq(sbh);
1467 +
1468 + /* Disable GPIO interrupt initially */
1469 + W_REG(&eir->gpiointpolarity, 0);
1470 + W_REG(&eir->gpiointmask, 0);
1471 +
1472 + /* Search for external UARTs */
1473 + n = 2;
1474 + for (i = 0; i < 2; i++) {
1475 + regs = (void *) REG_MAP(base + (i * 8), 8);
1476 + if (BCMINIT(serial_exists)(regs)) {
1477 + /* Set GPIO 1 to be the external UART IRQ */
1478 + W_REG(&eir->gpiointmask, 2);
1479 + if (add)
1480 + add(regs, irq, 13500000, 0);
1481 + }
1482 + }
1483 +
1484 + /* Add internal UART if enabled */
1485 + if (R_REG(&eir->corecontrol) & CC_UE)
1486 + if (add)
1487 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1488 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1489 + chipcregs_t *cc = (chipcregs_t *) regs;
1490 + uint32 rev, cap, pll, baud_base, div;
1491 +
1492 + /* Determine core revision and capabilities */
1493 + rev = sb_corerev(sbh);
1494 + cap = R_REG(&cc->capabilities);
1495 + pll = cap & CAP_PLL_MASK;
1496 +
1497 + /* Determine IRQ */
1498 + irq = sb_irq(sbh);
1499 +
1500 + if (pll == PLL_TYPE1) {
1501 + /* PLL clock */
1502 + baud_base = sb_clock_rate(pll,
1503 + R_REG(&cc->clockcontrol_n),
1504 + R_REG(&cc->clockcontrol_m2));
1505 + div = 1;
1506 + } else {
1507 + if (rev >= 11) {
1508 + /* Fixed ALP clock */
1509 + baud_base = 20000000;
1510 + div = 1;
1511 + /* Set the override bit so we don't divide it */
1512 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1513 + } else if (rev >= 3) {
1514 + /* Internal backplane clock */
1515 + baud_base = sb_clock(sbh);
1516 + div = 2; /* Minimum divisor */
1517 + W_REG(&cc->clkdiv,
1518 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1519 + } else {
1520 + /* Fixed internal backplane clock */
1521 + baud_base = 88000000;
1522 + div = 48;
1523 + }
1524 +
1525 + /* Clock source depends on strapping if UartClkOverride is unset */
1526 + if ((rev > 0) &&
1527 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1528 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1529 + /* Internal divided backplane clock */
1530 + baud_base /= div;
1531 + } else {
1532 + /* Assume external clock of 1.8432 MHz */
1533 + baud_base = 1843200;
1534 + }
1535 + }
1536 + }
1537 +
1538 + /* Add internal UARTs */
1539 + n = cap & CAP_UARTS_MASK;
1540 + for (i = 0; i < n; i++) {
1541 + /* Register offset changed after revision 0 */
1542 + if (rev)
1543 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1544 + else
1545 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1546 +
1547 + if (add)
1548 + add(regs, irq, baud_base, 0);
1549 + }
1550 + }
1551 +}
1552 +
1553 +/*
1554 + * Initialize jtag master and return handle for
1555 + * jtag_rwreg. Returns NULL on failure.
1556 + */
1557 +void *
1558 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1559 +{
1560 + void *regs;
1561 +
1562 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1563 + chipcregs_t *cc = (chipcregs_t *) regs;
1564 + uint32 tmp;
1565 +
1566 + /*
1567 + * Determine jtagm availability from
1568 + * core revision and capabilities.
1569 + */
1570 + tmp = sb_corerev(sbh);
1571 + /*
1572 + * Corerev 10 has jtagm, but the only chip
1573 + * with it does not have a mips, and
1574 + * the layout of the jtagcmd register is
1575 + * different. We'll only accept >= 11.
1576 + */
1577 + if (tmp < 11)
1578 + return (NULL);
1579 +
1580 + tmp = R_REG(&cc->capabilities);
1581 + if ((tmp & CAP_JTAGP) == 0)
1582 + return (NULL);
1583 +
1584 + /* Set clock divider if requested */
1585 + if (clkd != 0) {
1586 + tmp = R_REG(&cc->clkdiv);
1587 + tmp = (tmp & ~CLKD_JTAG) |
1588 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1589 + W_REG(&cc->clkdiv, tmp);
1590 + }
1591 +
1592 + /* Enable jtagm */
1593 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1594 + W_REG(&cc->jtagctrl, tmp);
1595 + }
1596 +
1597 + return (regs);
1598 +}
1599 +
1600 +void
1601 +sb_jtagm_disable(void *h)
1602 +{
1603 + chipcregs_t *cc = (chipcregs_t *)h;
1604 +
1605 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1606 +}
1607 +
1608 +/*
1609 + * Read/write a jtag register. Assumes a target with
1610 + * 8 bit IR and 32 bit DR.
1611 + */
1612 +#define IRWIDTH 8
1613 +#define DRWIDTH 32
1614 +uint32
1615 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1616 +{
1617 + chipcregs_t *cc = (chipcregs_t *) h;
1618 + uint32 tmp;
1619 +
1620 + W_REG(&cc->jtagir, ir);
1621 + W_REG(&cc->jtagdr, dr);
1622 + tmp = JCMD_START | JCMD_ACC_IRDR |
1623 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1624 + (DRWIDTH - 1);
1625 + W_REG(&cc->jtagcmd, tmp);
1626 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1627 + /* OSL_DELAY(1); */
1628 + }
1629 +
1630 + tmp = R_REG(&cc->jtagdr);
1631 + return (tmp);
1632 +}
1633 +
1634 +/* Returns the SB interrupt flag of the current core. */
1635 +uint32
1636 +sb_flag(sb_t *sbh)
1637 +{
1638 + void *regs;
1639 + sbconfig_t *sb;
1640 +
1641 + regs = sb_coreregs(sbh);
1642 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1643 +
1644 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1645 +}
1646 +
1647 +static const uint32 sbips_int_mask[] = {
1648 + 0,
1649 + SBIPS_INT1_MASK,
1650 + SBIPS_INT2_MASK,
1651 + SBIPS_INT3_MASK,
1652 + SBIPS_INT4_MASK
1653 +};
1654 +
1655 +static const uint32 sbips_int_shift[] = {
1656 + 0,
1657 + 0,
1658 + SBIPS_INT2_SHIFT,
1659 + SBIPS_INT3_SHIFT,
1660 + SBIPS_INT4_SHIFT
1661 +};
1662 +
1663 +/*
1664 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1665 + * 0 is returned.
1666 + */
1667 +uint
1668 +sb_irq(sb_t *sbh)
1669 +{
1670 + uint idx;
1671 + void *regs;
1672 + sbconfig_t *sb;
1673 + uint32 flag, sbipsflag;
1674 + uint irq = 0;
1675 +
1676 + flag = sb_flag(sbh);
1677 +
1678 + idx = sb_coreidx(sbh);
1679 +
1680 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1681 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1682 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1683 +
1684 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1685 + sbipsflag = R_REG(&sb->sbipsflag);
1686 + for (irq = 1; irq <= 4; irq++) {
1687 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1688 + break;
1689 + }
1690 + if (irq == 5)
1691 + irq = 0;
1692 + }
1693 +
1694 + sb_setcoreidx(sbh, idx);
1695 +
1696 + return irq;
1697 +}
1698 +
1699 +/* Clears the specified MIPS IRQ. */
1700 +static void
1701 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1702 +{
1703 + void *regs;
1704 + sbconfig_t *sb;
1705 +
1706 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1707 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1708 + ASSERT(regs);
1709 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1710 +
1711 + if (irq == 0)
1712 + W_REG(&sb->sbintvec, 0);
1713 + else
1714 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1715 +}
1716 +
1717 +/*
1718 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1719 + * IRQ 0 may be assigned more than once.
1720 + */
1721 +static void
1722 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 + uint32 flag;
1727 +
1728 + regs = sb_setcore(sbh, coreid, coreunit);
1729 + ASSERT(regs);
1730 + flag = sb_flag(sbh);
1731 +
1732 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1733 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1734 + ASSERT(regs);
1735 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1736 +
1737 + if (irq == 0)
1738 + OR_REG(&sb->sbintvec, 1 << flag);
1739 + else {
1740 + flag <<= sbips_int_shift[irq];
1741 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1742 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1743 + W_REG(&sb->sbipsflag, flag);
1744 + }
1745 +}
1746 +
1747 +/*
1748 + * Initializes clocks and interrupts. SB and NVRAM access must be
1749 + * initialized prior to calling.
1750 + */
1751 +void
1752 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1753 +{
1754 + ulong hz, ns, tmp;
1755 + extifregs_t *eir;
1756 + chipcregs_t *cc;
1757 + char *value;
1758 + uint irq;
1759 +
1760 + /* Figure out current SB clock speed */
1761 + if ((hz = sb_clock(sbh)) == 0)
1762 + hz = 100000000;
1763 + ns = 1000000000 / hz;
1764 +
1765 + /* Setup external interface timing */
1766 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1767 + /* Initialize extif so we can get to the LEDs and external UART */
1768 + W_REG(&eir->prog_config, CF_EN);
1769 +
1770 + /* Set timing for the flash */
1771 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1772 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1773 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1774 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1775 +
1776 + /* Set programmable interface timing for external uart */
1777 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1778 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1779 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1780 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1781 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1782 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1783 + /* set register for external IO to control LED. */
1784 + W_REG(&cc->prog_config, 0x11);
1785 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1786 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1787 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
1788 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1789 +
1790 + /* Set timing for the flash */
1791 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1792 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1793 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1794 +
1795 + // Added by Chen-I for 5365
1796 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1797 + {
1798 + W_REG(&cc->flash_waitcount, tmp);
1799 + W_REG(&cc->pcmcia_memwait, tmp);
1800 + }
1801 + else
1802 + {
1803 + if (sb_corerev(sbh) < 9)
1804 + W_REG(&cc->flash_waitcount, tmp);
1805 +
1806 + if ((sb_corerev(sbh) < 9) ||
1807 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1808 + W_REG(&cc->pcmcia_memwait, tmp);
1809 + }
1810 + }
1811 + // Added by Chen-I & Yen for enabling 5350 EXTIF
1812 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
1813 + {
1814 + /* Set programmable interface timing for external uart */
1815 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1816 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1817 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1818 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1819 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1820 + }
1821 + }
1822 +
1823 + /* Chip specific initialization */
1824 + switch (BCMINIT(sb_chip)(sbh)) {
1825 + case BCM4710_DEVICE_ID:
1826 + /* Clear interrupt map */
1827 + for (irq = 0; irq <= 4; irq++)
1828 + BCMINIT(sb_clearirq)(sbh, irq);
1829 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1830 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1831 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1832 + // BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0); /* seems to be unused */
1833 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1834 + ASSERT(eir);
1835 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1836 + if (value && !strcmp(value, "31")) {
1837 + /* Enable internal UART */
1838 + W_REG(&eir->corecontrol, CC_UE);
1839 + } else {
1840 + /* Disable internal UART */
1841 + W_REG(&eir->corecontrol, 0);
1842 + /* Give Ethernet its own interrupt */
1843 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1844 + }
1845 + /* USB gets its own interrupt */
1846 + BCMINIT(sb_setirq)(sbh, 3, SB_USB, 0);
1847 +
1848 + break;
1849 + case BCM5350_DEVICE_ID:
1850 + /* Clear interrupt map */
1851 + for (irq = 0; irq <= 4; irq++)
1852 + BCMINIT(sb_clearirq)(sbh, irq);
1853 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1854 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1855 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1856 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1857 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1858 + break;
1859 + }
1860 +}
1861 +
1862 +uint32
1863 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1864 +{
1865 + extifregs_t *eir;
1866 + chipcregs_t *cc;
1867 + uint32 n, m;
1868 + uint idx;
1869 + uint32 pll_type, rate = 0;
1870 +
1871 + /* get index of the current core */
1872 + idx = sb_coreidx(sbh);
1873 + pll_type = PLL_TYPE1;
1874 +
1875 + /* switch to extif or chipc core */
1876 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1877 + n = R_REG(&eir->clockcontrol_n);
1878 + m = R_REG(&eir->clockcontrol_sb);
1879 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1880 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1881 + n = R_REG(&cc->clockcontrol_n);
1882 + if ((pll_type == PLL_TYPE2) ||
1883 + (pll_type == PLL_TYPE4) ||
1884 + (pll_type == PLL_TYPE6) ||
1885 + (pll_type == PLL_TYPE7))
1886 + m = R_REG(&cc->clockcontrol_mips);
1887 + else if (pll_type == PLL_TYPE5) {
1888 + rate = 200000000;
1889 + goto out;
1890 + }
1891 + else if (pll_type == PLL_TYPE3) {
1892 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1893 + rate = 200000000;
1894 + goto out;
1895 + } else
1896 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1897 + } else
1898 + m = R_REG(&cc->clockcontrol_sb);
1899 + } else
1900 + goto out;
1901 +
1902 + // Added by Chen-I for 5365
1903 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1904 + rate = 100000000;
1905 + else
1906 + /* calculate rate */
1907 + rate = sb_clock_rate(pll_type, n, m);
1908 +
1909 + if (pll_type == PLL_TYPE6)
1910 + rate = SB2MIPS_T6(rate);
1911 +
1912 +out:
1913 + /* switch back to previous core */
1914 + sb_setcoreidx(sbh, idx);
1915 +
1916 + return rate;
1917 +}
1918 +
1919 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1920 +
1921 +static void
1922 +BCMINITFN(handler)(void)
1923 +{
1924 + /* Step 11 */
1925 + __asm__ (
1926 + ".set\tmips32\n\t"
1927 + "ssnop\n\t"
1928 + "ssnop\n\t"
1929 + /* Disable interrupts */
1930 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1931 + "mfc0 $15, $12\n\t"
1932 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1933 + "li $14, -31746\n\t"
1934 + "and $15, $15, $14\n\t"
1935 + "mtc0 $15, $12\n\t"
1936 + "eret\n\t"
1937 + "nop\n\t"
1938 + "nop\n\t"
1939 + ".set\tmips0"
1940 + );
1941 +}
1942 +
1943 +/* The following MUST come right after handler() */
1944 +static void
1945 +BCMINITFN(afterhandler)(void)
1946 +{
1947 +}
1948 +
1949 +/*
1950 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1951 + */
1952 +bool
1953 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1954 +{
1955 + extifregs_t *eir = NULL;
1956 + chipcregs_t *cc = NULL;
1957 + mipsregs_t *mipsr = NULL;
1958 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1959 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1960 + uint32 pll_type, sync_mode;
1961 + uint ic_size, ic_lsize;
1962 + uint idx, i;
1963 + typedef struct {
1964 + uint32 mipsclock;
1965 + uint16 n;
1966 + uint32 sb;
1967 + uint32 pci33;
1968 + uint32 pci25;
1969 + } n3m_table_t;
1970 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1971 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1972 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1973 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1974 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1975 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1976 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1977 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1978 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1979 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1980 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1981 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1982 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1983 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1984 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1985 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1986 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1987 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1988 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1989 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1990 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1991 + };
1992 + typedef struct {
1993 + uint32 mipsclock;
1994 + uint16 n;
1995 + uint32 m2; /* that is the clockcontrol_m2 */
1996 + } type3_table_t;
1997 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
1998 + { 150000000, 0x311, 0x4020005 },
1999 + { 200000000, 0x311, 0x4020003 },
2000 + };
2001 + typedef struct {
2002 + uint32 mipsclock;
2003 + uint32 sbclock;
2004 + uint16 n;
2005 + uint32 sb;
2006 + uint32 pci33;
2007 + uint32 m2;
2008 + uint32 m3;
2009 + uint32 ratio_cfg;
2010 + uint32 ratio_parm;
2011 + } n4m_table_t;
2012 +
2013 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2014 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2015 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2016 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2017 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2018 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2019 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2020 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2021 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2023 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2026 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2027 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2028 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2029 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2031 + };
2032 +
2033 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2034 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2035 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2036 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2037 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2038 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2039 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2041 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2042 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2043 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2045 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2047 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2048 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2049 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2050 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2051 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2052 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2053 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2054 + };
2055 +
2056 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2057 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2058 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2059 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2060 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2061 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2062 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2063 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2065 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2066 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2067 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2068 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2070 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2071 + };
2072 +
2073 + ulong start, end, dst;
2074 + bool ret = FALSE;
2075 +
2076 + /* get index of the current core */
2077 + idx = sb_coreidx(sbh);
2078 + clockcontrol_m2 = NULL;
2079 +
2080 + /* switch to extif or chipc core */
2081 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2082 + pll_type = PLL_TYPE1;
2083 + clockcontrol_n = &eir->clockcontrol_n;
2084 + clockcontrol_sb = &eir->clockcontrol_sb;
2085 + clockcontrol_pci = &eir->clockcontrol_pci;
2086 + clockcontrol_m2 = &cc->clockcontrol_m2;
2087 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2088 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2089 + if (pll_type == PLL_TYPE6) {
2090 + clockcontrol_n = NULL;
2091 + clockcontrol_sb = NULL;
2092 + clockcontrol_pci = NULL;
2093 + } else {
2094 + clockcontrol_n = &cc->clockcontrol_n;
2095 + clockcontrol_sb = &cc->clockcontrol_sb;
2096 + clockcontrol_pci = &cc->clockcontrol_pci;
2097 + clockcontrol_m2 = &cc->clockcontrol_m2;
2098 + }
2099 + } else
2100 + goto done;
2101 +
2102 + if (pll_type == PLL_TYPE6) {
2103 + /* Silence compilers */
2104 + orig_n = orig_sb = orig_pci = 0;
2105 + } else {
2106 + /* Store the current clock register values */
2107 + orig_n = R_REG(clockcontrol_n);
2108 + orig_sb = R_REG(clockcontrol_sb);
2109 + orig_pci = R_REG(clockcontrol_pci);
2110 + }
2111 +
2112 + if (pll_type == PLL_TYPE1) {
2113 + /* Keep the current PCI clock if not specified */
2114 + if (pciclock == 0) {
2115 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2116 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2117 + }
2118 +
2119 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2120 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2121 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2122 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2123 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2124 + break;
2125 + }
2126 + if (i == 0) {
2127 + ret = FALSE;
2128 + goto done;
2129 + } else {
2130 + ret = TRUE;
2131 + i--;
2132 + }
2133 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2134 +
2135 + /* No PLL change */
2136 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2137 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2138 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2139 + goto done;
2140 +
2141 + /* Set the PLL controls */
2142 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2143 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2144 + if (pciclock == 25000000)
2145 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2146 + else
2147 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2148 +
2149 + /* Reset */
2150 + sb_watchdog(sbh, 1);
2151 +
2152 + while (1);
2153 + } else if ((pll_type == PLL_TYPE3) &&
2154 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2155 + /* 5350 */
2156 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2157 +
2158 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2159 + if (type3_table[i].mipsclock > mipsclock)
2160 + break;
2161 + }
2162 + if (i == 0) {
2163 + ret = FALSE;
2164 + goto done;
2165 + } else {
2166 + ret = TRUE;
2167 + i--;
2168 + }
2169 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2170 +
2171 + /* No PLL change */
2172 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2173 + if ((orig_n == type3_table[i].n) &&
2174 + (orig_m2 == type3_table[i].m2)) {
2175 + goto done;
2176 + }
2177 +
2178 + /* Set the PLL controls */
2179 + W_REG(clockcontrol_n, type3_table[i].n);
2180 + W_REG(clockcontrol_m2, type3_table[i].m2);
2181 +
2182 + /* Reset */
2183 + sb_watchdog(sbh, 1);
2184 + while (1);
2185 + } else if ((pll_type == PLL_TYPE2) ||
2186 + (pll_type == PLL_TYPE4) ||
2187 + (pll_type == PLL_TYPE6) ||
2188 + (pll_type == PLL_TYPE7)) {
2189 + n4m_table_t *table = NULL, *te;
2190 + uint tabsz = 0;
2191 +
2192 + ASSERT(cc);
2193 +
2194 + orig_mips = R_REG(&cc->clockcontrol_mips);
2195 +
2196 + if (pll_type == PLL_TYPE6) {
2197 + uint32 new_mips = 0;
2198 +
2199 + ret = TRUE;
2200 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2201 + new_mips = CC_T6_MMASK;
2202 +
2203 + if (orig_mips == new_mips)
2204 + goto done;
2205 +
2206 + W_REG(&cc->clockcontrol_mips, new_mips);
2207 + goto end_fill;
2208 + }
2209 +
2210 + if (pll_type == PLL_TYPE2) {
2211 + table = BCMINIT(type2_table);
2212 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2213 + } else if (pll_type == PLL_TYPE4) {
2214 + table = BCMINIT(type4_table);
2215 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2216 + } else if (pll_type == PLL_TYPE7) {
2217 + table = BCMINIT(type7_table);
2218 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2219 + } else
2220 + ASSERT("No table for plltype" == NULL);
2221 +
2222 + /* Store the current clock register values */
2223 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2224 + orig_ratio_parm = 0;
2225 + orig_ratio_cfg = 0;
2226 +
2227 + /* Look up current ratio */
2228 + for (i = 0; i < tabsz; i++) {
2229 + if ((orig_n == table[i].n) &&
2230 + (orig_sb == table[i].sb) &&
2231 + (orig_pci == table[i].pci33) &&
2232 + (orig_m2 == table[i].m2) &&
2233 + (orig_mips == table[i].m3)) {
2234 + orig_ratio_parm = table[i].ratio_parm;
2235 + orig_ratio_cfg = table[i].ratio_cfg;
2236 + break;
2237 + }
2238 + }
2239 +
2240 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2241 + for (i = 0; i < tabsz; i++) {
2242 + ASSERT(table[i].mipsclock ==
2243 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2244 + if ((mipsclock <= table[i].mipsclock) &&
2245 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2246 + break;
2247 + }
2248 + if (i == tabsz) {
2249 + ret = FALSE;
2250 + goto done;
2251 + } else {
2252 + te = &table[i];
2253 + ret = TRUE;
2254 + }
2255 +
2256 + /* No PLL change */
2257 + if ((orig_n == te->n) &&
2258 + (orig_sb == te->sb) &&
2259 + (orig_pci == te->pci33) &&
2260 + (orig_m2 == te->m2) &&
2261 + (orig_mips == te->m3))
2262 + goto done;
2263 +
2264 + /* Set the PLL controls */
2265 + W_REG(clockcontrol_n, te->n);
2266 + W_REG(clockcontrol_sb, te->sb);
2267 + W_REG(clockcontrol_pci, te->pci33);
2268 + W_REG(&cc->clockcontrol_m2, te->m2);
2269 + W_REG(&cc->clockcontrol_mips, te->m3);
2270 +
2271 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2272 + if ((pll_type == PLL_TYPE7) &&
2273 + (te->sb != te->m2) &&
2274 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2275 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2276 +
2277 + /* No ratio change */
2278 + if (orig_ratio_parm == te->ratio_parm)
2279 + goto end_fill;
2280 +
2281 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2282 +
2283 + /* Preload the code into the cache */
2284 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2285 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2286 + while (start < end) {
2287 + cache_op(start, Fill_I);
2288 + start += ic_lsize;
2289 + }
2290 +
2291 + /* Copy the handler */
2292 + start = (ulong) &BCMINIT(handler);
2293 + end = (ulong) &BCMINIT(afterhandler);
2294 + dst = KSEG1ADDR(0x180);
2295 + for (i = 0; i < (end - start); i += 4)
2296 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2297 +
2298 + /* Preload handler into the cache one line at a time */
2299 + for (i = 0; i < (end - start); i += 4)
2300 + cache_op(dst + i, Fill_I);
2301 +
2302 + /* Clear BEV bit */
2303 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2304 +
2305 + /* Enable interrupts */
2306 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2307 +
2308 + /* Enable MIPS timer interrupt */
2309 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2310 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2311 + ASSERT(mipsr);
2312 + W_REG(&mipsr->intmask, 1);
2313 +
2314 + start_fill:
2315 + /* step 1, set clock ratios */
2316 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2317 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2318 +
2319 + /* step 2: program timer intr */
2320 + W_REG(&mipsr->timer, 100);
2321 + (void) R_REG(&mipsr->timer);
2322 +
2323 + /* step 3, switch to async */
2324 + sync_mode = MFC0(C0_BROADCOM, 4);
2325 + MTC0(C0_BROADCOM, 4, 1 << 22);
2326 +
2327 + /* step 4, set cfg active */
2328 + MTC0(C0_BROADCOM, 2, 0x9);
2329 +
2330 +
2331 + /* steps 5 & 6 */
2332 + __asm__ __volatile__ (
2333 + ".set\tmips3\n\t"
2334 + "wait\n\t"
2335 + ".set\tmips0"
2336 + );
2337 +
2338 + /* step 7, clear cfg_active */
2339 + MTC0(C0_BROADCOM, 2, 0);
2340 +
2341 + /* Additional Step: set back to orig sync mode */
2342 + MTC0(C0_BROADCOM, 4, sync_mode);
2343 +
2344 + /* step 8, fake soft reset */
2345 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2346 +
2347 + end_fill:
2348 + /* step 9 set watchdog timer */
2349 + sb_watchdog(sbh, 20);
2350 + (void) R_REG(&cc->chipid);
2351 +
2352 + /* step 11 */
2353 + __asm__ __volatile__ (
2354 + ".set\tmips3\n\t"
2355 + "sync\n\t"
2356 + "wait\n\t"
2357 + ".set\tmips0"
2358 + );
2359 + while (1);
2360 + }
2361 +
2362 +done:
2363 + /* switch back to previous core */
2364 + sb_setcoreidx(sbh, idx);
2365 +
2366 + return ret;
2367 +}
2368 +
2369 +/*
2370 + * This also must be run from the cache on 47xx
2371 + * so there are no mips core BIU ops in progress
2372 + * when the PFC is enabled.
2373 + */
2374 +
2375 +static void
2376 +BCMINITFN(_enable_pfc)(uint32 mode)
2377 +{
2378 + /* write range */
2379 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2380 +
2381 + /* enable */
2382 + *(volatile uint32 *)PFC_CR0 = mode;
2383 +}
2384 +
2385 +void
2386 +BCMINITFN(enable_pfc)(uint32 mode)
2387 +{
2388 + ulong start, end;
2389 + int i;
2390 +
2391 + /* If auto then choose the correct mode for this
2392 + platform, currently we only ever select one mode */
2393 + if (mode == PFC_AUTO)
2394 + mode = PFC_INST;
2395 +
2396 + /* enable prefetch cache if available */
2397 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2398 + start = (ulong) &BCMINIT(_enable_pfc);
2399 + end = (ulong) &BCMINIT(enable_pfc);
2400 +
2401 + /* Preload handler into the cache one line at a time */
2402 + for (i = 0; i < (end - start); i += 4)
2403 + cache_op(start + i, Fill_I);
2404 +
2405 + BCMINIT(_enable_pfc)(mode);
2406 + }
2407 +}
2408 +
2409 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2410 +uint32
2411 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2412 +{
2413 + sbmemcregs_t *memc;
2414 + uint32 ret = 0;
2415 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2416 + uint idx, rev;
2417 +
2418 + idx = sb_coreidx(sbh);
2419 +
2420 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2421 + if (memc == 0)
2422 + goto out;
2423 +
2424 + rev = sb_corerev(sbh);
2425 +
2426 + config = R_REG(&memc->config);
2427 + wr = R_REG(&memc->wrncdlcor);
2428 + rd = R_REG(&memc->rdncdlcor);
2429 + misc = R_REG(&memc->miscdlyctl);
2430 + dqsg = R_REG(&memc->dqsgatencdl);
2431 +
2432 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2433 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2434 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2435 +
2436 + if (config & MEMC_CONFIG_DDR) {
2437 + ret = (wr << 16) | (rd << 8) | dqsg;
2438 + } else {
2439 + if (rev > 0)
2440 + cd = rd;
2441 + else
2442 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2443 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2444 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2445 + ret = (sm << 16) | (sd << 8) | cd;
2446 + }
2447 +
2448 +out:
2449 + /* switch back to previous core */
2450 + sb_setcoreidx(sbh, idx);
2451 +
2452 + return ret;
2453 +}
2454 +
2455 +uint32
2456 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
2457 +{
2458 + extifregs_t *eir;
2459 + chipcregs_t *cc;
2460 + uint32 n, m;
2461 + uint idx;
2462 + uint32 pll_type, rate = 0;
2463 +
2464 + /* get index of the current core */
2465 + idx = sb_coreidx(sbh);
2466 + pll_type = PLL_TYPE1;
2467 +
2468 + /* switch to extif or chipc core */
2469 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2470 + n = R_REG(&eir->clockcontrol_n);
2471 + m = R_REG(&eir->clockcontrol_sb);
2472 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2473 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2474 + n = R_REG(&cc->clockcontrol_n);
2475 + if ((pll_type == PLL_TYPE2) ||
2476 + (pll_type == PLL_TYPE4) ||
2477 + (pll_type == PLL_TYPE6) ||
2478 + (pll_type == PLL_TYPE7))
2479 + m = R_REG(&cc->clockcontrol_mips);
2480 + else if (pll_type == PLL_TYPE5) {
2481 + rate = 200000000;
2482 + goto out;
2483 + }
2484 + else if (pll_type == PLL_TYPE3) {
2485 + if (sb_chip(sbh) == 0x5365) {
2486 + rate = 200000000;
2487 + goto out;
2488 + }
2489 + /* 5350 uses m2 to control mips */
2490 + else
2491 + m = R_REG(&cc->clockcontrol_m2);
2492 + } else
2493 + m = R_REG(&cc->clockcontrol_sb);
2494 + } else
2495 + goto out;
2496 +
2497 +
2498 + /* calculate rate */
2499 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
2500 + rate = 100000000;
2501 + else
2502 + rate = sb_clock_rate(pll_type, n, m);
2503 +
2504 + if (pll_type == PLL_TYPE6)
2505 + rate = SB2MIPS_T6(rate);
2506 +
2507 +out:
2508 + /* switch back to previous core */
2509 + sb_setcoreidx(sbh, idx);
2510 +
2511 + return rate;
2512 +}
2513 +
2514 +
2515
2516 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2517 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2518 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2006-10-15 23:29:14.000000000 +0200
2519 @@ -0,0 +1,534 @@
2520 +/*
2521 + * Low-Level PCI and SB support for BCM47xx
2522 + *
2523 + * Copyright 2005, Broadcom Corporation
2524 + * All Rights Reserved.
2525 + *
2526 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2527 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2528 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2529 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2530 + *
2531 + * $Id$
2532 + */
2533 +
2534 +#include <typedefs.h>
2535 +#include <pcicfg.h>
2536 +#include <bcmdevs.h>
2537 +#include <sbconfig.h>
2538 +#include <osl.h>
2539 +#include <sbutils.h>
2540 +#include <sbpci.h>
2541 +#include <bcmendian.h>
2542 +#include <bcmutils.h>
2543 +#include <bcmnvram.h>
2544 +#include <hndmips.h>
2545 +
2546 +/* Can free sbpci_init() memory after boot */
2547 +#ifndef linux
2548 +#define __init
2549 +#endif
2550 +
2551 +/* Emulated configuration space */
2552 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2553 +
2554 +/* Banned cores */
2555 +static uint16 pci_ban[32] = { 0 };
2556 +static uint pci_banned = 0;
2557 +
2558 +/* CardBus mode */
2559 +static bool cardbus = FALSE;
2560 +
2561 +/* Disable PCI host core */
2562 +static bool pci_disabled = FALSE;
2563 +
2564 +/*
2565 + * Functions for accessing external PCI configuration space
2566 + */
2567 +
2568 +/* Assume one-hot slot wiring */
2569 +#define PCI_SLOT_MAX 16
2570 +
2571 +static uint32
2572 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2573 +{
2574 + uint coreidx;
2575 + sbpciregs_t *regs;
2576 + uint32 addr = 0;
2577 +
2578 + /* CardBusMode supports only one device */
2579 + if (cardbus && dev > 1)
2580 + return 0;
2581 +
2582 + coreidx = sb_coreidx(sbh);
2583 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2584 +
2585 + /* Type 0 transaction */
2586 + if (bus == 1) {
2587 + /* Skip unwired slots */
2588 + if (dev < PCI_SLOT_MAX) {
2589 + /* Slide the PCI window to the appropriate slot */
2590 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2591 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2592 + (func << 8) | (off & ~3);
2593 + }
2594 + }
2595 +
2596 + /* Type 1 transaction */
2597 + else {
2598 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2599 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2600 + }
2601 +
2602 + sb_setcoreidx(sbh, coreidx);
2603 +
2604 + return addr;
2605 +}
2606 +
2607 +static int
2608 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2609 +{
2610 + uint32 addr, *reg = NULL, val;
2611 + int ret = 0;
2612 +
2613 + if (pci_disabled ||
2614 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2615 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2616 + BUSPROBE(val, reg))
2617 + val = 0xffffffff;
2618 +
2619 + val >>= 8 * (off & 3);
2620 + if (len == 4)
2621 + *((uint32 *) buf) = val;
2622 + else if (len == 2)
2623 + *((uint16 *) buf) = (uint16) val;
2624 + else if (len == 1)
2625 + *((uint8 *) buf) = (uint8) val;
2626 + else
2627 + ret = -1;
2628 +
2629 + if (reg)
2630 + REG_UNMAP(reg);
2631 +
2632 + return ret;
2633 +}
2634 +
2635 +static int
2636 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2637 +{
2638 + uint32 addr, *reg = NULL, val;
2639 + int ret = 0;
2640 +
2641 + if (pci_disabled ||
2642 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2643 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2644 + BUSPROBE(val, reg))
2645 + goto done;
2646 +
2647 + if (len == 4)
2648 + val = *((uint32 *) buf);
2649 + else if (len == 2) {
2650 + val &= ~(0xffff << (8 * (off & 3)));
2651 + val |= *((uint16 *) buf) << (8 * (off & 3));
2652 + } else if (len == 1) {
2653 + val &= ~(0xff << (8 * (off & 3)));
2654 + val |= *((uint8 *) buf) << (8 * (off & 3));
2655 + } else
2656 + ret = -1;
2657 +
2658 + W_REG(reg, val);
2659 +
2660 + done:
2661 + if (reg)
2662 + REG_UNMAP(reg);
2663 +
2664 + return ret;
2665 +}
2666 +
2667 +/*
2668 + * Functions for accessing translated SB configuration space
2669 + */
2670 +
2671 +static int
2672 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2673 +{
2674 + pci_config_regs *cfg;
2675 +
2676 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2677 + return -1;
2678 + cfg = &sb_config_regs[dev];
2679 +
2680 + ASSERT(ISALIGNED(off, len));
2681 + ASSERT(ISALIGNED((uintptr)buf, len));
2682 +
2683 + if (len == 4)
2684 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2685 + else if (len == 2)
2686 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2687 + else if (len == 1)
2688 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2689 + else
2690 + return -1;
2691 +
2692 + return 0;
2693 +}
2694 +
2695 +static int
2696 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2697 +{
2698 + uint coreidx, n;
2699 + void *regs;
2700 + sbconfig_t *sb;
2701 + pci_config_regs *cfg;
2702 +
2703 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2704 + return -1;
2705 + cfg = &sb_config_regs[dev];
2706 +
2707 + ASSERT(ISALIGNED(off, len));
2708 + ASSERT(ISALIGNED((uintptr)buf, len));
2709 +
2710 + /* Emulate BAR sizing */
2711 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2712 + len == 4 && *((uint32 *) buf) == ~0) {
2713 + coreidx = sb_coreidx(sbh);
2714 + if ((regs = sb_setcoreidx(sbh, dev))) {
2715 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2716 + /* Highest numbered address match register */
2717 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2718 + if (off == OFFSETOF(pci_config_regs, base[0]))
2719 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2720 +#if 0
2721 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2722 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2723 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2724 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2725 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2726 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2727 +#endif
2728 + }
2729 + sb_setcoreidx(sbh, coreidx);
2730 + return 0;
2731 + }
2732 +
2733 + if (len == 4)
2734 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2735 + else if (len == 2)
2736 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2737 + else if (len == 1)
2738 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2739 + else
2740 + return -1;
2741 +
2742 + return 0;
2743 +}
2744 +
2745 +int
2746 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2747 +{
2748 + if (bus == 0)
2749 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2750 + else
2751 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2752 +}
2753 +
2754 +int
2755 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2756 +{
2757 + if (bus == 0)
2758 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2759 + else
2760 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2761 +}
2762 +
2763 +void
2764 +sbpci_ban(uint16 core)
2765 +{
2766 + if (pci_banned < ARRAYSIZE(pci_ban))
2767 + pci_ban[pci_banned++] = core;
2768 +}
2769 +
2770 +static int
2771 +sbpci_init_pci(sb_t *sbh)
2772 +{
2773 + uint chip, chiprev, chippkg, host;
2774 + uint32 boardflags;
2775 + sbpciregs_t *pci;
2776 + sbconfig_t *sb;
2777 + uint32 val;
2778 +
2779 + chip = sb_chip(sbh);
2780 + chiprev = sb_chiprev(sbh);
2781 + chippkg = sb_chippkg(sbh);
2782 +
2783 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2784 + printf("PCI: no core\n");
2785 + pci_disabled = TRUE;
2786 + return -1;
2787 + }
2788 + sb_core_reset(sbh, 0);
2789 +
2790 + boardflags = (uint32) getintvar(NULL, "boardflags");
2791 +
2792 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2793 + pci_disabled = TRUE;
2794 +
2795 + /*
2796 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2797 + * PCI is bonded out, some boards may leave the pins
2798 + * floating.
2799 + */
2800 + if (((chip == BCM4712_DEVICE_ID) &&
2801 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2802 + (chippkg == BCM4712MID_PKG_ID))) ||
2803 + (chip == BCM5350_DEVICE_ID) ||
2804 + (boardflags & BFL_NOPCI))
2805 + pci_disabled = TRUE;
2806 +
2807 + /*
2808 + * If the PCI core should not be touched (disabled, not bonded
2809 + * out, or pins floating), do not even attempt to access core
2810 + * registers. Otherwise, try to determine if it is in host
2811 + * mode.
2812 + */
2813 + if (pci_disabled)
2814 + host = 0;
2815 + else
2816 + host = !BUSPROBE(val, &pci->control);
2817 +
2818 + if (!host) {
2819 + /* Disable PCI interrupts in client mode */
2820 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2821 + W_REG(&sb->sbintvec, 0);
2822 +
2823 + /* Disable the PCI bridge in client mode */
2824 + sbpci_ban(SB_PCI);
2825 + printf("PCI: Disabled\n");
2826 + } else {
2827 + /* Reset the external PCI bus and enable the clock */
2828 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2829 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2830 + OSL_DELAY(150); /* delay > 100 us */
2831 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2832 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2833 + OSL_DELAY(1); /* delay 1 us */
2834 +
2835 + /* Enable CardBusMode */
2836 + cardbus = nvram_match("cardbus", "1");
2837 + if (cardbus) {
2838 + printf("PCI: Enabling CardBus\n");
2839 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2840 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2841 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2842 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2843 + }
2844 +
2845 + /* 64 MB I/O access window */
2846 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2847 + /* 64 MB configuration access window */
2848 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2849 + /* 1 GB memory access window */
2850 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2851 +
2852 + /* Enable PCI bridge BAR0 prefetch and burst */
2853 + val = 6;
2854 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2855 +
2856 + /* Enable PCI interrupts */
2857 + W_REG(&pci->intmask, PCI_INTA);
2858 + }
2859 +
2860 + return 0;
2861 +}
2862 +
2863 +static int
2864 +sbpci_init_cores(sb_t *sbh)
2865 +{
2866 + uint chip, chiprev, chippkg, coreidx, i;
2867 + sbconfig_t *sb;
2868 + pci_config_regs *cfg;
2869 + void *regs;
2870 + char varname[8];
2871 + uint wlidx = 0;
2872 + uint16 vendor, core;
2873 + uint8 class, subclass, progif;
2874 + uint32 val;
2875 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2876 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2877 +
2878 + chip = sb_chip(sbh);
2879 + chiprev = sb_chiprev(sbh);
2880 + chippkg = sb_chippkg(sbh);
2881 + coreidx = sb_coreidx(sbh);
2882 +
2883 + /* Scan the SB bus */
2884 + bzero(sb_config_regs, sizeof(sb_config_regs));
2885 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2886 + cfg->vendor = 0xffff;
2887 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2888 + continue;
2889 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2890 +
2891 + /* Read ID register and parse vendor and core */
2892 + val = R_REG(&sb->sbidhigh);
2893 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2894 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2895 + progif = 0;
2896 +
2897 + /* Check if this core is banned */
2898 + for (i = 0; i < pci_banned; i++)
2899 + if (core == pci_ban[i])
2900 + break;
2901 + if (i < pci_banned)
2902 + continue;
2903 +
2904 + /* Known vendor translations */
2905 + switch (vendor) {
2906 + case SB_VEND_BCM:
2907 + vendor = VENDOR_BROADCOM;
2908 + break;
2909 + }
2910 +
2911 + /* Determine class based on known core codes */
2912 + switch (core) {
2913 + case SB_ILINE20:
2914 + class = PCI_CLASS_NET;
2915 + subclass = PCI_NET_ETHER;
2916 + core = BCM47XX_ILINE_ID;
2917 + break;
2918 + case SB_ILINE100:
2919 + class = PCI_CLASS_NET;
2920 + subclass = PCI_NET_ETHER;
2921 + core = BCM4610_ILINE_ID;
2922 + break;
2923 + case SB_ENET:
2924 + class = PCI_CLASS_NET;
2925 + subclass = PCI_NET_ETHER;
2926 + core = BCM47XX_ENET_ID;
2927 + break;
2928 + case SB_SDRAM:
2929 + case SB_MEMC:
2930 + class = PCI_CLASS_MEMORY;
2931 + subclass = PCI_MEMORY_RAM;
2932 + break;
2933 + case SB_PCI:
2934 +#if 0
2935 + class = PCI_CLASS_BRIDGE;
2936 + subclass = PCI_BRIDGE_PCI;
2937 + break;
2938 +#endif
2939 + case SB_MIPS:
2940 + case SB_MIPS33:
2941 + class = PCI_CLASS_CPU;
2942 + subclass = PCI_CPU_MIPS;
2943 + break;
2944 + case SB_CODEC:
2945 + class = PCI_CLASS_COMM;
2946 + subclass = PCI_COMM_MODEM;
2947 + core = BCM47XX_V90_ID;
2948 + break;
2949 + case SB_USB:
2950 + class = PCI_CLASS_SERIAL;
2951 + subclass = PCI_SERIAL_USB;
2952 + progif = 0x10; /* OHCI */
2953 + core = BCM47XX_USB_ID;
2954 + break;
2955 + case SB_USB11H:
2956 + class = PCI_CLASS_SERIAL;
2957 + subclass = PCI_SERIAL_USB;
2958 + progif = 0x10; /* OHCI */
2959 + core = BCM47XX_USBH_ID;
2960 + break;
2961 + case SB_USB11D:
2962 + class = PCI_CLASS_SERIAL;
2963 + subclass = PCI_SERIAL_USB;
2964 + core = BCM47XX_USBD_ID;
2965 + break;
2966 + case SB_IPSEC:
2967 + class = PCI_CLASS_CRYPT;
2968 + subclass = PCI_CRYPT_NETWORK;
2969 + core = BCM47XX_IPSEC_ID;
2970 + break;
2971 + case SB_ROBO:
2972 + class = PCI_CLASS_NET;
2973 + subclass = PCI_NET_OTHER;
2974 + core = BCM47XX_ROBO_ID;
2975 + break;
2976 + case SB_EXTIF:
2977 + case SB_CC:
2978 + class = PCI_CLASS_MEMORY;
2979 + subclass = PCI_MEMORY_FLASH;
2980 + break;
2981 + case SB_D11:
2982 + class = PCI_CLASS_NET;
2983 + subclass = PCI_NET_OTHER;
2984 + /* Let an nvram variable override this */
2985 + sprintf(varname, "wl%did", wlidx);
2986 + wlidx++;
2987 + if ((core = getintvar(NULL, varname)) == 0) {
2988 + if (chip == BCM4712_DEVICE_ID) {
2989 + if (chippkg == BCM4712SMALL_PKG_ID)
2990 + core = BCM4306_D11G_ID;
2991 + else
2992 + core = BCM4306_D11DUAL_ID;
2993 + } else {
2994 + /* 4310 */
2995 + core = BCM4310_D11B_ID;
2996 + }
2997 + }
2998 + break;
2999 +
3000 + default:
3001 + class = subclass = progif = 0xff;
3002 + break;
3003 + }
3004 +
3005 + /* Supported translations */
3006 + cfg->vendor = htol16(vendor);
3007 + cfg->device = htol16(core);
3008 + cfg->rev_id = chiprev;
3009 + cfg->prog_if = progif;
3010 + cfg->sub_class = subclass;
3011 + cfg->base_class = class;
3012 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
3013 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
3014 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
3015 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
3016 + cfg->base[4] = 0;
3017 + cfg->base[5] = 0;
3018 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
3019 + cfg->header_type = PCI_HEADER_BRIDGE;
3020 + else
3021 + cfg->header_type = PCI_HEADER_NORMAL;
3022 + /* Save core interrupt flag */
3023 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
3024 + /* Default to MIPS shared interrupt 0 */
3025 + cfg->int_line = 0;
3026 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
3027 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
3028 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
3029 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
3030 + val = R_REG(&sb->sbipsflag);
3031 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
3032 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
3033 + break;
3034 + }
3035 + if (cfg->int_line > 4)
3036 + cfg->int_line = 0;
3037 + }
3038 + /* Emulated core */
3039 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
3040 + }
3041 +
3042 + sb_setcoreidx(sbh, coreidx);
3043 + return 0;
3044 +}
3045 +
3046 +int __init
3047 +sbpci_init(sb_t *sbh)
3048 +{
3049 + sbpci_init_pci(sbh);
3050 + sbpci_init_cores(sbh);
3051 + return 0;
3052 +}
3053 +
3054 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
3055 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
3056 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2006-10-15 23:29:14.000000000 +0200
3057 @@ -0,0 +1,2371 @@
3058 +/*
3059 + * Misc utility routines for accessing chip-specific features
3060 + * of the SiliconBackplane-based Broadcom chips.
3061 + *
3062 + * Copyright 2005, Broadcom Corporation
3063 + * All Rights Reserved.
3064 + *
3065 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3066 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3067 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3068 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3069 + * $Id$
3070 + */
3071 +
3072 +#include <typedefs.h>
3073 +#include <osl.h>
3074 +#include <sbutils.h>
3075 +#include <bcmutils.h>
3076 +#include <bcmdevs.h>
3077 +#include <sbconfig.h>
3078 +#include <sbchipc.h>
3079 +#include <sbpci.h>
3080 +#include <pcicfg.h>
3081 +#include <sbextif.h>
3082 +#include <bcmsrom.h>
3083 +
3084 +/* debug/trace */
3085 +#define SB_ERROR(args)
3086 +
3087 +
3088 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3089 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3090 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3091 +
3092 +/* misc sb info needed by some of the routines */
3093 +typedef struct sb_info {
3094 +
3095 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3096 +
3097 + void *osh; /* osl os handle */
3098 + void *sdh; /* bcmsdh handle */
3099 +
3100 + void *curmap; /* current regs va */
3101 + void *regs[SB_MAXCORES]; /* other regs va */
3102 +
3103 + uint curidx; /* current core index */
3104 + uint dev_coreid; /* the core provides driver functions */
3105 +
3106 + uint gpioidx; /* gpio control core index */
3107 + uint gpioid; /* gpio control coretype */
3108 +
3109 + uint numcores; /* # discovered cores */
3110 + uint coreid[SB_MAXCORES]; /* id of each core */
3111 +
3112 + void *intr_arg; /* interrupt callback function arg */
3113 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3114 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3115 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3116 +
3117 +} sb_info_t;
3118 +
3119 +/* local prototypes */
3120 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3121 + uint bustype, void *sdh, char **vars, int *varsz);
3122 +static void BCMINIT(sb_scan)(sb_info_t *si);
3123 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3124 +static uint _sb_coreidx(sb_info_t *si);
3125 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3126 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3127 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3128 +static int sb_pci_fixcfg(sb_info_t *si);
3129 +
3130 +/* delay needed between the mdio control/ mdiodata register data access */
3131 +#define PR28829_DELAY() OSL_DELAY(10)
3132 +
3133 +
3134 +/* global variable to indicate reservation/release of gpio's*/
3135 +static uint32 sb_gpioreservation = 0;
3136 +
3137 +#define SB_INFO(sbh) (sb_info_t*)sbh
3138 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3139 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3140 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3141 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3142 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3143 +#define BADIDX (SB_MAXCORES+1)
3144 +#define NOREV -1
3145 +
3146 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3147 +
3148 +/* sonicsrev */
3149 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3150 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3151 +
3152 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3153 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3154 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3155 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3156 +
3157 +/*
3158 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3159 + * after core switching to avoid invalid register accesss inside ISR.
3160 + */
3161 +#define INTR_OFF(si, intr_val) \
3162 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3163 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3164 +#define INTR_RESTORE(si, intr_val) \
3165 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3166 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3167 +
3168 +/* dynamic clock control defines */
3169 +#define LPOMINFREQ 25000 /* low power oscillator min */
3170 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3171 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3172 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3173 +#define PCIMINFREQ 25000000 /* 25 MHz */
3174 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3175 +
3176 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3177 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3178 +
3179 +#define MIN_DUMPBUFLEN 32 /* debug */
3180 +
3181 +/* GPIO Based LED powersave defines */
3182 +#define DEFAULT_GPIO_ONTIME 10
3183 +#define DEFAULT_GPIO_OFFTIME 90
3184 +
3185 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3186 +
3187 +static uint32
3188 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3189 +{
3190 + uint32 val = R_REG(sbr);
3191 +
3192 + return (val);
3193 +}
3194 +
3195 +static void
3196 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3197 +{
3198 + W_REG(sbr, v);
3199 +}
3200 +
3201 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3202 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3203 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3204 +
3205 +/* global kernel resource */
3206 +static sb_info_t ksi;
3207 +
3208 +/* generic kernel variant of sb_attach() */
3209 +sb_t *
3210 +BCMINITFN(sb_kattach)()
3211 +{
3212 + uint32 *regs;
3213 +
3214 + if (ksi.curmap == NULL) {
3215 + uint32 cid;
3216 +
3217 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3218 + cid = R_REG((uint32 *)regs);
3219 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3220 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3221 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3222 + uint32 *scc, val;
3223 +
3224 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3225 + val = R_REG(scc);
3226 + SB_ERROR((" initial scc = 0x%x\n", val));
3227 + val |= SCC_SS_XTAL;
3228 + W_REG(scc, val);
3229 + }
3230 +
3231 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3232 + SB_BUS, NULL, NULL, NULL) == NULL) {
3233 + return NULL;
3234 + }
3235 + }
3236 +
3237 + return (sb_t *)&ksi;
3238 +}
3239 +#endif
3240 +
3241 +static sb_info_t *
3242 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3243 + uint bustype, void *sdh, char **vars, int *varsz)
3244 +{
3245 + uint origidx;
3246 + chipcregs_t *cc;
3247 + sbconfig_t *sb;
3248 + uint32 w;
3249 +
3250 + ASSERT(GOODREGS(regs));
3251 +
3252 + bzero((uchar*)si, sizeof (sb_info_t));
3253 +
3254 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3255 +
3256 + si->osh = osh;
3257 + si->curmap = regs;
3258 + si->sdh = sdh;
3259 +
3260 + /* check to see if we are a sb core mimic'ing a pci core */
3261 + if (bustype == PCI_BUS) {
3262 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3263 + bustype = SB_BUS;
3264 + else
3265 + bustype = PCI_BUS;
3266 + }
3267 +
3268 + si->sb.bustype = bustype;
3269 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3270 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3271 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3272 + return NULL;
3273 + }
3274 +
3275 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3276 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3277 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3278 +
3279 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3280 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3281 + if (!GOODCOREADDR(w))
3282 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3283 + }
3284 +
3285 + /* initialize current core index value */
3286 + si->curidx = _sb_coreidx(si);
3287 +
3288 + if (si->curidx == BADIDX) {
3289 + SB_ERROR(("sb_doattach: bad core index\n"));
3290 + return NULL;
3291 + }
3292 +
3293 + /* get sonics backplane revision */
3294 + sb = REGS2SB(si->curmap);
3295 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3296 +
3297 + /* keep and reuse the initial register mapping */
3298 + origidx = si->curidx;
3299 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3300 + si->regs[origidx] = regs;
3301 +
3302 + /* is core-0 a chipcommon core? */
3303 + si->numcores = 1;
3304 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3305 + if (sb_coreid(&si->sb) != SB_CC)
3306 + cc = NULL;
3307 +
3308 + /* determine chip id and rev */
3309 + if (cc) {
3310 + /* chip common core found! */
3311 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3312 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3313 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3314 + } else {
3315 + /* no chip common core -- must convert device id to chip id */
3316 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3317 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3318 + sb_setcoreidx(&si->sb, origidx);
3319 + return NULL;
3320 + }
3321 + }
3322 +
3323 + /* get chipcommon rev */
3324 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3325 +
3326 + /* determine numcores */
3327 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3328 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3329 + else
3330 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3331 +
3332 + /* return to original core */
3333 + sb_setcoreidx(&si->sb, origidx);
3334 +
3335 + /* sanity checks */
3336 + ASSERT(si->sb.chip);
3337 +
3338 + /* scan for cores */
3339 + BCMINIT(sb_scan)(si);
3340 +
3341 + /* fixup necessary chip/core configurations */
3342 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3343 + if (sb_pci_fixcfg(si)) {
3344 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3345 + return NULL;
3346 + }
3347 + }
3348 +
3349 + /* srom_var_init() depends on sb_scan() info */
3350 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3351 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3352 + return (NULL);
3353 + }
3354 +
3355 + if (cc == NULL) {
3356 + /*
3357 + * The chip revision number is hardwired into all
3358 + * of the pci function config rev fields and is
3359 + * independent from the individual core revision numbers.
3360 + * For example, the "A0" silicon of each chip is chip rev 0.
3361 + */
3362 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3363 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3364 + si->sb.chiprev = w & 0xff;
3365 + } else
3366 + si->sb.chiprev = 0;
3367 + }
3368 +
3369 + /* gpio control core is required */
3370 + if (!GOODIDX(si->gpioidx)) {
3371 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3372 + return NULL;
3373 + }
3374 +
3375 + /* get boardtype and boardrev */
3376 + switch (BUSTYPE(si->sb.bustype)) {
3377 + case PCI_BUS:
3378 + /* do a pci config read to get subsystem id and subvendor id */
3379 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3380 + si->sb.boardvendor = w & 0xffff;
3381 + si->sb.boardtype = (w >> 16) & 0xffff;
3382 + break;
3383 +
3384 + case SB_BUS:
3385 + case JTAG_BUS:
3386 + si->sb.boardvendor = VENDOR_BROADCOM;
3387 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3388 + si->sb.boardtype = 0xffff;
3389 + break;
3390 + }
3391 +
3392 + if (si->sb.boardtype == 0) {
3393 + SB_ERROR(("sb_doattach: unknown board type\n"));
3394 + ASSERT(si->sb.boardtype);
3395 + }
3396 +
3397 + /* setup the GPIO based LED powersave register */
3398 + if (si->sb.ccrev >= 16) {
3399 + w = getintvar(*vars, "gpiotimerval");
3400 + if (!w)
3401 + w = DEFAULT_GPIOTIMERVAL;
3402 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3403 + }
3404 +
3405 +
3406 + return (si);
3407 +}
3408 +
3409 +uint
3410 +sb_coreid(sb_t *sbh)
3411 +{
3412 + sb_info_t *si;
3413 + sbconfig_t *sb;
3414 +
3415 + si = SB_INFO(sbh);
3416 + sb = REGS2SB(si->curmap);
3417 +
3418 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3419 +}
3420 +
3421 +uint
3422 +sb_coreidx(sb_t *sbh)
3423 +{
3424 + sb_info_t *si;
3425 +
3426 + si = SB_INFO(sbh);
3427 + return (si->curidx);
3428 +}
3429 +
3430 +/* return current index of core */
3431 +static uint
3432 +_sb_coreidx(sb_info_t *si)
3433 +{
3434 + sbconfig_t *sb;
3435 + uint32 sbaddr = 0;
3436 +
3437 + ASSERT(si);
3438 +
3439 + switch (BUSTYPE(si->sb.bustype)) {
3440 + case SB_BUS:
3441 + sb = REGS2SB(si->curmap);
3442 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3443 + break;
3444 +
3445 + case PCI_BUS:
3446 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3447 + break;
3448 +
3449 +#ifdef BCMJTAG
3450 + case JTAG_BUS:
3451 + sbaddr = (uint32)si->curmap;
3452 + break;
3453 +#endif /* BCMJTAG */
3454 +
3455 + default:
3456 + ASSERT(0);
3457 + }
3458 +
3459 + if (!GOODCOREADDR(sbaddr))
3460 + return BADIDX;
3461 +
3462 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3463 +}
3464 +
3465 +uint
3466 +sb_corevendor(sb_t *sbh)
3467 +{
3468 + sb_info_t *si;
3469 + sbconfig_t *sb;
3470 +
3471 + si = SB_INFO(sbh);
3472 + sb = REGS2SB(si->curmap);
3473 +
3474 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3475 +}
3476 +
3477 +uint
3478 +sb_corerev(sb_t *sbh)
3479 +{
3480 + sb_info_t *si;
3481 + sbconfig_t *sb;
3482 + uint sbidh;
3483 +
3484 + si = SB_INFO(sbh);
3485 + sb = REGS2SB(si->curmap);
3486 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3487 +
3488 + return (SBCOREREV(sbidh));
3489 +}
3490 +
3491 +void *
3492 +sb_osh(sb_t *sbh)
3493 +{
3494 + sb_info_t *si;
3495 +
3496 + si = SB_INFO(sbh);
3497 + return si->osh;
3498 +}
3499 +
3500 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3501 +
3502 +/* set/clear sbtmstatelow core-specific flags */
3503 +uint32
3504 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3505 +{
3506 + sb_info_t *si;
3507 + sbconfig_t *sb;
3508 + uint32 w;
3509 +
3510 + si = SB_INFO(sbh);
3511 + sb = REGS2SB(si->curmap);
3512 +
3513 + ASSERT((val & ~mask) == 0);
3514 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3515 +
3516 + /* mask and set */
3517 + if (mask || val) {
3518 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3519 + W_SBREG(si, &sb->sbtmstatelow, w);
3520 + }
3521 +
3522 + /* return the new value */
3523 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3524 +}
3525 +
3526 +/* set/clear sbtmstatehigh core-specific flags */
3527 +uint32
3528 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3529 +{
3530 + sb_info_t *si;
3531 + sbconfig_t *sb;
3532 + uint32 w;
3533 +
3534 + si = SB_INFO(sbh);
3535 + sb = REGS2SB(si->curmap);
3536 +
3537 + ASSERT((val & ~mask) == 0);
3538 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3539 +
3540 + /* mask and set */
3541 + if (mask || val) {
3542 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3543 + W_SBREG(si, &sb->sbtmstatehigh, w);
3544 + }
3545 +
3546 + /* return the new value */
3547 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3548 +}
3549 +
3550 +/* caller needs to take care of core-specific bist hazards */
3551 +int
3552 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3553 +{
3554 + uint32 sblo;
3555 + uint coreidx;
3556 + sb_info_t *si;
3557 + int result = 0;
3558 +
3559 + si = SB_INFO(sbh);
3560 +
3561 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3562 + if (!GOODIDX(coreidx))
3563 + result = BCME_ERROR;
3564 + else {
3565 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3566 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3567 +
3568 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3569 +
3570 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3571 + result = BCME_ERROR;
3572 +
3573 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3574 + }
3575 +
3576 + return result;
3577 +}
3578 +
3579 +bool
3580 +sb_iscoreup(sb_t *sbh)
3581 +{
3582 + sb_info_t *si;
3583 + sbconfig_t *sb;
3584 +
3585 + si = SB_INFO(sbh);
3586 + sb = REGS2SB(si->curmap);
3587 +
3588 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3589 +}
3590 +
3591 +/*
3592 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3593 + * switch back to the original core, and return the new value.
3594 + */
3595 +static uint
3596 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3597 +{
3598 + uint origidx;
3599 + uint32 *r;
3600 + uint w;
3601 + uint intr_val = 0;
3602 +
3603 + ASSERT(GOODIDX(coreidx));
3604 + ASSERT(regoff < SB_CORE_SIZE);
3605 + ASSERT((val & ~mask) == 0);
3606 +
3607 + INTR_OFF(si, intr_val);
3608 +
3609 + /* save current core index */
3610 + origidx = sb_coreidx(&si->sb);
3611 +
3612 + /* switch core */
3613 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3614 +
3615 + /* mask and set */
3616 + if (mask || val) {
3617 + if (regoff >= SBCONFIGOFF) {
3618 + w = (R_SBREG(si, r) & ~mask) | val;
3619 + W_SBREG(si, r, w);
3620 + } else {
3621 + w = (R_REG(r) & ~mask) | val;
3622 + W_REG(r, w);
3623 + }
3624 + }
3625 +
3626 + /* readback */
3627 + if (regoff >= SBCONFIGOFF)
3628 + w = R_SBREG(si, r);
3629 + else
3630 + w = R_REG(r);
3631 +
3632 + /* restore core index */
3633 + if (origidx != coreidx)
3634 + sb_setcoreidx(&si->sb, origidx);
3635 +
3636 + INTR_RESTORE(si, intr_val);
3637 + return (w);
3638 +}
3639 +
3640 +#define DWORD_ALIGN(x) (x & ~(0x03))
3641 +#define BYTE_POS(x) (x & 0x3)
3642 +#define WORD_POS(x) (x & 0x1)
3643 +
3644 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3645 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3646 +
3647 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3648 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3649 +
3650 +#define read_pci_cfg_byte(a) \
3651 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3652 +
3653 +#define read_pci_cfg_write(a) \
3654 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3655 +
3656 +
3657 +/* scan the sb enumerated space to identify all cores */
3658 +static void
3659 +BCMINITFN(sb_scan)(sb_info_t *si)
3660 +{
3661 + uint origidx;
3662 + uint i;
3663 + bool pci;
3664 + uint pciidx;
3665 + uint pcirev;
3666 +
3667 +
3668 +
3669 + /* numcores should already be set */
3670 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3671 +
3672 + /* save current core index */
3673 + origidx = sb_coreidx(&si->sb);
3674 +
3675 + si->sb.buscorerev = NOREV;
3676 + si->sb.buscoreidx = BADIDX;
3677 +
3678 + si->gpioidx = BADIDX;
3679 +
3680 + pci = FALSE;
3681 + pcirev = NOREV;
3682 + pciidx = BADIDX;
3683 +
3684 + for (i = 0; i < si->numcores; i++) {
3685 + sb_setcoreidx(&si->sb, i);
3686 + si->coreid[i] = sb_coreid(&si->sb);
3687 +
3688 + if (si->coreid[i] == SB_PCI) {
3689 + pciidx = i;
3690 + pcirev = sb_corerev(&si->sb);
3691 + pci = TRUE;
3692 + }
3693 + }
3694 + if (pci) {
3695 + si->sb.buscoretype = SB_PCI;
3696 + si->sb.buscorerev = pcirev;
3697 + si->sb.buscoreidx = pciidx;
3698 + }
3699 +
3700 + /*
3701 + * Find the gpio "controlling core" type and index.
3702 + * Precedence:
3703 + * - if there's a chip common core - use that
3704 + * - else if there's a pci core (rev >= 2) - use that
3705 + * - else there had better be an extif core (4710 only)
3706 + */
3707 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3708 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3709 + si->gpioid = SB_CC;
3710 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3711 + si->gpioidx = si->sb.buscoreidx;
3712 + si->gpioid = SB_PCI;
3713 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3714 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3715 + si->gpioid = SB_EXTIF;
3716 + } else
3717 + ASSERT(si->gpioidx != BADIDX);
3718 +
3719 + /* return to original core index */
3720 + sb_setcoreidx(&si->sb, origidx);
3721 +}
3722 +
3723 +/* may be called with core in reset */
3724 +void
3725 +sb_detach(sb_t *sbh)
3726 +{
3727 + sb_info_t *si;
3728 + uint idx;
3729 +
3730 + si = SB_INFO(sbh);
3731 +
3732 + if (si == NULL)
3733 + return;
3734 +
3735 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3736 + for (idx = 0; idx < SB_MAXCORES; idx++)
3737 + if (si->regs[idx]) {
3738 + REG_UNMAP(si->regs[idx]);
3739 + si->regs[idx] = NULL;
3740 + }
3741 +
3742 + if (si != &ksi)
3743 + MFREE(si->osh, si, sizeof (sb_info_t));
3744 +}
3745 +
3746 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3747 +static uint
3748 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3749 +{
3750 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3751 + return (BCM4710_DEVICE_ID);
3752 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3753 + return (BCM4402_DEVICE_ID);
3754 + if (pcidev == BCM4401_ENET_ID)
3755 + return (BCM4402_DEVICE_ID);
3756 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3757 + return (BCM4307_DEVICE_ID);
3758 + if (pcidev == BCM4301_DEVICE_ID)
3759 + return (BCM4301_DEVICE_ID);
3760 +
3761 + return (0);
3762 +}
3763 +
3764 +/* convert chip number to number of i/o cores */
3765 +static uint
3766 +BCMINITFN(sb_chip2numcores)(uint chip)
3767 +{
3768 + if (chip == BCM4710_DEVICE_ID)
3769 + return (9);
3770 + if (chip == BCM4402_DEVICE_ID)
3771 + return (3);
3772 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3773 + return (5);
3774 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3775 + return (6);
3776 + if (chip == BCM4704_DEVICE_ID)
3777 + return (9);
3778 + if (chip == BCM5365_DEVICE_ID)
3779 + return (7);
3780 +
3781 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3782 + ASSERT(0);
3783 + return (1);
3784 +}
3785 +
3786 +/* return index of coreid or BADIDX if not found */
3787 +static uint
3788 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3789 +{
3790 + uint found;
3791 + uint i;
3792 +
3793 + found = 0;
3794 +
3795 + for (i = 0; i < si->numcores; i++)
3796 + if (si->coreid[i] == coreid) {
3797 + if (found == coreunit)
3798 + return (i);
3799 + found++;
3800 + }
3801 +
3802 + return (BADIDX);
3803 +}
3804 +
3805 +/*
3806 + * this function changes logical "focus" to the indiciated core,
3807 + * must be called with interrupt off.
3808 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3809 + */
3810 +void*
3811 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3812 +{
3813 + sb_info_t *si;
3814 + uint32 sbaddr;
3815 +
3816 + si = SB_INFO(sbh);
3817 +
3818 + if (coreidx >= si->numcores)
3819 + return (NULL);
3820 +
3821 + /*
3822 + * If the user has provided an interrupt mask enabled function,
3823 + * then assert interrupts are disabled before switching the core.
3824 + */
3825 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3826 +
3827 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3828 +
3829 + switch (BUSTYPE(si->sb.bustype)) {
3830 + case SB_BUS:
3831 + /* map new one */
3832 + if (!si->regs[coreidx]) {
3833 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3834 + ASSERT(GOODREGS(si->regs[coreidx]));
3835 + }
3836 + si->curmap = si->regs[coreidx];
3837 + break;
3838 +
3839 + case PCI_BUS:
3840 + /* point bar0 window */
3841 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3842 + break;
3843 +
3844 +#ifdef BCMJTAG
3845 + case JTAG_BUS:
3846 + /* map new one */
3847 + if (!si->regs[coreidx]) {
3848 + si->regs[coreidx] = (void *)sbaddr;
3849 + ASSERT(GOODREGS(si->regs[coreidx]));
3850 + }
3851 + si->curmap = si->regs[coreidx];
3852 + break;
3853 +#endif /* BCMJTAG */
3854 + }
3855 +
3856 + si->curidx = coreidx;
3857 +
3858 + return (si->curmap);
3859 +}
3860 +
3861 +/*
3862 + * this function changes logical "focus" to the indiciated core,
3863 + * must be called with interrupt off.
3864 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3865 + */
3866 +void*
3867 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3868 +{
3869 + sb_info_t *si;
3870 + uint idx;
3871 +
3872 + si = SB_INFO(sbh);
3873 + idx = sb_findcoreidx(si, coreid, coreunit);
3874 + if (!GOODIDX(idx))
3875 + return (NULL);
3876 +
3877 + return (sb_setcoreidx(sbh, idx));
3878 +}
3879 +
3880 +/* return chip number */
3881 +uint
3882 +BCMINITFN(sb_chip)(sb_t *sbh)
3883 +{
3884 + sb_info_t *si;
3885 +
3886 + si = SB_INFO(sbh);
3887 + return (si->sb.chip);
3888 +}
3889 +
3890 +/* return chip revision number */
3891 +uint
3892 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3893 +{
3894 + sb_info_t *si;
3895 +
3896 + si = SB_INFO(sbh);
3897 + return (si->sb.chiprev);
3898 +}
3899 +
3900 +/* return chip common revision number */
3901 +uint
3902 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3903 +{
3904 + sb_info_t *si;
3905 +
3906 + si = SB_INFO(sbh);
3907 + return (si->sb.ccrev);
3908 +}
3909 +
3910 +/* return chip package option */
3911 +uint
3912 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3913 +{
3914 + sb_info_t *si;
3915 +
3916 + si = SB_INFO(sbh);
3917 + return (si->sb.chippkg);
3918 +}
3919 +
3920 +/* return PCI core rev. */
3921 +uint
3922 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3923 +{
3924 + sb_info_t *si;
3925 +
3926 + si = SB_INFO(sbh);
3927 + return (si->sb.buscorerev);
3928 +}
3929 +
3930 +bool
3931 +BCMINITFN(sb_war16165)(sb_t *sbh)
3932 +{
3933 + sb_info_t *si;
3934 +
3935 + si = SB_INFO(sbh);
3936 +
3937 + return (PCI(si) && (si->sb.buscorerev <= 10));
3938 +}
3939 +
3940 +/* return board vendor id */
3941 +uint
3942 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3943 +{
3944 + sb_info_t *si;
3945 +
3946 + si = SB_INFO(sbh);
3947 + return (si->sb.boardvendor);
3948 +}
3949 +
3950 +/* return boardtype */
3951 +uint
3952 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3953 +{
3954 + sb_info_t *si;
3955 + char *var;
3956 +
3957 + si = SB_INFO(sbh);
3958 +
3959 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3960 + /* boardtype format is a hex string */
3961 + si->sb.boardtype = getintvar(NULL, "boardtype");
3962 +
3963 + /* backward compatibility for older boardtype string format */
3964 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3965 + if (!strcmp(var, "bcm94710dev"))
3966 + si->sb.boardtype = BCM94710D_BOARD;
3967 + else if (!strcmp(var, "bcm94710ap"))
3968 + si->sb.boardtype = BCM94710AP_BOARD;
3969 + else if (!strcmp(var, "bu4710"))
3970 + si->sb.boardtype = BU4710_BOARD;
3971 + else if (!strcmp(var, "bcm94702mn"))
3972 + si->sb.boardtype = BCM94702MN_BOARD;
3973 + else if (!strcmp(var, "bcm94710r1"))
3974 + si->sb.boardtype = BCM94710R1_BOARD;
3975 + else if (!strcmp(var, "bcm94710r4"))
3976 + si->sb.boardtype = BCM94710R4_BOARD;
3977 + else if (!strcmp(var, "bcm94702cpci"))
3978 + si->sb.boardtype = BCM94702CPCI_BOARD;
3979 + else if (!strcmp(var, "bcm95380_rr"))
3980 + si->sb.boardtype = BCM95380RR_BOARD;
3981 + }
3982 + }
3983 +
3984 + return (si->sb.boardtype);
3985 +}
3986 +
3987 +/* return bus type of sbh device */
3988 +uint
3989 +sb_bus(sb_t *sbh)
3990 +{
3991 + sb_info_t *si;
3992 +
3993 + si = SB_INFO(sbh);
3994 + return (si->sb.bustype);
3995 +}
3996 +
3997 +/* return bus core type */
3998 +uint
3999 +sb_buscoretype(sb_t *sbh)
4000 +{
4001 + sb_info_t *si;
4002 +
4003 + si = SB_INFO(sbh);
4004 +
4005 + return (si->sb.buscoretype);
4006 +}
4007 +
4008 +/* return bus core revision */
4009 +uint
4010 +sb_buscorerev(sb_t *sbh)
4011 +{
4012 + sb_info_t *si;
4013 + si = SB_INFO(sbh);
4014 +
4015 + return (si->sb.buscorerev);
4016 +}
4017 +
4018 +/* return list of found cores */
4019 +uint
4020 +sb_corelist(sb_t *sbh, uint coreid[])
4021 +{
4022 + sb_info_t *si;
4023 +
4024 + si = SB_INFO(sbh);
4025 +
4026 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
4027 + return (si->numcores);
4028 +}
4029 +
4030 +/* return current register mapping */
4031 +void *
4032 +sb_coreregs(sb_t *sbh)
4033 +{
4034 + sb_info_t *si;
4035 +
4036 + si = SB_INFO(sbh);
4037 + ASSERT(GOODREGS(si->curmap));
4038 +
4039 + return (si->curmap);
4040 +}
4041 +
4042 +
4043 +/* do buffered registers update */
4044 +void
4045 +sb_commit(sb_t *sbh)
4046 +{
4047 + sb_info_t *si;
4048 + uint origidx;
4049 + uint intr_val = 0;
4050 +
4051 + si = SB_INFO(sbh);
4052 +
4053 + origidx = si->curidx;
4054 + ASSERT(GOODIDX(origidx));
4055 +
4056 + INTR_OFF(si, intr_val);
4057 +
4058 + /* switch over to chipcommon core if there is one, else use pci */
4059 + if (si->sb.ccrev != NOREV) {
4060 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4061 +
4062 + /* do the buffer registers update */
4063 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4064 + W_REG(&ccregs->broadcastdata, 0x0);
4065 + } else if (PCI(si)) {
4066 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4067 +
4068 + /* do the buffer registers update */
4069 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4070 + W_REG(&pciregs->bcastdata, 0x0);
4071 + } else
4072 + ASSERT(0);
4073 +
4074 + /* restore core index */
4075 + sb_setcoreidx(sbh, origidx);
4076 + INTR_RESTORE(si, intr_val);
4077 +}
4078 +
4079 +/* reset and re-enable a core */
4080 +void
4081 +sb_core_reset(sb_t *sbh, uint32 bits)
4082 +{
4083 + sb_info_t *si;
4084 + sbconfig_t *sb;
4085 + volatile uint32 dummy;
4086 +
4087 + si = SB_INFO(sbh);
4088 + ASSERT(GOODREGS(si->curmap));
4089 + sb = REGS2SB(si->curmap);
4090 +
4091 + /*
4092 + * Must do the disable sequence first to work for arbitrary current core state.
4093 + */
4094 + sb_core_disable(sbh, bits);
4095 +
4096 + /*
4097 + * Now do the initialization sequence.
4098 + */
4099 +
4100 + /* set reset while enabling the clock and forcing them on throughout the core */
4101 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4102 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4103 + OSL_DELAY(1);
4104 +
4105 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4106 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4107 + }
4108 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4109 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4110 + }
4111 +
4112 + /* clear reset and allow it to propagate throughout the core */
4113 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4114 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4115 + OSL_DELAY(1);
4116 +
4117 + /* leave clock enabled */
4118 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4119 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4120 + OSL_DELAY(1);
4121 +}
4122 +
4123 +void
4124 +sb_core_tofixup(sb_t *sbh)
4125 +{
4126 + sb_info_t *si;
4127 + sbconfig_t *sb;
4128 +
4129 + si = SB_INFO(sbh);
4130 +
4131 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4132 + return;
4133 +
4134 + ASSERT(GOODREGS(si->curmap));
4135 + sb = REGS2SB(si->curmap);
4136 +
4137 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4138 + SET_SBREG(si, &sb->sbimconfiglow,
4139 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4140 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4141 + } else {
4142 + if (sb_coreid(sbh) == SB_PCI) {
4143 + SET_SBREG(si, &sb->sbimconfiglow,
4144 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4145 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4146 + } else {
4147 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4148 + }
4149 + }
4150 +
4151 + sb_commit(sbh);
4152 +}
4153 +
4154 +/*
4155 + * Set the initiator timeout for the "master core".
4156 + * The master core is defined to be the core in control
4157 + * of the chip and so it issues accesses to non-memory
4158 + * locations (Because of dma *any* core can access memeory).
4159 + *
4160 + * The routine uses the bus to decide who is the master:
4161 + * SB_BUS => mips
4162 + * JTAG_BUS => chipc
4163 + * PCI_BUS => pci
4164 + *
4165 + * This routine exists so callers can disable initiator
4166 + * timeouts so accesses to very slow devices like otp
4167 + * won't cause an abort. The routine allows arbitrary
4168 + * settings of the service and request timeouts, though.
4169 + *
4170 + * Returns the timeout state before changing it or -1
4171 + * on error.
4172 + */
4173 +
4174 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4175 +
4176 +uint32
4177 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4178 +{
4179 + sb_info_t *si;
4180 + uint origidx, idx;
4181 + uint intr_val = 0;
4182 + uint32 tmp, ret = 0xffffffff;
4183 + sbconfig_t *sb;
4184 +
4185 + si = SB_INFO(sbh);
4186 +
4187 + if ((to & ~TO_MASK) != 0)
4188 + return ret;
4189 +
4190 + /* Figure out the master core */
4191 + idx = BADIDX;
4192 + switch (BUSTYPE(si->sb.bustype)) {
4193 + case PCI_BUS:
4194 + idx = si->sb.buscoreidx;
4195 + break;
4196 + case JTAG_BUS:
4197 + idx = SB_CC_IDX;
4198 + break;
4199 + case SB_BUS:
4200 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4201 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4202 + break;
4203 + default:
4204 + ASSERT(0);
4205 + }
4206 + if (idx == BADIDX)
4207 + return ret;
4208 +
4209 + INTR_OFF(si, intr_val);
4210 + origidx = sb_coreidx(sbh);
4211 +
4212 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4213 +
4214 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4215 + ret = tmp & TO_MASK;
4216 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4217 +
4218 + sb_commit(sbh);
4219 + sb_setcoreidx(sbh, origidx);
4220 + INTR_RESTORE(si, intr_val);
4221 + return ret;
4222 +}
4223 +
4224 +void
4225 +sb_core_disable(sb_t *sbh, uint32 bits)
4226 +{
4227 + sb_info_t *si;
4228 + volatile uint32 dummy;
4229 + uint32 rej;
4230 + sbconfig_t *sb;
4231 +
4232 + si = SB_INFO(sbh);
4233 +
4234 + ASSERT(GOODREGS(si->curmap));
4235 + sb = REGS2SB(si->curmap);
4236 +
4237 + /* if core is already in reset, just return */
4238 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4239 + return;
4240 +
4241 + /* reject value changed between sonics 2.2 and 2.3 */
4242 + if (si->sb.sonicsrev == SONICS_2_2)
4243 + rej = (1 << SBTML_REJ_SHIFT);
4244 + else
4245 + rej = (2 << SBTML_REJ_SHIFT);
4246 +
4247 + /* if clocks are not enabled, put into reset and return */
4248 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4249 + goto disable;
4250 +
4251 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4252 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4253 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4254 + OSL_DELAY(1);
4255 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4256 +
4257 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4258 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4259 + dummy = R_SBREG(si, &sb->sbimstate);
4260 + OSL_DELAY(1);
4261 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4262 + }
4263 +
4264 + /* set reset and reject while enabling the clocks */
4265 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4266 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4267 + OSL_DELAY(10);
4268 +
4269 + /* don't forget to clear the initiator reject bit */
4270 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4271 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4272 +
4273 +disable:
4274 + /* leave reset and reject asserted */
4275 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4276 + OSL_DELAY(1);
4277 +}
4278 +
4279 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4280 +void
4281 +sb_watchdog(sb_t *sbh, uint ticks)
4282 +{
4283 + sb_info_t *si = SB_INFO(sbh);
4284 +
4285 + /* instant NMI */
4286 + switch (si->gpioid) {
4287 + case SB_CC:
4288 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4289 + break;
4290 + case SB_EXTIF:
4291 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4292 + break;
4293 + }
4294 +}
4295 +
4296 +
4297 +/*
4298 + * Configure the pci core for pci client (NIC) action
4299 + * coremask is the bitvec of cores by index to be enabled.
4300 + */
4301 +void
4302 +sb_pci_setup(sb_t *sbh, uint coremask)
4303 +{
4304 + sb_info_t *si;
4305 + sbconfig_t *sb;
4306 + sbpciregs_t *pciregs;
4307 + uint32 sbflag;
4308 + uint32 w;
4309 + uint idx;
4310 +
4311 + si = SB_INFO(sbh);
4312 +
4313 + /* if not pci bus, we're done */
4314 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4315 + return;
4316 +
4317 + ASSERT(PCI(si));
4318 + ASSERT(si->sb.buscoreidx != BADIDX);
4319 +
4320 + /* get current core index */
4321 + idx = si->curidx;
4322 +
4323 + /* we interrupt on this backplane flag number */
4324 + ASSERT(GOODREGS(si->curmap));
4325 + sb = REGS2SB(si->curmap);
4326 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4327 +
4328 + /* switch over to pci core */
4329 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4330 + sb = REGS2SB(pciregs);
4331 +
4332 + /*
4333 + * Enable sb->pci interrupts. Assume
4334 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4335 + */
4336 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4337 + /* pci config write to set this core bit in PCIIntMask */
4338 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4339 + w |= (coremask << PCI_SBIM_SHIFT);
4340 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4341 + } else {
4342 + /* set sbintvec bit for our flag number */
4343 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4344 + }
4345 +
4346 + if (PCI(si)) {
4347 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4348 + if (si->sb.buscorerev >= 11)
4349 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4350 + if (si->sb.buscorerev < 5) {
4351 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4352 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4353 + sb_commit(sbh);
4354 + }
4355 + }
4356 +
4357 + /* switch back to previous core */
4358 + sb_setcoreidx(sbh, idx);
4359 +}
4360 +
4361 +uint32
4362 +sb_base(uint32 admatch)
4363 +{
4364 + uint32 base;
4365 + uint type;
4366 +
4367 + type = admatch & SBAM_TYPE_MASK;
4368 + ASSERT(type < 3);
4369 +
4370 + base = 0;
4371 +
4372 + if (type == 0) {
4373 + base = admatch & SBAM_BASE0_MASK;
4374 + } else if (type == 1) {
4375 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4376 + base = admatch & SBAM_BASE1_MASK;
4377 + } else if (type == 2) {
4378 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4379 + base = admatch & SBAM_BASE2_MASK;
4380 + }
4381 +
4382 + return (base);
4383 +}
4384 +
4385 +uint32
4386 +sb_size(uint32 admatch)
4387 +{
4388 + uint32 size;
4389 + uint type;
4390 +
4391 + type = admatch & SBAM_TYPE_MASK;
4392 + ASSERT(type < 3);
4393 +
4394 + size = 0;
4395 +
4396 + if (type == 0) {
4397 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4398 + } else if (type == 1) {
4399 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4400 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4401 + } else if (type == 2) {
4402 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4403 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4404 + }
4405 +
4406 + return (size);
4407 +}
4408 +
4409 +/* return the core-type instantiation # of the current core */
4410 +uint
4411 +sb_coreunit(sb_t *sbh)
4412 +{
4413 + sb_info_t *si;
4414 + uint idx;
4415 + uint coreid;
4416 + uint coreunit;
4417 + uint i;
4418 +
4419 + si = SB_INFO(sbh);
4420 + coreunit = 0;
4421 +
4422 + idx = si->curidx;
4423 +
4424 + ASSERT(GOODREGS(si->curmap));
4425 + coreid = sb_coreid(sbh);
4426 +
4427 + /* count the cores of our type */
4428 + for (i = 0; i < idx; i++)
4429 + if (si->coreid[i] == coreid)
4430 + coreunit++;
4431 +
4432 + return (coreunit);
4433 +}
4434 +
4435 +static INLINE uint32
4436 +factor6(uint32 x)
4437 +{
4438 + switch (x) {
4439 + case CC_F6_2: return 2;
4440 + case CC_F6_3: return 3;
4441 + case CC_F6_4: return 4;
4442 + case CC_F6_5: return 5;
4443 + case CC_F6_6: return 6;
4444 + case CC_F6_7: return 7;
4445 + default: return 0;
4446 + }
4447 +}
4448 +
4449 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4450 +uint32
4451 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4452 +{
4453 + uint32 n1, n2, clock, m1, m2, m3, mc;
4454 +
4455 + n1 = n & CN_N1_MASK;
4456 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4457 +
4458 + if (pll_type == PLL_TYPE6) {
4459 + if (m & CC_T6_MMASK)
4460 + return CC_T6_M1;
4461 + else
4462 + return CC_T6_M0;
4463 + } else if ((pll_type == PLL_TYPE1) ||
4464 + (pll_type == PLL_TYPE3) ||
4465 + (pll_type == PLL_TYPE4) ||
4466 + (pll_type == PLL_TYPE7)) {
4467 + n1 = factor6(n1);
4468 + n2 += CC_F5_BIAS;
4469 + } else if (pll_type == PLL_TYPE2) {
4470 + n1 += CC_T2_BIAS;
4471 + n2 += CC_T2_BIAS;
4472 + ASSERT((n1 >= 2) && (n1 <= 7));
4473 + ASSERT((n2 >= 5) && (n2 <= 23));
4474 + } else if (pll_type == PLL_TYPE5) {
4475 + return (100000000);
4476 + } else
4477 + ASSERT(0);
4478 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4479 + if ((pll_type == PLL_TYPE3) ||
4480 + (pll_type == PLL_TYPE7)) {
4481 + clock = CC_CLOCK_BASE2 * n1 * n2;
4482 + }
4483 + else
4484 + clock = CC_CLOCK_BASE1 * n1 * n2;
4485 +
4486 + if (clock == 0)
4487 + return 0;
4488 +
4489 + m1 = m & CC_M1_MASK;
4490 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4491 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4492 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4493 +
4494 + if ((pll_type == PLL_TYPE1) ||
4495 + (pll_type == PLL_TYPE3) ||
4496 + (pll_type == PLL_TYPE4) ||
4497 + (pll_type == PLL_TYPE7)) {
4498 + m1 = factor6(m1);
4499 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4500 + m2 += CC_F5_BIAS;
4501 + else
4502 + m2 = factor6(m2);
4503 + m3 = factor6(m3);
4504 +
4505 + switch (mc) {
4506 + case CC_MC_BYPASS: return (clock);
4507 + case CC_MC_M1: return (clock / m1);
4508 + case CC_MC_M1M2: return (clock / (m1 * m2));
4509 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4510 + case CC_MC_M1M3: return (clock / (m1 * m3));
4511 + default: return (0);
4512 + }
4513 + } else {
4514 + ASSERT(pll_type == PLL_TYPE2);
4515 +
4516 + m1 += CC_T2_BIAS;
4517 + m2 += CC_T2M2_BIAS;
4518 + m3 += CC_T2_BIAS;
4519 + ASSERT((m1 >= 2) && (m1 <= 7));
4520 + ASSERT((m2 >= 3) && (m2 <= 10));
4521 + ASSERT((m3 >= 2) && (m3 <= 7));
4522 +
4523 + if ((mc & CC_T2MC_M1BYP) == 0)
4524 + clock /= m1;
4525 + if ((mc & CC_T2MC_M2BYP) == 0)
4526 + clock /= m2;
4527 + if ((mc & CC_T2MC_M3BYP) == 0)
4528 + clock /= m3;
4529 +
4530 + return(clock);
4531 + }
4532 +}
4533 +
4534 +/* returns the current speed the SB is running at */
4535 +uint32
4536 +sb_clock(sb_t *sbh)
4537 +{
4538 + sb_info_t *si;
4539 + extifregs_t *eir;
4540 + chipcregs_t *cc;
4541 + uint32 n, m;
4542 + uint idx;
4543 + uint32 pll_type, rate;
4544 + uint intr_val = 0;
4545 +
4546 + si = SB_INFO(sbh);
4547 + idx = si->curidx;
4548 + pll_type = PLL_TYPE1;
4549 +
4550 + INTR_OFF(si, intr_val);
4551 +
4552 + /* switch to extif or chipc core */
4553 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4554 + n = R_REG(&eir->clockcontrol_n);
4555 + m = R_REG(&eir->clockcontrol_sb);
4556 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4557 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4558 + n = R_REG(&cc->clockcontrol_n);
4559 + if (pll_type == PLL_TYPE6)
4560 + m = R_REG(&cc->clockcontrol_mips);
4561 + else if (pll_type == PLL_TYPE3)
4562 + {
4563 + // Added by Chen-I for 5365
4564 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4565 + m = R_REG(&cc->clockcontrol_sb);
4566 + else
4567 + m = R_REG(&cc->clockcontrol_m2);
4568 + }
4569 + else
4570 + m = R_REG(&cc->clockcontrol_sb);
4571 + } else {
4572 + INTR_RESTORE(si, intr_val);
4573 + return 0;
4574 + }
4575 +
4576 + // Added by Chen-I for 5365
4577 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4578 + {
4579 + rate = 100000000;
4580 + }
4581 + else
4582 + {
4583 + /* calculate rate */
4584 + rate = sb_clock_rate(pll_type, n, m);
4585 + if (pll_type == PLL_TYPE3)
4586 + rate = rate / 2;
4587 + }
4588 +
4589 + /* switch back to previous core */
4590 + sb_setcoreidx(sbh, idx);
4591 +
4592 + INTR_RESTORE(si, intr_val);
4593 +
4594 + return rate;
4595 +}
4596 +
4597 +/* change logical "focus" to the gpio core for optimized access */
4598 +void*
4599 +sb_gpiosetcore(sb_t *sbh)
4600 +{
4601 + sb_info_t *si;
4602 +
4603 + si = SB_INFO(sbh);
4604 +
4605 + return (sb_setcoreidx(sbh, si->gpioidx));
4606 +}
4607 +
4608 +/* mask&set gpiocontrol bits */
4609 +uint32
4610 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4611 +{
4612 + sb_info_t *si;
4613 + uint regoff;
4614 +
4615 + si = SB_INFO(sbh);
4616 + regoff = 0;
4617 +
4618 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4619 +
4620 + /* gpios could be shared on router platforms */
4621 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4622 + mask = priority ? (sb_gpioreservation & mask) :
4623 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4624 + val &= mask;
4625 + }
4626 +
4627 + switch (si->gpioid) {
4628 + case SB_CC:
4629 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4630 + break;
4631 +
4632 + case SB_PCI:
4633 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4634 + break;
4635 +
4636 + case SB_EXTIF:
4637 + return (0);
4638 + }
4639 +
4640 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4641 +}
4642 +
4643 +/* mask&set gpio output enable bits */
4644 +uint32
4645 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4646 +{
4647 + sb_info_t *si;
4648 + uint regoff;
4649 +
4650 + si = SB_INFO(sbh);
4651 + regoff = 0;
4652 +
4653 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4654 +
4655 + /* gpios could be shared on router platforms */
4656 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4657 + mask = priority ? (sb_gpioreservation & mask) :
4658 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4659 + val &= mask;
4660 + }
4661 +
4662 + switch (si->gpioid) {
4663 + case SB_CC:
4664 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4665 + break;
4666 +
4667 + case SB_PCI:
4668 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4669 + break;
4670 +
4671 + case SB_EXTIF:
4672 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4673 + break;
4674 + }
4675 +
4676 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4677 +}
4678 +
4679 +/* mask&set gpio output bits */
4680 +uint32
4681 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4682 +{
4683 + sb_info_t *si;
4684 + uint regoff;
4685 +
4686 + si = SB_INFO(sbh);
4687 + regoff = 0;
4688 +
4689 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4690 +
4691 + /* gpios could be shared on router platforms */
4692 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4693 + mask = priority ? (sb_gpioreservation & mask) :
4694 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4695 + val &= mask;
4696 + }
4697 +
4698 + switch (si->gpioid) {
4699 + case SB_CC:
4700 + regoff = OFFSETOF(chipcregs_t, gpioout);
4701 + break;
4702 +
4703 + case SB_PCI:
4704 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4705 + break;
4706 +
4707 + case SB_EXTIF:
4708 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4709 + break;
4710 + }
4711 +
4712 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4713 +}
4714 +
4715 +/* reserve one gpio */
4716 +uint32
4717 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4718 +{
4719 + sb_info_t *si;
4720 +
4721 + si = SB_INFO(sbh);
4722 +
4723 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4724 +
4725 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4726 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4727 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4728 + return -1;
4729 + }
4730 + /* make sure only one bit is set */
4731 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4732 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4733 + return -1;
4734 + }
4735 +
4736 + /* already reserved */
4737 + if (sb_gpioreservation & gpio_bitmask)
4738 + return -1;
4739 + /* set reservation */
4740 + sb_gpioreservation |= gpio_bitmask;
4741 +
4742 + return sb_gpioreservation;
4743 +}
4744 +
4745 +/* release one gpio */
4746 +/*
4747 + * releasing the gpio doesn't change the current value on the GPIO last write value
4748 + * persists till some one overwrites it
4749 +*/
4750 +
4751 +uint32
4752 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4753 +{
4754 + sb_info_t *si;
4755 +
4756 + si = SB_INFO(sbh);
4757 +
4758 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4759 +
4760 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4761 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4762 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4763 + return -1;
4764 + }
4765 + /* make sure only one bit is set */
4766 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4767 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4768 + return -1;
4769 + }
4770 +
4771 + /* already released */
4772 + if (!(sb_gpioreservation & gpio_bitmask))
4773 + return -1;
4774 +
4775 + /* clear reservation */
4776 + sb_gpioreservation &= ~gpio_bitmask;
4777 +
4778 + return sb_gpioreservation;
4779 +}
4780 +
4781 +/* return the current gpioin register value */
4782 +uint32
4783 +sb_gpioin(sb_t *sbh)
4784 +{
4785 + sb_info_t *si;
4786 + uint regoff;
4787 +
4788 + si = SB_INFO(sbh);
4789 + regoff = 0;
4790 +
4791 + switch (si->gpioid) {
4792 + case SB_CC:
4793 + regoff = OFFSETOF(chipcregs_t, gpioin);
4794 + break;
4795 +
4796 + case SB_PCI:
4797 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4798 + break;
4799 +
4800 + case SB_EXTIF:
4801 + regoff = OFFSETOF(extifregs_t, gpioin);
4802 + break;
4803 + }
4804 +
4805 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4806 +}
4807 +
4808 +/* mask&set gpio interrupt polarity bits */
4809 +uint32
4810 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4811 +{
4812 + sb_info_t *si;
4813 + uint regoff;
4814 +
4815 + si = SB_INFO(sbh);
4816 + regoff = 0;
4817 +
4818 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4819 +
4820 + /* gpios could be shared on router platforms */
4821 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4822 + mask = priority ? (sb_gpioreservation & mask) :
4823 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4824 + val &= mask;
4825 + }
4826 +
4827 + switch (si->gpioid) {
4828 + case SB_CC:
4829 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4830 + break;
4831 +
4832 + case SB_PCI:
4833 + /* pci gpio implementation does not support interrupt polarity */
4834 + ASSERT(0);
4835 + break;
4836 +
4837 + case SB_EXTIF:
4838 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4839 + break;
4840 + }
4841 +
4842 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4843 +}
4844 +
4845 +/* mask&set gpio interrupt mask bits */
4846 +uint32
4847 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4848 +{
4849 + sb_info_t *si;
4850 + uint regoff;
4851 +
4852 + si = SB_INFO(sbh);
4853 + regoff = 0;
4854 +
4855 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4856 +
4857 + /* gpios could be shared on router platforms */
4858 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4859 + mask = priority ? (sb_gpioreservation & mask) :
4860 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4861 + val &= mask;
4862 + }
4863 +
4864 + switch (si->gpioid) {
4865 + case SB_CC:
4866 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4867 + break;
4868 +
4869 + case SB_PCI:
4870 + /* pci gpio implementation does not support interrupt mask */
4871 + ASSERT(0);
4872 + break;
4873 +
4874 + case SB_EXTIF:
4875 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4876 + break;
4877 + }
4878 +
4879 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4880 +}
4881 +
4882 +/* assign the gpio to an led */
4883 +uint32
4884 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4885 +{
4886 + sb_info_t *si;
4887 +
4888 + si = SB_INFO(sbh);
4889 + if (si->sb.ccrev < 16)
4890 + return -1;
4891 +
4892 + /* gpio led powersave reg */
4893 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4894 +}
4895 +
4896 +/* mask&set gpio timer val */
4897 +uint32
4898 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4899 +{
4900 + sb_info_t *si;
4901 + si = SB_INFO(sbh);
4902 +
4903 + if (si->sb.ccrev < 16)
4904 + return -1;
4905 +
4906 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4907 +}
4908 +
4909 +
4910 +/* return the slow clock source - LPO, XTAL, or PCI */
4911 +static uint
4912 +sb_slowclk_src(sb_info_t *si)
4913 +{
4914 + chipcregs_t *cc;
4915 +
4916 +
4917 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4918 +
4919 + if (si->sb.ccrev < 6) {
4920 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4921 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4922 + return (SCC_SS_PCI);
4923 + else
4924 + return (SCC_SS_XTAL);
4925 + } else if (si->sb.ccrev < 10) {
4926 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4927 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4928 + } else /* Insta-clock */
4929 + return (SCC_SS_XTAL);
4930 +}
4931 +
4932 +/* return the ILP (slowclock) min or max frequency */
4933 +static uint
4934 +sb_slowclk_freq(sb_info_t *si, bool max)
4935 +{
4936 + chipcregs_t *cc;
4937 + uint32 slowclk;
4938 + uint div;
4939 +
4940 +
4941 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4942 +
4943 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4944 +
4945 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4946 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4947 +
4948 + slowclk = sb_slowclk_src(si);
4949 + if (si->sb.ccrev < 6) {
4950 + if (slowclk == SCC_SS_PCI)
4951 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4952 + else
4953 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4954 + } else if (si->sb.ccrev < 10) {
4955 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4956 + if (slowclk == SCC_SS_LPO)
4957 + return (max? LPOMAXFREQ : LPOMINFREQ);
4958 + else if (slowclk == SCC_SS_XTAL)
4959 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4960 + else if (slowclk == SCC_SS_PCI)
4961 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4962 + else
4963 + ASSERT(0);
4964 + } else {
4965 + /* Chipc rev 10 is InstaClock */
4966 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4967 + div = 4 * (div + 1);
4968 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4969 + }
4970 + return (0);
4971 +}
4972 +
4973 +static void
4974 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4975 +{
4976 + chipcregs_t * cc;
4977 + uint slowmaxfreq, pll_delay, slowclk;
4978 + uint pll_on_delay, fref_sel_delay;
4979 +
4980 + pll_delay = PLL_DELAY;
4981 +
4982 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4983 + * since the xtal will also be powered down by dynamic clk control logic.
4984 + */
4985 + slowclk = sb_slowclk_src(si);
4986 + if (slowclk != SCC_SS_XTAL)
4987 + pll_delay += XTAL_ON_DELAY;
4988 +
4989 + /* Starting with 4318 it is ILP that is used for the delays */
4990 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4991 +
4992 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4993 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4994 +
4995 + cc = (chipcregs_t *)chipcregs;
4996 + W_REG(&cc->pll_on_delay, pll_on_delay);
4997 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4998 +}
4999 +
5000 +int
5001 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
5002 +{
5003 + sb_info_t *si;
5004 + uint origidx;
5005 + chipcregs_t *cc;
5006 + uint intr_val = 0;
5007 + uint err = 0;
5008 +
5009 + si = SB_INFO(sbh);
5010 +
5011 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
5012 + if (si->sb.ccrev < 6)
5013 + return 1;
5014 +
5015 + /* chipcommon cores rev10 are a whole new ball game */
5016 + if (si->sb.ccrev >= 10)
5017 + return 1;
5018 +
5019 + if (set && ((*div % 4) || (*div < 4)))
5020 + return 2;
5021 +
5022 + INTR_OFF(si, intr_val);
5023 + origidx = si->curidx;
5024 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5025 + ASSERT(cc != NULL);
5026 +
5027 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
5028 + err = 3;
5029 + goto done;
5030 + }
5031 +
5032 + if (set) {
5033 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
5034 + sb_clkctl_setdelay(sbh, (void *)cc);
5035 + } else
5036 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
5037 +
5038 +done:
5039 + sb_setcoreidx(sbh, origidx);
5040 + INTR_RESTORE(si, intr_val);
5041 + return err;
5042 +}
5043 +
5044 +/* initialize power control delay registers */
5045 +void sb_clkctl_init(sb_t *sbh)
5046 +{
5047 + sb_info_t *si;
5048 + uint origidx;
5049 + chipcregs_t *cc;
5050 +
5051 + si = SB_INFO(sbh);
5052 +
5053 + origidx = si->curidx;
5054 +
5055 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5056 + return;
5057 +
5058 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5059 + goto done;
5060 +
5061 + /* set all Instaclk chip ILP to 1 MHz */
5062 + if (si->sb.ccrev >= 10)
5063 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5064 +
5065 + sb_clkctl_setdelay(si, (void *)cc);
5066 +
5067 +done:
5068 + sb_setcoreidx(sbh, origidx);
5069 +}
5070 +void sb_pwrctl_init(sb_t *sbh)
5071 +{
5072 +sb_clkctl_init(sbh);
5073 +}
5074 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5075 +uint16
5076 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5077 +{
5078 + sb_info_t *si;
5079 + uint origidx;
5080 + chipcregs_t *cc;
5081 + uint slowminfreq;
5082 + uint16 fpdelay;
5083 + uint intr_val = 0;
5084 +
5085 + si = SB_INFO(sbh);
5086 + fpdelay = 0;
5087 + origidx = si->curidx;
5088 +
5089 + INTR_OFF(si, intr_val);
5090 +
5091 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5092 + goto done;
5093 +
5094 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5095 + goto done;
5096 +
5097 + slowminfreq = sb_slowclk_freq(si, FALSE);
5098 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5099 +
5100 +done:
5101 + sb_setcoreidx(sbh, origidx);
5102 + INTR_RESTORE(si, intr_val);
5103 + return (fpdelay);
5104 +}
5105 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5106 +{
5107 +return sb_clkctl_fast_pwrup_delay(sbh);
5108 +}
5109 +/* turn primary xtal and/or pll off/on */
5110 +int
5111 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5112 +{
5113 + sb_info_t *si;
5114 + uint32 in, out, outen;
5115 +
5116 + si = SB_INFO(sbh);
5117 +
5118 + switch (BUSTYPE(si->sb.bustype)) {
5119 + case PCI_BUS:
5120 +
5121 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5122 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5123 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5124 +
5125 + /*
5126 + * Avoid glitching the clock if GPRS is already using it.
5127 + * We can't actually read the state of the PLLPD so we infer it
5128 + * by the value of XTAL_PU which *is* readable via gpioin.
5129 + */
5130 + if (on && (in & PCI_CFG_GPIO_XTAL))
5131 + return (0);
5132 +
5133 + if (what & XTAL)
5134 + outen |= PCI_CFG_GPIO_XTAL;
5135 + if (what & PLL)
5136 + outen |= PCI_CFG_GPIO_PLL;
5137 +
5138 + if (on) {
5139 + /* turn primary xtal on */
5140 + if (what & XTAL) {
5141 + out |= PCI_CFG_GPIO_XTAL;
5142 + if (what & PLL)
5143 + out |= PCI_CFG_GPIO_PLL;
5144 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5145 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5146 + OSL_DELAY(XTAL_ON_DELAY);
5147 + }
5148 +
5149 + /* turn pll on */
5150 + if (what & PLL) {
5151 + out &= ~PCI_CFG_GPIO_PLL;
5152 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5153 + OSL_DELAY(2000);
5154 + }
5155 + } else {
5156 + if (what & XTAL)
5157 + out &= ~PCI_CFG_GPIO_XTAL;
5158 + if (what & PLL)
5159 + out |= PCI_CFG_GPIO_PLL;
5160 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5161 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5162 + }
5163 +
5164 + default:
5165 + return (-1);
5166 + }
5167 +
5168 + return (0);
5169 +}
5170 +
5171 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5172 +{
5173 +return sb_clkctl_xtal(sbh,what,on);
5174 +}
5175 +
5176 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5177 +/* returns true if ignore pll off is set and false if it is not */
5178 +bool
5179 +sb_clkctl_clk(sb_t *sbh, uint mode)
5180 +{
5181 + sb_info_t *si;
5182 + uint origidx;
5183 + chipcregs_t *cc;
5184 + uint32 scc;
5185 + bool forcefastclk=FALSE;
5186 + uint intr_val = 0;
5187 +
5188 + si = SB_INFO(sbh);
5189 +
5190 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5191 + if (si->sb.ccrev < 6)
5192 + return (FALSE);
5193 +
5194 + /* chipcommon cores rev10 are a whole new ball game */
5195 + if (si->sb.ccrev >= 10)
5196 + return (FALSE);
5197 +
5198 + INTR_OFF(si, intr_val);
5199 +
5200 + origidx = si->curidx;
5201 +
5202 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5203 + ASSERT(cc != NULL);
5204 +
5205 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5206 + goto done;
5207 +
5208 + switch (mode) {
5209 + case CLK_FAST: /* force fast (pll) clock */
5210 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5211 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5212 +
5213 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5214 + break;
5215 +
5216 + case CLK_DYNAMIC: /* enable dynamic clock control */
5217 + scc = R_REG(&cc->slow_clk_ctl);
5218 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5219 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5220 + scc |= SCC_XC;
5221 + W_REG(&cc->slow_clk_ctl, scc);
5222 +
5223 + /* for dynamic control, we have to release our xtal_pu "force on" */
5224 + if (scc & SCC_XC)
5225 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5226 + break;
5227 +
5228 + default:
5229 + ASSERT(0);
5230 + }
5231 +
5232 + /* Is the h/w forcing the use of the fast clk */
5233 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5234 +
5235 +done:
5236 + sb_setcoreidx(sbh, origidx);
5237 + INTR_RESTORE(si, intr_val);
5238 + return (forcefastclk);
5239 +}
5240 +
5241 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5242 +{
5243 +return sb_clkctl_clk(sbh, mode);
5244 +}
5245 +/* register driver interrupt disabling and restoring callback functions */
5246 +void
5247 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5248 +{
5249 + sb_info_t *si;
5250 +
5251 + si = SB_INFO(sbh);
5252 + si->intr_arg = intr_arg;
5253 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5254 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5255 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5256 + /* save current core id. when this function called, the current core
5257 + * must be the core which provides driver functions(il, et, wl, etc.)
5258 + */
5259 + si->dev_coreid = si->coreid[si->curidx];
5260 +}
5261 +
5262 +
5263 +void
5264 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5265 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5266 +{
5267 + uint vendor, core, unit;
5268 + uint chip, chippkg;
5269 + char varname[8];
5270 + uint8 class, subclass, progif;
5271 +
5272 + vendor = sb_corevendor(sbh);
5273 + core = sb_coreid(sbh);
5274 + unit = sb_coreunit(sbh);
5275 +
5276 + chip = BCMINIT(sb_chip)(sbh);
5277 + chippkg = BCMINIT(sb_chippkg)(sbh);
5278 +
5279 + progif = 0;
5280 +
5281 + /* Known vendor translations */
5282 + switch (vendor) {
5283 + case SB_VEND_BCM:
5284 + vendor = VENDOR_BROADCOM;
5285 + break;
5286 + }
5287 +
5288 + /* Determine class based on known core codes */
5289 + switch (core) {
5290 + case SB_ILINE20:
5291 + class = PCI_CLASS_NET;
5292 + subclass = PCI_NET_ETHER;
5293 + core = BCM47XX_ILINE_ID;
5294 + break;
5295 + case SB_ENET:
5296 + class = PCI_CLASS_NET;
5297 + subclass = PCI_NET_ETHER;
5298 + core = BCM47XX_ENET_ID;
5299 + break;
5300 + case SB_SDRAM:
5301 + case SB_MEMC:
5302 + class = PCI_CLASS_MEMORY;
5303 + subclass = PCI_MEMORY_RAM;
5304 + break;
5305 + case SB_PCI:
5306 + class = PCI_CLASS_BRIDGE;
5307 + subclass = PCI_BRIDGE_PCI;
5308 + break;
5309 + case SB_MIPS:
5310 + case SB_MIPS33:
5311 + class = PCI_CLASS_CPU;
5312 + subclass = PCI_CPU_MIPS;
5313 + break;
5314 + case SB_CODEC:
5315 + class = PCI_CLASS_COMM;
5316 + subclass = PCI_COMM_MODEM;
5317 + core = BCM47XX_V90_ID;
5318 + break;
5319 + case SB_USB:
5320 + class = PCI_CLASS_SERIAL;
5321 + subclass = PCI_SERIAL_USB;
5322 + progif = 0x10; /* OHCI */
5323 + core = BCM47XX_USB_ID;
5324 + break;
5325 + case SB_USB11H:
5326 + class = PCI_CLASS_SERIAL;
5327 + subclass = PCI_SERIAL_USB;
5328 + progif = 0x10; /* OHCI */
5329 + core = BCM47XX_USBH_ID;
5330 + break;
5331 + case SB_USB11D:
5332 + class = PCI_CLASS_SERIAL;
5333 + subclass = PCI_SERIAL_USB;
5334 + core = BCM47XX_USBD_ID;
5335 + break;
5336 + case SB_IPSEC:
5337 + class = PCI_CLASS_CRYPT;
5338 + subclass = PCI_CRYPT_NETWORK;
5339 + core = BCM47XX_IPSEC_ID;
5340 + break;
5341 + case SB_ROBO:
5342 + class = PCI_CLASS_NET;
5343 + subclass = PCI_NET_OTHER;
5344 + core = BCM47XX_ROBO_ID;
5345 + break;
5346 + case SB_EXTIF:
5347 + case SB_CC:
5348 + class = PCI_CLASS_MEMORY;
5349 + subclass = PCI_MEMORY_FLASH;
5350 + break;
5351 + case SB_D11:
5352 + class = PCI_CLASS_NET;
5353 + subclass = PCI_NET_OTHER;
5354 + /* Let an nvram variable override this */
5355 + sprintf(varname, "wl%did", unit);
5356 + if ((core = getintvar(NULL, varname)) == 0) {
5357 + if (chip == BCM4712_DEVICE_ID) {
5358 + if (chippkg == BCM4712SMALL_PKG_ID)
5359 + core = BCM4306_D11G_ID;
5360 + else
5361 + core = BCM4306_D11DUAL_ID;
5362 + }
5363 + }
5364 + break;
5365 +
5366 + default:
5367 + class = subclass = progif = 0xff;
5368 + break;
5369 + }
5370 +
5371 + *pcivendor = (uint16)vendor;
5372 + *pcidevice = (uint16)core;
5373 + *pciclass = class;
5374 + *pcisubclass = subclass;
5375 + *pciprogif = progif;
5376 +}
5377 +
5378 +/* Fix chip's configuration. The current core may be changed upon return */
5379 +static int
5380 +sb_pci_fixcfg(sb_info_t *si)
5381 +{
5382 + uint origidx, pciidx;
5383 + sbpciregs_t *pciregs;
5384 + uint16 val16, *reg16;
5385 +
5386 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5387 +
5388 + /* Fix PCI(e) SROM shadow area */
5389 + /* save the current index */
5390 + origidx = sb_coreidx(&si->sb);
5391 +
5392 + if (si->sb.buscoretype == SB_PCI) {
5393 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5394 + ASSERT(pciregs);
5395 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5396 + }
5397 + else {
5398 + ASSERT(0);
5399 + return -1;
5400 + }
5401 + pciidx = sb_coreidx(&si->sb);
5402 + val16 = R_REG(reg16);
5403 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5404 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5405 + W_REG(reg16, val16);
5406 + }
5407 +
5408 + /* restore the original index */
5409 + sb_setcoreidx(&si->sb, origidx);
5410 +
5411 + return 0;
5412 +}
5413 +
5414 +EXPORT_SYMBOL(sb_boardtype);
5415 +EXPORT_SYMBOL(sb_boardvendor);
5416 +EXPORT_SYMBOL(sb_gpiocontrol);
5417 +EXPORT_SYMBOL(sb_gpioin);
5418 +EXPORT_SYMBOL(sb_gpiointmask);
5419 +EXPORT_SYMBOL(sb_gpiointpolarity);
5420 +EXPORT_SYMBOL(sb_gpioled);
5421 +EXPORT_SYMBOL(sb_gpioout);
5422 +EXPORT_SYMBOL(sb_gpioouten);
5423 +EXPORT_SYMBOL(sb_gpiorelease);
5424 +EXPORT_SYMBOL(sb_gpioreserve);
5425 +EXPORT_SYMBOL(sb_gpiosetcore);
5426 +EXPORT_SYMBOL(sb_gpiotimerval);
5427 +EXPORT_SYMBOL(sb_watchdog);
5428 +EXPORT_SYMBOL(sb_kattach);
5429 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5430 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5431 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2006-10-15 23:29:14.000000000 +0200
5432 @@ -0,0 +1,418 @@
5433 +/*
5434 + * Broadcom SiliconBackplane chipcommon serial flash interface
5435 + *
5436 + * Copyright 2005, Broadcom Corporation
5437 + * All Rights Reserved.
5438 + *
5439 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5440 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5441 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5442 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5443 + *
5444 + * $Id$
5445 + */
5446 +
5447 +#include <osl.h>
5448 +#include <typedefs.h>
5449 +#include <sbconfig.h>
5450 +#include <sbchipc.h>
5451 +#include <mipsinc.h>
5452 +#include <bcmutils.h>
5453 +#include <bcmdevs.h>
5454 +#include <sflash.h>
5455 +
5456 +/* Private global state */
5457 +static struct sflash sflash;
5458 +
5459 +/* Issue a serial flash command */
5460 +static INLINE void
5461 +sflash_cmd(chipcregs_t *cc, uint opcode)
5462 +{
5463 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5464 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5465 +}
5466 +
5467 +/* Initialize serial flash access */
5468 +struct sflash *
5469 +sflash_init(chipcregs_t *cc)
5470 +{
5471 + uint32 id, id2;
5472 +
5473 + bzero(&sflash, sizeof(sflash));
5474 +
5475 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5476 +
5477 + switch (sflash.type) {
5478 + case SFLASH_ST:
5479 + /* Probe for ST chips */
5480 + sflash_cmd(cc, SFLASH_ST_DP);
5481 + sflash_cmd(cc, SFLASH_ST_RES);
5482 + id = R_REG(&cc->flashdata);
5483 + switch (id) {
5484 + case 0x11:
5485 + /* ST M25P20 2 Mbit Serial Flash */
5486 + sflash.blocksize = 64 * 1024;
5487 + sflash.numblocks = 4;
5488 + break;
5489 + case 0x12:
5490 + /* ST M25P40 4 Mbit Serial Flash */
5491 + sflash.blocksize = 64 * 1024;
5492 + sflash.numblocks = 8;
5493 + break;
5494 + case 0x13:
5495 + /* ST M25P80 8 Mbit Serial Flash */
5496 + sflash.blocksize = 64 * 1024;
5497 + sflash.numblocks = 16;
5498 + break;
5499 + case 0x14:
5500 + /* ST M25P16 16 Mbit Serial Flash */
5501 + sflash.blocksize = 64 * 1024;
5502 + sflash.numblocks = 32;
5503 + break;
5504 + case 0x15:
5505 + /* ST M25P32 32 Mbit Serial Flash */
5506 + sflash.blocksize = 64 * 1024;
5507 + sflash.numblocks = 64;
5508 + break;
5509 + case 0xbf:
5510 + W_REG(&cc->flashaddress, 1);
5511 + sflash_cmd(cc, SFLASH_ST_RES);
5512 + id2 = R_REG(&cc->flashdata);
5513 + if (id2 == 0x44) {
5514 + /* SST M25VF80 4 Mbit Serial Flash */
5515 + sflash.blocksize = 64 * 1024;
5516 + sflash.numblocks = 8;
5517 + }
5518 + break;
5519 + }
5520 + break;
5521 +
5522 + case SFLASH_AT:
5523 + /* Probe for Atmel chips */
5524 + sflash_cmd(cc, SFLASH_AT_STATUS);
5525 + id = R_REG(&cc->flashdata) & 0x3c;
5526 + switch (id) {
5527 + case 0xc:
5528 + /* Atmel AT45DB011 1Mbit Serial Flash */
5529 + sflash.blocksize = 256;
5530 + sflash.numblocks = 512;
5531 + break;
5532 + case 0x14:
5533 + /* Atmel AT45DB021 2Mbit Serial Flash */
5534 + sflash.blocksize = 256;
5535 + sflash.numblocks = 1024;
5536 + break;
5537 + case 0x1c:
5538 + /* Atmel AT45DB041 4Mbit Serial Flash */
5539 + sflash.blocksize = 256;
5540 + sflash.numblocks = 2048;
5541 + break;
5542 + case 0x24:
5543 + /* Atmel AT45DB081 8Mbit Serial Flash */
5544 + sflash.blocksize = 256;
5545 + sflash.numblocks = 4096;
5546 + break;
5547 + case 0x2c:
5548 + /* Atmel AT45DB161 16Mbit Serial Flash */
5549 + sflash.blocksize = 512;
5550 + sflash.numblocks = 4096;
5551 + break;
5552 + case 0x34:
5553 + /* Atmel AT45DB321 32Mbit Serial Flash */
5554 + sflash.blocksize = 512;
5555 + sflash.numblocks = 8192;
5556 + break;
5557 + case 0x3c:
5558 + /* Atmel AT45DB642 64Mbit Serial Flash */
5559 + sflash.blocksize = 1024;
5560 + sflash.numblocks = 8192;
5561 + break;
5562 + }
5563 + break;
5564 + }
5565 +
5566 + sflash.size = sflash.blocksize * sflash.numblocks;
5567 + return sflash.size ? &sflash : NULL;
5568 +}
5569 +
5570 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5571 +int
5572 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5573 +{
5574 + int cnt;
5575 + uint32 *from, *to;
5576 +
5577 + if (!len)
5578 + return 0;
5579 +
5580 + if ((offset + len) > sflash.size)
5581 + return -22;
5582 +
5583 + if ((len >= 4) && (offset & 3))
5584 + cnt = 4 - (offset & 3);
5585 + else if ((len >= 4) && ((uint32)buf & 3))
5586 + cnt = 4 - ((uint32)buf & 3);
5587 + else
5588 + cnt = len;
5589 +
5590 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5591 + to = (uint32 *)buf;
5592 +
5593 + if (cnt < 4) {
5594 + bcopy(from, to, cnt);
5595 + return cnt;
5596 + }
5597 +
5598 + while (cnt >= 4) {
5599 + *to++ = *from++;
5600 + cnt -= 4;
5601 + }
5602 +
5603 + return (len - cnt);
5604 +}
5605 +
5606 +/* Poll for command completion. Returns zero when complete. */
5607 +int
5608 +sflash_poll(chipcregs_t *cc, uint offset)
5609 +{
5610 + if (offset >= sflash.size)
5611 + return -22;
5612 +
5613 + switch (sflash.type) {
5614 + case SFLASH_ST:
5615 + /* Check for ST Write In Progress bit */
5616 + sflash_cmd(cc, SFLASH_ST_RDSR);
5617 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5618 + case SFLASH_AT:
5619 + /* Check for Atmel Ready bit */
5620 + sflash_cmd(cc, SFLASH_AT_STATUS);
5621 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5622 + }
5623 +
5624 + return 0;
5625 +}
5626 +
5627 +/* Write len bytes starting at offset into buf. Returns number of bytes
5628 + * written. Caller should poll for completion.
5629 + */
5630 +int
5631 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5632 +{
5633 + struct sflash *sfl;
5634 + int ret = 0;
5635 + bool is4712b0;
5636 + uint32 page, byte, mask;
5637 +
5638 + if (!len)
5639 + return 0;
5640 +
5641 + if ((offset + len) > sflash.size)
5642 + return -22;
5643 +
5644 + sfl = &sflash;
5645 + switch (sfl->type) {
5646 + case SFLASH_ST:
5647 + mask = R_REG(&cc->chipid);
5648 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5649 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5650 + /* Enable writes */
5651 + sflash_cmd(cc, SFLASH_ST_WREN);
5652 + if (is4712b0) {
5653 + mask = 1 << 14;
5654 + W_REG(&cc->flashaddress, offset);
5655 + W_REG(&cc->flashdata, *buf++);
5656 + /* Set chip select */
5657 + OR_REG(&cc->gpioout, mask);
5658 + /* Issue a page program with the first byte */
5659 + sflash_cmd(cc, SFLASH_ST_PP);
5660 + ret = 1;
5661 + offset++;
5662 + len--;
5663 + while (len > 0) {
5664 + if ((offset & 255) == 0) {
5665 + /* Page boundary, drop cs and return */
5666 + AND_REG(&cc->gpioout, ~mask);
5667 + if (!sflash_poll(cc, offset)) {
5668 + /* Flash rejected command */
5669 + return -11;
5670 + }
5671 + return ret;
5672 + } else {
5673 + /* Write single byte */
5674 + sflash_cmd(cc, *buf++);
5675 + }
5676 + ret++;
5677 + offset++;
5678 + len--;
5679 + }
5680 + /* All done, drop cs if needed */
5681 + if ((offset & 255) != 1) {
5682 + /* Drop cs */
5683 + AND_REG(&cc->gpioout, ~mask);
5684 + if (!sflash_poll(cc, offset)) {
5685 + /* Flash rejected command */
5686 + return -12;
5687 + }
5688 + }
5689 + } else {
5690 + ret = 1;
5691 + W_REG(&cc->flashaddress, offset);
5692 + W_REG(&cc->flashdata, *buf);
5693 + /* Page program */
5694 + sflash_cmd(cc, SFLASH_ST_PP);
5695 + }
5696 + break;
5697 + case SFLASH_AT:
5698 + mask = sfl->blocksize - 1;
5699 + page = (offset & ~mask) << 1;
5700 + byte = offset & mask;
5701 + /* Read main memory page into buffer 1 */
5702 + if (byte || len < sfl->blocksize) {
5703 + W_REG(&cc->flashaddress, page);
5704 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5705 + /* 250 us for AT45DB321B */
5706 + SPINWAIT(sflash_poll(cc, offset), 1000);
5707 + ASSERT(!sflash_poll(cc, offset));
5708 + }
5709 + /* Write into buffer 1 */
5710 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5711 + W_REG(&cc->flashaddress, byte++);
5712 + W_REG(&cc->flashdata, *buf++);
5713 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5714 + }
5715 + /* Write buffer 1 into main memory page */
5716 + W_REG(&cc->flashaddress, page);
5717 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5718 + break;
5719 + }
5720 +
5721 + return ret;
5722 +}
5723 +
5724 +/* Erase a region. Returns number of bytes scheduled for erasure.
5725 + * Caller should poll for completion.
5726 + */
5727 +int
5728 +sflash_erase(chipcregs_t *cc, uint offset)
5729 +{
5730 + struct sflash *sfl;
5731 +
5732 + if (offset >= sflash.size)
5733 + return -22;
5734 +
5735 + sfl = &sflash;
5736 + switch (sfl->type) {
5737 + case SFLASH_ST:
5738 + sflash_cmd(cc, SFLASH_ST_WREN);
5739 + W_REG(&cc->flashaddress, offset);
5740 + sflash_cmd(cc, SFLASH_ST_SE);
5741 + return sfl->blocksize;
5742 + case SFLASH_AT:
5743 + W_REG(&cc->flashaddress, offset << 1);
5744 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5745 + return sfl->blocksize;
5746 + }
5747 +
5748 + return 0;
5749 +}
5750 +
5751 +/*
5752 + * writes the appropriate range of flash, a NULL buf simply erases
5753 + * the region of flash
5754 + */
5755 +int
5756 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5757 +{
5758 + struct sflash *sfl;
5759 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5760 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5761 + uint blk_offset, blk_len, copied;
5762 + int bytes, ret = 0;
5763 +
5764 + /* Check address range */
5765 + if (len <= 0)
5766 + return 0;
5767 +
5768 + sfl = &sflash;
5769 + if ((offset + len) > sfl->size)
5770 + return -1;
5771 +
5772 + blocksize = sfl->blocksize;
5773 + mask = blocksize - 1;
5774 +
5775 + /* Allocate a block of mem */
5776 + if (!(block = MALLOC(NULL, blocksize)))
5777 + return -1;
5778 +
5779 + while (len) {
5780 + /* Align offset */
5781 + cur_offset = offset & ~mask;
5782 + cur_length = blocksize;
5783 + cur_ptr = block;
5784 +
5785 + remainder = blocksize - (offset & mask);
5786 + if (len < remainder)
5787 + cur_retlen = len;
5788 + else
5789 + cur_retlen = remainder;
5790 +
5791 + /* buf == NULL means erase only */
5792 + if (buf) {
5793 + /* Copy existing data into holding block if necessary */
5794 + if ((offset & mask) || (len < blocksize)) {
5795 + blk_offset = cur_offset;
5796 + blk_len = cur_length;
5797 + blk_ptr = cur_ptr;
5798 +
5799 + /* Copy entire block */
5800 + while(blk_len) {
5801 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5802 + blk_offset += copied;
5803 + blk_len -= copied;
5804 + blk_ptr += copied;
5805 + }
5806 + }
5807 +
5808 + /* Copy input data into holding block */
5809 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5810 + }
5811 +
5812 + /* Erase block */
5813 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5814 + goto done;
5815 + while (sflash_poll(cc, (uint) cur_offset));
5816 +
5817 + /* buf == NULL means erase only */
5818 + if (!buf) {
5819 + offset += cur_retlen;
5820 + len -= cur_retlen;
5821 + continue;
5822 + }
5823 +
5824 + /* Write holding block */
5825 + while (cur_length > 0) {
5826 + if ((bytes = sflash_write(cc,
5827 + (uint) cur_offset,
5828 + (uint) cur_length,
5829 + (uchar *) cur_ptr)) < 0) {
5830 + ret = bytes;
5831 + goto done;
5832 + }
5833 + while (sflash_poll(cc, (uint) cur_offset));
5834 + cur_offset += bytes;
5835 + cur_length -= bytes;
5836 + cur_ptr += bytes;
5837 + }
5838 +
5839 + offset += cur_retlen;
5840 + len -= cur_retlen;
5841 + buf += cur_retlen;
5842 + }
5843 +
5844 + ret = len;
5845 +done:
5846 + if (block)
5847 + MFREE(NULL, block, blocksize);
5848 + return ret;
5849 +}
5850 +
5851 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5852 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5853 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-15 23:29:14.000000000 +0200
5854 @@ -0,0 +1,391 @@
5855 +/*
5856 + * Broadcom device-specific manifest constants.
5857 + *
5858 + * Copyright 2005, Broadcom Corporation
5859 + * All Rights Reserved.
5860 + *
5861 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5862 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5863 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5864 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5865 + * $Id$
5866 + */
5867 +
5868 +#ifndef _BCMDEVS_H
5869 +#define _BCMDEVS_H
5870 +
5871 +
5872 +/* Known PCI vendor Id's */
5873 +#define VENDOR_EPIGRAM 0xfeda
5874 +#define VENDOR_BROADCOM 0x14e4
5875 +#define VENDOR_3COM 0x10b7
5876 +#define VENDOR_NETGEAR 0x1385
5877 +#define VENDOR_DIAMOND 0x1092
5878 +#define VENDOR_DELL 0x1028
5879 +#define VENDOR_HP 0x0e11
5880 +#define VENDOR_APPLE 0x106b
5881 +
5882 +/* PCI Device Id's */
5883 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5884 +#define BCM4211_DEVICE_ID 0x4211
5885 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5886 +#define BCM4231_DEVICE_ID 0x4231
5887 +
5888 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5889 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5890 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5891 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5892 +
5893 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5894 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5895 +
5896 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5897 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5898 +
5899 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5900 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5901 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5902 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5903 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5904 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5905 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5906 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5907 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5908 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5909 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5910 +
5911 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5912 +
5913 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5914 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5915 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5916 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5917 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5918 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5919 +
5920 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5921 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5922 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5923 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5924 +
5925 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5926 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5927 +
5928 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5929 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5930 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5931 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5932 +
5933 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5934 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5935 +#define BCM4306_D11G_ID2 0x4325
5936 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5937 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5938 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5939 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5940 +
5941 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5942 +
5943 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5944 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5945 +
5946 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5947 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5948 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5949 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5950 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5951 +
5952 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5953 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5954 +
5955 +
5956 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5957 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5958 +
5959 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5960 +
5961 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5962 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5963 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5964 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5965 +
5966 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5967 +
5968 +/* Address map */
5969 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5970 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5971 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5972 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5973 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5974 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5975 +
5976 +/* Core register space */
5977 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5978 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5979 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5980 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5981 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5982 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5983 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5984 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5985 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5986 +
5987 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5988 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5989 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5990 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5991 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5992 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5993 +
5994 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5995 +
5996 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5997 +
5998 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5999 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
6000 +
6001 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
6002 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
6003 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
6004 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
6005 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
6006 +
6007 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
6008 +
6009 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
6010 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
6011 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
6012 +
6013 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
6014 +
6015 +/* PCMCIA vendor Id's */
6016 +
6017 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
6018 +
6019 +/* SDIO vendor Id's */
6020 +#define VENDOR_BROADCOM_SDIO 0x00BF
6021 +
6022 +
6023 +/* boardflags */
6024 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
6025 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
6026 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
6027 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
6028 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
6029 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
6030 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
6031 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
6032 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
6033 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
6034 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
6035 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
6036 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
6037 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
6038 +
6039 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6040 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6041 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
6042 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
6043 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6044 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6045 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6046 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6047 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6048 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6049 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6050 +
6051 +/* Bus types */
6052 +#define SB_BUS 0 /* Silicon Backplane */
6053 +#define PCI_BUS 1 /* PCI target */
6054 +#define PCMCIA_BUS 2 /* PCMCIA target */
6055 +#define SDIO_BUS 3 /* SDIO target */
6056 +#define JTAG_BUS 4 /* JTAG */
6057 +
6058 +/* Allows optimization for single-bus support */
6059 +#ifdef BCMBUSTYPE
6060 +#define BUSTYPE(bus) (BCMBUSTYPE)
6061 +#else
6062 +#define BUSTYPE(bus) (bus)
6063 +#endif
6064 +
6065 +/* power control defines */
6066 +#define PLL_DELAY 150 /* us pll on delay */
6067 +#define FREF_DELAY 200 /* us fref change delay */
6068 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6069 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6070 +
6071 +/* Reference Board Types */
6072 +
6073 +#define BU4710_BOARD 0x0400
6074 +#define VSIM4710_BOARD 0x0401
6075 +#define QT4710_BOARD 0x0402
6076 +
6077 +#define BU4610_BOARD 0x0403
6078 +#define VSIM4610_BOARD 0x0404
6079 +
6080 +#define BU4307_BOARD 0x0405
6081 +#define BCM94301CB_BOARD 0x0406
6082 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6083 +#define BCM94301MP_BOARD 0x0407
6084 +#define BCM94307MP_BOARD 0x0408
6085 +#define BCMAP4307_BOARD 0x0409
6086 +
6087 +#define BU4309_BOARD 0x040a
6088 +#define BCM94309CB_BOARD 0x040b
6089 +#define BCM94309MP_BOARD 0x040c
6090 +#define BCM4309AP_BOARD 0x040d
6091 +
6092 +#define BCM94302MP_BOARD 0x040e
6093 +
6094 +#define VSIM4310_BOARD 0x040f
6095 +#define BU4711_BOARD 0x0410
6096 +#define BCM94310U_BOARD 0x0411
6097 +#define BCM94310AP_BOARD 0x0412
6098 +#define BCM94310MP_BOARD 0x0414
6099 +
6100 +#define BU4306_BOARD 0x0416
6101 +#define BCM94306CB_BOARD 0x0417
6102 +#define BCM94306MP_BOARD 0x0418
6103 +
6104 +#define BCM94710D_BOARD 0x041a
6105 +#define BCM94710R1_BOARD 0x041b
6106 +#define BCM94710R4_BOARD 0x041c
6107 +#define BCM94710AP_BOARD 0x041d
6108 +
6109 +
6110 +#define BU2050_BOARD 0x041f
6111 +
6112 +
6113 +#define BCM94309G_BOARD 0x0421
6114 +
6115 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6116 +
6117 +#define BU4704_BOARD 0x0423
6118 +#define BU4702_BOARD 0x0424
6119 +
6120 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6121 +
6122 +#define BU4317_BOARD 0x0426
6123 +
6124 +
6125 +#define BCM94702MN_BOARD 0x0428
6126 +
6127 +/* BCM4702 1U CompactPCI Board */
6128 +#define BCM94702CPCI_BOARD 0x0429
6129 +
6130 +/* BCM4702 with BCM95380 VLAN Router */
6131 +#define BCM95380RR_BOARD 0x042a
6132 +
6133 +/* cb4306 with SiGe PA */
6134 +#define BCM94306CBSG_BOARD 0x042b
6135 +
6136 +/* mp4301 with 2050 radio */
6137 +#define BCM94301MPL_BOARD 0x042c
6138 +
6139 +/* cb4306 with SiGe PA */
6140 +#define PCSG94306_BOARD 0x042d
6141 +
6142 +/* bu4704 with sdram */
6143 +#define BU4704SD_BOARD 0x042e
6144 +
6145 +/* Dual 11a/11g Router */
6146 +#define BCM94704AGR_BOARD 0x042f
6147 +
6148 +/* 11a-only minipci */
6149 +#define BCM94308MP_BOARD 0x0430
6150 +
6151 +
6152 +
6153 +/* BCM94317 boards */
6154 +#define BCM94317CB_BOARD 0x0440
6155 +#define BCM94317MP_BOARD 0x0441
6156 +#define BCM94317PCMCIA_BOARD 0x0442
6157 +#define BCM94317SDIO_BOARD 0x0443
6158 +
6159 +#define BU4712_BOARD 0x0444
6160 +#define BU4712SD_BOARD 0x045d
6161 +#define BU4712L_BOARD 0x045f
6162 +
6163 +/* BCM4712 boards */
6164 +#define BCM94712AP_BOARD 0x0445
6165 +#define BCM94712P_BOARD 0x0446
6166 +
6167 +/* BCM4318 boards */
6168 +#define BU4318_BOARD 0x0447
6169 +#define CB4318_BOARD 0x0448
6170 +#define MPG4318_BOARD 0x0449
6171 +#define MP4318_BOARD 0x044a
6172 +#define SD4318_BOARD 0x044b
6173 +
6174 +/* BCM63XX boards */
6175 +#define BCM96338_BOARD 0x6338
6176 +#define BCM96345_BOARD 0x6345
6177 +#define BCM96348_BOARD 0x6348
6178 +
6179 +/* Another mp4306 with SiGe */
6180 +#define BCM94306P_BOARD 0x044c
6181 +
6182 +/* CF-like 4317 modules */
6183 +#define BCM94317CF_BOARD 0x044d
6184 +
6185 +/* mp4303 */
6186 +#define BCM94303MP_BOARD 0x044e
6187 +
6188 +/* mpsgh4306 */
6189 +#define BCM94306MPSGH_BOARD 0x044f
6190 +
6191 +/* BRCM 4306 w/ Front End Modules */
6192 +#define BCM94306MPM 0x0450
6193 +#define BCM94306MPL 0x0453
6194 +
6195 +/* 4712agr */
6196 +#define BCM94712AGR_BOARD 0x0451
6197 +
6198 +/* The real CF 4317 board */
6199 +#define CFI4317_BOARD 0x0452
6200 +
6201 +/* pcmcia 4303 */
6202 +#define PC4303_BOARD 0x0454
6203 +
6204 +/* 5350K */
6205 +#define BCM95350K_BOARD 0x0455
6206 +
6207 +/* 5350R */
6208 +#define BCM95350R_BOARD 0x0456
6209 +
6210 +/* 4306mplna */
6211 +#define BCM94306MPLNA_BOARD 0x0457
6212 +
6213 +/* 4320 boards */
6214 +#define BU4320_BOARD 0x0458
6215 +#define BU4320S_BOARD 0x0459
6216 +#define BCM94320PH_BOARD 0x045a
6217 +
6218 +/* 4306mph */
6219 +#define BCM94306MPH_BOARD 0x045b
6220 +
6221 +/* 4306pciv */
6222 +#define BCM94306PCIV_BOARD 0x045c
6223 +
6224 +#define BU4712SD_BOARD 0x045d
6225 +
6226 +#define BCM94320PFLSH_BOARD 0x045e
6227 +
6228 +#define BU4712L_BOARD 0x045f
6229 +#define BCM94712LGR_BOARD 0x0460
6230 +#define BCM94320R_BOARD 0x0461
6231 +
6232 +#define BU5352_BOARD 0x0462
6233 +
6234 +#define BCM94318MPGH_BOARD 0x0463
6235 +
6236 +
6237 +#define BCM95352GR_BOARD 0x0467
6238 +
6239 +/* bcm95351agr */
6240 +#define BCM95351AGR_BOARD 0x0470
6241 +
6242 +/* # of GPIO pins */
6243 +#define GPIO_NUMPINS 16
6244 +
6245 +#endif /* _BCMDEVS_H */
6246 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6247 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6248 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-15 23:29:14.000000000 +0200
6249 @@ -0,0 +1,152 @@
6250 +/*
6251 + * local version of endian.h - byte order defines
6252 + *
6253 + * Copyright 2005, Broadcom Corporation
6254 + * All Rights Reserved.
6255 + *
6256 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6257 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6258 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6259 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6260 + *
6261 + * $Id$
6262 +*/
6263 +
6264 +#ifndef _BCMENDIAN_H_
6265 +#define _BCMENDIAN_H_
6266 +
6267 +#include <typedefs.h>
6268 +
6269 +/* Byte swap a 16 bit value */
6270 +#define BCMSWAP16(val) \
6271 + ((uint16)( \
6272 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6273 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6274 +
6275 +/* Byte swap a 32 bit value */
6276 +#define BCMSWAP32(val) \
6277 + ((uint32)( \
6278 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6279 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6280 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6281 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6282 +
6283 +/* 2 Byte swap a 32 bit value */
6284 +#define BCMSWAP32BY16(val) \
6285 + ((uint32)( \
6286 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6287 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6288 +
6289 +
6290 +static INLINE uint16
6291 +bcmswap16(uint16 val)
6292 +{
6293 + return BCMSWAP16(val);
6294 +}
6295 +
6296 +static INLINE uint32
6297 +bcmswap32(uint32 val)
6298 +{
6299 + return BCMSWAP32(val);
6300 +}
6301 +
6302 +static INLINE uint32
6303 +bcmswap32by16(uint32 val)
6304 +{
6305 + return BCMSWAP32BY16(val);
6306 +}
6307 +
6308 +/* buf - start of buffer of shorts to swap */
6309 +/* len - byte length of buffer */
6310 +static INLINE void
6311 +bcmswap16_buf(uint16 *buf, uint len)
6312 +{
6313 + len = len/2;
6314 +
6315 + while(len--){
6316 + *buf = bcmswap16(*buf);
6317 + buf++;
6318 + }
6319 +}
6320 +
6321 +#ifndef hton16
6322 +#ifndef IL_BIGENDIAN
6323 +#define HTON16(i) BCMSWAP16(i)
6324 +#define hton16(i) bcmswap16(i)
6325 +#define hton32(i) bcmswap32(i)
6326 +#define ntoh16(i) bcmswap16(i)
6327 +#define ntoh32(i) bcmswap32(i)
6328 +#define ltoh16(i) (i)
6329 +#define ltoh32(i) (i)
6330 +#define htol16(i) (i)
6331 +#define htol32(i) (i)
6332 +#else
6333 +#define HTON16(i) (i)
6334 +#define hton16(i) (i)
6335 +#define hton32(i) (i)
6336 +#define ntoh16(i) (i)
6337 +#define ntoh32(i) (i)
6338 +#define ltoh16(i) bcmswap16(i)
6339 +#define ltoh32(i) bcmswap32(i)
6340 +#define htol16(i) bcmswap16(i)
6341 +#define htol32(i) bcmswap32(i)
6342 +#endif
6343 +#endif
6344 +
6345 +#ifndef IL_BIGENDIAN
6346 +#define ltoh16_buf(buf, i)
6347 +#define htol16_buf(buf, i)
6348 +#else
6349 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6350 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6351 +#endif
6352 +
6353 +/*
6354 +* load 16-bit value from unaligned little endian byte array.
6355 +*/
6356 +static INLINE uint16
6357 +ltoh16_ua(uint8 *bytes)
6358 +{
6359 + return (bytes[1]<<8)+bytes[0];
6360 +}
6361 +
6362 +/*
6363 +* load 32-bit value from unaligned little endian byte array.
6364 +*/
6365 +static INLINE uint32
6366 +ltoh32_ua(uint8 *bytes)
6367 +{
6368 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6369 +}
6370 +
6371 +/*
6372 +* load 16-bit value from unaligned big(network) endian byte array.
6373 +*/
6374 +static INLINE uint16
6375 +ntoh16_ua(uint8 *bytes)
6376 +{
6377 + return (bytes[0]<<8)+bytes[1];
6378 +}
6379 +
6380 +/*
6381 +* load 32-bit value from unaligned big(network) endian byte array.
6382 +*/
6383 +static INLINE uint32
6384 +ntoh32_ua(uint8 *bytes)
6385 +{
6386 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6387 +}
6388 +
6389 +#define ltoh_ua(ptr) ( \
6390 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6391 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6392 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6393 +)
6394 +
6395 +#define ntoh_ua(ptr) ( \
6396 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6397 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6398 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6399 +)
6400 +
6401 +#endif /* _BCMENDIAN_H_ */
6402 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6403 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6404 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-15 23:29:14.000000000 +0200
6405 @@ -0,0 +1,95 @@
6406 +/*
6407 + * NVRAM variable manipulation
6408 + *
6409 + * Copyright 2005, Broadcom Corporation
6410 + * All Rights Reserved.
6411 + *
6412 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6413 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6414 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6415 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6416 + *
6417 + * $Id$
6418 + */
6419 +
6420 +#ifndef _bcmnvram_h_
6421 +#define _bcmnvram_h_
6422 +
6423 +#ifndef _LANGUAGE_ASSEMBLY
6424 +
6425 +#include <typedefs.h>
6426 +
6427 +struct nvram_header {
6428 + uint32 magic;
6429 + uint32 len;
6430 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6431 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6432 + uint32 config_ncdl; /* ncdl values for memc */
6433 +};
6434 +
6435 +struct nvram_tuple {
6436 + char *name;
6437 + char *value;
6438 + struct nvram_tuple *next;
6439 +};
6440 +
6441 +/*
6442 + * Get the value of an NVRAM variable. The pointer returned may be
6443 + * invalid after a set.
6444 + * @param name name of variable to get
6445 + * @return value of variable or NULL if undefined
6446 + */
6447 +extern char * __init early_nvram_get(const char *name);
6448 +
6449 +/*
6450 + * Get the value of an NVRAM variable. The pointer returned may be
6451 + * invalid after a set.
6452 + * @param name name of variable to get
6453 + * @return value of variable or NULL if undefined
6454 + */
6455 +extern char *nvram_get(const char *name);
6456 +
6457 +/*
6458 + * Get the value of an NVRAM variable.
6459 + * @param name name of variable to get
6460 + * @return value of variable or NUL if undefined
6461 + */
6462 +#define nvram_safe_get(name) (BCMINIT(early_nvram_get)(name) ? : "")
6463 +
6464 +/*
6465 + * Match an NVRAM variable.
6466 + * @param name name of variable to match
6467 + * @param match value to compare against value of variable
6468 + * @return TRUE if variable is defined and its value is string equal
6469 + * to match or FALSE otherwise
6470 + */
6471 +static inline int
6472 +nvram_match(char *name, char *match) {
6473 + const char *value = BCMINIT(early_nvram_get)(name);
6474 + return (value && !strcmp(value, match));
6475 +}
6476 +
6477 +/*
6478 + * Inversely match an NVRAM variable.
6479 + * @param name name of variable to match
6480 + * @param match value to compare against value of variable
6481 + * @return TRUE if variable is defined and its value is not string
6482 + * equal to invmatch or FALSE otherwise
6483 + */
6484 +static inline int
6485 +nvram_invmatch(char *name, char *invmatch) {
6486 + const char *value = BCMINIT(early_nvram_get)(name);
6487 + return (value && strcmp(value, invmatch));
6488 +}
6489 +
6490 +#endif /* _LANGUAGE_ASSEMBLY */
6491 +
6492 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6493 +#define NVRAM_VERSION 1
6494 +#define NVRAM_HEADER_SIZE 20
6495 +#define NVRAM_SPACE 0x8000
6496 +
6497 +#define NVRAM_MAX_VALUE_LEN 255
6498 +#define NVRAM_MAX_PARAM_LEN 64
6499 +
6500 +#endif /* _bcmnvram_h_ */
6501 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6502 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6503 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-15 23:29:14.000000000 +0200
6504 @@ -0,0 +1,23 @@
6505 +/*
6506 + * Misc useful routines to access NIC local SROM/OTP .
6507 + *
6508 + * Copyright 2005, Broadcom Corporation
6509 + * All Rights Reserved.
6510 + *
6511 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6512 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6513 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6514 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6515 + *
6516 + * $Id$
6517 + */
6518 +
6519 +#ifndef _bcmsrom_h_
6520 +#define _bcmsrom_h_
6521 +
6522 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6523 +
6524 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6525 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6526 +
6527 +#endif /* _bcmsrom_h_ */
6528 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6529 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6530 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-15 23:29:14.000000000 +0200
6531 @@ -0,0 +1,308 @@
6532 +/*
6533 + * Misc useful os-independent macros and functions.
6534 + *
6535 + * Copyright 2005, Broadcom Corporation
6536 + * All Rights Reserved.
6537 + *
6538 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6539 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6540 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6541 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6542 + * $Id$
6543 + */
6544 +
6545 +#ifndef _bcmutils_h_
6546 +#define _bcmutils_h_
6547 +
6548 +/*** driver-only section ***/
6549 +#include <osl.h>
6550 +
6551 +#define _BCM_U 0x01 /* upper */
6552 +#define _BCM_L 0x02 /* lower */
6553 +#define _BCM_D 0x04 /* digit */
6554 +#define _BCM_C 0x08 /* cntrl */
6555 +#define _BCM_P 0x10 /* punct */
6556 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6557 +#define _BCM_X 0x40 /* hex digit */
6558 +#define _BCM_SP 0x80 /* hard space (0x20) */
6559 +
6560 +#define GPIO_PIN_NOTDEFINED 0x20
6561 +
6562 +extern unsigned char bcm_ctype[];
6563 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6564 +
6565 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6566 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6567 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6568 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6569 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6570 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6571 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6572 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6573 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6574 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6575 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6576 +
6577 +/*
6578 + * Spin at most 'us' microseconds while 'exp' is true.
6579 + * Caller should explicitly test 'exp' when this completes
6580 + * and take appropriate error action if 'exp' is still true.
6581 + */
6582 +#define SPINWAIT(exp, us) { \
6583 + uint countdown = (us) + 9; \
6584 + while ((exp) && (countdown >= 10)) {\
6585 + OSL_DELAY(10); \
6586 + countdown -= 10; \
6587 + } \
6588 +}
6589 +
6590 +/* generic osl packet queue */
6591 +struct pktq {
6592 + void *head; /* first packet to dequeue */
6593 + void *tail; /* last packet to dequeue */
6594 + uint len; /* number of queued packets */
6595 + uint maxlen; /* maximum number of queued packets */
6596 + bool priority; /* enqueue by packet priority */
6597 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6598 +};
6599 +#define DEFAULT_QLEN 128
6600 +
6601 +#define pktq_len(q) ((q)->len)
6602 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6603 +#define pktq_head(q) ((q)->head)
6604 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6605 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6606 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6607 +
6608 +/* externs */
6609 +/* packet */
6610 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6611 +extern uint pkttotlen(osl_t *osh, void *);
6612 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6613 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6614 +extern void *pktdeq(struct pktq *q);
6615 +extern void *pktdeqtail(struct pktq *q);
6616 +/* string */
6617 +extern uint bcm_atoi(char *s);
6618 +extern uchar bcm_toupper(uchar c);
6619 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6620 +extern char *bcmstrstr(char *haystack, char *needle);
6621 +extern char *bcmstrcat(char *dest, const char *src);
6622 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6623 +/* ethernet address */
6624 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6625 +extern int bcm_ether_atoe(char *p, char *ea);
6626 +/* delay */
6627 +extern void bcm_mdelay(uint ms);
6628 +/* variable access */
6629 +extern char *getvar(char *vars, char *name);
6630 +extern int getintvar(char *vars, char *name);
6631 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6632 +#define bcmlog(fmt, a1, a2)
6633 +#define bcmdumplog(buf, size) *buf = '\0'
6634 +#define bcmdumplogent(buf, idx) -1
6635 +
6636 +/*** driver/apps-shared section ***/
6637 +
6638 +#define BCME_STRLEN 64
6639 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6640 +
6641 +
6642 +/*
6643 + * error codes could be added but the defined ones shouldn't be changed/deleted
6644 + * these error codes are exposed to the user code
6645 + * when ever a new error code is added to this list
6646 + * please update errorstring table with the related error string and
6647 + * update osl files with os specific errorcode map
6648 +*/
6649 +
6650 +#define BCME_ERROR -1 /* Error generic */
6651 +#define BCME_BADARG -2 /* Bad Argument */
6652 +#define BCME_BADOPTION -3 /* Bad option */
6653 +#define BCME_NOTUP -4 /* Not up */
6654 +#define BCME_NOTDOWN -5 /* Not down */
6655 +#define BCME_NOTAP -6 /* Not AP */
6656 +#define BCME_NOTSTA -7 /* Not STA */
6657 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6658 +#define BCME_RADIOOFF -9 /* Radio Off */
6659 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6660 +#define BCME_NOCLK -11 /* No Clock*/
6661 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6662 +#define BCME_BADBAND -13 /* BAD Band */
6663 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6664 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6665 +#define BCME_BUSY -16 /* Busy*/
6666 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6667 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6668 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6669 +#define BCME_BADCHAN -20 /* BAD Channel */
6670 +#define BCME_BADADDR -21 /* BAD Address*/
6671 +#define BCME_NORESOURCE -22 /* No resources*/
6672 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6673 +#define BCME_BADLEN -24 /* Bad Length*/
6674 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6675 +#define BCME_EPERM -26 /* Not Permitted */
6676 +#define BCME_NOMEM -27 /* No Memory */
6677 +#define BCME_ASSOCIATED -28 /* Associated */
6678 +#define BCME_RANGE -29 /* Range Error*/
6679 +#define BCME_NOTFOUND -30 /* Not found */
6680 +#define BCME_LAST BCME_NOTFOUND
6681 +
6682 +#ifndef ABS
6683 +#define ABS(a) (((a)<0)?-(a):(a))
6684 +#endif
6685 +
6686 +#ifndef MIN
6687 +#define MIN(a, b) (((a)<(b))?(a):(b))
6688 +#endif
6689 +
6690 +#ifndef MAX
6691 +#define MAX(a, b) (((a)>(b))?(a):(b))
6692 +#endif
6693 +
6694 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6695 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6696 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6697 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6698 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6699 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6700 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6701 +
6702 +/* bit map related macros */
6703 +#ifndef setbit
6704 +#define NBBY 8 /* 8 bits per byte */
6705 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6706 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6707 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6708 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6709 +#endif
6710 +
6711 +#define NBITS(type) (sizeof(type) * 8)
6712 +#define NBITVAL(bits) (1 << (bits))
6713 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6714 +
6715 +/* crc defines */
6716 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6717 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6718 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6719 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6720 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6721 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6722 +
6723 +/* bcm_format_flags() bit description structure */
6724 +typedef struct bcm_bit_desc {
6725 + uint32 bit;
6726 + char* name;
6727 +} bcm_bit_desc_t;
6728 +
6729 +/* tag_ID/length/value_buffer tuple */
6730 +typedef struct bcm_tlv {
6731 + uint8 id;
6732 + uint8 len;
6733 + uint8 data[1];
6734 +} bcm_tlv_t;
6735 +
6736 +/* Check that bcm_tlv_t fits into the given buflen */
6737 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6738 +
6739 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6740 +#define ETHER_ADDR_STR_LEN 18
6741 +
6742 +/* unaligned load and store macros */
6743 +#ifdef IL_BIGENDIAN
6744 +static INLINE uint32
6745 +load32_ua(uint8 *a)
6746 +{
6747 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6748 +}
6749 +
6750 +static INLINE void
6751 +store32_ua(uint8 *a, uint32 v)
6752 +{
6753 + a[0] = (v >> 24) & 0xff;
6754 + a[1] = (v >> 16) & 0xff;
6755 + a[2] = (v >> 8) & 0xff;
6756 + a[3] = v & 0xff;
6757 +}
6758 +
6759 +static INLINE uint16
6760 +load16_ua(uint8 *a)
6761 +{
6762 + return ((a[0] << 8) | a[1]);
6763 +}
6764 +
6765 +static INLINE void
6766 +store16_ua(uint8 *a, uint16 v)
6767 +{
6768 + a[0] = (v >> 8) & 0xff;
6769 + a[1] = v & 0xff;
6770 +}
6771 +
6772 +#else
6773 +
6774 +static INLINE uint32
6775 +load32_ua(uint8 *a)
6776 +{
6777 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6778 +}
6779 +
6780 +static INLINE void
6781 +store32_ua(uint8 *a, uint32 v)
6782 +{
6783 + a[3] = (v >> 24) & 0xff;
6784 + a[2] = (v >> 16) & 0xff;
6785 + a[1] = (v >> 8) & 0xff;
6786 + a[0] = v & 0xff;
6787 +}
6788 +
6789 +static INLINE uint16
6790 +load16_ua(uint8 *a)
6791 +{
6792 + return ((a[1] << 8) | a[0]);
6793 +}
6794 +
6795 +static INLINE void
6796 +store16_ua(uint8 *a, uint16 v)
6797 +{
6798 + a[1] = (v >> 8) & 0xff;
6799 + a[0] = v & 0xff;
6800 +}
6801 +
6802 +#endif
6803 +
6804 +/* externs */
6805 +/* crc */
6806 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6807 +/* format/print */
6808 +/* IE parsing */
6809 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6810 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6811 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6812 +
6813 +/* bcmerror*/
6814 +extern const char *bcmerrorstr(int bcmerror);
6815 +
6816 +/* multi-bool data type: set of bools, mbool is true if any is set */
6817 +typedef uint32 mbool;
6818 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6819 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6820 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6821 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6822 +
6823 +/* power conversion */
6824 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6825 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6826 +
6827 +/* generic datastruct to help dump routines */
6828 +struct fielddesc {
6829 + char *nameandfmt;
6830 + uint32 offset;
6831 + uint32 len;
6832 +};
6833 +
6834 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6835 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6836 +
6837 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6838 +
6839 +#endif /* _bcmutils_h_ */
6840 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6841 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6842 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2006-10-15 23:29:14.000000000 +0200
6843 @@ -0,0 +1,85 @@
6844 +/*
6845 + * bit manipulation utility functions
6846 + *
6847 + * Copyright 2005, Broadcom Corporation
6848 + * All Rights Reserved.
6849 + *
6850 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6851 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6852 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6853 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6854 + * $Id$
6855 + */
6856 +
6857 +#ifndef _BITFUNCS_H
6858 +#define _BITFUNCS_H
6859 +
6860 +#include <typedefs.h>
6861 +
6862 +/* local prototypes */
6863 +static INLINE uint32 find_msbit(uint32 x);
6864 +
6865 +
6866 +/*
6867 + * find_msbit: returns index of most significant set bit in x, with index
6868 + * range defined as 0-31. NOTE: returns zero if input is zero.
6869 + */
6870 +
6871 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6872 +
6873 +/*
6874 + * Implementation for Pentium processors and gcc. Note that this
6875 + * instruction is actually very slow on some processors (e.g., family 5,
6876 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6877 + * implementation instead.
6878 + */
6879 +static INLINE uint32 find_msbit(uint32 x)
6880 +{
6881 + uint msbit;
6882 + __asm__("bsrl %1,%0"
6883 + :"=r" (msbit)
6884 + :"r" (x));
6885 + return msbit;
6886 +}
6887 +
6888 +#else
6889 +
6890 +/*
6891 + * Generic Implementation
6892 + */
6893 +
6894 +#define DB_POW_MASK16 0xffff0000
6895 +#define DB_POW_MASK8 0x0000ff00
6896 +#define DB_POW_MASK4 0x000000f0
6897 +#define DB_POW_MASK2 0x0000000c
6898 +#define DB_POW_MASK1 0x00000002
6899 +
6900 +static INLINE uint32 find_msbit(uint32 x)
6901 +{
6902 + uint32 temp_x = x;
6903 + uint msbit = 0;
6904 + if (temp_x & DB_POW_MASK16) {
6905 + temp_x >>= 16;
6906 + msbit = 16;
6907 + }
6908 + if (temp_x & DB_POW_MASK8) {
6909 + temp_x >>= 8;
6910 + msbit += 8;
6911 + }
6912 + if (temp_x & DB_POW_MASK4) {
6913 + temp_x >>= 4;
6914 + msbit += 4;
6915 + }
6916 + if (temp_x & DB_POW_MASK2) {
6917 + temp_x >>= 2;
6918 + msbit += 2;
6919 + }
6920 + if (temp_x & DB_POW_MASK1) {
6921 + msbit += 1;
6922 + }
6923 + return(msbit);
6924 +}
6925 +
6926 +#endif
6927 +
6928 +#endif /* _BITFUNCS_H */
6929 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6930 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6931 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2006-10-15 23:29:14.000000000 +0200
6932 @@ -0,0 +1,188 @@
6933 +/*
6934 + * flash.h: Common definitions for flash access.
6935 + *
6936 + * Copyright 2005, Broadcom Corporation
6937 + * All Rights Reserved.
6938 + *
6939 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6940 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6941 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6942 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6943 + *
6944 + * $Id$
6945 + */
6946 +
6947 +/* Types of flashes we know about */
6948 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6949 +
6950 +/* Commands to write/erase the flases */
6951 +typedef struct _flash_cmds{
6952 + flash_type_t type;
6953 + bool need_unlock;
6954 + uint16 pre_erase;
6955 + uint16 erase_block;
6956 + uint16 erase_chip;
6957 + uint16 write_word;
6958 + uint16 write_buf;
6959 + uint16 clear_csr;
6960 + uint16 read_csr;
6961 + uint16 read_id;
6962 + uint16 confirm;
6963 + uint16 read_array;
6964 +} flash_cmds_t;
6965 +
6966 +#define UNLOCK_CMD_WORDS 2
6967 +
6968 +typedef struct _unlock_cmd {
6969 + uint addr[UNLOCK_CMD_WORDS];
6970 + uint16 cmd[UNLOCK_CMD_WORDS];
6971 +} unlock_cmd_t;
6972 +
6973 +/* Flash descriptors */
6974 +typedef struct _flash_desc {
6975 + uint16 mfgid; /* Manufacturer Id */
6976 + uint16 devid; /* Device Id */
6977 + uint size; /* Total size in bytes */
6978 + uint width; /* Device width in bytes */
6979 + flash_type_t type; /* Device type old, S, J */
6980 + uint bsize; /* Block size */
6981 + uint nb; /* Number of blocks */
6982 + uint ff; /* First full block */
6983 + uint lf; /* Last full block */
6984 + uint nsub; /* Number of subblocks */
6985 + uint *subblocks; /* Offsets for subblocks */
6986 + char *desc; /* Description */
6987 +} flash_desc_t;
6988 +
6989 +
6990 +#ifdef DECLARE_FLASHES
6991 +flash_cmds_t sflash_cmd_t =
6992 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6993 +
6994 +flash_cmds_t flash_cmds[] = {
6995 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6996 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6997 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6998 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6999 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
7000 + { 0 }
7001 +};
7002 +
7003 +unlock_cmd_t unlock_cmd_amd = {
7004 +#ifdef MIPSEB
7005 +/* addr: */ { 0x0aa8, 0x0556},
7006 +#else
7007 +/* addr: */ { 0x0aaa, 0x0554},
7008 +#endif
7009 +/* data: */ { 0xaa, 0x55}
7010 +};
7011 +
7012 +unlock_cmd_t unlock_cmd_sst = {
7013 +#ifdef MIPSEB
7014 +/* addr: */ { 0xaaa8, 0x5556},
7015 +#else
7016 +/* addr: */ { 0xaaaa, 0x5554},
7017 +#endif
7018 +/* data: */ { 0xaa, 0x55}
7019 +};
7020 +
7021 +#define AMD_CMD 0xaaa
7022 +#define SST_CMD 0xaaaa
7023 +
7024 +/* intel unlock block cmds */
7025 +#define INTEL_UNLOCK1 0x60
7026 +#define INTEL_UNLOCK2 0xD0
7027 +
7028 +/* Just eight blocks of 8KB byte each */
7029 +
7030 +uint blk8x8k[] = { 0x00000000,
7031 + 0x00002000,
7032 + 0x00004000,
7033 + 0x00006000,
7034 + 0x00008000,
7035 + 0x0000a000,
7036 + 0x0000c000,
7037 + 0x0000e000,
7038 + 0x00010000
7039 +};
7040 +
7041 +/* Funky AMD arrangement for 29xx800's */
7042 +uint amd800[] = { 0x00000000, /* 16KB */
7043 + 0x00004000, /* 32KB */
7044 + 0x0000c000, /* 8KB */
7045 + 0x0000e000, /* 8KB */
7046 + 0x00010000, /* 8KB */
7047 + 0x00012000, /* 8KB */
7048 + 0x00014000, /* 32KB */
7049 + 0x0001c000, /* 16KB */
7050 + 0x00020000
7051 +};
7052 +
7053 +/* AMD arrangement for 29xx160's */
7054 +uint amd4112[] = { 0x00000000, /* 32KB */
7055 + 0x00008000, /* 8KB */
7056 + 0x0000a000, /* 8KB */
7057 + 0x0000c000, /* 16KB */
7058 + 0x00010000
7059 +};
7060 +uint amd2114[] = { 0x00000000, /* 16KB */
7061 + 0x00004000, /* 8KB */
7062 + 0x00006000, /* 8KB */
7063 + 0x00008000, /* 32KB */
7064 + 0x00010000
7065 +};
7066 +
7067 +
7068 +flash_desc_t sflash_desc =
7069 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7070 +
7071 +flash_desc_t flashes[] = {
7072 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7073 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7074 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7075 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7076 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7077 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7078 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7079 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7080 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7081 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7082 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7083 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7084 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7085 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7086 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7087 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7088 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7089 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7090 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7091 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7092 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7093 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7094 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7095 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7096 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7097 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7098 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7099 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7100 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7101 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7102 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7103 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7104 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7105 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7106 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7107 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7108 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7109 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7110 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7111 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7112 +};
7113 +
7114 +#else
7115 +
7116 +extern flash_cmds_t flash_cmds[];
7117 +extern unlock_cmd_t unlock_cmd;
7118 +extern flash_desc_t flashes[];
7119 +
7120 +#endif
7121 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7122 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7123 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2006-10-15 23:29:14.000000000 +0200
7124 @@ -0,0 +1,27 @@
7125 +/*
7126 + * BCM47XX FLASH driver interface
7127 + *
7128 + * Copyright 2005, Broadcom Corporation
7129 + * All Rights Reserved.
7130 + *
7131 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7132 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7133 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7134 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7135 + * $Id$
7136 + */
7137 +
7138 +#ifndef _flashutl_h_
7139 +#define _flashutl_h_
7140 +
7141 +
7142 +#ifndef _LANGUAGE_ASSEMBLY
7143 +
7144 +int sysFlashInit(char *flash_str);
7145 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7146 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7147 +void nvWrite(unsigned short *data, unsigned int len);
7148 +
7149 +#endif /* _LANGUAGE_ASSEMBLY */
7150 +
7151 +#endif /* _flashutl_h_ */
7152 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7153 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7154 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-15 23:29:14.000000000 +0200
7155 @@ -0,0 +1,16 @@
7156 +/*
7157 + * Alternate include file for HND sbmips.h since CFE also ships with
7158 + * a sbmips.h.
7159 + *
7160 + * Copyright 2005, Broadcom Corporation
7161 + * All Rights Reserved.
7162 + *
7163 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7164 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7165 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7166 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7167 + *
7168 + * $Id$
7169 + */
7170 +
7171 +#include "sbmips.h"
7172 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7173 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7174 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2006-10-15 23:29:14.000000000 +0200
7175 @@ -0,0 +1,331 @@
7176 +/*
7177 + * Linux OS Independent Layer
7178 + *
7179 + * Copyright 2005, Broadcom Corporation
7180 + * All Rights Reserved.
7181 + *
7182 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7183 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7184 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7185 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7186 + *
7187 + * $Id$
7188 + */
7189 +
7190 +#ifndef _linux_osl_h_
7191 +#define _linux_osl_h_
7192 +
7193 +#include <typedefs.h>
7194 +
7195 +/* use current 2.4.x calling conventions */
7196 +#include <linuxver.h>
7197 +
7198 +/* assert and panic */
7199 +#ifdef __GNUC__
7200 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7201 +#if GCC_VERSION > 30100
7202 +#define ASSERT(exp) do {} while (0)
7203 +#else
7204 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7205 +#define ASSERT(exp)
7206 +#endif
7207 +#endif
7208 +
7209 +/* microsecond delay */
7210 +#define OSL_DELAY(usec) osl_delay(usec)
7211 +extern void osl_delay(uint usec);
7212 +
7213 +/* PCI configuration space access macros */
7214 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7215 + osl_pci_read_config((osh), (offset), (size))
7216 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7217 + osl_pci_write_config((osh), (offset), (size), (val))
7218 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7219 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7220 +
7221 +/* PCI device bus # and slot # */
7222 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7223 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7224 +extern uint osl_pci_bus(osl_t *osh);
7225 +extern uint osl_pci_slot(osl_t *osh);
7226 +
7227 +/* OSL initialization */
7228 +extern osl_t *osl_attach(void *pdev);
7229 +extern void osl_detach(osl_t *osh);
7230 +
7231 +/* host/bus architecture-specific byte swap */
7232 +#define BUS_SWAP32(v) (v)
7233 +
7234 +/* general purpose memory allocation */
7235 +
7236 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7237 +#define MFREE(osh, addr, size) kfree(addr);
7238 +
7239 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7240 +
7241 +extern void *osl_malloc(osl_t *osh, uint size);
7242 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7243 +extern uint osl_malloced(osl_t *osh);
7244 +extern uint osl_malloc_failed(osl_t *osh);
7245 +
7246 +/* allocate/free shared (dma-able) consistent memory */
7247 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7248 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7249 + osl_dma_alloc_consistent((osh), (size), (pap))
7250 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7251 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7252 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7253 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7254 +
7255 +/* map/unmap direction */
7256 +#define DMA_TX 1
7257 +#define DMA_RX 2
7258 +
7259 +/* register access macros */
7260 +#if defined(BCMJTAG)
7261 +#include <bcmjtag.h>
7262 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7263 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7264 +#endif
7265 +
7266 +/*
7267 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7268 + * Macros expand to calls to functions defined in linux_osl.c .
7269 + */
7270 +#ifndef BINOSL
7271 +
7272 +/* string library, kernel mode */
7273 +#define printf(fmt, args...) printk(fmt, ## args)
7274 +#include <linux/kernel.h>
7275 +#include <linux/string.h>
7276 +
7277 +/* register access macros */
7278 +#if !defined(BCMJTAG)
7279 +#ifndef IL_BIGENDIAN
7280 +#define R_REG(r) ( \
7281 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7282 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7283 + readl((volatile uint32*)(r)) \
7284 +)
7285 +#define W_REG(r, v) do { \
7286 + switch (sizeof(*(r))) { \
7287 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7288 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7289 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7290 + } \
7291 +} while (0)
7292 +#else /* IL_BIGENDIAN */
7293 +#define R_REG(r) ({ \
7294 + __typeof(*(r)) __osl_v; \
7295 + switch (sizeof(*(r))) { \
7296 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7297 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7298 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7299 + } \
7300 + __osl_v; \
7301 +})
7302 +#define W_REG(r, v) do { \
7303 + switch (sizeof(*(r))) { \
7304 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7305 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7306 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7307 + } \
7308 +} while (0)
7309 +#endif
7310 +#endif
7311 +
7312 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7313 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7314 +
7315 +/* bcopy, bcmp, and bzero */
7316 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7317 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7318 +#define bzero(b, len) memset((b), '\0', (len))
7319 +
7320 +/* uncached virtual address */
7321 +#ifdef mips
7322 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7323 +#include <asm/addrspace.h>
7324 +#else
7325 +#define OSL_UNCACHED(va) (va)
7326 +#endif
7327 +
7328 +/* get processor cycle count */
7329 +#if defined(mips)
7330 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7331 +#elif defined(__i386__)
7332 +#define OSL_GETCYCLES(x) rdtscl((x))
7333 +#else
7334 +#define OSL_GETCYCLES(x) ((x) = 0)
7335 +#endif
7336 +
7337 +/* dereference an address that may cause a bus exception */
7338 +#ifdef mips
7339 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7340 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7341 +#else
7342 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7343 +#include <asm/paccess.h>
7344 +#endif
7345 +#else
7346 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7347 +#endif
7348 +
7349 +/* map/unmap physical to virtual I/O */
7350 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7351 +#define REG_UNMAP(va) iounmap((void *)(va))
7352 +
7353 +/* shared (dma-able) memory access macros */
7354 +#define R_SM(r) *(r)
7355 +#define W_SM(r, v) (*(r) = (v))
7356 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7357 +
7358 +/* packet primitives */
7359 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7360 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7361 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7362 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7363 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7364 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7365 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7366 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7367 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7368 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7369 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7370 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7371 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7372 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7373 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7374 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7375 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7376 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7377 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7378 +extern void osl_pktfree(void *skb);
7379 +
7380 +#else /* BINOSL */
7381 +
7382 +/* string library */
7383 +#ifndef LINUX_OSL
7384 +#undef printf
7385 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7386 +#undef sprintf
7387 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7388 +#undef strcmp
7389 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7390 +#undef strncmp
7391 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7392 +#undef strlen
7393 +#define strlen(s) osl_strlen((s))
7394 +#undef strcpy
7395 +#define strcpy(d, s) osl_strcpy((d), (s))
7396 +#undef strncpy
7397 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7398 +#endif
7399 +extern int osl_printf(const char *format, ...);
7400 +extern int osl_sprintf(char *buf, const char *format, ...);
7401 +extern int osl_strcmp(const char *s1, const char *s2);
7402 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7403 +extern int osl_strlen(const char *s);
7404 +extern char* osl_strcpy(char *d, const char *s);
7405 +extern char* osl_strncpy(char *d, const char *s, uint n);
7406 +
7407 +/* register access macros */
7408 +#if !defined(BCMJTAG)
7409 +#define R_REG(r) ( \
7410 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7411 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7412 + osl_readl((volatile uint32*)(r)) \
7413 +)
7414 +#define W_REG(r, v) do { \
7415 + switch (sizeof(*(r))) { \
7416 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7417 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7418 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7419 + } \
7420 +} while (0)
7421 +#endif
7422 +
7423 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7424 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7425 +extern uint8 osl_readb(volatile uint8 *r);
7426 +extern uint16 osl_readw(volatile uint16 *r);
7427 +extern uint32 osl_readl(volatile uint32 *r);
7428 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7429 +extern void osl_writew(uint16 v, volatile uint16 *r);
7430 +extern void osl_writel(uint32 v, volatile uint32 *r);
7431 +
7432 +/* bcopy, bcmp, and bzero */
7433 +extern void bcopy(const void *src, void *dst, int len);
7434 +extern int bcmp(const void *b1, const void *b2, int len);
7435 +extern void bzero(void *b, int len);
7436 +
7437 +/* uncached virtual address */
7438 +#define OSL_UNCACHED(va) osl_uncached((va))
7439 +extern void *osl_uncached(void *va);
7440 +
7441 +/* get processor cycle count */
7442 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7443 +extern uint osl_getcycles(void);
7444 +
7445 +/* dereference an address that may target abort */
7446 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7447 +extern int osl_busprobe(uint32 *val, uint32 addr);
7448 +
7449 +/* map/unmap physical to virtual */
7450 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7451 +#define REG_UNMAP(va) osl_reg_unmap((va))
7452 +extern void *osl_reg_map(uint32 pa, uint size);
7453 +extern void osl_reg_unmap(void *va);
7454 +
7455 +/* shared (dma-able) memory access macros */
7456 +#define R_SM(r) *(r)
7457 +#define W_SM(r, v) (*(r) = (v))
7458 +#define BZERO_SM(r, len) bzero((r), (len))
7459 +
7460 +/* packet primitives */
7461 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7462 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7463 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7464 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7465 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7466 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7467 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7468 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7469 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7470 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7471 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7472 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7473 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7474 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7475 +#define PKTLINK(skb) osl_pktlink((skb))
7476 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7477 +#define PKTPRIO(skb) osl_pktprio((skb))
7478 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7479 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7480 +extern void osl_pktfree(void *skb);
7481 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7482 +extern uint osl_pktlen(osl_t *osh, void *skb);
7483 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7484 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7485 +extern void *osl_pktnext(osl_t *osh, void *skb);
7486 +extern void osl_pktsetnext(void *skb, void *x);
7487 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7488 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7489 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7490 +extern void *osl_pktdup(osl_t *osh, void *skb);
7491 +extern void *osl_pktcookie(void *skb);
7492 +extern void osl_pktsetcookie(void *skb, void *x);
7493 +extern void *osl_pktlink(void *skb);
7494 +extern void osl_pktsetlink(void *skb, void *x);
7495 +extern uint osl_pktprio(void *skb);
7496 +extern void osl_pktsetprio(void *skb, uint x);
7497 +
7498 +#endif /* BINOSL */
7499 +
7500 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7501 +extern int osl_error(int bcmerror);
7502 +
7503 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7504 +#define PKTBUFSZ 2048
7505 +
7506 +#endif /* _linux_osl_h_ */
7507 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7508 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7509 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-15 23:29:14.000000000 +0200
7510 @@ -0,0 +1,389 @@
7511 +/*
7512 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7513 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7514 + *
7515 + * Copyright 2005, Broadcom Corporation
7516 + * All Rights Reserved.
7517 + *
7518 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7519 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7520 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7521 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7522 + *
7523 + * $Id$
7524 + */
7525 +
7526 +#ifndef _linuxver_h_
7527 +#define _linuxver_h_
7528 +
7529 +#include <linux/config.h>
7530 +#include <linux/version.h>
7531 +
7532 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7533 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7534 +#ifdef __UNDEF_NO_VERSION__
7535 +#undef __NO_VERSION__
7536 +#else
7537 +#define __NO_VERSION__
7538 +#endif
7539 +#endif
7540 +
7541 +#if defined(MODULE) && defined(MODVERSIONS)
7542 +#include <linux/modversions.h>
7543 +#endif
7544 +
7545 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7546 +#include <linux/moduleparam.h>
7547 +#endif
7548 +
7549 +
7550 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7551 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7552 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7553 +#endif
7554 +
7555 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7556 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7557 +#include <linux/malloc.h>
7558 +#else
7559 +#include <linux/slab.h>
7560 +#endif
7561 +
7562 +#include <linux/types.h>
7563 +#include <linux/init.h>
7564 +#include <linux/mm.h>
7565 +#include <linux/string.h>
7566 +#include <linux/pci.h>
7567 +#include <linux/interrupt.h>
7568 +#include <linux/netdevice.h>
7569 +#include <asm/io.h>
7570 +
7571 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7572 +#include <linux/workqueue.h>
7573 +#else
7574 +#include <linux/tqueue.h>
7575 +#ifndef work_struct
7576 +#define work_struct tq_struct
7577 +#endif
7578 +#ifndef INIT_WORK
7579 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7580 +#endif
7581 +#ifndef schedule_work
7582 +#define schedule_work(_work) schedule_task((_work))
7583 +#endif
7584 +#ifndef flush_scheduled_work
7585 +#define flush_scheduled_work() flush_scheduled_tasks()
7586 +#endif
7587 +#endif
7588 +
7589 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7590 +/* Some distributions have their own 2.6.x compatibility layers */
7591 +#ifndef IRQ_NONE
7592 +typedef void irqreturn_t;
7593 +#define IRQ_NONE
7594 +#define IRQ_HANDLED
7595 +#define IRQ_RETVAL(x)
7596 +#endif
7597 +#else
7598 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7599 +#endif
7600 +
7601 +#ifndef __exit
7602 +#define __exit
7603 +#endif
7604 +#ifndef __devexit
7605 +#define __devexit
7606 +#endif
7607 +#ifndef __devinit
7608 +#define __devinit __init
7609 +#endif
7610 +#ifndef __devinitdata
7611 +#define __devinitdata
7612 +#endif
7613 +#ifndef __devexit_p
7614 +#define __devexit_p(x) x
7615 +#endif
7616 +
7617 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7618 +
7619 +#define pci_get_drvdata(dev) (dev)->sysdata
7620 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7621 +
7622 +/*
7623 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7624 + */
7625 +
7626 +struct pci_device_id {
7627 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7628 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7629 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7630 + unsigned long driver_data; /* Data private to the driver */
7631 +};
7632 +
7633 +struct pci_driver {
7634 + struct list_head node;
7635 + char *name;
7636 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7637 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7638 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7639 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7640 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7641 +};
7642 +
7643 +#define MODULE_DEVICE_TABLE(type, name)
7644 +#define PCI_ANY_ID (~0)
7645 +
7646 +/* compatpci.c */
7647 +#define pci_module_init pci_register_driver
7648 +extern int pci_register_driver(struct pci_driver *drv);
7649 +extern void pci_unregister_driver(struct pci_driver *drv);
7650 +
7651 +#endif /* PCI registration */
7652 +
7653 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7654 +#ifdef MODULE
7655 +#define module_init(x) int init_module(void) { return x(); }
7656 +#define module_exit(x) void cleanup_module(void) { x(); }
7657 +#else
7658 +#define module_init(x) __initcall(x);
7659 +#define module_exit(x) __exitcall(x);
7660 +#endif
7661 +#endif
7662 +
7663 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7664 +#define list_for_each(pos, head) \
7665 + for (pos = (head)->next; pos != (head); pos = pos->next)
7666 +#endif
7667 +
7668 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7669 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7670 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7671 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7672 +#endif
7673 +
7674 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7675 +#define pci_enable_device(dev) do { } while (0)
7676 +#endif
7677 +
7678 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7679 +#define net_device device
7680 +#endif
7681 +
7682 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7683 +
7684 +/*
7685 + * DMA mapping
7686 + *
7687 + * See linux/Documentation/DMA-mapping.txt
7688 + */
7689 +
7690 +#ifndef PCI_DMA_TODEVICE
7691 +#define PCI_DMA_TODEVICE 1
7692 +#define PCI_DMA_FROMDEVICE 2
7693 +#endif
7694 +
7695 +typedef u32 dma_addr_t;
7696 +
7697 +/* Pure 2^n version of get_order */
7698 +static inline int get_order(unsigned long size)
7699 +{
7700 + int order;
7701 +
7702 + size = (size-1) >> (PAGE_SHIFT-1);
7703 + order = -1;
7704 + do {
7705 + size >>= 1;
7706 + order++;
7707 + } while (size);
7708 + return order;
7709 +}
7710 +
7711 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7712 + dma_addr_t *dma_handle)
7713 +{
7714 + void *ret;
7715 + int gfp = GFP_ATOMIC | GFP_DMA;
7716 +
7717 + ret = (void *)__get_free_pages(gfp, get_order(size));
7718 +
7719 + if (ret != NULL) {
7720 + memset(ret, 0, size);
7721 + *dma_handle = virt_to_bus(ret);
7722 + }
7723 + return ret;
7724 +}
7725 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7726 + void *vaddr, dma_addr_t dma_handle)
7727 +{
7728 + free_pages((unsigned long)vaddr, get_order(size));
7729 +}
7730 +#ifdef ILSIM
7731 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7732 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7733 +#else
7734 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7735 +#define pci_unmap_single(cookie, address, size, dir)
7736 +#endif
7737 +
7738 +#endif /* DMA mapping */
7739 +
7740 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7741 +
7742 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7743 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7744 +
7745 +/* pcmcia-cs provides its own netdevice compatibility layer */
7746 +#ifndef _COMPAT_NETDEVICE_H
7747 +
7748 +/*
7749 + * SoftNet
7750 + *
7751 + * For pre-softnet kernels we need to tell the upper layer not to
7752 + * re-enter start_xmit() while we are in there. However softnet
7753 + * guarantees not to enter while we are in there so there is no need
7754 + * to do the netif_stop_queue() dance unless the transmit queue really
7755 + * gets stuck. This should also improve performance according to tests
7756 + * done by Aman Singla.
7757 + */
7758 +
7759 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7760 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7761 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7762 +
7763 +static inline void netif_start_queue(struct net_device *dev)
7764 +{
7765 + dev->tbusy = 0;
7766 + dev->interrupt = 0;
7767 + dev->start = 1;
7768 +}
7769 +
7770 +#define netif_queue_stopped(dev) (dev)->tbusy
7771 +#define netif_running(dev) (dev)->start
7772 +
7773 +#endif /* _COMPAT_NETDEVICE_H */
7774 +
7775 +#define netif_device_attach(dev) netif_start_queue(dev)
7776 +#define netif_device_detach(dev) netif_stop_queue(dev)
7777 +
7778 +/* 2.4.x renamed bottom halves to tasklets */
7779 +#define tasklet_struct tq_struct
7780 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7781 +{
7782 + queue_task(tasklet, &tq_immediate);
7783 + mark_bh(IMMEDIATE_BH);
7784 +}
7785 +
7786 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7787 + void (*func)(unsigned long),
7788 + unsigned long data)
7789 +{
7790 + tasklet->next = NULL;
7791 + tasklet->sync = 0;
7792 + tasklet->routine = (void (*)(void *))func;
7793 + tasklet->data = (void *)data;
7794 +}
7795 +#define tasklet_kill(tasklet) {do{} while(0);}
7796 +
7797 +/* 2.4.x introduced del_timer_sync() */
7798 +#define del_timer_sync(timer) del_timer(timer)
7799 +
7800 +#else
7801 +
7802 +#define netif_down(dev)
7803 +
7804 +#endif /* SoftNet */
7805 +
7806 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7807 +
7808 +/*
7809 + * Emit code to initialise a tq_struct's routine and data pointers
7810 + */
7811 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7812 + do { \
7813 + (_tq)->routine = _routine; \
7814 + (_tq)->data = _data; \
7815 + } while (0)
7816 +
7817 +/*
7818 + * Emit code to initialise all of a tq_struct
7819 + */
7820 +#define INIT_TQUEUE(_tq, _routine, _data) \
7821 + do { \
7822 + INIT_LIST_HEAD(&(_tq)->list); \
7823 + (_tq)->sync = 0; \
7824 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7825 + } while (0)
7826 +
7827 +#endif
7828 +
7829 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7830 +
7831 +/* Power management related routines */
7832 +
7833 +static inline int
7834 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7835 +{
7836 + int i;
7837 + if (buffer) {
7838 + for (i = 0; i < 16; i++)
7839 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7840 + }
7841 + return 0;
7842 +}
7843 +
7844 +static inline int
7845 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7846 +{
7847 + int i;
7848 +
7849 + if (buffer) {
7850 + for (i = 0; i < 16; i++)
7851 + pci_write_config_dword(dev,i * 4, buffer[i]);
7852 + }
7853 + /*
7854 + * otherwise, write the context information we know from bootup.
7855 + * This works around a problem where warm-booting from Windows
7856 + * combined with a D3(hot)->D0 transition causes PCI config
7857 + * header data to be forgotten.
7858 + */
7859 + else {
7860 + for (i = 0; i < 6; i ++)
7861 + pci_write_config_dword(dev,
7862 + PCI_BASE_ADDRESS_0 + (i * 4),
7863 + pci_resource_start(dev, i));
7864 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7865 + }
7866 + return 0;
7867 +}
7868 +
7869 +#endif /* PCI power management */
7870 +
7871 +/* Old cp0 access macros deprecated in 2.4.19 */
7872 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7873 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7874 +#endif
7875 +
7876 +/* Module refcount handled internally in 2.6.x */
7877 +#ifndef SET_MODULE_OWNER
7878 +#define SET_MODULE_OWNER(dev) do {} while (0)
7879 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7880 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7881 +#else
7882 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7883 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7884 +#endif
7885 +
7886 +#ifndef SET_NETDEV_DEV
7887 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7888 +#endif
7889 +
7890 +#ifndef HAVE_FREE_NETDEV
7891 +#define free_netdev(dev) kfree(dev)
7892 +#endif
7893 +
7894 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7895 +/* struct packet_type redefined in 2.6.x */
7896 +#define af_packet_priv data
7897 +#endif
7898 +
7899 +#endif /* _linuxver_h_ */
7900 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7901 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7902 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-15 23:29:14.000000000 +0200
7903 @@ -0,0 +1,552 @@
7904 +/*
7905 + * HND Run Time Environment for standalone MIPS programs.
7906 + *
7907 + * Copyright 2005, Broadcom Corporation
7908 + * All Rights Reserved.
7909 + *
7910 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7911 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7912 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7913 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7914 + *
7915 + * $Id$
7916 + */
7917 +
7918 +#ifndef _MISPINC_H
7919 +#define _MISPINC_H
7920 +
7921 +
7922 +/* MIPS defines */
7923 +
7924 +#ifdef _LANGUAGE_ASSEMBLY
7925 +
7926 +/*
7927 + * Symbolic register names for 32 bit ABI
7928 + */
7929 +#define zero $0 /* wired zero */
7930 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7931 +#define v0 $2 /* return value */
7932 +#define v1 $3
7933 +#define a0 $4 /* argument registers */
7934 +#define a1 $5
7935 +#define a2 $6
7936 +#define a3 $7
7937 +#define t0 $8 /* caller saved */
7938 +#define t1 $9
7939 +#define t2 $10
7940 +#define t3 $11
7941 +#define t4 $12
7942 +#define t5 $13
7943 +#define t6 $14
7944 +#define t7 $15
7945 +#define s0 $16 /* callee saved */
7946 +#define s1 $17
7947 +#define s2 $18
7948 +#define s3 $19
7949 +#define s4 $20
7950 +#define s5 $21
7951 +#define s6 $22
7952 +#define s7 $23
7953 +#define t8 $24 /* caller saved */
7954 +#define t9 $25
7955 +#define jp $25 /* PIC jump register */
7956 +#define k0 $26 /* kernel scratch */
7957 +#define k1 $27
7958 +#define gp $28 /* global pointer */
7959 +#define sp $29 /* stack pointer */
7960 +#define fp $30 /* frame pointer */
7961 +#define s8 $30 /* same like fp! */
7962 +#define ra $31 /* return address */
7963 +
7964 +
7965 +/*
7966 + * CP0 Registers
7967 + */
7968 +
7969 +#define C0_INX $0
7970 +#define C0_RAND $1
7971 +#define C0_TLBLO0 $2
7972 +#define C0_TLBLO C0_TLBLO0
7973 +#define C0_TLBLO1 $3
7974 +#define C0_CTEXT $4
7975 +#define C0_PGMASK $5
7976 +#define C0_WIRED $6
7977 +#define C0_BADVADDR $8
7978 +#define C0_COUNT $9
7979 +#define C0_TLBHI $10
7980 +#define C0_COMPARE $11
7981 +#define C0_SR $12
7982 +#define C0_STATUS C0_SR
7983 +#define C0_CAUSE $13
7984 +#define C0_EPC $14
7985 +#define C0_PRID $15
7986 +#define C0_CONFIG $16
7987 +#define C0_LLADDR $17
7988 +#define C0_WATCHLO $18
7989 +#define C0_WATCHHI $19
7990 +#define C0_XCTEXT $20
7991 +#define C0_DIAGNOSTIC $22
7992 +#define C0_BROADCOM C0_DIAGNOSTIC
7993 +#define C0_PERFORMANCE $25
7994 +#define C0_ECC $26
7995 +#define C0_CACHEERR $27
7996 +#define C0_TAGLO $28
7997 +#define C0_TAGHI $29
7998 +#define C0_ERREPC $30
7999 +#define C0_DESAVE $31
8000 +
8001 +/*
8002 + * LEAF - declare leaf routine
8003 + */
8004 +#define LEAF(symbol) \
8005 + .globl symbol; \
8006 + .align 2; \
8007 + .type symbol,@function; \
8008 + .ent symbol,0; \
8009 +symbol: .frame sp,0,ra
8010 +
8011 +/*
8012 + * END - mark end of function
8013 + */
8014 +#define END(function) \
8015 + .end function; \
8016 + .size function,.-function
8017 +
8018 +#define _ULCAST_
8019 +
8020 +#else
8021 +
8022 +/*
8023 + * The following macros are especially useful for __asm__
8024 + * inline assembler.
8025 + */
8026 +#ifndef __STR
8027 +#define __STR(x) #x
8028 +#endif
8029 +#ifndef STR
8030 +#define STR(x) __STR(x)
8031 +#endif
8032 +
8033 +#define _ULCAST_ (unsigned long)
8034 +
8035 +
8036 +/*
8037 + * CP0 Registers
8038 + */
8039 +
8040 +#define C0_INX 0 /* CP0: TLB Index */
8041 +#define C0_RAND 1 /* CP0: TLB Random */
8042 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
8043 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
8044 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
8045 +#define C0_CTEXT 4 /* CP0: Context */
8046 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
8047 +#define C0_WIRED 6 /* CP0: TLB Wired */
8048 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
8049 +#define C0_COUNT 9 /* CP0: Count */
8050 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
8051 +#define C0_COMPARE 11 /* CP0: Compare */
8052 +#define C0_SR 12 /* CP0: Processor Status */
8053 +#define C0_STATUS C0_SR /* CP0: Processor Status */
8054 +#define C0_CAUSE 13 /* CP0: Exception Cause */
8055 +#define C0_EPC 14 /* CP0: Exception PC */
8056 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
8057 +#define C0_CONFIG 16 /* CP0: Config */
8058 +#define C0_LLADDR 17 /* CP0: LLAddr */
8059 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
8060 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
8061 +#define C0_XCTEXT 20 /* CP0: XContext */
8062 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
8063 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
8064 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
8065 +#define C0_ECC 26 /* CP0: ECC */
8066 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8067 +#define C0_TAGLO 28 /* CP0: TagLo */
8068 +#define C0_TAGHI 29 /* CP0: TagHi */
8069 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8070 +#define C0_DESAVE 31 /* CP0: DebugSave */
8071 +
8072 +#endif /* _LANGUAGE_ASSEMBLY */
8073 +
8074 +/*
8075 + * Memory segments (32bit kernel mode addresses)
8076 + */
8077 +#undef KUSEG
8078 +#undef KSEG0
8079 +#undef KSEG1
8080 +#undef KSEG2
8081 +#undef KSEG3
8082 +#define KUSEG 0x00000000
8083 +#define KSEG0 0x80000000
8084 +#define KSEG1 0xa0000000
8085 +#define KSEG2 0xc0000000
8086 +#define KSEG3 0xe0000000
8087 +#define PHYSADDR_MASK 0x1fffffff
8088 +
8089 +/*
8090 + * Map an address to a certain kernel segment
8091 + */
8092 +#undef PHYSADDR
8093 +#undef KSEG0ADDR
8094 +#undef KSEG1ADDR
8095 +#undef KSEG2ADDR
8096 +#undef KSEG3ADDR
8097 +
8098 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8099 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8100 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8101 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8102 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8103 +
8104 +
8105 +#ifndef Index_Invalidate_I
8106 +/*
8107 + * Cache Operations
8108 + */
8109 +#define Index_Invalidate_I 0x00
8110 +#define Index_Writeback_Inv_D 0x01
8111 +#define Index_Invalidate_SI 0x02
8112 +#define Index_Writeback_Inv_SD 0x03
8113 +#define Index_Load_Tag_I 0x04
8114 +#define Index_Load_Tag_D 0x05
8115 +#define Index_Load_Tag_SI 0x06
8116 +#define Index_Load_Tag_SD 0x07
8117 +#define Index_Store_Tag_I 0x08
8118 +#define Index_Store_Tag_D 0x09
8119 +#define Index_Store_Tag_SI 0x0A
8120 +#define Index_Store_Tag_SD 0x0B
8121 +#define Create_Dirty_Excl_D 0x0d
8122 +#define Create_Dirty_Excl_SD 0x0f
8123 +#define Hit_Invalidate_I 0x10
8124 +#define Hit_Invalidate_D 0x11
8125 +#define Hit_Invalidate_SI 0x12
8126 +#define Hit_Invalidate_SD 0x13
8127 +#define Fill_I 0x14
8128 +#define Hit_Writeback_Inv_D 0x15
8129 + /* 0x16 is unused */
8130 +#define Hit_Writeback_Inv_SD 0x17
8131 +#define R5K_Page_Invalidate_S 0x17
8132 +#define Hit_Writeback_I 0x18
8133 +#define Hit_Writeback_D 0x19
8134 + /* 0x1a is unused */
8135 +#define Hit_Writeback_SD 0x1b
8136 + /* 0x1c is unused */
8137 + /* 0x1e is unused */
8138 +#define Hit_Set_Virtual_SI 0x1e
8139 +#define Hit_Set_Virtual_SD 0x1f
8140 +#endif
8141 +
8142 +
8143 +/*
8144 + * R4x00 interrupt enable / cause bits
8145 + */
8146 +#define IE_SW0 (_ULCAST_(1) << 8)
8147 +#define IE_SW1 (_ULCAST_(1) << 9)
8148 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8149 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8150 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8151 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8152 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8153 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8154 +
8155 +#ifndef ST0_UM
8156 +/*
8157 + * Bitfields in the mips32 cp0 status register
8158 + */
8159 +#define ST0_IE 0x00000001
8160 +#define ST0_EXL 0x00000002
8161 +#define ST0_ERL 0x00000004
8162 +#define ST0_UM 0x00000010
8163 +#define ST0_SWINT0 0x00000100
8164 +#define ST0_SWINT1 0x00000200
8165 +#define ST0_HWINT0 0x00000400
8166 +#define ST0_HWINT1 0x00000800
8167 +#define ST0_HWINT2 0x00001000
8168 +#define ST0_HWINT3 0x00002000
8169 +#define ST0_HWINT4 0x00004000
8170 +#define ST0_HWINT5 0x00008000
8171 +#define ST0_IM 0x0000ff00
8172 +#define ST0_NMI 0x00080000
8173 +#define ST0_SR 0x00100000
8174 +#define ST0_TS 0x00200000
8175 +#define ST0_BEV 0x00400000
8176 +#define ST0_RE 0x02000000
8177 +#define ST0_RP 0x08000000
8178 +#define ST0_CU 0xf0000000
8179 +#define ST0_CU0 0x10000000
8180 +#define ST0_CU1 0x20000000
8181 +#define ST0_CU2 0x40000000
8182 +#define ST0_CU3 0x80000000
8183 +#endif
8184 +
8185 +
8186 +/*
8187 + * Bitfields in the mips32 cp0 cause register
8188 + */
8189 +#define C_EXC 0x0000007c
8190 +#define C_EXC_SHIFT 2
8191 +#define C_INT 0x0000ff00
8192 +#define C_INT_SHIFT 8
8193 +#define C_SW0 (_ULCAST_(1) << 8)
8194 +#define C_SW1 (_ULCAST_(1) << 9)
8195 +#define C_IRQ0 (_ULCAST_(1) << 10)
8196 +#define C_IRQ1 (_ULCAST_(1) << 11)
8197 +#define C_IRQ2 (_ULCAST_(1) << 12)
8198 +#define C_IRQ3 (_ULCAST_(1) << 13)
8199 +#define C_IRQ4 (_ULCAST_(1) << 14)
8200 +#define C_IRQ5 (_ULCAST_(1) << 15)
8201 +#define C_WP 0x00400000
8202 +#define C_IV 0x00800000
8203 +#define C_CE 0x30000000
8204 +#define C_CE_SHIFT 28
8205 +#define C_BD 0x80000000
8206 +
8207 +/* Values in C_EXC */
8208 +#define EXC_INT 0
8209 +#define EXC_TLBM 1
8210 +#define EXC_TLBL 2
8211 +#define EXC_TLBS 3
8212 +#define EXC_AEL 4
8213 +#define EXC_AES 5
8214 +#define EXC_IBE 6
8215 +#define EXC_DBE 7
8216 +#define EXC_SYS 8
8217 +#define EXC_BPT 9
8218 +#define EXC_RI 10
8219 +#define EXC_CU 11
8220 +#define EXC_OV 12
8221 +#define EXC_TR 13
8222 +#define EXC_WATCH 23
8223 +#define EXC_MCHK 24
8224 +
8225 +
8226 +/*
8227 + * Bits in the cp0 config register.
8228 + */
8229 +#define CONF_CM_CACHABLE_NO_WA 0
8230 +#define CONF_CM_CACHABLE_WA 1
8231 +#define CONF_CM_UNCACHED 2
8232 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8233 +#define CONF_CM_CACHABLE_CE 4
8234 +#define CONF_CM_CACHABLE_COW 5
8235 +#define CONF_CM_CACHABLE_CUW 6
8236 +#define CONF_CM_CACHABLE_ACCELERATED 7
8237 +#define CONF_CM_CMASK 7
8238 +#define CONF_CU (_ULCAST_(1) << 3)
8239 +#define CONF_DB (_ULCAST_(1) << 4)
8240 +#define CONF_IB (_ULCAST_(1) << 5)
8241 +#define CONF_SE (_ULCAST_(1) << 12)
8242 +#define CONF_SC (_ULCAST_(1) << 17)
8243 +#define CONF_AC (_ULCAST_(1) << 23)
8244 +#define CONF_HALT (_ULCAST_(1) << 25)
8245 +
8246 +
8247 +/*
8248 + * Bits in the cp0 config register select 1.
8249 + */
8250 +#define CONF1_FP 0x00000001 /* FPU present */
8251 +#define CONF1_EP 0x00000002 /* EJTAG present */
8252 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8253 +#define CONF1_WR 0x00000008 /* Watch registers present */
8254 +#define CONF1_PC 0x00000010 /* Performance counters present */
8255 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8256 +#define CONF1_DA_MASK 0x00000380
8257 +#define CONF1_DA_BASE 1
8258 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8259 +#define CONF1_DL_MASK 0x00001c00
8260 +#define CONF1_DL_BASE 2
8261 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8262 +#define CONF1_DS_MASK 0x0000e000
8263 +#define CONF1_DS_BASE 64
8264 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8265 +#define CONF1_IA_MASK 0x00070000
8266 +#define CONF1_IA_BASE 1
8267 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8268 +#define CONF1_IL_MASK 0x00380000
8269 +#define CONF1_IL_BASE 2
8270 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8271 +#define CONF1_IS_MASK 0x01c00000
8272 +#define CONF1_IS_BASE 64
8273 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8274 +#define CONF1_MS_SHIFT 25
8275 +
8276 +/* PRID register */
8277 +#define PRID_COPT_MASK 0xff000000
8278 +#define PRID_COMP_MASK 0x00ff0000
8279 +#define PRID_IMP_MASK 0x0000ff00
8280 +#define PRID_REV_MASK 0x000000ff
8281 +
8282 +#define PRID_COMP_LEGACY 0x000000
8283 +#define PRID_COMP_MIPS 0x010000
8284 +#define PRID_COMP_BROADCOM 0x020000
8285 +#define PRID_COMP_ALCHEMY 0x030000
8286 +#define PRID_COMP_SIBYTE 0x040000
8287 +#define PRID_IMP_BCM4710 0x4000
8288 +#define PRID_IMP_BCM3302 0x9000
8289 +#define PRID_IMP_BCM3303 0x9100
8290 +
8291 +#define PRID_IMP_UNKNOWN 0xff00
8292 +
8293 +#define BCM330X(id) \
8294 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8295 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8296 +
8297 +/* Bits in C0_BROADCOM */
8298 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8299 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8300 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8301 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8302 +
8303 +/* PreFetch Cache aka Read Ahead Cache */
8304 +
8305 +#define PFC_CR0 0xff400000 /* control reg 0 */
8306 +#define PFC_CR1 0xff400004 /* control reg 1 */
8307 +
8308 +/* PFC operations */
8309 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8310 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8311 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8312 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8313 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8314 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8315 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8316 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8317 +#define PFC_BRR 0x40000000 /* Bus error indication */
8318 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8319 +
8320 +/* Handy defaults */
8321 +#define PFC_DISABLED 0
8322 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8323 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8324 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8325 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8326 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8327 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8328 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8329 +
8330 +
8331 +/*
8332 + * These are the UART port assignments, expressed as offsets from the base
8333 + * register. These assignments should hold for any serial port based on
8334 + * a 8250, 16450, or 16550(A).
8335 + */
8336 +
8337 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8338 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8339 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8340 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8341 +#define UART_LCR 3 /* Out: Line Control Register */
8342 +#define UART_MCR 4 /* Out: Modem Control Register */
8343 +#define UART_LSR 5 /* In: Line Status Register */
8344 +#define UART_MSR 6 /* In: Modem Status Register */
8345 +#define UART_SCR 7 /* I/O: Scratch Register */
8346 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8347 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8348 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8349 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8350 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8351 +
8352 +
8353 +#ifndef _LANGUAGE_ASSEMBLY
8354 +
8355 +/*
8356 + * Macros to access the system control coprocessor
8357 + */
8358 +
8359 +#define MFC0(source, sel) \
8360 +({ \
8361 + int __res; \
8362 + __asm__ __volatile__( \
8363 + ".set\tnoreorder\n\t" \
8364 + ".set\tnoat\n\t" \
8365 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8366 + "move\t%0,$1\n\t" \
8367 + ".set\tat\n\t" \
8368 + ".set\treorder" \
8369 + :"=r" (__res) \
8370 + : \
8371 + :"$1"); \
8372 + __res; \
8373 +})
8374 +
8375 +#define MTC0(source, sel, value) \
8376 +do { \
8377 + __asm__ __volatile__( \
8378 + ".set\tnoreorder\n\t" \
8379 + ".set\tnoat\n\t" \
8380 + "move\t$1,%z0\n\t" \
8381 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8382 + ".set\tat\n\t" \
8383 + ".set\treorder" \
8384 + : \
8385 + :"jr" (value) \
8386 + :"$1"); \
8387 +} while (0)
8388 +
8389 +#define get_c0_count() \
8390 +({ \
8391 + int __res; \
8392 + __asm__ __volatile__( \
8393 + ".set\tnoreorder\n\t" \
8394 + ".set\tnoat\n\t" \
8395 + "mfc0\t%0,$9\n\t" \
8396 + ".set\tat\n\t" \
8397 + ".set\treorder" \
8398 + :"=r" (__res)); \
8399 + __res; \
8400 +})
8401 +
8402 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8403 +{
8404 + uint lsz, sets, ways;
8405 +
8406 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8407 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8408 + lsz = CONF1_IL_BASE << lsz;
8409 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8410 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8411 + *size = lsz * sets * ways;
8412 + *lsize = lsz;
8413 +}
8414 +
8415 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8416 +{
8417 + uint lsz, sets, ways;
8418 +
8419 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8420 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8421 + lsz = CONF1_DL_BASE << lsz;
8422 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8423 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8424 + *size = lsz * sets * ways;
8425 + *lsize = lsz;
8426 +}
8427 +
8428 +#define cache_op(base, op) \
8429 + __asm__ __volatile__(" \
8430 + .set noreorder; \
8431 + .set mips3; \
8432 + cache %1, (%0); \
8433 + .set mips0; \
8434 + .set reorder" \
8435 + : \
8436 + : "r" (base), \
8437 + "i" (op));
8438 +
8439 +#define cache_unroll4(base, delta, op) \
8440 + __asm__ __volatile__(" \
8441 + .set noreorder; \
8442 + .set mips3; \
8443 + cache %1,0(%0); \
8444 + cache %1,delta(%0); \
8445 + cache %1,(2 * delta)(%0); \
8446 + cache %1,(3 * delta)(%0); \
8447 + .set mips0; \
8448 + .set reorder" \
8449 + : \
8450 + : "r" (base), \
8451 + "i" (op));
8452 +
8453 +#endif /* !_LANGUAGE_ASSEMBLY */
8454 +
8455 +#endif /* _MISPINC_H */
8456 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8457 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8458 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-15 23:29:14.000000000 +0200
8459 @@ -0,0 +1,42 @@
8460 +/*
8461 + * OS Abstraction Layer
8462 + *
8463 + * Copyright 2005, Broadcom Corporation
8464 + * All Rights Reserved.
8465 + *
8466 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8467 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8468 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8469 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8470 + * $Id$
8471 + */
8472 +
8473 +#ifndef _osl_h_
8474 +#define _osl_h_
8475 +
8476 +/* osl handle type forward declaration */
8477 +typedef struct os_handle osl_t;
8478 +
8479 +#if defined(linux)
8480 +#include <linux_osl.h>
8481 +#elif defined(NDIS)
8482 +#include <ndis_osl.h>
8483 +#elif defined(_CFE_)
8484 +#include <cfe_osl.h>
8485 +#elif defined(_HNDRTE_)
8486 +#include <hndrte_osl.h>
8487 +#elif defined(_MINOSL_)
8488 +#include <min_osl.h>
8489 +#elif PMON
8490 +#include <pmon_osl.h>
8491 +#elif defined(MACOSX)
8492 +#include <macosx_osl.h>
8493 +#else
8494 +#error "Unsupported OSL requested"
8495 +#endif
8496 +
8497 +/* handy */
8498 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8499 +#define MAXPRIO 7 /* 0-7 */
8500 +
8501 +#endif /* _osl_h_ */
8502 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8503 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8504 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-15 23:29:14.000000000 +0200
8505 @@ -0,0 +1,398 @@
8506 +/*
8507 + * pcicfg.h: PCI configuration constants and structures.
8508 + *
8509 + * Copyright 2005, Broadcom Corporation
8510 + * All Rights Reserved.
8511 + *
8512 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8513 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8514 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8515 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8516 + *
8517 + * $Id$
8518 + */
8519 +
8520 +#ifndef _h_pci_
8521 +#define _h_pci_
8522 +
8523 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8524 +#ifndef PCI_MAX_BUS
8525 +#define PCI_MAX_BUS 0x100
8526 +#endif
8527 +#ifndef PCI_MAX_DEVICES
8528 +#define PCI_MAX_DEVICES 0x20
8529 +#endif
8530 +#ifndef PCI_MAX_FUNCTION
8531 +#define PCI_MAX_FUNCTION 0x8
8532 +#endif
8533 +
8534 +#ifndef PCI_INVALID_VENDORID
8535 +#define PCI_INVALID_VENDORID 0xffff
8536 +#endif
8537 +#ifndef PCI_INVALID_DEVICEID
8538 +#define PCI_INVALID_DEVICEID 0xffff
8539 +#endif
8540 +
8541 +
8542 +/* Convert between bus-slot-function-register and config addresses */
8543 +
8544 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8545 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8546 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8547 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8548 +
8549 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8550 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8551 +#define PCICFG_FUN_MASK 7 /* Function mask */
8552 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8553 +
8554 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8555 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8556 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8557 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8558 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8559 +
8560 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8561 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8562 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8563 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8564 +
8565 +/* The actual config space */
8566 +
8567 +#define PCI_BAR_MAX 6
8568 +
8569 +#define PCI_ROM_BAR 8
8570 +
8571 +#define PCR_RSVDA_MAX 2
8572 +
8573 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8574 +
8575 +#define PCI_CAPPTR_PRESENT 0x0010
8576 +
8577 +typedef struct _pci_config_regs {
8578 + unsigned short vendor;
8579 + unsigned short device;
8580 + unsigned short command;
8581 + unsigned short status;
8582 + unsigned char rev_id;
8583 + unsigned char prog_if;
8584 + unsigned char sub_class;
8585 + unsigned char base_class;
8586 + unsigned char cache_line_size;
8587 + unsigned char latency_timer;
8588 + unsigned char header_type;
8589 + unsigned char bist;
8590 + unsigned long base[PCI_BAR_MAX];
8591 + unsigned long cardbus_cis;
8592 + unsigned short subsys_vendor;
8593 + unsigned short subsys_id;
8594 + unsigned long baserom;
8595 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8596 + unsigned char int_line;
8597 + unsigned char int_pin;
8598 + unsigned char min_gnt;
8599 + unsigned char max_lat;
8600 + unsigned char dev_dep[192];
8601 +} pci_config_regs;
8602 +
8603 +#define SZPCR (sizeof (pci_config_regs))
8604 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8605 +
8606 +/* A structure for the config registers is nice, but in most
8607 + * systems the config space is not memory mapped, so we need
8608 + * filed offsetts. :-(
8609 + */
8610 +#define PCI_CFG_VID 0
8611 +#define PCI_CFG_DID 2
8612 +#define PCI_CFG_CMD 4
8613 +#define PCI_CFG_STAT 6
8614 +#define PCI_CFG_REV 8
8615 +#define PCI_CFG_PROGIF 9
8616 +#define PCI_CFG_SUBCL 0xa
8617 +#define PCI_CFG_BASECL 0xb
8618 +#define PCI_CFG_CLSZ 0xc
8619 +#define PCI_CFG_LATTIM 0xd
8620 +#define PCI_CFG_HDR 0xe
8621 +#define PCI_CFG_BIST 0xf
8622 +#define PCI_CFG_BAR0 0x10
8623 +#define PCI_CFG_BAR1 0x14
8624 +#define PCI_CFG_BAR2 0x18
8625 +#define PCI_CFG_BAR3 0x1c
8626 +#define PCI_CFG_BAR4 0x20
8627 +#define PCI_CFG_BAR5 0x24
8628 +#define PCI_CFG_CIS 0x28
8629 +#define PCI_CFG_SVID 0x2c
8630 +#define PCI_CFG_SSID 0x2e
8631 +#define PCI_CFG_ROMBAR 0x30
8632 +#define PCI_CFG_CAPPTR 0x34
8633 +#define PCI_CFG_INT 0x3c
8634 +#define PCI_CFG_PIN 0x3d
8635 +#define PCI_CFG_MINGNT 0x3e
8636 +#define PCI_CFG_MAXLAT 0x3f
8637 +
8638 +/* Classes and subclasses */
8639 +
8640 +typedef enum {
8641 + PCI_CLASS_OLD = 0,
8642 + PCI_CLASS_DASDI,
8643 + PCI_CLASS_NET,
8644 + PCI_CLASS_DISPLAY,
8645 + PCI_CLASS_MMEDIA,
8646 + PCI_CLASS_MEMORY,
8647 + PCI_CLASS_BRIDGE,
8648 + PCI_CLASS_COMM,
8649 + PCI_CLASS_BASE,
8650 + PCI_CLASS_INPUT,
8651 + PCI_CLASS_DOCK,
8652 + PCI_CLASS_CPU,
8653 + PCI_CLASS_SERIAL,
8654 + PCI_CLASS_INTELLIGENT = 0xe,
8655 + PCI_CLASS_SATELLITE,
8656 + PCI_CLASS_CRYPT,
8657 + PCI_CLASS_DSP,
8658 + PCI_CLASS_MAX
8659 +} pci_classes;
8660 +
8661 +typedef enum {
8662 + PCI_DASDI_SCSI,
8663 + PCI_DASDI_IDE,
8664 + PCI_DASDI_FLOPPY,
8665 + PCI_DASDI_IPI,
8666 + PCI_DASDI_RAID,
8667 + PCI_DASDI_OTHER = 0x80
8668 +} pci_dasdi_subclasses;
8669 +
8670 +typedef enum {
8671 + PCI_NET_ETHER,
8672 + PCI_NET_TOKEN,
8673 + PCI_NET_FDDI,
8674 + PCI_NET_ATM,
8675 + PCI_NET_OTHER = 0x80
8676 +} pci_net_subclasses;
8677 +
8678 +typedef enum {
8679 + PCI_DISPLAY_VGA,
8680 + PCI_DISPLAY_XGA,
8681 + PCI_DISPLAY_3D,
8682 + PCI_DISPLAY_OTHER = 0x80
8683 +} pci_display_subclasses;
8684 +
8685 +typedef enum {
8686 + PCI_MMEDIA_VIDEO,
8687 + PCI_MMEDIA_AUDIO,
8688 + PCI_MMEDIA_PHONE,
8689 + PCI_MEDIA_OTHER = 0x80
8690 +} pci_mmedia_subclasses;
8691 +
8692 +typedef enum {
8693 + PCI_MEMORY_RAM,
8694 + PCI_MEMORY_FLASH,
8695 + PCI_MEMORY_OTHER = 0x80
8696 +} pci_memory_subclasses;
8697 +
8698 +typedef enum {
8699 + PCI_BRIDGE_HOST,
8700 + PCI_BRIDGE_ISA,
8701 + PCI_BRIDGE_EISA,
8702 + PCI_BRIDGE_MC,
8703 + PCI_BRIDGE_PCI,
8704 + PCI_BRIDGE_PCMCIA,
8705 + PCI_BRIDGE_NUBUS,
8706 + PCI_BRIDGE_CARDBUS,
8707 + PCI_BRIDGE_RACEWAY,
8708 + PCI_BRIDGE_OTHER = 0x80
8709 +} pci_bridge_subclasses;
8710 +
8711 +typedef enum {
8712 + PCI_COMM_UART,
8713 + PCI_COMM_PARALLEL,
8714 + PCI_COMM_MULTIUART,
8715 + PCI_COMM_MODEM,
8716 + PCI_COMM_OTHER = 0x80
8717 +} pci_comm_subclasses;
8718 +
8719 +typedef enum {
8720 + PCI_BASE_PIC,
8721 + PCI_BASE_DMA,
8722 + PCI_BASE_TIMER,
8723 + PCI_BASE_RTC,
8724 + PCI_BASE_PCI_HOTPLUG,
8725 + PCI_BASE_OTHER = 0x80
8726 +} pci_base_subclasses;
8727 +
8728 +typedef enum {
8729 + PCI_INPUT_KBD,
8730 + PCI_INPUT_PEN,
8731 + PCI_INPUT_MOUSE,
8732 + PCI_INPUT_SCANNER,
8733 + PCI_INPUT_GAMEPORT,
8734 + PCI_INPUT_OTHER = 0x80
8735 +} pci_input_subclasses;
8736 +
8737 +typedef enum {
8738 + PCI_DOCK_GENERIC,
8739 + PCI_DOCK_OTHER = 0x80
8740 +} pci_dock_subclasses;
8741 +
8742 +typedef enum {
8743 + PCI_CPU_386,
8744 + PCI_CPU_486,
8745 + PCI_CPU_PENTIUM,
8746 + PCI_CPU_ALPHA = 0x10,
8747 + PCI_CPU_POWERPC = 0x20,
8748 + PCI_CPU_MIPS = 0x30,
8749 + PCI_CPU_COPROC = 0x40,
8750 + PCI_CPU_OTHER = 0x80
8751 +} pci_cpu_subclasses;
8752 +
8753 +typedef enum {
8754 + PCI_SERIAL_IEEE1394,
8755 + PCI_SERIAL_ACCESS,
8756 + PCI_SERIAL_SSA,
8757 + PCI_SERIAL_USB,
8758 + PCI_SERIAL_FIBER,
8759 + PCI_SERIAL_SMBUS,
8760 + PCI_SERIAL_OTHER = 0x80
8761 +} pci_serial_subclasses;
8762 +
8763 +typedef enum {
8764 + PCI_INTELLIGENT_I2O,
8765 +} pci_intelligent_subclasses;
8766 +
8767 +typedef enum {
8768 + PCI_SATELLITE_TV,
8769 + PCI_SATELLITE_AUDIO,
8770 + PCI_SATELLITE_VOICE,
8771 + PCI_SATELLITE_DATA,
8772 + PCI_SATELLITE_OTHER = 0x80
8773 +} pci_satellite_subclasses;
8774 +
8775 +typedef enum {
8776 + PCI_CRYPT_NETWORK,
8777 + PCI_CRYPT_ENTERTAINMENT,
8778 + PCI_CRYPT_OTHER = 0x80
8779 +} pci_crypt_subclasses;
8780 +
8781 +typedef enum {
8782 + PCI_DSP_DPIO,
8783 + PCI_DSP_OTHER = 0x80
8784 +} pci_dsp_subclasses;
8785 +
8786 +/* Header types */
8787 +typedef enum {
8788 + PCI_HEADER_NORMAL,
8789 + PCI_HEADER_BRIDGE,
8790 + PCI_HEADER_CARDBUS
8791 +} pci_header_types;
8792 +
8793 +
8794 +/* Overlay for a PCI-to-PCI bridge */
8795 +
8796 +#define PPB_RSVDA_MAX 2
8797 +#define PPB_RSVDD_MAX 8
8798 +
8799 +typedef struct _ppb_config_regs {
8800 + unsigned short vendor;
8801 + unsigned short device;
8802 + unsigned short command;
8803 + unsigned short status;
8804 + unsigned char rev_id;
8805 + unsigned char prog_if;
8806 + unsigned char sub_class;
8807 + unsigned char base_class;
8808 + unsigned char cache_line_size;
8809 + unsigned char latency_timer;
8810 + unsigned char header_type;
8811 + unsigned char bist;
8812 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8813 + unsigned char prim_bus;
8814 + unsigned char sec_bus;
8815 + unsigned char sub_bus;
8816 + unsigned char sec_lat;
8817 + unsigned char io_base;
8818 + unsigned char io_lim;
8819 + unsigned short sec_status;
8820 + unsigned short mem_base;
8821 + unsigned short mem_lim;
8822 + unsigned short pf_mem_base;
8823 + unsigned short pf_mem_lim;
8824 + unsigned long pf_mem_base_hi;
8825 + unsigned long pf_mem_lim_hi;
8826 + unsigned short io_base_hi;
8827 + unsigned short io_lim_hi;
8828 + unsigned short subsys_vendor;
8829 + unsigned short subsys_id;
8830 + unsigned long rsvd_b;
8831 + unsigned char rsvd_c;
8832 + unsigned char int_pin;
8833 + unsigned short bridge_ctrl;
8834 + unsigned char chip_ctrl;
8835 + unsigned char diag_ctrl;
8836 + unsigned short arb_ctrl;
8837 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8838 + unsigned char dev_dep[192];
8839 +} ppb_config_regs;
8840 +
8841 +
8842 +/* PCI CAPABILITY DEFINES */
8843 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8844 +#define PCI_CAP_MSICAP_ID 0x05
8845 +
8846 +/* Data structure to define the Message Signalled Interrupt facility
8847 + * Valid for PCI and PCIE configurations */
8848 +typedef struct _pciconfig_cap_msi {
8849 + unsigned char capID;
8850 + unsigned char nextptr;
8851 + unsigned short msgctrl;
8852 + unsigned int msgaddr;
8853 +} pciconfig_cap_msi;
8854 +
8855 +/* Data structure to define the Power managment facility
8856 + * Valid for PCI and PCIE configurations */
8857 +typedef struct _pciconfig_cap_pwrmgmt {
8858 + unsigned char capID;
8859 + unsigned char nextptr;
8860 + unsigned short pme_cap;
8861 + unsigned short pme_sts_ctrl;
8862 + unsigned char pme_bridge_ext;
8863 + unsigned char data;
8864 +} pciconfig_cap_pwrmgmt;
8865 +
8866 +/* Everything below is BRCM HND proprietary */
8867 +
8868 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8869 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8870 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8871 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8872 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8873 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8874 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8875 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8876 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8877 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8878 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8879 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8880 +
8881 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8882 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8883 +
8884 +/* PCI_INT_STATUS */
8885 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8886 +
8887 +/* PCI_INT_MASK */
8888 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8889 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8890 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8891 +
8892 +/* PCI_SPROM_CONTROL */
8893 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8894 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8895 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8896 +
8897 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8898 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8899 +
8900 +/* PCI_CFG_CMD_STAT */
8901 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8902 +
8903 +#endif
8904 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8905 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8906 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2006-10-15 23:29:14.000000000 +0200
8907 @@ -0,0 +1,145 @@
8908 +/*******************************************************************************
8909 + * $Id$
8910 + * Copyright 2001-2003, Broadcom Corporation
8911 + * All Rights Reserved.
8912 + *
8913 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8914 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8915 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8916 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8917 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8918 + ******************************************************************************/
8919 +
8920 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8921 +#define _NET_ETHERNET_H_
8922 +
8923 +#ifndef _TYPEDEFS_H_
8924 +#include "typedefs.h"
8925 +#endif
8926 +
8927 +#if defined(__GNUC__)
8928 +#define PACKED __attribute__((packed))
8929 +#else
8930 +#define PACKED
8931 +#endif
8932 +
8933 +/*
8934 + * The number of bytes in an ethernet (MAC) address.
8935 + */
8936 +#define ETHER_ADDR_LEN 6
8937 +
8938 +/*
8939 + * The number of bytes in the type field.
8940 + */
8941 +#define ETHER_TYPE_LEN 2
8942 +
8943 +/*
8944 + * The number of bytes in the trailing CRC field.
8945 + */
8946 +#define ETHER_CRC_LEN 4
8947 +
8948 +/*
8949 + * The length of the combined header.
8950 + */
8951 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8952 +
8953 +/*
8954 + * The minimum packet length.
8955 + */
8956 +#define ETHER_MIN_LEN 64
8957 +
8958 +/*
8959 + * The minimum packet user data length.
8960 + */
8961 +#define ETHER_MIN_DATA 46
8962 +
8963 +/*
8964 + * The maximum packet length.
8965 + */
8966 +#define ETHER_MAX_LEN 1518
8967 +
8968 +/*
8969 + * The maximum packet user data length.
8970 + */
8971 +#define ETHER_MAX_DATA 1500
8972 +
8973 +/*
8974 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8975 + */
8976 +#define VLAN_TAG 0x8100
8977 +
8978 +/*
8979 + * Located after dest & src address in ether header.
8980 + */
8981 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8982 +
8983 +/*
8984 + * 4 bytes of vlan field info.
8985 + */
8986 +#define VLAN_FIELDS_SIZE 4
8987 +
8988 +/* location of pri bits in 16-bit vlan fields */
8989 +#define VLAN_PRI_SHIFT 13
8990 +
8991 +/* 3 bits of priority */
8992 +#define VLAN_PRI_MASK 7
8993 +
8994 +/* 802.1X ethertype */
8995 +#define ETHER_TYPE_802_1X 0x888e
8996 +
8997 +/*
8998 + * A macro to validate a length with
8999 + */
9000 +#define ETHER_IS_VALID_LEN(foo) \
9001 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
9002 +
9003 +
9004 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
9005 +/*
9006 + * Structure of a 10Mb/s Ethernet header.
9007 + */
9008 +struct ether_header {
9009 + uint8 ether_dhost[ETHER_ADDR_LEN];
9010 + uint8 ether_shost[ETHER_ADDR_LEN];
9011 + uint16 ether_type;
9012 +} PACKED ;
9013 +
9014 +/*
9015 + * Structure of a 48-bit Ethernet address.
9016 + */
9017 +struct ether_addr {
9018 + uint8 octet[ETHER_ADDR_LEN];
9019 +} PACKED ;
9020 +#endif
9021 +
9022 +/*
9023 + * Takes a pointer, returns true if a 48-bit multicast address
9024 + * (including broadcast, since it is all ones)
9025 + */
9026 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
9027 +
9028 +/*
9029 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
9030 + */
9031 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9032 + ((uint8 *)(ea))[1] & \
9033 + ((uint8 *)(ea))[2] & \
9034 + ((uint8 *)(ea))[3] & \
9035 + ((uint8 *)(ea))[4] & \
9036 + ((uint8 *)(ea))[5]) == 0xff)
9037 +
9038 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9039 +
9040 +/*
9041 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9042 + */
9043 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9044 + ((uint8 *)(ea))[1] | \
9045 + ((uint8 *)(ea))[2] | \
9046 + ((uint8 *)(ea))[3] | \
9047 + ((uint8 *)(ea))[4] | \
9048 + ((uint8 *)(ea))[5]) == 0)
9049 +
9050 +#undef PACKED
9051 +
9052 +#endif /* _NET_ETHERNET_H_ */
9053 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
9054 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9055 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2006-10-15 23:29:14.000000000 +0200
9056 @@ -0,0 +1,103 @@
9057 +#ifndef _S5_H_
9058 +#define _S5_H_
9059 +/*
9060 + * Copyright 2003, Broadcom Corporation
9061 + * All Rights Reserved.
9062 + *
9063 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9064 + * and MIPS3301 (R4K) System Address Space
9065 + *
9066 + * This program is free software; you can redistribute it and/or
9067 + * modify it under the terms of the GNU General Public License as
9068 + * published by the Free Software Foundation, located in the file
9069 + * LICENSE.
9070 + *
9071 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9072 + *
9073 + */
9074 +
9075 +/* BCM5365 Address map */
9076 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9077 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9078 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9079 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9080 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9081 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9082 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9083 +
9084 +/* BCM5365 Core register space */
9085 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9086 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9087 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9088 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9089 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9090 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9091 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9092 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9093 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9094 +
9095 +/* COM Ports 1/2 */
9096 +#define BCM5365_UART (BCM5365_REG_UARTS)
9097 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9098 +
9099 +/* Registers common to MIPS33 Core used in 5365 */
9100 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9101 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9102 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9103 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9104 +
9105 +/* Internal Core Sonics Backplane Devices */
9106 +#define INTERNAL_UART_COM1 BCM5365_UART
9107 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9108 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9109 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9110 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9111 +#define SB_REG_USB BCM5365_REG_USB
9112 +#define SB_REG_PCI BCM5365_REG_PCI
9113 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9114 +#define SB_REG_MEMC BCM5365_REG_MEMC
9115 +#define SB_REG_MEMC_OFF 0x6000
9116 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9117 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9118 +
9119 +/*
9120 + * XXX
9121 + * 5365-specific backplane interrupt flag numbers. This should be done
9122 + * dynamically instead.
9123 + */
9124 +#define SBFLAG_PCI 0
9125 +#define SBFLAG_ENET0 1
9126 +#define SBFLAG_ILINE20 2
9127 +#define SBFLAG_CODEC 3
9128 +#define SBFLAG_USB 4
9129 +#define SBFLAG_EXTIF 5
9130 +#define SBFLAG_ENET1 6
9131 +
9132 +/* BCM95365 Local Bus devices */
9133 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9134 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9135 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9136 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9137 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9138 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9139 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9140 +
9141 +/* Write to DLR2416 VFD Display character RAM */
9142 +#define LED_REG(x) \
9143 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9144 +
9145 +#ifdef CONFIG_VSIM
9146 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9147 + } while (0)
9148 +#else
9149 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9150 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9151 + *((int *)0xa0002ff8) = (trval); } while (0)
9152 +#endif
9153 +
9154 +/* BCM9536R Local Bus devices */
9155 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9156 +
9157 +
9158 +
9159 +#endif /*!_S5_H_ */
9160 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9161 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9162 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-15 23:29:14.000000000 +0200
9163 @@ -0,0 +1,440 @@
9164 +/*
9165 + * SiliconBackplane Chipcommon core hardware definitions.
9166 + *
9167 + * The chipcommon core provides chip identification, SB control,
9168 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9169 + * gpio interface, extbus, and support for serial and parallel flashes.
9170 + *
9171 + * $Id$
9172 + * Copyright 2005, Broadcom Corporation
9173 + * All Rights Reserved.
9174 + *
9175 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9176 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9177 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9178 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9179 + *
9180 + */
9181 +
9182 +#ifndef _SBCHIPC_H
9183 +#define _SBCHIPC_H
9184 +
9185 +
9186 +#ifndef _LANGUAGE_ASSEMBLY
9187 +
9188 +/* cpp contortions to concatenate w/arg prescan */
9189 +#ifndef PAD
9190 +#define _PADLINE(line) pad ## line
9191 +#define _XSTR(line) _PADLINE(line)
9192 +#define PAD _XSTR(__LINE__)
9193 +#endif /* PAD */
9194 +
9195 +typedef volatile struct {
9196 + uint32 chipid; /* 0x0 */
9197 + uint32 capabilities;
9198 + uint32 corecontrol; /* corerev >= 1 */
9199 + uint32 bist;
9200 +
9201 + /* OTP */
9202 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9203 + uint32 otpcontrol;
9204 + uint32 otpprog;
9205 + uint32 PAD;
9206 +
9207 + /* Interrupt control */
9208 + uint32 intstatus; /* 0x20 */
9209 + uint32 intmask;
9210 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9211 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9212 +
9213 + /* Jtag Master */
9214 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9215 + uint32 jtagir;
9216 + uint32 jtagdr;
9217 + uint32 jtagctrl;
9218 +
9219 + /* serial flash interface registers */
9220 + uint32 flashcontrol; /* 0x40 */
9221 + uint32 flashaddress;
9222 + uint32 flashdata;
9223 + uint32 PAD[1];
9224 +
9225 + /* Silicon backplane configuration broadcast control */
9226 + uint32 broadcastaddress; /* 0x50 */
9227 + uint32 broadcastdata;
9228 + uint32 PAD[2];
9229 +
9230 + /* gpio - cleared only by power-on-reset */
9231 + uint32 gpioin; /* 0x60 */
9232 + uint32 gpioout;
9233 + uint32 gpioouten;
9234 + uint32 gpiocontrol;
9235 + uint32 gpiointpolarity;
9236 + uint32 gpiointmask;
9237 + uint32 PAD[2];
9238 +
9239 + /* Watchdog timer */
9240 + uint32 watchdog; /* 0x80 */
9241 + uint32 PAD[1];
9242 +
9243 + /*GPIO based LED powersave registers corerev >= 16*/
9244 + uint32 gpiotimerval; /*0x88 */
9245 + uint32 gpiotimeroutmask;
9246 +
9247 + /* clock control */
9248 + uint32 clockcontrol_n; /* 0x90 */
9249 + uint32 clockcontrol_sb; /* aka m0 */
9250 + uint32 clockcontrol_pci; /* aka m1 */
9251 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9252 + uint32 clockcontrol_mips; /* aka m3 */
9253 + uint32 clkdiv; /* corerev >= 3 */
9254 + uint32 PAD[2];
9255 +
9256 + /* pll delay registers (corerev >= 4) */
9257 + uint32 pll_on_delay; /* 0xb0 */
9258 + uint32 fref_sel_delay;
9259 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9260 + uint32 PAD[1];
9261 +
9262 + /* Instaclock registers (corerev >= 10) */
9263 + uint32 system_clk_ctl; /* 0xc0 */
9264 + uint32 clkstatestretch;
9265 + uint32 PAD[14];
9266 +
9267 + /* ExtBus control registers (corerev >= 3) */
9268 + uint32 pcmcia_config; /* 0x100 */
9269 + uint32 pcmcia_memwait;
9270 + uint32 pcmcia_attrwait;
9271 + uint32 pcmcia_iowait;
9272 + uint32 ide_config;
9273 + uint32 ide_memwait;
9274 + uint32 ide_attrwait;
9275 + uint32 ide_iowait;
9276 + uint32 prog_config;
9277 + uint32 prog_waitcount;
9278 + uint32 flash_config;
9279 + uint32 flash_waitcount;
9280 + uint32 PAD[116];
9281 +
9282 + /* uarts */
9283 + uint8 uart0data; /* 0x300 */
9284 + uint8 uart0imr;
9285 + uint8 uart0fcr;
9286 + uint8 uart0lcr;
9287 + uint8 uart0mcr;
9288 + uint8 uart0lsr;
9289 + uint8 uart0msr;
9290 + uint8 uart0scratch;
9291 + uint8 PAD[248]; /* corerev >= 1 */
9292 +
9293 + uint8 uart1data; /* 0x400 */
9294 + uint8 uart1imr;
9295 + uint8 uart1fcr;
9296 + uint8 uart1lcr;
9297 + uint8 uart1mcr;
9298 + uint8 uart1lsr;
9299 + uint8 uart1msr;
9300 + uint8 uart1scratch;
9301 +} chipcregs_t;
9302 +
9303 +#endif /* _LANGUAGE_ASSEMBLY */
9304 +
9305 +#define CC_CHIPID 0
9306 +#define CC_CAPABILITIES 4
9307 +#define CC_JTAGCMD 0x30
9308 +#define CC_JTAGIR 0x34
9309 +#define CC_JTAGDR 0x38
9310 +#define CC_JTAGCTRL 0x3c
9311 +#define CC_WATCHDOG 0x80
9312 +#define CC_CLKC_N 0x90
9313 +#define CC_CLKC_M0 0x94
9314 +#define CC_CLKC_M1 0x98
9315 +#define CC_CLKC_M2 0x9c
9316 +#define CC_CLKC_M3 0xa0
9317 +#define CC_CLKDIV 0xa4
9318 +#define CC_SYS_CLK_CTL 0xc0
9319 +#define CC_OTP 0x800
9320 +
9321 +/* chipid */
9322 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9323 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9324 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9325 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9326 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9327 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9328 +#define CID_CC_SHIFT 24
9329 +
9330 +/* capabilities */
9331 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9332 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9333 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9334 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9335 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9336 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9337 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9338 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9339 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9340 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9341 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9342 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9343 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9344 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9345 +
9346 +/* PLL type */
9347 +#define PLL_NONE 0x00000000
9348 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9349 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9350 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9351 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9352 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9353 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9354 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9355 +
9356 +/* corecontrol */
9357 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9358 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9359 +
9360 +/* Fields in the otpstatus register */
9361 +#define OTPS_PROGFAIL 0x80000000
9362 +#define OTPS_PROTECT 0x00000007
9363 +#define OTPS_HW_PROTECT 0x00000001
9364 +#define OTPS_SW_PROTECT 0x00000002
9365 +#define OTPS_CID_PROTECT 0x00000004
9366 +
9367 +/* Fields in the otpcontrol register */
9368 +#define OTPC_RECWAIT 0xff000000
9369 +#define OTPC_PROGWAIT 0x00ffff00
9370 +#define OTPC_PRW_SHIFT 8
9371 +#define OTPC_MAXFAIL 0x00000038
9372 +#define OTPC_VSEL 0x00000006
9373 +#define OTPC_SELVL 0x00000001
9374 +
9375 +/* Fields in otpprog */
9376 +#define OTPP_COL_MASK 0x000000ff
9377 +#define OTPP_ROW_MASK 0x0000ff00
9378 +#define OTPP_ROW_SHIFT 8
9379 +#define OTPP_READERR 0x10000000
9380 +#define OTPP_VALUE 0x20000000
9381 +#define OTPP_VALUE_SHIFT 29
9382 +#define OTPP_READ 0x40000000
9383 +#define OTPP_START 0x80000000
9384 +#define OTPP_BUSY 0x80000000
9385 +
9386 +/* jtagcmd */
9387 +#define JCMD_START 0x80000000
9388 +#define JCMD_BUSY 0x80000000
9389 +#define JCMD_PAUSE 0x40000000
9390 +#define JCMD0_ACC_MASK 0x0000f000
9391 +#define JCMD0_ACC_IRDR 0x00000000
9392 +#define JCMD0_ACC_DR 0x00001000
9393 +#define JCMD0_ACC_IR 0x00002000
9394 +#define JCMD0_ACC_RESET 0x00003000
9395 +#define JCMD0_ACC_IRPDR 0x00004000
9396 +#define JCMD0_ACC_PDR 0x00005000
9397 +#define JCMD0_IRW_MASK 0x00000f00
9398 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9399 +#define JCMD_ACC_IRDR 0x00000000
9400 +#define JCMD_ACC_DR 0x00010000
9401 +#define JCMD_ACC_IR 0x00020000
9402 +#define JCMD_ACC_RESET 0x00030000
9403 +#define JCMD_ACC_IRPDR 0x00040000
9404 +#define JCMD_ACC_PDR 0x00050000
9405 +#define JCMD_IRW_MASK 0x00001f00
9406 +#define JCMD_IRW_SHIFT 8
9407 +#define JCMD_DRW_MASK 0x0000003f
9408 +
9409 +/* jtagctrl */
9410 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9411 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9412 +#define JCTRL_EN 1 /* Enable Jtag master */
9413 +
9414 +/* Fields in clkdiv */
9415 +#define CLKD_SFLASH 0x0f000000
9416 +#define CLKD_SFLASH_SHIFT 24
9417 +#define CLKD_OTP 0x000f0000
9418 +#define CLKD_OTP_SHIFT 16
9419 +#define CLKD_JTAG 0x00000f00
9420 +#define CLKD_JTAG_SHIFT 8
9421 +#define CLKD_UART 0x000000ff
9422 +
9423 +/* intstatus/intmask */
9424 +#define CI_GPIO 0x00000001 /* gpio intr */
9425 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9426 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9427 +
9428 +/* slow_clk_ctl */
9429 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9430 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9431 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9432 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9433 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9434 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9435 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9436 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9437 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9438 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9439 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9440 +#define SCC_CD_SHIFT 16
9441 +
9442 +/* system_clk_ctl */
9443 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9444 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9445 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9446 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9447 +#define SYCC_HR 0x00000010 /* Force HT */
9448 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9449 +#define SYCC_CD_SHIFT 16
9450 +
9451 +/* gpiotimerval*/
9452 +#define GPIO_ONTIME_SHIFT 16
9453 +
9454 +/* clockcontrol_n */
9455 +#define CN_N1_MASK 0x3f /* n1 control */
9456 +#define CN_N2_MASK 0x3f00 /* n2 control */
9457 +#define CN_N2_SHIFT 8
9458 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9459 +#define CN_PLLC_SHIFT 16
9460 +
9461 +/* clockcontrol_sb/pci/uart */
9462 +#define CC_M1_MASK 0x3f /* m1 control */
9463 +#define CC_M2_MASK 0x3f00 /* m2 control */
9464 +#define CC_M2_SHIFT 8
9465 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9466 +#define CC_M3_SHIFT 16
9467 +#define CC_MC_MASK 0x1f000000 /* mux control */
9468 +#define CC_MC_SHIFT 24
9469 +
9470 +/* N3M Clock control magic field values */
9471 +#define CC_F6_2 0x02 /* A factor of 2 in */
9472 +#define CC_F6_3 0x03 /* 6-bit fields like */
9473 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9474 +#define CC_F6_5 0x09
9475 +#define CC_F6_6 0x11
9476 +#define CC_F6_7 0x21
9477 +
9478 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9479 +
9480 +#define CC_MC_BYPASS 0x08
9481 +#define CC_MC_M1 0x04
9482 +#define CC_MC_M1M2 0x02
9483 +#define CC_MC_M1M2M3 0x01
9484 +#define CC_MC_M1M3 0x11
9485 +
9486 +/* Type 2 Clock control magic field values */
9487 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9488 +#define CC_T2M2_BIAS 3 /* m2 bias */
9489 +
9490 +#define CC_T2MC_M1BYP 1
9491 +#define CC_T2MC_M2BYP 2
9492 +#define CC_T2MC_M3BYP 4
9493 +
9494 +/* Type 6 Clock control magic field values */
9495 +#define CC_T6_MMASK 1 /* bits of interest in m */
9496 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9497 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9498 +#define SB2MIPS_T6(sb) (2 * (sb))
9499 +
9500 +/* Common clock base */
9501 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9502 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9503 +
9504 +/* Clock control values for 200Mhz in 5350 */
9505 +#define CLKC_5350_N 0x0311
9506 +#define CLKC_5350_M 0x04020009
9507 +
9508 +/* Flash types in the chipcommon capabilities register */
9509 +#define FLASH_NONE 0x000 /* No flash */
9510 +#define SFLASH_ST 0x100 /* ST serial flash */
9511 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9512 +#define PFLASH 0x700 /* Parallel flash */
9513 +
9514 +/* Bits in the config registers */
9515 +#define CC_CFG_EN 0x0001 /* Enable */
9516 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9517 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9518 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9519 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9520 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9521 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9522 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9523 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9524 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9525 +
9526 +/* Start/busy bit in flashcontrol */
9527 +#define SFLASH_START 0x80000000
9528 +#define SFLASH_BUSY SFLASH_START
9529 +
9530 +/* flashcontrol opcodes for ST flashes */
9531 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9532 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9533 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9534 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9535 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9536 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9537 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9538 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9539 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9540 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9541 +
9542 +/* Status register bits for ST flashes */
9543 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9544 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9545 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9546 +#define SFLASH_ST_BP_SHIFT 2
9547 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9548 +
9549 +/* flashcontrol opcodes for Atmel flashes */
9550 +#define SFLASH_AT_READ 0x07e8
9551 +#define SFLASH_AT_PAGE_READ 0x07d2
9552 +#define SFLASH_AT_BUF1_READ
9553 +#define SFLASH_AT_BUF2_READ
9554 +#define SFLASH_AT_STATUS 0x01d7
9555 +#define SFLASH_AT_BUF1_WRITE 0x0384
9556 +#define SFLASH_AT_BUF2_WRITE 0x0387
9557 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9558 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9559 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9560 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9561 +#define SFLASH_AT_PAGE_ERASE 0x0281
9562 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9563 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9564 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9565 +#define SFLASH_AT_BUF1_LOAD 0x0253
9566 +#define SFLASH_AT_BUF2_LOAD 0x0255
9567 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9568 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9569 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9570 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9571 +
9572 +/* Status register bits for Atmel flashes */
9573 +#define SFLASH_AT_READY 0x80
9574 +#define SFLASH_AT_MISMATCH 0x40
9575 +#define SFLASH_AT_ID_MASK 0x38
9576 +#define SFLASH_AT_ID_SHIFT 3
9577 +
9578 +/* OTP regions */
9579 +#define OTP_HW_REGION OTPS_HW_PROTECT
9580 +#define OTP_SW_REGION OTPS_SW_PROTECT
9581 +#define OTP_CID_REGION OTPS_CID_PROTECT
9582 +
9583 +/* OTP regions (Byte offsets from otp size) */
9584 +#define OTP_SWLIM_OFF (-8)
9585 +#define OTP_CIDBASE_OFF 0
9586 +#define OTP_CIDLIM_OFF 8
9587 +
9588 +/* Predefined OTP words (Word offset from otp size) */
9589 +#define OTP_BOUNDARY_OFF (-4)
9590 +#define OTP_HWSIGN_OFF (-3)
9591 +#define OTP_SWSIGN_OFF (-2)
9592 +#define OTP_CIDSIGN_OFF (-1)
9593 +
9594 +#define OTP_CID_OFF 0
9595 +#define OTP_PKG_OFF 1
9596 +#define OTP_FID_OFF 2
9597 +#define OTP_RSV_OFF 3
9598 +#define OTP_LIM_OFF 4
9599 +
9600 +#define OTP_SIGNATURE 0x578a
9601 +#define OTP_MAGIC 0x4e56
9602 +
9603 +#endif /* _SBCHIPC_H */
9604 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9605 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9606 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-15 23:29:14.000000000 +0200
9607 @@ -0,0 +1,342 @@
9608 +/*
9609 + * Broadcom SiliconBackplane hardware register definitions.
9610 + *
9611 + * Copyright 2005, Broadcom Corporation
9612 + * All Rights Reserved.
9613 + *
9614 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9615 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9616 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9617 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9618 + * $Id$
9619 + */
9620 +
9621 +#ifndef _SBCONFIG_H
9622 +#define _SBCONFIG_H
9623 +
9624 +/* cpp contortions to concatenate w/arg prescan */
9625 +#ifndef PAD
9626 +#define _PADLINE(line) pad ## line
9627 +#define _XSTR(line) _PADLINE(line)
9628 +#define PAD _XSTR(__LINE__)
9629 +#endif
9630 +
9631 +/*
9632 + * SiliconBackplane Address Map.
9633 + * All regions may not exist on all chips.
9634 + */
9635 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9636 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9637 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9638 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9639 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9640 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9641 +
9642 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9643 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9644 +
9645 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9646 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9647 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9648 +
9649 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9650 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9651 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9652 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9653 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9654 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9655 +
9656 +
9657 +/* enumeration space related defs */
9658 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9659 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9660 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9661 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9662 +
9663 +/* mips address */
9664 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9665 +
9666 +/*
9667 + * Sonics Configuration Space Registers.
9668 + */
9669 +#define SBIPSFLAG 0x08
9670 +#define SBTPSFLAG 0x18
9671 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9672 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9673 +#define SBADMATCH3 0x60
9674 +#define SBADMATCH2 0x68
9675 +#define SBADMATCH1 0x70
9676 +#define SBIMSTATE 0x90
9677 +#define SBINTVEC 0x94
9678 +#define SBTMSTATELOW 0x98
9679 +#define SBTMSTATEHIGH 0x9c
9680 +#define SBBWA0 0xa0
9681 +#define SBIMCONFIGLOW 0xa8
9682 +#define SBIMCONFIGHIGH 0xac
9683 +#define SBADMATCH0 0xb0
9684 +#define SBTMCONFIGLOW 0xb8
9685 +#define SBTMCONFIGHIGH 0xbc
9686 +#define SBBCONFIG 0xc0
9687 +#define SBBSTATE 0xc8
9688 +#define SBACTCNFG 0xd8
9689 +#define SBFLAGST 0xe8
9690 +#define SBIDLOW 0xf8
9691 +#define SBIDHIGH 0xfc
9692 +
9693 +#ifndef _LANGUAGE_ASSEMBLY
9694 +
9695 +typedef volatile struct _sbconfig {
9696 + uint32 PAD[2];
9697 + uint32 sbipsflag; /* initiator port ocp slave flag */
9698 + uint32 PAD[3];
9699 + uint32 sbtpsflag; /* target port ocp slave flag */
9700 + uint32 PAD[11];
9701 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9702 + uint32 PAD;
9703 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9704 + uint32 PAD[3];
9705 + uint32 sbadmatch3; /* address match3 */
9706 + uint32 PAD;
9707 + uint32 sbadmatch2; /* address match2 */
9708 + uint32 PAD;
9709 + uint32 sbadmatch1; /* address match1 */
9710 + uint32 PAD[7];
9711 + uint32 sbimstate; /* initiator agent state */
9712 + uint32 sbintvec; /* interrupt mask */
9713 + uint32 sbtmstatelow; /* target state */
9714 + uint32 sbtmstatehigh; /* target state */
9715 + uint32 sbbwa0; /* bandwidth allocation table0 */
9716 + uint32 PAD;
9717 + uint32 sbimconfiglow; /* initiator configuration */
9718 + uint32 sbimconfighigh; /* initiator configuration */
9719 + uint32 sbadmatch0; /* address match0 */
9720 + uint32 PAD;
9721 + uint32 sbtmconfiglow; /* target configuration */
9722 + uint32 sbtmconfighigh; /* target configuration */
9723 + uint32 sbbconfig; /* broadcast configuration */
9724 + uint32 PAD;
9725 + uint32 sbbstate; /* broadcast state */
9726 + uint32 PAD[3];
9727 + uint32 sbactcnfg; /* activate configuration */
9728 + uint32 PAD[3];
9729 + uint32 sbflagst; /* current sbflags */
9730 + uint32 PAD[3];
9731 + uint32 sbidlow; /* identification */
9732 + uint32 sbidhigh; /* identification */
9733 +} sbconfig_t;
9734 +
9735 +#endif /* _LANGUAGE_ASSEMBLY */
9736 +
9737 +/* sbipsflag */
9738 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9739 +#define SBIPS_INT1_SHIFT 0
9740 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9741 +#define SBIPS_INT2_SHIFT 8
9742 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9743 +#define SBIPS_INT3_SHIFT 16
9744 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9745 +#define SBIPS_INT4_SHIFT 24
9746 +
9747 +/* sbtpsflag */
9748 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9749 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9750 +
9751 +/* sbtmerrlog */
9752 +#define SBTMEL_CM 0x00000007 /* command */
9753 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9754 +#define SBTMEL_EC 0x0f000000 /* error code */
9755 +#define SBTMEL_ME 0x80000000 /* multiple error */
9756 +
9757 +/* sbimstate */
9758 +#define SBIM_PC 0xf /* pipecount */
9759 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9760 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9761 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9762 +#define SBIM_AP_TK 0x20 /* use token only */
9763 +#define SBIM_AP_RSV 0x30 /* reserved */
9764 +#define SBIM_IBE 0x20000 /* inbanderror */
9765 +#define SBIM_TO 0x40000 /* timeout */
9766 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9767 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9768 +
9769 +/* sbtmstatelow */
9770 +#define SBTML_RESET 0x1 /* reset */
9771 +#define SBTML_REJ_MASK 0x6 /* reject */
9772 +#define SBTML_REJ_SHIFT 1
9773 +#define SBTML_CLK 0x10000 /* clock enable */
9774 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9775 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9776 +#define SBTML_PE 0x40000000 /* pme enable */
9777 +#define SBTML_BE 0x80000000 /* bist enable */
9778 +
9779 +/* sbtmstatehigh */
9780 +#define SBTMH_SERR 0x1 /* serror */
9781 +#define SBTMH_INT 0x2 /* interrupt */
9782 +#define SBTMH_BUSY 0x4 /* busy */
9783 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9784 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9785 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9786 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9787 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9788 +#define SBTMH_BISTD 0x80000000 /* bist done */
9789 +
9790 +
9791 +/* sbbwa0 */
9792 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9793 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9794 +#define SBBWA_TAB1_SHIFT 16
9795 +
9796 +/* sbimconfiglow */
9797 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9798 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9799 +#define SBIMCL_RTO_SHIFT 4
9800 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9801 +#define SBIMCL_CID_SHIFT 16
9802 +
9803 +/* sbimconfighigh */
9804 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9805 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9806 +#define SBIMCH_TEM_SHIFT 4
9807 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9808 +#define SBIMCH_BEM_SHIFT 6
9809 +
9810 +/* sbadmatch0 */
9811 +#define SBAM_TYPE_MASK 0x3 /* address type */
9812 +#define SBAM_AD64 0x4 /* reserved */
9813 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9814 +#define SBAM_ADINT0_SHIFT 3
9815 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9816 +#define SBAM_ADINT1_SHIFT 3
9817 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9818 +#define SBAM_ADINT2_SHIFT 3
9819 +#define SBAM_ADEN 0x400 /* enable */
9820 +#define SBAM_ADNEG 0x800 /* negative decode */
9821 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9822 +#define SBAM_BASE0_SHIFT 8
9823 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9824 +#define SBAM_BASE1_SHIFT 12
9825 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9826 +#define SBAM_BASE2_SHIFT 16
9827 +
9828 +/* sbtmconfiglow */
9829 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9830 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9831 +#define SBTMCL_CO_SHIFT 11
9832 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9833 +#define SBTMCL_IF_SHIFT 18
9834 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9835 +#define SBTMCL_IM_SHIFT 24
9836 +
9837 +/* sbtmconfighigh */
9838 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9839 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9840 +#define SBTMCH_RM_SHIFT 2
9841 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9842 +#define SBTMCH_SM_SHIFT 4
9843 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9844 +#define SBTMCH_EM_SHIFT 8
9845 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9846 +#define SBTMCH_IM_SHIFT 10
9847 +
9848 +/* sbbconfig */
9849 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9850 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9851 +#define SBBC_MAX0_SHIFT 16
9852 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9853 +#define SBBC_MAX1_SHIFT 20
9854 +
9855 +/* sbbstate */
9856 +#define SBBS_SRD 0x1 /* st reg disable */
9857 +#define SBBS_HRD 0x2 /* hold reg disable */
9858 +
9859 +/* sbidlow */
9860 +#define SBIDL_CS_MASK 0x3 /* config space */
9861 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9862 +#define SBIDL_AR_SHIFT 3
9863 +#define SBIDL_SYNCH 0x40 /* sync */
9864 +#define SBIDL_INIT 0x80 /* initiator */
9865 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9866 +#define SBIDL_MINLAT_SHIFT 8
9867 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9868 +#define SBIDL_MAXLAT_SHIFT 12
9869 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9870 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9871 +#define SBIDL_CW_SHIFT 18
9872 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9873 +#define SBIDL_TP_SHIFT 20
9874 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9875 +#define SBIDL_IP_SHIFT 24
9876 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9877 +#define SBIDL_RV_SHIFT 28
9878 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9879 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9880 +
9881 +/* sbidhigh */
9882 +#define SBIDH_RC_MASK 0x000f /* revision code */
9883 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9884 +#define SBIDH_RCE_SHIFT 8
9885 +#define SBCOREREV(sbidh) \
9886 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9887 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9888 +#define SBIDH_CC_SHIFT 4
9889 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9890 +#define SBIDH_VC_SHIFT 16
9891 +
9892 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9893 +
9894 +/* vendor codes */
9895 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9896 +
9897 +/* core codes */
9898 +#define SB_CC 0x800 /* chipcommon core */
9899 +#define SB_ILINE20 0x801 /* iline20 core */
9900 +#define SB_SDRAM 0x803 /* sdram core */
9901 +#define SB_PCI 0x804 /* pci core */
9902 +#define SB_MIPS 0x805 /* mips core */
9903 +#define SB_ENET 0x806 /* enet mac core */
9904 +#define SB_CODEC 0x807 /* v90 codec core */
9905 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9906 +#define SB_ADSL 0x809 /* ADSL core */
9907 +#define SB_ILINE100 0x80a /* iline100 core */
9908 +#define SB_IPSEC 0x80b /* ipsec core */
9909 +#define SB_PCMCIA 0x80d /* pcmcia core */
9910 +#define SB_SOCRAM 0x80e /* internal memory core */
9911 +#define SB_MEMC 0x80f /* memc sdram core */
9912 +#define SB_EXTIF 0x811 /* external interface core */
9913 +#define SB_D11 0x812 /* 802.11 MAC core */
9914 +#define SB_MIPS33 0x816 /* mips3302 core */
9915 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9916 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9917 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9918 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9919 +#define SB_SDIOH 0x81b /* sdio host core */
9920 +#define SB_ROBO 0x81c /* roboswitch core */
9921 +#define SB_ATA100 0x81d /* parallel ATA core */
9922 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9923 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9924 +#define SB_PCIE 0x820 /* pci express core */
9925 +#define SB_SRAMC 0x822 /* SRAM controller core */
9926 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9927 +
9928 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9929 +
9930 +/* Not really related to Silicon Backplane, but a couple of software
9931 + * conventions for the use the flash space:
9932 + */
9933 +
9934 +/* Minumum amount of flash we support */
9935 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9936 +
9937 +/* A boot/binary may have an embedded block that describes its size */
9938 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9939 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9940 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9941 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9942 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9943 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9944 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9945 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9946 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9947 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9948 +
9949 +#endif /* _SBCONFIG_H */
9950 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9951 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9952 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-15 23:29:14.000000000 +0200
9953 @@ -0,0 +1,242 @@
9954 +/*
9955 + * Hardware-specific External Interface I/O core definitions
9956 + * for the BCM47xx family of SiliconBackplane-based chips.
9957 + *
9958 + * The External Interface core supports a total of three external chip selects
9959 + * supporting external interfaces. One of the external chip selects is
9960 + * used for Flash, one is used for PCMCIA, and the other may be
9961 + * programmed to support either a synchronous interface or an
9962 + * asynchronous interface. The asynchronous interface can be used to
9963 + * support external devices such as UARTs and the BCM2019 Bluetooth
9964 + * baseband processor.
9965 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9966 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9967 + *
9968 + * Copyright 2005, Broadcom Corporation
9969 + * All Rights Reserved.
9970 + *
9971 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9972 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9973 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9974 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9975 + * $Id$
9976 + */
9977 +
9978 +#ifndef _SBEXTIF_H
9979 +#define _SBEXTIF_H
9980 +
9981 +/* external interface address space */
9982 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9983 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9984 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9985 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9986 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9987 +
9988 +/* cpp contortions to concatenate w/arg prescan */
9989 +#ifndef PAD
9990 +#define _PADLINE(line) pad ## line
9991 +#define _XSTR(line) _PADLINE(line)
9992 +#define PAD _XSTR(__LINE__)
9993 +#endif /* PAD */
9994 +
9995 +/*
9996 + * The multiple instances of output and output enable registers
9997 + * are present to allow driver software for multiple cores to control
9998 + * gpio outputs without needing to share a single register pair.
9999 + */
10000 +struct gpiouser {
10001 + uint32 out;
10002 + uint32 outen;
10003 +};
10004 +#define NGPIOUSER 5
10005 +
10006 +typedef volatile struct {
10007 + uint32 corecontrol;
10008 + uint32 extstatus;
10009 + uint32 PAD[2];
10010 +
10011 + /* pcmcia control registers */
10012 + uint32 pcmcia_config;
10013 + uint32 pcmcia_memwait;
10014 + uint32 pcmcia_attrwait;
10015 + uint32 pcmcia_iowait;
10016 +
10017 + /* programmable interface control registers */
10018 + uint32 prog_config;
10019 + uint32 prog_waitcount;
10020 +
10021 + /* flash control registers */
10022 + uint32 flash_config;
10023 + uint32 flash_waitcount;
10024 + uint32 PAD[4];
10025 +
10026 + uint32 watchdog;
10027 +
10028 + /* clock control */
10029 + uint32 clockcontrol_n;
10030 + uint32 clockcontrol_sb;
10031 + uint32 clockcontrol_pci;
10032 + uint32 clockcontrol_mii;
10033 + uint32 PAD[3];
10034 +
10035 + /* gpio */
10036 + uint32 gpioin;
10037 + struct gpiouser gpio[NGPIOUSER];
10038 + uint32 PAD;
10039 + uint32 ejtagouten;
10040 + uint32 gpiointpolarity;
10041 + uint32 gpiointmask;
10042 + uint32 PAD[153];
10043 +
10044 + uint8 uartdata;
10045 + uint8 PAD[3];
10046 + uint8 uartimer;
10047 + uint8 PAD[3];
10048 + uint8 uartfcr;
10049 + uint8 PAD[3];
10050 + uint8 uartlcr;
10051 + uint8 PAD[3];
10052 + uint8 uartmcr;
10053 + uint8 PAD[3];
10054 + uint8 uartlsr;
10055 + uint8 PAD[3];
10056 + uint8 uartmsr;
10057 + uint8 PAD[3];
10058 + uint8 uartscratch;
10059 + uint8 PAD[3];
10060 +} extifregs_t;
10061 +
10062 +/* corecontrol */
10063 +#define CC_UE (1 << 0) /* uart enable */
10064 +
10065 +/* extstatus */
10066 +#define ES_EM (1 << 0) /* endian mode (ro) */
10067 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10068 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10069 +
10070 +/* gpio bit mask */
10071 +#define GPIO_BIT0 (1 << 0)
10072 +#define GPIO_BIT1 (1 << 1)
10073 +#define GPIO_BIT2 (1 << 2)
10074 +#define GPIO_BIT3 (1 << 3)
10075 +#define GPIO_BIT4 (1 << 4)
10076 +#define GPIO_BIT5 (1 << 5)
10077 +#define GPIO_BIT6 (1 << 6)
10078 +#define GPIO_BIT7 (1 << 7)
10079 +
10080 +
10081 +/* pcmcia/prog/flash_config */
10082 +#define CF_EN (1 << 0) /* enable */
10083 +#define CF_EM_MASK 0xe /* mode */
10084 +#define CF_EM_SHIFT 1
10085 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10086 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10087 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10088 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10089 +#define CF_BS (1 << 5) /* byteswap */
10090 +#define CF_CD_MASK 0xc0 /* clock divider */
10091 +#define CF_CD_SHIFT 6
10092 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10093 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10094 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10095 +#define CF_CE (1 << 8) /* clock enable */
10096 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10097 +
10098 +/* pcmcia_memwait */
10099 +#define PM_W0_MASK 0x3f /* waitcount0 */
10100 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10101 +#define PM_W1_SHIFT 8
10102 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10103 +#define PM_W2_SHIFT 16
10104 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10105 +#define PM_W3_SHIFT 24
10106 +
10107 +/* pcmcia_attrwait */
10108 +#define PA_W0_MASK 0x3f /* waitcount0 */
10109 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10110 +#define PA_W1_SHIFT 8
10111 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10112 +#define PA_W2_SHIFT 16
10113 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10114 +#define PA_W3_SHIFT 24
10115 +
10116 +/* pcmcia_iowait */
10117 +#define PI_W0_MASK 0x3f /* waitcount0 */
10118 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10119 +#define PI_W1_SHIFT 8
10120 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10121 +#define PI_W2_SHIFT 16
10122 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10123 +#define PI_W3_SHIFT 24
10124 +
10125 +/* prog_waitcount */
10126 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10127 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10128 +#define PW_W1_SHIFT 8
10129 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10130 +#define PW_W2_SHIFT 16
10131 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10132 +#define PW_W3_SHIFT 24
10133 +
10134 +#define PW_W0 0x0000000c
10135 +#define PW_W1 0x00000a00
10136 +#define PW_W2 0x00020000
10137 +#define PW_W3 0x01000000
10138 +
10139 +/* flash_waitcount */
10140 +#define FW_W0_MASK 0x1f /* waitcount0 */
10141 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10142 +#define FW_W1_SHIFT 8
10143 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10144 +#define FW_W2_SHIFT 16
10145 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10146 +#define FW_W3_SHIFT 24
10147 +
10148 +/* watchdog */
10149 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10150 +
10151 +/* clockcontrol_n */
10152 +#define CN_N1_MASK 0x3f /* n1 control */
10153 +#define CN_N2_MASK 0x3f00 /* n2 control */
10154 +#define CN_N2_SHIFT 8
10155 +
10156 +/* clockcontrol_sb/pci/mii */
10157 +#define CC_M1_MASK 0x3f /* m1 control */
10158 +#define CC_M2_MASK 0x3f00 /* m2 control */
10159 +#define CC_M2_SHIFT 8
10160 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10161 +#define CC_M3_SHIFT 16
10162 +#define CC_MC_MASK 0x1f000000 /* mux control */
10163 +#define CC_MC_SHIFT 24
10164 +
10165 +/* Clock control default values */
10166 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10167 +#define CC_DEF_100 0x04020011
10168 +#define CC_DEF_33 0x11030011
10169 +#define CC_DEF_25 0x11050011
10170 +
10171 +/* Clock control values for 125Mhz */
10172 +#define CC_125_N 0x0802
10173 +#define CC_125_M 0x04020009
10174 +#define CC_125_M25 0x11090009
10175 +#define CC_125_M33 0x11090005
10176 +
10177 +/* Clock control magic field values */
10178 +#define CC_F6_2 0x02 /* A factor of 2 in */
10179 +#define CC_F6_3 0x03 /* 6-bit fields like */
10180 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10181 +#define CC_F6_5 0x09
10182 +#define CC_F6_6 0x11
10183 +#define CC_F6_7 0x21
10184 +
10185 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10186 +
10187 +#define CC_MC_BYPASS 0x08
10188 +#define CC_MC_M1 0x04
10189 +#define CC_MC_M1M2 0x02
10190 +#define CC_MC_M1M2M3 0x01
10191 +#define CC_MC_M1M3 0x11
10192 +
10193 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10194 +
10195 +#endif /* _SBEXTIF_H */
10196 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10197 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10198 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-15 23:29:14.000000000 +0200
10199 @@ -0,0 +1,148 @@
10200 +/*
10201 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10202 + *
10203 + * Copyright 2005, Broadcom Corporation
10204 + * All Rights Reserved.
10205 + *
10206 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10207 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10208 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10209 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10210 + *
10211 + * $Id$
10212 + */
10213 +
10214 +#ifndef _SBMEMC_H
10215 +#define _SBMEMC_H
10216 +
10217 +#ifdef _LANGUAGE_ASSEMBLY
10218 +
10219 +#define MEMC_CONTROL 0x00
10220 +#define MEMC_CONFIG 0x04
10221 +#define MEMC_REFRESH 0x08
10222 +#define MEMC_BISTSTAT 0x0c
10223 +#define MEMC_MODEBUF 0x10
10224 +#define MEMC_BKCLS 0x14
10225 +#define MEMC_PRIORINV 0x18
10226 +#define MEMC_DRAMTIM 0x1c
10227 +#define MEMC_INTSTAT 0x20
10228 +#define MEMC_INTMASK 0x24
10229 +#define MEMC_INTINFO 0x28
10230 +#define MEMC_NCDLCTL 0x30
10231 +#define MEMC_RDNCDLCOR 0x34
10232 +#define MEMC_WRNCDLCOR 0x38
10233 +#define MEMC_MISCDLYCTL 0x3c
10234 +#define MEMC_DQSGATENCDL 0x40
10235 +#define MEMC_SPARE 0x44
10236 +#define MEMC_TPADDR 0x48
10237 +#define MEMC_TPDATA 0x4c
10238 +#define MEMC_BARRIER 0x50
10239 +#define MEMC_CORE 0x54
10240 +
10241 +
10242 +#else
10243 +
10244 +/* Sonics side: MEMC core registers */
10245 +typedef volatile struct sbmemcregs {
10246 + uint32 control;
10247 + uint32 config;
10248 + uint32 refresh;
10249 + uint32 biststat;
10250 + uint32 modebuf;
10251 + uint32 bkcls;
10252 + uint32 priorinv;
10253 + uint32 dramtim;
10254 + uint32 intstat;
10255 + uint32 intmask;
10256 + uint32 intinfo;
10257 + uint32 reserved1;
10258 + uint32 ncdlctl;
10259 + uint32 rdncdlcor;
10260 + uint32 wrncdlcor;
10261 + uint32 miscdlyctl;
10262 + uint32 dqsgatencdl;
10263 + uint32 spare;
10264 + uint32 tpaddr;
10265 + uint32 tpdata;
10266 + uint32 barrier;
10267 + uint32 core;
10268 +} sbmemcregs_t;
10269 +
10270 +#endif
10271 +
10272 +/* MEMC Core Init values (OCP ID 0x80f) */
10273 +
10274 +/* For sdr: */
10275 +#define MEMC_SD_CONFIG_INIT 0x00048000
10276 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10277 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10278 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10279 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10280 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10281 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10282 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10283 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10284 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10285 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10286 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10287 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10288 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10289 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10290 +
10291 +
10292 +/* This is for SDRM8X8X4 */
10293 +#define MEMC_SDR_INIT 0x0008
10294 +#define MEMC_SDR_MODE 0x32
10295 +#define MEMC_SDR_NCDL 0x00020032
10296 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10297 +
10298 +/* For ddr: */
10299 +#define MEMC_CONFIG_INIT 0x00048000
10300 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10301 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10302 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10303 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10304 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10305 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10306 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10307 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10308 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10309 +#define MEMC_NCDLCTL_INIT 0x00002001
10310 +#define MEMC_CONTROL_INIT0 0x00000002
10311 +#define MEMC_CONTROL_INIT1 0x00000008
10312 +#define MEMC_MODEBUF_INIT0 0x00004000
10313 +#define MEMC_CONTROL_INIT2 0x00000010
10314 +#define MEMC_MODEBUF_INIT1 0x00000100
10315 +#define MEMC_CONTROL_INIT3 0x00000010
10316 +#define MEMC_CONTROL_INIT4 0x00000008
10317 +#define MEMC_REFRESH_INIT 0x0000840f
10318 +#define MEMC_CONTROL_INIT5 0x00000004
10319 +#define MEMC_MODEBUF_INIT2 0x00000000
10320 +#define MEMC_CONTROL_INIT6 0x00000010
10321 +#define MEMC_CONTROL_INIT7 0x00000001
10322 +
10323 +
10324 +/* This is for DDRM16X16X2 */
10325 +#define MEMC_DDR_INIT 0x0009
10326 +#define MEMC_DDR_MODE 0x62
10327 +#define MEMC_DDR_NCDL 0x0005050a
10328 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10329 +
10330 +/* mask for sdr/ddr calibration registers */
10331 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10332 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10333 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10334 +
10335 +/* masks for miscdlyctl registers */
10336 +#define MEMC_MISC_SM_MASK 0x30000000
10337 +#define MEMC_MISC_SM_SHIFT 28
10338 +#define MEMC_MISC_SD_MASK 0x0f000000
10339 +#define MEMC_MISC_SD_SHIFT 24
10340 +
10341 +/* hw threshhold for calculating wr/rd for sdr memc */
10342 +#define MEMC_CD_THRESHOLD 128
10343 +
10344 +/* Low bit of init register says if memc is ddr or sdr */
10345 +#define MEMC_CONFIG_DDR 0x00000001
10346 +
10347 +#endif /* _SBMEMC_H */
10348 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10349 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10350 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2006-10-15 23:37:15.000000000 +0200
10351 @@ -0,0 +1,63 @@
10352 +/*
10353 + * Broadcom SiliconBackplane MIPS definitions
10354 + *
10355 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10356 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10357 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10358 + * interface. The core revision is stored in the SB ID register in SB
10359 + * configuration space.
10360 + *
10361 + * Copyright 2005, Broadcom Corporation
10362 + * All Rights Reserved.
10363 + *
10364 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10365 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10366 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10367 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10368 + *
10369 + * $Id$
10370 + */
10371 +
10372 +#ifndef _SBMIPS_H
10373 +#define _SBMIPS_H
10374 +
10375 +#include <mipsinc.h>
10376 +
10377 +#ifndef _LANGUAGE_ASSEMBLY
10378 +
10379 +/* cpp contortions to concatenate w/arg prescan */
10380 +#ifndef PAD
10381 +#define _PADLINE(line) pad ## line
10382 +#define _XSTR(line) _PADLINE(line)
10383 +#define PAD _XSTR(__LINE__)
10384 +#endif /* PAD */
10385 +
10386 +typedef volatile struct {
10387 + uint32 corecontrol;
10388 + uint32 PAD[2];
10389 + uint32 biststatus;
10390 + uint32 PAD[4];
10391 + uint32 intstatus;
10392 + uint32 intmask;
10393 + uint32 timer;
10394 +} mipsregs_t;
10395 +
10396 +extern uint32 sb_flag(sb_t *sbh);
10397 +extern uint sb_irq(sb_t *sbh);
10398 +
10399 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10400 +
10401 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10402 +extern void sb_jtagm_disable(void *h);
10403 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10404 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10405 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10406 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10407 +extern void BCMINIT(enable_pfc)(uint32 mode);
10408 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10409 +extern uint32 BCMINIT(sb_cpu_clock)(sb_t *sbh);
10410 +
10411 +
10412 +#endif /* _LANGUAGE_ASSEMBLY */
10413 +
10414 +#endif /* _SBMIPS_H */
10415 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10416 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10417 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-15 23:29:14.000000000 +0200
10418 @@ -0,0 +1,122 @@
10419 +/*
10420 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10421 + *
10422 + * $Id$
10423 + * Copyright 2005, Broadcom Corporation
10424 + * All Rights Reserved.
10425 + *
10426 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10427 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10428 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10429 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10430 + */
10431 +
10432 +#ifndef _SBPCI_H
10433 +#define _SBPCI_H
10434 +
10435 +/* cpp contortions to concatenate w/arg prescan */
10436 +#ifndef PAD
10437 +#define _PADLINE(line) pad ## line
10438 +#define _XSTR(line) _PADLINE(line)
10439 +#define PAD _XSTR(__LINE__)
10440 +#endif
10441 +
10442 +/* Sonics side: PCI core and host control registers */
10443 +typedef struct sbpciregs {
10444 + uint32 control; /* PCI control */
10445 + uint32 PAD[3];
10446 + uint32 arbcontrol; /* PCI arbiter control */
10447 + uint32 PAD[3];
10448 + uint32 intstatus; /* Interrupt status */
10449 + uint32 intmask; /* Interrupt mask */
10450 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10451 + uint32 PAD[9];
10452 + uint32 bcastaddr; /* Sonics broadcast address */
10453 + uint32 bcastdata; /* Sonics broadcast data */
10454 + uint32 PAD[2];
10455 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10456 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10457 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10458 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10459 + uint32 PAD[36];
10460 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10461 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10462 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10463 + uint32 PAD[445];
10464 + uint16 sprom[36]; /* SPROM shadow Area */
10465 + uint32 PAD[46];
10466 +} sbpciregs_t;
10467 +
10468 +/* PCI control */
10469 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10470 +#define PCI_RST 0x02 /* Value driven out to pin */
10471 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10472 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10473 +
10474 +/* PCI arbiter control */
10475 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10476 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10477 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10478 +#define PCI_PARKID_SHIFT 1
10479 +#define PCI_PARKID_LAST 0 /* Last requestor */
10480 +#define PCI_PARKID_4710 1 /* 4710 */
10481 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10482 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10483 +
10484 +/* Interrupt status/mask */
10485 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10486 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10487 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10488 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10489 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10490 +
10491 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10492 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10493 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10494 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10495 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10496 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10497 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10498 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10499 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10500 +
10501 +/* Sonics broadcast address */
10502 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10503 +
10504 +/* Sonics to PCI translation types */
10505 +#define SBTOPCI0_MASK 0xfc000000
10506 +#define SBTOPCI1_MASK 0xfc000000
10507 +#define SBTOPCI2_MASK 0xc0000000
10508 +#define SBTOPCI_MEM 0
10509 +#define SBTOPCI_IO 1
10510 +#define SBTOPCI_CFG0 2
10511 +#define SBTOPCI_CFG1 3
10512 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10513 +#define SBTOPCI_BURST 0x8 /* burst enable */
10514 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10515 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10516 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10517 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10518 +
10519 +/* PCI core index in SROM shadow area */
10520 +#define SRSH_PI_OFFSET 0 /* first word */
10521 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10522 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10523 +
10524 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10525 +#define cap_list rsvd_a[0]
10526 +#define bar0_window dev_dep[0x80 - 0x40]
10527 +#define bar1_window dev_dep[0x84 - 0x40]
10528 +#define sprom_control dev_dep[0x88 - 0x40]
10529 +
10530 +#ifndef _LANGUAGE_ASSEMBLY
10531 +
10532 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10533 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10534 +extern void sbpci_ban(uint16 core);
10535 +extern int sbpci_init(sb_t *sbh);
10536 +extern void sbpci_check(sb_t *sbh);
10537 +
10538 +#endif /* !_LANGUAGE_ASSEMBLY */
10539 +
10540 +#endif /* _SBPCI_H */
10541 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10542 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10543 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-15 23:29:14.000000000 +0200
10544 @@ -0,0 +1,75 @@
10545 +/*
10546 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10547 + *
10548 + * Copyright 2005, Broadcom Corporation
10549 + * All Rights Reserved.
10550 + *
10551 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10552 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10553 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10554 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10555 + * $Id$
10556 + */
10557 +
10558 +#ifndef _SBSDRAM_H
10559 +#define _SBSDRAM_H
10560 +
10561 +#ifndef _LANGUAGE_ASSEMBLY
10562 +
10563 +/* Sonics side: SDRAM core registers */
10564 +typedef volatile struct sbsdramregs {
10565 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10566 + uint32 config; /* Initializes external SDRAM mode register */
10567 + uint32 refresh; /* Controls external SDRAM refresh rate */
10568 + uint32 pad1;
10569 + uint32 pad2;
10570 +} sbsdramregs_t;
10571 +
10572 +#endif
10573 +
10574 +/* SDRAM initialization control (initcontrol) register bits */
10575 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10576 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10577 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10578 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10579 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10580 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10581 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10582 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10583 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10584 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10585 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10586 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10587 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10588 +
10589 +/* SDRAM configuration (config) register bits */
10590 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10591 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10592 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10593 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10594 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10595 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10596 +
10597 +/* SDRAM refresh control (refresh) register bits */
10598 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10599 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10600 +
10601 +/* SDRAM Core default Init values (OCP ID 0x803) */
10602 +#define SDRAM_INIT MEM4MX16X2
10603 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10604 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10605 +
10606 +#define MEM1MX16 0x009 /* 2 MB */
10607 +#define MEM1MX16X2 0x409 /* 4 MB */
10608 +#define MEM2MX8X2 0x809 /* 4 MB */
10609 +#define MEM2MX8X4 0xc09 /* 8 MB */
10610 +#define MEM2MX32 0x439 /* 8 MB */
10611 +#define MEM4MX16 0x019 /* 8 MB */
10612 +#define MEM4MX16X2 0x419 /* 16 MB */
10613 +#define MEM8MX8X2 0x819 /* 16 MB */
10614 +#define MEM8MX16 0x829 /* 16 MB */
10615 +#define MEM4MX32 0x429 /* 16 MB */
10616 +#define MEM8MX8X4 0xc19 /* 32 MB */
10617 +#define MEM8MX16X2 0xc29 /* 32 MB */
10618 +
10619 +#endif /* _SBSDRAM_H */
10620 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10621 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10622 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-15 23:29:14.000000000 +0200
10623 @@ -0,0 +1,136 @@
10624 +/*
10625 + * Misc utility routines for accessing chip-specific features
10626 + * of Broadcom HNBU SiliconBackplane-based chips.
10627 + *
10628 + * Copyright 2005, Broadcom Corporation
10629 + * All Rights Reserved.
10630 + *
10631 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10632 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10633 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10634 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10635 + *
10636 + * $Id$
10637 + */
10638 +
10639 +#ifndef _sbutils_h_
10640 +#define _sbutils_h_
10641 +
10642 +/*
10643 + * Datastructure to export all chip specific common variables
10644 + * public (read-only) portion of sbutils handle returned by
10645 + * sb_attach()/sb_kattach()
10646 +*/
10647 +
10648 +struct sb_pub {
10649 +
10650 + uint bustype; /* SB_BUS, PCI_BUS */
10651 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10652 + uint buscorerev; /* buscore rev */
10653 + uint buscoreidx; /* buscore index */
10654 + int ccrev; /* chip common core rev */
10655 + uint boardtype; /* board type */
10656 + uint boardvendor; /* board vendor */
10657 + uint chip; /* chip number */
10658 + uint chiprev; /* chip revision */
10659 + uint chippkg; /* chip package option */
10660 + uint sonicsrev; /* sonics backplane rev */
10661 +};
10662 +
10663 +typedef const struct sb_pub sb_t;
10664 +
10665 +/*
10666 + * Many of the routines below take an 'sbh' handle as their first arg.
10667 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10668 + * At any one time, the sbh is logically focused on one particular sb core
10669 + * (the "current core").
10670 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10671 + */
10672 +
10673 +/* exported externs */
10674 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10675 +extern sb_t * BCMINIT(sb_kattach)(void);
10676 +extern void sb_detach(sb_t *sbh);
10677 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10678 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10679 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10680 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10681 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10682 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10683 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10684 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10685 +extern uint sb_bus(sb_t *sbh);
10686 +extern uint sb_buscoretype(sb_t *sbh);
10687 +extern uint sb_buscorerev(sb_t *sbh);
10688 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10689 +extern uint sb_coreid(sb_t *sbh);
10690 +extern uint sb_coreidx(sb_t *sbh);
10691 +extern uint sb_coreunit(sb_t *sbh);
10692 +extern uint sb_corevendor(sb_t *sbh);
10693 +extern uint sb_corerev(sb_t *sbh);
10694 +extern void *sb_osh(sb_t *sbh);
10695 +extern void *sb_coreregs(sb_t *sbh);
10696 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10697 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10698 +extern bool sb_iscoreup(sb_t *sbh);
10699 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10700 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10701 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10702 +extern void sb_commit(sb_t *sbh);
10703 +extern uint32 sb_base(uint32 admatch);
10704 +extern uint32 sb_size(uint32 admatch);
10705 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10706 +extern void sb_core_tofixup(sb_t *sbh);
10707 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10708 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10709 +extern uint32 sb_clock(sb_t *sbh);
10710 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10711 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10712 +extern void *sb_gpiosetcore(sb_t *sbh);
10713 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10714 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10715 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10716 +extern uint32 sb_gpioin(sb_t *sbh);
10717 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10718 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10719 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10720 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10721 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10722 +
10723 +extern void sb_clkctl_init(sb_t *sbh);
10724 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10725 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10726 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10727 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10728 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10729 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10730 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10731 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10732 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10733 +
10734 +
10735 +
10736 +/*
10737 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10738 +* The returned path is NULL terminated and has trailing '/'.
10739 +* Return 0 on success, nonzero otherwise.
10740 +*/
10741 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10742 +
10743 +/* clkctl xtal what flags */
10744 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10745 +#define PLL 0x2 /* main chip pll */
10746 +
10747 +/* clkctl clk mode */
10748 +#define CLK_FAST 0 /* force fast (pll) clock */
10749 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10750 +
10751 +
10752 +/* GPIO usage priorities */
10753 +#define GPIO_DRV_PRIORITY 0
10754 +#define GPIO_APP_PRIORITY 1
10755 +
10756 +/* device path */
10757 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10758 +
10759 +#endif /* _sbutils_h_ */
10760 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10761 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10762 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-15 23:29:14.000000000 +0200
10763 @@ -0,0 +1,36 @@
10764 +/*
10765 + * Broadcom SiliconBackplane chipcommon serial flash interface
10766 + *
10767 + * Copyright 2005, Broadcom Corporation
10768 + * All Rights Reserved.
10769 + *
10770 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10771 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10772 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10773 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10774 + *
10775 + * $Id$
10776 + */
10777 +
10778 +#ifndef _sflash_h_
10779 +#define _sflash_h_
10780 +
10781 +#include <typedefs.h>
10782 +#include <sbchipc.h>
10783 +
10784 +struct sflash {
10785 + uint blocksize; /* Block size */
10786 + uint numblocks; /* Number of blocks */
10787 + uint32 type; /* Type */
10788 + uint size; /* Total size in bytes */
10789 +};
10790 +
10791 +/* Utility functions */
10792 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10793 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10794 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10795 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10796 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10797 +extern struct sflash * sflash_init(chipcregs_t *cc);
10798 +
10799 +#endif /* _sflash_h_ */
10800 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10801 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10802 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-15 23:29:14.000000000 +0200
10803 @@ -0,0 +1,33 @@
10804 +/*
10805 + * TRX image file header format.
10806 + *
10807 + * Copyright 2005, Broadcom Corporation
10808 + * All Rights Reserved.
10809 + *
10810 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10811 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10812 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10813 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10814 + *
10815 + * $Id$
10816 + */
10817 +
10818 +#include <typedefs.h>
10819 +
10820 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10821 +#define TRX_VERSION 1
10822 +#define TRX_MAX_LEN 0x3A0000
10823 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10824 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10825 +#define TRX_MAX_OFFSET 3
10826 +
10827 +struct trx_header {
10828 + uint32 magic; /* "HDR0" */
10829 + uint32 len; /* Length of file including header */
10830 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10831 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10832 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10833 +};
10834 +
10835 +/* Compatibility */
10836 +typedef struct trx_header TRXHDR, *PTRXHDR;
10837 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10838 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10839 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-15 23:29:14.000000000 +0200
10840 @@ -0,0 +1,326 @@
10841 +/*
10842 + * Copyright 2005, Broadcom Corporation
10843 + * All Rights Reserved.
10844 + *
10845 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10846 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10847 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10848 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10849 + * $Id$
10850 + */
10851 +
10852 +#ifndef _TYPEDEFS_H_
10853 +#define _TYPEDEFS_H_
10854 +
10855 +
10856 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10857 + * typedef file "site_typedefs.h".
10858 + *
10859 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10860 + * section of this file makes inferences about the compile environment
10861 + * based on defined symbols and possibly compiler pragmas.
10862 + *
10863 + * Following these two sections is the "Default Typedefs"
10864 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10865 + * defined. This section has a default set of typedefs and a few
10866 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10867 + */
10868 +
10869 +#ifdef SITE_TYPEDEFS
10870 +
10871 +/*******************************************************************************
10872 + * Site Specific Typedefs
10873 + *******************************************************************************/
10874 +
10875 +#include "site_typedefs.h"
10876 +
10877 +#else
10878 +
10879 +/*******************************************************************************
10880 + * Inferred Typedefs
10881 + *******************************************************************************/
10882 +
10883 +/* Infer the compile environment based on preprocessor symbols and pramas.
10884 + * Override type definitions as needed, and include configuration dependent
10885 + * header files to define types.
10886 + */
10887 +
10888 +#ifdef __cplusplus
10889 +
10890 +#define TYPEDEF_BOOL
10891 +#ifndef FALSE
10892 +#define FALSE false
10893 +#endif
10894 +#ifndef TRUE
10895 +#define TRUE true
10896 +#endif
10897 +
10898 +#else /* ! __cplusplus */
10899 +
10900 +#if defined(_WIN32)
10901 +
10902 +#define TYPEDEF_BOOL
10903 +typedef unsigned char bool; /* consistent w/BOOL */
10904 +
10905 +#endif /* _WIN32 */
10906 +
10907 +#endif /* ! __cplusplus */
10908 +
10909 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10910 +#if defined(_WIN64)
10911 +#include <basetsd.h>
10912 +#define TYPEDEF_UINTPTR
10913 +typedef ULONG_PTR uintptr;
10914 +#endif
10915 +
10916 +#ifdef _HNDRTE_
10917 +typedef long unsigned int size_t;
10918 +#endif
10919 +
10920 +#ifdef _MSC_VER /* Microsoft C */
10921 +#define TYPEDEF_INT64
10922 +#define TYPEDEF_UINT64
10923 +typedef signed __int64 int64;
10924 +typedef unsigned __int64 uint64;
10925 +#endif
10926 +
10927 +#if defined(MACOSX) && defined(KERNEL)
10928 +#define TYPEDEF_BOOL
10929 +#endif
10930 +
10931 +
10932 +#if defined(linux)
10933 +#define TYPEDEF_UINT
10934 +#define TYPEDEF_USHORT
10935 +#define TYPEDEF_ULONG
10936 +#endif
10937 +
10938 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10939 +#define TYPEDEF_UINT
10940 +#define TYPEDEF_USHORT
10941 +#endif
10942 +
10943 +
10944 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10945 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10946 +#define TYPEDEF_INT64
10947 +#define TYPEDEF_UINT64
10948 +#endif
10949 +
10950 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10951 + * for singned or unsigned */
10952 +#if defined(__ICL)
10953 +
10954 +#define TYPEDEF_INT64
10955 +
10956 +#if defined(__STDC__)
10957 +#define TYPEDEF_UINT64
10958 +#endif
10959 +
10960 +#endif /* __ICL */
10961 +
10962 +
10963 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10964 +
10965 +/* pick up ushort & uint from standard types.h */
10966 +#if defined(linux) && defined(__KERNEL__)
10967 +
10968 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10969 +
10970 +#else
10971 +
10972 +#include <sys/types.h>
10973 +
10974 +#endif
10975 +
10976 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10977 +
10978 +#if defined(MACOSX) && defined(KERNEL)
10979 +#include <IOKit/IOTypes.h>
10980 +#endif
10981 +
10982 +
10983 +/* use the default typedefs in the next section of this file */
10984 +#define USE_TYPEDEF_DEFAULTS
10985 +
10986 +#endif /* SITE_TYPEDEFS */
10987 +
10988 +
10989 +/*******************************************************************************
10990 + * Default Typedefs
10991 + *******************************************************************************/
10992 +
10993 +#ifdef USE_TYPEDEF_DEFAULTS
10994 +#undef USE_TYPEDEF_DEFAULTS
10995 +
10996 +#ifndef TYPEDEF_BOOL
10997 +typedef /*@abstract@*/ unsigned char bool;
10998 +#endif
10999 +
11000 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
11001 +
11002 +#ifndef TYPEDEF_UCHAR
11003 +typedef unsigned char uchar;
11004 +#endif
11005 +
11006 +#ifndef TYPEDEF_USHORT
11007 +typedef unsigned short ushort;
11008 +#endif
11009 +
11010 +#ifndef TYPEDEF_UINT
11011 +typedef unsigned int uint;
11012 +#endif
11013 +
11014 +#ifndef TYPEDEF_ULONG
11015 +typedef unsigned long ulong;
11016 +#endif
11017 +
11018 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
11019 +
11020 +#ifndef TYPEDEF_UINT8
11021 +typedef unsigned char uint8;
11022 +#endif
11023 +
11024 +#ifndef TYPEDEF_UINT16
11025 +typedef unsigned short uint16;
11026 +#endif
11027 +
11028 +#ifndef TYPEDEF_UINT32
11029 +typedef unsigned int uint32;
11030 +#endif
11031 +
11032 +#ifndef TYPEDEF_UINT64
11033 +typedef unsigned long long uint64;
11034 +#endif
11035 +
11036 +#ifndef TYPEDEF_UINTPTR
11037 +typedef unsigned int uintptr;
11038 +#endif
11039 +
11040 +#ifndef TYPEDEF_INT8
11041 +typedef signed char int8;
11042 +#endif
11043 +
11044 +#ifndef TYPEDEF_INT16
11045 +typedef signed short int16;
11046 +#endif
11047 +
11048 +#ifndef TYPEDEF_INT32
11049 +typedef signed int int32;
11050 +#endif
11051 +
11052 +#ifndef TYPEDEF_INT64
11053 +typedef signed long long int64;
11054 +#endif
11055 +
11056 +/*----------------------- define float32/64, float_t -----------------------*/
11057 +
11058 +#ifndef TYPEDEF_FLOAT32
11059 +typedef float float32;
11060 +#endif
11061 +
11062 +#ifndef TYPEDEF_FLOAT64
11063 +typedef double float64;
11064 +#endif
11065 +
11066 +/*
11067 + * abstracted floating point type allows for compile time selection of
11068 + * single or double precision arithmetic. Compiling with -DFLOAT32
11069 + * selects single precision; the default is double precision.
11070 + */
11071 +
11072 +#ifndef TYPEDEF_FLOAT_T
11073 +
11074 +#if defined(FLOAT32)
11075 +typedef float32 float_t;
11076 +#else /* default to double precision floating point */
11077 +typedef float64 float_t;
11078 +#endif
11079 +
11080 +#endif /* TYPEDEF_FLOAT_T */
11081 +
11082 +/*----------------------- define macro values -----------------------------*/
11083 +
11084 +#ifndef FALSE
11085 +#define FALSE 0
11086 +#endif
11087 +
11088 +#ifndef TRUE
11089 +#define TRUE 1
11090 +#endif
11091 +
11092 +#ifndef NULL
11093 +#define NULL 0
11094 +#endif
11095 +
11096 +#ifndef OFF
11097 +#define OFF 0
11098 +#endif
11099 +
11100 +#ifndef ON
11101 +#define ON 1
11102 +#endif
11103 +
11104 +#define AUTO (-1)
11105 +
11106 +/* Reclaiming text and data :
11107 + The following macros specify special linker sections that can be reclaimed
11108 + after a system is considered 'up'.
11109 + */
11110 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11111 +extern bool bcmreclaimed;
11112 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11113 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11114 +#define BCMINIT(_id) _id##_ini
11115 +#else
11116 +#define BCMINITDATA(_data) _data
11117 +#define BCMINITFN(_fn) _fn
11118 +#define BCMINIT(_id) _id
11119 +#define bcmreclaimed 0
11120 +#endif
11121 +
11122 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11123 +
11124 +#ifndef PTRSZ
11125 +#define PTRSZ sizeof (char*)
11126 +#endif
11127 +
11128 +#ifndef INLINE
11129 +
11130 +#ifdef _MSC_VER
11131 +
11132 +#define INLINE __inline
11133 +
11134 +#elif __GNUC__
11135 +
11136 +#define INLINE __inline__
11137 +
11138 +#else
11139 +
11140 +#define INLINE
11141 +
11142 +#endif /* _MSC_VER */
11143 +
11144 +#endif /* INLINE */
11145 +
11146 +#undef TYPEDEF_BOOL
11147 +#undef TYPEDEF_UCHAR
11148 +#undef TYPEDEF_USHORT
11149 +#undef TYPEDEF_UINT
11150 +#undef TYPEDEF_ULONG
11151 +#undef TYPEDEF_UINT8
11152 +#undef TYPEDEF_UINT16
11153 +#undef TYPEDEF_UINT32
11154 +#undef TYPEDEF_UINT64
11155 +#undef TYPEDEF_UINTPTR
11156 +#undef TYPEDEF_INT8
11157 +#undef TYPEDEF_INT16
11158 +#undef TYPEDEF_INT32
11159 +#undef TYPEDEF_INT64
11160 +#undef TYPEDEF_FLOAT32
11161 +#undef TYPEDEF_FLOAT64
11162 +#undef TYPEDEF_FLOAT_T
11163 +
11164 +#endif /* USE_TYPEDEF_DEFAULTS */
11165 +
11166 +#endif /* _TYPEDEFS_H_ */
11167 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11168 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11169 +++ linux.dev/arch/mips/bcm947xx/irq.c 2006-10-15 23:29:14.000000000 +0200
11170 @@ -0,0 +1,64 @@
11171 +/*
11172 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11173 + *
11174 + * This program is free software; you can redistribute it and/or modify it
11175 + * under the terms of the GNU General Public License as published by the
11176 + * Free Software Foundation; either version 2 of the License, or (at your
11177 + * option) any later version.
11178 + *
11179 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11180 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11181 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11182 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11183 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11184 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11185 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11186 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11187 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11188 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11189 + *
11190 + * You should have received a copy of the GNU General Public License along
11191 + * with this program; if not, write to the Free Software Foundation, Inc.,
11192 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11193 + */
11194 +
11195 +#include <linux/config.h>
11196 +#include <linux/errno.h>
11197 +#include <linux/init.h>
11198 +#include <linux/interrupt.h>
11199 +#include <linux/irq.h>
11200 +#include <linux/module.h>
11201 +#include <linux/smp.h>
11202 +#include <linux/types.h>
11203 +
11204 +#include <asm/cpu.h>
11205 +#include <asm/io.h>
11206 +#include <asm/irq.h>
11207 +#include <asm/irq_cpu.h>
11208 +
11209 +void plat_irq_dispatch(struct pt_regs *regs)
11210 +{
11211 + u32 cause;
11212 +
11213 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11214 +
11215 + clear_c0_status(cause);
11216 +
11217 + if (cause & CAUSEF_IP7)
11218 + do_IRQ(7, regs);
11219 + if (cause & CAUSEF_IP2)
11220 + do_IRQ(2, regs);
11221 + if (cause & CAUSEF_IP3)
11222 + do_IRQ(3, regs);
11223 + if (cause & CAUSEF_IP4)
11224 + do_IRQ(4, regs);
11225 + if (cause & CAUSEF_IP5)
11226 + do_IRQ(5, regs);
11227 + if (cause & CAUSEF_IP6)
11228 + do_IRQ(6, regs);
11229 +}
11230 +
11231 +void __init arch_init_irq(void)
11232 +{
11233 + mips_cpu_irq_init(0);
11234 +}
11235 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
11236 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
11237 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-15 23:29:14.000000000 +0200
11238 @@ -0,0 +1,6 @@
11239 +#
11240 +# Makefile for the BCM47xx specific kernel interface routines
11241 +# under Linux.
11242 +#
11243 +
11244 +obj-y := irq.o prom.o setup.o time.o pci.o
11245 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11246 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11247 +++ linux.dev/arch/mips/bcm947xx/pci.c 2006-10-15 23:29:14.000000000 +0200
11248 @@ -0,0 +1,227 @@
11249 +#include <linux/kernel.h>
11250 +#include <linux/init.h>
11251 +#include <linux/pci.h>
11252 +#include <linux/types.h>
11253 +
11254 +#include <asm/cpu.h>
11255 +#include <asm/io.h>
11256 +
11257 +#include <typedefs.h>
11258 +#include <osl.h>
11259 +#include <sbutils.h>
11260 +#include <sbmips.h>
11261 +#include <sbconfig.h>
11262 +#include <sbpci.h>
11263 +#include <bcmdevs.h>
11264 +#include <pcicfg.h>
11265 +
11266 +extern sb_t *sbh;
11267 +extern spinlock_t sbh_lock;
11268 +
11269 +
11270 +static int
11271 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11272 + int reg, int size, u32 *val)
11273 +{
11274 + int ret;
11275 + unsigned long flags;
11276 +
11277 + spin_lock_irqsave(&sbh_lock, flags);
11278 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11279 + spin_unlock_irqrestore(&sbh_lock, flags);
11280 +
11281 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11282 +}
11283 +
11284 +static int
11285 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11286 + int reg, int size, u32 val)
11287 +{
11288 + int ret;
11289 + unsigned long flags;
11290 +
11291 + spin_lock_irqsave(&sbh_lock, flags);
11292 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11293 + spin_unlock_irqrestore(&sbh_lock, flags);
11294 +
11295 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11296 +}
11297 +
11298 +
11299 +static struct pci_ops sb_pci_ops = {
11300 + .read = sb_pci_read_config,
11301 + .write = sb_pci_write_config,
11302 +};
11303 +
11304 +static struct resource sb_pci_mem_resource = {
11305 + .name = "SB PCI Memory resources",
11306 + .start = SB_ENUM_BASE,
11307 + .end = SB_ENUM_LIM - 1,
11308 + .flags = IORESOURCE_MEM,
11309 +};
11310 +
11311 +static struct resource sb_pci_io_resource = {
11312 + .name = "SB PCI I/O resources",
11313 + .start = 0x000,
11314 + .end = 0x0FF,
11315 + .flags = IORESOURCE_IO,
11316 +};
11317 +
11318 +static struct pci_controller bcm47xx_sb_pci_controller = {
11319 + .pci_ops = &sb_pci_ops,
11320 + .mem_resource = &sb_pci_mem_resource,
11321 + .io_resource = &sb_pci_io_resource,
11322 +};
11323 +
11324 +static struct resource ext_pci_mem_resource = {
11325 + .name = "Ext PCI Memory resources",
11326 + .start = 0x40000000,
11327 + .end = 0x7fffffff,
11328 + .flags = IORESOURCE_MEM,
11329 +};
11330 +
11331 +static struct resource ext_pci_io_resource = {
11332 + .name = "Ext PCI I/O resources",
11333 + .start = 0x100,
11334 + .end = 0x7FF,
11335 + .flags = IORESOURCE_IO,
11336 +};
11337 +
11338 +static struct pci_controller bcm47xx_ext_pci_controller = {
11339 + .pci_ops = &sb_pci_ops,
11340 + .io_resource = &ext_pci_io_resource,
11341 + .mem_resource = &ext_pci_mem_resource,
11342 + .mem_offset = 0x24000000,
11343 +};
11344 +
11345 +void bcm47xx_pci_init(void)
11346 +{
11347 + unsigned long flags;
11348 +
11349 + spin_lock_irqsave(&sbh_lock, flags);
11350 + sbpci_init(sbh);
11351 + spin_unlock_irqrestore(&sbh_lock, flags);
11352 +
11353 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11354 +
11355 + register_pci_controller(&bcm47xx_sb_pci_controller);
11356 + register_pci_controller(&bcm47xx_ext_pci_controller);
11357 +}
11358 +
11359 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11360 +{
11361 + unsigned long flags;
11362 + u8 irq;
11363 + uint idx;
11364 +
11365 + /* external: use the irq of the pci core */
11366 + if (dev->bus->number >= 1) {
11367 + spin_lock_irqsave(&sbh_lock, flags);
11368 + idx = sb_coreidx(sbh);
11369 + sb_setcore(sbh, SB_PCI, 0);
11370 + irq = sb_irq(sbh);
11371 + sb_setcoreidx(sbh, idx);
11372 + spin_unlock_irqrestore(&sbh_lock, flags);
11373 +
11374 + return irq + 2;
11375 + }
11376 +
11377 + /* internal */
11378 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11379 + return irq + 2;
11380 +}
11381 +
11382 +u32 pci_iobase = 0x100;
11383 +u32 pci_membase = SB_PCI_DMA;
11384 +
11385 +static void bcm47xx_fixup_device(struct pci_dev *d)
11386 +{
11387 + struct resource *res;
11388 + int pos, size;
11389 + u32 *base;
11390 +
11391 + if (d->bus->number == 0)
11392 + return;
11393 +
11394 + printk("PCI: Fixing up device %s\n", pci_name(d));
11395 +
11396 + /* Fix up resource bases */
11397 + for (pos = 0; pos < 6; pos++) {
11398 + res = &d->resource[pos];
11399 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11400 + if (res->end) {
11401 + size = res->end - res->start + 1;
11402 + if (*base & (size - 1))
11403 + *base = (*base + size) & ~(size - 1);
11404 + res->start = *base;
11405 + res->end = res->start + size - 1;
11406 + *base += size;
11407 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11408 + }
11409 + /* Fix up PCI bridge BAR0 only */
11410 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11411 + break;
11412 + }
11413 + /* Fix up interrupt lines */
11414 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11415 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11416 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11417 +}
11418 +
11419 +
11420 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11421 +{
11422 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11423 + return;
11424 +
11425 + printk("PCI: fixing up bridge\n");
11426 +
11427 + /* Enable PCI bridge bus mastering and memory space */
11428 + pci_set_master(dev);
11429 + pcibios_enable_device(dev, ~0);
11430 +
11431 + /* Enable PCI bridge BAR1 prefetch and burst */
11432 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11433 +}
11434 +
11435 +/* Do platform specific device initialization at pci_enable_device() time */
11436 +int pcibios_plat_dev_init(struct pci_dev *dev)
11437 +{
11438 + uint coreidx;
11439 + unsigned long flags;
11440 +
11441 + bcm47xx_fixup_device(dev);
11442 +
11443 + /* These cores come out of reset enabled */
11444 + if ((dev->bus->number != 0) ||
11445 + (dev->device == SB_MIPS) ||
11446 + (dev->device == SB_MIPS33) ||
11447 + (dev->device == SB_EXTIF) ||
11448 + (dev->device == SB_CC))
11449 + return 0;
11450 +
11451 + /* Do a core reset */
11452 + spin_lock_irqsave(&sbh_lock, flags);
11453 + coreidx = sb_coreidx(sbh);
11454 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11455 + /*
11456 + * The USB core requires a special bit to be set during core
11457 + * reset to enable host (OHCI) mode. Resetting the SB core in
11458 + * pcibios_enable_device() is a hack for compatibility with
11459 + * vanilla usb-ohci so that it does not have to know about
11460 + * SB. A driver that wants to use the USB core in device mode
11461 + * should know about SB and should reset the bit back to 0
11462 + * after calling pcibios_enable_device().
11463 + */
11464 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11465 + sb_core_reset(sbh, 1 << 29);
11466 + } else {
11467 + sb_core_reset(sbh, 0);
11468 + }
11469 + sb_setcoreidx(sbh, coreidx);
11470 + spin_unlock_irqrestore(&sbh_lock, flags);
11471 +
11472 + return 0;
11473 +}
11474 +
11475 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11476 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11477 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11478 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-15 23:29:14.000000000 +0200
11479 @@ -0,0 +1,59 @@
11480 +/*
11481 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11482 + *
11483 + * This program is free software; you can redistribute it and/or modify it
11484 + * under the terms of the GNU General Public License as published by the
11485 + * Free Software Foundation; either version 2 of the License, or (at your
11486 + * option) any later version.
11487 + *
11488 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11489 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11490 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11491 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11492 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11493 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11494 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11495 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11496 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11497 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11498 + *
11499 + * You should have received a copy of the GNU General Public License along
11500 + * with this program; if not, write to the Free Software Foundation, Inc.,
11501 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11502 + */
11503 +
11504 +#include <linux/init.h>
11505 +#include <linux/mm.h>
11506 +#include <linux/sched.h>
11507 +#include <linux/bootmem.h>
11508 +
11509 +#include <asm/addrspace.h>
11510 +#include <asm/bootinfo.h>
11511 +#include <asm/pmon.h>
11512 +
11513 +const char *get_system_type(void)
11514 +{
11515 + return "Broadcom BCM47xx";
11516 +}
11517 +
11518 +void __init prom_init(void)
11519 +{
11520 + unsigned long mem;
11521 +
11522 + mips_machgroup = MACH_GROUP_BRCM;
11523 + mips_machtype = MACH_BCM47XX;
11524 +
11525 + /* Figure out memory size by finding aliases */
11526 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11527 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11528 + *(unsigned long *)(prom_init))
11529 + break;
11530 + }
11531 +
11532 + add_memory_region(0, mem, BOOT_MEM_RAM);
11533 +}
11534 +
11535 +unsigned long __init prom_free_prom_memory(void)
11536 +{
11537 + return 0;
11538 +}
11539 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11540 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11541 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-15 23:29:14.000000000 +0200
11542 @@ -0,0 +1,158 @@
11543 +/*
11544 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11545 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11546 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11547 + *
11548 + * This program is free software; you can redistribute it and/or modify it
11549 + * under the terms of the GNU General Public License as published by the
11550 + * Free Software Foundation; either version 2 of the License, or (at your
11551 + * option) any later version.
11552 + *
11553 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11554 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11555 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11556 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11557 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11558 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11559 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11560 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11561 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11562 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11563 + *
11564 + * You should have received a copy of the GNU General Public License along
11565 + * with this program; if not, write to the Free Software Foundation, Inc.,
11566 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11567 + */
11568 +
11569 +#include <linux/init.h>
11570 +#include <linux/types.h>
11571 +#include <linux/tty.h>
11572 +#include <linux/serial.h>
11573 +#include <linux/serial_core.h>
11574 +#include <linux/serial_reg.h>
11575 +#include <asm/bootinfo.h>
11576 +#include <asm/time.h>
11577 +#include <asm/reboot.h>
11578 +#include <linux/pm.h>
11579 +
11580 +#include <typedefs.h>
11581 +#include <osl.h>
11582 +#include <sbutils.h>
11583 +#include <sbmips.h>
11584 +#include <sbpci.h>
11585 +#include <sbconfig.h>
11586 +#include <bcmdevs.h>
11587 +#include <bcmutils.h>
11588 +#include <bcmnvram.h>
11589 +
11590 +extern void bcm47xx_pci_init(void);
11591 +extern void bcm47xx_time_init(void);
11592 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11593 +void *sbh;
11594 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11595 +int boardflags;
11596 +
11597 +static int ser_line = 0;
11598 +
11599 +typedef struct {
11600 + void *regs;
11601 + uint irq;
11602 + uint baud_base;
11603 + uint reg_shift;
11604 +} serial_port;
11605 +
11606 +static serial_port ports[4];
11607 +static int num_ports = 0;
11608 +
11609 +static void
11610 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11611 +{
11612 + ports[num_ports].regs = regs;
11613 + ports[num_ports].irq = irq;
11614 + ports[num_ports].baud_base = baud_base;
11615 + ports[num_ports].reg_shift = reg_shift;
11616 + num_ports++;
11617 +}
11618 +
11619 +static void
11620 +do_serial_add(serial_port *port)
11621 +{
11622 + void *regs;
11623 + uint irq;
11624 + uint baud_base;
11625 + uint reg_shift;
11626 + struct uart_port s;
11627 +
11628 + regs = port->regs;
11629 + irq = port->irq;
11630 + baud_base = port->baud_base;
11631 + reg_shift = port->reg_shift;
11632 +
11633 + memset(&s, 0, sizeof(s));
11634 +
11635 + s.line = ser_line++;
11636 + s.membase = regs;
11637 + s.irq = irq + 2;
11638 + s.uartclk = baud_base;
11639 + s.flags = ASYNC_BOOT_AUTOCONF;
11640 + s.iotype = SERIAL_IO_MEM;
11641 + s.regshift = reg_shift;
11642 +
11643 + if (early_serial_setup(&s) != 0) {
11644 + printk(KERN_ERR "Serial setup failed!\n");
11645 + }
11646 +}
11647 +
11648 +static void bcm47xx_machine_restart(char *command)
11649 +{
11650 + printk("Please stand by while rebooting the system...\n");
11651 +
11652 + /* Set the watchdog timer to reset immediately */
11653 + local_irq_disable();
11654 + sb_watchdog(sbh, 1);
11655 + while (1);
11656 +}
11657 +
11658 +static void bcm47xx_machine_halt(void)
11659 +{
11660 + /* Disable interrupts and watchdog and spin forever */
11661 + local_irq_disable();
11662 + sb_watchdog(sbh, 0);
11663 + while (1);
11664 +}
11665 +
11666 +void __init plat_setup(void)
11667 +{
11668 + char *s;
11669 + int i;
11670 +
11671 + sbh = (void *) sb_kattach();
11672 + sb_mips_init(sbh);
11673 +
11674 + bcm47xx_pci_init();
11675 +
11676 + sb_serial_init(sbh, serial_add);
11677 + boardflags = getintvar(NULL, "boardflags");
11678 +
11679 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11680 + s = early_nvram_get("kernel_args");
11681 + if (!s) s = "";
11682 + if (!strncmp(s, "console=ttyS1", 13)) {
11683 + for (i = num_ports; i; i--)
11684 + do_serial_add(&ports[i - 1]);
11685 + } else {
11686 + for (i = 0; i < num_ports; i++)
11687 + do_serial_add(&ports[i]);
11688 + }
11689 +
11690 + _machine_restart = bcm47xx_machine_restart;
11691 + _machine_halt = bcm47xx_machine_halt;
11692 + pm_power_off = bcm47xx_machine_halt;
11693 +
11694 + board_time_init = bcm47xx_time_init;
11695 + board_timer_setup = bcm47xx_timer_setup;
11696 +}
11697 +
11698 +EXPORT_SYMBOL(sbh);
11699 +EXPORT_SYMBOL(sbh_lock);
11700 +EXPORT_SYMBOL(boardflags);
11701 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11702 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11703 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-15 23:38:36.000000000 +0200
11704 @@ -0,0 +1,65 @@
11705 +/*
11706 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11707 + *
11708 + * This program is free software; you can redistribute it and/or modify it
11709 + * under the terms of the GNU General Public License as published by the
11710 + * Free Software Foundation; either version 2 of the License, or (at your
11711 + * option) any later version.
11712 + *
11713 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11714 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11715 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11716 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11717 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11718 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11719 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11720 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11721 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11722 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11723 + *
11724 + * You should have received a copy of the GNU General Public License along
11725 + * with this program; if not, write to the Free Software Foundation, Inc.,
11726 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11727 + */
11728 +
11729 +#include <linux/config.h>
11730 +#include <linux/init.h>
11731 +#include <linux/kernel.h>
11732 +#include <linux/sched.h>
11733 +#include <linux/serial_reg.h>
11734 +#include <linux/interrupt.h>
11735 +#include <asm/addrspace.h>
11736 +#include <asm/io.h>
11737 +#include <asm/time.h>
11738 +#include <typedefs.h>
11739 +#include <osl.h>
11740 +#include <sbutils.h>
11741 +#include <sbmips.h>
11742 +
11743 +extern sb_t *sbh;
11744 +
11745 +void __init
11746 +bcm47xx_time_init(void)
11747 +{
11748 + unsigned int hz;
11749 +
11750 + /*
11751 + * Use deterministic values for initial counter interrupt
11752 + * so that calibrate delay avoids encountering a counter wrap.
11753 + */
11754 + write_c0_count(0);
11755 + write_c0_compare(0xffff);
11756 +
11757 + hz = sb_cpu_clock(sbh);
11758 +
11759 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11760 + mips_hpt_frequency = hz / 2;
11761 +
11762 +}
11763 +
11764 +void __init
11765 +bcm47xx_timer_setup(struct irqaction *irq)
11766 +{
11767 + /* Enable the timer interrupt */
11768 + setup_irq(7, irq);
11769 +}
11770 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
11771 --- linux.old/arch/mips/Kconfig 2006-10-15 23:32:44.000000000 +0200
11772 +++ linux.dev/arch/mips/Kconfig 2006-10-15 23:29:14.000000000 +0200
11773 @@ -245,6 +245,17 @@
11774 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
11775 Olivetti M700-10 workstations.
11776
11777 +config BCM947XX
11778 + bool "Support for BCM947xx based boards"
11779 + select DMA_NONCOHERENT
11780 + select HW_HAS_PCI
11781 + select IRQ_CPU
11782 + select SYS_HAS_CPU_MIPS32_R1
11783 + select SYS_SUPPORTS_32BIT_KERNEL
11784 + select SYS_SUPPORTS_LITTLE_ENDIAN
11785 + help
11786 + Support for BCM947xx based boards
11787 +
11788 config LASAT
11789 bool "LASAT Networks platforms"
11790 select DMA_NONCOHERENT
11791 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11792 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-15 23:32:44.000000000 +0200
11793 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-15 23:29:14.000000000 +0200
11794 @@ -691,6 +691,28 @@
11795 }
11796
11797
11798 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11799 +{
11800 + decode_config1(c);
11801 + switch (c->processor_id & 0xff00) {
11802 + case PRID_IMP_BCM3302:
11803 + c->cputype = CPU_BCM3302;
11804 + c->isa_level = MIPS_CPU_ISA_M32R1;
11805 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11806 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11807 + break;
11808 + case PRID_IMP_BCM4710:
11809 + c->cputype = CPU_BCM4710;
11810 + c->isa_level = MIPS_CPU_ISA_M32R1;
11811 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11812 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11813 + break;
11814 + default:
11815 + c->cputype = CPU_UNKNOWN;
11816 + break;
11817 + }
11818 +}
11819 +
11820 __init void cpu_probe(void)
11821 {
11822 struct cpuinfo_mips *c = &current_cpu_data;
11823 @@ -713,6 +735,9 @@
11824 case PRID_COMP_SIBYTE:
11825 cpu_probe_sibyte(c);
11826 break;
11827 + case PRID_COMP_BROADCOM:
11828 + cpu_probe_broadcom(c);
11829 + break;
11830 case PRID_COMP_SANDCRAFT:
11831 cpu_probe_sandcraft(c);
11832 break;
11833 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11834 --- linux.old/arch/mips/kernel/head.S 2006-10-15 23:32:44.000000000 +0200
11835 +++ linux.dev/arch/mips/kernel/head.S 2006-10-15 23:29:14.000000000 +0200
11836 @@ -133,6 +133,11 @@
11837 j kernel_entry
11838 nop
11839
11840 +#ifdef CONFIG_BCM4710
11841 +#undef eret
11842 +#define eret nop; nop; eret
11843 +#endif
11844 +
11845 /*
11846 * Reserved space for exception handlers.
11847 * Necessary for machines which link their kernels at KSEG0.
11848 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11849 --- linux.old/arch/mips/kernel/proc.c 2006-10-15 23:32:44.000000000 +0200
11850 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-15 23:29:14.000000000 +0200
11851 @@ -84,6 +84,8 @@
11852 [CPU_VR4181] = "NEC VR4181",
11853 [CPU_VR4181A] = "NEC VR4181A",
11854 [CPU_SR71000] = "Sandcraft SR71000",
11855 + [CPU_BCM3302] = "Broadcom BCM3302",
11856 + [CPU_BCM4710] = "Broadcom BCM4710",
11857 [CPU_PR4450] = "Philips PR4450",
11858 };
11859
11860 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
11861 --- linux.old/arch/mips/Makefile 2006-10-15 23:32:44.000000000 +0200
11862 +++ linux.dev/arch/mips/Makefile 2006-10-15 23:29:14.000000000 +0200
11863 @@ -565,6 +565,13 @@
11864 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
11865
11866 #
11867 +# Broadcom BCM47XX boards
11868 +#
11869 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
11870 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
11871 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
11872 +
11873 +#
11874 # SNI RM200 PCI
11875 #
11876 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
11877 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11878 --- linux.old/arch/mips/mm/tlbex.c 2006-10-15 23:32:44.000000000 +0200
11879 +++ linux.dev/arch/mips/mm/tlbex.c 2006-10-15 23:31:06.000000000 +0200
11880 @@ -882,6 +882,8 @@
11881 case CPU_4KSC:
11882 case CPU_20KC:
11883 case CPU_25KF:
11884 + case CPU_BCM3302:
11885 + case CPU_BCM4710:
11886 tlbw(p);
11887 break;
11888
11889 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11890 --- linux.old/include/asm-mips/bootinfo.h 2006-10-15 23:32:44.000000000 +0200
11891 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-15 23:29:14.000000000 +0200
11892 @@ -218,6 +218,12 @@
11893 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11894 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11895
11896 +/*
11897 + * Valid machtype for group Broadcom
11898 + */
11899 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11900 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11901 +
11902 #define CL_SIZE COMMAND_LINE_SIZE
11903
11904 const char *get_system_type(void);
11905 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11906 --- linux.old/include/asm-mips/cpu.h 2006-10-15 23:32:44.000000000 +0200
11907 +++ linux.dev/include/asm-mips/cpu.h 2006-10-15 23:29:14.000000000 +0200
11908 @@ -104,6 +104,13 @@
11909 #define PRID_IMP_SR71000 0x0400
11910
11911 /*
11912 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11913 + */
11914 +
11915 +#define PRID_IMP_BCM4710 0x4000
11916 +#define PRID_IMP_BCM3302 0x9000
11917 +
11918 +/*
11919 * Definitions for 7:0 on legacy processors
11920 */
11921
11922 @@ -200,7 +207,9 @@
11923 #define CPU_SB1A 62
11924 #define CPU_74K 63
11925 #define CPU_R14000 64
11926 -#define CPU_LAST 64
11927 +#define CPU_BCM3302 65
11928 +#define CPU_BCM4710 66
11929 +#define CPU_LAST 66
11930
11931 /*
11932 * ISA Level encodings
11933 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11934 --- linux.old/include/linux/pci_ids.h 2006-10-15 23:32:44.000000000 +0200
11935 +++ linux.dev/include/linux/pci_ids.h 2006-10-15 23:29:14.000000000 +0200
11936 @@ -1906,6 +1906,7 @@
11937 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11938 #define PCI_DEVICE_ID_BCM4401 0x4401
11939 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11940 +#define PCI_DEVICE_ID_BCM4713 0x4713
11941
11942 #define PCI_VENDOR_ID_TOPIC 0x151f
11943 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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