projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
fix board support patch and add mtd flash map driver for ar7
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -ruN linux_2_4_30/Makefile linux/Makefile
2 --- linux_2_4_30/Makefile 2005-05-22 18:23:27.000000000 +0000
3 +++ linux/Makefile 2005-06-12 11:49:50.000000000 +0000
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -ruN linux_2_4_30/arch/mips/Makefile linux/arch/mips/Makefile
14 --- linux_2_4_30/arch/mips/Makefile 2005-05-22 18:24:01.000000000 +0000
15 +++ linux/arch/mips/Makefile 2005-06-11 09:41:27.000000000 +0000
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
25 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -ruN linux_2_4_30/arch/mips/ar7/Makefile linux/arch/mips/ar7/Makefile
34 --- linux_2_4_30/arch/mips/ar7/Makefile 1970-01-01 00:00:00.000000000 +0000
35 +++ linux/arch/mips/ar7/Makefile 2005-06-11 12:36:01.000000000 +0000
36 @@ -0,0 +1,12 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +O_TARGET := ar7.o
44 +
45 +obj-y := tnetd73xx_misc.o
46 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
47 +
48 +include $(TOPDIR)/Rules.make
49 diff -ruN linux_2_4_30/arch/mips/ar7/avalanche/Makefile linux/arch/mips/ar7/avalanche/Makefile
50 --- linux_2_4_30/arch/mips/ar7/avalanche/Makefile 1970-01-01 00:00:00.000000000 +0000
51 +++ linux/arch/mips/ar7/avalanche/Makefile 2005-06-11 07:59:49.000000000 +0000
52 @@ -0,0 +1,13 @@
53 +.S.s:
54 + $(CPP) $(AFLAGS) $< -o $*.s
55 +
56 +.S.o:
57 + $(CC) $(AFLAGS) -c $< -o $*.o
58 +
59 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
60 +
61 +O_TARGET := avalanche.o
62 +
63 +obj-y += avalanche_paging.o avalanche_jump.o
64 +
65 +include $(TOPDIR)/Rules.make
66 diff -ruN linux_2_4_30/arch/mips/ar7/avalanche/avalanche_jump.S linux/arch/mips/ar7/avalanche/avalanche_jump.S
67 --- linux_2_4_30/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 00:00:00.000000000 +0000
68 +++ linux/arch/mips/ar7/avalanche/avalanche_jump.S 2005-06-11 17:20:29.000000000 +0000
69 @@ -0,0 +1,69 @@
70 +#include <linux/config.h>
71 +#include <linux/threads.h>
72 +
73 +#include <asm/asm.h>
74 +#include <asm/cacheops.h>
75 +#include <asm/current.h>
76 +#include <asm/offset.h>
77 +#include <asm/processor.h>
78 +#include <asm/regdef.h>
79 +#include <asm/cachectl.h>
80 +#include <asm/mipsregs.h>
81 +#include <asm/stackframe.h>
82 +
83 +.text
84 +
85 +.set noreorder
86 +.set noat
87 +
88 +/* TLB Miss Vector */
89 +
90 +LEAF(jump_tlb_miss)
91 + .set mips2
92 + lui k0,0x9400
93 + ori k0,0
94 + jr k0
95 + nop
96 +END(jump_tlb_miss)
97 +
98 + /* Unused TLB Miss Vector */
99 +
100 +LEAF(jump_tlb_miss_unused)
101 + .set mips2
102 + lui k0,0x9400
103 + ori k0,0x80
104 + jr k0
105 + nop
106 +END(jump_tlb_miss_unused)
107 +
108 + /* Cache Error Vector */
109 +
110 +LEAF(jump_cache_error)
111 + .set mips2
112 + lui k0,0x9400
113 + ori k0,0x100
114 + jr k0
115 + nop
116 +END(jump_cache_error)
117 +
118 + /* General Exception */
119 +
120 +LEAF(jump_general_exception)
121 + .set mips2
122 + lui k0,0x9400
123 + ori k0,0x180
124 + jr k0
125 + nop
126 +END(jump_general_exception)
127 +
128 + /* Dedicated Interrupt */
129 +
130 +LEAF(jump_dedicated_interrupt)
131 + .set mips2
132 + lui k0,0x9400
133 + ori k0,0x200
134 + jr k0
135 + nop
136 +END(jump_dedicated_interrupt)
137 +
138 + .set at
139 diff -ruN linux_2_4_30/arch/mips/ar7/avalanche/avalanche_paging.c linux/arch/mips/ar7/avalanche/avalanche_paging.c
140 --- linux_2_4_30/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 00:00:00.000000000 +0000
141 +++ linux/arch/mips/ar7/avalanche/avalanche_paging.c 2005-06-12 10:21:34.000000000 +0000
142 @@ -0,0 +1,314 @@
143 +/*
144 + * -*- linux-c -*-
145 + * This file is subject to the terms and conditions of the GNU General Public
146 + * License. See the file "COPYING" in the main directory of this archive
147 + * for more details.
148 + *
149 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
150 + * Copyright (C) 2002 Texas Instruments, Inc.
151 + *
152 + */
153 +
154 +/*
155 + * This file takes care of the "memory hole" issue that exists with the standard
156 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
157 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
158 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
159 + *
160 + * -JAH
161 + */
162 +#include <linux/config.h>
163 +#include <linux/signal.h>
164 +#include <linux/sched.h>
165 +#include <linux/kernel.h>
166 +#include <linux/errno.h>
167 +#include <linux/string.h>
168 +#include <linux/types.h>
169 +#include <linux/ptrace.h>
170 +#include <linux/mman.h>
171 +#include <linux/mm.h>
172 +#include <linux/swap.h>
173 +#include <linux/smp.h>
174 +#include <linux/init.h>
175 +#ifdef CONFIG_BLK_DEV_INITRD
176 +#include <linux/blk.h>
177 +#endif /* CONFIG_BLK_DEV_INITRD */
178 +#include <linux/highmem.h>
179 +#include <linux/bootmem.h>
180 +
181 +#include <asm/processor.h>
182 +#include <asm/system.h>
183 +#include <asm/uaccess.h>
184 +#include <asm/pgtable.h>
185 +#include <asm/pgalloc.h>
186 +#include <asm/mmu_context.h>
187 +#include <asm/io.h>
188 +#include <asm/tlb.h>
189 +#include <asm/cpu.h>
190 +
191 +#define __MEMORY_START CONFIG_AR7_MEMORY
192 +
193 +#ifdef CONFIG_DISCONTIGMEM
194 +pg_data_t discontig_page_data[NR_NODES];
195 +bootmem_data_t discontig_node_bdata[NR_NODES];
196 +#endif
197 +
198 +static unsigned long totalram_pages;
199 +/* static unsigned long totalhigh_pages; */
200 +
201 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
202 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
203 +
204 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
205 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
206 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
207 +
208 +unsigned long bootmap_size;
209 +
210 +extern char *prom_getenv(char *envname);
211 +
212 +/*
213 + * We have upto 8 empty zeroed pages so we can map one of the right colour
214 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
215 + * where we have to avoid VCED / VECI exceptions for good performance at
216 + * any price. Since page is never written to after the initialization we
217 + * don't have to care about aliases on other CPUs.
218 + */
219 +
220 +static inline unsigned long setup_zero_pages(void)
221 +{
222 + unsigned long order, size;
223 + struct page *page;
224 + if(current_cpu_data.options & MIPS_CPU_VCE)
225 + order = 3;
226 + else
227 + order = 0;
228 +
229 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
230 +
231 + if (!empty_zero_page)
232 + panic("Oh boy, that early out of memory?");
233 +
234 + page = virt_to_page(empty_zero_page);
235 +
236 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
237 + set_bit(PG_reserved, &page->flags);
238 + set_page_count(page, 0);
239 + page++;
240 + }
241 +
242 + size = PAGE_SIZE << order;
243 + zero_page_mask = (size - 1) & PAGE_MASK;
244 + memset((void *)empty_zero_page, 0, size);
245 +
246 + return 1UL << order;
247 +}
248 +
249 +/*
250 + * paging_init() sets up the page tables
251 + *
252 + * This routines also unmaps the page at virtual kernel address 0, so
253 + * that we can trap those pesky NULL-reference errors in the kernel.
254 + */
255 +void __init paging_init(void)
256 +{
257 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
258 + unsigned long low, start_pfn;
259 +
260 + /* Initialize the entire pgd. */
261 + pgd_init((unsigned long)swapper_pg_dir);
262 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
263 +
264 +
265 + start_pfn = START_PFN;
266 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
267 + low = MAX_LOW_PFN;
268 +
269 + /* Avalanche DMA-able memory 0x14000000+memsize */
270 +
271 + zones_size[ZONE_DMA] = low - start_pfn;
272 +
273 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
274 +
275 +#ifdef CONFIG_DISCONTIGMEM
276 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
277 + zones_size[ZONE_NORMAL] = 0;
278 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
279 +#endif /* CONFIG_DISCONTIGMEM */
280 +
281 +}
282 +
283 +extern char _ftext, _etext, _fdata, _edata, _end;
284 +extern char __init_begin, __init_end;
285 +
286 +void __init mem_init(void)
287 +{
288 + int codesize, reservedpages, datasize, initsize;
289 + int tmp;
290 +
291 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
292 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
293 +
294 + /* free up the memory associated with Adam2 -
295 + * that is the, after the first page that is
296 + * reserved all the way up to the start of the kernel
297 + */
298 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
299 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
300 +
301 + /* this will put all low memory onto the freelists */
302 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
303 +
304 + /* Setup zeroed pages */
305 + totalram_pages -= setup_zero_pages();
306 +
307 +
308 +#ifdef CONFIG_DISCONTIGMEM
309 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
310 +#endif
311 + reservedpages = 0;
312 + for (tmp = 0; tmp < num_physpages; tmp++)
313 + /*
314 + * Only count reserved RAM pages
315 + */
316 + if (PageReserved(mem_map+tmp))
317 + reservedpages++;
318 +
319 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
320 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
321 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
322 +
323 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
324 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
325 + max_mapnr << (PAGE_SHIFT-10),
326 + codesize >> 10,
327 + reservedpages << (PAGE_SHIFT-10),
328 + datasize >> 10,
329 + initsize >> 10);
330 +
331 +}
332 +
333 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
334 +
335 +void avalanche_bootmem_init(void)
336 +{
337 + unsigned long start_pfn, max_pfn;
338 + unsigned long max_low_pfn;
339 + unsigned int memsize,memory_end,memory_start;
340 + char *memsize_str;
341 +
342 + memsize_str = prom_getenv("memsize");
343 + if (!memsize_str) {
344 + memsize = 0x02000000;
345 + } else {
346 + memsize = simple_strtol(memsize_str, NULL, 0);
347 + }
348 +
349 +
350 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
351 + memory_end = memory_start + memsize;
352 +
353 + /*
354 + * Find the highest memory page fram number we have available
355 + */
356 +
357 + max_pfn = PFN_DOWN(__pa(memory_end));
358 +
359 + /*
360 + * Determine the low and high memory ranges
361 + */
362 +
363 + max_low_pfn = max_pfn;
364 +
365 + /*
366 + * Partially used pages are not usable - thus we are
367 + * rounding upwards:
368 + */
369 +
370 + start_pfn = PFN_UP(__pa(&_end));
371 +
372 + /*
373 + * Find a proper area for the bootmem bitmap. After this
374 + * bootstrap step all allocations (until the page allocator is
375 + * intact) must be done via bootmem_alloc().
376 + */
377 +
378 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
379 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
380 +
381 +
382 + /*
383 + * Register fully available low RAM pages with the bootmem allocator.
384 + */
385 +
386 + {
387 + unsigned long curr_pfn, last_pfn, pages;
388 +
389 + /*
390 + * We are rounding up the start address of usable memory:
391 + */
392 + curr_pfn = PFN_UP(__MEMORY_START);
393 +
394 + /*
395 + * ... and at the end of the usable range downwards:
396 + */
397 + last_pfn = PFN_DOWN(__pa(memory_end));
398 +
399 + if (last_pfn > max_low_pfn)
400 + last_pfn = max_low_pfn;
401 +
402 + pages = last_pfn - curr_pfn;
403 +
404 +
405 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
406 + PFN_PHYS(pages));
407 + }
408 +
409 + /*
410 + * Reserve the kernel text and
411 + * Reserve the bootmem bitmap. We do this in two steps (first step
412 + * was init_bootmem()), because this catches the (definitely buggy)
413 + * case of us accidentally initializing the bootmem allocator with
414 + * an invalid RAM area.
415 + */
416 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
417 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
418 +
419 + /*
420 + * reserve physical page 0 - it's a special BIOS page on many boxes,
421 + * enabling clean reboots, SMP operation, laptop functions.
422 + */
423 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
424 +}
425 +
426 +extern char __init_begin, __init_end;
427 +
428 +void free_initmem(void)
429 +{
430 + unsigned long addr;
431 + // prom_free_prom_memory ();
432 +
433 + addr = (unsigned long) &__init_begin;
434 + while (addr < (unsigned long) &__init_end) {
435 + ClearPageReserved(virt_to_page(addr));
436 + set_page_count(virt_to_page(addr), 1);
437 + free_page(addr);
438 + totalram_pages++;
439 + addr += PAGE_SIZE;
440 + }
441 + printk("Freeing unused kernel memory: %dk freed\n",
442 + (&__init_end - &__init_begin) >> 10);
443 +}
444 +
445 +void si_meminfo(struct sysinfo *val)
446 +{
447 + val->totalram = totalram_pages;
448 + val->sharedram = 0;
449 + val->freeram = nr_free_pages();
450 + val->bufferram = atomic_read(&buffermem_pages);
451 + val->totalhigh = 0;
452 + val->freehigh = nr_free_highpages();
453 + val->mem_unit = PAGE_SIZE;
454 +
455 + return;
456 +}
457 diff -ruN linux_2_4_30/arch/mips/ar7/cmdline.c linux/arch/mips/ar7/cmdline.c
458 --- linux_2_4_30/arch/mips/ar7/cmdline.c 1970-01-01 00:00:00.000000000 +0000
459 +++ linux/arch/mips/ar7/cmdline.c 2005-06-12 08:55:20.000000000 +0000
460 @@ -0,0 +1,64 @@
461 +/*
462 + * Carsten Langgaard, carstenl@mips.com
463 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
464 + *
465 + * This program is free software; you can distribute it and/or modify it
466 + * under the terms of the GNU General Public License (Version 2) as
467 + * published by the Free Software Foundation.
468 + *
469 + * This program is distributed in the hope it will be useful, but WITHOUT
470 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
471 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
472 + * for more details.
473 + *
474 + * You should have received a copy of the GNU General Public License along
475 + * with this program; if not, write to the Free Software Foundation, Inc.,
476 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
477 + *
478 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
479 + */
480 +#include <linux/init.h>
481 +#include <linux/string.h>
482 +
483 +#include <asm/bootinfo.h>
484 +
485 +extern int prom_argc;
486 +extern int *_prom_argv;
487 +
488 +/*
489 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
490 + * This macro take care of sign extension.
491 + */
492 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
493 +
494 +char arcs_cmdline[CL_SIZE];
495 +
496 +char * __init prom_getcmdline(void)
497 +{
498 + return &(arcs_cmdline[0]);
499 +}
500 +
501 +
502 +void __init prom_init_cmdline(void)
503 +{
504 + char *cp;
505 + int actr;
506 +
507 + actr = 1; /* Always ignore argv[0] */
508 +
509 + cp = &(arcs_cmdline[0]);
510 +#ifdef CONFIG_CMDLINE_BOOL
511 + strcpy(cp, CONFIG_CMDLINE);
512 + cp += strlen(CONFIG_CMDLINE);
513 + *cp++ = ' ';
514 +#endif
515 + while(actr < prom_argc) {
516 + strcpy(cp, prom_argv(actr));
517 + cp += strlen(prom_argv(actr));
518 + *cp++ = ' ';
519 + actr++;
520 + }
521 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
522 + --cp;
523 + *cp = '\0';
524 +}
525 diff -ruN linux_2_4_30/arch/mips/ar7/init.c linux/arch/mips/ar7/init.c
526 --- linux_2_4_30/arch/mips/ar7/init.c 1970-01-01 00:00:00.000000000 +0000
527 +++ linux/arch/mips/ar7/init.c 2005-06-11 10:43:59.000000000 +0000
528 @@ -0,0 +1,127 @@
529 +/*
530 + * Carsten Langgaard, carstenl@mips.com
531 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
532 + *
533 + * This program is free software; you can distribute it and/or modify it
534 + * under the terms of the GNU General Public License (Version 2) as
535 + * published by the Free Software Foundation.
536 + *
537 + * This program is distributed in the hope it will be useful, but WITHOUT
538 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
539 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
540 + * for more details.
541 + *
542 + * You should have received a copy of the GNU General Public License along
543 + * with this program; if not, write to the Free Software Foundation, Inc.,
544 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
545 + *
546 + * PROM library initialisation code.
547 + */
548 +#include <linux/config.h>
549 +#include <linux/init.h>
550 +#include <linux/string.h>
551 +#include <linux/kernel.h>
552 +
553 +#include <asm/io.h>
554 +#include <asm/mips-boards/prom.h>
555 +#include <asm/mips-boards/generic.h>
556 +
557 +/* Environment variable */
558 +typedef struct {
559 + char *name;
560 + char *val;
561 +} t_env_var;
562 +
563 +int prom_argc;
564 +int *_prom_argv, *_prom_envp;
565 +
566 +/*
567 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
568 + * This macro take care of sign extension, if running in 64-bit mode.
569 + */
570 +#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)]))
571 +
572 +int init_debug = 0;
573 +
574 +char *prom_getenv(char *envname)
575 +{
576 + /*
577 + * Return a pointer to the given environment variable.
578 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
579 + * in the PROM structures are only 32-bit, so we need some
580 + * workarounds, if we are running in 64-bit mode.
581 + */
582 + int i, index=0;
583 +
584 + i = strlen(envname);
585 +
586 + while (prom_envp(index)) {
587 + if(strncmp(envname, prom_envp(index), i) == 0) {
588 + return(prom_envp(index+1));
589 + }
590 + index += 2;
591 + }
592 +
593 + return NULL;
594 +}
595 +
596 +static inline unsigned char str2hexnum(unsigned char c)
597 +{
598 + if (c >= '0' && c <= '9')
599 + return c - '0';
600 + if (c >= 'a' && c <= 'f')
601 + return c - 'a' + 10;
602 + return 0; /* foo */
603 +}
604 +
605 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
606 +{
607 + int i;
608 +
609 + for (i = 0; i < 6; i++) {
610 + unsigned char num;
611 +
612 + if((*str == '.') || (*str == ':'))
613 + str++;
614 + num = str2hexnum(*str++) << 4;
615 + num |= (str2hexnum(*str++));
616 + ea[i] = num;
617 + }
618 +}
619 +
620 +int get_ethernet_addr(char *ethernet_addr)
621 +{
622 + char *ethaddr_str;
623 +
624 + ethaddr_str = prom_getenv("ethaddr");
625 + if (!ethaddr_str) {
626 + printk("ethaddr not set in boot prom\n");
627 + return -1;
628 + }
629 + str2eaddr(ethernet_addr, ethaddr_str);
630 +
631 + if (init_debug > 1) {
632 + int i;
633 + printk("get_ethernet_addr: ");
634 + for (i=0; i<5; i++)
635 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
636 + printk("%02x\n", *(ethernet_addr+i));
637 + }
638 +
639 + return 0;
640 +}
641 +
642 +int __init prom_init(int argc, char **argv, char **envp)
643 +{
644 + prom_argc = argc;
645 + _prom_argv = (int *)argv;
646 + _prom_envp = (int *)envp;
647 +
648 + set_io_port_base(0);
649 +
650 + prom_printf("\nLINUX started...\n");
651 + prom_init_cmdline();
652 + prom_meminit();
653 +
654 + return 0;
655 +}
656 diff -ruN linux_2_4_30/arch/mips/ar7/irq.c linux/arch/mips/ar7/irq.c
657 --- linux_2_4_30/arch/mips/ar7/irq.c 1970-01-01 00:00:00.000000000 +0000
658 +++ linux/arch/mips/ar7/irq.c 2005-06-11 10:54:13.000000000 +0000
659 @@ -0,0 +1,669 @@
660 +/*
661 + * Nitin Dhingra, iamnd@ti.com
662 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
663 + *
664 + * ########################################################################
665 + *
666 + * This program is free software; you can distribute it and/or modify it
667 + * under the terms of the GNU General Public License (Version 2) as
668 + * published by the Free Software Foundation.
669 + *
670 + * This program is distributed in the hope it will be useful, but WITHOUT
671 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
672 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
673 + * for more details.
674 + *
675 + * You should have received a copy of the GNU General Public License along
676 + * with this program; if not, write to the Free Software Foundation, Inc.,
677 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
678 + *
679 + * ########################################################################
680 + *
681 + * Routines for generic manipulation of the interrupts found on the Texas
682 + * Instruments avalanche board
683 + *
684 + */
685 +
686 +#include <linux/config.h>
687 +#include <linux/init.h>
688 +#include <linux/sched.h>
689 +#include <linux/slab.h>
690 +#include <linux/interrupt.h>
691 +#include <linux/kernel_stat.h>
692 +#include <linux/proc_fs.h>
693 +#include <asm/irq.h>
694 +#include <asm/mips-boards/prom.h>
695 +#include <asm/ar7/ar7.h>
696 +#include <asm/ar7/avalanche_intc.h>
697 +#include <asm/gdb-stub.h>
698 +
699 +
700 +#define shutdown_avalanche_irq disable_avalanche_irq
701 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
702 +
703 +static unsigned int startup_avalanche_irq(unsigned int irq);
704 +static void end_avalanche_irq(unsigned int irq);
705 +void enable_avalanche_irq(unsigned int irq_nr);
706 +void disable_avalanche_irq(unsigned int irq_nr);
707 +
708 +static struct hw_interrupt_type avalanche_irq_type = {
709 + "TI AVALANCHE",
710 + startup_avalanche_irq,
711 + shutdown_avalanche_irq,
712 + enable_avalanche_irq,
713 + disable_avalanche_irq,
714 + mask_and_ack_avalanche_irq,
715 + end_avalanche_irq,
716 + NULL
717 +};
718 +
719 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
720 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
721 +
722 +
723 +unsigned long spurious_count = 0;
724 +
725 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
726 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
727 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
728 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
729 +
730 +extern asmlinkage void mipsIRQ(void);
731 +
732 +
733 +/*
734 + * The avalanche/MIPS interrupt line numbers are used to represent the
735 + * interrupts within the irqaction arrays. The index notation is
736 + * is as follows:
737 + *
738 + * 0-7 MIPS CPU Exceptions (HW/SW)
739 + * 8-47 Primary Interrupts (Avalanche)
740 + * 48-79 Secondary Interrupts (Avalanche)
741 + *
742 + */
743 +
744 +
745 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
746 +{
747 + NULL, NULL, NULL, NULL,
748 + NULL, NULL, NULL, NULL,
749 + NULL, NULL, NULL, NULL,
750 + NULL, NULL, NULL, NULL,
751 + NULL, NULL, NULL, NULL,
752 + NULL, NULL, NULL, NULL,
753 + NULL, NULL, NULL, NULL,
754 + NULL, NULL, NULL, NULL,
755 + NULL, NULL, NULL, NULL,
756 + NULL, NULL, NULL, NULL
757 +};
758 +
759 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
760 +{
761 + NULL, NULL, NULL, NULL,
762 + NULL, NULL, NULL, NULL,
763 + NULL, NULL, NULL, NULL,
764 + NULL, NULL, NULL, NULL,
765 + NULL, NULL, NULL, NULL,
766 + NULL, NULL, NULL, NULL,
767 + NULL, NULL, NULL, NULL,
768 + NULL, NULL, NULL, NULL
769 +};
770 +
771 +/*
772 + This remaps interrupts to exist on other channels than the default
773 + channels. essentially we can use the line # as the index for this
774 + array
775 + */
776 +
777 +
778 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
779 +unsigned long uni_secondary_interrupt = 0;
780 +
781 +static struct irqaction r4ktimer_action = {
782 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
783 +};
784 +
785 +static struct irqaction *irq_action[8] = {
786 + NULL, /* SW int 0 */
787 + NULL, /* SW int 1 */
788 + NULL, /* HW int 0 */
789 + NULL,
790 + NULL,
791 + NULL, /* HW int 3 */
792 + NULL, /* HW int 4 */
793 + &r4ktimer_action /* HW int 5 */
794 +};
795 +
796 +static void end_avalanche_irq(unsigned int irq)
797 +{
798 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
799 + enable_avalanche_irq(irq);
800 +}
801 +
802 +void disable_avalanche_irq(unsigned int irq_nr)
803 +{
804 + unsigned long flags;
805 + unsigned long chan_nr=0;
806 + unsigned long int_bit=0;
807 +
808 + if(irq_nr >= AVALANCHE_INT_END)
809 + {
810 + printk("whee, invalid irq_nr %d\n", irq_nr);
811 + panic("IRQ, you lose...");
812 + }
813 +
814 + save_and_cli(flags);
815 +
816 +
817 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
818 + {
819 + /* disable mips exception */
820 +
821 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
822 + change_c0_status(ST0_IM,int_bit);
823 + restore_flags(flags);
824 + return;
825 + }
826 +
827 + /* irq_nr represents the line number for the interrupt. We must
828 + * disable the channel number associated with that line number.
829 + */
830 +
831 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
832 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
833 + else
834 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
835 +
836 + /* disable the interrupt channel bit */
837 +
838 + /* primary interrupt #'s 0-31 */
839 +
840 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
841 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
842 +
843 + /* primary interrupt #'s 32-39 */
844 +
845 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
846 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
847 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
848 +
849 + else /* secondary interrupt #'s 0-31 */
850 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
851 +
852 + restore_flags(flags);
853 +}
854 +
855 +void enable_avalanche_irq(unsigned int irq_nr)
856 +{
857 + unsigned long flags;
858 + unsigned long chan_nr=0;
859 + unsigned long int_bit=0;
860 +
861 + if(irq_nr > AVALANCHE_INT_END) {
862 + printk("whee, invalid irq_nr %d\n", irq_nr);
863 + panic("IRQ, you lose...");
864 + }
865 +
866 + save_and_cli(flags);
867 +
868 +
869 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
870 + {
871 + /* Enable MIPS exceptions */
872 + int_bit = read_c0_status();
873 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
874 + restore_flags(flags);
875 + return;
876 + }
877 +
878 + /* irq_nr represents the line number for the interrupt. We must
879 + * disable the channel number associated with that line number.
880 + */
881 +
882 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
883 + chan_nr = AVINTNUM(irq_nr);
884 + else
885 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
886 +
887 + /* enable the interrupt channel bit */
888 +
889 + /* primary interrupt #'s 0-31 */
890 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
891 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
892 +
893 + /* primary interrupt #'s 32 throuth 39 */
894 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
895 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
896 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
897 +
898 + else /* secondary interrupt #'s 0-31 */
899 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
900 +
901 + restore_flags(flags);
902 +}
903 +
904 +static unsigned int startup_avalanche_irq(unsigned int irq)
905 +{
906 + enable_avalanche_irq(irq);
907 + return 0; /* never anything pending */
908 +}
909 +
910 +
911 +int get_irq_list(char *buf)
912 +{
913 + int i, len = 0;
914 + int num = 0;
915 + struct irqaction *action;
916 +
917 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
918 + {
919 + action = irq_action[i];
920 + if (!action)
921 + continue;
922 + len += sprintf(buf+len, "%2d: %8d %c %s",
923 + num, kstat.irqs[0][num],
924 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
925 + action->name);
926 + for (action=action->next; action; action = action->next) {
927 + len += sprintf(buf+len, ",%s %s",
928 + (action->flags & SA_INTERRUPT) ? " +" : "",
929 + action->name);
930 + }
931 + len += sprintf(buf+len, " [MIPS interrupt]\n");
932 + }
933 +
934 +
935 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
936 + {
937 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
938 + action = hw0_irq_action_primary[i];
939 + else
940 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
941 + if (!action)
942 + continue;
943 + len += sprintf(buf+len, "%2d: %8d %c %s",
944 + num, kstat.irqs[0][ LNXINTNUM(i) ],
945 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
946 + action->name);
947 +
948 + for (action=action->next; action; action = action->next)
949 + {
950 + len += sprintf(buf+len, ",%s %s",
951 + (action->flags & SA_INTERRUPT) ? " +" : "",
952 + action->name);
953 + }
954 +
955 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
956 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
957 + else
958 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
959 +
960 + }
961 +
962 + return len;
963 +}
964 +
965 +int request_irq(unsigned int irq,
966 + void (*handler)(int, void *, struct pt_regs *),
967 + unsigned long irqflags,
968 + const char * devname,
969 + void *dev_id)
970 +{
971 + struct irqaction *action;
972 +
973 + if (irq > AVALANCHE_INT_END)
974 + return -EINVAL;
975 + if (!handler)
976 + return -EINVAL;
977 +
978 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
979 + if(!action)
980 + return -ENOMEM;
981 +
982 + action->handler = handler;
983 + action->flags = irqflags;
984 + action->mask = 0;
985 + action->name = devname;
986 + irq_desc_ti[irq].action = action;
987 + action->dev_id = dev_id;
988 +
989 + action->next = 0;
990 +
991 + if(irq < MIPS_EXCEPTION_OFFSET)
992 + {
993 + irq_action[irq] = action;
994 + enable_avalanche_irq(irq);
995 + return 0;
996 + }
997 +
998 + if(irq < AVALANCHE_INT_END_PRIMARY)
999 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1000 + else
1001 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1002 +
1003 + enable_avalanche_irq(irq);
1004 +
1005 + return 0;
1006 +}
1007 +
1008 +void free_irq(unsigned int irq, void *dev_id)
1009 +{
1010 + struct irqaction *action;
1011 +
1012 + if (irq > AVALANCHE_INT_END) {
1013 + printk("Trying to free IRQ%d\n",irq);
1014 + return;
1015 + }
1016 +
1017 + if(irq < MIPS_EXCEPTION_OFFSET)
1018 + {
1019 + action = irq_action[irq];
1020 + irq_action[irq] = NULL;
1021 + irq_desc_ti[irq].action = NULL;
1022 + disable_avalanche_irq(irq);
1023 + kfree(action);
1024 + return;
1025 + }
1026 +
1027 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1028 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1029 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1030 + irq_desc_ti[irq].action = NULL;
1031 + }
1032 + else {
1033 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1034 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1035 + irq_desc_ti[irq].action = NULL;
1036 + }
1037 +
1038 + disable_avalanche_irq(irq);
1039 + kfree(action);
1040 +}
1041 +
1042 +#ifdef CONFIG_KGDB
1043 +extern void breakpoint(void);
1044 +extern int remote_debug;
1045 +#endif
1046 +
1047 +//void init_IRQ(void) __init;
1048 +void __init init_IRQ(void)
1049 +{
1050 + int i;
1051 +
1052 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1053 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1054 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1055 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1056 +
1057 + /* Disable interrupts and clear pending
1058 + */
1059 +
1060 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1061 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1062 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1063 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1064 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1065 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1066 +
1067 +
1068 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1069 + /* hack for speeding up the pacing. */
1070 + printk("the pacing pre-scalar has been set as 600.\n");
1071 + avalanche_hw0_ipaceregs->ipacep = 600;
1072 + /* Channel to line mapping, Line to Channel mapping */
1073 +
1074 + for(i = 0; i < 40; i++)
1075 + avalanche_int_set(i,i);
1076 +
1077 + /* Now safe to set the exception vector. */
1078 + set_except_vector(0, mipsIRQ);
1079 +
1080 + /* Setup the IRQ description array. These will be mapped
1081 + * as flat interrupts numbers. The mapping is as follows
1082 + *
1083 + * 0-7 MIPS CPU Exceptions (HW/SW)
1084 + * 8-46 Primary Interrupts (Avalanche)
1085 + * 47-78 Secondary Interrupts (Avalanche)
1086 + */
1087 +
1088 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1089 + {
1090 + irq_desc_ti[i].status = IRQ_DISABLED;
1091 + irq_desc_ti[i].action = 0;
1092 + irq_desc_ti[i].depth = 1;
1093 + irq_desc_ti[i].handler = &avalanche_irq_type;
1094 + }
1095 +
1096 +#ifdef CONFIG_KGDB
1097 + if (remote_debug)
1098 + {
1099 + set_debug_traps();
1100 + breakpoint();
1101 + }
1102 +#endif
1103 +}
1104 +
1105 +
1106 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1107 +{
1108 + struct irqaction *action;
1109 + int irq, cpu = smp_processor_id();
1110 + unsigned long int_line_number,status;
1111 + int i,secondary = 0;
1112 + int chan_nr=0;
1113 +
1114 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1115 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1116 +
1117 +
1118 + if(chan_nr < 32)
1119 + {
1120 + if( chan_nr != uni_secondary_interrupt)
1121 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1122 +
1123 + }
1124 +
1125 + if((chan_nr < 40) && (chan_nr > 31))
1126 + {
1127 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1128 + }
1129 +
1130 +
1131 + /* If the Priority Interrupt Index Register returns 40 then no
1132 + * interrupts are pending
1133 + */
1134 +
1135 + if(chan_nr == 40)
1136 + return;
1137 +
1138 + if(chan_nr == uni_secondary_interrupt)
1139 + {
1140 + status = avalanche_hw0_ecregs->exsr;
1141 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1142 + {
1143 + if (status & 1<<i)
1144 + {
1145 + /* clear secondary interrupt */
1146 + avalanche_hw0_ecregs->excr = 1 << i;
1147 + break;
1148 + }
1149 + }
1150 + irq = i;
1151 + secondary = 1;
1152 +
1153 + /* clear the universal secondary interrupt */
1154 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1155 +
1156 + }
1157 + else
1158 + irq = chan_nr;
1159 +
1160 + /* Suraj Add code to clear secondary interrupt */
1161 +
1162 + if(secondary)
1163 + action = hw0_irq_action_secondary[irq];
1164 + else
1165 + action = hw0_irq_action_primary[irq];
1166 +
1167 + /* if action == NULL, then we don't have a handler for the irq */
1168 +
1169 + if ( action == NULL ) {
1170 + printk("No handler for hw0 irq: %i\n", irq);
1171 + return;
1172 + }
1173 +
1174 + irq_enter(cpu,irq);
1175 + if(secondary)
1176 + {
1177 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1178 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1179 + }
1180 + else
1181 + {
1182 + kstat.irqs[0][irq + 8]++;
1183 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1184 + }
1185 +
1186 + irq_exit(cpu,irq);
1187 +
1188 + if(softirq_pending(cpu))
1189 + do_softirq();
1190 +
1191 + return;
1192 +}
1193 +
1194 +void avalanche_int_set(int channel, int line)
1195 +{
1196 + switch(channel)
1197 + {
1198 + case(0):
1199 + avalanche_hw0_chregs->cintnr0 = line;
1200 + break;
1201 + case(1):
1202 + avalanche_hw0_chregs->cintnr1 = line;
1203 + break;
1204 + case(2):
1205 + avalanche_hw0_chregs->cintnr2 = line;
1206 + break;
1207 + case(3):
1208 + avalanche_hw0_chregs->cintnr3 = line;
1209 + break;
1210 + case(4):
1211 + avalanche_hw0_chregs->cintnr4 = line;
1212 + break;
1213 + case(5):
1214 + avalanche_hw0_chregs->cintnr5 = line;
1215 + break;
1216 + case(6):
1217 + avalanche_hw0_chregs->cintnr6 = line;
1218 + break;
1219 + case(7):
1220 + avalanche_hw0_chregs->cintnr7 = line;
1221 + break;
1222 + case(8):
1223 + avalanche_hw0_chregs->cintnr8 = line;
1224 + break;
1225 + case(9):
1226 + avalanche_hw0_chregs->cintnr9 = line;
1227 + break;
1228 + case(10):
1229 + avalanche_hw0_chregs->cintnr10 = line;
1230 + break;
1231 + case(11):
1232 + avalanche_hw0_chregs->cintnr11 = line;
1233 + break;
1234 + case(12):
1235 + avalanche_hw0_chregs->cintnr12 = line;
1236 + break;
1237 + case(13):
1238 + avalanche_hw0_chregs->cintnr13 = line;
1239 + break;
1240 + case(14):
1241 + avalanche_hw0_chregs->cintnr14 = line;
1242 + break;
1243 + case(15):
1244 + avalanche_hw0_chregs->cintnr15 = line;
1245 + break;
1246 + case(16):
1247 + avalanche_hw0_chregs->cintnr16 = line;
1248 + break;
1249 + case(17):
1250 + avalanche_hw0_chregs->cintnr17 = line;
1251 + break;
1252 + case(18):
1253 + avalanche_hw0_chregs->cintnr18 = line;
1254 + break;
1255 + case(19):
1256 + avalanche_hw0_chregs->cintnr19 = line;
1257 + break;
1258 + case(20):
1259 + avalanche_hw0_chregs->cintnr20 = line;
1260 + break;
1261 + case(21):
1262 + avalanche_hw0_chregs->cintnr21 = line;
1263 + break;
1264 + case(22):
1265 + avalanche_hw0_chregs->cintnr22 = line;
1266 + break;
1267 + case(23):
1268 + avalanche_hw0_chregs->cintnr23 = line;
1269 + break;
1270 + case(24):
1271 + avalanche_hw0_chregs->cintnr24 = line;
1272 + break;
1273 + case(25):
1274 + avalanche_hw0_chregs->cintnr25 = line;
1275 + break;
1276 + case(26):
1277 + avalanche_hw0_chregs->cintnr26 = line;
1278 + break;
1279 + case(27):
1280 + avalanche_hw0_chregs->cintnr27 = line;
1281 + break;
1282 + case(28):
1283 + avalanche_hw0_chregs->cintnr28 = line;
1284 + break;
1285 + case(29):
1286 + avalanche_hw0_chregs->cintnr29 = line;
1287 + break;
1288 + case(30):
1289 + avalanche_hw0_chregs->cintnr30 = line;
1290 + break;
1291 + case(31):
1292 + avalanche_hw0_chregs->cintnr31 = line;
1293 + break;
1294 + case(32):
1295 + avalanche_hw0_chregs->cintnr32 = line;
1296 + break;
1297 + case(33):
1298 + avalanche_hw0_chregs->cintnr33 = line;
1299 + break;
1300 + case(34):
1301 + avalanche_hw0_chregs->cintnr34 = line;
1302 + break;
1303 + case(35):
1304 + avalanche_hw0_chregs->cintnr35 = line;
1305 + break;
1306 + case(36):
1307 + avalanche_hw0_chregs->cintnr36 = line;
1308 + break;
1309 + case(37):
1310 + avalanche_hw0_chregs->cintnr37 = line;
1311 + break;
1312 + case(38):
1313 + avalanche_hw0_chregs->cintnr38 = line;
1314 + break;
1315 + case(39):
1316 + avalanche_hw0_chregs->cintnr39 = line;
1317 + break;
1318 + default:
1319 + printk("Error: Unknown Avalanche interrupt channel\n");
1320 + }
1321 +
1322 + line_to_channel[line] = channel; /* Suraj check */
1323 +
1324 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1325 + uni_secondary_interrupt = line;
1326 +
1327 +}
1328 +
1329 diff -ruN linux_2_4_30/arch/mips/ar7/memory.c linux/arch/mips/ar7/memory.c
1330 --- linux_2_4_30/arch/mips/ar7/memory.c 1970-01-01 00:00:00.000000000 +0000
1331 +++ linux/arch/mips/ar7/memory.c 2005-06-11 10:43:59.000000000 +0000
1332 @@ -0,0 +1,130 @@
1333 +/*
1334 + * Carsten Langgaard, carstenl@mips.com
1335 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1336 + *
1337 + * ########################################################################
1338 + *
1339 + * This program is free software; you can distribute it and/or modify it
1340 + * under the terms of the GNU General Public License (Version 2) as
1341 + * published by the Free Software Foundation.
1342 + *
1343 + * This program is distributed in the hope it will be useful, but WITHOUT
1344 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1345 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1346 + * for more details.
1347 + *
1348 + * You should have received a copy of the GNU General Public License along
1349 + * with this program; if not, write to the Free Software Foundation, Inc.,
1350 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1351 + *
1352 + * ########################################################################
1353 + *
1354 + * PROM library functions for acquiring/using memory descriptors given to
1355 + * us from the YAMON.
1356 + *
1357 + */
1358 +#include <linux/config.h>
1359 +#include <linux/init.h>
1360 +#include <linux/mm.h>
1361 +#include <linux/bootmem.h>
1362 +
1363 +#include <asm/bootinfo.h>
1364 +#include <asm/page.h>
1365 +#include <asm/mips-boards/prom.h>
1366 +#include <asm/ar7/ar7.h>
1367 +
1368 +enum yamon_memtypes {
1369 + yamon_dontuse,
1370 + yamon_prom,
1371 + yamon_free,
1372 +};
1373 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1374 +
1375 +/* References to section boundaries */
1376 +extern char _end;
1377 +
1378 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1379 +
1380 +
1381 +struct prom_pmemblock * __init prom_getmdesc(void)
1382 +{
1383 + char *memsize_str;
1384 + unsigned int memsize;
1385 +
1386 + memsize_str = prom_getenv("memsize");
1387 + if (!memsize_str) {
1388 + memsize = 0x02000000;
1389 + } else {
1390 + memsize = simple_strtol(memsize_str, NULL, 0);
1391 + }
1392 +
1393 + memset(mdesc, 0, sizeof(mdesc));
1394 +
1395 + mdesc[0].type = yamon_dontuse;
1396 + mdesc[0].base = 0x00000000;
1397 + mdesc[0].size = AVALANCHE_SDRAM_BASE;
1398 +
1399 + mdesc[1].type = yamon_prom;
1400 + mdesc[1].base = AVALANCHE_SDRAM_BASE;
1401 + mdesc[1].size = 0x00020000;
1402 +
1403 + mdesc[2].type = yamon_free;
1404 + mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
1405 + mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
1406 +
1407 + return &mdesc[0];
1408 +}
1409 +
1410 +static int __init prom_memtype_classify (unsigned int type)
1411 +{
1412 + switch (type) {
1413 + case yamon_free:
1414 + return BOOT_MEM_RAM;
1415 + case yamon_prom:
1416 + return BOOT_MEM_ROM_DATA;
1417 + default:
1418 + return BOOT_MEM_RESERVED;
1419 + }
1420 +}
1421 +
1422 +void __init prom_meminit(void)
1423 +{
1424 + struct prom_pmemblock *p;
1425 +
1426 + p = prom_getmdesc();
1427 +
1428 + while (p->size) {
1429 + long type;
1430 + unsigned long base, size;
1431 +
1432 + type = prom_memtype_classify (p->type);
1433 + base = p->base;
1434 + size = p->size;
1435 +
1436 + add_memory_region(base, size, type);
1437 + p++;
1438 + }
1439 +}
1440 +
1441 +void __init prom_free_prom_memory (void)
1442 +{
1443 + int i;
1444 + unsigned long freed = 0;
1445 + unsigned long addr;
1446 +
1447 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1448 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1449 + continue;
1450 +
1451 + addr = boot_mem_map.map[i].addr;
1452 + while (addr < boot_mem_map.map[i].addr
1453 + + boot_mem_map.map[i].size) {
1454 + ClearPageReserved(virt_to_page(__va(addr)));
1455 + set_page_count(virt_to_page(__va(addr)), 1);
1456 + free_page((unsigned long)__va(addr));
1457 + addr += PAGE_SIZE;
1458 + freed += PAGE_SIZE;
1459 + }
1460 + }
1461 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1462 +}
1463 diff -ruN linux_2_4_30/arch/mips/ar7/mipsIRQ.S linux/arch/mips/ar7/mipsIRQ.S
1464 --- linux_2_4_30/arch/mips/ar7/mipsIRQ.S 1970-01-01 00:00:00.000000000 +0000
1465 +++ linux/arch/mips/ar7/mipsIRQ.S 2005-06-11 08:30:52.000000000 +0000
1466 @@ -0,0 +1,120 @@
1467 +/*
1468 + * Carsten Langgaard, carstenl@mips.com
1469 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1470 + *
1471 + * ########################################################################
1472 + *
1473 + * This program is free software; you can distribute it and/or modify it
1474 + * under the terms of the GNU General Public License (Version 2) as
1475 + * published by the Free Software Foundation.
1476 + *
1477 + * This program is distributed in the hope it will be useful, but WITHOUT
1478 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1479 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1480 + * for more details.
1481 + *
1482 + * You should have received a copy of the GNU General Public License along
1483 + * with this program; if not, write to the Free Software Foundation, Inc.,
1484 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1485 + *
1486 + * ########################################################################
1487 + *
1488 + * Interrupt exception dispatch code.
1489 + *
1490 + */
1491 +#include <linux/config.h>
1492 +
1493 +#include <asm/asm.h>
1494 +#include <asm/mipsregs.h>
1495 +#include <asm/regdef.h>
1496 +#include <asm/stackframe.h>
1497 +
1498 +/* A lot of complication here is taken away because:
1499 + *
1500 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1501 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1502 + * common case is one pending IRQ so optimize in that direction.
1503 + *
1504 + * 2) We need not check against bits in the status register IRQ mask, that
1505 + * would make this routine slow as hell.
1506 + *
1507 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1508 + * between like BSD spl() brain-damage.
1509 + *
1510 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1511 + * IRQs which we don't use at all and all external interrupt sources are
1512 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1513 + *
1514 + * MIPS IRQ Source
1515 + * -------- ------
1516 + * 0 Software (ignored)
1517 + * 1 Software (ignored)
1518 + * 2 Combined hardware interrupt (hw0)
1519 + * 3 Hardware (ignored)
1520 + * 4 Hardware (ignored)
1521 + * 5 Hardware (ignored)
1522 + * 6 Hardware (ignored)
1523 + * 7 R4k timer (what we use)
1524 + *
1525 + * Note: On the SEAD board thing are a little bit different.
1526 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1527 + * wired to UART1.
1528 + *
1529 + * We handle the IRQ according to _our_ priority which is:
1530 + *
1531 + * Highest ---- R4k Timer
1532 + * Lowest ---- Combined hardware interrupt
1533 + *
1534 + * then we just return, if multiple IRQs are pending then we will just take
1535 + * another exception, big deal.
1536 + */
1537 +
1538 +.text
1539 +.set noreorder
1540 +.set noat
1541 + .align 5
1542 +NESTED(mipsIRQ, PT_SIZE, sp)
1543 + SAVE_ALL
1544 + CLI
1545 + .set at
1546 +
1547 + mfc0 s0, CP0_CAUSE # get irq bits
1548 +
1549 + /* First we check for r4k counter/timer IRQ. */
1550 + andi a0, s0, CAUSEF_IP7
1551 + beq a0, zero, 1f
1552 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1553 +
1554 + /* Wheee, a timer interrupt. */
1555 + move a0, sp
1556 + jal ar7_timer_interrupt
1557 + nop
1558 +
1559 + j ret_from_irq
1560 + nop
1561 +
1562 + 1:
1563 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1564 + nop
1565 +
1566 + /* Wheee, combined hardware level zero interrupt. */
1567 + jal avalanche_hw0_irqdispatch
1568 + move a0, sp # delay slot
1569 +
1570 + j ret_from_irq
1571 + nop # delay slot
1572 +
1573 + 1:
1574 + /*
1575 + * Here by mistake? This is possible, what can happen is that by the
1576 + * time we take the exception the IRQ pin goes low, so just leave if
1577 + * this is the case.
1578 + */
1579 + move a1,s0
1580 + PRINT("Got interrupt: c0_cause = %08x\n")
1581 + mfc0 a1, CP0_EPC
1582 + PRINT("c0_epc = %08x\n")
1583 +
1584 + j ret_from_irq
1585 + nop
1586 +END(mipsIRQ)
1587 diff -ruN linux_2_4_30/arch/mips/ar7/printf.c linux/arch/mips/ar7/printf.c
1588 --- linux_2_4_30/arch/mips/ar7/printf.c 1970-01-01 00:00:00.000000000 +0000
1589 +++ linux/arch/mips/ar7/printf.c 2005-06-11 10:43:59.000000000 +0000
1590 @@ -0,0 +1,51 @@
1591 +/*
1592 + * Carsten Langgaard, carstenl@mips.com
1593 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1594 + *
1595 + * This program is free software; you can distribute it and/or modify it
1596 + * under the terms of the GNU General Public License (Version 2) as
1597 + * published by the Free Software Foundation.
1598 + *
1599 + * This program is distributed in the hope it will be useful, but WITHOUT
1600 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1601 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1602 + * for more details.
1603 + *
1604 + * You should have received a copy of the GNU General Public License along
1605 + * with this program; if not, write to the Free Software Foundation, Inc.,
1606 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1607 + *
1608 + * Putting things on the screen/serial line using Adam2 facilities.
1609 + */
1610 +
1611 +#include <linux/config.h>
1612 +#include <linux/init.h>
1613 +#include <linux/kernel.h>
1614 +#include <linux/serial_reg.h>
1615 +#include <linux/spinlock.h>
1616 +#include <asm/io.h>
1617 +#include <asm/serial.h>
1618 +#include <asm/addrspace.h>
1619 +#include <asm/ar7/ar7.h>
1620 +
1621 +static char ppbuf[1024];
1622 +
1623 +void (*prom_print_str)(unsigned int out, char *s, int len);
1624 +
1625 +void prom_printf(char *fmt, ...) __init;
1626 +void prom_printf(char *fmt, ...)
1627 +{
1628 + va_list args;
1629 + int len;
1630 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1631 +
1632 + va_start(args, fmt);
1633 + vsprintf(ppbuf, fmt, args);
1634 + len = strlen(ppbuf);
1635 +
1636 + prom_print_str(1, ppbuf, len);
1637 +
1638 + va_end(args);
1639 + return;
1640 +
1641 +}
1642 diff -ruN linux_2_4_30/arch/mips/ar7/reset.c linux/arch/mips/ar7/reset.c
1643 --- linux_2_4_30/arch/mips/ar7/reset.c 1970-01-01 00:00:00.000000000 +0000
1644 +++ linux/arch/mips/ar7/reset.c 2005-06-11 10:43:59.000000000 +0000
1645 @@ -0,0 +1,54 @@
1646 +/*
1647 + * Carsten Langgaard, carstenl@mips.com
1648 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1649 + *
1650 + * ########################################################################
1651 + *
1652 + * This program is free software; you can distribute it and/or modify it
1653 + * under the terms of the GNU General Public License (Version 2) as
1654 + * published by the Free Software Foundation.
1655 + *
1656 + * This program is distributed in the hope it will be useful, but WITHOUT
1657 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1658 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1659 + * for more details.
1660 + *
1661 + * You should have received a copy of the GNU General Public License along
1662 + * with this program; if not, write to the Free Software Foundation, Inc.,
1663 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1664 + *
1665 + * ########################################################################
1666 + *
1667 + * Reset the MIPS boards.
1668 + *
1669 + */
1670 +#include <linux/config.h>
1671 +
1672 +#include <asm/reboot.h>
1673 +#include <asm/mips-boards/generic.h>
1674 +
1675 +static void ar7_machine_restart(char *command);
1676 +static void ar7_machine_halt(void);
1677 +static void ar7_machine_power_off(void);
1678 +
1679 +static void ar7_machine_restart(char *command)
1680 +{
1681 +
1682 +}
1683 +
1684 +static void ar7_machine_halt(void)
1685 +{
1686 +
1687 +}
1688 +
1689 +static void ar7_machine_power_off(void)
1690 +{
1691 +
1692 +}
1693 +
1694 +void ar7_reboot_setup(void)
1695 +{
1696 + _machine_restart = ar7_machine_restart;
1697 + _machine_halt = ar7_machine_halt;
1698 + _machine_power_off = ar7_machine_power_off;
1699 +}
1700 diff -ruN linux_2_4_30/arch/mips/ar7/setup.c linux/arch/mips/ar7/setup.c
1701 --- linux_2_4_30/arch/mips/ar7/setup.c 1970-01-01 00:00:00.000000000 +0000
1702 +++ linux/arch/mips/ar7/setup.c 2005-06-12 08:53:26.000000000 +0000
1703 @@ -0,0 +1,150 @@
1704 +/*
1705 + * Carsten Langgaard, carstenl@mips.com
1706 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1707 + *
1708 + * This program is free software; you can distribute it and/or modify it
1709 + * under the terms of the GNU General Public License (Version 2) as
1710 + * published by the Free Software Foundation.
1711 + *
1712 + * This program is distributed in the hope it will be useful, but WITHOUT
1713 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1714 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1715 + * for more details.
1716 + *
1717 + * You should have received a copy of the GNU General Public License along
1718 + * with this program; if not, write to the Free Software Foundation, Inc.,
1719 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1720 + */
1721 +#include <linux/config.h>
1722 +#include <linux/init.h>
1723 +#include <linux/sched.h>
1724 +#include <linux/mc146818rtc.h>
1725 +#include <linux/ioport.h>
1726 +
1727 +#include <asm/cpu.h>
1728 +#include <asm/bootinfo.h>
1729 +#include <asm/irq.h>
1730 +#include <asm/mips-boards/generic.h>
1731 +#include <asm/mips-boards/prom.h>
1732 +
1733 +#include <asm/dma.h>
1734 +#include <asm/time.h>
1735 +#include <asm/traps.h>
1736 +
1737 +
1738 +#define _LINK_KSEG0_
1739 +#define LITTLE_ENDIAN
1740 +#include <asm/ar7/tnetd73xx.h>
1741 +#include <asm/ar7/tnetd73xx_misc.h>
1742 +
1743 +// Specific for ar7wrd
1744 +unsigned int tnetd73xx_vbus_freq;
1745 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
1746 +#define AFECLK_FREQ 35328000
1747 +#define REFCLK_FREQ 25000000
1748 +#define OSC3_FREQ 24000000
1749 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
1750 +
1751 +#if defined(CONFIG_AR7_MARVELL)
1752 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
1753 +#else
1754 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
1755 +#endif
1756 +
1757 +
1758 +#ifdef CONFIG_KGDB
1759 +extern void rs_kgdb_hook(int);
1760 +int remote_debug = 0;
1761 +#endif
1762 +
1763 +extern struct rtc_ops no_rtc_ops;
1764 +
1765 +extern void ar7_reboot_setup(void);
1766 +
1767 +extern void ar7_time_init(void);
1768 +extern void ar7_timer_setup(struct irqaction *irq);
1769 +
1770 +/* maybe some of this is not needed? */
1771 +static void ar7_platform_init(void)
1772 +{
1773 + //tnetd73xx_gpio_init();
1774 +
1775 + tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
1776 + //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
1777 + //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
1778 +
1779 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
1780 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
1781 +
1782 + tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
1783 +
1784 + tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
1785 +
1786 +#if defined(CONFIG_AR7WRD)
1787 + if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
1788 + tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
1789 + }
1790 +#endif
1791 +
1792 +}
1793 +
1794 +const char *get_system_type(void)
1795 +{
1796 + return "Texas Instruments AR7";
1797 +}
1798 +
1799 +void __init ar7_setup(void)
1800 +{
1801 +#ifdef CONFIG_KGDB
1802 + int rs_putDebugChar(char);
1803 + char rs_getDebugChar(void);
1804 + extern int (*generic_putDebugChar)(char);
1805 + extern char (*generic_getDebugChar)(void);
1806 +#endif
1807 + char *argptr;
1808 +
1809 +#ifdef CONFIG_SERIAL_CONSOLE
1810 + argptr = prom_getcmdline();
1811 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1812 + argptr = prom_getcmdline();
1813 + strcat(argptr, " console=ttyS0,38400");
1814 + }
1815 +#endif
1816 +
1817 +#ifdef CONFIG_KGDB
1818 + argptr = prom_getcmdline();
1819 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1820 + int line;
1821 + argptr += strlen("kgdb=ttyS");
1822 + if (*argptr != '0' && *argptr != '1')
1823 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1824 + "falling back to /dev/ttyS1\n", *argptr);
1825 + line = *argptr == '0' ? 0 : 1;
1826 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1827 + line ? 1 : 0);
1828 +
1829 + rs_kgdb_hook(line);
1830 + generic_putDebugChar = rs_putDebugChar;
1831 + generic_getDebugChar = rs_getDebugChar;
1832 +
1833 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1834 + "please connect your debugger\n", line ? 1 : 0);
1835 +
1836 + remote_debug = 1;
1837 + /* Breakpoints are in init_IRQ() */
1838 + }
1839 +#endif
1840 +
1841 + argptr = prom_getcmdline();
1842 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1843 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1844 +
1845 + rtc_ops = &no_rtc_ops;
1846 +
1847 + ar7_platform_init();
1848 +
1849 + ar7_reboot_setup();
1850 +
1851 + board_time_init = ar7_time_init;
1852 + board_timer_setup = ar7_timer_setup;
1853 +}
1854 diff -ruN linux_2_4_30/arch/mips/ar7/time.c linux/arch/mips/ar7/time.c
1855 --- linux_2_4_30/arch/mips/ar7/time.c 1970-01-01 00:00:00.000000000 +0000
1856 +++ linux/arch/mips/ar7/time.c 2005-06-11 11:53:22.000000000 +0000
1857 @@ -0,0 +1,125 @@
1858 +/*
1859 + * Carsten Langgaard, carstenl@mips.com
1860 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1861 + *
1862 + * ########################################################################
1863 + *
1864 + * This program is free software; you can distribute it and/or modify it
1865 + * under the terms of the GNU General Public License (Version 2) as
1866 + * published by the Free Software Foundation.
1867 + *
1868 + * This program is distributed in the hope it will be useful, but WITHOUT
1869 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1870 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1871 + * for more details.
1872 + *
1873 + * You should have received a copy of the GNU General Public License along
1874 + * with this program; if not, write to the Free Software Foundation, Inc.,
1875 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1876 + *
1877 + * ########################################################################
1878 + *
1879 + * Setting up the clock on the MIPS boards.
1880 + *
1881 + */
1882 +
1883 +#include <linux/types.h>
1884 +#include <linux/config.h>
1885 +#include <linux/init.h>
1886 +#include <linux/kernel_stat.h>
1887 +#include <linux/sched.h>
1888 +#include <linux/spinlock.h>
1889 +
1890 +#include <asm/mipsregs.h>
1891 +#include <asm/ptrace.h>
1892 +#include <asm/hardirq.h>
1893 +#include <asm/div64.h>
1894 +
1895 +#include <linux/interrupt.h>
1896 +#include <linux/mc146818rtc.h>
1897 +#include <linux/timex.h>
1898 +
1899 +#include <asm/mips-boards/generic.h>
1900 +#include <asm/mips-boards/prom.h>
1901 +#include <asm/ar7/ar7.h>
1902 +
1903 +extern asmlinkage void mipsIRQ(void);
1904 +
1905 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
1906 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1907 +
1908 +#define MIPS_CPU_TIMER_IRQ 7
1909 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1910 +
1911 +static inline void ack_r4ktimer(unsigned long newval)
1912 +{
1913 + write_c0_compare(newval);
1914 +}
1915 +
1916 +void ar7_timer_interrupt(struct pt_regs *regs)
1917 +{
1918 + int cpu = smp_processor_id();
1919 +
1920 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
1921 +
1922 + if (r4k_offset == 0)
1923 + goto null;
1924 +
1925 + do {
1926 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
1927 + do_timer(regs);
1928 + r4k_cur += r4k_offset;
1929 + ack_r4ktimer(r4k_cur);
1930 +
1931 + } while (((unsigned long)read_c0_count()
1932 + - r4k_cur) < 0x7fffffff);
1933 +
1934 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
1935 +
1936 + if (softirq_pending(cpu))
1937 + do_softirq();
1938 +
1939 + return;
1940 +
1941 +null:
1942 + ack_r4ktimer(0);
1943 +}
1944 +
1945 +/*
1946 + * Figure out the r4k offset, the amount to increment the compare
1947 + * register for each time tick.
1948 + */
1949 +static unsigned long __init cal_r4koff(void)
1950 +{
1951 + return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
1952 +}
1953 +
1954 +void __init ar7_time_init(void)
1955 +{
1956 + unsigned long flags;
1957 + unsigned int est_freq;
1958 +
1959 + set_except_vector(0, mipsIRQ);
1960 + write_c0_count(0);
1961 +
1962 + printk("calculating r4koff... ");
1963 + r4k_offset = cal_r4koff();
1964 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1965 +
1966 + est_freq = 2*r4k_offset*HZ;
1967 + est_freq += 5000; /* round */
1968 + est_freq -= est_freq%10000;
1969 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1970 + (est_freq%1000000)*100/1000000);
1971 +}
1972 +
1973 +void __init ar7_timer_setup(struct irqaction *irq)
1974 +{
1975 + /* we are using the cpu counter for timer interrupts */
1976 + irq->handler = no_action; /* we use our own handler */
1977 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1978 +
1979 + r4k_cur = (read_c0_count() + r4k_offset);
1980 + write_c0_compare(r4k_cur);
1981 + set_c0_status(ALLINTS);
1982 +}
1983 diff -ruN linux_2_4_30/arch/mips/ar7/tnetd73xx_misc.c linux/arch/mips/ar7/tnetd73xx_misc.c
1984 --- linux_2_4_30/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 00:00:00.000000000 +0000
1985 +++ linux/arch/mips/ar7/tnetd73xx_misc.c 2005-06-11 10:43:59.000000000 +0000
1986 @@ -0,0 +1,924 @@
1987 +/******************************************************************************
1988 + * FILE PURPOSE: TNETD73xx Misc modules API Source
1989 + ******************************************************************************
1990 + * FILE NAME: tnetd73xx_misc.c
1991 + *
1992 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
1993 + * FSER Modules API
1994 + * As per TNETD73xx specifications
1995 + *
1996 + * REVISION HISTORY:
1997 + * 27 Nov 02 - Sharath Kumar PSP TII
1998 + * 14 Feb 03 - Anant Gole PSP TII
1999 + *
2000 + * (C) Copyright 2002, Texas Instruments, Inc
2001 + *******************************************************************************/
2002 +
2003 +#define LITTLE_ENDIAN
2004 +#define _LINK_KSEG0_
2005 +
2006 +#include <linux/types.h>
2007 +#include <asm/ar7/tnetd73xx.h>
2008 +#include <asm/ar7/tnetd73xx_misc.h>
2009 +
2010 +/* TNETD73XX Revision */
2011 +u32 tnetd73xx_get_revision(void)
2012 +{
2013 + /* Read Chip revision register - This register is from GPIO module */
2014 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2015 +}
2016 +
2017 +/*****************************************************************************
2018 + * Reset Control Module
2019 + *****************************************************************************/
2020 +
2021 +
2022 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2023 +{
2024 + u32 reset_status;
2025 +
2026 + /* read current reset register */
2027 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2028 +
2029 + if (reset_ctrl == OUT_OF_RESET)
2030 + {
2031 + /* bring module out of reset */
2032 + reset_status |= (1 << reset_module);
2033 + }
2034 + else
2035 + {
2036 + /* put module in reset */
2037 + reset_status &= (~(1 << reset_module));
2038 + }
2039 +
2040 + /* write to the reset register */
2041 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2042 +}
2043 +
2044 +
2045 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2046 +{
2047 + u32 reset_status;
2048 +
2049 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2050 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2051 +}
2052 +
2053 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2054 +{
2055 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2056 +}
2057 +
2058 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2059 +
2060 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2061 +{
2062 + u32 sys_reset_status;
2063 +
2064 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2065 +
2066 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2067 +}
2068 +
2069 +
2070 +/*****************************************************************************
2071 + * Power Control Module
2072 + *****************************************************************************/
2073 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2074 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2075 +
2076 +
2077 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2078 +{
2079 + u32 power_status;
2080 +
2081 + /* read current power down control register */
2082 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2083 +
2084 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2085 + {
2086 + /* power down the module */
2087 + power_status |= (1 << power_module);
2088 + }
2089 + else
2090 + {
2091 + /* power on the module */
2092 + power_status &= (~(1 << power_module));
2093 + }
2094 +
2095 + /* write to the reset register */
2096 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2097 +}
2098 +
2099 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2100 +{
2101 + u32 power_status;
2102 +
2103 + /* read current power down control register */
2104 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2105 +
2106 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2107 +}
2108 +
2109 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2110 +{
2111 + u32 power_status;
2112 +
2113 + /* read current power down control register */
2114 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2115 +
2116 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2117 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2118 +
2119 + /* write to power down control register */
2120 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2121 +}
2122 +
2123 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2124 +{
2125 + u32 power_status;
2126 +
2127 + /* read current power down control register */
2128 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2129 +
2130 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2131 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2132 +
2133 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2134 +}
2135 +
2136 +
2137 +/*****************************************************************************
2138 + * Wakeup Control
2139 + *****************************************************************************/
2140 +
2141 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2142 +
2143 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2144 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2145 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2146 +{
2147 + u32 wakeup_status;
2148 +
2149 + /* read the wakeup control register */
2150 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2151 +
2152 + /* enable/disable */
2153 + if (wakeup_ctrl == WAKEUP_ENABLED)
2154 + {
2155 + /* enable wakeup */
2156 + wakeup_status |= wakeup_int;
2157 + }
2158 + else
2159 + {
2160 + /* disable wakeup */
2161 + wakeup_status &= (~wakeup_int);
2162 + }
2163 +
2164 + /* set polarity */
2165 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2166 + {
2167 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2168 + }
2169 + else
2170 + {
2171 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2172 + }
2173 +
2174 + /* write the wakeup control register */
2175 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2176 +}
2177 +
2178 +
2179 +/*****************************************************************************
2180 + * FSER Control
2181 + *****************************************************************************/
2182 +
2183 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2184 +{
2185 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2186 +}
2187 +
2188 +/*****************************************************************************
2189 + * Clock Control
2190 + *****************************************************************************/
2191 +
2192 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2193 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2194 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2195 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2196 +
2197 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2198 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2199 +
2200 +#define CLKC_PRE_DIVIDER 0x0000001F
2201 +#define CLKC_POST_DIVIDER 0x001F0000
2202 +
2203 +#define CLKC_PLL_STATUS 0x1
2204 +#define CLKC_PLL_FACTOR 0x0000F000
2205 +
2206 +#define BOOTCR_PLL_BYPASS (1 << 5)
2207 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2208 +
2209 +#define MIPS_PLL_SELECT 0x00030000
2210 +#define SYSTEM_PLL_SELECT 0x0000C000
2211 +#define USB_PLL_SELECT 0x000C0000
2212 +#define ADSLSS_PLL_SELECT 0x00C00000
2213 +
2214 +#define MIPS_AFECLKI_SELECT 0x00000000
2215 +#define MIPS_REFCLKI_SELECT 0x00010000
2216 +#define MIPS_XTAL3IN_SELECT 0x00020000
2217 +
2218 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2219 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2220 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2221 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2222 +
2223 +#define USB_SYSPLL_SELECT 0x00000000
2224 +#define USB_REFCLKI_SELECT 0x00040000
2225 +#define USB_XTAL3IN_SELECT 0x00080000
2226 +#define USB_MIPSPLL_SELECT 0x000C0000
2227 +
2228 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2229 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2230 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2231 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2232 +
2233 +#define SYS_MAX CLK_MHZ(150)
2234 +#define SYS_MIN CLK_MHZ(1)
2235 +
2236 +#define MIPS_SYNC_MAX SYS_MAX
2237 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2238 +#define MIPS_MIN CLK_MHZ(1)
2239 +
2240 +#define USB_MAX CLK_MHZ(100)
2241 +#define USB_MIN CLK_MHZ(1)
2242 +
2243 +#define ADSL_MAX CLK_MHZ(180)
2244 +#define ADSL_MIN CLK_MHZ(1)
2245 +
2246 +#define PLL_MUL_MAXFACTOR 15
2247 +#define MAX_DIV_VALUE 32
2248 +#define MIN_DIV_VALUE 1
2249 +
2250 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2251 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2252 +
2253 +#define DIVIDER_LOCK_TIME 10100
2254 +#define PLL_LOCK_TIME 10100 * 75
2255 +
2256 +
2257 +
2258 + /****************************************************************************
2259 + * DATA PURPOSE: PRIVATE Variables
2260 + **************************************************************************/
2261 + static u32 *clk_src[4];
2262 + static u32 mips_pll_out;
2263 + static u32 sys_pll_out;
2264 + static u32 afeclk_inp;
2265 + static u32 refclk_inp;
2266 + static u32 xtal_inp;
2267 + static u32 present_min;
2268 + static u32 present_max;
2269 +
2270 + /* Forward References */
2271 + static u32 find_gcd(u32 min, u32 max);
2272 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2273 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2274 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2275 + static void find_approx(u32 *,u32 *,u32);
2276 +
2277 + /****************************************************************************
2278 + * FUNCTION: tnetd73xx_clkc_init
2279 + ****************************************************************************
2280 + * Description: The routine initializes the internal variables depending on
2281 + * on the sources selected for different clocks.
2282 + ***************************************************************************/
2283 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2284 +{
2285 +
2286 + u32 choice;
2287 +
2288 + afeclk_inp = afeclk;
2289 + refclk_inp = refclk;
2290 + xtal_inp = xtal3in;
2291 +
2292 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2293 + switch(choice)
2294 + {
2295 + case MIPS_AFECLKI_SELECT:
2296 + clk_src[CLKC_MIPS] = &afeclk_inp;
2297 + break;
2298 +
2299 + case MIPS_REFCLKI_SELECT:
2300 + clk_src[CLKC_MIPS] = &refclk_inp;
2301 + break;
2302 +
2303 + case MIPS_XTAL3IN_SELECT:
2304 + clk_src[CLKC_MIPS] = &xtal_inp;
2305 + break;
2306 +
2307 + default :
2308 + clk_src[CLKC_MIPS] = 0;
2309 +
2310 + }
2311 +
2312 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2313 + switch(choice)
2314 + {
2315 + case SYSTEM_AFECLKI_SELECT:
2316 + clk_src[CLKC_SYS] = &afeclk_inp;
2317 + break;
2318 +
2319 + case SYSTEM_REFCLKI_SELECT:
2320 + clk_src[CLKC_SYS] = &refclk_inp;
2321 + break;
2322 +
2323 + case SYSTEM_XTAL3IN_SELECT:
2324 + clk_src[CLKC_SYS] = &xtal_inp;
2325 + break;
2326 +
2327 + case SYSTEM_MIPSPLL_SELECT:
2328 + clk_src[CLKC_SYS] = &mips_pll_out;
2329 + break;
2330 +
2331 + default :
2332 + clk_src[CLKC_SYS] = 0;
2333 +
2334 + }
2335 +
2336 +
2337 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2338 + switch(choice)
2339 + {
2340 + case ADSLSS_AFECLKI_SELECT:
2341 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2342 + break;
2343 +
2344 + case ADSLSS_REFCLKI_SELECT:
2345 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2346 + break;
2347 +
2348 + case ADSLSS_XTAL3IN_SELECT:
2349 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2350 + break;
2351 +
2352 + case ADSLSS_MIPSPLL_SELECT:
2353 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2354 + break;
2355 +
2356 + default :
2357 + clk_src[CLKC_ADSLSS] = 0;
2358 +
2359 + }
2360 +
2361 +
2362 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2363 + switch(choice)
2364 + {
2365 + case USB_SYSPLL_SELECT:
2366 + clk_src[CLKC_USB] = &sys_pll_out ;
2367 + break;
2368 +
2369 + case USB_REFCLKI_SELECT:
2370 + clk_src[CLKC_USB] = &refclk_inp;
2371 + break;
2372 +
2373 + case USB_XTAL3IN_SELECT:
2374 + clk_src[CLKC_USB] = &xtal_inp;
2375 + break;
2376 +
2377 + case USB_MIPSPLL_SELECT:
2378 + clk_src[CLKC_USB] = &mips_pll_out;
2379 + break;
2380 +
2381 + default :
2382 + clk_src[CLKC_USB] = 0;
2383 +
2384 + }
2385 +}
2386 +
2387 +
2388 +
2389 +/****************************************************************************
2390 + * FUNCTION: tnetd73xx_clkc_set_freq
2391 + ****************************************************************************
2392 + * Description: The above routine is called to set the output_frequency of the
2393 + * selected clock(using clk_id) to the required value given
2394 + * by the variable output_freq.
2395 + ***************************************************************************/
2396 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2397 +(
2398 + TNETD73XX_CLKC_ID_T clk_id,
2399 + u32 output_freq
2400 + )
2401 +{
2402 + u32 base_freq;
2403 + u32 multiplier;
2404 + u32 divider;
2405 + u32 min_prediv;
2406 + u32 max_prediv;
2407 + u32 prediv;
2408 + u32 postdiv;
2409 + u32 temp;
2410 +
2411 + /* check if PLLs are bypassed*/
2412 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2413 + {
2414 + return TNETD73XX_ERR_ERROR;
2415 + }
2416 +
2417 + /*check if the requested output_frequency is in valid range*/
2418 + switch( clk_id )
2419 + {
2420 + case CLKC_SYS:
2421 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2422 + {
2423 + return TNETD73XX_ERR_ERROR;
2424 + }
2425 + present_min = SYS_MIN;
2426 + present_max = SYS_MAX;
2427 + break;
2428 +
2429 + case CLKC_MIPS:
2430 + if((output_freq < MIPS_MIN) ||
2431 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2432 + {
2433 + return TNETD73XX_ERR_ERROR;
2434 + }
2435 + present_min = MIPS_MIN;
2436 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2437 + break;
2438 +
2439 + case CLKC_USB:
2440 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2441 + {
2442 + return TNETD73XX_ERR_ERROR;
2443 + }
2444 + present_min = USB_MIN;
2445 + present_max = USB_MAX;
2446 + break;
2447 +
2448 + case CLKC_ADSLSS:
2449 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2450 + {
2451 + return TNETD73XX_ERR_ERROR;
2452 + }
2453 + present_min = ADSL_MIN;
2454 + present_max = ADSL_MAX;
2455 + break;
2456 + }
2457 +
2458 +
2459 + base_freq = get_base_frequency(clk_id);
2460 +
2461 +
2462 + /* check for minimum base frequency value */
2463 + if( base_freq < MIN_PLL_INP_FREQ)
2464 + {
2465 + return TNETD73XX_ERR_ERROR;
2466 + }
2467 +
2468 + get_val(output_freq, base_freq, &multiplier, &divider);
2469 +
2470 + /* check multiplier range */
2471 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2472 + {
2473 + return TNETD73XX_ERR_ERROR;
2474 + }
2475 +
2476 + /* check divider value */
2477 + if( divider == 0 )
2478 + {
2479 + return TNETD73XX_ERR_ERROR;
2480 + }
2481 +
2482 + /*compute minimum and maximum predivider values */
2483 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2484 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2485 +
2486 + /*adjust the value of divider so that it not less than minimum predivider value*/
2487 + if (divider < min_prediv)
2488 + {
2489 + temp = CEIL(min_prediv, divider);
2490 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2491 + {
2492 + return TNETD73XX_ERR_ERROR ;
2493 + }
2494 + else
2495 + {
2496 + multiplier = temp * multiplier;
2497 + divider = min_prediv;
2498 + }
2499 +
2500 + }
2501 +
2502 + /* compute predivider and postdivider values */
2503 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2504 + postdiv = CEIL(divider,prediv);
2505 +
2506 + /*return fail if postdivider value falls out of range */
2507 + if(postdiv > MAX_DIV_VALUE)
2508 + {
2509 + return TNETD73XX_ERR_ERROR;
2510 + }
2511 +
2512 +
2513 + /*write predivider and postdivider values*/
2514 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2515 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2516 +
2517 + /*wait for divider output to stabilise*/
2518 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2519 +
2520 + /*write to PLL clock register*/
2521 +
2522 + if(clk_id == CLKC_SYS)
2523 + {
2524 + /* but before writing put DRAM to hold mode */
2525 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2526 + }
2527 + /*Bring PLL into div mode */
2528 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2529 +
2530 + /*compute the word to be written to PLLCR
2531 + *corresponding to multiplier value
2532 + */
2533 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2534 +
2535 + /* wait till PLL enters div mode */
2536 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2537 + /*nothing*/;
2538 +
2539 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2540 +
2541 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2542 + /*nothing*/;
2543 +
2544 +
2545 + /*wait for External pll to lock*/
2546 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2547 +
2548 + if(clk_id == CLKC_SYS)
2549 + {
2550 + /* Bring DRAM out of hold */
2551 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2552 + }
2553 +
2554 + return TNETD73XX_ERR_OK ;
2555 +}
2556 +
2557 +/****************************************************************************
2558 + * FUNCTION: tnetd73xx_clkc_get_freq
2559 + ****************************************************************************
2560 + * Description: The above routine is called to get the output_frequency of the
2561 + * selected clock( clk_id)
2562 + ***************************************************************************/
2563 +u32 tnetd73xx_clkc_get_freq
2564 +(
2565 + TNETD73XX_CLKC_ID_T clk_id
2566 + )
2567 +{
2568 +
2569 + u32 clk_ctrl_register;
2570 + u32 clk_pll_setting;
2571 + u32 clk_predivider;
2572 + u32 clk_postdivider;
2573 + u16 pll_factor;
2574 + u32 base_freq;
2575 + u32 divider;
2576 +
2577 + base_freq = get_base_frequency(clk_id);
2578 +
2579 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2580 +
2581 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2582 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2583 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2584 +
2585 + divider = clk_predivider * clk_postdivider;
2586 +
2587 +
2588 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2589 + {
2590 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2591 + }
2592 +
2593 +
2594 + else
2595 + {
2596 + /* return the current clock speed based upon the PLL setting */
2597 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2598 +
2599 + /* Get the PLL multiplication factor */
2600 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2601 +
2602 + /* Check if we're in divide mode or multiply mode */
2603 + if((clk_pll_setting & 0x1) == 0)
2604 + {
2605 + /* We're in divide mode */
2606 + if(pll_factor < 0x10)
2607 + return (CEIL(base_freq >> 1, divider));
2608 + else
2609 + return (CEIL(base_freq >> 2, divider));
2610 + }
2611 +
2612 + else /* We're in PLL mode */
2613 + {
2614 + /* See if PLLNDIV & PLLDIV are set */
2615 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2616 + {
2617 + if(clk_pll_setting & 0x1000)
2618 + {
2619 + /* clk = base_freq * k/2 */
2620 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2621 + }
2622 + else
2623 + {
2624 + /* clk = base_freq * (k-1) / 4)*/
2625 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2626 + }
2627 + }
2628 + else
2629 + {
2630 + if(pll_factor < 0x10)
2631 + {
2632 + /* clk = base_freq * k */
2633 + return(CEIL(base_freq * pll_factor, divider));
2634 + }
2635 +
2636 + else
2637 + {
2638 + /* clk = base_freq */
2639 + return(CEIL(base_freq, divider));
2640 + }
2641 + }
2642 + }
2643 + return(0); /* Should never reach here */
2644 +
2645 + }
2646 +
2647 +}
2648 +
2649 +
2650 +/* local helper functions */
2651 +
2652 +/****************************************************************************
2653 + * FUNCTION: get_base_frequency
2654 + ****************************************************************************
2655 + * Description: The above routine is called to get base frequency of the clocks.
2656 + ***************************************************************************/
2657 +
2658 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2659 +{
2660 + /* update the current MIPs PLL output value, if the required
2661 + * source is MIPS PLL
2662 + */
2663 + if ( clk_src[clk_id] == &mips_pll_out)
2664 + {
2665 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2666 + }
2667 +
2668 +
2669 + /* update the current System PLL output value, if the required
2670 + * source is system PLL
2671 + */
2672 + if ( clk_src[clk_id] == &sys_pll_out)
2673 + {
2674 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2675 + }
2676 +
2677 + return (*clk_src[clk_id]);
2678 +
2679 +}
2680 +
2681 +
2682 +
2683 +/****************************************************************************
2684 + * FUNCTION: find_gcd
2685 + ****************************************************************************
2686 + * Description: The above routine is called to find gcd of 2 numbers.
2687 + ***************************************************************************/
2688 +static u32 find_gcd
2689 +(
2690 + u32 min,
2691 + u32 max
2692 + )
2693 +{
2694 + if (max % min == 0)
2695 + {
2696 + return min;
2697 + }
2698 + else
2699 + {
2700 + return find_gcd(max % min, min);
2701 + }
2702 +}
2703 +
2704 +/****************************************************************************
2705 + * FUNCTION: compute_prediv
2706 + ****************************************************************************
2707 + * Description: The above routine is called to compute predivider value
2708 + ***************************************************************************/
2709 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2710 +{
2711 + u16 prediv;
2712 +
2713 + /* return the divider itself it it falls within the range of predivider*/
2714 + if (min <= divider && divider <= max)
2715 + {
2716 + return divider;
2717 + }
2718 +
2719 + /* find a value for prediv such that it is a factor of divider */
2720 + for (prediv = max; prediv >= min ; prediv--)
2721 + {
2722 + if ( (divider % prediv) == 0 )
2723 + {
2724 + return prediv;
2725 + }
2726 + }
2727 +
2728 + /* No such factor exists, return min as prediv */
2729 + return min;
2730 +}
2731 +
2732 +/****************************************************************************
2733 + * FUNCTION: get_val
2734 + ****************************************************************************
2735 + * Description: This routine is called to get values of divider and multiplier.
2736 + ***************************************************************************/
2737 +
2738 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2739 +{
2740 + u32 temp_mul;
2741 + u32 temp_div;
2742 + u32 gcd;
2743 + u32 min_freq;
2744 + u32 max_freq;
2745 +
2746 + /* find gcd of base_freq, output_freq */
2747 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2748 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2749 + gcd = find_gcd(min_freq , max_freq);
2750 +
2751 + if(gcd == 0)
2752 + return; /* ERROR */
2753 +
2754 + /* compute values of multiplier and divider */
2755 + temp_mul = output_freq / gcd;
2756 + temp_div = base_freq / gcd;
2757 +
2758 +
2759 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2760 + if( temp_mul > PLL_MUL_MAXFACTOR )
2761 + {
2762 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2763 + return;
2764 +
2765 + find_approx(&temp_mul,&temp_div,base_freq);
2766 + }
2767 +
2768 + *multiplier = temp_mul;
2769 + *divider = temp_div;
2770 +}
2771 +
2772 +/****************************************************************************
2773 + * FUNCTION: find_approx
2774 + ****************************************************************************
2775 + * Description: This function gets the approx value of num/denom.
2776 + ***************************************************************************/
2777 +
2778 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2779 +{
2780 + u32 num1;
2781 + u32 denom1;
2782 + u32 num2;
2783 + u32 denom2;
2784 + int32_t closest;
2785 + int32_t prev_closest;
2786 + u32 temp_num;
2787 + u32 temp_denom;
2788 + u32 normalize;
2789 + u32 gcd;
2790 + u32 output_freq;
2791 +
2792 + num1 = *num;
2793 + denom1 = *denom;
2794 +
2795 + prev_closest = 0x7fffffff; /* maximum possible value */
2796 + num2 = num1;
2797 + denom2 = denom1;
2798 +
2799 + /* start with max */
2800 + for(temp_num = 15; temp_num >=1; temp_num--)
2801 + {
2802 +
2803 + temp_denom = CEIL(temp_num * denom1, num1);
2804 + output_freq = (temp_num * base_freq) / temp_denom;
2805 +
2806 + if(temp_denom < 1)
2807 + {
2808 + break;
2809 + }
2810 + else
2811 + {
2812 + normalize = CEIL(num1,temp_num);
2813 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2814 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2815 + {
2816 + prev_closest = closest;
2817 + num2 = temp_num;
2818 + denom2 = temp_denom;
2819 + }
2820 +
2821 + }
2822 +
2823 + }
2824 +
2825 + gcd = find_gcd(num2,denom2);
2826 + num2 = num2 / gcd;
2827 + denom2 = denom2 /gcd;
2828 +
2829 + *num = num2;
2830 + *denom = denom2;
2831 +}
2832 +
2833 +
2834 +/*****************************************************************************
2835 + * GPIO Control
2836 + *****************************************************************************/
2837 +
2838 +/****************************************************************************
2839 + * FUNCTION: tnetd73xx_gpio_init
2840 + ***************************************************************************/
2841 +void tnetd73xx_gpio_init()
2842 +{
2843 + /* Bring module out of reset */
2844 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2845 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2846 +}
2847 +
2848 +/****************************************************************************
2849 + * FUNCTION: tnetd73xx_gpio_ctrl
2850 + ***************************************************************************/
2851 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2852 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2853 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2854 +{
2855 + u32 pin_status;
2856 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2857 + if (pin_mode == GPIO_PIN)
2858 + {
2859 + pin_status |= (1 << gpio_pin);
2860 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2861 +
2862 + /* Set pin direction */
2863 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2864 + if (pin_direction == GPIO_INPUT_PIN)
2865 + {
2866 + pin_status |= (1 << gpio_pin);
2867 + }
2868 + else /* GPIO_OUTPUT_PIN */
2869 + {
2870 + pin_status &= (~(1 << gpio_pin));
2871 + }
2872 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2873 + }
2874 + else /* FUNCTIONAL PIN */
2875 + {
2876 + pin_status &= (~(1 << gpio_pin));
2877 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2878 + }
2879 +
2880 +}
2881 +
2882 +/****************************************************************************
2883 + * FUNCTION: tnetd73xx_gpio_out
2884 + ***************************************************************************/
2885 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2886 +{
2887 + u32 pin_value;
2888 +
2889 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2890 + if (value == 1)
2891 + {
2892 + pin_value |= (1 << gpio_pin);
2893 + }
2894 + else
2895 + {
2896 + pin_value &= (~(1 << gpio_pin));
2897 + }
2898 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2899 +}
2900 +
2901 +/****************************************************************************
2902 + * FUNCTION: tnetd73xx_gpio_in
2903 + ***************************************************************************/
2904 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2905 +{
2906 + u32 pin_value;
2907 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2908 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2909 +}
2910 +
2911 diff -ruN linux_2_4_30/arch/mips/config-shared.in linux/arch/mips/config-shared.in
2912 --- linux_2_4_30/arch/mips/config-shared.in 2005-05-22 18:24:01.000000000 +0000
2913 +++ linux/arch/mips/config-shared.in 2005-06-12 10:34:41.000000000 +0000
2914 @@ -20,6 +20,15 @@
2915 mainmenu_option next_comment
2916 comment 'Machine selection'
2917 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2918 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2919 +if [ "$CONFIG_AR7" = "y" ]; then
2920 + choice 'Texas Instruments Reference Platform' \
2921 + "AR7DB CONFIG_AR7DB \
2922 + AR7RD CONFIG_AR7RD \
2923 + AR7WRD CONFIG_AR7WRD" AR7DB
2924 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
2925 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2926 +fi
2927 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2928 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2929 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2930 @@ -239,6 +248,11 @@
2931 define_bool CONFIG_NONCOHERENT_IO y
2932 define_bool CONFIG_PC_KEYB y
2933 fi
2934 +if [ "$CONFIG_AR7" = "y" ]; then
2935 + define_bool CONFIG_NONCOHERENT_IO y
2936 + define_bool CONFIG_SWAP_IO_SPACE y
2937 + define_bool CONFIG_AR7_PAGING y
2938 +fi
2939 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2940 define_bool CONFIG_IRQ_CPU y
2941 define_bool CONFIG_NONCOHERENT_IO y
2942 @@ -736,6 +750,7 @@
2943 mainmenu_option next_comment
2944 comment 'General setup'
2945 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2946 + "$CONFIG_AR7" = "y" -o \
2947 "$CONFIG_CASIO_E55" = "y" -o \
2948 "$CONFIG_DDB5074" = "y" -o \
2949 "$CONFIG_DDB5476" = "y" -o \
2950 @@ -797,6 +812,7 @@
2951 bool 'Networking support' CONFIG_NET
2952
2953 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2954 + "$CONFIG_AR7" = "y" -o \
2955 "$CONFIG_CASIO_E55" = "y" -o \
2956 "$CONFIG_DECSTATION" = "y" -o \
2957 "$CONFIG_IBM_WORKPAD" = "y" -o \
2958 diff -ruN linux_2_4_30/arch/mips/kernel/irq.c linux/arch/mips/kernel/irq.c
2959 --- linux_2_4_30/arch/mips/kernel/irq.c 2005-05-22 18:24:12.000000000 +0000
2960 +++ linux/arch/mips/kernel/irq.c 2005-06-11 11:02:36.000000000 +0000
2961 @@ -76,6 +76,7 @@
2962 * Generic, controller-independent functions:
2963 */
2964
2965 +#ifndef CONFIG_AR7
2966 int get_irq_list(char *buf)
2967 {
2968 int i, j;
2969 @@ -110,6 +111,7 @@
2970 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2971 return p - buf;
2972 }
2973 +#endif
2974
2975 #ifdef CONFIG_SMP
2976 int global_irq_holder = NO_PROC_ID;
2977 @@ -525,6 +527,7 @@
2978 *
2979 */
2980
2981 +#ifndef CONFIG_AR7
2982 int request_irq(unsigned int irq,
2983 void (*handler)(int, void *, struct pt_regs *),
2984 unsigned long irqflags,
2985 @@ -569,6 +572,7 @@
2986 kfree(action);
2987 return retval;
2988 }
2989 +#endif
2990
2991 /**
2992 * free_irq - free an interrupt
2993 @@ -588,6 +592,7 @@
2994 * the machine.
2995 */
2996
2997 +#ifndef CONFIG_AR7
2998 void free_irq(unsigned int irq, void *dev_id)
2999 {
3000 irq_desc_t *desc;
3001 @@ -629,6 +634,7 @@
3002 return;
3003 }
3004 }
3005 +#endif
3006
3007 /*
3008 * IRQ autodetection code..
3009 diff -ruN linux_2_4_30/arch/mips/kernel/setup.c linux/arch/mips/kernel/setup.c
3010 --- linux_2_4_30/arch/mips/kernel/setup.c 2005-05-22 18:24:12.000000000 +0000
3011 +++ linux/arch/mips/kernel/setup.c 2005-06-12 10:37:51.000000000 +0000
3012 @@ -109,6 +109,7 @@
3013 unsigned long isa_slot_offset;
3014 EXPORT_SYMBOL(isa_slot_offset);
3015
3016 +extern void avalanche_bootmem_init(void);
3017 extern void SetUpBootInfo(void);
3018 extern void load_mmu(void);
3019 extern asmlinkage void start_kernel(void);
3020 @@ -267,6 +268,9 @@
3021 #endif /* CONFIG_BLK_DEV_INITRD */
3022
3023 /* Find the highest page frame number we have available. */
3024 +#ifdef CONFIG_AR7_PAGING
3025 + avalanche_bootmem_init();
3026 +#else
3027 max_pfn = 0;
3028 first_usable_pfn = -1UL;
3029 for (i = 0; i < boot_mem_map.nr_map; i++) {
3030 @@ -376,7 +380,7 @@
3031
3032 /* Reserve the bootmap memory. */
3033 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3034 -
3035 +#endif
3036 #ifdef CONFIG_BLK_DEV_INITRD
3037 /* Board specific code should have set up initrd_start and initrd_end */
3038 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3039 @@ -494,6 +498,7 @@
3040 void hp_setup(void);
3041 void au1x00_setup(void);
3042 void frame_info_init(void);
3043 + void ar7_setup(void);
3044
3045 frame_info_init();
3046 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3047 @@ -691,6 +696,11 @@
3048 pmc_yosemite_setup();
3049 break;
3050 #endif
3051 +#ifdef CONFIG_AR7
3052 + case MACH_GROUP_UNKNOWN:
3053 + ar7_setup();
3054 + break;
3055 +#endif
3056 default:
3057 panic("Unsupported architecture");
3058 }
3059 diff -ruN linux_2_4_30/arch/mips/kernel/traps.c linux/arch/mips/kernel/traps.c
3060 --- linux_2_4_30/arch/mips/kernel/traps.c 2005-05-22 18:24:13.000000000 +0000
3061 +++ linux/arch/mips/kernel/traps.c 2005-06-12 11:07:11.000000000 +0000
3062 @@ -40,6 +40,10 @@
3063 #include <asm/uaccess.h>
3064 #include <asm/mmu_context.h>
3065
3066 +#ifdef CONFIG_AR7
3067 +#include <asm/ar7/ar7.h>
3068 +#endif
3069 +
3070 extern asmlinkage void handle_mod(void);
3071 extern asmlinkage void handle_tlbl(void);
3072 extern asmlinkage void handle_tlbs(void);
3073 @@ -869,9 +873,15 @@
3074
3075 exception_handlers[n] = handler;
3076 if (n == 0 && cpu_has_divec) {
3077 +#ifdef CONFIG_AR7
3078 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
3079 + (0x03ffffff & (handler >> 2));
3080 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
3081 +#else
3082 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3083 (0x03ffffff & (handler >> 2));
3084 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3085 +#endif
3086 }
3087 return (void *)old_handler;
3088 }
3089 @@ -920,14 +930,46 @@
3090 void __init trap_init(void)
3091 {
3092 extern char except_vec1_generic;
3093 + extern char except_vec2_generic;
3094 extern char except_vec3_generic, except_vec3_r4000;
3095 extern char except_vec_ejtag_debug;
3096 extern char except_vec4;
3097 unsigned long i;
3098
3099 +#ifdef CONFIG_AR7
3100 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3101 + extern char jump_cache_error,jump_general_exception;
3102 + extern char jump_dedicated_interrupt;
3103 + clear_c0_status(ST0_BEV);
3104 +#endif
3105 +
3106 /* Copy the generic exception handler code to it's final destination. */
3107 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3108 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3109 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3110
3111 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3112 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3113 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3114 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3115 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3116 +
3117 +#ifdef CONFIG_AR7
3118 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
3119 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
3120 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3121 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3122 +
3123 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3124 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3125 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3126 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3127 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3128 +#else
3129 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3130 +#endif
3131 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3132 +
3133 /*
3134 * Setup default vectors
3135 */
3136 @@ -951,8 +993,12 @@
3137 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3138 * interrupt processing overhead. Use it where available.
3139 */
3140 +#ifdef CONFIG_AR7
3141 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
3142 +#else
3143 if (cpu_has_divec)
3144 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3145 +#endif
3146
3147 /*
3148 * Some CPUs can enable/disable for cache parity detection, but does
3149 @@ -991,12 +1037,17 @@
3150 if (cpu_has_mcheck)
3151 set_except_vector(24, handle_mcheck);
3152
3153 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3154 +#ifdef CONFIG_AR7
3155 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3156 +#else
3157 if (cpu_has_vce)
3158 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3159 else if (cpu_has_4kex)
3160 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3161 else
3162 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3163 +#endif
3164
3165 if (current_cpu_data.cputype == CPU_R6000 ||
3166 current_cpu_data.cputype == CPU_R6000A) {
3167 @@ -1023,7 +1074,11 @@
3168 if (board_nmi_handler_setup)
3169 board_nmi_handler_setup();
3170
3171 +#ifdef CONFIG_AR7
3172 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3173 +#else
3174 flush_icache_range(KSEG0, KSEG0 + 0x400);
3175 +#endif
3176
3177 per_cpu_trap_init();
3178 }
3179 diff -ruN linux_2_4_30/arch/mips/lib/promlib.c linux/arch/mips/lib/promlib.c
3180 --- linux_2_4_30/arch/mips/lib/promlib.c 2005-05-22 18:24:14.000000000 +0000
3181 +++ linux/arch/mips/lib/promlib.c 2005-06-12 09:16:23.000000000 +0000
3182 @@ -1,3 +1,4 @@
3183 +#ifndef CONFIG_AR7
3184 #include <stdarg.h>
3185 #include <linux/kernel.h>
3186
3187 @@ -22,3 +23,4 @@
3188 }
3189 va_end(args);
3190 }
3191 +#endif
3192 diff -ruN linux_2_4_30/arch/mips/mm/init.c linux/arch/mips/mm/init.c
3193 --- linux_2_4_30/arch/mips/mm/init.c 2005-05-22 18:24:17.000000000 +0000
3194 +++ linux/arch/mips/mm/init.c 2005-06-12 10:33:49.000000000 +0000
3195 @@ -40,8 +40,10 @@
3196
3197 mmu_gather_t mmu_gathers[NR_CPUS];
3198 unsigned long highstart_pfn, highend_pfn;
3199 +#ifndef CONFIG_AR7_PAGING
3200 static unsigned long totalram_pages;
3201 static unsigned long totalhigh_pages;
3202 +#endif
3203
3204 void pgd_init(unsigned long page)
3205 {
3206 @@ -235,6 +237,7 @@
3207 #endif
3208 }
3209
3210 +#ifndef CONFIG_AR7_PAGING
3211 void __init paging_init(void)
3212 {
3213 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3214 @@ -272,6 +275,7 @@
3215
3216 free_area_init(zones_size);
3217 }
3218 +#endif
3219
3220 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3221 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3222 @@ -298,6 +302,7 @@
3223 return 0;
3224 }
3225
3226 +#ifndef CONFIG_AR7_PAGING
3227 void __init mem_init(void)
3228 {
3229 unsigned long codesize, reservedpages, datasize, initsize;
3230 @@ -359,6 +364,7 @@
3231 initsize >> 10,
3232 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3233 }
3234 +#endif
3235
3236 #ifdef CONFIG_BLK_DEV_INITRD
3237 void free_initrd_mem(unsigned long start, unsigned long end)
3238 @@ -376,6 +382,7 @@
3239 }
3240 #endif
3241
3242 +#ifndef CONFIG_AR7_PAGING
3243 extern char __init_begin, __init_end;
3244 extern void prom_free_prom_memory(void) __init;
3245
3246 @@ -383,7 +390,9 @@
3247 {
3248 unsigned long addr;
3249
3250 +#ifndef CONFIG_AR7
3251 prom_free_prom_memory ();
3252 +#endif
3253
3254 addr = (unsigned long) &__init_begin;
3255 while (addr < (unsigned long) &__init_end) {
3256 @@ -409,3 +418,4 @@
3257
3258 return;
3259 }
3260 +#endif
3261 diff -ruN linux_2_4_30/arch/mips/mm/tlb-r4k.c linux/arch/mips/mm/tlb-r4k.c
3262 --- linux_2_4_30/arch/mips/mm/tlb-r4k.c 2005-05-22 18:24:17.000000000 +0000
3263 +++ linux/arch/mips/mm/tlb-r4k.c 2005-06-12 11:07:31.000000000 +0000
3264 @@ -20,6 +20,10 @@
3265 #include <asm/pgtable.h>
3266 #include <asm/system.h>
3267
3268 +#ifdef CONFIG_AR7
3269 +#include <asm/ar7/ar7.h>
3270 +#endif
3271 +
3272 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3273
3274 /* CP0 hazard avoidance. */
3275 @@ -375,7 +379,12 @@
3276 else if (current_cpu_data.cputype == CPU_R4600)
3277 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3278 else
3279 +#ifdef CONFIG_AR7
3280 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
3281 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
3282 +#else
3283 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3284 flush_icache_range(KSEG0, KSEG0 + 0x80);
3285 +#endif
3286 }
3287 }
3288 diff -ruN linux_2_4_30/drivers/char/serial.c linux/drivers/char/serial.c
3289 --- linux_2_4_30/drivers/char/serial.c 2005-05-22 18:25:22.000000000 +0000
3290 +++ linux/drivers/char/serial.c 2005-06-11 17:39:00.000000000 +0000
3291 @@ -419,7 +419,40 @@
3292 return 0;
3293 }
3294
3295 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3296 +#if defined(CONFIG_AR7)
3297 +
3298 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3299 +{
3300 + return (inb(info->port + (offset * 4)) & 0xff);
3301 +}
3302 +
3303 +
3304 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3305 +{
3306 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3307 + return (inb(info->port + (offset * 4)) & 0xff);
3308 +#else
3309 + return (inb_p(info->port + (offset * 4)) & 0xff);
3310 +#endif
3311 +}
3312 +
3313 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3314 +{
3315 + outb(value, info->port + (offset * 4));
3316 +}
3317 +
3318 +
3319 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3320 + int value)
3321 +{
3322 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3323 + outb(value, info->port + (offset * 4));
3324 +#else
3325 + outb_p(value, info->port + (offset * 4));
3326 +#endif
3327 +}
3328 +
3329 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3330
3331 #include <asm/mips-boards/atlas.h>
3332
3333 @@ -478,8 +511,10 @@
3334 * needed for certain old 386 machines, I've left these #define's
3335 * in....
3336 */
3337 +#ifdef CONFIG_AR7
3338 #define serial_inp(info, offset) serial_in(info, offset)
3339 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3340 +#endif
3341
3342
3343 /*
3344 @@ -1728,7 +1763,15 @@
3345 /* Special case since 134 is really 134.5 */
3346 quot = (2*baud_base / 269);
3347 else if (baud)
3348 +#ifdef CONFIG_AR7
3349 + quot = get_avalanche_vbus_freq() / baud;
3350 +
3351 + if ((quot%16)>7)
3352 + quot += 8;
3353 + quot /=16;
3354 +#else
3355 quot = baud_base / baud;
3356 +#endif
3357 }
3358 /* If the quotient is zero refuse the change */
3359 if (!quot && old_termios) {
3360 @@ -5552,8 +5595,10 @@
3361 state->irq = irq_cannonicalize(state->irq);
3362 if (state->hub6)
3363 state->io_type = SERIAL_IO_HUB6;
3364 +#ifdef CONFIG_AR7
3365 if (state->port && check_region(state->port,8))
3366 continue;
3367 +#endif
3368 #ifdef CONFIG_MCA
3369 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3370 continue;
3371 @@ -6009,7 +6054,15 @@
3372 info->io_type = state->io_type;
3373 info->iomem_base = state->iomem_base;
3374 info->iomem_reg_shift = state->iomem_reg_shift;
3375 +#ifdef CONFIG_AR7
3376 + quot = get_avalanche_vbus_freq() / baud;
3377 +
3378 + if ((quot%16)>7)
3379 + quot += 8;
3380 + quot /=16;
3381 +#else
3382 quot = state->baud_base / baud;
3383 +#endif
3384 cval = cflag & (CSIZE | CSTOPB);
3385 #if defined(__powerpc__) || defined(__alpha__)
3386 cval >>= 8;
3387 diff -ruN linux_2_4_30/include/asm-mips/ar7/ar7.h linux/include/asm-mips/ar7/ar7.h
3388 --- linux_2_4_30/include/asm-mips/ar7/ar7.h 1970-01-01 00:00:00.000000000 +0000
3389 +++ linux/include/asm-mips/ar7/ar7.h 2005-06-12 11:08:12.000000000 +0000
3390 @@ -0,0 +1,137 @@
3391 +#ifndef _MIPS_AR7_H
3392 +#define _MIPS_AR7_H
3393 +
3394 +#include <linux/config.h>
3395 +#include <asm/addrspace.h>
3396 +
3397 +
3398 +#ifndef LITTLE_ENDIAN
3399 +#define LITTLE_ENDIAN
3400 +#endif
3401 +
3402 +#ifndef _LINK_KSEG0_
3403 +#define _LINK_KSEG0_
3404 +#endif
3405 +
3406 +#include <asm/ar7/tnetd73xx.h>
3407 +
3408 +#define AVALANCHE_UART0_INT 7
3409 +#define AVALANCHE_UART1_INT 8
3410 +
3411 +#define MIPS_EXCEPTION_OFFSET 8
3412 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3413 +
3414 +/*
3415 + * AR7 board SDRAM base address. This is used to setup the
3416 + * bootmem tables
3417 + */
3418 +
3419 +#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
3420 +#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
3421 +
3422 +
3423 +/*
3424 + * AR7 board vectors
3425 + */
3426 +
3427 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3428 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3429 +
3430 +
3431 +/*
3432 + * Yamon Prom print address.
3433 + */
3434 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3435 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3436 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3437 +
3438 +/*
3439 + * AR7 Reset and PSU standby register.
3440 + */
3441 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3442 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3443 +#define AVALANCHE_GORESET 0x1
3444 +#define AVALANCHE_GOSTBY 0x1
3445 +#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
3446 +
3447 +/*
3448 + * Avalanche UART register base.
3449 + */
3450 +
3451 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3452 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3453 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3454 +
3455 +/*
3456 + * AVALANCHE DMA controller base
3457 + */
3458 +
3459 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3460 +
3461 +
3462 +
3463 +/*
3464 + * GPIO register map
3465 + */
3466 +
3467 +/* to be obtained from avalanche_map.h */
3468 +#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
3469 +#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
3470 +#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
3471 +#define AVALANCHE_GPIO_PIN_COUNT 32
3472 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
3473 +
3474 +
3475 +// Let us define board specific information here.
3476 +
3477 +#if defined(CONFIG_AR7DB)
3478 +
3479 +#define AFECLK_FREQ 35328000
3480 +#define REFCLK_FREQ 25000000
3481 +#define OSC3_FREQ 24000000
3482 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3483 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
3484 +
3485 +#endif
3486 +
3487 +
3488 +#if defined(CONFIG_AR7RD)
3489 +
3490 +#define AFECLK_FREQ 35328000
3491 +#define REFCLK_FREQ 25000000
3492 +#define OSC3_FREQ 24000000
3493 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3494 +
3495 +#if defined(CONFIG_AR7_MARVELL)
3496 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3497 +#else
3498 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3499 +#endif
3500 +
3501 +#endif
3502 +
3503 +
3504 +#if defined(CONFIG_AR7WRD)
3505 +
3506 +#define AFECLK_FREQ 35328000
3507 +#define REFCLK_FREQ 25000000
3508 +#define OSC3_FREQ 24000000
3509 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3510 +
3511 +#if defined(CONFIG_AR7_MARVELL)
3512 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3513 +#else
3514 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3515 +#endif
3516 +
3517 +#endif
3518 +
3519 +extern unsigned int tnetd73xx_vbus_freq;
3520 +#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
3521 +
3522 +static inline unsigned int get_avalanche_vbus_freq(void)
3523 +{
3524 + return (tnetd73xx_vbus_freq);
3525 +}
3526 +
3527 +#endif /*_MIPS_AR7_H */
3528 diff -ruN linux_2_4_30/include/asm-mips/ar7/avalanche.h linux/include/asm-mips/ar7/avalanche.h
3529 --- linux_2_4_30/include/asm-mips/ar7/avalanche.h 1970-01-01 00:00:00.000000000 +0000
3530 +++ linux/include/asm-mips/ar7/avalanche.h 2005-06-11 07:48:48.000000000 +0000
3531 @@ -0,0 +1,183 @@
3532 +/* $Id$
3533 + *
3534 + * avalanche.h
3535 + *
3536 + * Jeff Harrell, jharrell@ti.com
3537 + * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
3538 + *
3539 + *
3540 + * ########################################################################
3541 + *
3542 + * This program is free software; you can distribute it and/or modify it
3543 + * under the terms of the GNU General Public License (Version 2) as
3544 + * published by the Free Software Foundation.
3545 + *
3546 + * This program is distributed in the hope it will be useful, but WITHOUT
3547 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3548 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3549 + * for more details.
3550 + *
3551 + * You should have received a copy of the GNU General Public License along
3552 + * with this program; if not, write to the Free Software Foundation, Inc.,
3553 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3554 + *
3555 + * ########################################################################
3556 + *
3557 + * Defines of the AVALANCHE board specific address-MAP, registers, etc.
3558 + *
3559 + */
3560 +#ifndef _MIPS_AVALANCHE_H
3561 +#define _MIPS_AVALANCHE_H
3562 +
3563 +#include <asm/addrspace.h>
3564 +
3565 +/*
3566 + * AVALANCHE board SDRAM base address. This is used to setup the
3567 + * bootmem tables
3568 + */
3569 +
3570 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
3571 +
3572 +/*
3573 + * AVALANCHE board vectors
3574 + */
3575 +
3576 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3577 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3578 +/*
3579 + * Avalanche RTC-device indirect register access.
3580 + */
3581 +
3582 +#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
3583 +#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
3584 +
3585 +/*
3586 + * Evm3 interrupt controller register base (primary)
3587 + */
3588 +
3589 +#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
3590 +
3591 +/*
3592 + * Avalanche exception controller register base (secondary)
3593 + */
3594 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
3595 +
3596 +
3597 +/*
3598 + * Avalanche Interrupt Channel Control register base
3599 + */
3600 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3601 +
3602 +
3603 +/*
3604 + * Avalanche UART register base.
3605 + */
3606 +
3607 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3608 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3609 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3610 +/*
3611 + * AVALANCHE DMA controller base
3612 + */
3613 +
3614 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3615 +
3616 +
3617 +/*
3618 + * AVALANCHE display register base.
3619 + */
3620 +
3621 +#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
3622 +#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
3623 +
3624 +
3625 +#define EVM3_ASCIIPOS0 0x1D000038
3626 +#define EVM3_ASCIIPOS1 0x1D000039
3627 +#define EVM3_ASCIIPOS2 0x1D00003A
3628 +#define EVM3_ASCIIPOS3 0x1D00003B
3629 +#define EVM3_ASCIIPOS4 0x1D00003C
3630 +#define EVM3_ASCIIPOS5 0x1D00003D
3631 +#define EVM3_ASCIIPOS6 0x1D00003E
3632 +#define EVM3_ASCIIPOS7 0x1D00003F
3633 +
3634 +/*
3635 + * Yamon Prom print address.
3636 + */
3637 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3638 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3639 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3640 +
3641 +/*
3642 + * Evm3 Reset and PSU standby register.
3643 + */
3644 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3645 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3646 +#define AVALANCHE_GORESET 0x1
3647 +#define AVALANCHE_GOSTBY 0x1
3648 +
3649 +/************************************************************************
3650 + * PERIPHERAL BUS LEDs (P-LED):
3651 +*************************************************************************/
3652 +
3653 +/************************************************************************
3654 + * P-LED Register Addresses
3655 +*************************************************************************/
3656 +
3657 +#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
3658 +
3659 +
3660 +/************************************************************************
3661 + * Register field encodings
3662 +*************************************************************************/
3663 +
3664 +/******** reg: PLED ********/
3665 +/* bits 7:0: VAL */
3666 +#define EVM3_PLED_VAL_MSK 0xff
3667 +
3668 +/* bit 0: */
3669 +#define EVM3_PLED_BIT0_SHF 0
3670 +#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
3671 +#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
3672 +
3673 +/* bit 1: */
3674 +#define EVM3_PLED_BIT1_SHF 1
3675 +#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
3676 +#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
3677 +
3678 +/* bit 2: */
3679 +#define EVM3_PLED_BIT2_SHF 2
3680 +#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
3681 +#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
3682 +
3683 +/* bit 3: */
3684 +#define EVM3_PLED_BIT3_SHF 3
3685 +#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
3686 +#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
3687 +
3688 +/* bit 4: */
3689 +#define EVM3_PLED_BIT4_SHF 4
3690 +#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
3691 +#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
3692 +
3693 +/* bit 5: */
3694 +#define EVM3_PLED_BIT5_SHF 5
3695 +#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
3696 +#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
3697 +
3698 +/* bit 6: */
3699 +#define EVM3_PLED_BIT6_SHF 6
3700 +#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
3701 +#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
3702 +
3703 +/* bit 7: */
3704 +#define EVM3_PLED_BIT7_SHF 7
3705 +#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
3706 +#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
3707 +
3708 +#endif /* !(_MIPS_AVALANCHE_H) */
3709 +
3710 +
3711 +
3712 +
3713 +
3714 +
3715 diff -ruN linux_2_4_30/include/asm-mips/ar7/avalanche_int.h linux/include/asm-mips/ar7/avalanche_int.h
3716 --- linux_2_4_30/include/asm-mips/ar7/avalanche_int.h 1970-01-01 00:00:00.000000000 +0000
3717 +++ linux/include/asm-mips/ar7/avalanche_int.h 2005-06-11 07:48:48.000000000 +0000
3718 @@ -0,0 +1,298 @@
3719 +/* $Id$
3720 + *
3721 + * avalancheint.h
3722 + *
3723 + * Jeff Harrell, jharrell@ti.com
3724 + * Copyright (C) 2000,2001 Texas Instruments , Inc.
3725 + *
3726 + * ########################################################################
3727 + *
3728 + * This program is free software; you can distribute it and/or modify it
3729 + * under the terms of the GNU General Public License (Version 2) as
3730 + * published by the Free Software Foundation.
3731 + *
3732 + * This program is distributed in the hope it will be useful, but WITHOUT
3733 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3734 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3735 + * for more details.
3736 + *
3737 + * You should have received a copy of the GNU General Public License along
3738 + * with this program; if not, write to the Free Software Foundation, Inc.,
3739 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3740 + *
3741 + * ########################################################################
3742 + *
3743 + * Defines for the AVALANCHE interrupt controller.
3744 + *
3745 + */
3746 +#ifndef _MIPS_AVALANCHEINT_H
3747 +#define _MIPS_AVALANCHEINT_H
3748 +
3749 +#include <linux/config.h>
3750 +
3751 +/* Avalanche Interrupt number */
3752 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3753 +/* Linux Interrupt number */
3754 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3755 +/* Number of IRQ supported on hw interrupt 0. */
3756 +
3757 +//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
3758 +//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
3759 +
3760 +
3761 +#define MIPS_EXCEPTION_OFFSET 8
3762 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
3763 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
3764 +
3765 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3766 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3767 +
3768 +
3769 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
3770 + + MIPS_EXCEPTION_OFFSET - 1)
3771 +
3772 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3773 +{
3774 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */
3775 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */
3776 + volatile unsigned long unused1; /* 0x08 */
3777 + volatile unsigned long unused2; /* 0x0C */
3778 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */
3779 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */
3780 + volatile unsigned long unused3; /* 0x18 */
3781 + volatile unsigned long unused4; /* 0x1C */
3782 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
3783 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
3784 + volatile unsigned long unused5; /* 0x28 */
3785 + volatile unsigned long unused6; /* 0x2C */
3786 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */
3787 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */
3788 + volatile unsigned long unused7; /* 0x38 */
3789 + volatile unsigned long unused8; /* 0x3c */
3790 + volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */
3791 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
3792 + volatile unsigned long unused9; /* 0x48 */
3793 + volatile unsigned long unused10; /* 0x4C */
3794 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */
3795 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */
3796 +};
3797 +
3798 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3799 +{
3800 + volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */
3801 + volatile unsigned long reserved; /* 0x84 */
3802 + volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */
3803 + volatile unsigned long reserved1; /* 0x8c */
3804 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */
3805 + volatile unsigned long reserved2; /* 0x94 */
3806 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
3807 +};
3808 +
3809 +struct avalanche_channel_int_number
3810 +{
3811 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */
3812 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */
3813 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */
3814 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */
3815 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */
3816 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */
3817 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */
3818 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */
3819 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */
3820 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */
3821 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */
3822 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */
3823 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */
3824 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */
3825 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */
3826 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */
3827 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */
3828 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */
3829 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */
3830 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */
3831 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */
3832 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */
3833 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */
3834 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */
3835 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */
3836 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */
3837 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */
3838 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */
3839 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */
3840 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */
3841 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */
3842 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */
3843 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */
3844 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */
3845 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */
3846 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */
3847 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */
3848 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */
3849 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */
3850 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */
3851 +};
3852 +
3853 +struct avalanche_interrupt_line_to_channel
3854 +{
3855 + unsigned long int_line0; /* Start of primary interrupts */
3856 + unsigned long int_line1;
3857 + unsigned long int_line2;
3858 + unsigned long int_line3;
3859 + unsigned long int_line4;
3860 + unsigned long int_line5;
3861 + unsigned long int_line6;
3862 + unsigned long int_line7;
3863 + unsigned long int_line8;
3864 + unsigned long int_line9;
3865 + unsigned long int_line10;
3866 + unsigned long int_line11;
3867 + unsigned long int_line12;
3868 + unsigned long int_line13;
3869 + unsigned long int_line14;
3870 + unsigned long int_line15;
3871 + unsigned long int_line16;
3872 + unsigned long int_line17;
3873 + unsigned long int_line18;
3874 + unsigned long int_line19;
3875 + unsigned long int_line20;
3876 + unsigned long int_line21;
3877 + unsigned long int_line22;
3878 + unsigned long int_line23;
3879 + unsigned long int_line24;
3880 + unsigned long int_line25;
3881 + unsigned long int_line26;
3882 + unsigned long int_line27;
3883 + unsigned long int_line28;
3884 + unsigned long int_line29;
3885 + unsigned long int_line30;
3886 + unsigned long int_line31;
3887 + unsigned long int_line32;
3888 + unsigned long int_line33;
3889 + unsigned long int_line34;
3890 + unsigned long int_line35;
3891 + unsigned long int_line36;
3892 + unsigned long int_line37;
3893 + unsigned long int_line38;
3894 + unsigned long int_line39;
3895 +};
3896 +
3897 +/* Interrupt Line #'s (Avalanche peripherals) */
3898 +
3899 +/*------------------------------*/
3900 +/* Avalanche primary interrupts */
3901 +/*------------------------------*/
3902 +#define UNIFIED_SECONDARY_INTERRUPT 0
3903 +#define AVALANCHE_EXT_INT_0 1
3904 +#define AVALANCHE_EXT_INT_1 2
3905 +#define AVALANCHE_EXT_INT_2 3
3906 +#define AVALANCHE_EXT_INT_3 4
3907 +#define AVALANCHE_TIMER_0_INT 5
3908 +#define AVALANCHE_TIMER_1_INT 6
3909 +#define AVALANCHE_UART0_INT 7
3910 +#define AVALANCHE_UART1_INT 8
3911 +#define AVALANCHE_PDMA_INT0 9
3912 +#define AVALANCHE_PDMA_INT1 10
3913 +#define AVALANCHE_HDLC_TXA 11
3914 +#define AVALANCHE_HDLC_TXB 12
3915 +#define AVALANCHE_HDLC_RXA 13
3916 +#define AVALANCHE_HDLC_RXB 14
3917 +#define AVALANCHE_ATM_SAR_TXA 15
3918 +#define AVALANCHE_ATM_SAR_TXB 16
3919 +#define AVALANCHE_ATM_SAR_RXA 17
3920 +#define AVALANCHE_ATM_SAR_RXB 18
3921 +#define AVALANCHE_MAC_TXA 19
3922 +#define AVALANCHE_MAC_RXA 20
3923 +#define AVALANCHE_DSP_SUB0 21
3924 +#define AVALANCHE_DSP_SUB1 22
3925 +#define AVALANCHE_DES_INT 23
3926 +#define AVALANCHE_USB_INT 24
3927 +#define AVALANCHE_PCI_INTA 25
3928 +#define AVALANCHE_PCI_INTB 26
3929 +#define AVALANCHE_PCI_INTC 27
3930 +/* Line #28 Reserved */
3931 +#define AVALANCHE_I2CM_INT 29
3932 +#define AVALANCHE_PDMA_INT2 30
3933 +#define AVALANCHE_PDMA_INT3 31
3934 +#define AVALANCHE_CODEC 32
3935 +#define AVALANCHE_MAC_TXB 33
3936 +#define AVALANCHE_MAC_RXB 34
3937 +/* Line #35 Reserved */
3938 +/* Line #36 Reserved */
3939 +/* Line #37 Reserved */
3940 +/* Line #38 Reserved */
3941 +/* Line #39 Reserved */
3942 +
3943 +#define DEBUG_MISSED_INTS 1
3944 +
3945 +#ifdef DEBUG_MISSED_INTS
3946 +struct debug_missed_int
3947 +{
3948 + unsigned int atm_sar_txa;
3949 + unsigned int atm_sar_txb;
3950 + unsigned int atm_sar_rxa;
3951 + unsigned int atm_sar_rxb;
3952 + unsigned int mac_txa;
3953 + unsigned int mac_rxa;
3954 + unsigned int mac_txb;
3955 + unsigned int mac_rxb;
3956 +};
3957 +#endif /* DEBUG_MISSED_INTS */
3958 +
3959 +/*-----------------------------------*/
3960 +/* Avalanche Secondary Interrupts */
3961 +/*-----------------------------------*/
3962 +#define PRIMARY_INTS 40
3963 +
3964 +#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS)
3965 +#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS)
3966 +/* Line #02 Reserved */
3967 +#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS)
3968 +#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS)
3969 +#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS)
3970 +/* Line #06 Reserved */
3971 +#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS)
3972 +#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS)
3973 +#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS)
3974 +/* Line #10-#20 Reserved */
3975 +#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS)
3976 +#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS)
3977 +#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS)
3978 +/* Line #24-#31 Reserved */
3979 +
3980 +#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT)
3981 +#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT)
3982 +#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
3983 +#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
3984 +
3985 +#ifdef JIMK_INT_CTRLR
3986 +/*-----------------------------------*/
3987 +/* Jim Kennedy's Interrupt Controller*/
3988 +/*-----------------------------------*/
3989 +
3990 +/* to clear the interrupt write the bit back to the status reg */
3991 +
3992 +#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
3993 +#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404))
3994 +#define JIMK_SAR_STATUS (1<<0)
3995 +#define JIMK_SAR_TX_A (1<<1)
3996 +#define JIMK_SAR_TX_B (1<<2)
3997 +#define JIMK_SAR_RX_A (1<<3)
3998 +#define JIMK_SAR_RX_B (1<<4)
3999 +#define JIMK_AAL2_STATUS (1<<5)
4000 +#define JIMK_UART0_INT (1<<11)
4001 +
4002 +#ifdef SEAD_USB_DEVELOPMENT
4003 +#define JIMK_USB_INT (1<<0)
4004 +#endif /* SEAD_USB_DEVELOPMENT */
4005 +
4006 +#endif /* JIMK_INT_CTRLR */
4007 +
4008 +extern void avalanche_int_set(int channel, int line);
4009 +extern void avalancheint_init(void);
4010 +
4011 +
4012 +#endif /* !(_MIPS_AVALANCHEINT_H) */
4013 +
4014 +
4015 +
4016 +
4017 diff -ruN linux_2_4_30/include/asm-mips/ar7/avalanche_intc.h linux/include/asm-mips/ar7/avalanche_intc.h
4018 --- linux_2_4_30/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 00:00:00.000000000 +0000
4019 +++ linux/include/asm-mips/ar7/avalanche_intc.h 2005-06-11 07:48:48.000000000 +0000
4020 @@ -0,0 +1,273 @@
4021 + /*
4022 + * Nitin Dhingra, iamnd@ti.com
4023 + * Copyright (C) 2000 Texas Instruments Inc.
4024 + *
4025 + *
4026 + * ########################################################################
4027 + *
4028 + * This program is free software; you can distribute it and/or modify it
4029 + * under the terms of the GNU General Public License (Version 2) as
4030 + * published by the Free Software Foundation.
4031 + *
4032 + * This program is distributed in the hope it will be useful, but WITHOUT
4033 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4034 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4035 + * for more details.
4036 + *
4037 + * You should have received a copy of the GNU General Public License along
4038 + * with this program; if not, write to the Free Software Foundation, Inc.,
4039 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4040 + *
4041 + * ########################################################################
4042 + *
4043 + * Defines of the Sead board specific address-MAP, registers, etc.
4044 + *
4045 + */
4046 +#ifndef _AVALANCHE_INTC_H
4047 +#define _AVALANCHE_INTC_H
4048 +
4049 +#define MIPS_EXCEPTION_OFFSET 8
4050 +
4051 +/******************************************************************************
4052 + Avalanche Interrupt number
4053 +******************************************************************************/
4054 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
4055 +
4056 +/*******************************************************************************
4057 +*Linux Interrupt number
4058 +*******************************************************************************/
4059 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
4060 +
4061 +
4062 +
4063 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
4064 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
4065 +
4066 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
4067 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
4068 +
4069 +
4070 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
4071 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
4072 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
4073 +
4074 +
4075 +/*
4076 + * Avalanche interrupt controller register base (primary)
4077 + */
4078 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
4079 +
4080 +/******************************************************************************
4081 + * Avalanche exception controller register base (secondary)
4082 + ******************************************************************************/
4083 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
4084 +
4085 +
4086 +/******************************************************************************
4087 + * Avalanche Interrupt pacing register base (secondary)
4088 + ******************************************************************************/
4089 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
4090 +
4091 +
4092 +
4093 +/******************************************************************************
4094 + * Avalanche Interrupt Channel Control register base
4095 + *****************************************************************************/
4096 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
4097 +
4098 +
4099 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
4100 +{
4101 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
4102 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
4103 + volatile unsigned long unused1; /*0x08 */
4104 + volatile unsigned long unused2; /*0x0C */
4105 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
4106 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
4107 + volatile unsigned long unused3; /*0x18 */
4108 + volatile unsigned long unused4; /*0x1C */
4109 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
4110 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
4111 + volatile unsigned long unused5; /*0x28 */
4112 + volatile unsigned long unused6; /*0x2C */
4113 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
4114 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
4115 + volatile unsigned long unused7; /* 0x38 */
4116 + volatile unsigned long unused8; /* 0x3c */
4117 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
4118 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
4119 + volatile unsigned long unused9; /* 0x48 */
4120 + volatile unsigned long unused10; /* 0x4C */
4121 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
4122 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
4123 + volatile unsigned long unused11; /* 0x58 */
4124 + volatile unsigned long unused12; /*0x5C */
4125 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
4126 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
4127 +};
4128 +
4129 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
4130 +{
4131 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
4132 + volatile unsigned long reserved; /*0x84 */
4133 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
4134 + volatile unsigned long reserved1; /*0x8c */
4135 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
4136 + volatile unsigned long reserved2; /*0x94 */
4137 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
4138 +};
4139 +struct avalanche_ipace_regs
4140 +{
4141 +
4142 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
4143 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
4144 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
4145 +};
4146 +struct avalanche_channel_int_number
4147 +{
4148 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
4149 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
4150 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
4151 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
4152 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
4153 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
4154 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
4155 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
4156 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
4157 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
4158 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
4159 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
4160 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
4161 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
4162 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
4163 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
4164 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
4165 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
4166 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
4167 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
4168 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
4169 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
4170 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
4171 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
4172 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
4173 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
4174 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
4175 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
4176 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
4177 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
4178 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
4179 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
4180 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
4181 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
4182 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
4183 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
4184 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
4185 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
4186 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
4187 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
4188 +};
4189 +
4190 +struct avalanche_interrupt_line_to_channel
4191 +{
4192 + unsigned long int_line0; /* Start of primary interrupts */
4193 + unsigned long int_line1;
4194 + unsigned long int_line2;
4195 + unsigned long int_line3;
4196 + unsigned long int_line4;
4197 + unsigned long int_line5;
4198 + unsigned long int_line6;
4199 + unsigned long int_line7;
4200 + unsigned long int_line8;
4201 + unsigned long int_line9;
4202 + unsigned long int_line10;
4203 + unsigned long int_line11;
4204 + unsigned long int_line12;
4205 + unsigned long int_line13;
4206 + unsigned long int_line14;
4207 + unsigned long int_line15;
4208 + unsigned long int_line16;
4209 + unsigned long int_line17;
4210 + unsigned long int_line18;
4211 + unsigned long int_line19;
4212 + unsigned long int_line20;
4213 + unsigned long int_line21;
4214 + unsigned long int_line22;
4215 + unsigned long int_line23;
4216 + unsigned long int_line24;
4217 + unsigned long int_line25;
4218 + unsigned long int_line26;
4219 + unsigned long int_line27;
4220 + unsigned long int_line28;
4221 + unsigned long int_line29;
4222 + unsigned long int_line30;
4223 + unsigned long int_line31;
4224 + unsigned long int_line32;
4225 + unsigned long int_line33;
4226 + unsigned long int_line34;
4227 + unsigned long int_line35;
4228 + unsigned long int_line36;
4229 + unsigned long int_line37;
4230 + unsigned long int_line38;
4231 + unsigned long int_line39;
4232 +};
4233 +
4234 +
4235 +/* Interrupt Line #'s (Sangam peripherals) */
4236 +
4237 +/*------------------------------*/
4238 +/* Sangam primary interrupts */
4239 +/*------------------------------*/
4240 +
4241 +#define UNIFIED_SECONDARY_INTERRUPT 0
4242 +#define AVALANCHE_EXT_INT_0 1
4243 +#define AVALANCHE_EXT_INT_1 2
4244 +/* Line #3 Reserved */
4245 +/* Line #4 Reserved */
4246 +#define AVALANCHE_TIMER_0_INT 5
4247 +#define AVALANCHE_TIMER_1_INT 6
4248 +#define AVALANCHE_UART0_INT 7
4249 +#define AVALANCHE_UART1_INT 8
4250 +#define AVALANCHE_PDMA_INT0 9
4251 +#define AVALANCHE_PDMA_INT1 10
4252 +/* Line #11 Reserved */
4253 +/* Line #12 Reserved */
4254 +/* Line #13 Reserved */
4255 +/* Line #14 Reserved */
4256 +#define AVALANCHE_ATM_SAR_INT 15
4257 +/* Line #16 Reserved */
4258 +/* Line #17 Reserved */
4259 +/* Line #18 Reserved */
4260 +#define AVALANCHE_MAC0_INT 19
4261 +/* Line #20 Reserved */
4262 +#define AVALANCHE_VLYNQ0_INT 21
4263 +#define AVALANCHE_CODEC_WAKE_INT 22
4264 +/* Line #23 Reserved */
4265 +#define AVALANCHE_USB_INT 24
4266 +#define AVALANCHE_VLYNQ1_INT 25
4267 +/* Line #26 Reserved */
4268 +/* Line #27 Reserved */
4269 +#define AVALANCHE_MAC1_INT 28
4270 +#define AVALANCHE_I2CM_INT 29
4271 +#define AVALANCHE_PDMA_INT2 30
4272 +#define AVALANCHE_PDMA_INT3 31
4273 +/* Line #32 Reserved */
4274 +/* Line #33 Reserved */
4275 +/* Line #34 Reserved */
4276 +/* Line #35 Reserved */
4277 +/* Line #36 Reserved */
4278 +#define AVALANCHE_VDMA_VT_RX_INT 37
4279 +#define AVALANCHE_VDMA_VT_TX_INT 38
4280 +#define AVALANCHE_ADSLSS_INT 39
4281 +
4282 +/*-----------------------------------*/
4283 +/* Sangam Secondary Interrupts */
4284 +/*-----------------------------------*/
4285 +#define PRIMARY_INTS 40
4286 +
4287 +#define EMIF_INT (7 + PRIMARY_INTS)
4288 +
4289 +
4290 +extern void avalanche_int_set(int channel, int line);
4291 +
4292 +
4293 +#endif /* _AVALANCHE_INTC_H */
4294 diff -ruN linux_2_4_30/include/asm-mips/ar7/avalanche_prom.h linux/include/asm-mips/ar7/avalanche_prom.h
4295 --- linux_2_4_30/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 00:00:00.000000000 +0000
4296 +++ linux/include/asm-mips/ar7/avalanche_prom.h 2005-06-11 07:48:48.000000000 +0000
4297 @@ -0,0 +1,54 @@
4298 +/* $Id$
4299 + *
4300 + * prom.h
4301 + *
4302 + * Carsten Langgaard, carstenl@mips.com
4303 + * Copyright (C) 1999 MIPS Technologies, Inc.
4304 + *
4305 + * ########################################################################
4306 + *
4307 + * This program is free software; you can distribute it and/or modify it
4308 + * under the terms of the GNU General Public License (Version 2) as
4309 + * published by the Free Software Foundation.
4310 + *
4311 + * This program is distributed in the hope it will be useful, but WITHOUT
4312 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4313 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4314 + * for more details.
4315 + *
4316 + * You should have received a copy of the GNU General Public License along
4317 + * with this program; if not, write to the Free Software Foundation, Inc.,
4318 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4319 + *
4320 + * ########################################################################
4321 + *
4322 + * Sead bootprom interface for the Linux kernel.
4323 + *
4324 + */
4325 +
4326 +#ifndef _MIPS_PROM_H
4327 +#define _MIPS_PROM_H
4328 +
4329 +extern char *prom_getcmdline(void);
4330 +extern char *prom_getenv(char *name);
4331 +extern void setup_prom_printf(void);
4332 +extern void prom_printf(char *fmt, ...);
4333 +extern void prom_init_cmdline(void);
4334 +extern void prom_meminit(void);
4335 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
4336 +extern void prom_free_prom_memory (void);
4337 +extern void sead_display_message(const char *str);
4338 +extern void sead_display_word(unsigned int num);
4339 +extern int get_ethernet_addr(char *ethernet_addr);
4340 +
4341 +/* Memory descriptor management. */
4342 +#define PROM_MAX_PMEMBLOCKS 32
4343 +struct prom_pmemblock {
4344 + unsigned long base; /* Within KSEG0. */
4345 + unsigned int size; /* In bytes. */
4346 + unsigned int type; /* free or prom memory */
4347 +};
4348 +
4349 +
4350 +#endif /* !(_MIPS_PROM_H) */
4351 +
4352 diff -ruN linux_2_4_30/include/asm-mips/ar7/avalanche_regs.h linux/include/asm-mips/ar7/avalanche_regs.h
4353 --- linux_2_4_30/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 00:00:00.000000000 +0000
4354 +++ linux/include/asm-mips/ar7/avalanche_regs.h 2005-06-11 07:48:48.000000000 +0000
4355 @@ -0,0 +1,567 @@
4356 +/*
4357 + * $Id$
4358 + * Avalanche Register Descriptions
4359 + *
4360 + * Jeff Harrell, jharrell@ti.com
4361 + * 2000 (c) Texas Instruments Inc.
4362 + */
4363 +
4364 +#ifndef __AVALANCHE_REGS_H
4365 +#define __AVALANCHE_REGS_H
4366 +
4367 +#include <asm/addrspace.h>
4368 +#include <linux/config.h>
4369 +
4370 +/*----------------------------------------*/
4371 +/* Base offsets within the Avalanche ASIC */
4372 +/*----------------------------------------*/
4373 +
4374 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4375 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4376 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4377 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4378 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4379 +#define DES_BASE (KSEG1ADDR(0x08600000))
4380 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4381 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4382 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4383 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4384 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4385 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4386 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4387 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4388 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4389 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4390 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4391 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4392 +#define USB_BASE (KSEG1ADDR(0x08611200))
4393 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4394 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4395 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4396 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4397 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4398 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4399 +
4400 +/*---------------------------------*/
4401 +/* Device ID, chip version number */
4402 +/*---------------------------------*/
4403 +
4404 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4405 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4406 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4407 +
4408 +/*----------------------------------*/
4409 +/* Reset Control VW changed to ptrs */
4410 +/*----------------------------------*/
4411 +
4412 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4413 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4414 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4415 +
4416 +/* reset control bits */
4417 +
4418 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4419 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4420 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4421 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4422 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4423 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4424 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4425 +/*
4426 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4427 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4428 + interface pins are inputs and must be reconfigured so as not to lose the
4429 + serial console interface
4430 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4431 +*/
4432 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4433 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4434 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4435 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4436 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4437 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4438 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4439 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4440 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4441 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4442 +
4443 +/*----------------------*/
4444 +/* Physical interfaces */
4445 +/*----------------------*/
4446 +
4447 +/* Phy loopback */
4448 +#define PHY_LOOPBACK 1
4449 +
4450 +
4451 +/* Phy 0 */
4452 +#define PHY0BASE (PHY_BASE)
4453 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4454 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4455 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4456 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4457 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4458 +
4459 +
4460 +/* Phy 1 */
4461 +
4462 +#define PHY1BASE (PHY_BASE + 0x100000)
4463 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4464 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4465 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4466 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4467 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4468 +
4469 +/* Phy 2 */
4470 +
4471 +#define PHY2BASE (PHY_BASE + 0x200000)
4472 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4473 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4474 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4475 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4476 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4477 +
4478 +/*-------------------*/
4479 +/* Avalanche ATM SAR */
4480 +/*-------------------*/
4481 +
4482 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4483 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4484 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4485 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4486 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4487 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4488 +
4489 +/* Transmit completion ring registers */
4490 +
4491 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4492 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4493 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4494 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4495 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4496 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4497 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4498 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4499 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4500 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4501 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4502 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4503 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4504 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4505 +
4506 +/* Transmit Queue Packet registers */
4507 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4508 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4509 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4510 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4511 +/* Receive completion ring registers */
4512 +
4513 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4514 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4515 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4516 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4517 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4518 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4519 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4520 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4521 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4522 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4523 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4524 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4525 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4526 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4527 +
4528 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4529 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4530 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4531 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4532 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4533 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4534 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4535 +
4536 +
4537 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4538 +
4539 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4540 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4541 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4542 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4543 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4544 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4545 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4546 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4547 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4548 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4549 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4550 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4551 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4552 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4553 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4554 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4555 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4556 +
4557 +
4558 +/*
4559 +
4560 +#define OAM_CPID_ADD 0xa30104e0
4561 +
4562 +#define OAM_LLID_ADD 0xa30104f0
4563 +
4564 +#define OAM_LLID_VAL 0xffffffff
4565 +
4566 +#define OAM_CORR_TAG 0xa3010500
4567 +
4568 +#define OAM_FAR_COUNT_ADD 0xa3010520
4569 +
4570 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4571 +
4572 +#define OAM_CONFIG_REG_ADD 0xa3000018
4573 +*/
4574 +
4575 +
4576 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4577 +
4578 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4579 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4580 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4581 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4582 +
4583 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4584 +
4585 +
4586 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4587 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4588 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4589 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4590 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4591 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4592 +
4593 +/*------------------------------------------*/
4594 +/* DSL Interface */
4595 +/*------------------------------------------*/
4596 +
4597 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4598 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4599 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4600 +
4601 +/* Fast */
4602 +
4603 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4604 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4605 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4606 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4607 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4608 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4609 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4610 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4611 +
4612 +/* Interleaved */
4613 +
4614 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4615 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4616 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4617 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4618 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4619 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4620 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4621 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4622 +
4623 +/*------------------------------------------*/
4624 +/* Broadband I/F */
4625 +/*------------------------------------------*/
4626 +
4627 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4628 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4629 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4630 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4631 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4632 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4633 +
4634 +#define AVBBIF_DISABLED 0x0
4635 +#define AVBBIF_LBT4040_INT 0x1
4636 +#define AVBBIF_XBUS 0x2
4637 +#define AVBBIF_LBT4040_EXT 0x4
4638 +
4639 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4640 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4641 +#define AVBBIF_TRANS_MASK 0xff000000
4642 +/*------------------------------------------*/
4643 +/* GPIO I/F */
4644 +/*------------------------------------------*/
4645 +
4646 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4647 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4648 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4649 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4650 +
4651 +#define GPIO_0 (1<<21)
4652 +#define GPIO_1 (1<<22)
4653 +#define GPIO_2 (1<<23)
4654 +#define GPIO_3 (1<<24)
4655 +#define EINT_1 (1<<18)
4656 +
4657 +/*
4658 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4659 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4660 + interface pins are inputs and must be reconfigured so as not to lose the
4661 + serial console interface
4662 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4663 +*/
4664 +
4665 +/*------------------------------------------*/
4666 +/* CLK_CTRL */
4667 +/*------------------------------------------*/
4668 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4669 +
4670 +#define PCLK_0_HALF_VBUS (0<<16)
4671 +#define PCLK_EQ_INPUT (1<<16)
4672 +#define BBIF_CLK_HALF_VBUS (0<<17)
4673 +#define BBIF_CLK_EQ_VBUS (1<<17)
4674 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4675 +#define DSP_MODCLK_DSPCLKI (0<<20)
4676 +#define DSP_MODCLK_REFCLKI (1<<20)
4677 +#define USB_CLK_EQ_USBCLKI (0<<21)
4678 +#define USB_CLK_EQ_REFCLKI (1<<21)
4679 +
4680 +/*------------------------------------------*/
4681 +/* PCI Control Registers */
4682 +/*------------------------------------------*/
4683 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4684 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4685 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4686 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4687 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4688 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4689 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4690 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4691 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4692 +#define PCIC_CONTROL_IO_MASK (1<<8)
4693 +/* PCIC_CONTROL_RESERVED (1<<9) */
4694 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4695 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4696 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4697 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4698 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4699 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4700 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4701 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4702 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4703 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4704 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4705 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4706 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4707 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4708 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4709 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4710 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4711 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4712 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4713 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4714 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4715 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4716 +#define PCIC_INT_CLEAR_PM (1<<0)
4717 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4718 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4719 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4720 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4721 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4722 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4723 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4724 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4725 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4726 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4727 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4728 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4729 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4730 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4731 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4732 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4733 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4734 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4735 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4736 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4737 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4738 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4739 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4740 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4741 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4742 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4743 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4744 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4745 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4746 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4747 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4748 +#define PCIC_INT_EN_PCI_PM (1<<0)
4749 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4750 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4751 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4752 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4753 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4754 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4755 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4756 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4757 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4758 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4759 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
4760 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
4761 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
4762 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
4763 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4764 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
4765 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
4766 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
4767 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
4768 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4769 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
4770 +/* PCIC_PM_CTL_RESERVED (1<<2) */
4771 +/* PCIC_PM_CTL_RESERVED (1<<3) */
4772 +/* PCIC_PM_CTL_RESERVED (1<<4) */
4773 +/* PCIC_PM_CTL_RESERVED (1<<5) */
4774 +/* PCIC_PM_CTL_RESERVED (1<<6) */
4775 +/* PCIC_PM_CTL_RESERVED (1<<7) */
4776 +/* PCIC_PM_CTL_RESERVED (1<<8) */
4777 +/* PCIC_PM_CTL_RESERVED (1<<9) */
4778 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
4779 +#define PCIC_PM_CTL_PMEIN (1<<11)
4780 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4781 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4782 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4783 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4784 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4785 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4786 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4787 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4788 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4789 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4790 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4791 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4792 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4793 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4794 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4795 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4796 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4797 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4798 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4799 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4800 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4801 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4802 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4803 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4804 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4805 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4806 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4807 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4808 +
4809 +/*------------------------------------------*/
4810 +/* IIC_INTERFACE */
4811 +/*------------------------------------------*/
4812 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
4813 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
4814 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
4815 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
4816 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
4817 +
4818 +#define I2CWRITE 0x200
4819 +#define I2CREAD 0x300
4820 +#define I2C_END_BURST 0x400
4821 +
4822 +/* read bits */
4823 +#define I2C_READ_ERROR 0x8000
4824 +#define I2C_READ_COMPLETE 0x4000
4825 +#define I2C_READ_BUSY 0x2000
4826 +
4827 +/* device types */
4828 +#define I2C_IO_EXPANDER 0x2
4829 +#define I2C_RTC 0xd
4830 +
4831 +/* device Addresses on I2C bus (EVM3) */
4832 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
4833 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
4834 +#define EVM3_RTC_I2C_ADDR 0x0
4835 +
4836 +/*------------------------------------------*/
4837 +/* Ethernet MAC register offset definitions */
4838 +/*------------------------------------------*/
4839 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
4840 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
4841 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
4842 +
4843 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4844 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
4845 +
4846 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
4847 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
4848 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
4849 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
4850 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
4851 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
4852 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
4853 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
4854 +
4855 +
4856 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
4857 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
4858 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
4859 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
4860 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
4861 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
4862 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
4863 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
4864 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
4865 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
4866 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
4867 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
4868 +
4869 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
4870 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
4871 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
4872 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
4873 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
4874 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
4875 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
4876 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
4877 +
4878 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
4879 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
4880 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
4881 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
4882 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
4883 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
4884 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
4885 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
4886 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
4887 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
4888 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
4889 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
4890 +
4891 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
4892 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
4893 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
4894 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
4895 +
4896 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
4897 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
4898 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
4899 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
4900 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
4901 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
4902 +
4903 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4904 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
4905 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
4906 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
4907 +
4908 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
4909 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4910 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
4911 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
4912 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
4913 +
4914 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
4915 +
4916 +#endif
4917 +
4918 +
4919 +
4920 +
4921 +
4922 +
4923 diff -ruN linux_2_4_30/include/asm-mips/ar7/tnetd73xx.h linux/include/asm-mips/ar7/tnetd73xx.h
4924 --- linux_2_4_30/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 00:00:00.000000000 +0000
4925 +++ linux/include/asm-mips/ar7/tnetd73xx.h 2005-06-12 10:28:19.000000000 +0000
4926 @@ -0,0 +1,340 @@
4927 +/******************************************************************************
4928 + * FILE PURPOSE: TNETD73xx Common Header File
4929 + ******************************************************************************
4930 + * FILE NAME: tnetd73xx.h
4931 + *
4932 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
4933 + *
4934 + * REVISION HISTORY:
4935 + * 27 Nov 02 - PSP TII
4936 + *
4937 + * (C) Copyright 2002, Texas Instruments, Inc
4938 + *******************************************************************************/
4939 +
4940 +/*
4941 + *
4942 + *
4943 + * These are const, typedef, and api definitions for tnetd73xx.
4944 + *
4945 + * NOTES:
4946 + * 1. This file may be included into both C and Assembly files.
4947 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
4948 + * avoid C data types (typedefs) below;
4949 + * - for .c files, you don't have to do anything special.
4950 + *
4951 + * 2. This file has a number of sections for each SOC subsystem. When adding
4952 + * a new constant, find the subsystem you are working on and follow the
4953 + * name pattern. If you are adding another typedef for your interface, please,
4954 + * place it with other typedefs and function prototypes.
4955 + *
4956 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
4957 + * cluttering. Include such items directly into the module's .c file or have a
4958 + * local .h file to pass data between smaller modules. This file defines only
4959 + * shared items.
4960 + */
4961 +
4962 +#ifndef __TNETD73XX_H__
4963 +#define __TNETD73XX_H__
4964 +
4965 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
4966 +
4967 +#include <linux/types.h>
4968 +
4969 +extern unsigned int tnetd73xx_mips_freq;
4970 +extern unsigned int tnetd73xx_vbus_freq;
4971 +
4972 +#include "tnetd73xx_err.h"
4973 +
4974 +#endif /* _ASMLANGUAGE */
4975 +
4976 +
4977 +/*******************************************************************************************
4978 +* Emerald core specific
4979 +******************************************************************************************** */
4980 +
4981 +#ifdef BIG_ENDIAN
4982 +#elif defined(LITTLE_ENDIAN)
4983 +#else
4984 +#error Need to define endianism
4985 +#endif
4986 +
4987 +#ifndef KSEG_MSK
4988 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
4989 +#endif
4990 +
4991 +#ifndef KSEG_INV_MASK
4992 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
4993 +#endif
4994 +
4995 +#ifndef KSEG0_BASE
4996 +#define KSEG0_BASE 0x80000000
4997 +#endif
4998 +
4999 +#ifndef KSEG1_BASE
5000 +#define KSEG1_BASE 0xA0000000
5001 +#endif
5002 +
5003 +#ifndef KSEG0
5004 +#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5005 +#endif
5006 +
5007 +#ifndef KSEG1
5008 +#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5009 +#endif
5010 +
5011 +#ifndef KUSEG
5012 +#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
5013 +#endif
5014 +
5015 +#ifndef PHYS_ADDR
5016 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5017 +#endif
5018 +
5019 +#ifndef PHYS_TO_K0
5020 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5021 +#endif
5022 +
5023 +#ifndef PHYS_TO_K1
5024 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5025 +#endif
5026 +
5027 +#ifndef REG8_ADDR
5028 +#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
5029 +#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
5030 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5031 +#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
5032 +#endif
5033 +
5034 +#ifndef REG16_ADDR
5035 +#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
5036 +#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
5037 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5038 +#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
5039 +#endif
5040 +
5041 +#ifndef REG32_ADDR
5042 +#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
5043 +#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
5044 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5045 +#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
5046 +#endif
5047 +
5048 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5049 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5050 +#endif
5051 +
5052 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5053 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5054 +#endif
5055 +
5056 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5057 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5058 +#endif
5059 +
5060 +/* TNETD73XX chip definations */
5061 +
5062 +#define FREQ_1MHZ 1000000
5063 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5064 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5065 +
5066 +#ifdef AR7SEAD2
5067 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5068 +#else
5069 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5070 +#endif
5071 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5072 +
5073 +
5074 +
5075 +/* Module base addresses */
5076 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5077 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5078 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5079 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5080 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5081 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5082 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5083 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5084 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5085 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5086 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5087 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5088 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5089 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5090 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5091 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5092 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5093 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5094 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5095 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5096 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5097 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5098 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5099 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5100 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5101 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5102 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5103 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5104 +
5105 +/* BBIF Registers */
5106 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5107 +
5108 +/* Device Configuration Latch Registers */
5109 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5110 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5111 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5112 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5113 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5114 +
5115 +/* GPIO Control */
5116 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5117 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5118 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5119 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5120 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5121 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5122 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5123 +
5124 +/* Reset Control */
5125 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5126 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5127 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5128 +
5129 +/* Power Control */
5130 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5131 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5132 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5133 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5134 +
5135 +/* Clock Control */
5136 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5137 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5138 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5139 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5140 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5141 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5142 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5143 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5144 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5145 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5146 +
5147 +/* EMIF control */
5148 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5149 +
5150 +/* UART */
5151 +#ifdef AR7SEAD2
5152 +#define TNETD73XX_UART_FREQ 3686400
5153 +#else
5154 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5155 +#endif
5156 +
5157 +/* Interrupt Controller */
5158 +
5159 +/* Primary interrupts */
5160 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5161 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5162 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5163 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5164 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5165 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5166 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5167 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5168 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5169 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5170 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5171 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5172 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5173 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5174 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5175 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5176 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5177 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5178 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5179 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5180 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5181 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5182 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5183 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5184 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5185 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5186 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5187 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5188 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5189 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5190 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5191 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5192 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5193 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5194 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5195 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5196 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5197 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5198 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5199 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5200 +
5201 +/* Secondary interrupts */
5202 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5203 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5204 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5205 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5206 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5207 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5208 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5209 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5210 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5211 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5212 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5213 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5214 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5215 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5216 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5217 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5218 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5219 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5220 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5221 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5222 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5223 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5224 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5225 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5226 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5227 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5228 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5229 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5230 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5231 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5232 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5233 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5234 +
5235 +/* These ugly macros are to access the -1 registers, like config1 */
5236 +#define MFC0_SEL1_OPCODE(dst, src)\
5237 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5238 + nop; \
5239 + nop; \
5240 + nop
5241 +
5242 +#define MTC0_SEL1_OPCODE(dst, src)\
5243 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5244 + nop; \
5245 + nop; \
5246 + nop
5247 +
5248 +
5249 +/* Below are Jade core specific */
5250 +#define CFG0_4K_IL_MASK 0x00380000
5251 +#define CFG0_4K_IL_SHIFT 19
5252 +#define CFG0_4K_IA_MASK 0x00070000
5253 +#define CFG0_4K_IA_SHIFT 16
5254 +#define CFG0_4K_IS_MASK 0x01c00000
5255 +#define CFG0_4K_IS_SHIFT 22
5256 +
5257 +#define CFG0_4K_DL_MASK 0x00001c00
5258 +#define CFG0_4K_DL_SHIFT 10
5259 +#define CFG0_4K_DA_MASK 0x00000380
5260 +#define CFG0_4K_DA_SHIFT 7
5261 +#define CFG0_4K_DS_MASK 0x0000E000
5262 +#define CFG0_4K_DS_SHIFT 13
5263 +
5264 +
5265 +
5266 +#endif /* __TNETD73XX_H_ */
5267 diff -ruN linux_2_4_30/include/asm-mips/ar7/tnetd73xx_err.h linux/include/asm-mips/ar7/tnetd73xx_err.h
5268 --- linux_2_4_30/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 00:00:00.000000000 +0000
5269 +++ linux/include/asm-mips/ar7/tnetd73xx_err.h 2005-06-11 07:48:48.000000000 +0000
5270 @@ -0,0 +1,42 @@
5271 +/******************************************************************************
5272 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5273 + ******************************************************************************
5274 + * FILE NAME: tnetd73xx_err.h
5275 + *
5276 + * DESCRIPTION: Error definations for TNETD73XX
5277 + *
5278 + * REVISION HISTORY:
5279 + * 27 Nov 02 - PSP TII
5280 + *
5281 + * (C) Copyright 2002, Texas Instruments, Inc
5282 + *******************************************************************************/
5283 +
5284 +
5285 +#ifndef __TNETD73XX_ERR_H__
5286 +#define __TNETD73XX_ERR_H__
5287 +
5288 +typedef enum TNETD73XX_ERR_t
5289 +{
5290 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5291 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5292 +
5293 + /* Pointers and args */
5294 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5295 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5296 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5297 +
5298 + /* Memory issues */
5299 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5300 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5301 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5302 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5303 +
5304 + /* Device issues */
5305 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5306 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5307 +
5308 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5309 +
5310 +} TNETD73XX_ERR;
5311 +
5312 +#endif /* __TNETD73XX_ERR_H__ */
5313 diff -ruN linux_2_4_30/include/asm-mips/ar7/tnetd73xx_misc.h linux/include/asm-mips/ar7/tnetd73xx_misc.h
5314 --- linux_2_4_30/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 00:00:00.000000000 +0000
5315 +++ linux/include/asm-mips/ar7/tnetd73xx_misc.h 2005-06-12 10:29:31.000000000 +0000
5316 @@ -0,0 +1,243 @@
5317 +/******************************************************************************
5318 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5319 + ******************************************************************************
5320 + * FILE NAME: tnetd73xx_misc.h
5321 + *
5322 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5323 + * FSER Modules API
5324 + * As per TNETD73xx specifications
5325 + *
5326 + * REVISION HISTORY:
5327 + * 27 Nov 02 - Sharath Kumar PSP TII
5328 + * 14 Feb 03 - Anant Gole PSP TII
5329 + *
5330 + * (C) Copyright 2002, Texas Instruments, Inc
5331 + *******************************************************************************/
5332 +
5333 +#ifndef __TNETD73XX_MISC_H__
5334 +#define __TNETD73XX_MISC_H__
5335 +
5336 +#include <linux/types.h>
5337 +
5338 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
5339 +
5340 +/*****************************************************************************
5341 + * Reset Control Module
5342 + *****************************************************************************/
5343 +
5344 +typedef enum TNETD73XX_RESET_MODULE_tag
5345 +{
5346 + RESET_MODULE_UART0 = 0,
5347 + RESET_MODULE_UART1 = 1,
5348 + RESET_MODULE_I2C = 2,
5349 + RESET_MODULE_TIMER0 = 3,
5350 + RESET_MODULE_TIMER1 = 4,
5351 + RESET_MODULE_GPIO = 6,
5352 + RESET_MODULE_ADSLSS = 7,
5353 + RESET_MODULE_USBS = 8,
5354 + RESET_MODULE_SAR = 9,
5355 + RESET_MODULE_VDMA_VT = 11,
5356 + RESET_MODULE_FSER = 12,
5357 + RESET_MODULE_VLYNQ1 = 16,
5358 + RESET_MODULE_EMAC0 = 17,
5359 + RESET_MODULE_DMA = 18,
5360 + RESET_MODULE_BIST = 19,
5361 + RESET_MODULE_VLYNQ0 = 20,
5362 + RESET_MODULE_EMAC1 = 21,
5363 + RESET_MODULE_MDIO = 22,
5364 + RESET_MODULE_ADSLSS_DSP = 23,
5365 + RESET_MODULE_EPHY = 26
5366 +} TNETD73XX_RESET_MODULE_T;
5367 +
5368 +typedef enum TNETD73XX_RESET_CTRL_tag
5369 +{
5370 + IN_RESET = 0,
5371 + OUT_OF_RESET
5372 +} TNETD73XX_RESET_CTRL_T;
5373 +
5374 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5375 +{
5376 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5377 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5378 +} TNETD73XX_SYS_RST_MODE_T;
5379 +
5380 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5381 +{
5382 + HARDWARE_RESET = 0,
5383 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5384 + WATCHDOG_RESET,
5385 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
5386 +} TNETD73XX_SYS_RESET_STATUS_T;
5387 +
5388 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5389 + TNETD73XX_RESET_CTRL_T reset_ctrl);
5390 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5391 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5392 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5393 +
5394 +/*****************************************************************************
5395 + * Power Control Module
5396 + *****************************************************************************/
5397 +
5398 +typedef enum TNETD73XX_POWER_MODULE_tag
5399 +{
5400 + POWER_MODULE_USBSP = 0,
5401 + POWER_MODULE_WDTP = 1,
5402 + POWER_MODULE_UT0P = 2,
5403 + POWER_MODULE_UT1P = 3,
5404 + POWER_MODULE_IICP = 4,
5405 + POWER_MODULE_VDMAP = 5,
5406 + POWER_MODULE_GPIOP = 6,
5407 + POWER_MODULE_VLYNQ1P = 7,
5408 + POWER_MODULE_SARP = 8,
5409 + POWER_MODULE_ADSLP = 9,
5410 + POWER_MODULE_EMIFP = 10,
5411 + POWER_MODULE_ADSPP = 12,
5412 + POWER_MODULE_RAMP = 13,
5413 + POWER_MODULE_ROMP = 14,
5414 + POWER_MODULE_DMAP = 15,
5415 + POWER_MODULE_BISTP = 16,
5416 + POWER_MODULE_TIMER0P = 18,
5417 + POWER_MODULE_TIMER1P = 19,
5418 + POWER_MODULE_EMAC0P = 20,
5419 + POWER_MODULE_EMAC1P = 22,
5420 + POWER_MODULE_EPHYP = 24,
5421 + POWER_MODULE_VLYNQ0P = 27,
5422 +} TNETD73XX_POWER_MODULE_T;
5423 +
5424 +typedef enum TNETD73XX_POWER_CTRL_tag
5425 +{
5426 + POWER_CTRL_POWER_UP = 0,
5427 + POWER_CTRL_POWER_DOWN
5428 +} TNETD73XX_POWER_CTRL_T;
5429 +
5430 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5431 +{
5432 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
5433 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
5434 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
5435 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
5436 +} TNETD73XX_SYS_POWER_MODE_T;
5437 +
5438 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
5439 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5440 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5441 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5442 +
5443 +/*****************************************************************************
5444 + * Wakeup Control
5445 + *****************************************************************************/
5446 +
5447 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5448 +{
5449 + WAKEUP_INT0 = 1,
5450 + WAKEUP_INT1 = 2,
5451 + WAKEUP_INT2 = 4,
5452 + WAKEUP_INT3 = 8
5453 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5454 +
5455 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5456 +{
5457 + WAKEUP_DISABLED = 0,
5458 + WAKEUP_ENABLED
5459 +} TNETD73XX_WAKEUP_CTRL_T;
5460 +
5461 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5462 +{
5463 + WAKEUP_ACTIVE_HIGH = 0,
5464 + WAKEUP_ACTIVE_LOW
5465 +} TNETD73XX_WAKEUP_POLARITY_T;
5466 +
5467 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5468 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5469 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5470 +
5471 +/*****************************************************************************
5472 + * FSER Control
5473 + *****************************************************************************/
5474 +
5475 +typedef enum TNETD73XX_FSER_MODE_tag
5476 +{
5477 + FSER_I2C = 0,
5478 + FSER_UART = 1
5479 +} TNETD73XX_FSER_MODE_T;
5480 +
5481 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5482 +
5483 +/*****************************************************************************
5484 + * Clock Control
5485 + *****************************************************************************/
5486 +
5487 +#define CLK_MHZ(x) ( (x) * 1000000 )
5488 +
5489 +typedef enum TNETD73XX_CLKC_ID_tag
5490 +{
5491 + CLKC_SYS = 0,
5492 + CLKC_MIPS,
5493 + CLKC_USB,
5494 + CLKC_ADSLSS
5495 +} TNETD73XX_CLKC_ID_T;
5496 +
5497 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
5498 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
5499 +u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5500 +
5501 +/*****************************************************************************
5502 + * GPIO Control
5503 + *****************************************************************************/
5504 +
5505 +typedef enum TNETD73XX_GPIO_PIN_tag
5506 +{
5507 + GPIO_UART0_RD = 0,
5508 + GPIO_UART0_TD = 1,
5509 + GPIO_UART0_RTS = 2,
5510 + GPIO_UART0_CTS = 3,
5511 + GPIO_FSER_CLK = 4,
5512 + GPIO_FSER_D = 5,
5513 + GPIO_EXT_AFE_SCLK = 6,
5514 + GPIO_EXT_AFE_TX_FS = 7,
5515 + GPIO_EXT_AFE_TXD = 8,
5516 + GPIO_EXT_AFE_RS_FS = 9,
5517 + GPIO_EXT_AFE_RXD1 = 10,
5518 + GPIO_EXT_AFE_RXD0 = 11,
5519 + GPIO_EXT_AFE_CDIN = 12,
5520 + GPIO_EXT_AFE_CDOUT = 13,
5521 + GPIO_EPHY_SPEED100 = 14,
5522 + GPIO_EPHY_LINKON = 15,
5523 + GPIO_EPHY_ACTIVITY = 16,
5524 + GPIO_EPHY_FDUPLEX = 17,
5525 + GPIO_EINT0 = 18,
5526 + GPIO_EINT1 = 19,
5527 + GPIO_MBSP0_TCLK = 20,
5528 + GPIO_MBSP0_RCLK = 21,
5529 + GPIO_MBSP0_RD = 22,
5530 + GPIO_MBSP0_TD = 23,
5531 + GPIO_MBSP0_RFS = 24,
5532 + GPIO_MBSP0_TFS = 25,
5533 + GPIO_MII_DIO = 26,
5534 + GPIO_MII_DCLK = 27,
5535 +} TNETD73XX_GPIO_PIN_T;
5536 +
5537 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5538 +{
5539 + FUNCTIONAL_PIN = 0,
5540 + GPIO_PIN = 1
5541 +} TNETD73XX_GPIO_PIN_MODE_T;
5542 +
5543 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5544 +{
5545 + GPIO_OUTPUT_PIN = 0,
5546 + GPIO_INPUT_PIN = 1
5547 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5548 +
5549 +void tnetd73xx_gpio_init(void);
5550 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5551 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5552 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5553 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5554 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5555 +
5556 +/* TNETD73XX Revision */
5557 +u32 tnetd73xx_get_revision(void);
5558 +
5559 +#endif /* __TNETD73XX_MISC_H__ */
5560 diff -ruN linux_2_4_30/include/asm-mips/io.h linux/include/asm-mips/io.h
5561 --- linux_2_4_30/include/asm-mips/io.h 2005-05-22 18:27:58.000000000 +0000
5562 +++ linux/include/asm-mips/io.h 2005-06-12 11:08:22.000000000 +0000
5563 @@ -63,8 +63,12 @@
5564 #ifdef CONFIG_64BIT_PHYS_ADDR
5565 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
5566 #else
5567 +#ifdef CONFIG_AR7_PAGING
5568 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5569 +#else
5570 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
5571 #endif
5572 +#endif
5573
5574 #define IO_SPACE_LIMIT 0xffff
5575
5576 diff -ruN linux_2_4_30/include/asm-mips/irq.h linux/include/asm-mips/irq.h
5577 --- linux_2_4_30/include/asm-mips/irq.h 2005-05-22 18:27:58.000000000 +0000
5578 +++ linux/include/asm-mips/irq.h 2005-06-12 10:22:33.000000000 +0000
5579 @@ -14,7 +14,12 @@
5580 #include <linux/config.h>
5581 #include <linux/linkage.h>
5582
5583 +#ifdef CONFIG_AR7
5584 +#include <asm/ar7/avalanche_intc.h>
5585 +#define NR_IRQS AVALANCHE_INT_END + 1
5586 +#else
5587 #define NR_IRQS 128 /* Largest number of ints of all machines. */
5588 +#endif
5589
5590 #ifdef CONFIG_I8259
5591 static inline int irq_cannonicalize(int irq)
5592 diff -ruN linux_2_4_30/include/asm-mips/page.h linux/include/asm-mips/page.h
5593 --- linux_2_4_30/include/asm-mips/page.h 2005-05-22 18:27:59.000000000 +0000
5594 +++ linux/include/asm-mips/page.h 2005-06-12 10:39:06.000000000 +0000
5595 @@ -129,7 +129,11 @@
5596
5597 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
5598 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
5599 +#ifdef CONFIG_AR7_PAGING
5600 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
5601 +#else
5602 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5603 +#endif
5604 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
5605
5606 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
5607 diff -ruN linux_2_4_30/include/asm-mips/pgtable-32.h linux/include/asm-mips/pgtable-32.h
5608 --- linux_2_4_30/include/asm-mips/pgtable-32.h 2005-05-22 18:27:59.000000000 +0000
5609 +++ linux/include/asm-mips/pgtable-32.h 2005-06-12 10:39:06.000000000 +0000
5610 @@ -108,7 +108,18 @@
5611 * and a page entry and page directory to the page they refer to.
5612 */
5613
5614 -#ifdef CONFIG_CPU_VR41XX
5615 +#if defined(CONFIG_AR7_PAGING)
5616 +#define mk_pte(page, pgprot) \
5617 +({ \
5618 + pte_t __pte; \
5619 + \
5620 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
5621 + CONFIG_AR7_MEMORY) | \
5622 + pgprot_val(pgprot); \
5623 + \
5624 + __pte; \
5625 +})
5626 +#elif defined(CONFIG_CPU_VR41XX)
5627 #define mk_pte(page, pgprot) \
5628 ({ \
5629 pte_t __pte; \
5630 @@ -130,6 +141,7 @@
5631 })
5632 #endif
5633
5634 +
5635 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5636 {
5637 #ifdef CONFIG_CPU_VR41XX
5638 @@ -175,7 +187,10 @@
5639 set_pte(ptep, __pte(0));
5640 }
5641
5642 -#ifdef CONFIG_CPU_VR41XX
5643 +#if defined(CONFIG_AR7_PAGING)
5644 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5645 +#define pte_page(x) phys_to_page(pte_val(x))
5646 +#elif defined(CONFIG_CPU_VR41XX)
5647 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5648 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5649 #else
5650 diff -ruN linux_2_4_30/include/asm-mips/serial.h linux/include/asm-mips/serial.h
5651 --- linux_2_4_30/include/asm-mips/serial.h 2005-05-22 18:28:00.000000000 +0000
5652 +++ linux/include/asm-mips/serial.h 2005-06-12 11:08:39.000000000 +0000
5653 @@ -65,6 +65,15 @@
5654
5655 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5656
5657 +#ifdef CONFIG_AR7
5658 +#include <asm/ar7/ar7.h>
5659 +#define AR7_SERIAL_PORT_DEFNS \
5660 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5661 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5662 +#else
5663 +#define AR7_SERIAL_PORT_DEFNS
5664 +#endif
5665 +
5666 #ifdef CONFIG_MIPS_JAZZ
5667 #define _JAZZ_SERIAL_INIT(int, base) \
5668 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
5669 @@ -468,6 +477,7 @@
5670 #endif
5671
5672 #define SERIAL_PORT_DFNS \
5673 + AR7_SERIAL_PORT_DEFNS \
5674 ATLAS_SERIAL_PORT_DEFNS \
5675 AU1000_SERIAL_PORT_DEFNS \
5676 COBALT_SERIAL_PORT_DEFNS \
Personal OpenWRT clone
This page took 0.30153 seconds and 5 git commands to generate.