target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbsocram.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane embedded ram core
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  */
  13
  14 #ifndef _SBSOCRAM_H
  15 #define _SBSOCRAM_H
  16
  17 #ifndef _LANGUAGE_ASSEMBLY
  18
  19 /* cpp contortions to concatenate w/arg prescan */
  20 #ifndef PAD
  21 #define _PADLINE(line)  pad ## line
  22 #define _XSTR(line)     _PADLINE(line)
  23 #define PAD             _XSTR(__LINE__)
  24 #endif  /* PAD */
  25
  26 /* Memcsocram core registers */
  27 typedef volatile struct sbsocramregs {
  28         uint32  coreinfo;
  29         uint32  bwalloc;
  30         uint32  PAD;
  31         uint32  biststat;
  32         uint32  bankidx;
  33         uint32  standbyctrl;
  34         uint32  PAD[116];
  35         uint32  pwrctl;         /* corerev >= 2 */
  36 } sbsocramregs_t;
  37
  38 #endif  /* _LANGUAGE_ASSEMBLY */
  39
  40 /* Register offsets */
  41 #define SR_COREINFO             0x00
  42 #define SR_BWALLOC              0x04
  43 #define SR_BISTSTAT             0x0c
  44 #define SR_BANKINDEX            0x10
  45 #define SR_BANKSTBYCTL          0x14
  46 #define SR_PWRCTL               0x1e8
  47
  48 /* Coreinfo register */
  49 #define SRCI_PT_MASK            0x00030000
  50 #define SRCI_PT_SHIFT           16
  51 /* corerev >= 3 */
  52 #define SRCI_LSS_MASK           0x00f00000
  53 #define SRCI_LSS_SHIFT          20
  54 #define SRCI_LRS_MASK           0x0f000000
  55 #define SRCI_LRS_SHIFT          24
  56
  57 /* In corerev 0, the memory size is 2 to the power of the
  58  * base plus 16 plus to the contents of the memsize field plus 1.
  59  */
  60 #define SRCI_MS0_MASK           0xf
  61 #define SR_MS0_BASE             16
  62
  63 /*
  64  * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
  65  * the memory size is number of banks times bank size.
  66  * The same applies to rom size.
  67  */
  68 #define SRCI_ROMNB_MASK         0xf000
  69 #define SRCI_ROMNB_SHIFT        12
  70 #define SRCI_ROMBSZ_MASK        0xf00
  71 #define SRCI_ROMBSZ_SHIFT       8
  72 #define SRCI_SRNB_MASK          0xf0
  73 #define SRCI_SRNB_SHIFT         4
  74 #define SRCI_SRBSZ_MASK         0xf
  75 #define SRCI_SRBSZ_SHIFT        0
  76
  77 #define SR_BSZ_BASE             14
  78
  79 /* Standby control register */
  80 #define SRSC_SBYOVR_MASK                0x80000000
  81 #define SRSC_SBYOVR_SHIFT               31
  82 #define SRSC_SBYOVRVAL_MASK             0x60000000
  83 #define SRSC_SBYOVRVAL_SHIFT            29
  84
  85 #endif  /* _SBSOCRAM_H */