target/linux/adm5120/files/drivers/usb/host/adm5120.h

   1 /*
   2  * ADM5120 HCD (Host Controller Driver) for USB
   3  *
   4  * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   5  *
   6  * This file was derived from: drivers/usb/host/ohci.h
   7  *   (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   8  *   (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   9  *
  10  * This file is licenced under the GPL.
  11  */
  12
  13 /*
  14  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  15  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  16  * host controller implementation.
  17  */
  18 typedef __u32 __bitwise __hc32;
  19 typedef __u16 __bitwise __hc16;
  20
  21 /*
  22  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  23  * See OHCI spec, section 4.2
  24  *
  25  * This is a "Queue Head" for those transfers, which is why
  26  * both EHCI and UHCI call similar structures a "QH".
  27  */
  28
  29 #define TD_DATALEN_MAX  4096
  30
  31 #define ED_ALIGN        16
  32 #define ED_MASK ((u32)~(ED_ALIGN-1))    /* strip hw status in low addr bits */
  33
  34 struct ed {
  35         /* first fields are hardware-specified */
  36         __hc32                  hwINFO;      /* endpoint config bitmap */
  37         /* info bits defined by hcd */
  38 #define ED_DEQUEUE      (1 << 27)
  39         /* info bits defined by the hardware */
  40 #define ED_MPS_SHIFT    16
  41 #define ED_MPS_MASK     ((1 << 11)-1)
  42 #define ED_MPS_GET(x)   (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
  43 #define ED_ISO          (1 << 15)               /* isochronous endpoint */
  44 #define ED_SKIP         (1 << 14)
  45 #define ED_SPEED_FULL   (1 << 13)               /* fullspeed device */
  46 #define ED_INT          (1 << 11)               /* interrupt endpoint */
  47 #define ED_EN_SHIFT     7                       /* endpoint shift */
  48 #define ED_EN_MASK      ((1 << 4)-1)            /* endpoint mask */
  49 #define ED_EN_GET(x)    (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
  50 #define ED_FA_MASK      ((1 << 7)-1)            /* function address mask */
  51 #define ED_FA_GET(x)    ((x) & ED_FA_MASK)
  52         __hc32                  hwTailP;        /* tail of TD list */
  53         __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  54 #define ED_C            (0x02)                  /* toggle carry */
  55 #define ED_H            (0x01)                  /* halted */
  56         __hc32                  hwNextED;       /* next ED in list */
  57
  58         /* rest are purely for the driver's use */
  59         dma_addr_t              dma;            /* addr of ED */
  60         struct td               *dummy;         /* next TD to activate */
  61
  62         struct list_head        urb_list;       /* list of our URBs */
  63
  64         /* host's view of schedule */
  65         struct ed               *ed_next;       /* on schedule list */
  66         struct ed               *ed_prev;       /* for non-interrupt EDs */
  67         struct ed               *ed_rm_next;    /* on rm list */
  68         struct list_head        td_list;        /* "shadow list" of our TDs */
  69
  70         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  71          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  72          */
  73         u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
  74 #define ED_IDLE         0x00            /* NOT linked to HC */
  75 #define ED_UNLINK       0x01            /* being unlinked from hc */
  76 #define ED_OPER         0x02            /* IS linked to hc */
  77
  78         u8                      type;           /* PIPE_{BULK,...} */
  79
  80         /* periodic scheduling params (for intr and iso) */
  81         u8                      branch;
  82         u16                     interval;
  83         u16                     load;
  84         u16                     last_iso;       /* iso only */
  85
  86         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  87         u16                     tick;
  88 } __attribute__ ((aligned(ED_ALIGN)));
  89
  90 /*
  91  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  92  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  93  * and 4.3.2 (iso)
  94  */
  95
  96 #define TD_ALIGN        32
  97 #define TD_MASK ((u32)~(TD_ALIGN-1))    /* strip hw status in low addr bits */
  98
  99 struct td {
 100         /* first fields are hardware-specified */
 101         __hc32          hwINFO;         /* transfer info bitmask */
 102
 103         /* hwINFO bits */
 104 #define TD_OWN          (1 << 31)               /* owner of the descriptor */
 105 #define TD_CC_SHIFT     27                      /* condition code */
 106 #define TD_CC_MASK      0xf
 107 #define TD_CC           (TD_CC_MASK << TD_CC_SHIFT)
 108 #define TD_CC_GET(x)    (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
 109
 110 #define TD_EC_SHIFT     25                      /* error count */
 111 #define TD_EC_MASK      0x3
 112 #define TD_EC           (TD_EC_MASK << TD_EC_SHIFT)
 113 #define TD_EC_GET(x)    ((x >> TD_EC_SHIFT) & TD_EC_MASK)
 114 #define TD_T_SHIFT      23                      /* data toggle state */
 115 #define TD_T_MASK       0x3
 116 #define TD_T            (TD_T_MASK << TD_T_SHIFT)
 117 #define TD_T_DATA0      (0x2 << TD_T_SHIFT)     /* DATA0 */
 118 #define TD_T_DATA1      (0x3 << TD_T_SHIFT)     /* DATA1 */
 119 #define TD_T_CARRY      (0x0 << TD_T_SHIFT)     /* uses ED_C */
 120 #define TD_T_GET(x)     (((x) >> TD_T_SHIFT) & TD_T_MASK)
 121 #define TD_DP_SHIFT     21                      /* direction/pid */
 122 #define TD_DP_MASK      0x3
 123 #define TD_DP           (TD_DP_MASK << TD_DP_SHIFT)
 124 #define TD_DP_GET       (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
 125 #define TD_DP_SETUP     (0x0 << TD_DP_SHIFT)    /* SETUP pid */
 126 #define TD_DP_OUT       (0x1 << TD_DP_SHIFT)    /* OUT pid */
 127 #define TD_DP_IN        (0x2 << TD_DP_SHIFT)    /* IN pid */
 128 #define TD_ISI_SHIFT    8                       /* Interrupt Service Interval */
 129 #define TD_ISI_MASK     0x3f
 130 #define TD_ISI_GET(x)   (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
 131 #define TD_FN_MASK      0x3f                    /* frame number */
 132 #define TD_FN_GET(x)    ((x) & TD_FN_MASK)
 133
 134         __hc32          hwDBP;          /* Data Buffer Pointer (or 0) */
 135         __hc32          hwCBL;          /* Controller/Buffer Length */
 136
 137         /* hwCBL bits */
 138 #define TD_BL_MASK      0xffff          /* buffer length */
 139 #define TD_BL_GET(x)    ((x) & TD_BL_MASK)
 140 #define TD_IE           (1 << 16)       /* interrupt enable */
 141         __hc32          hwNextTD;       /* Next TD Pointer */
 142
 143         /* rest are purely for the driver's use */
 144         __u8            index;
 145         struct ed       *ed;
 146         struct td       *td_hash;       /* dma-->td hashtable */
 147         struct td       *next_dl_td;
 148         struct urb      *urb;
 149
 150         dma_addr_t      td_dma;         /* addr of this TD */
 151         dma_addr_t      data_dma;       /* addr of data it points to */
 152
 153         struct list_head td_list;       /* "shadow list", TDs on same ED */
 154
 155         u32             flags;
 156 #define TD_FLAG_DONE    (1 << 17)       /* retired to done list */
 157 #define TD_FLAG_ISO     (1 << 16)       /* copy of ED_ISO */
 158 } __attribute__ ((aligned(TD_ALIGN)));  /* c/b/i need 16; only iso needs 32 */
 159
 160 /*
 161  * Hardware transfer status codes -- CC from td->hwINFO
 162  */
 163 #define TD_CC_NOERROR           0x00
 164 #define TD_CC_CRC               0x01
 165 #define TD_CC_BITSTUFFING       0x02
 166 #define TD_CC_DATATOGGLEM       0x03
 167 #define TD_CC_STALL             0x04
 168 #define TD_CC_DEVNOTRESP        0x05
 169 #define TD_CC_PIDCHECKFAIL      0x06
 170 #define TD_CC_UNEXPECTEDPID     0x07
 171 #define TD_CC_DATAOVERRUN       0x08
 172 #define TD_CC_DATAUNDERRUN      0x09
 173     /* 0x0A, 0x0B reserved for hardware */
 174 #define TD_CC_BUFFEROVERRUN     0x0C
 175 #define TD_CC_BUFFERUNDERRUN    0x0D
 176     /* 0x0E, 0x0F reserved for HCD */
 177 #define TD_CC_HCD0              0x0E
 178 #define TD_CC_NOTACCESSED       0x0F
 179
 180 /*
 181  * preshifted status codes
 182  */
 183 #define TD_SCC_NOTACCESSED      (TD_CC_NOTACCESSED << TD_CC_SHIFT)
 184
 185
 186 /* map OHCI TD status codes (CC) to errno values */
 187 static const int cc_to_error [16] = {
 188         /* No  Error  */        0,
 189         /* CRC Error  */        -EILSEQ,
 190         /* Bit Stuff  */        -EPROTO,
 191         /* Data Togg  */        -EILSEQ,
 192         /* Stall      */        -EPIPE,
 193         /* DevNotResp */        -ETIME,
 194         /* PIDCheck   */        -EPROTO,
 195         /* UnExpPID   */        -EPROTO,
 196         /* DataOver   */        -EOVERFLOW,
 197         /* DataUnder  */        -EREMOTEIO,
 198         /* (for hw)   */        -EIO,
 199         /* (for hw)   */        -EIO,
 200         /* BufferOver */        -ECOMM,
 201         /* BuffUnder  */        -ENOSR,
 202         /* (for HCD)  */        -EALREADY,
 203         /* (for HCD)  */        -EALREADY
 204 };
 205
 206 #define NUM_INTS        32
 207
 208 /*
 209  * This is the structure of the OHCI controller's memory mapped I/O region.
 210  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 211  * Layout is in section 7 (and appendix B) of the spec.
 212  */
 213 struct admhcd_regs {
 214         __hc32  gencontrol;     /* General Control */
 215         __hc32  int_status;     /* Interrupt Status */
 216         __hc32  int_enable;     /* Interrupt Enable */
 217         __hc32  reserved00;
 218         __hc32  host_control;   /* Host General Control */
 219         __hc32  reserved01;
 220         __hc32  fminterval;     /* Frame Interval */
 221         __hc32  fmnumber;       /* Frame Number */
 222         __hc32  reserved02;
 223         __hc32  reserved03;
 224         __hc32  reserved04;
 225         __hc32  reserved05;
 226         __hc32  reserved06;
 227         __hc32  reserved07;
 228         __hc32  reserved08;
 229         __hc32  reserved09;
 230         __hc32  reserved10;
 231         __hc32  reserved11;
 232         __hc32  reserved12;
 233         __hc32  reserved13;
 234         __hc32  reserved14;
 235         __hc32  reserved15;
 236         __hc32  reserved16;
 237         __hc32  reserved17;
 238         __hc32  reserved18;
 239         __hc32  reserved19;
 240         __hc32  reserved20;
 241         __hc32  reserved21;
 242         __hc32  lsthresh;       /* Low Speed Threshold */
 243         __hc32  rhdesc;         /* Root Hub Descriptor */
 244 #define MAX_ROOT_PORTS  2
 245         __hc32  portstatus[MAX_ROOT_PORTS]; /* Port Status */
 246         __hc32  hosthead;       /* Host Descriptor Head */
 247 } __attribute__ ((aligned(32)));
 248
 249 /*
 250  * General Control register bits
 251  */
 252 #define ADMHC_CTRL_UHFE (1 << 0)        /* USB Host Function Enable */
 253 #define ADMHC_CTRL_SIR  (1 << 1)        /* Software Interrupt request */
 254 #define ADMHC_CTRL_DMAA (1 << 2)        /* DMA Arbitration Control */
 255 #define ADMHC_CTRL_SR   (1 << 3)        /* Software Reset */
 256
 257 /*
 258  * Host General Control register bits
 259  */
 260 #define ADMHC_HC_BUSS           0x3             /* USB bus state */
 261 #define   ADMHC_BUSS_RESET      0x0
 262 #define   ADMHC_BUSS_RESUME     0x1
 263 #define   ADMHC_BUSS_OPER       0x2
 264 #define   ADMHC_BUSS_SUSPEND    0x3
 265 #define ADMHC_HC_DMAE           (1 << 2)        /* DMA enable */
 266
 267 /*
 268  * Interrupt Status/Enable register bits
 269  */
 270 #define ADMHC_INTR_SOFI (1 << 4)        /* start of frame */
 271 #define ADMHC_INTR_RESI (1 << 5)        /* resume detected */
 272 #define ADMHC_INTR_6    (1 << 6)        /* unknown */
 273 #define ADMHC_INTR_7    (1 << 7)        /* unknown */
 274 #define ADMHC_INTR_BABI (1 << 8)        /* babble detected */
 275 #define ADMHC_INTR_INSM (1 << 9)        /* root hub status change */
 276 #define ADMHC_INTR_SO   (1 << 10)       /* scheduling overrun */
 277 #define ADMHC_INTR_FNO  (1 << 11)       /* frame number overflow */
 278 #define ADMHC_INTR_TDC  (1 << 20)       /* transfer descriptor completed */
 279 #define ADMHC_INTR_SWI  (1 << 29)       /* software interrupt */
 280 #define ADMHC_INTR_FATI (1 << 30)       /* fatal error */
 281 #define ADMHC_INTR_INTA (1 << 31)       /* interrupt active */
 282
 283 #define ADMHC_INTR_MIE  (1 << 31)       /* master interrupt enable */
 284
 285 /*
 286  * SOF Frame Interval register bits
 287  */
 288 #define ADMHC_SFI_FI_MASK       ((1 << 14)-1)   /* Frame Interval value */
 289 #define ADMHC_SFI_FSLDP_SHIFT   16
 290 #define ADMHC_SFI_FSLDP_MASK    ((1 << 15)-1)
 291 #define ADMHC_SFI_FIT           (1 << 31)       /* Frame Interval Toggle */
 292
 293 /*
 294  * SOF Frame Number register bits
 295  */
 296 #define ADMHC_SFN_FN_MASK       ((1 << 16)-1)   /* Frame Number Mask */
 297 #define ADMHC_SFN_FR_SHIFT      16              /* Frame Remaining Shift */
 298 #define ADMHC_SFN_FR_MASK       ((1 << 14)-1)   /* Frame Remaining Mask */
 299 #define ADMHC_SFN_FRT           (1 << 31)       /* Frame Remaining Toggle */
 300
 301 /*
 302  * Root Hub Descriptor register bits
 303  */
 304 #define ADMHC_RH_NUMP   0xff            /* number of ports */
 305 #define ADMHC_RH_PSM    (1 << 8)        /* power switching mode */
 306 #define ADMHC_RH_NPS    (1 << 9)        /* no power switching */
 307 #define ADMHC_RH_OCPM   (1 << 10)       /* over current protection mode */
 308 #define ADMHC_RH_NOCP   (1 << 11)       /* no over current protection */
 309 #define ADMHC_RH_PPCM   (0xff << 16)    /* port power control */
 310
 311 #define ADMHC_RH_LPS    (1 << 24)       /* local power switch */
 312 #define ADMHC_RH_OCI    (1 << 25)       /* over current indicator */
 313
 314 /* status change bits */
 315 #define ADMHC_RH_LPSC   (1 << 26)       /* local power switch change */
 316 #define ADMHC_RH_OCIC   (1 << 27)       /* over current indicator change */
 317
 318 #define ADMHC_RH_DRWE   (1 << 28)       /* device remote wakeup enable */
 319 #define ADMHC_RH_CRWE   (1 << 29)       /* clear remote wakeup enable */
 320
 321 #define ADMHC_RH_CGP    (1 << 24)       /* clear global power */
 322 #define ADMHC_RH_SGP    (1 << 26)       /* set global power */
 323
 324 /*
 325  * Port Status register bits
 326  */
 327 #define ADMHC_PS_CCS    (1 << 0)        /* current connect status */
 328 #define ADMHC_PS_PES    (1 << 1)        /* port enable status */
 329 #define ADMHC_PS_PSS    (1 << 2)        /* port suspend status */
 330 #define ADMHC_PS_POCI   (1 << 3)        /* port over current indicator */
 331 #define ADMHC_PS_PRS    (1 << 4)        /* port reset status */
 332 #define ADMHC_PS_PPS    (1 << 8)        /* port power status */
 333 #define ADMHC_PS_LSDA   (1 << 9)        /* low speed device attached */
 334
 335 /* status change bits */
 336 #define ADMHC_PS_CSC    (1 << 16)       /* connect status change */
 337 #define ADMHC_PS_PESC   (1 << 17)       /* port enable status change */
 338 #define ADMHC_PS_PSSC   (1 << 18)       /* port suspend status change */
 339 #define ADMHC_PS_OCIC   (1 << 19)       /* over current indicator change */
 340 #define ADMHC_PS_PRSC   (1 << 20)       /* port reset status change */
 341
 342 /* port feature bits */
 343 #define ADMHC_PS_CPE    (1 << 0)        /* clear port enable */
 344 #define ADMHC_PS_SPE    (1 << 1)        /* set port enable */
 345 #define ADMHC_PS_SPS    (1 << 2)        /* set port suspend */
 346 #define ADMHC_PS_CPS    (1 << 3)        /* clear suspend status */
 347 #define ADMHC_PS_SPR    (1 << 4)        /* set port reset */
 348 #define ADMHC_PS_SPP    (1 << 8)        /* set port power */
 349 #define ADMHC_PS_CPP    (1 << 9)        /* clear port power */
 350
 351 /*
 352  * the POTPGT value is not defined in the ADMHC, so define a dummy value
 353  */
 354 #define ADMHC_POTPGT    2               /* in ms */
 355
 356 /* hcd-private per-urb state */
 357 struct urb_priv {
 358         struct ed               *ed;
 359         struct list_head        pending;        /* URBs on the same ED */
 360
 361         u32                     td_cnt;         /* # tds in this request */
 362         u32                     td_idx;         /* index of the current td */
 363         struct td               *td[0];         /* all TDs in this request */
 364 };
 365
 366 #define TD_HASH_SIZE    64    /* power'o'two */
 367 /* sizeof (struct td) ~= 64 == 2^6 ... */
 368 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 369
 370 /*
 371  * This is the full ADMHCD controller description
 372  *
 373  * Note how the "proper" USB information is just
 374  * a subset of what the full implementation needs. (Linus)
 375  */
 376
 377 struct admhcd {
 378         spinlock_t              lock;
 379
 380         /*
 381          * I/O memory used to communicate with the HC (dma-consistent)
 382          */
 383         struct admhcd_regs __iomem *regs;
 384
 385         /*
 386          * hcd adds to schedule for a live hc any time, but removals finish
 387          * only at the start of the next frame.
 388          */
 389
 390         struct ed               *ed_head;
 391         struct ed               *ed_tails[4];
 392
 393         struct ed               *ed_rm_list;    /* to be removed */
 394
 395         struct ed               *periodic[NUM_INTS];    /* shadow int_table */
 396
 397 #if 0   /* TODO: remove? */
 398         /*
 399          * OTG controllers and transceivers need software interaction;
 400          * other external transceivers should be software-transparent
 401          */
 402         struct otg_transceiver  *transceiver;
 403 #endif
 404
 405         /*
 406          * memory management for queue data structures
 407          */
 408         struct dma_pool         *td_cache;
 409         struct dma_pool         *ed_cache;
 410         struct td               *td_hash[TD_HASH_SIZE];
 411         struct list_head        pending;
 412
 413         /*
 414          * driver state
 415          */
 416         int                     num_ports;
 417         int                     load[NUM_INTS];
 418         u32                     host_control;   /* copy of the host_control reg */
 419         unsigned long           next_statechange;       /* suspend/resume */
 420         u32                     fminterval;             /* saved register */
 421         unsigned                autostop:1;     /* rh auto stopping/stopped */
 422
 423         unsigned long           flags;          /* for HC bugs */
 424 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 425 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 426 #define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 427 #define OHCI_QUIRK_BE_DESC      0x08                    /* BE descriptors */
 428 #define OHCI_QUIRK_BE_MMIO      0x10                    /* BE registers */
 429 #define OHCI_QUIRK_ZFMICRO      0x20                    /* Compaq ZFMicro chipset*/
 430         // there are also chip quirks/bugs in init logic
 431 };
 432
 433 /* convert between an hcd pointer and the corresponding ahcd_hcd */
 434 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
 435 {
 436         return (struct admhcd *)(hcd->hcd_priv);
 437 }
 438 static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
 439 {
 440         return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
 441 }
 442
 443 /*-------------------------------------------------------------------------*/
 444
 445 #ifndef DEBUG
 446 #define STUB_DEBUG_FILES
 447 #endif  /* DEBUG */
 448
 449 #ifdef DEBUG
 450 #       define admhc_dbg(ahcd, fmt, args...) \
 451                 printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
 452 #else
 453 #       define admhc_dbg(ahcd, fmt, args...) do { } while (0)
 454 #endif
 455
 456 #define admhc_err(ahcd, fmt, args...) \
 457         printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
 458 #define admhc_info(ahcd, fmt, args...) \
 459         printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
 460 #define admhc_warn(ahcd, fmt, args...) \
 461         printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
 462
 463 #ifdef ADMHC_VERBOSE_DEBUG
 464 #       define admhc_vdbg admhc_dbg
 465 #else
 466 #       define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
 467 #endif
 468
 469 /*-------------------------------------------------------------------------*/
 470
 471 /*
 472  * While most USB host controllers implement their registers and
 473  * in-memory communication descriptors in little-endian format,
 474  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 475  * processors) implement them in big endian format.
 476  *
 477  * In addition some more exotic implementations like the Toshiba
 478  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
 479  * they have a different endianness for registers vs. in-memory
 480  * descriptors.
 481  *
 482  * This attempts to support either format at compile time without a
 483  * runtime penalty, or both formats with the additional overhead
 484  * of checking a flag bit.
 485  *
 486  * That leads to some tricky Kconfig rules howevber. There are
 487  * different defaults based on some arch/ppc platforms, though
 488  * the basic rules are:
 489  *
 490  * Controller type              Kconfig options needed
 491  * ---------------              ----------------------
 492  * little endian                CONFIG_USB_ADMHC_LITTLE_ENDIAN
 493  *
 494  * fully big endian             CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
 495  *                              CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 496  *
 497  * mixed endian                 CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
 498  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
 499  *
 500  * (If you have a mixed endian controller, you -must- also define
 501  * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
 502  * both your mixed endian and a fully big endian controller support in
 503  * the same kernel image).
 504  */
 505
 506 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
 507 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 508 #define big_endian_desc(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_DESC)
 509 #else
 510 #define big_endian_desc(ahcd)   1               /* only big endian */
 511 #endif
 512 #else
 513 #define big_endian_desc(ahcd)   0               /* only little endian */
 514 #endif
 515
 516 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 517 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 518 #define big_endian_mmio(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_MMIO)
 519 #else
 520 #define big_endian_mmio(ahcd)   1               /* only big endian */
 521 #endif
 522 #else
 523 #define big_endian_mmio(ahcd)   0               /* only little endian */
 524 #endif
 525
 526 /*
 527  * Big-endian read/write functions are arch-specific.
 528  * Other arches can be added if/when they're needed.
 529  *
 530  * REVISIT: arch/powerpc now has readl/writel_be, so the
 531  * definition below can die once the STB04xxx support is
 532  * finally ported over.
 533  */
 534 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
 535 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 536 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 537 #endif
 538
 539 static inline unsigned int admhc_readl(const struct admhcd *ahcd,
 540         __hc32 __iomem *regs)
 541 {
 542 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 543         return big_endian_mmio(ahcd) ?
 544                 readl_be(regs) :
 545                 readl(regs);
 546 #else
 547         return readl(regs);
 548 #endif
 549 }
 550
 551 static inline void admhc_writel(const struct admhcd *ahcd,
 552         const unsigned int val, __hc32 __iomem *regs)
 553 {
 554 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 555         big_endian_mmio(ahcd) ?
 556                 writel_be(val, regs) :
 557                 writel(val, regs);
 558 #else
 559                 writel(val, regs);
 560 #endif
 561 }
 562
 563 static inline void admhc_writel_flush(const struct admhcd *ahcd)
 564 {
 565 #if 0
 566         /* TODO: remove? */
 567         (void) admhc_readl(ahcd, &ahcd->regs->gencontrol);
 568 #endif
 569 }
 570
 571
 572 /*-------------------------------------------------------------------------*/
 573
 574 /* cpu to ahcd */
 575 static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
 576 {
 577         return big_endian_desc(ahcd) ?
 578                 (__force __hc16)cpu_to_be16(x) :
 579                 (__force __hc16)cpu_to_le16(x);
 580 }
 581
 582 static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
 583 {
 584         return big_endian_desc(ahcd) ?
 585                 cpu_to_be16p(x) :
 586                 cpu_to_le16p(x);
 587 }
 588
 589 static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
 590 {
 591         return big_endian_desc(ahcd) ?
 592                 (__force __hc32)cpu_to_be32(x) :
 593                 (__force __hc32)cpu_to_le32(x);
 594 }
 595
 596 static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
 597 {
 598         return big_endian_desc(ahcd) ?
 599                 cpu_to_be32p(x) :
 600                 cpu_to_le32p(x);
 601 }
 602
 603 /* ahcd to cpu */
 604 static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
 605 {
 606         return big_endian_desc(ahcd) ?
 607                 be16_to_cpu((__force __be16)x) :
 608                 le16_to_cpu((__force __le16)x);
 609 }
 610
 611 static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
 612 {
 613         return big_endian_desc(ahcd) ?
 614                 be16_to_cpup((__force __be16 *)x) :
 615                 le16_to_cpup((__force __le16 *)x);
 616 }
 617
 618 static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
 619 {
 620         return big_endian_desc(ahcd) ?
 621                 be32_to_cpu((__force __be32)x) :
 622                 le32_to_cpu((__force __le32)x);
 623 }
 624
 625 static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
 626 {
 627         return big_endian_desc(ahcd) ?
 628                 be32_to_cpup((__force __be32 *)x) :
 629                 le32_to_cpup((__force __le32 *)x);
 630 }
 631
 632 /*-------------------------------------------------------------------------*/
 633
 634 static inline u16 admhc_frame_no(const struct admhcd *ahcd)
 635 {
 636         u32     t;
 637
 638         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
 639         return (u16)t;
 640 }
 641
 642 static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
 643 {
 644         u32     t;
 645
 646         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
 647         t &= ADMHC_SFN_FR_MASK;
 648         return (u16)t;
 649 }
 650
 651 /*-------------------------------------------------------------------------*/
 652
 653 static inline void admhc_disable(struct admhcd *ahcd)
 654 {
 655         admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
 656 }
 657
 658 #define FI              0x2edf          /* 12000 bits per frame (-1) */
 659 #define FSLDP(fi)       (0x7fff & ((6 * ((fi) - 1200)) / 7))
 660 #define FIT             ADMHC_SFI_FIT
 661 #define LSTHRESH        0x628           /* lowspeed bit threshold */
 662
 663 static inline void periodic_reinit(struct admhcd *ahcd)
 664 {
 665 #if 0
 666         u32     fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
 667         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 668
 669         /* TODO: adjust FSLargestDataPacket value too? */
 670         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 671                                         &ahcd->regs->fminterval);
 672 #else
 673         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 674
 675         /* TODO: adjust FSLargestDataPacket value too? */
 676         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 677                                         &ahcd->regs->fminterval);
 678 #endif
 679 }
 680
 681 static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
 682 {
 683         return admhc_readl(ahcd, &ahcd->regs->rhdesc);
 684 }
 685
 686 static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
 687 {
 688         return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
 689 }
 690
 691 static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
 692                 u32 value)
 693 {
 694         admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
 695 }
 696
 697 static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
 698 {
 699         /* FIXME: read-only bits must be masked out */
 700         admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
 701 }
 702
 703 static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
 704 {
 705         u32     t;
 706
 707         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 708         t &= ~(ints);
 709         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 710         /* TODO: flush writes ?*/
 711 }
 712
 713 static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
 714 {
 715         u32     t;
 716
 717         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 718         t |= ints;
 719         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 720         /* TODO: flush writes ?*/
 721 }
 722
 723 static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
 724 {
 725         admhc_writel(ahcd, ints, &ahcd->regs->int_status);
 726 }
 727
 728 static inline void admhc_dma_enable(struct admhcd *ahcd)
 729 {
 730         u32 t;
 731
 732         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 733         if (t & ADMHC_HC_DMAE)
 734                 return;
 735
 736         t |= ADMHC_HC_DMAE;
 737         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 738         admhc_vdbg(ahcd,"DMA enabled\n");
 739 }
 740
 741 static inline void admhc_dma_disable(struct admhcd *ahcd)
 742 {
 743         u32 t;
 744
 745         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 746         if (!(t & ADMHC_HC_DMAE))
 747                 return;
 748
 749         t &= ~ADMHC_HC_DMAE;
 750         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 751         admhc_vdbg(ahcd,"DMA disabled\n");
 752 }