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ar71xx: fix a typo in the ar724x PCI code
[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c
1 /*
2 * Atheros AR71xx PCI host controller driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/resource.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/pci.h>
19 #include <linux/pci_regs.h>
20
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
23
24 #undef DEBUG
25 #ifdef DEBUG
26 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
27 #else
28 #define DBG(fmt, args...)
29 #endif
30
31 #define AR71XX_PCI_DELAY 100 /* msecs */
32
33 #if 0
34 #define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
35 #else
36 #define PCI_IDSEL_BASE 0
37 #endif
38
39 static void __iomem *ar71xx_pcicfg_base;
40 static DEFINE_SPINLOCK(ar71xx_pci_lock);
41
42 static inline void ar71xx_pci_delay(void)
43 {
44 mdelay(AR71XX_PCI_DELAY);
45 }
46
47 static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
48 {
49 return __raw_readl(ar71xx_pcicfg_base + reg);
50 }
51
52 static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
53 {
54 __raw_writel(val, ar71xx_pcicfg_base + reg);
55 }
56
57 /* Byte lane enable bits */
58 static u8 ble_table[4][4] = {
59 {0x0, 0xf, 0xf, 0xf},
60 {0xe, 0xd, 0xb, 0x7},
61 {0xc, 0xf, 0x3, 0xf},
62 {0xf, 0xf, 0xf, 0xf},
63 };
64
65 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
66 {
67 u32 t;
68
69 t = ble_table[size & 3][where & 3];
70 BUG_ON(t == 0xf);
71 t <<= (local) ? 20 : 4;
72 return t;
73 }
74
75 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
76 int where)
77 {
78 u32 ret;
79
80 if (!bus->number) {
81 /* type 0 */
82 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
83 | (PCI_FUNC(devfn) << 8) | (where & ~3);
84 } else {
85 /* type 1 */
86 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
87 | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
88 }
89
90 return ret;
91 }
92
93 int ar71xx_pci_be_handler(int is_fixup)
94 {
95 u32 pci_err;
96 u32 ahb_err;
97
98 pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
99 if (pci_err) {
100 if (!is_fixup)
101 printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
102 pci_err,
103 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
104
105 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
106 }
107
108 ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
109 if (ahb_err) {
110 if (!is_fixup)
111 printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
112 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
113
114 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
115 }
116
117 return ((ahb_err | pci_err) ? 1 : 0);
118 }
119
120 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
121 unsigned int devfn, int where, int size, u32 cmd)
122 {
123 u32 addr;
124
125 addr = ar71xx_pci_bus_addr(bus, devfn, where);
126
127 DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
128 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
129 where, size, addr);
130
131 ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
132 ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
133 cmd | ar71xx_pci_get_ble(where, size, 0));
134
135 return ar71xx_pci_be_handler(1);
136 }
137
138 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
139 int where, int size, u32 *value)
140 {
141 static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
142 unsigned long flags;
143 u32 data;
144 int ret;
145
146 ret = PCIBIOS_SUCCESSFUL;
147
148 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
149 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
150
151 spin_lock_irqsave(&ar71xx_pci_lock, flags);
152
153 if (bus->number == 0 && devfn == 0) {
154 u32 t;
155
156 t = PCI_CRP_CMD_READ | (where & ~3);
157
158 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
159 data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
160
161 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
162
163 } else {
164 int err;
165
166 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
167 PCI_CFG_CMD_READ);
168
169 if (err == 0) {
170 data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
171 } else {
172 ret = PCIBIOS_DEVICE_NOT_FOUND;
173 data = ~0;
174 }
175 }
176
177 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
178
179 DBG("PCI: read config: data=%08x raw=%08x\n",
180 (data >> (8 * (where & 3))) & mask[size & 7], data);
181
182 *value = (data >> (8 * (where & 3))) & mask[size & 7];
183
184 return ret;
185 }
186
187 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
188 int where, int size, u32 value)
189 {
190 unsigned long flags;
191 int ret;
192
193 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
194 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
195 where, size, value);
196
197 value = value << (8 * (where & 3));
198 ret = PCIBIOS_SUCCESSFUL;
199
200 spin_lock_irqsave(&ar71xx_pci_lock, flags);
201 if (bus->number == 0 && devfn == 0) {
202 u32 t;
203
204 t = PCI_CRP_CMD_WRITE | (where & ~3);
205 t |= ar71xx_pci_get_ble(where, size, 1);
206
207 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
208
209 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
210 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
211 } else {
212 int err;
213
214 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
215 PCI_CFG_CMD_WRITE);
216
217 if (err == 0)
218 ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
219 else
220 ret = PCIBIOS_DEVICE_NOT_FOUND;
221 }
222 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
223
224 return ret;
225 }
226
227 static void ar71xx_pci_fixup(struct pci_dev *dev)
228 {
229 u32 t;
230
231 if (dev->bus->number != 0 || dev->devfn != 0)
232 return;
233
234 DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
235 dev->vendor, dev->device);
236
237 /* setup COMMAND register */
238 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
239 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
240
241 pci_write_config_word(dev, PCI_COMMAND, t);
242 }
243 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
244
245 int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
246 uint8_t pin)
247 {
248 int irq = -1;
249 int i;
250
251 slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
252
253 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
254 struct ar71xx_pci_irq *entry;
255
256 entry = &ar71xx_pci_irq_map[i];
257 if (entry->slot == slot && entry->pin == pin) {
258 irq = entry->irq;
259 break;
260 }
261 }
262
263 if (irq < 0) {
264 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
265 pin, pci_name((struct pci_dev *)dev));
266 } else {
267 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
268 irq, pin, pci_name((struct pci_dev *)dev));
269 }
270
271 return irq;
272 }
273
274 static struct pci_ops ar71xx_pci_ops = {
275 .read = ar71xx_pci_read_config,
276 .write = ar71xx_pci_write_config,
277 };
278
279 static struct resource ar71xx_pci_io_resource = {
280 .name = "PCI IO space",
281 .start = 0,
282 .end = 0,
283 .flags = IORESOURCE_IO,
284 };
285
286 static struct resource ar71xx_pci_mem_resource = {
287 .name = "PCI memory space",
288 .start = AR71XX_PCI_MEM_BASE,
289 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
290 .flags = IORESOURCE_MEM
291 };
292
293 static struct pci_controller ar71xx_pci_controller = {
294 .pci_ops = &ar71xx_pci_ops,
295 .mem_resource = &ar71xx_pci_mem_resource,
296 .io_resource = &ar71xx_pci_io_resource,
297 };
298
299 int __init ar71xx_pcibios_init(void)
300 {
301 ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
302 ar71xx_pci_delay();
303
304 ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
305 ar71xx_pci_delay();
306
307 ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
308 AR71XX_PCI_CFG_SIZE);
309
310 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
311 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
312 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
313 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
314 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
315 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
316 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
317 ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
318
319 ar71xx_pci_delay();
320
321 /* clear bus errors */
322 (void)ar71xx_pci_be_handler(1);
323
324 register_pci_controller(&ar71xx_pci_controller);
325
326 return 0;
327 }
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