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add rb532 support
[openwrt.git] / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-06-08 20:21:20.000000000 +0200
3 +++ linux.dev/arch/mips/Kconfig 2006-06-15 16:26:53.000000000 +0200
4 @@ -739,6 +739,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Support for Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1012,7 +1025,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-06-08 20:21:20.000000000 +0200
35 +++ linux.dev/arch/mips/Makefile 2006-06-15 16:26:53.000000000 +0200
36 @@ -725,6 +725,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-06-08 20:21:20.000000000 +0200
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-06-15 16:26:53.000000000 +0200
53 @@ -852,7 +852,6 @@
54
55 case CPU_R10000:
56 case CPU_R12000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -880,6 +879,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-06-15 16:26:53.000000000 +0200
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/config.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-06-08 20:21:20.000000000 +0200
124 +++ linux.dev/arch/mips/pci/Makefile 2006-06-15 16:26:53.000000000 +0200
125 @@ -57,3 +57,4 @@
126 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
127 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
128 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-06-15 16:26:53.000000000 +0200
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/config.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-06-15 16:26:53.000000000 +0200
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/config.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-06-15 16:27:14.000000000 +0200
570 @@ -0,0 +1,211 @@
571 +#include <linux/kernel.h>
572 +#include <linux/init.h>
573 +#include <linux/module.h>
574 +#include <linux/ctype.h>
575 +#include <linux/string.h>
576 +#include <linux/platform_device.h>
577 +#include <asm/unaligned.h>
578 +#include <asm/io.h>
579 +
580 +#include <asm/rc32434/rc32434.h>
581 +#include <asm/rc32434/dma.h>
582 +#include <asm/rc32434/dma_v.h>
583 +#include <asm/rc32434/eth.h>
584 +#include <asm/rc32434/rb.h>
585 +
586 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
587 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
588 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
589 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
590 +
591 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
592 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
593 +
594 +static struct resource korina_dev0_res[] = {
595 + {
596 + .name = "korina_regs",
597 + .start = ETH0_PhysicalAddress,
598 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
599 + .flags = IORESOURCE_MEM,
600 + },
601 + {
602 + .name = "korina_rx",
603 + .start = ETH0_DMA_RX_IRQ,
604 + .end = ETH0_DMA_RX_IRQ,
605 + .flags = IORESOURCE_IRQ
606 + },
607 + {
608 + .name = "korina_tx",
609 + .start = ETH0_DMA_TX_IRQ,
610 + .end = ETH0_DMA_TX_IRQ,
611 + .flags = IORESOURCE_IRQ
612 + },
613 + {
614 + .name = "korina_ovr",
615 + .start = ETH0_RX_OVR_IRQ,
616 + .end = ETH0_RX_OVR_IRQ,
617 + .flags = IORESOURCE_IRQ
618 + },
619 + {
620 + .name = "korina_und",
621 + .start = ETH0_TX_UND_IRQ,
622 + .end = ETH0_TX_UND_IRQ,
623 + .flags = IORESOURCE_IRQ
624 + },
625 + {
626 + .name = "korina_dma_rx",
627 + .start = ETH0_RX_DMA_ADDR,
628 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
629 + .flags = IORESOURCE_MEM,
630 + },
631 + {
632 + .name = "korina_dma_tx",
633 + .start = ETH0_TX_DMA_ADDR,
634 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
635 + .flags = IORESOURCE_MEM,
636 + }
637 +};
638 +
639 +static struct korina_device korina_dev0_data = {
640 + .name = "korina0",
641 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
642 +};
643 +
644 +static struct platform_device korina_dev0 = {
645 + .id = 0,
646 + .name = "korina",
647 + .dev.platform_data = &korina_dev0_data,
648 + .resource = korina_dev0_res,
649 + .num_resources = ARRAY_SIZE(korina_dev0_res),
650 +};
651 +
652 +
653 +#define CF_GPIO_NUM 13
654 +
655 +static struct resource cf_slot0_res[] = {
656 + {
657 + .name = "cf_membase",
658 + .flags = IORESOURCE_MEM
659 + },
660 + {
661 + .name = "cf_irq",
662 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
663 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
664 + .flags = IORESOURCE_IRQ
665 + }
666 +};
667 +
668 +static struct cf_device cf_slot0_data = {
669 + .gpio_pin = 13
670 +};
671 +
672 +static struct platform_device cf_slot0 = {
673 + .id = 0,
674 + .name = "rb500-cf",
675 + .dev.platform_data = &cf_slot0_data,
676 + .resource = cf_slot0_res,
677 + .num_resources = ARRAY_SIZE(cf_slot0_res),
678 +};
679 +
680 +
681 +
682 +static struct platform_device *rb500_devs[] = {
683 + &korina_dev0,
684 + &cf_slot0
685 +};
686 +
687 +static void __init parse_mac_addr(char* macstr)
688 +{
689 + int i, j;
690 + unsigned char result, value;
691 +
692 + for (i=0; i<6; i++) {
693 + result = 0;
694 + if (i != 5 && *(macstr+2) != ':') {
695 + return;
696 + }
697 + for (j=0; j<2; j++) {
698 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
699 + toupper(*macstr)-'A'+10) < 16) {
700 + result = result*16 + value;
701 + macstr++;
702 + }
703 + else return;
704 + }
705 +
706 + macstr++;
707 + korina_dev0_data.mac[i] = result;
708 + }
709 +}
710 +
711 +
712 +/* DEVICE CONTROLLER 1 */
713 +#define CFG_DC_DEV1 (void*)0xb8010010
714 +#define CFG_DC_DEVBASE 0x0
715 +#define CFG_DC_DEVMASK 0x4
716 +#define CFG_DC_DEVC 0x8
717 +#define CFG_DC_DEVTC 0xC
718 +
719 +
720 +static int __init plat_setup_devices(void)
721 +{
722 + /* Look for the CF card reader */
723 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
724 + rb500_devs[1] = NULL;
725 + else {
726 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
727 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
728 + }
729 +
730 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
731 +}
732 +
733 +static int __init setup_kmac(char *s)
734 +{
735 + printk("korina mac = %s\n",s);
736 + parse_mac_addr(s);
737 + return 0;
738 +}
739 +
740 +__setup("kmac=", setup_kmac);
741 +arch_initcall(plat_setup_devices);
742 +
743 +
744 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
745 +extern void block2mtd_setup(char *initstr);
746 +extern void mount_devfs_fs(void);
747 +
748 +static int __init setup_mtd(void)
749 +{
750 + struct hd_struct **part;
751 + int num = 0, i;
752 + char initstr[64];
753 +
754 + if (cf_slot0_data.gd == NULL)
755 + return 0;
756 +
757 + /* count partitions */
758 + part = cf_slot0_data.gd->part;
759 + while (part[num] != NULL) {
760 + num++;
761 + }
762 +
763 + if (num < 2)
764 + return 0;
765 +
766 + mount_devfs_fs();
767 + printk("Setting up block2mtd devices\n");
768 +
769 + block2mtd_setup("/dev/cf/card0/part1,131072,kernel");
770 + block2mtd_setup("/dev/cf/card0/part2,131072,rootfs");
771 +
772 + for (i = 2; part[i]; i++) {
773 + sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1);
774 + block2mtd_setup(initstr);
775 + }
776 +
777 + return 0;
778 +}
779 +
780 +late_initcall(setup_mtd);
781 +#endif
782 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
783 --- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
784 +++ linux.dev/arch/mips/rb500/early_serial.c 2006-06-15 16:26:53.000000000 +0200
785 @@ -0,0 +1,199 @@
786 +/**************************************************************************
787 + *
788 + * BRIEF MODULE DESCRIPTION
789 + * EB434 specific polling driver for 16550 UART.
790 + *
791 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
792 + *
793 + * This program is free software; you can redistribute it and/or modify it
794 + * under the terms of the GNU General Public License as published by the
795 + * Free Software Foundation; either version 2 of the License, or (at your
796 + * option) any later version.
797 + *
798 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
799 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
800 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
801 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
802 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
803 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
804 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
805 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
806 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
807 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
808 + *
809 + * You should have received a copy of the GNU General Public License along
810 + * with this program; if not, write to the Free Software Foundation, Inc.,
811 + * 675 Mass Ave, Cambridge, MA 02139, USA.
812 + *
813 + *
814 + **************************************************************************
815 + * Copyright (C) 2000 by Lineo, Inc.
816 + * Written by Quinn Jensen (jensenq@lineo.com)
817 + **************************************************************************
818 + * P. Sadik Oct 20, 2003
819 + *
820 + * DIVISOR is made a function of idt_cpu_freq
821 + **************************************************************************
822 + * P. Sadik Oct 30, 2003
823 + *
824 + * added reset_cons_port
825 + **************************************************************************
826 + */
827 +
828 +#include <linux/serial_reg.h>
829 +
830 +/* turn this on to watch the debug protocol echoed on the console port */
831 +#define DEBUG_REMOTE_DEBUG
832 +
833 +#define CONS_BAUD 115200
834 +
835 +extern unsigned int idt_cpu_freq;
836 +
837 +#define EXT_FREQ 24000000
838 +#define INT_FREQ idt_cpu_freq
839 +
840 +#define EXT_PORT 0xb9800000u
841 +#define EXT_SHIFT 0
842 +
843 +#ifdef __MIPSEB__
844 +#define INT_PORT 0xb8058003u
845 +#else
846 +#define INT_PORT 0xb8058000u
847 +#endif
848 +#define INT_SHIFT 2
849 +
850 +#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
851 +#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
852 +
853 +typedef struct
854 +{
855 + volatile unsigned char *base;
856 + unsigned int shift;
857 + unsigned int freq;
858 + unsigned int fcr;
859 +} ser_port;
860 +
861 +ser_port ports[2] =
862 +{
863 + { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
864 + { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
865 +};
866 +
867 +#define CONS_PORT 0
868 +
869 +void cons_putc(char c);
870 +int port_getc(int port);
871 +void port_putc(int port, char c);
872 +
873 +int cons_getc(void)
874 +{
875 + return port_getc(CONS_PORT);
876 +}
877 +
878 +void cons_putc(char c)
879 +{
880 + port_putc(CONS_PORT, c);
881 +}
882 +
883 +void cons_puts(char *s)
884 +{
885 + while(*s) {
886 + if(*s == '\n') cons_putc('\r');
887 + cons_putc(*s);
888 + s++;
889 + }
890 +}
891 +
892 +void cons_do_putn(int n)
893 +{
894 + if(n) {
895 + cons_do_putn(n / 10);
896 + cons_putc(n % 10 + '0');
897 + }
898 +}
899 +
900 +void cons_putn(int n)
901 +{
902 + if(n < 0) {
903 + cons_putc('-');
904 + n = -n;
905 + }
906 +
907 + if (n == 0) {
908 + cons_putc('0');
909 + } else {
910 + cons_do_putn(n);
911 + }
912 +}
913 +
914 +int port_getc(int p)
915 +{
916 + volatile unsigned char *port = ports[p].base;
917 + int s = ports[p].shift;
918 + int c;
919 +
920 + while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
921 + continue;
922 + }
923 +
924 + c = *(port + (UART_RX << s));
925 +
926 + return c;
927 +}
928 +
929 +int port_getc_ready(int p)
930 +{
931 + volatile unsigned char *port = ports[p].base;
932 + int s = ports[p].shift;
933 +
934 + return *(port + (UART_LSR << s)) & UART_LSR_DR;
935 +}
936 +
937 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
938 +
939 +void port_putc(int p, char c)
940 +{
941 + volatile unsigned char *port = ports[p].base;
942 + int s = ports[p].shift;
943 + volatile unsigned char *lsr = port + (UART_LSR << s);
944 +
945 + while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
946 + continue;
947 + }
948 +
949 + *(port + (UART_TX << s)) = c;
950 +}
951 +
952 +void reset_cons_port(void)
953 +{
954 + volatile unsigned char *port = ports[CONS_PORT].base;
955 + unsigned int s = ports[CONS_PORT].shift;
956 + unsigned int DIVISOR;
957 +
958 + if (ports[CONS_PORT].freq)
959 + DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
960 + else
961 + DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
962 +
963 + /* reset the port */
964 + *(port + (UART_CSR << s)) = 0;
965 +
966 + /* clear and enable the FIFOs */
967 + *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
968 +
969 + /* set the baud rate */
970 + *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
971 +
972 + *(port + (UART_DLL << s)) = DIVISOR;
973 + *(port + (UART_DLM << s)) = DIVISOR >> 8;
974 + /* set the line control stuff and disable DLL, DLM regs */
975 +
976 + *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
977 + UART_LCR_WLEN8; /* 8 bit word length */
978 +
979 + /* leave interrupts off */
980 + *(port + (UART_IER << s)) = 0;
981 +
982 + /* the modem controls don't leave the chip on this port, so leave them alone */
983 + *(port + (UART_MCR << s)) = 0;
984 +}
985 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
986 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
987 +++ linux.dev/arch/mips/rb500/irq.c 2006-06-15 16:26:53.000000000 +0200
988 @@ -0,0 +1,266 @@
989 +/*
990 + * BRIEF MODULE DESCRIPTION
991 + * RC32434 interrupt routines.
992 + *
993 + * Copyright 2002 MontaVista Software Inc.
994 + * Author: MontaVista Software, Inc.
995 + * stevel@mvista.com or source@mvista.com
996 + *
997 + * This program is free software; you can redistribute it and/or modify it
998 + * under the terms of the GNU General Public License as published by the
999 + * Free Software Foundation; either version 2 of the License, or (at your
1000 + * option) any later version.
1001 + *
1002 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1003 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1004 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1005 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1006 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1007 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1008 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1009 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1010 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1011 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1012 + *
1013 + * You should have received a copy of the GNU General Public License along
1014 + * with this program; if not, write to the Free Software Foundation, Inc.,
1015 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1016 + */
1017 +
1018 +#include <linux/errno.h>
1019 +#include <linux/init.h>
1020 +#include <linux/kernel_stat.h>
1021 +#include <linux/module.h>
1022 +#include <linux/signal.h>
1023 +#include <linux/sched.h>
1024 +#include <linux/types.h>
1025 +#include <linux/interrupt.h>
1026 +#include <linux/ioport.h>
1027 +#include <linux/timex.h>
1028 +#include <linux/slab.h>
1029 +#include <linux/random.h>
1030 +#include <linux/delay.h>
1031 +
1032 +#include <asm/bitops.h>
1033 +#include <asm/bootinfo.h>
1034 +#include <asm/io.h>
1035 +#include <asm/irq.h>
1036 +#include <asm/time.h>
1037 +#include <asm/mipsregs.h>
1038 +#include <asm/system.h>
1039 +#include <asm/rc32434/rc32434.h>
1040 +#include <asm/rc32434/gpio.h>
1041 +
1042 +extern void set_debug_traps(void);
1043 +extern irq_cpustat_t irq_stat [NR_CPUS];
1044 +unsigned int local_bh_count[NR_CPUS];
1045 +unsigned int local_irq_count[NR_CPUS];
1046 +
1047 +static unsigned int startup_irq(unsigned int irq);
1048 +static void rb500_end_irq(unsigned int irq_nr);
1049 +static void mask_and_ack_irq(unsigned int irq_nr);
1050 +static void rb500_enable_irq(unsigned int irq_nr);
1051 +static void rb500_disable_irq(unsigned int irq_nr);
1052 +
1053 +extern void __init init_generic_irq(void);
1054 +
1055 +typedef struct {
1056 + u32 mask; /* mask of valid bits in pending/mask registers */
1057 + volatile u32 *base_addr;
1058 +} intr_group_t;
1059 +
1060 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
1061 +
1062 +#if (NR_IRQS < RC32434_NR_IRQS)
1063 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1064 +#endif
1065 +
1066 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1067 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1068 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1069 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1070 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1071 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1072 +};
1073 +
1074 +#define READ_PEND(base) (*(base))
1075 +#define READ_MASK(base) (*(base + 2))
1076 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1077 +
1078 +static inline int irq_to_group(unsigned int irq_nr)
1079 +{
1080 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1081 +}
1082 +
1083 +static inline int group_to_ip(unsigned int group)
1084 +{
1085 + return group + 2;
1086 +}
1087 +
1088 +static inline void enable_local_irq(unsigned int ip)
1089 +{
1090 + int ipnum = 0x100 << ip;
1091 + clear_c0_cause(ipnum);
1092 + set_c0_status(ipnum);
1093 +}
1094 +
1095 +static inline void disable_local_irq(unsigned int ip)
1096 +{
1097 + int ipnum = 0x100 << ip;
1098 + clear_c0_status(ipnum);
1099 +}
1100 +
1101 +static inline void ack_local_irq(unsigned int ip)
1102 +{
1103 + int ipnum = 0x100 << ip;
1104 + clear_c0_cause(ipnum);
1105 +}
1106 +
1107 +static void rb500_enable_irq(unsigned int irq_nr)
1108 +{
1109 + int ip = irq_nr - GROUP0_IRQ_BASE;
1110 + unsigned int group, intr_bit;
1111 + volatile unsigned int *addr;
1112 +
1113 +
1114 + if (ip < 0)
1115 + enable_local_irq(irq_nr);
1116 + else {
1117 + group = ip >> 5;
1118 +
1119 + ip &= (1<<5)-1;
1120 + intr_bit = 1 << ip;
1121 +
1122 + enable_local_irq(group_to_ip(group));
1123 +
1124 + addr = intr_group[group].base_addr;
1125 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1126 + }
1127 +}
1128 +
1129 +static void rb500_disable_irq(unsigned int irq_nr)
1130 +{
1131 + int ip = irq_nr - GROUP0_IRQ_BASE;
1132 + unsigned int group, intr_bit, mask;
1133 + volatile unsigned int *addr;
1134 +
1135 + if (ip < 0) {
1136 + disable_local_irq(irq_nr);
1137 + }else{
1138 + group = ip >> 5;
1139 +
1140 + ip &= (1<<5) -1;
1141 + intr_bit = 1 << ip;
1142 + addr = intr_group[group].base_addr;
1143 + mask = READ_MASK(addr);
1144 + mask |= intr_bit;
1145 + WRITE_MASK(addr,mask);
1146 +
1147 + /*
1148 + * if there are no more interrupts enabled in this
1149 + * group, disable corresponding IP
1150 + */
1151 + if (mask == intr_group[group].mask)
1152 + disable_local_irq(group_to_ip(group));
1153 + }
1154 +}
1155 +
1156 +static unsigned int startup_irq(unsigned int irq_nr)
1157 +{
1158 + rb500_enable_irq(irq_nr);
1159 + return 0;
1160 +}
1161 +
1162 +static void shutdown_irq(unsigned int irq_nr)
1163 +{
1164 + rb500_disable_irq(irq_nr);
1165 + return;
1166 +}
1167 +
1168 +static void mask_and_ack_irq(unsigned int irq_nr)
1169 +{
1170 + rb500_disable_irq(irq_nr);
1171 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1172 +}
1173 +
1174 +static void rb500_end_irq(unsigned int irq_nr)
1175 +{
1176 +
1177 + int ip = irq_nr - GROUP0_IRQ_BASE;
1178 + unsigned int intr_bit, group;
1179 + volatile unsigned int *addr;
1180 +
1181 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1182 + printk("warning: end_irq %d did not enable (%x)\n",
1183 + irq_nr, irq_desc[irq_nr].status);
1184 + return;
1185 + }
1186 +
1187 + if (ip < 0) {
1188 + enable_local_irq(irq_nr);
1189 + } else {
1190 + group = ip >> 5;
1191 +
1192 + ip &= (1 << 5) - 1;
1193 + intr_bit = 1 << ip;
1194 +
1195 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1196 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1197 + }
1198 +
1199 + enable_local_irq(group_to_ip(group));
1200 +
1201 + addr = intr_group[group].base_addr;
1202 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1203 + }
1204 +}
1205 +
1206 +static struct hw_interrupt_type rc32434_irq_type = {
1207 + .typename = "RB500",
1208 + .startup = startup_irq,
1209 + .shutdown = shutdown_irq,
1210 + .enable = rb500_enable_irq,
1211 + .disable = rb500_disable_irq,
1212 + .ack = mask_and_ack_irq,
1213 + .end = rb500_end_irq,
1214 +};
1215 +
1216 +
1217 +/* Main Interrupt dispatcher */
1218 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1219 +{
1220 + unsigned int ip, pend, group;
1221 + volatile unsigned int *addr;
1222 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1223 +
1224 + if ((ip = (cp0_cause & 0x7c00))) {
1225 + group = 21 - rc32434_clz(ip);
1226 +
1227 + addr = intr_group[group].base_addr;
1228 +
1229 + pend = READ_PEND(addr);
1230 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1231 + pend = 39 - rc32434_clz(pend);
1232 + do_IRQ((group << 5) + pend, regs);
1233 + }
1234 +}
1235 +
1236 +void __init arch_init_irq(void)
1237 +{
1238 + int i;
1239 + extern void rbIRQ(void);
1240 +
1241 + set_except_vector(0, rbIRQ);
1242 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1243 + memset(irq_desc, 0, sizeof(irq_desc));
1244 +
1245 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1246 + irq_desc[i].status = IRQ_DISABLED;
1247 + irq_desc[i].action = NULL;
1248 + irq_desc[i].depth = 1;
1249 + irq_desc[i].handler = &rc32434_irq_type;
1250 + spin_lock_init(&irq_desc[i].lock);
1251 + }
1252 +}
1253 +
1254 +
1255 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1256 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1257 +++ linux.dev/arch/mips/rb500/Makefile 2006-06-15 16:26:53.000000000 +0200
1258 @@ -0,0 +1,5 @@
1259 +#
1260 +# Makefile for the RB500 board specific parts of the kernel
1261 +#
1262 +
1263 +obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o rbIRQ.o
1264 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1265 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1266 +++ linux.dev/arch/mips/rb500/misc.c 2006-06-15 16:26:53.000000000 +0200
1267 @@ -0,0 +1,54 @@
1268 +#include <linux/module.h>
1269 +#include <linux/kernel.h> /* printk() */
1270 +#include <linux/types.h> /* size_t */
1271 +#include <linux/pci.h>
1272 +#include <linux/spinlock.h>
1273 +#include <asm/rc32434/rb.h>
1274 +
1275 +#define GPIO_BADDR 0xb8050000
1276 +
1277 +
1278 +static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030);
1279 +static unsigned char latchU5State = 0;
1280 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1281 +
1282 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1283 + unsigned flags, data;
1284 + unsigned i = 0;
1285 + spin_lock_irqsave(&clu5Lock, flags);
1286 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1287 + for (i = 0; i != len; ++i) {
1288 + if (val & (1 << i)) data |= (1 << (i + bit));
1289 + else data &= ~(1 << (i + bit));
1290 + }
1291 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1292 + spin_unlock_irqrestore(&clu5Lock, flags);
1293 +}
1294 +
1295 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1296 + unsigned flags;
1297 + spin_lock_irqsave(&clu5Lock, flags);
1298 + latchU5State = (latchU5State | orMask) & ~nandMask;
1299 + *devCtl3Base = latchU5State;
1300 + spin_unlock_irqrestore(&clu5Lock, flags);
1301 +}
1302 +
1303 +u32 gpio_get(gpio_func func)
1304 +{
1305 + return readl((void *) GPIO_BADDR + func);
1306 +}
1307 +
1308 +void gpio_set(gpio_func func, u32 mask, u32 value)
1309 +{
1310 + u32 val = readl((void *) GPIO_BADDR + func);
1311 +
1312 + val &= ~mask;
1313 + val |= value & mask;
1314 +
1315 + writel(val, (void *) GPIO_BADDR + func);
1316 +}
1317 +
1318 +EXPORT_SYMBOL(gpio_set);
1319 +EXPORT_SYMBOL(gpio_get);
1320 +EXPORT_SYMBOL(set434Reg);
1321 +EXPORT_SYMBOL(changeLatchU5);
1322 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1323 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1324 +++ linux.dev/arch/mips/rb500/prom.c 2006-06-15 16:26:53.000000000 +0200
1325 @@ -0,0 +1,181 @@
1326 +/*
1327 +* prom.c
1328 +**********************************************************************
1329 +* P . Sadik Oct 10, 2003
1330 +*
1331 +* Started change log
1332 +* idt_cpu_freq is make a kernel configuration parameter
1333 +* idt_cpu_freq is exported so that other modules can use it.
1334 +* Code cleanup
1335 +**********************************************************************
1336 +* P. Sadik Oct 20, 2003
1337 +*
1338 +* Removed NVRAM code from here, since they are already available under
1339 +* nvram directory.
1340 +* Added serial port initialisation.
1341 +**********************************************************************
1342 +**********************************************************************
1343 +* P. Sadik Oct 30, 2003
1344 +*
1345 +* Added reset_cons_port
1346 +**********************************************************************
1347 +
1348 + P.Christeas, 2005-2006
1349 + Port to 2.6, add 2.6 cmdline parsing
1350 +
1351 +*/
1352 +
1353 +#include <linux/config.h>
1354 +#include <linux/init.h>
1355 +#include <linux/mm.h>
1356 +#include <linux/module.h>
1357 +#include <linux/string.h>
1358 +#include <linux/console.h>
1359 +#include <asm/bootinfo.h>
1360 +#include <linux/bootmem.h>
1361 +#include <linux/ioport.h>
1362 +#include <linux/blkdev.h>
1363 +#include <asm/rc32434/ddr.h>
1364 +
1365 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1366 +extern void __init setup_serial_port(void);
1367 +extern void cons_putc(char c);
1368 +extern void cons_puts(char *s);
1369 +
1370 +unsigned int idt_cpu_freq = 132000000;
1371 +EXPORT_SYMBOL(idt_cpu_freq);
1372 +unsigned int board_type = 500;
1373 +EXPORT_SYMBOL(board_type);
1374 +unsigned int gpio_bootup_state = 0;
1375 +EXPORT_SYMBOL(gpio_bootup_state);
1376 +
1377 +
1378 +char mips_mac_address[18] = "08:00:06:05:40:01";
1379 +EXPORT_SYMBOL(mips_mac_address);
1380 +
1381 +/* what to append to cmdline when button is [not] pressed */
1382 +#define GPIO_INIT_NOBUTTON ""
1383 +#define GPIO_INIT_BUTTON " 2"
1384 +
1385 +#ifdef CONFIG_MIKROTIK_RB500
1386 +unsigned soft_reboot = 0;
1387 +EXPORT_SYMBOL(soft_reboot);
1388 +#endif
1389 +
1390 +#define SR_NMI 0x00180000 /* NMI */
1391 +#define SERIAL_SPEED_ENTRY 0x00000001
1392 +
1393 +#ifdef CONFIG_REMOTE_DEBUG
1394 +extern int remote_debug;
1395 +#endif
1396 +
1397 +extern unsigned long mips_machgroup;
1398 +extern unsigned long mips_machtype;
1399 +
1400 +#define FREQ_TAG "HZ="
1401 +#define GPIO_TAG "gpio="
1402 +#define KMAC_TAG "kmac="
1403 +#define MEM_TAG "mem="
1404 +#define BOARD_TAG "board="
1405 +#define IGNORE_CMDLINE_MEM 1
1406 +#define DEBUG_DDR
1407 +
1408 +void parse_soft_settings(unsigned *ptr, unsigned size);
1409 +void parse_hard_settings(unsigned *ptr, unsigned size);
1410 +
1411 +void __init prom_setup_cmdline(void);
1412 +
1413 +#ifdef DEBUG_DDR
1414 +void cons_puthex4(u32 h){
1415 + h&=0x0f;
1416 + if (h>=10)
1417 + cons_putc((h-10)+'a');
1418 + else
1419 + cons_putc(h+'0');
1420 +}
1421 +
1422 +void cons_putreg32(u32 reg){
1423 + char c;
1424 + cons_putc('0');
1425 + cons_putc('x');
1426 + for (c=28;c>=0;c-=4)
1427 + cons_puthex4(reg>>c);
1428 +}
1429 +#endif
1430 +
1431 +void __init prom_init(void)
1432 +{
1433 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1434 + phys_t memsize = 0-ddr->ddrmask;
1435 +
1436 + /* this should be the very first message, even before serial is properly initialized */
1437 + prom_setup_cmdline();
1438 + setup_serial_port();
1439 +
1440 + mips_machgroup = MACH_GROUP_MIKROTIK;
1441 + soft_reboot = read_c0_status() & SR_NMI;
1442 + pm_power_off = NULL;
1443 +
1444 + /*
1445 + * give all RAM to boot allocator,
1446 + * except for the first 0x400 and the last 0x200 bytes
1447 + */
1448 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1449 +}
1450 +
1451 +void prom_free_prom_memory(void)
1452 +{
1453 + /* FIXME: STUB */
1454 +}
1455 +
1456 +void __init prom_setup_cmdline(void){
1457 + char cmd_line[CL_SIZE];
1458 + char *cp;
1459 + int prom_argc;
1460 + char **prom_argv, **prom_envp;
1461 + int i;
1462 +
1463 + prom_argc = fw_arg0;
1464 + prom_argv = (char **) fw_arg1;
1465 + prom_envp = (char **) fw_arg2;
1466 +
1467 + cp=cmd_line;
1468 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1469 + however, our elf loader starts at [0] */
1470 + for(i=0;i<prom_argc;i++){
1471 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1472 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1473 + continue;
1474 + }
1475 +#ifdef IGNORE_CMDLINE_MEM
1476 + /* parses out the "mem=xx" arg */
1477 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1478 + continue;
1479 + }
1480 +#endif
1481 + if (i>0) *(cp++) = ' ';
1482 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1483 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1484 + }
1485 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1486 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1487 + }
1488 + strcpy(cp,prom_argv[i]);
1489 + cp+=strlen(prom_argv[i]);
1490 + }
1491 +
1492 + i=strlen(arcs_cmdline);
1493 + if (i>0){
1494 + *(cp++) = ' ';
1495 + strcpy(cp,arcs_cmdline);
1496 + cp+=strlen(arcs_cmdline);
1497 + }
1498 + if (gpio_bootup_state&0x02)
1499 + strcpy(cp,GPIO_INIT_NOBUTTON);
1500 + else
1501 + strcpy(cp,GPIO_INIT_BUTTON);
1502 + cmd_line[CL_SIZE-1] = '\0';
1503 +
1504 + strcpy(arcs_cmdline,cmd_line);
1505 +}
1506 +
1507 diff -urN linux.old/arch/mips/rb500/rbIRQ.S linux.dev/arch/mips/rb500/rbIRQ.S
1508 --- linux.old/arch/mips/rb500/rbIRQ.S 1970-01-01 01:00:00.000000000 +0100
1509 +++ linux.dev/arch/mips/rb500/rbIRQ.S 2006-06-15 16:26:53.000000000 +0200
1510 @@ -0,0 +1,62 @@
1511 +/*
1512 + * Copyright 2001 MontaVista Software Inc.
1513 + * Author: stevel@mvista.com
1514 + *
1515 + * Interrupt dispatcher for RB500 board.
1516 + *
1517 + * This program is free software; you can redistribute it and/or modify it
1518 + * under the terms of the GNU General Public License as published by the
1519 + * Free Software Foundation; either version 2 of the License, or (at your
1520 + * option) any later version.
1521 + */
1522 +
1523 +#define __ASSEMBLY__ 1
1524 +
1525 +#include <asm/asm.h>
1526 +#include <asm/mipsregs.h>
1527 +#include <asm/regdef.h>
1528 +#include <asm/stackframe.h>
1529 +
1530 + .text
1531 + .set noreorder
1532 + .set noat
1533 + .align 5
1534 + NESTED(rbIRQ, PT_SIZE, sp)
1535 + .set noat
1536 + SAVE_ALL
1537 + CLI
1538 +
1539 + .set at
1540 + .set noreorder
1541 +
1542 + /* Get the pending interrupts */
1543 + mfc0 t0, CP0_CAUSE
1544 + nop
1545 +
1546 + /* Isolate the allowed ones by anding the irq mask */
1547 + mfc0 t2, CP0_STATUS
1548 + move a1, sp /* need a nop here, hence we anticipate */
1549 + andi t0, CAUSEF_IP
1550 + and t0, t2
1551 +
1552 + /* check for r4k counter/timer IRQ. */
1553 +
1554 + andi t1, t0, CAUSEF_IP7
1555 + beqz t1, 1f
1556 + nop
1557 +
1558 + jal ll_timer_interrupt
1559 +
1560 + li a0, 7
1561 +
1562 + j ret_from_irq
1563 + nop
1564 +1:
1565 + jal plat_irq_dispatch
1566 + move a0, t0
1567 + j ret_from_irq
1568 + nop
1569 +
1570 + END(rbIRQ)
1571 +
1572 +
1573 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1574 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1575 +++ linux.dev/arch/mips/rb500/serial.c 2006-06-15 16:26:53.000000000 +0200
1576 @@ -0,0 +1,79 @@
1577 +/**************************************************************************
1578 + *
1579 + * BRIEF MODULE DESCRIPTION
1580 + * Serial port initialisation.
1581 + *
1582 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1583 + *
1584 + * This program is free software; you can redistribute it and/or modify it
1585 + * under the terms of the GNU General Public License as published by the
1586 + * Free Software Foundation; either version 2 of the License, or (at your
1587 + * option) any later version.
1588 + *
1589 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1590 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1591 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1592 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1593 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1594 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1595 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1596 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1597 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1598 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1599 + *
1600 + * You should have received a copy of the GNU General Public License along
1601 + * with this program; if not, write to the Free Software Foundation, Inc.,
1602 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1603 + *
1604 + *
1605 + **************************************************************************
1606 + * May 2004 rkt, neb
1607 + *
1608 + * Initial Release
1609 + *
1610 + *
1611 + *
1612 + **************************************************************************
1613 + */
1614 +
1615 +
1616 +#include <linux/config.h>
1617 +#include <linux/init.h>
1618 +#include <linux/sched.h>
1619 +#include <linux/pci.h>
1620 +#include <linux/interrupt.h>
1621 +#include <linux/tty.h>
1622 +#include <linux/serial.h>
1623 +#include <linux/serial_core.h>
1624 +
1625 +#include <asm/time.h>
1626 +#include <asm/cpu.h>
1627 +#include <asm/bootinfo.h>
1628 +#include <asm/irq.h>
1629 +#include <asm/serial.h>
1630 +#include <asm/rc32434/rc32434.h>
1631 +
1632 +extern unsigned int idt_cpu_freq;
1633 +
1634 +static struct uart_port serial_req = {
1635 + .type = PORT_16550A,
1636 + .line = 0,
1637 + .irq = RC32434_UART0_IRQ,
1638 + .flags = STD_COM_FLAGS,
1639 + .iotype = UPIO_MEM,
1640 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1641 +// .fifosize = 14
1642 + .regshift = 2
1643 +};
1644 +
1645 +int __init setup_serial_port(void)
1646 +{
1647 + serial_req.uartclk = idt_cpu_freq;
1648 +
1649 + if (early_serial_setup(&serial_req)){
1650 + cons_puts("Serial setup failed!\n");
1651 + return -ENODEV;
1652 + }
1653 +
1654 + return(0);
1655 +}
1656 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1657 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1658 +++ linux.dev/arch/mips/rb500/setup.c 2006-06-15 16:26:53.000000000 +0200
1659 @@ -0,0 +1,84 @@
1660 +/*
1661 + * setup.c - boot time setup code
1662 + */
1663 +
1664 +#include <linux/init.h>
1665 +#include <linux/mm.h>
1666 +#include <linux/sched.h>
1667 +#include <linux/irq.h>
1668 +#include <asm/bootinfo.h>
1669 +#include <asm/io.h>
1670 +#include <linux/ioport.h>
1671 +#include <asm/mipsregs.h>
1672 +#include <asm/pgtable.h>
1673 +#include <asm/reboot.h>
1674 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1675 +#include <asm/rc32434/rc32434.h>
1676 +#include <linux/pm.h>
1677 +#include <asm/rc32434/pci.h>
1678 +
1679 +extern void (*board_time_init)(void);
1680 +extern void (*board_timer_setup)(struct irqaction *irq);
1681 +extern void rc32434_time_init(void);
1682 +extern void rc32434_timer_setup(struct irqaction *irq);
1683 +#ifdef CONFIG_PCI
1684 +extern int __init rc32434_pcibridge_init(void);
1685 +#endif
1686 +
1687 +#define epldMask ((volatile unsigned char *)0xB900000d)
1688 +
1689 +static void rb_machine_restart(char *command)
1690 +{
1691 + /* just jump to the reset vector */
1692 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1693 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1694 +}
1695 +
1696 +static void rb_machine_halt(void)
1697 +{
1698 + for(;;) continue;
1699 +}
1700 +
1701 +#ifdef CONFIG_CPU_HAS_WB
1702 +void (*__wbflush) (void);
1703 +
1704 +static void rb_write_buffer_flush(void)
1705 +{
1706 + __asm__ __volatile__
1707 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1708 +}
1709 +#endif
1710 +
1711 +void __init plat_setup(void)
1712 +{
1713 + unsigned int pciCntlVal;
1714 +
1715 + board_time_init = rc32434_time_init;
1716 + board_timer_setup = rc32434_timer_setup;
1717 +
1718 +#ifdef CONFIG_CPU_HAS_WB
1719 + __wbflush = rb_write_buffer_flush;
1720 +#endif
1721 + _machine_restart = rb_machine_restart;
1722 + _machine_halt = rb_machine_halt;
1723 + /*_machine_power_off = rb_machine_power_halt;*/
1724 + pm_power_off = rb_machine_halt;
1725 +
1726 + set_io_port_base(KSEG1);
1727 +
1728 + pciCntlVal=rc32434_pci->pcic;
1729 + pciCntlVal &= 0xFFFFFF7;
1730 + rc32434_pci->pcic = pciCntlVal;
1731 +
1732 +#ifdef CONFIG_PCI
1733 + /* Enable PCI interrupts in EPLD Mask register */
1734 + *epldMask = 0x0;
1735 + *(epldMask + 1) = 0x0;
1736 +#endif
1737 + write_c0_wired(0);
1738 +}
1739 +
1740 +const char *get_system_type(void)
1741 +{
1742 + return "MIPS RB500";
1743 +}
1744 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1745 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1746 +++ linux.dev/arch/mips/rb500/time.c 2006-06-15 16:26:53.000000000 +0200
1747 @@ -0,0 +1,94 @@
1748 +/*
1749 +****************************************************************************
1750 +* Carsten Langgaard, carstenl@mips.com
1751 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1752 +*
1753 +***************************************************************************
1754 +*
1755 +* This program is free software; you can distribute it and/or modify it
1756 +* under the terms of the GNU General Public License (Version 2) as
1757 +* published by the Free Software Foundation.
1758 +*
1759 +* This program is distributed in the hope it will be useful, but WITHOUT
1760 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1761 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1762 +* for more details.
1763 +*
1764 +* You should have received a copy of the GNU General Public License along
1765 +* with this program; if not, write to the Free Software Foundation, Inc.,
1766 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1767 +*
1768 +****************************************************************************
1769 +*
1770 +* Setting up the clock on the MIPS boards.
1771 +*
1772 +****************************************************************************
1773 +* P. Sadik Oct 10, 2003
1774 +*
1775 +* Started change log.
1776 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1777 +* Code cleanup
1778 +****************************************************************************
1779 +*/
1780 +
1781 +#include <linux/config.h>
1782 +#include <linux/init.h>
1783 +#include <linux/kernel_stat.h>
1784 +#include <linux/sched.h>
1785 +#include <linux/spinlock.h>
1786 +#include <linux/mc146818rtc.h>
1787 +#include <linux/irq.h>
1788 +#include <linux/timex.h>
1789 +
1790 +#include <asm/mipsregs.h>
1791 +#include <asm/ptrace.h>
1792 +#include <asm/debug.h>
1793 +#include <asm/rc32434/rc32434.h>
1794 +
1795 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1796 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1797 +extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
1798 +extern unsigned int mips_hpt_frequency;
1799 +extern unsigned int idt_cpu_freq;
1800 +
1801 +/*
1802 + * Figure out the r4k offset, the amount to increment the compare
1803 + * register for each time tick. There is no RTC available.
1804 + *
1805 + * The RC32434 counts at half the CPU *core* speed.
1806 + */
1807 +static unsigned long __init cal_r4koff(void)
1808 +{
1809 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1810 + return (mips_hpt_frequency / HZ);
1811 +}
1812 +
1813 +
1814 +void __init rc32434_time_init(void)
1815 +{
1816 + unsigned int est_freq, flags;
1817 +
1818 + local_irq_save(flags);
1819 +
1820 + printk("calculating r4koff... ");
1821 + r4k_offset = cal_r4koff();
1822 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1823 +
1824 + est_freq = 2*r4k_offset*HZ;
1825 + est_freq += 5000; /* round */
1826 + est_freq -= est_freq%10000;
1827 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1828 + (est_freq%1000000)*100/1000000);
1829 + local_irq_restore(flags);
1830 +}
1831 +
1832 +void __init rc32434_timer_setup(struct irqaction *irq)
1833 +{
1834 + /* we are using the cpu counter for timer interrupts */
1835 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1836 +
1837 + /* to generate the first timer interrupt */
1838 + r4k_cur = (read_c0_count() + r4k_offset);
1839 + write_c0_compare(r4k_cur);
1840 +}
1841 +
1842 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1843 --- linux.old/drivers/mtd/devices/block2mtd.c 2006-05-31 02:31:44.000000000 +0200
1844 +++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-06-15 18:46:28.000000000 +0200
1845 @@ -25,7 +25,6 @@
1846 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1847 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1848
1849 -
1850 /* Info for the block device */
1851 struct block2mtd_dev {
1852 struct list_head list;
1853 @@ -61,10 +60,8 @@
1854 read_lock_irq(&mapping->tree_lock);
1855 for (i = 0; i < PAGE_READAHEAD; i++) {
1856 pagei = index + i;
1857 - if (pagei > end_index) {
1858 - INFO("Overrun end of disk in cache readahead\n");
1859 + if (pagei > end_index)
1860 break;
1861 - }
1862 page = radix_tree_lookup(&mapping->page_tree, pagei);
1863 if (page && (!i))
1864 break;
1865 @@ -105,7 +102,7 @@
1866
1867 while (pages) {
1868 page = page_readahead(mapping, index);
1869 - if (!page)
1870 + if (!page || !page_address(page))
1871 return -ENOMEM;
1872 if (IS_ERR(page))
1873 return PTR_ERR(page);
1874 @@ -284,7 +281,7 @@
1875
1876
1877 /* FIXME: ensure that mtd->size % erase_size == 0 */
1878 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1879 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1880 {
1881 struct block_device *bdev;
1882 struct block2mtd_dev *dev;
1883 @@ -314,14 +311,15 @@
1884
1885 /* Setup the MTD structure */
1886 /* make the name contain the block device in */
1887 - dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1888 + dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1889 GFP_KERNEL);
1890 if (!dev->mtd.name)
1891 goto devinit_err;
1892
1893 - sprintf(dev->mtd.name, "block2mtd: %s", devname);
1894 + strcpy(dev->mtd.name, (alias ?: devname));
1895
1896 dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1897 + dev->mtd.size -= dev->mtd.size % erase_size;
1898 dev->mtd.erasesize = erase_size;
1899 dev->mtd.type = MTD_RAM;
1900 dev->mtd.flags = MTD_CAP_RAM;
1901 @@ -340,7 +338,7 @@
1902 }
1903 list_add(&dev->list, &blkmtd_device_list);
1904 INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1905 - dev->mtd.name + strlen("blkmtd: "),
1906 + dev->mtd.name,
1907 dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1908 return dev;
1909
1910 @@ -415,7 +413,7 @@
1911 return 0; \
1912 } while (0)
1913
1914 -static int block2mtd_setup(const char *val, struct kernel_param *kp)
1915 +int block2mtd_setup(const char *val, struct kernel_param *kp)
1916 {
1917 char buf[80+12], *str=buf; /* 80 for device, 12 for erase size */
1918 char *token[2];
1919 @@ -429,7 +427,7 @@
1920 strcpy(str, val);
1921 kill_final_newline(str);
1922
1923 - for (i=0; i<2; i++)
1924 + for (i=0; i<3; i++)
1925 token[i] = strsep(&str, ",");
1926
1927 if (str)
1928 @@ -452,7 +450,7 @@
1929 parse_err("illegal erase size");
1930 }
1931
1932 - add_device(name, erase_size);
1933 + add_device(name, erase_size, token[2]);
1934
1935 return 0;
1936 }
1937 @@ -460,6 +458,7 @@
1938
1939 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1940 MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1941 +EXPORT_SYMBOL(block2mtd_setup);
1942
1943 static int __init block2mtd_init(void)
1944 {
1945 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1946 --- linux.old/drivers/pci/Makefile 2006-06-08 20:21:20.000000000 +0200
1947 +++ linux.dev/drivers/pci/Makefile 2006-06-15 16:26:53.000000000 +0200
1948 @@ -27,6 +27,7 @@
1949 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
1950 obj-$(CONFIG_X86_VISWS) += setup-irq.o
1951 obj-$(CONFIG_PCI_MSI) += msi.o
1952 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1953
1954 #
1955 # ACPI Related PCI FW Functions
1956 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1957 --- linux.old/include/asm-mips/bootinfo.h 2006-06-08 20:21:20.000000000 +0200
1958 +++ linux.dev/include/asm-mips/bootinfo.h 2006-06-15 16:26:53.000000000 +0200
1959 @@ -218,6 +218,8 @@
1960 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
1961 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
1962
1963 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1964 +
1965 #define CL_SIZE COMMAND_LINE_SIZE
1966
1967 const char *get_system_type(void);
1968 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1969 --- linux.old/include/asm-mips/cpu.h 2006-06-08 20:21:20.000000000 +0200
1970 +++ linux.dev/include/asm-mips/cpu.h 2006-06-15 16:26:53.000000000 +0200
1971 @@ -196,7 +196,8 @@
1972 #define CPU_34K 60
1973 #define CPU_PR4450 61
1974 #define CPU_SB1A 62
1975 -#define CPU_LAST 62
1976 +#define CPU_RC32300 63
1977 +#define CPU_LAST 63
1978
1979 /*
1980 * ISA Level encodings
1981 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1982 --- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
1983 +++ linux.dev/include/asm-mips/rc32434/crom.h 2006-06-15 16:26:53.000000000 +0200
1984 @@ -0,0 +1,98 @@
1985 +#ifndef __IDT_CROM_H__
1986 +#define __IDT_CROM_H__
1987 +
1988 +/*******************************************************************************
1989 + *
1990 + * Copyright 2002 Integrated Device Technology, Inc.
1991 + * All rights reserved.
1992 + *
1993 + * Configuration ROM register definitions.
1994 + *
1995 + * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1996 + *
1997 + * Author : Allen.Stichter@idt.com
1998 + * Date : 20020118
1999 + * Update :
2000 + * $Log: crom.h,v $
2001 + * Revision 1.2 2002/06/06 18:34:03 astichte
2002 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2003 + *
2004 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2005 + * jba File moved from vcode/include/idt/acacia
2006 + *
2007 + *
2008 + ******************************************************************************/
2009 +
2010 +#include <asm/rc32434/types.h>
2011 +
2012 +enum
2013 +{
2014 + CROM0_PhysicalAddress = 0x100b8000,
2015 + CROM_PhysicalAddress = CROM0_PhysicalAddress,
2016 +
2017 + CROM0_VirtualAddress = 0xb00b8000,
2018 + CROM_VirtualAddress = CROM0_VirtualAddress,
2019 +} ;
2020 +
2021 +typedef struct CROM_s
2022 +{
2023 + U32 cromw0 ; // use CROMW0_
2024 + U32 cromw1 ; // use CROMW1_
2025 + U32 cromw2 ; // use CROMW2_
2026 +} volatile * CROM_t ;
2027 +
2028 +enum
2029 +{
2030 + CROMW0_xloc_b = 0,
2031 + CROMW0_xloc_m = 0x0000003f,
2032 + CROMW0_yloc_b = 8,
2033 + CROMW0_yloc_m = 0x00003f00,
2034 + CROMW0_speed_b = 16,
2035 + CROMW0_speed_m = 0x01ff0000,
2036 + CROMW1_wafer_b = 0,
2037 + CROMW1_wafer_m = 0x0000001f,
2038 + CROMW1_lot_b = 8,
2039 + CROMW1_lot_m = 0x0fffff00,
2040 + CROMW1_fab_b = 28,
2041 + CROMW1_fab_m = 0xf0000000,
2042 + CROMW2_pci_b = 0,
2043 + CROMW2_pci_m = 0x00000001,
2044 + CROMW2_eth0_b = 1,
2045 + CROMW2_eth0_m = 0x00000002,
2046 + CROMW2_eth1_b = 2,
2047 + CROMW2_eth1_m = 0x00000004
2048 + CROMW2_i2c_b = 3,
2049 + CROMW2_i2c_m = 0x00000008,
2050 + CROMW2_rng_b = 4,
2051 + CROMW2_rng_m = 0x00000010,
2052 + CROMW2_se_b = 5,
2053 + CROMW2_se_m = 0x00000020,
2054 + CROMW2_des_b = 6,
2055 + CROMW2_des_m = 0x00000040,
2056 + CROMW2_tdes_b = 7,
2057 + CROMW2_tdes_m = 0x00000080,
2058 + CROMW2_a128_b = 8,
2059 + CROMW2_a128_m = 0x00000100,
2060 + CROMW2_a192_b = 9,
2061 + CROMW2_a192_m = 0x00000200,
2062 + CROMW2_a256_b = 10,
2063 + CROMW2_a256_m = 0x00000400,
2064 + CROMW2_md5_b = 11,
2065 + CROMW2_md5_m = 0x00000800,
2066 + CROMW2_s1_b = 12,
2067 + CROMW2_s1_m = 0x00001000,
2068 + CROMW2_s256_b = 13,
2069 + CROMW2_s256_m = 0x00002000,
2070 + CROMW2_pka_b = 14,
2071 + CROMW2_pka_m = 0x00004000,
2072 + CROMW2_exp_b = 15,
2073 + CROMW2_exp_m = 0x00018000,
2074 + CROMW2_exp_8192_v = 0,
2075 + CROMW2_exp_1536_v = 1,
2076 + CROMW2_exp_1024_v = 2,
2077 + CROMW2_exp_512_v = 3,
2078 + CROMW2_rocfg_b = 17,
2079 + CROMW2_rocfg_m = 0x000e0000,
2080 +} ;
2081 +
2082 +#endif // __IDT_CROM_H__
2083 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2084 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
2085 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-06-15 16:26:53.000000000 +0200
2086 @@ -0,0 +1,175 @@
2087 +#ifndef __IDT_DDR_H__
2088 +#define __IDT_DDR_H__
2089 +
2090 +/*******************************************************************************
2091 + *
2092 + * Copyright 2002 Integrated Device Technology, Inc.
2093 + * All rights reserved.
2094 + *
2095 + * DDR register definition.
2096 + *
2097 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2098 + *
2099 + * Author : ryan.holmQVist@idt.com
2100 + * Date : 20011005
2101 + * Update :
2102 + * $Log: ddr.h,v $
2103 + * Revision 1.2 2002/06/06 18:34:03 astichte
2104 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2105 + *
2106 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2107 + * jba File moved from vcode/include/idt/acacia
2108 + *
2109 + *
2110 + ******************************************************************************/
2111 +
2112 +#include <asm/rc32434/types.h>
2113 +
2114 +enum
2115 +{
2116 + DDR0_PhysicalAddress = 0x18018000,
2117 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
2118 +
2119 + DDR0_VirtualAddress = 0xb8018000,
2120 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
2121 +} ;
2122 +
2123 +typedef struct DDR_s
2124 +{
2125 + U32 ddrbase ;
2126 + U32 ddrmask ;
2127 + U32 res1;
2128 + U32 res2;
2129 + U32 ddrc ;
2130 + U32 ddrabase ;
2131 + U32 ddramask ;
2132 + U32 ddramap ;
2133 + U32 ddrcust;
2134 + U32 ddrrdc;
2135 + U32 ddrspare;
2136 +} volatile *DDR_t ;
2137 +
2138 +enum
2139 +{
2140 + DDR0BASE_baseaddr_b = 16,
2141 + DDR0BASE_baseaddr_m = 0xffff0000,
2142 +
2143 + DDR0MASK_mask_b = 16,
2144 + DDR0MASK_mask_m = 0xffff0000,
2145 +
2146 + DDR1BASE_baseaddr_b = 16,
2147 + DDR1BASE_baseaddr_m = 0xffff0000,
2148 +
2149 + DDR1MASK_mask_b = 16,
2150 + DDR1MASK_mask_m = 0xffff0000,
2151 +
2152 + DDRC_ata_b = 5,
2153 + DDRC_ata_m = 0x000000E0,
2154 + DDRC_dbw_b = 8,
2155 + DDRC_dbw_m = 0x00000100,
2156 + DDRC_wr_b = 9,
2157 + DDRC_wr_m = 0x00000600,
2158 + DDRC_ps_b = 11,
2159 + DDRC_ps_m = 0x00001800,
2160 + DDRC_dtype_b = 13,
2161 + DDRC_dtype_m = 0x0000e000,
2162 + DDRC_rfc_b = 16,
2163 + DDRC_rfc_m = 0x000f0000,
2164 + DDRC_rp_b = 20,
2165 + DDRC_rp_m = 0x00300000,
2166 + DDRC_ap_b = 22,
2167 + DDRC_ap_m = 0x00400000,
2168 + DDRC_rcd_b = 23,
2169 + DDRC_rcd_m = 0x01800000,
2170 + DDRC_cl_b = 25,
2171 + DDRC_cl_m = 0x06000000,
2172 + DDRC_dbm_b = 27,
2173 + DDRC_dbm_m = 0x08000000,
2174 + DDRC_sds_b = 28,
2175 + DDRC_sds_m = 0x10000000,
2176 + DDRC_atp_b = 29,
2177 + DDRC_atp_m = 0x60000000,
2178 + DDRC_re_b = 31,
2179 + DDRC_re_m = 0x80000000,
2180 +
2181 + DDRRDC_ces_b = 0,
2182 + DDRRDC_ces_m = 0x00000001,
2183 + DDRRDC_ace_b = 1,
2184 + DDRRDC_ace_m = 0x00000002,
2185 +
2186 + DDRABASE_baseaddr_b = 16,
2187 + DDRABASE_baseaddr_m = 0xffff0000,
2188 +
2189 + DDRAMASK_mask_b = 16,
2190 + DDRAMASK_mask_m = 0xffff0000,
2191 +
2192 + DDRAMAP_map_b = 16,
2193 + DDRAMAP_map_m = 0xffff0000,
2194 +
2195 + DDRCUST_cs_b = 0,
2196 + DDRCUST_cs_m = 0x00000003,
2197 + DDRCUST_we_b = 2,
2198 + DDRCUST_we_m = 0x00000004,
2199 + DDRCUST_ras_b = 3,
2200 + DDRCUST_ras_m = 0x00000008,
2201 + DDRCUST_cas_b = 4,
2202 + DDRCUST_cas_m = 0x00000010,
2203 + DDRCUST_cke_b = 5,
2204 + DDRCUST_cke_m = 0x00000020,
2205 + DDRCUST_ba_b = 6,
2206 + DDRCUST_ba_m = 0x000000c0,
2207 +
2208 + RCOUNT_rcount_b = 0,
2209 + RCOUNT_rcount_m = 0x0000ffff,
2210 +
2211 + RCOMPARE_rcompare_b = 0,
2212 + RCOMPARE_rcompare_m = 0x0000ffff,
2213 +
2214 + RTC_ce_b = 0,
2215 + RTC_ce_m = 0x00000001,
2216 + RTC_to_b = 1,
2217 + RTC_to_m = 0x00000002,
2218 + RTC_rqe_b = 2,
2219 + RTC_rqe_m = 0x00000004,
2220 +
2221 + DDRDQSC_dm_b = 0,
2222 + DDRDQSC_dm_m = 0x00000003,
2223 + DDRDQSC_dqsbs_b = 2,
2224 + DDRDQSC_dqsbs_m = 0x000000fc,
2225 + DDRDQSC_db_b = 8,
2226 + DDRDQSC_db_m = 0x00000100,
2227 + DDRDQSC_dbsp_b = 9,
2228 + DDRDQSC_dbsp_m = 0x01fffe00,
2229 + DDRDQSC_bdp_b = 25,
2230 + DDRDQSC_bdp_m = 0x7e000000,
2231 +
2232 + DDRDLLC_eao_b = 0,
2233 + DDRDLLC_eao_m = 0x00000001,
2234 + DDRDLLC_eo_b = 1,
2235 + DDRDLLC_eo_m = 0x0000003e,
2236 + DDRDLLC_fs_b = 6,
2237 + DDRDLLC_fs_m = 0x000000c0,
2238 + DDRDLLC_as_b = 8,
2239 + DDRDLLC_as_m = 0x00000700,
2240 + DDRDLLC_sp_b = 11,
2241 + DDRDLLC_sp_m = 0x001ff800,
2242 +
2243 + DDRDLLFC_men_b = 0,
2244 + DDRDLLFC_men_m = 0x00000001,
2245 + DDRDLLFC_aen_b = 1,
2246 + DDRDLLFC_aen_m = 0x00000002,
2247 + DDRDLLFC_ff_b = 2,
2248 + DDRDLLFC_ff_m = 0x00000004,
2249 +
2250 + DDRDLLTA_addr_b = 2,
2251 + DDRDLLTA_addr_m = 0xfffffffc,
2252 +
2253 + DDRDLLED_dbe_b = 0,
2254 + DDRDLLED_dbe_m = 0x00000001,
2255 + DDRDLLED_dte_b = 1,
2256 + DDRDLLED_dte_m = 0x00000002,
2257 +
2258 +
2259 +} ;
2260 +
2261 +#endif // __IDT_DDR_H__
2262 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2263 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
2264 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-06-15 16:26:53.000000000 +0200
2265 @@ -0,0 +1,134 @@
2266 +#ifndef __IDT_DEV_H__
2267 +#define __IDT_DEV_H__
2268 +
2269 +/*******************************************************************************
2270 + *
2271 + * Copyright 2002 Integrated Device Technology, Inc.
2272 + * All rights reserved.
2273 + *
2274 + * Device Controller register definition.
2275 + *
2276 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2277 + *
2278 + * Author : John.Ahrens@idt.com
2279 + * Date : 200112013
2280 + * Update :
2281 + * $Log: dev.h,v $
2282 + * Revision 1.2 2002/06/06 18:34:03 astichte
2283 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2284 + *
2285 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2286 + * jba File moved from vcode/include/idt/acacia
2287 + *
2288 + *
2289 + ******************************************************************************/
2290 +
2291 +#include <asm/rc32434/types.h>
2292 +
2293 +enum
2294 +{
2295 + DEV0_PhysicalAddress = 0x18010000,
2296 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
2297 +
2298 + DEV0_VirtualAddress = 0xb8010000,
2299 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
2300 +} ;
2301 +
2302 +typedef struct DEVICE_s
2303 +{
2304 + U32 devbase ; // Device Base
2305 + U32 devmask ; // Device Mask
2306 + U32 devc ; // Device Control
2307 + U32 devtc ; // Device Timing Control
2308 +} volatile *DEVICE_t ;
2309 +
2310 +enum
2311 +{
2312 + DEV_Count = 3,
2313 +} ;
2314 +
2315 +typedef struct DEV_s
2316 +{
2317 + struct DEVICE_s dev [DEV_Count] ;
2318 + U32 btcs ; // Bus timeout control / status
2319 + U32 btcompare ; // Compare
2320 + U32 btaddr ; // Timeout address.
2321 + U32 devdacs ; // Decoupled access control.
2322 + U32 devdaa ; // Decoupled access address.
2323 + U32 devdad ; // Decoupled access address.
2324 + U32 devspare ; // spare.
2325 +} volatile *DEV_t ;
2326 +
2327 +enum
2328 +{
2329 + DEVBASE_baseaddr_b = 16,
2330 + DEVBASE_baseaddr_m = 0xffff0000,
2331 + DEVMASK_mask_b = 16,
2332 + DEVMASK_mask_m = 0xffff0000,
2333 +
2334 + DEVC_ds_b = 0,
2335 + DEVC_ds_m = 0x00000003,
2336 + DEVC_ds_8_v = 0, // 8-bit device.
2337 + DEVC_ds_16_v = 1, // reserved
2338 + DEVC_ds_res_v = 2, // reserved.
2339 + DEVC_ds_res2_v = 3, // reserved.
2340 + DEVC_be_b = 2,
2341 + DEVC_be_m = 0x00000004,
2342 + DEVC_wp_b = 3,
2343 + DEVC_wp_m = 0x00000008,
2344 + DEVC_csd_b = 4,
2345 + DEVC_csd_m = 0x000000f0,
2346 + DEVC_oed_b = 8,
2347 + DEVC_oed_m = 0x00000f00,
2348 + DEVC_bwd_b = 12,
2349 + DEVC_bwd_m = 0x0000f000,
2350 + DEVC_rws_b = 16,
2351 + DEVC_rws_m = 0x003f0000,
2352 + DEVC_wws_b = 22,
2353 + DEVC_wws_m = 0x0fc00000,
2354 + DEVC_bre_b = 28,
2355 + DEVC_bre_m = 0x10000000,
2356 + DEVC_bwe_b = 29,
2357 + DEVC_bwe_m = 0x20000000,
2358 + DEVC_wam_b = 30,
2359 + DEVC_wam_m = 0x40000000,
2360 +
2361 + DEVTC_prd_b = 0,
2362 + DEVTC_prd_m = 0x0000000f,
2363 + DEVTC_pwd_b = 4,
2364 + DEVTC_pwd_m = 0x000000f0,
2365 + DEVTC_wdh_b = 8,
2366 + DEVTC_wdh_m = 0x00000700,
2367 + DEVTC_csh_b = 11,
2368 + DEVTC_csh_m = 0x00001800,
2369 +
2370 + BTCS_tt_b = 0,
2371 + BTCS_tt_m = 0x00000001,
2372 + BTCS_tt_write = 0,
2373 + BTCS_tt_read = 1,
2374 + BTCS_bto_b = 1, // In btcs
2375 + BTCS_bto_m = 0x00000002, // In btcs
2376 + BTCS_bte_b = 2, // In btcs
2377 + BTCS_bte_m = 0x00000004, // In btcs
2378 +
2379 + BTCOMPARE_compare_b = 0, // In btcompare
2380 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
2381 +
2382 + DEVDACS_op_b = 0, // In devdacs
2383 + DEVDACS_op_m = 0x00000001, // In devdacs
2384 + DEVDACS_op_write_v = 0,
2385 + DEVDACS_op_read_v = 1,
2386 + DEVDACS_size_b = 1, // In devdacs
2387 + DEVDACS_size_m = 0x00000006, // In devdacs
2388 + DEVDACS_size_byte_v = 0,
2389 + DEVDACS_size_halfword = 1,
2390 + DEVDACS_size_triplebyte = 2,
2391 + DEVDACS_size_word = 3,
2392 + DEVDACS_err_b = 3, // In devdacs
2393 + DEVDACS_err_m = 0x00000008, // In devdacs
2394 + DEVDACS_f_b = 4, // In devdacs
2395 + DEVDACS_f_m = 0x00000010, // In devdacs
2396 +} ;
2397 +
2398 +#endif //__IDT_DEV_H__
2399 +
2400 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2401 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
2402 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-06-15 16:26:53.000000000 +0200
2403 @@ -0,0 +1,202 @@
2404 +#ifndef __IDT_DMA_H__
2405 +#define __IDT_DMA_H__
2406 +
2407 +/*******************************************************************************
2408 + *
2409 + * Copyright 2002 Integrated Device Technology, Inc.
2410 + * All rights reserved.
2411 + *
2412 + * DMA register definition.
2413 + *
2414 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2415 + *
2416 + * Author : ryan.holmQVist@idt.com
2417 + * Date : 20011005
2418 + * Update :
2419 + * $Log: dma.h,v $
2420 + * Revision 1.3 2002/06/06 18:34:03 astichte
2421 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2422 + *
2423 + * Revision 1.2 2002/06/05 18:30:46 astichte
2424 + * Removed IDTField
2425 + *
2426 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2427 + * jba File moved from vcode/include/idt/acacia
2428 + *
2429 + *
2430 + ******************************************************************************/
2431 +
2432 +#include <asm/rc32434/types.h>
2433 +enum
2434 +{
2435 + DMA0_PhysicalAddress = 0x18040000,
2436 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
2437 +
2438 + DMA0_VirtualAddress = 0xb8040000,
2439 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
2440 +} ;
2441 +
2442 +/*
2443 + * DMA descriptor (in physical memory).
2444 + */
2445 +
2446 +typedef struct DMAD_s
2447 +{
2448 + U32 control ; // Control. use DMAD_*
2449 + U32 ca ; // Current Address.
2450 + U32 devcs ; // Device control and status.
2451 + U32 link ; // Next descriptor in chain.
2452 +} volatile *DMAD_t ;
2453 +
2454 +enum
2455 +{
2456 + DMAD_size = sizeof (struct DMAD_s),
2457 + DMAD_count_b = 0, // in DMAD_t -> control
2458 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
2459 + DMAD_ds_b = 20, // in DMAD_t -> control
2460 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
2461 + DMAD_ds_ethRcv_v = 0,
2462 + DMAD_ds_ethXmt_v = 0,
2463 + DMAD_ds_memToFifo_v = 0,
2464 + DMAD_ds_fifoToMem_v = 0,
2465 + DMAD_ds_pciToMem_v = 0,
2466 + DMAD_ds_memToPci_v = 0,
2467 +
2468 + DMAD_devcmd_b = 22, // in DMAD_t -> control
2469 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
2470 + DMAD_devcmd_byte_v = 0, //memory-to-memory
2471 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
2472 + DMAD_devcmd_word_v = 2, //memory-to-memory
2473 + DMAD_devcmd_2words_v = 3, //memory-to-memory
2474 + DMAD_devcmd_4words_v = 4, //memory-to-memory
2475 + DMAD_devcmd_6words_v = 5, //memory-to-memory
2476 + DMAD_devcmd_8words_v = 6, //memory-to-memory
2477 + DMAD_devcmd_16words_v = 7, //memory-to-memory
2478 + DMAD_cof_b = 25, // chain on finished
2479 + DMAD_cof_m = 0x02000000, //
2480 + DMAD_cod_b = 26, // chain on done
2481 + DMAD_cod_m = 0x04000000, //
2482 + DMAD_iof_b = 27, // interrupt on finished
2483 + DMAD_iof_m = 0x08000000, //
2484 + DMAD_iod_b = 28, // interrupt on done
2485 + DMAD_iod_m = 0x10000000, //
2486 + DMAD_t_b = 29, // terminated
2487 + DMAD_t_m = 0x20000000, //
2488 + DMAD_d_b = 30, // done
2489 + DMAD_d_m = 0x40000000, //
2490 + DMAD_f_b = 31, // finished
2491 + DMAD_f_m = 0x80000000, //
2492 +} ;
2493 +
2494 +/*
2495 + * DMA register (within Internal Register Map).
2496 + */
2497 +
2498 +struct DMA_Chan_s
2499 +{
2500 + U32 dmac ; // Control.
2501 + U32 dmas ; // Status.
2502 + U32 dmasm ; // Mask.
2503 + U32 dmadptr ; // Descriptor pointer.
2504 + U32 dmandptr ; // Next descriptor pointer.
2505 +};
2506 +
2507 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2508 +
2509 +//DMA_Channels use DMACH_count instead
2510 +
2511 +enum
2512 +{
2513 + DMAC_run_b = 0, //
2514 + DMAC_run_m = 0x00000001, //
2515 + DMAC_dm_b = 1, // done mask
2516 + DMAC_dm_m = 0x00000002, //
2517 + DMAC_mode_b = 2, //
2518 + DMAC_mode_m = 0x0000000c, //
2519 + DMAC_mode_auto_v = 0,
2520 + DMAC_mode_burst_v = 1,
2521 + DMAC_mode_transfer_v = 2, //usually used
2522 + DMAC_mode_reserved_v = 3,
2523 + DMAC_a_b = 4, //
2524 + DMAC_a_m = 0x00000010, //
2525 +
2526 + DMAS_f_b = 0, // finished (sticky)
2527 + DMAS_f_m = 0x00000001, //
2528 + DMAS_d_b = 1, // done (sticky)
2529 + DMAS_d_m = 0x00000002, //
2530 + DMAS_c_b = 2, // chain (sticky)
2531 + DMAS_c_m = 0x00000004, //
2532 + DMAS_e_b = 3, // error (sticky)
2533 + DMAS_e_m = 0x00000008, //
2534 + DMAS_h_b = 4, // halt (sticky)
2535 + DMAS_h_m = 0x00000010, //
2536 +
2537 + DMASM_f_b = 0, // finished (1=mask)
2538 + DMASM_f_m = 0x00000001, //
2539 + DMASM_d_b = 1, // done (1=mask)
2540 + DMASM_d_m = 0x00000002, //
2541 + DMASM_c_b = 2, // chain (1=mask)
2542 + DMASM_c_m = 0x00000004, //
2543 + DMASM_e_b = 3, // error (1=mask)
2544 + DMASM_e_m = 0x00000008, //
2545 + DMASM_h_b = 4, // halt (1=mask)
2546 + DMASM_h_m = 0x00000010, //
2547 +} ;
2548 +
2549 +/*
2550 + * DMA channel definitions
2551 + */
2552 +
2553 +enum
2554 +{
2555 + DMACH_ethRcv = 0,
2556 + DMACH_ethXmt = 1,
2557 + DMACH_memToFifo = 2,
2558 + DMACH_fifoToMem = 3,
2559 + DMACH_pciToMem = 4,
2560 + DMACH_memToPci = 5,
2561 +
2562 + DMACH_count //must be last
2563 +};
2564 +
2565 +
2566 +typedef struct DMAC_s
2567 +{
2568 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2569 +} volatile *DMA_t ;
2570 +
2571 +
2572 +/*
2573 + * External DMA parameters
2574 +*/
2575 +#if 0
2576 +enum
2577 +{
2578 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2579 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2580 + DMADEVCMD_ts_byte_v = 0,
2581 + DMADEVCMD_ts_halfword_v = 1,
2582 + DMADEVCMD_ts_word_v = 2,
2583 + DMADEVCMD_ts_2word_v = 3,
2584 + DMADEVCMD_ts_4word_v = 4,
2585 + DMADEVCMD_ts_6word_v = 5,
2586 + DMADEVCMD_ts_8word_v = 6,
2587 + DMADEVCMD_ts_16word_v = 7
2588 +};
2589 +#endif
2590 +
2591 +#if 1 // aws - Compatibility.
2592 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2593 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2594 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2595 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2596 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2597 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2598 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2599 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2600 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2601 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2602 +#endif // aws - Compatibility.
2603 +
2604 +#endif // __IDT_DMA_H__
2605 +
2606 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2607 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2608 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-06-15 16:26:53.000000000 +0200
2609 @@ -0,0 +1,73 @@
2610 +#ifndef __IDT_DMA_V_H__
2611 +#define __IDT_DMA_V_H__
2612 +
2613 +/*******************************************************************************
2614 + *
2615 + * Copyright 2002 Integrated Device Technology, Inc.
2616 + * All rights reserved.
2617 + *
2618 + * DMA register definition.
2619 + *
2620 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2621 + *
2622 + * Author : ryan.holmQVist@idt.com
2623 + * Date : 20011005
2624 + * Update :
2625 + * $Log: dma.h,v $
2626 + * Revision 1.3 2002/06/06 18:34:03 astichte
2627 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2628 + *
2629 + * Revision 1.2 2002/06/05 18:30:46 astichte
2630 + * Removed IDTField
2631 + *
2632 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2633 + * jba File moved from vcode/include/idt/acacia
2634 + *
2635 + *
2636 + ******************************************************************************/
2637 +#include <asm/rc32434/types.h>
2638 +#include <asm/rc32434/dma.h>
2639 +#include <asm/rc32434/rc32434.h>
2640 +#define DMA_CHAN_OFFSET 0x14
2641 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2642 +#define DMA_COUNT(count) \
2643 + ((count) & DMAD_count_m)
2644 +
2645 +#define DMA_HALT_TIMEOUT 500
2646 +
2647 +
2648 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2649 +{
2650 + int timeout=1;
2651 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2652 + local_writel(0, &ch->dmac);
2653 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2654 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2655 + local_writel(0, &ch->dmas);
2656 + break;
2657 + }
2658 + }
2659 + }
2660 +
2661 + return timeout ? 0 : 1;
2662 +}
2663 +
2664 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2665 +{
2666 + local_writel(0, &ch->dmandptr);
2667 + local_writel(dma_addr, &ch->dmadptr);
2668 +}
2669 +
2670 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2671 +{
2672 + local_writel(dma_addr, &ch->dmandptr);
2673 +}
2674 +
2675 +#endif // __IDT_DMA_V_H__
2676 +
2677 +
2678 +
2679 +
2680 +
2681 +
2682 +
2683 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2684 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2685 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-06-15 16:26:53.000000000 +0200
2686 @@ -0,0 +1,322 @@
2687 +#ifndef __IDT_ETH_H__
2688 +#define __IDT_ETH_H__
2689 +
2690 +/*******************************************************************************
2691 + *
2692 + * Copyright 2002 Integrated Device Technology, Inc.
2693 + * All rights reserved.
2694 + *
2695 + * Ethernet register definition.
2696 + *
2697 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2698 + *
2699 + * Author : Allen.Stichter@idt.com
2700 + * Date : 20020605
2701 + * Update :
2702 + * $Log: eth.h,v $
2703 + * Revision 1.3 2002/06/06 18:34:04 astichte
2704 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2705 + *
2706 + * Revision 1.2 2002/06/05 18:19:46 astichte
2707 + * Added
2708 + *
2709 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2710 + * jba File moved from vcode/include/idt/acacia
2711 + *
2712 + ******************************************************************************/
2713 +
2714 +#include <asm/rc32434/types.h>
2715 +
2716 +enum
2717 +{
2718 + ETH0_PhysicalAddress = 0x18060000,
2719 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2720 +
2721 + ETH0_VirtualAddress = 0xb8060000,
2722 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2723 +} ;
2724 +
2725 +typedef struct
2726 +{
2727 + U32 ethintfc ;
2728 + U32 ethfifott ;
2729 + U32 etharc ;
2730 + U32 ethhash0 ;
2731 + U32 ethhash1 ;
2732 + U32 ethu0 [4] ; // Reserved.
2733 + U32 ethpfs ;
2734 + U32 ethmcp ;
2735 + U32 eth_u1 [10] ; // Reserved.
2736 + U32 ethspare ;
2737 + U32 eth_u2 [42] ; // Reserved.
2738 + U32 ethsal0 ;
2739 + U32 ethsah0 ;
2740 + U32 ethsal1 ;
2741 + U32 ethsah1 ;
2742 + U32 ethsal2 ;
2743 + U32 ethsah2 ;
2744 + U32 ethsal3 ;
2745 + U32 ethsah3 ;
2746 + U32 ethrbc ;
2747 + U32 ethrpc ;
2748 + U32 ethrupc ;
2749 + U32 ethrfc ;
2750 + U32 ethtbc ;
2751 + U32 ethgpf ;
2752 + U32 eth_u9 [50] ; // Reserved.
2753 + U32 ethmac1 ;
2754 + U32 ethmac2 ;
2755 + U32 ethipgt ;
2756 + U32 ethipgr ;
2757 + U32 ethclrt ;
2758 + U32 ethmaxf ;
2759 + U32 eth_u10 ; // Reserved.
2760 + U32 ethmtest ;
2761 + U32 miimcfg ;
2762 + U32 miimcmd ;
2763 + U32 miimaddr ;
2764 + U32 miimwtd ;
2765 + U32 miimrdd ;
2766 + U32 miimind ;
2767 + U32 eth_u11 ; // Reserved.
2768 + U32 eth_u12 ; // Reserved.
2769 + U32 ethcfsa0 ;
2770 + U32 ethcfsa1 ;
2771 + U32 ethcfsa2 ;
2772 +} volatile *ETH_t;
2773 +
2774 +enum
2775 +{
2776 + ETHINTFC_en_b = 0,
2777 + ETHINTFC_en_m = 0x00000001,
2778 + ETHINTFC_its_b = 1,
2779 + ETHINTFC_its_m = 0x00000002,
2780 + ETHINTFC_rip_b = 2,
2781 + ETHINTFC_rip_m = 0x00000004,
2782 + ETHINTFC_jam_b = 3,
2783 + ETHINTFC_jam_m = 0x00000008,
2784 + ETHINTFC_ovr_b = 4,
2785 + ETHINTFC_ovr_m = 0x00000010,
2786 + ETHINTFC_und_b = 5,
2787 + ETHINTFC_und_m = 0x00000020,
2788 + ETHINTFC_iom_b = 6,
2789 + ETHINTFC_iom_m = 0x000000c0,
2790 +
2791 + ETHFIFOTT_tth_b = 0,
2792 + ETHFIFOTT_tth_m = 0x0000007f,
2793 +
2794 + ETHARC_pro_b = 0,
2795 + ETHARC_pro_m = 0x00000001,
2796 + ETHARC_am_b = 1,
2797 + ETHARC_am_m = 0x00000002,
2798 + ETHARC_afm_b = 2,
2799 + ETHARC_afm_m = 0x00000004,
2800 + ETHARC_ab_b = 3,
2801 + ETHARC_ab_m = 0x00000008,
2802 +
2803 + ETHSAL_byte5_b = 0,
2804 + ETHSAL_byte5_m = 0x000000ff,
2805 + ETHSAL_byte4_b = 8,
2806 + ETHSAL_byte4_m = 0x0000ff00,
2807 + ETHSAL_byte3_b = 16,
2808 + ETHSAL_byte3_m = 0x00ff0000,
2809 + ETHSAL_byte2_b = 24,
2810 + ETHSAL_byte2_m = 0xff000000,
2811 +
2812 + ETHSAH_byte1_b = 0,
2813 + ETHSAH_byte1_m = 0x000000ff,
2814 + ETHSAH_byte0_b = 8,
2815 + ETHSAH_byte0_m = 0x0000ff00,
2816 +
2817 + ETHGPF_ptv_b = 0,
2818 + ETHGPF_ptv_m = 0x0000ffff,
2819 +
2820 + ETHPFS_pfd_b = 0,
2821 + ETHPFS_pfd_m = 0x00000001,
2822 +
2823 + ETHCFSA0_cfsa4_b = 0,
2824 + ETHCFSA0_cfsa4_m = 0x000000ff,
2825 + ETHCFSA0_cfsa5_b = 8,
2826 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2827 +
2828 + ETHCFSA1_cfsa2_b = 0,
2829 + ETHCFSA1_cfsa2_m = 0x000000ff,
2830 + ETHCFSA1_cfsa3_b = 8,
2831 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2832 +
2833 + ETHCFSA2_cfsa0_b = 0,
2834 + ETHCFSA2_cfsa0_m = 0x000000ff,
2835 + ETHCFSA2_cfsa1_b = 8,
2836 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2837 +
2838 + ETHMAC1_re_b = 0,
2839 + ETHMAC1_re_m = 0x00000001,
2840 + ETHMAC1_paf_b = 1,
2841 + ETHMAC1_paf_m = 0x00000002,
2842 + ETHMAC1_rfc_b = 2,
2843 + ETHMAC1_rfc_m = 0x00000004,
2844 + ETHMAC1_tfc_b = 3,
2845 + ETHMAC1_tfc_m = 0x00000008,
2846 + ETHMAC1_lb_b = 4,
2847 + ETHMAC1_lb_m = 0x00000010,
2848 + ETHMAC1_mr_b = 31,
2849 + ETHMAC1_mr_m = 0x80000000,
2850 +
2851 + ETHMAC2_fd_b = 0,
2852 + ETHMAC2_fd_m = 0x00000001,
2853 + ETHMAC2_flc_b = 1,
2854 + ETHMAC2_flc_m = 0x00000002,
2855 + ETHMAC2_hfe_b = 2,
2856 + ETHMAC2_hfe_m = 0x00000004,
2857 + ETHMAC2_dc_b = 3,
2858 + ETHMAC2_dc_m = 0x00000008,
2859 + ETHMAC2_cen_b = 4,
2860 + ETHMAC2_cen_m = 0x00000010,
2861 + ETHMAC2_pe_b = 5,
2862 + ETHMAC2_pe_m = 0x00000020,
2863 + ETHMAC2_vpe_b = 6,
2864 + ETHMAC2_vpe_m = 0x00000040,
2865 + ETHMAC2_ape_b = 7,
2866 + ETHMAC2_ape_m = 0x00000080,
2867 + ETHMAC2_ppe_b = 8,
2868 + ETHMAC2_ppe_m = 0x00000100,
2869 + ETHMAC2_lpe_b = 9,
2870 + ETHMAC2_lpe_m = 0x00000200,
2871 + ETHMAC2_nb_b = 12,
2872 + ETHMAC2_nb_m = 0x00001000,
2873 + ETHMAC2_bp_b = 13,
2874 + ETHMAC2_bp_m = 0x00002000,
2875 + ETHMAC2_ed_b = 14,
2876 + ETHMAC2_ed_m = 0x00004000,
2877 +
2878 + ETHIPGT_ipgt_b = 0,
2879 + ETHIPGT_ipgt_m = 0x0000007f,
2880 +
2881 + ETHIPGR_ipgr2_b = 0,
2882 + ETHIPGR_ipgr2_m = 0x0000007f,
2883 + ETHIPGR_ipgr1_b = 8,
2884 + ETHIPGR_ipgr1_m = 0x00007f00,
2885 +
2886 + ETHCLRT_maxret_b = 0,
2887 + ETHCLRT_maxret_m = 0x0000000f,
2888 + ETHCLRT_colwin_b = 8,
2889 + ETHCLRT_colwin_m = 0x00003f00,
2890 +
2891 + ETHMAXF_maxf_b = 0,
2892 + ETHMAXF_maxf_m = 0x0000ffff,
2893 +
2894 + ETHMTEST_tb_b = 2,
2895 + ETHMTEST_tb_m = 0x00000004,
2896 +
2897 + ETHMCP_div_b = 0,
2898 + ETHMCP_div_m = 0x000000ff,
2899 +
2900 + MIIMCFG_rsv_b = 0,
2901 + MIIMCFG_rsv_m = 0x0000000c,
2902 +
2903 + MIIMCMD_rd_b = 0,
2904 + MIIMCMD_rd_m = 0x00000001,
2905 + MIIMCMD_scn_b = 1,
2906 + MIIMCMD_scn_m = 0x00000002,
2907 +
2908 + MIIMADDR_regaddr_b = 0,
2909 + MIIMADDR_regaddr_m = 0x0000001f,
2910 + MIIMADDR_phyaddr_b = 8,
2911 + MIIMADDR_phyaddr_m = 0x00001f00,
2912 +
2913 + MIIMWTD_wdata_b = 0,
2914 + MIIMWTD_wdata_m = 0x0000ffff,
2915 +
2916 + MIIMRDD_rdata_b = 0,
2917 + MIIMRDD_rdata_m = 0x0000ffff,
2918 +
2919 + MIIMIND_bsy_b = 0,
2920 + MIIMIND_bsy_m = 0x00000001,
2921 + MIIMIND_scn_b = 1,
2922 + MIIMIND_scn_m = 0x00000002,
2923 + MIIMIND_nv_b = 2,
2924 + MIIMIND_nv_m = 0x00000004,
2925 +
2926 +} ;
2927 +
2928 +/*
2929 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2930 + */
2931 +enum
2932 +{
2933 + ETHRX_fd_b = 0,
2934 + ETHRX_fd_m = 0x00000001,
2935 + ETHRX_ld_b = 1,
2936 + ETHRX_ld_m = 0x00000002,
2937 + ETHRX_rok_b = 2,
2938 + ETHRX_rok_m = 0x00000004,
2939 + ETHRX_fm_b = 3,
2940 + ETHRX_fm_m = 0x00000008,
2941 + ETHRX_mp_b = 4,
2942 + ETHRX_mp_m = 0x00000010,
2943 + ETHRX_bp_b = 5,
2944 + ETHRX_bp_m = 0x00000020,
2945 + ETHRX_vlt_b = 6,
2946 + ETHRX_vlt_m = 0x00000040,
2947 + ETHRX_cf_b = 7,
2948 + ETHRX_cf_m = 0x00000080,
2949 + ETHRX_ovr_b = 8,
2950 + ETHRX_ovr_m = 0x00000100,
2951 + ETHRX_crc_b = 9,
2952 + ETHRX_crc_m = 0x00000200,
2953 + ETHRX_cv_b = 10,
2954 + ETHRX_cv_m = 0x00000400,
2955 + ETHRX_db_b = 11,
2956 + ETHRX_db_m = 0x00000800,
2957 + ETHRX_le_b = 12,
2958 + ETHRX_le_m = 0x00001000,
2959 + ETHRX_lor_b = 13,
2960 + ETHRX_lor_m = 0x00002000,
2961 + ETHRX_ces_b = 14,
2962 + ETHRX_ces_m = 0x00004000,
2963 + ETHRX_length_b = 16,
2964 + ETHRX_length_m = 0xffff0000,
2965 +
2966 + ETHTX_fd_b = 0,
2967 + ETHTX_fd_m = 0x00000001,
2968 + ETHTX_ld_b = 1,
2969 + ETHTX_ld_m = 0x00000002,
2970 + ETHTX_oen_b = 2,
2971 + ETHTX_oen_m = 0x00000004,
2972 + ETHTX_pen_b = 3,
2973 + ETHTX_pen_m = 0x00000008,
2974 + ETHTX_cen_b = 4,
2975 + ETHTX_cen_m = 0x00000010,
2976 + ETHTX_hen_b = 5,
2977 + ETHTX_hen_m = 0x00000020,
2978 + ETHTX_tok_b = 6,
2979 + ETHTX_tok_m = 0x00000040,
2980 + ETHTX_mp_b = 7,
2981 + ETHTX_mp_m = 0x00000080,
2982 + ETHTX_bp_b = 8,
2983 + ETHTX_bp_m = 0x00000100,
2984 + ETHTX_und_b = 9,
2985 + ETHTX_und_m = 0x00000200,
2986 + ETHTX_of_b = 10,
2987 + ETHTX_of_m = 0x00000400,
2988 + ETHTX_ed_b = 11,
2989 + ETHTX_ed_m = 0x00000800,
2990 + ETHTX_ec_b = 12,
2991 + ETHTX_ec_m = 0x00001000,
2992 + ETHTX_lc_b = 13,
2993 + ETHTX_lc_m = 0x00002000,
2994 + ETHTX_td_b = 14,
2995 + ETHTX_td_m = 0x00004000,
2996 + ETHTX_crc_b = 15,
2997 + ETHTX_crc_m = 0x00008000,
2998 + ETHTX_le_b = 16,
2999 + ETHTX_le_m = 0x00010000,
3000 + ETHTX_cc_b = 17,
3001 + ETHTX_cc_m = 0x001E0000,
3002 +} ;
3003 +
3004 +#endif // __IDT_ETH_H__
3005 +
3006 +
3007 +
3008 +
3009 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
3010 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
3011 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-06-15 16:26:53.000000000 +0200
3012 @@ -0,0 +1,64 @@
3013 +#ifndef __IDT_ETH_V_H__
3014 +#define __IDT_ETH_V_H__
3015 +
3016 +/*******************************************************************************
3017 + *
3018 + * Copyright 2002 Integrated Device Technology, Inc.
3019 + * All rights reserved.
3020 + *
3021 + * Ethernet register definition.
3022 + *
3023 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3024 + *
3025 + * Author : Allen.Stichter@idt.com
3026 + * Date : 20020605
3027 + * Update :
3028 + * $Log: eth.h,v $
3029 + * Revision 1.3 2002/06/06 18:34:04 astichte
3030 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3031 + *
3032 + * Revision 1.2 2002/06/05 18:19:46 astichte
3033 + * Added
3034 + *
3035 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3036 + * jba File moved from vcode/include/idt/acacia
3037 + *
3038 + ******************************************************************************/
3039 +
3040 +#include <asm/rc32434/types.h>
3041 +#include <asm/rc32434/eth.h>
3042 +
3043 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
3044 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
3045 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
3046 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
3047 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
3048 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
3049 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
3050 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
3051 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
3052 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
3053 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
3054 +
3055 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
3056 +
3057 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
3058 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
3059 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
3060 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
3061 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
3062 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
3063 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
3064 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
3065 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
3066 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
3067 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
3068 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
3069 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
3070 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
3071 +#endif // __IDT_ETH_V_H__
3072 +
3073 +
3074 +
3075 +
3076 +
3077 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
3078 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
3079 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-06-15 16:26:53.000000000 +0200
3080 @@ -0,0 +1,182 @@
3081 +#ifndef __IDT_GPIO_H__
3082 +#define __IDT_GPIO_H__
3083 +
3084 +/*******************************************************************************
3085 + *
3086 + * Copyright 2002 Integrated Device Technology, Inc.
3087 + * All rights reserved.
3088 + *
3089 + * GPIO register definition.
3090 + *
3091 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3092 + *
3093 + * Author : ryan.holmQVist@idt.com
3094 + * Date : 20011005
3095 + * Update :
3096 + * $Log: gpio.h,v $
3097 + * Revision 1.2 2002/06/06 18:34:04 astichte
3098 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3099 + *
3100 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3101 + * jba File moved from vcode/include/idt/acacia
3102 + *
3103 + *
3104 + ******************************************************************************/
3105 +
3106 +#include <asm/rc32434/types.h>
3107 +enum
3108 +{
3109 + GPIO0_PhysicalAddress = 0x18050000,
3110 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
3111 +
3112 + GPIO0_VirtualAddress = 0xb8050000,
3113 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
3114 +} ;
3115 +
3116 +typedef struct
3117 +{
3118 + U32 gpiofunc; /* GPIO Function Register
3119 + * gpiofunc[x]==0 bit = gpio
3120 + * func[x]==1 bit = altfunc
3121 + */
3122 + U32 gpiocfg; /* GPIO Configuration Register
3123 + * gpiocfg[x]==0 bit = input
3124 + * gpiocfg[x]==1 bit = output
3125 + */
3126 + U32 gpiod; /* GPIO Data Register
3127 + * gpiod[x] read/write gpio pinX status
3128 + */
3129 + U32 gpioilevel; /* GPIO Interrupt Status Register
3130 + * interrupt level (see gpioistat)
3131 + */
3132 + U32 gpioistat; /* Gpio Interrupt Status Register
3133 + * istat[x] = (gpiod[x] == level[x])
3134 + * cleared in ISR (STICKY bits)
3135 + */
3136 + U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
3137 +} volatile * GPIO_t ;
3138 +
3139 +typedef enum
3140 +{
3141 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
3142 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
3143 + GPIO_input_v = 0, // gpiocfg use pin as input.
3144 + GPIO_output_v = 1, // gpiocfg use pin as output.
3145 + GPIO_pin0_b = 0,
3146 + GPIO_pin0_m = 0x00000001,
3147 + GPIO_pin1_b = 1,
3148 + GPIO_pin1_m = 0x00000002,
3149 + GPIO_pin2_b = 2,
3150 + GPIO_pin2_m = 0x00000004,
3151 + GPIO_pin3_b = 3,
3152 + GPIO_pin3_m = 0x00000008,
3153 + GPIO_pin4_b = 4,
3154 + GPIO_pin4_m = 0x00000010,
3155 + GPIO_pin5_b = 5,
3156 + GPIO_pin5_m = 0x00000020,
3157 + GPIO_pin6_b = 6,
3158 + GPIO_pin6_m = 0x00000040,
3159 + GPIO_pin7_b = 7,
3160 + GPIO_pin7_m = 0x00000080,
3161 + GPIO_pin8_b = 8,
3162 + GPIO_pin8_m = 0x00000100,
3163 + GPIO_pin9_b = 9,
3164 + GPIO_pin9_m = 0x00000200,
3165 + GPIO_pin10_b = 10,
3166 + GPIO_pin10_m = 0x00000400,
3167 + GPIO_pin11_b = 11,
3168 + GPIO_pin11_m = 0x00000800,
3169 + GPIO_pin12_b = 12,
3170 + GPIO_pin12_m = 0x00001000,
3171 + GPIO_pin13_b = 13,
3172 + GPIO_pin13_m = 0x00002000,
3173 + GPIO_pin14_b = 14,
3174 + GPIO_pin14_m = 0x00004000,
3175 + GPIO_pin15_b = 15,
3176 + GPIO_pin15_m = 0x00008000,
3177 + GPIO_pin16_b = 16,
3178 + GPIO_pin16_m = 0x00010000,
3179 + GPIO_pin17_b = 17,
3180 + GPIO_pin17_m = 0x00020000,
3181 + GPIO_pin18_b = 18,
3182 + GPIO_pin18_m = 0x00040000,
3183 + GPIO_pin19_b = 19,
3184 + GPIO_pin19_m = 0x00080000,
3185 + GPIO_pin20_b = 20,
3186 + GPIO_pin20_m = 0x00100000,
3187 + GPIO_pin21_b = 21,
3188 + GPIO_pin21_m = 0x00200000,
3189 + GPIO_pin22_b = 22,
3190 + GPIO_pin22_m = 0x00400000,
3191 + GPIO_pin23_b = 23,
3192 + GPIO_pin23_m = 0x00800000,
3193 + GPIO_pin24_b = 24,
3194 + GPIO_pin24_m = 0x01000000,
3195 + GPIO_pin25_b = 25,
3196 + GPIO_pin25_m = 0x02000000,
3197 + GPIO_pin26_b = 26,
3198 + GPIO_pin26_m = 0x04000000,
3199 + GPIO_pin27_b = 27,
3200 + GPIO_pin27_m = 0x08000000,
3201 + GPIO_pin28_b = 28,
3202 + GPIO_pin28_m = 0x10000000,
3203 + GPIO_pin29_b = 29,
3204 + GPIO_pin29_m = 0x20000000,
3205 + GPIO_pin30_b = 30,
3206 + GPIO_pin30_m = 0x40000000,
3207 + GPIO_pin31_b = 31,
3208 + GPIO_pin31_m = 0x80000000,
3209 +
3210 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
3211 +
3212 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
3213 + GPIO_u0sout_m = GPIO_pin0_m,
3214 + GPIO_u0sout_cfg_v = GPIO_output_v,
3215 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
3216 + GPIO_u0sinp_m = GPIO_pin1_m,
3217 + GPIO_u0sinp_cfg_v = GPIO_input_v,
3218 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
3219 + GPIO_u0rtsn_m = GPIO_pin2_m,
3220 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
3221 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
3222 + GPIO_u0ctsn_m = GPIO_pin3_m,
3223 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
3224 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
3225 + GPIO_maddr22_m = GPIO_pin4_m,
3226 + GPIO_maddr22_cfg_v = GPIO_output_v,
3227 +
3228 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
3229 + GPIO_maddr23_m = GPIO_pin5_m,
3230 + GPIO_maddr23_cfg_v = GPIO_output_v,
3231 +
3232 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
3233 + GPIO_maddr24_m = GPIO_pin6_m,
3234 + GPIO_maddr24_cfg_v = GPIO_output_v,
3235 +
3236 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
3237 + GPIO_maddr25_m = GPIO_pin7_m,
3238 + GPIO_maddr25_cfg_v = GPIO_output_v,
3239 +
3240 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
3241 + GPIO_cpu_m = GPIO_pin8_m,
3242 + GPIO_cpu_cfg_v = GPIO_output_v,
3243 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
3244 + GPIO_afspare6_m = GPIO_pin9_m,
3245 + GPIO_afspare6_cfg_v = GPIO_input_v,
3246 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
3247 + GPIO_afspare4_m = GPIO_pin10_m,
3248 + GPIO_afspare4_cfg_v = GPIO_input_v,
3249 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
3250 + GPIO_afspare3_m = GPIO_pin11_m,
3251 + GPIO_afspare3_cfg_v = GPIO_input_v,
3252 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
3253 + GPIO_afspare2_m = GPIO_pin12_m,
3254 + GPIO_afspare2_cfg_v = GPIO_input_v,
3255 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
3256 + GPIO_pcimuintn_m = GPIO_pin13_m,
3257 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
3258 +
3259 +} GPIO_DEFS_t;
3260 +
3261 +#endif // __IDT_GPIO_H__
3262 +
3263 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3264 --- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
3265 +++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-06-15 16:26:53.000000000 +0200
3266 @@ -0,0 +1,147 @@
3267 +#ifndef __IDT_I2C_H__
3268 +#define __IDT_I2C_H__
3269 +
3270 +/*******************************************************************************
3271 + *
3272 + * Copyright 2002 Integrated Device Technology, Inc.
3273 + * All rights reserved.
3274 + *
3275 + * I2C register definitions.
3276 + *
3277 + * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3278 + *
3279 + * Author : Allen.Stichter@idt.com
3280 + * Date : 20020120
3281 + * Update :
3282 + * $Log: i2c.h,v $
3283 + * Revision 1.2 2002/06/06 18:34:04 astichte
3284 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3285 + *
3286 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3287 + * jba File moved from vcode/include/idt/acacia
3288 + *
3289 + *
3290 + ******************************************************************************/
3291 +
3292 +#include <asm/rc32434/types.h>
3293 +
3294 +enum
3295 +{
3296 + I2C0_PhysicalAddress = 0x18068000,
3297 + I2C_PhysicalAddress = I2C0_PhysicalAddress,
3298 +
3299 + I2C0_VirtualAddress = 0xb8068000,
3300 + I2C_VirtualAddress = I2C0_VirtualAddress,
3301 +} ;
3302 +
3303 +typedef struct
3304 +{
3305 + U32 i2cc ;
3306 + U32 i2cdi ;
3307 + U32 i2cdo ;
3308 + U32 i2ccp ; // I2C clk = ICLK / div / 8
3309 + U32 i2cmcmd ;
3310 + U32 i2cms ;
3311 + U32 i2cmsm ;
3312 + U32 i2css ;
3313 + U32 i2cssm ;
3314 + U32 i2csaddr ;
3315 + U32 i2csack ;
3316 +} volatile * I2C_t ;
3317 +enum
3318 +{
3319 + I2CC_men_b = 0, // In I2C-> i2cc
3320 + I2CC_men_m = 0x00000001,
3321 + I2CC_sen_b = 1, // In I2C-> i2cc
3322 + I2CC_sen_m = 0x00000002,
3323 + I2CC_iom_b = 2, // In I2C-> i2cc
3324 + I2CC_iom_m = 0x00000004,
3325 +
3326 + I2CDI_data_b = 0, // In I2C-> i2cdi
3327 + I2CDI_data_m = 0x000000ff,
3328 +
3329 + I2CDO_data_b = 0, // In I2C-> i2cdo
3330 + I2CDO_data_m = 0x000000ff,
3331 +
3332 + I2CCP_div_b = 0, // In I2C-> i2ccp
3333 + I2CCP_div_m = 0x0000ffff,
3334 +
3335 + I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
3336 + I2CMCMD_cmd_m = 0x0000000f,
3337 + I2CMCMD_cmd_nop_v = 0,
3338 + I2CMCMD_cmd_start_v = 1,
3339 + I2CMCMD_cmd_stop_v = 2,
3340 + I2CMCMD_cmd_res3_v = 3,
3341 + I2CMCMD_cmd_rd_v = 4,
3342 + I2CMCMD_cmd_rdack_v = 5,
3343 + I2CMCMD_cmd_wd_v = 6,
3344 + I2CMCMD_cmd_wdack_v = 7,
3345 + I2CMCMD_cmd_res8_v = 8,
3346 + I2CMCMD_cmd_res9_v = 9,
3347 + I2CMCMD_cmd_res10_v = 10,
3348 + I2CMCMD_cmd_res11_v = 11,
3349 + I2CMCMD_cmd_res12_v = 12,
3350 + I2CMCMD_cmd_res13_v = 13,
3351 + I2CMCMD_cmd_res14_v = 14,
3352 + I2CMCMD_cmd_res15_v = 15,
3353 +
3354 + I2CMS_d_b = 0, // In I2C-> i2cms
3355 + I2CMS_d_m = 0x00000001,
3356 + I2CMS_na_b = 1, // In I2C-> i2cms
3357 + I2CMS_na_m = 0x00000002,
3358 + I2CMS_la_b = 2, // In I2C-> i2cms
3359 + I2CMS_la_m = 0x00000004,
3360 + I2CMS_err_b = 3, // In I2C-> i2cms
3361 + I2CMS_err_m = 0x00000008,
3362 +
3363 + I2CMSM_d_b = 0, // In I2C-> i2cmsm
3364 + I2CMSM_d_m = 0x00000001,
3365 + I2CMSM_na_b = 1, // In I2C-> i2cmsm
3366 + I2CMSM_na_m = 0x00000002,
3367 + I2CMSM_la_b = 2, // In I2C-> i2cmsm
3368 + I2CMSM_la_m = 0x00000004,
3369 + I2CMSM_err_b = 3, // In I2C-> i2cmsm
3370 + I2CMSM_err_m = 0x00000008,
3371 +
3372 + I2CSS_rr_b = 0, // In I2C-> i2css
3373 + I2CSS_rr_m = 0x00000001,
3374 + I2CSS_wr_b = 1, // In I2C-> i2css
3375 + I2CSS_wr_m = 0x00000002,
3376 + I2CSS_sa_b = 2, // In I2C-> i2css
3377 + I2CSS_sa_m = 0x00000004,
3378 + I2CSS_tf_b = 3, // In I2C-> i2css
3379 + I2CSS_tf_m = 0x00000008,
3380 + I2CSS_gc_b = 4, // In I2C-> i2css
3381 + I2CSS_gc_m = 0x00000010,
3382 + I2CSS_na_b = 5, // In I2C-> i2css
3383 + I2CSS_na_m = 0x00000020,
3384 + I2CSS_err_b = 6, // In I2C-> i2css
3385 + I2CSS_err_m = 0x00000040,
3386 +
3387 + I2CSSM_rr_b = 0, // In I2C-> i2cssm
3388 + I2CSSM_rr_m = 0x00000001,
3389 + I2CSSM_wr_b = 1, // In I2C-> i2cssm
3390 + I2CSSM_wr_m = 0x00000002,
3391 + I2CSSM_sa_b = 2, // In I2C-> i2cssm
3392 + I2CSSM_sa_m = 0x00000004,
3393 + I2CSSM_tf_b = 3, // In I2C-> i2cssm
3394 + I2CSSM_tf_m = 0x00000008,
3395 + I2CSSM_gc_b = 4, // In I2C-> i2cssm
3396 + I2CSSM_gc_m = 0x00000010,
3397 + I2CSSM_na_b = 5, // In I2C-> i2cssm
3398 + I2CSSM_na_m = 0x00000020,
3399 + I2CSSM_err_b = 6, // In I2C-> i2cssm
3400 + I2CSSM_err_m = 0x00000040,
3401 +
3402 + I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
3403 + I2CSADDR_addr_m = 0x000003ff,
3404 + I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
3405 + I2CSADDR_a_gc_m = 0x00000400,
3406 + I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
3407 + I2CSADDR_a10_m = 0x00000800,
3408 +
3409 + I2CSACK_ack_b = 0, // In I2C-> i2csack
3410 + I2CSACK_ack_m = 0x00000001,
3411 +
3412 +} ;
3413 +#endif // __IDT_I2C_H__
3414 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3415 --- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
3416 +++ linux.dev/include/asm-mips/rc32434/integ.h 2006-06-15 16:26:53.000000000 +0200
3417 @@ -0,0 +1,78 @@
3418 +#ifndef __IDT_INTEG_H__
3419 +#define __IDT_INTEG_H__
3420 +
3421 +/*******************************************************************************
3422 + *
3423 + * Copyright 2002 Integrated Device Technology, Inc.
3424 + * All rights reserved.
3425 + *
3426 + * System Integrity register definition.
3427 + *
3428 + * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3429 + *
3430 + * Author : ryan.holmQVist@idt.com
3431 + * Date : 20011005
3432 + * Update :
3433 + * $Log: integ.h,v $
3434 + * Revision 1.3 2002/06/06 18:34:04 astichte
3435 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3436 + *
3437 + * Revision 1.2 2002/06/05 18:32:33 astichte
3438 + * Removed IDTField
3439 + *
3440 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3441 + * jba File moved from vcode/include/idt/acacia
3442 + *
3443 + ******************************************************************************/
3444 +
3445 +#include <asm/rc32434/types.h>
3446 +
3447 +enum
3448 +{
3449 + INTEG0_PhysicalAddress = 0x18030000,
3450 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
3451 +
3452 + INTEG0_VirtualAddress = 0xb8030000,
3453 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
3454 +} ;
3455 +
3456 +// if you are looing for CEA, try rst.h
3457 +typedef struct
3458 +{
3459 + U32 filler [0xc] ; // 0x30 bytes unused.
3460 + U32 errcs ; // sticky use ERRCS_
3461 + U32 wtcount ; // Watchdog timer count reg.
3462 + U32 wtcompare ; // Watchdog timer timeout value.
3463 + U32 wtc ; // Watchdog timer control. use WTC_
3464 +} volatile *INTEG_t ;
3465 +
3466 +enum
3467 +{
3468 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
3469 + ERRCS_wto_m = 0x00000001,
3470 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
3471 + ERRCS_wne_m = 0x00000002,
3472 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
3473 + ERRCS_ucw_m = 0x00000004,
3474 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
3475 + ERRCS_ucr_m = 0x00000008,
3476 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
3477 + ERRCS_upw_m = 0x00000010,
3478 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
3479 + ERRCS_upr_m = 0x00000020,
3480 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
3481 + ERRCS_udw_m = 0x00000040,
3482 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
3483 + ERRCS_udr_m = 0x00000080,
3484 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
3485 + ERRCS_sae_m = 0x00000100,
3486 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
3487 + ERRCS_wre_m = 0x00000200,
3488 +
3489 + WTC_en_b = 0, // In INTEG_t -> wtc
3490 + WTC_en_m = 0x00000001,
3491 + WTC_to_b = 1, // In INTEG_t -> wtc
3492 + WTC_to_m = 0x00000002,
3493 +} ;
3494 +
3495 +#endif // __IDT_INTEG_H__
3496 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3497 --- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
3498 +++ linux.dev/include/asm-mips/rc32434/int.h 2006-06-15 16:26:53.000000000 +0200
3499 @@ -0,0 +1,167 @@
3500 +#ifndef __IDT_INT_H__
3501 +#define __IDT_INT_H__
3502 +
3503 +/*******************************************************************************
3504 + *
3505 + * Copyright 2002 Integrated Device Technology, Inc.
3506 + * All rights reserved.
3507 + *
3508 + * Interrupt Controller register definition.
3509 + *
3510 + * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3511 + *
3512 + * Author : ryan.holmqvist@idt.com
3513 + * Date : 20011005
3514 + * Update :
3515 + * $Log: int.h,v $
3516 + * Revision 1.3 2002/06/06 18:34:04 astichte
3517 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3518 + *
3519 + * Revision 1.2 2002/06/05 18:47:33 astichte
3520 + * Removed IDTField
3521 + *
3522 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3523 + * jba File moved from vcode/include/idt/acacia
3524 + *
3525 + *
3526 + ******************************************************************************/
3527 +
3528 +#include <asm/rc32434/types.h>
3529 +
3530 +enum
3531 +{
3532 + INT0_PhysicalAddress = 0x18038000,
3533 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
3534 +
3535 + INT0_VirtualAddress = 0xb8038000,
3536 + INT_VirtualAddress = INT0_VirtualAddress, // Default
3537 +} ;
3538 +
3539 +struct INT_s
3540 +{
3541 + U32 ipend ; //Pending interrupts. use INT?_
3542 + U32 itest ; //Test bits. use INT?_
3543 + U32 imask ; //Interrupt disabled when set. use INT?_
3544 +} ;
3545 +
3546 +enum
3547 +{
3548 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
3549 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
3550 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
3551 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
3552 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
3553 +
3554 + IPEND_count, // must be last (used in loops)
3555 + IPEND_min = IPEND2 // min IPEND (used in loops)
3556 +};
3557 +
3558 +typedef struct INTC_s
3559 +{
3560 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
3561 + U32 nmips ; // use NMIPS_
3562 +} volatile *INT_t ;
3563 +
3564 +enum
3565 +{
3566 + INT2_timer0_b = 0,
3567 + INT2_timer0_m = 0x00000001,
3568 + INT2_timer1_b = 1,
3569 + INT2_timer1_m = 0x00000002,
3570 + INT2_timer2_b = 2,
3571 + INT2_timer2_m = 0x00000004,
3572 + INT2_refresh_b = 3,
3573 + INT2_refresh_m = 0x00000008,
3574 + INT2_watchdogTimeout_b = 4,
3575 + INT2_watchdogTimeout_m = 0x00000010,
3576 + INT2_undecodedCpuWrite_b = 5,
3577 + INT2_undecodedCpuWrite_m = 0x00000020,
3578 + INT2_undecodedCpuRead_b = 6,
3579 + INT2_undecodedCpuRead_m = 0x00000040,
3580 + INT2_undecodedPciWrite_b = 7,
3581 + INT2_undecodedPciWrite_m = 0x00000080,
3582 + INT2_undecodedPciRead_b = 8,
3583 + INT2_undecodedPciRead_m = 0x00000100,
3584 + INT2_undecodedDmaWrite_b = 9,
3585 + INT2_undecodedDmaWrite_m = 0x00000200,
3586 + INT2_undecodedDmaRead_b = 10,
3587 + INT2_undecodedDmaRead_m = 0x00000400,
3588 + INT2_ipBusSlaveAckError_b = 11,
3589 + INT2_ipBusSlaveAckError_m = 0x00000800,
3590 +
3591 + INT3_dmaChannel0_b = 0,
3592 + INT3_dmaChannel0_m = 0x00000001,
3593 + INT3_dmaChannel1_b = 1,
3594 + INT3_dmaChannel1_m = 0x00000002,
3595 + INT3_dmaChannel2_b = 2,
3596 + INT3_dmaChannel2_m = 0x00000004,
3597 + INT3_dmaChannel3_b = 3,
3598 + INT3_dmaChannel3_m = 0x00000008,
3599 + INT3_dmaChannel4_b = 4,
3600 + INT3_dmaChannel4_m = 0x00000010,
3601 + INT3_dmaChannel5_b = 5,
3602 + INT3_dmaChannel5_m = 0x00000020,
3603 +
3604 + INT5_uartGeneral0_b = 0,
3605 + INT5_uartGeneral0_m = 0x00000001,
3606 + INT5_uartTxrdy0_b = 1,
3607 + INT5_uartTxrdy0_m = 0x00000002,
3608 + INT5_uartRxrdy0_b = 2,
3609 + INT5_uartRxrdy0_m = 0x00000004,
3610 + INT5_pci_b = 3,
3611 + INT5_pci_m = 0x00000008,
3612 + INT5_pciDecoupled_b = 4,
3613 + INT5_pciDecoupled_m = 0x00000010,
3614 + INT5_spi_b = 5,
3615 + INT5_spi_m = 0x00000020,
3616 + INT5_deviceDecoupled_b = 6,
3617 + INT5_deviceDecoupled_m = 0x00000040,
3618 + INT5_i2cMaster_b = 7,
3619 + INT5_i2cMaster_m = 0x00000080,
3620 + INT5_i2cSlave_b = 8,
3621 + INT5_i2cSlave_m = 0x00000100,
3622 + INT5_ethOvr_b = 9,
3623 + INT5_ethOvr_m = 0x00000200,
3624 + INT5_ethUnd_b = 10,
3625 + INT5_ethUnd_m = 0x00000400,
3626 + INT5_ethPfd_b = 11,
3627 + INT5_ethPfd_m = 0x00000800,
3628 + INT5_nvram_b = 12,
3629 + INT5_nvram_m = 0x00001000,
3630 +
3631 + INT6_gpio0_b = 0,
3632 + INT6_gpio0_m = 0x00000001,
3633 + INT6_gpio1_b = 1,
3634 + INT6_gpio1_m = 0x00000002,
3635 + INT6_gpio2_b = 2,
3636 + INT6_gpio2_m = 0x00000004,
3637 + INT6_gpio3_b = 3,
3638 + INT6_gpio3_m = 0x00000008,
3639 + INT6_gpio4_b = 4,
3640 + INT6_gpio4_m = 0x00000010,
3641 + INT6_gpio5_b = 5,
3642 + INT6_gpio5_m = 0x00000020,
3643 + INT6_gpio6_b = 6,
3644 + INT6_gpio6_m = 0x00000040,
3645 + INT6_gpio7_b = 7,
3646 + INT6_gpio7_m = 0x00000080,
3647 + INT6_gpio8_b = 8,
3648 + INT6_gpio8_m = 0x00000100,
3649 + INT6_gpio9_b = 9,
3650 + INT6_gpio9_m = 0x00000200,
3651 + INT6_gpio10_b = 10,
3652 + INT6_gpio10_m = 0x00000400,
3653 + INT6_gpio11_b = 11,
3654 + INT6_gpio11_m = 0x00000800,
3655 + INT6_gpio12_b = 12,
3656 + INT6_gpio12_m = 0x00001000,
3657 + INT6_gpio13_b = 13,
3658 + INT6_gpio13_m = 0x00002000,
3659 +
3660 + NMIPS_gpio_b = 0,
3661 + NMIPS_gpio_m = 0x00000001,
3662 +} ;
3663 +
3664 +#endif // __IDT_INT_H__
3665 +
3666 +
3667 diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
3668 --- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
3669 +++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-06-15 16:26:53.000000000 +0200
3670 @@ -0,0 +1,95 @@
3671 +#ifndef __IDT_IPARB_H__
3672 +#define __IDT_IPARB_H__
3673 +
3674 +/*******************************************************************************
3675 + *
3676 + * Copyright 2002 Integrated Device Technology, Inc.
3677 + * All rights reserved.
3678 + *
3679 + * IP Arbiter register definitions.
3680 + *
3681 + * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3682 + *
3683 + * Author : Allen.Stichter@idt.com
3684 + * Date : 20020120
3685 + * Update :
3686 + * $Log: iparb.h,v $
3687 + * Revision 1.3 2002/06/06 18:34:04 astichte
3688 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3689 + *
3690 + * Revision 1.2 2002/06/05 19:01:42 astichte
3691 + * Removed IDTField
3692 + *
3693 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3694 + * jba File moved from vcode/include/idt/acacia
3695 + *
3696 + ******************************************************************************/
3697 +
3698 +#include <asm/rc32434/types.h>
3699 +
3700 +enum
3701 +{
3702 + IPARB0_PhysicalAddress = 0x18048000,
3703 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
3704 +
3705 + IPARB0_VirtualAddress = 0xb8048000,
3706 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
3707 +} ;
3708 +
3709 +enum
3710 +{
3711 + IPABMXC_ethernetReceive = 0,
3712 + IPABMXC_ethernetTransmit = 1,
3713 + IPABMXC_memoryToHoldFifo = 2,
3714 + IPABMXC_holdFifoToMemory = 3,
3715 + IPABMXC_pciToMemory = 4,
3716 + IPABMXC_memoryToPci = 5,
3717 + IPABMXC_pciTarget = 6,
3718 + IPABMXC_pciTargetStart = 7,
3719 + IPABMXC_cpuToIpBus = 8,
3720 +
3721 + IPABMXC_Count, // Must be last in list !
3722 + IPABMXC_Min = IPABMXC_ethernetReceive,
3723 +
3724 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
3725 +} ;
3726 +
3727 +typedef struct
3728 +{
3729 + U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
3730 + U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
3731 + U32 ipac ; // use IPAC_
3732 + U32 ipaitcc; // use IPAITCC_
3733 + U32 ipaspare ;
3734 +} volatile * IPARB_t ;
3735 +
3736 +enum
3737 +{
3738 + IPAC_dwm_b = 2,
3739 + IPAC_dwm_m = 0x00000004,
3740 + IPAC_drm_b = 3,
3741 + IPAC_drm_m = 0x00000008,
3742 + IPAC_msk_b = 4,
3743 + IPAC_msk_m = 0x00000010,
3744 +
3745 + IPAPC_ptc_b = 0,
3746 + IPAPC_ptc_m = 0x00003fff,
3747 + IPAPC_mf_b = 14,
3748 + IPAPC_mf_m = 0x00004000,
3749 + IPAPC_cptc_b = 16,
3750 + IPAPC_cptc_m = 0x3fff0000,
3751 +
3752 + IPAITCC_itcc = 0,
3753 + IPAITCC_itcc, = 0x000001ff,
3754 +
3755 + IPABMC_mtc_b = 0,
3756 + IPABMC_mtc_m = 0x00000fff,
3757 + IPABMC_p_b = 12,
3758 + IPABMC_p_m = 0x00003000,
3759 + IPABMC_msk_b = 14,
3760 + IPABMC_msk_m = 0x00004000,
3761 + IPABMC_cmtc_b = 16,
3762 + IPABMC_cmtc_m = 0x0fff0000,
3763 +};
3764 +
3765 +#endif // __IDT_IPARB_H__
3766 diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
3767 --- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
3768 +++ linux.dev/include/asm-mips/rc32434/irm.h 2006-06-15 16:26:53.000000000 +0200
3769 @@ -0,0 +1,55 @@
3770 +#ifndef __IDT_IRM_H__
3771 +#define __IDT_IRM_H__
3772 +
3773 +/*******************************************************************************
3774 + *
3775 + * Copyright 2002 Integrated Device Technology, Inc.
3776 + * All rights reserved.
3777 + *
3778 + * Internal Register Map
3779 + *
3780 + * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
3781 + *
3782 + * Author : Allen.Stichter@idt.com
3783 + * Date : 20020605
3784 + * Update :
3785 + * $Log: irm.h,v $
3786 + * Revision 1.2 2002/06/05 14:51:06 astichte
3787 + * *** empty log message ***
3788 + *
3789 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3790 + * jba File moved from vcode/include/idt/acacia
3791 + *
3792 + ******************************************************************************/
3793 +
3794 +/*
3795 + * NOTE --
3796 + * This file is here for backwards compatibility.
3797 + * DO NOT USE !!!!
3798 + */
3799 +
3800 +typedef enum
3801 +{
3802 + IRM_Physical = 0x18000000, // Internal Reg. map physical.
3803 + RST_Offset = 0x00000000, // Includes sysid and RST.
3804 + DEV_Offset = 0x00010000, // Device Controller 0.
3805 + DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
3806 + PMARB_Offset = 0x00020000, // PM bus arbiter.
3807 + TIM_Offset = 0x00028000, // Counter / timer.
3808 + INTEG_Offset = 0x00030000, // System Integrity.
3809 + INT_Offset = 0x00038000, // Interrupt controller.
3810 + DMA_Offset = 0x00040000, // DMA.
3811 + IPARB_Offset = 0x00044000, // IP bus arbiter.
3812 + GPIO_Offset = 0x00050000, // GPIO.
3813 + UART_Offset = 0x00058000, // UART
3814 + ETH_Offset = 0x00060000, // Ethernet 1.
3815 + I2C_Offset = 0x00068000, // I2C interface.
3816 + SPI_Offset = 0x00070000, // Serial Peripheral Interface.
3817 + NVRAM_Offset = 0x00078000, // NVRAM interface
3818 + AUTH_Offset = 0x0007c000, // Authorization unit
3819 + PCI_Offset = 0x00080000,
3820 + CROM_Offset = 0x000b8000, // Configuration ROM.
3821 + IRM_Size = 0x00200000, // Internal Reg. map size.
3822 +} IRM_Offset_t ;
3823 +
3824 +#endif // __IDT_IRM_H__
3825 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
3826 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
3827 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-06-15 16:26:53.000000000 +0200
3828 @@ -0,0 +1,8 @@
3829 +#ifndef __ASM_MACH_MIPS_IRQ_H
3830 +#define __ASM_MACH_MIPS_IRQ_H
3831 +
3832 +#include <linux/config.h>
3833 +
3834 +#define NR_IRQS 256
3835 +
3836 +#endif /* __ASM_MACH_MIPS_IRQ_H */
3837 diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
3838 --- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
3839 +++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-06-15 16:26:53.000000000 +0200
3840 @@ -0,0 +1,97 @@
3841 +#ifndef __IDT_NVRAM_H
3842 +#define __IDT_NVRAM_H
3843 +
3844 +/*******************************************************************************
3845 + *
3846 + * Copyright 2002 Integrated Device Technology, Inc.
3847 + * All rights reserved.
3848 + *
3849 + * IP Arbiter register definitions.
3850 + *
3851 + * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
3852 + *
3853 + * Author : kiran.rao@idt.com
3854 + * Date : 20030724
3855 + * Update :
3856 + * $Log: nvram.h,v $
3857 + *
3858 + *
3859 + ******************************************************************************/
3860 +#include <asm/rc32434/tpes.h>
3861 +
3862 +
3863 +enum
3864 +{
3865 + NVRAM0_PhysicalAddress = 0xba000000,
3866 + NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
3867 +
3868 + NVRAM0_VirtualAddress = 0xba000000,
3869 + NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
3870 +} ;
3871 +
3872 +enum
3873 +{
3874 + NVRCMD_cmd_b = 0,
3875 + NVRCMD_cmd_m = 0x0000007f,
3876 +
3877 + NVRS_r_b = 0,
3878 + NVRS_r_m = 0x00000001,
3879 + NVRS_e_b = 1,
3880 + NVRS_e_m = 0x00000002,
3881 + NVRS_k_b = 2,
3882 + NVRS_k_m = 0x00000004,
3883 +
3884 + NVRSM_r_b = 0,
3885 + NVRSM_r_m = 0x00000001,
3886 + NVRSM_e_b = 1,
3887 + NVRSM_e_m = 0x00000002,
3888 + NVRSM_k_b = 2,
3889 + NVRSM_k_m = 0x00000004,
3890 +
3891 + NVRCFG0_pwidth_b = 0,
3892 + NVRCFG0_pwidth_m = 0x00000003,
3893 + NVRCFG0_nmax_b = 2,
3894 + NVRCFG0_nmax_m = 0x0000000C,
3895 + NVRCFG0_vppl_b = 4,
3896 + NVRCFG0_vppl_m = 0x000000f0,
3897 + NVRCFG0_vppm_b = 8,
3898 + NVRCFG0_vppm_m = 0x00000300,
3899 + NVRCFG0_dvpp_b = 10,
3900 + NVRCFG0_dvpp_m = 0x00000c00,
3901 + NVRCFG0_x_b = 12,
3902 + NVRCFG0_x_m = 0x00007000,
3903 +
3904 + NVRCFG1_t1tecc_b = 0,
3905 + NVRCFG1_t1tecc_m = 0x00000003,
3906 + NVRCFG1_t1mrcl_b = 2,
3907 + NVRCFG1_t1mrcl_m = 0x0000000c,
3908 + NVRCFG1_t1bias_b = 4,
3909 + NVRCFG1_t1bias_m = 0x00000030,
3910 + NVRCFG1_t2tecc_b = 6,
3911 + NVRCFG1_t2tecc_m = 0x000000c0,
3912 + NVRCFG1_t2mrcl_b = 8,
3913 + NVRCFG1_t2mrcl_m = 0x00000300,
3914 + NVRCFG1_t2bias_b = 10,
3915 + NVRCFG1_t2bias_m = 0x00000c00,
3916 + NVRCFG1_t3tecc_b = 12,
3917 + NVRCFG1_t3tecc_m = 0x00003000,
3918 + NVRCFG1_t3mrcl_b = 14,
3919 + NVRCFG1_t3mrcl_m = 0x0000c000,
3920 + NVRCFG1_t3bias_b = 16,
3921 + NVRCFG1_t3bias_m = 0x00030000,
3922 + NVRCFG1_t4tecc_b = 18,
3923 + NVRCFG1_t4tecc_m = 0x000c0000,
3924 + NVRCFG1_t4mrcl_b = 20,
3925 + NVRCFG1_t4mrcl_m = 0x00300000,
3926 + NVRCFG1_t4bias_b = 22,
3927 + NVRCFG1_t4bias_m = 0x00c00000,
3928 + NVRCFG1_t5tecc_b = 24,
3929 + NVRCFG1_t5tecc_m = 0x03000000,
3930 + NVRCFG1_t5mrcl_b = 26,
3931 + NVRCFG1_t5mrcl_m = 0x0c000000,
3932 + NVRCFG1_t5bias_b = 28,
3933 + NVRCFG1_t5bias_m = 0x30000000,
3934 +}
3935 +
3936 +#endif // __IDT_NVRAM_H__
3937 +
3938 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
3939 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
3940 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-06-15 16:26:53.000000000 +0200
3941 @@ -0,0 +1,695 @@
3942 +/**************************************************************************
3943 + *
3944 + * BRIEF MODULE DESCRIPTION
3945 + * PCI register definitio
3946 + *
3947 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3948 + *
3949 + * This program is free software; you can redistribute it and/or modify it
3950 + * under the terms of the GNU General Public License as published by the
3951 + * Free Software Foundation; either version 2 of the License, or (at your
3952 + * option) any later version.
3953 + *
3954 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3955 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3956 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3957 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3958 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3959 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3960 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3961 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3962 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3963 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3964 + *
3965 + * You should have received a copy of the GNU General Public License along
3966 + * with this program; if not, write to the Free Software Foundation, Inc.,
3967 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3968 + *
3969 + *
3970 + **************************************************************************
3971 + * May 2004 rkt, neb.
3972 + *
3973 + * Initial Release
3974 + *
3975 + *
3976 + *
3977 + **************************************************************************
3978 + */
3979 +
3980 +#ifndef __IDT_PCI_H__
3981 +#define __IDT_PCI_H__
3982 +
3983 +enum
3984 +{
3985 + PCI0_PhysicalAddress = 0x18080000,
3986 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
3987 +
3988 + PCI0_VirtualAddress = 0xB8080000,
3989 + PCI_VirtualAddress = PCI0_VirtualAddress,
3990 +} ;
3991 +
3992 +enum
3993 +{
3994 + PCI_LbaCount = 4, // Local base addresses.
3995 +} ;
3996 +
3997 +typedef struct
3998 +{
3999 + u32 a ; // Address.
4000 + u32 c ; // Control.
4001 + u32 m ; // mapping.
4002 +} PCI_Map_s ;
4003 +
4004 +typedef struct
4005 +{
4006 + u32 pcic ;
4007 + u32 pcis ;
4008 + u32 pcism ;
4009 + u32 pcicfga ;
4010 + u32 pcicfgd ;
4011 + PCI_Map_s pcilba [PCI_LbaCount] ;
4012 + u32 pcidac ;
4013 + u32 pcidas ;
4014 + u32 pcidasm ;
4015 + u32 pcidad ;
4016 + u32 pcidma8c ;
4017 + u32 pcidma9c ;
4018 + u32 pcitc ;
4019 +} volatile *PCI_t ;
4020 +
4021 +// PCI messaging unit.
4022 +enum
4023 +{
4024 + PCIM_Count = 2,
4025 +} ;
4026 +typedef struct
4027 +{
4028 + u32 pciim [PCIM_Count] ;
4029 + u32 pciom [PCIM_Count] ;
4030 + u32 pciid ;
4031 + u32 pciiic ;
4032 + u32 pciiim ;
4033 + u32 pciiod ;
4034 + u32 pciioic ;
4035 + u32 pciioim ;
4036 +} volatile *PCIM_t ;
4037 +
4038 +/*******************************************************************************
4039 + *
4040 + * PCI Control Register
4041 + *
4042 + ******************************************************************************/
4043 +enum
4044 +{
4045 + PCIC_en_b = 0,
4046 + PCIC_en_m = 0x00000001,
4047 + PCIC_tnr_b = 1,
4048 + PCIC_tnr_m = 0x00000002,
4049 + PCIC_sce_b = 2,
4050 + PCIC_sce_m = 0x00000004,
4051 + PCIC_ien_b = 3,
4052 + PCIC_ien_m = 0x00000008,
4053 + PCIC_aaa_b = 4,
4054 + PCIC_aaa_m = 0x00000010,
4055 + PCIC_eap_b = 5,
4056 + PCIC_eap_m = 0x00000020,
4057 + PCIC_pcim_b = 6,
4058 + PCIC_pcim_m = 0x000001c0,
4059 + PCIC_pcim_disabled_v = 0,
4060 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
4061 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
4062 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
4063 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
4064 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
4065 + PCIC_pcim_reserved6_v = 6,
4066 + PCIC_pcim_reserved7_v = 7,
4067 + PCIC_igm_b = 9,
4068 + PCIC_igm_m = 0x00000200,
4069 +} ;
4070 +
4071 +/*******************************************************************************
4072 + *
4073 + * PCI Status Register
4074 + *
4075 + ******************************************************************************/
4076 +enum {
4077 + PCIS_eed_b = 0,
4078 + PCIS_eed_m = 0x00000001,
4079 + PCIS_wr_b = 1,
4080 + PCIS_wr_m = 0x00000002,
4081 + PCIS_nmi_b = 2,
4082 + PCIS_nmi_m = 0x00000004,
4083 + PCIS_ii_b = 3,
4084 + PCIS_ii_m = 0x00000008,
4085 + PCIS_cwe_b = 4,
4086 + PCIS_cwe_m = 0x00000010,
4087 + PCIS_cre_b = 5,
4088 + PCIS_cre_m = 0x00000020,
4089 + PCIS_mdpe_b = 6,
4090 + PCIS_mdpe_m = 0x00000040,
4091 + PCIS_sta_b = 7,
4092 + PCIS_sta_m = 0x00000080,
4093 + PCIS_rta_b = 8,
4094 + PCIS_rta_m = 0x00000100,
4095 + PCIS_rma_b = 9,
4096 + PCIS_rma_m = 0x00000200,
4097 + PCIS_sse_b = 10,
4098 + PCIS_sse_m = 0x00000400,
4099 + PCIS_ose_b = 11,
4100 + PCIS_ose_m = 0x00000800,
4101 + PCIS_pe_b = 12,
4102 + PCIS_pe_m = 0x00001000,
4103 + PCIS_tae_b = 13,
4104 + PCIS_tae_m = 0x00002000,
4105 + PCIS_rle_b = 14,
4106 + PCIS_rle_m = 0x00004000,
4107 + PCIS_bme_b = 15,
4108 + PCIS_bme_m = 0x00008000,
4109 + PCIS_prd_b = 16,
4110 + PCIS_prd_m = 0x00010000,
4111 + PCIS_rip_b = 17,
4112 + PCIS_rip_m = 0x00020000,
4113 +} ;
4114 +
4115 +/*******************************************************************************
4116 + *
4117 + * PCI Status Mask Register
4118 + *
4119 + ******************************************************************************/
4120 +enum {
4121 + PCISM_eed_b = 0,
4122 + PCISM_eed_m = 0x00000001,
4123 + PCISM_wr_b = 1,
4124 + PCISM_wr_m = 0x00000002,
4125 + PCISM_nmi_b = 2,
4126 + PCISM_nmi_m = 0x00000004,
4127 + PCISM_ii_b = 3,
4128 + PCISM_ii_m = 0x00000008,
4129 + PCISM_cwe_b = 4,
4130 + PCISM_cwe_m = 0x00000010,
4131 + PCISM_cre_b = 5,
4132 + PCISM_cre_m = 0x00000020,
4133 + PCISM_mdpe_b = 6,
4134 + PCISM_mdpe_m = 0x00000040,
4135 + PCISM_sta_b = 7,
4136 + PCISM_sta_m = 0x00000080,
4137 + PCISM_rta_b = 8,
4138 + PCISM_rta_m = 0x00000100,
4139 + PCISM_rma_b = 9,
4140 + PCISM_rma_m = 0x00000200,
4141 + PCISM_sse_b = 10,
4142 + PCISM_sse_m = 0x00000400,
4143 + PCISM_ose_b = 11,
4144 + PCISM_ose_m = 0x00000800,
4145 + PCISM_pe_b = 12,
4146 + PCISM_pe_m = 0x00001000,
4147 + PCISM_tae_b = 13,
4148 + PCISM_tae_m = 0x00002000,
4149 + PCISM_rle_b = 14,
4150 + PCISM_rle_m = 0x00004000,
4151 + PCISM_bme_b = 15,
4152 + PCISM_bme_m = 0x00008000,
4153 + PCISM_prd_b = 16,
4154 + PCISM_prd_m = 0x00010000,
4155 + PCISM_rip_b = 17,
4156 + PCISM_rip_m = 0x00020000,
4157 +} ;
4158 +
4159 +/*******************************************************************************
4160 + *
4161 + * PCI Configuration Address Register
4162 + *
4163 + ******************************************************************************/
4164 +enum {
4165 + PCICFGA_reg_b = 2,
4166 + PCICFGA_reg_m = 0x000000fc,
4167 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
4168 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
4169 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
4170 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
4171 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
4172 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
4173 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
4174 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
4175 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
4176 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
4177 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
4178 + PCICFGA_reg_pba0m_v = 0x48>>2,
4179 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
4180 + PCICFGA_reg_pba1m_v = 0x50>>2,
4181 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
4182 + PCICFGA_reg_pba2m_v = 0x58>>2,
4183 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
4184 + PCICFGA_reg_pba3m_v = 0x60>>2,
4185 + PCICFGA_reg_pmgt_v = 0x64>>2,
4186 + PCICFGA_func_b = 8,
4187 + PCICFGA_func_m = 0x00000700,
4188 + PCICFGA_dev_b = 11,
4189 + PCICFGA_dev_m = 0x0000f800,
4190 + PCICFGA_dev_internal_v = 0,
4191 + PCICFGA_bus_b = 16,
4192 + PCICFGA_bus_m = 0x00ff0000,
4193 + PCICFGA_bus_type0_v = 0, //local bus
4194 + PCICFGA_en_b = 31, // read only
4195 + PCICFGA_en_m = 0x80000000,
4196 +} ;
4197 +
4198 +enum {
4199 + PCFGID_vendor_b = 0,
4200 + PCFGID_vendor_m = 0x0000ffff,
4201 + PCFGID_vendor_IDT_v = 0x111d,
4202 + PCFGID_device_b = 16,
4203 + PCFGID_device_m = 0xffff0000,
4204 + PCFGID_device_Korinade_v = 0x0214,
4205 +
4206 + PCFG04_command_ioena_b = 1,
4207 + PCFG04_command_ioena_m = 0x00000001,
4208 + PCFG04_command_memena_b = 2,
4209 + PCFG04_command_memena_m = 0x00000002,
4210 + PCFG04_command_bmena_b = 3,
4211 + PCFG04_command_bmena_m = 0x00000004,
4212 + PCFG04_command_mwinv_b = 5,
4213 + PCFG04_command_mwinv_m = 0x00000010,
4214 + PCFG04_command_parena_b = 7,
4215 + PCFG04_command_parena_m = 0x00000040,
4216 + PCFG04_command_serrena_b = 9,
4217 + PCFG04_command_serrena_m = 0x00000100,
4218 + PCFG04_command_fastbbena_b = 10,
4219 + PCFG04_command_fastbbena_m = 0x00000200,
4220 + PCFG04_status_b = 16,
4221 + PCFG04_status_m = 0xffff0000,
4222 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
4223 + PCFG04_status_66MHz_m = 0x00200000,
4224 + PCFG04_status_fbb_b = 23,
4225 + PCFG04_status_fbb_m = 0x00800000,
4226 + PCFG04_status_mdpe_b = 24,
4227 + PCFG04_status_mdpe_m = 0x01000000,
4228 + PCFG04_status_dst_b = 25,
4229 + PCFG04_status_dst_m = 0x06000000,
4230 + PCFG04_status_sta_b = 27,
4231 + PCFG04_status_sta_m = 0x08000000,
4232 + PCFG04_status_rta_b = 28,
4233 + PCFG04_status_rta_m = 0x10000000,
4234 + PCFG04_status_rma_b = 29,
4235 + PCFG04_status_rma_m = 0x20000000,
4236 + PCFG04_status_sse_b = 30,
4237 + PCFG04_status_sse_m = 0x40000000,
4238 + PCFG04_status_pe_b = 31,
4239 + PCFG04_status_pe_m = 0x40000000,
4240 +
4241 + PCFG08_revId_b = 0,
4242 + PCFG08_revId_m = 0x000000ff,
4243 + PCFG08_classCode_b = 0,
4244 + PCFG08_classCode_m = 0xffffff00,
4245 + PCFG08_classCode_bridge_v = 06,
4246 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
4247 + PCFG0C_cacheline_b = 0,
4248 + PCFG0C_cacheline_m = 0x000000ff,
4249 + PCFG0C_masterLatency_b = 8,
4250 + PCFG0C_masterLatency_m = 0x0000ff00,
4251 + PCFG0C_headerType_b = 16,
4252 + PCFG0C_headerType_m = 0x00ff0000,
4253 + PCFG0C_bist_b = 24,
4254 + PCFG0C_bist_m = 0xff000000,
4255 +
4256 + PCIPBA_msi_b = 0,
4257 + PCIPBA_msi_m = 0x00000001,
4258 + PCIPBA_p_b = 3,
4259 + PCIPBA_p_m = 0x00000004,
4260 + PCIPBA_baddr_b = 8,
4261 + PCIPBA_baddr_m = 0xffffff00,
4262 +
4263 + PCFGSS_vendorId_b = 0,
4264 + PCFGSS_vendorId_m = 0x0000ffff,
4265 + PCFGSS_id_b = 16,
4266 + PCFGSS_id_m = 0xffff0000,
4267 +
4268 + PCFG3C_interruptLine_b = 0,
4269 + PCFG3C_interruptLine_m = 0x000000ff,
4270 + PCFG3C_interruptPin_b = 8,
4271 + PCFG3C_interruptPin_m = 0x0000ff00,
4272 + PCFG3C_minGrant_b = 16,
4273 + PCFG3C_minGrant_m = 0x00ff0000,
4274 + PCFG3C_maxLat_b = 24,
4275 + PCFG3C_maxLat_m = 0xff000000,
4276 +
4277 + PCIPBAC_msi_b = 0,
4278 + PCIPBAC_msi_m = 0x00000001,
4279 + PCIPBAC_p_b = 1,
4280 + PCIPBAC_p_m = 0x00000002,
4281 + PCIPBAC_size_b = 2,
4282 + PCIPBAC_size_m = 0x0000007c,
4283 + PCIPBAC_sb_b = 7,
4284 + PCIPBAC_sb_m = 0x00000080,
4285 + PCIPBAC_pp_b = 8,
4286 + PCIPBAC_pp_m = 0x00000100,
4287 + PCIPBAC_mr_b = 9,
4288 + PCIPBAC_mr_m = 0x00000600,
4289 + PCIPBAC_mr_read_v =0, //no prefetching
4290 + PCIPBAC_mr_readLine_v =1,
4291 + PCIPBAC_mr_readMult_v =2,
4292 + PCIPBAC_mrl_b = 11,
4293 + PCIPBAC_mrl_m = 0x00000800,
4294 + PCIPBAC_mrm_b = 12,
4295 + PCIPBAC_mrm_m = 0x00001000,
4296 + PCIPBAC_trp_b = 13,
4297 + PCIPBAC_trp_m = 0x00002000,
4298 +
4299 + PCFG40_trdyTimeout_b = 0,
4300 + PCFG40_trdyTimeout_m = 0x000000ff,
4301 + PCFG40_retryLim_b = 8,
4302 + PCFG40_retryLim_m = 0x0000ff00,
4303 +};
4304 +
4305 +/*******************************************************************************
4306 + *
4307 + * PCI Local Base Address [0|1|2|3] Register
4308 + *
4309 + ******************************************************************************/
4310 +enum {
4311 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
4312 + PCILBA_baddr_m = 0xffffff00,
4313 +} ;
4314 +/*******************************************************************************
4315 + *
4316 + * PCI Local Base Address Control Register
4317 + *
4318 + ******************************************************************************/
4319 +enum {
4320 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
4321 + PCILBAC_msi_m = 0x00000001,
4322 + PCILBAC_msi_mem_v = 0,
4323 + PCILBAC_msi_io_v = 1,
4324 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
4325 + PCILBAC_size_m = 0x0000007c,
4326 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
4327 + PCILBAC_sb_m = 0x00000080,
4328 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
4329 + PCILBAC_rt_m = 0x00000100,
4330 + PCILBAC_rt_noprefetch_v = 0, // mem read
4331 + PCILBAC_rt_prefetch_v = 1, // mem readline
4332 +} ;
4333 +
4334 +/*******************************************************************************
4335 + *
4336 + * PCI Local Base Address [0|1|2|3] Mapping Register
4337 + *
4338 + ******************************************************************************/
4339 +enum {
4340 + PCILBAM_maddr_b = 8,
4341 + PCILBAM_maddr_m = 0xffffff00,
4342 +} ;
4343 +
4344 +/*******************************************************************************
4345 + *
4346 + * PCI Decoupled Access Control Register
4347 + *
4348 + ******************************************************************************/
4349 +enum {
4350 + PCIDAC_den_b = 0,
4351 + PCIDAC_den_m = 0x00000001,
4352 +} ;
4353 +
4354 +/*******************************************************************************
4355 + *
4356 + * PCI Decoupled Access Status Register
4357 + *
4358 + ******************************************************************************/
4359 +enum {
4360 + PCIDAS_d_b = 0,
4361 + PCIDAS_d_m = 0x00000001,
4362 + PCIDAS_b_b = 1,
4363 + PCIDAS_b_m = 0x00000002,
4364 + PCIDAS_e_b = 2,
4365 + PCIDAS_e_m = 0x00000004,
4366 + PCIDAS_ofe_b = 3,
4367 + PCIDAS_ofe_m = 0x00000008,
4368 + PCIDAS_off_b = 4,
4369 + PCIDAS_off_m = 0x00000010,
4370 + PCIDAS_ife_b = 5,
4371 + PCIDAS_ife_m = 0x00000020,
4372 + PCIDAS_iff_b = 6,
4373 + PCIDAS_iff_m = 0x00000040,
4374 +} ;
4375 +
4376 +/*******************************************************************************
4377 + *
4378 + * PCI DMA Channel 8 Configuration Register
4379 + *
4380 + ******************************************************************************/
4381 +enum
4382 +{
4383 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
4384 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
4385 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
4386 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
4387 +} ;
4388 +
4389 +/*******************************************************************************
4390 + *
4391 + * PCI DMA Channel 9 Configuration Register
4392 + *
4393 + ******************************************************************************/
4394 +enum
4395 +{
4396 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
4397 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
4398 +} ;
4399 +
4400 +/*******************************************************************************
4401 + *
4402 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
4403 + *
4404 + ******************************************************************************/
4405 +enum {
4406 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
4407 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
4408 + // These are for reads (DMA channel 8)
4409 + PCIDMAD_devcmd_mr_v = 0, //memory read
4410 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
4411 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
4412 + PCIDMAD_devcmd_ior_v = 3, //I/O read
4413 + // These are for writes (DMA channel 9)
4414 + PCIDMAD_devcmd_mw_v = 0, //memory write
4415 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
4416 + PCIDMAD_devcmd_iow_v = 3, //I/O write
4417 +
4418 + // Swap byte field applies to both DMA channel 8 and 9
4419 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
4420 + PCIDMAD_sb_m = 0x01000000, // swap byte field
4421 +} ;
4422 +
4423 +
4424 +/*******************************************************************************
4425 + *
4426 + * PCI Target Control Register
4427 + *
4428 + ******************************************************************************/
4429 +enum
4430 +{
4431 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
4432 + PCITC_rtimer_m = 0x000000ff,
4433 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
4434 + PCITC_dtimer_m = 0x0000ff00,
4435 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
4436 + PCITC_rdr_m = 0x00040000,
4437 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
4438 + PCITC_ddt_m = 0x00080000,
4439 +} ;
4440 +/*******************************************************************************
4441 + *
4442 + * PCI messaging unit [applies to both inbound and outbound registers ]
4443 + *
4444 + ******************************************************************************/
4445 +enum
4446 +{
4447 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4448 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
4449 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4450 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
4451 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4452 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
4453 +};
4454 +
4455 +
4456 +
4457 +
4458 +
4459 +
4460 +#define PCI_MSG_VirtualAddress 0xB8088010
4461 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4462 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4463 +
4464 +#define PCIM_SHFT 0x6
4465 +#define PCIM_BIT_LEN 0x7
4466 +#define PCIM_H_EA 0x3
4467 +#define PCIM_H_IA_FIX 0x4
4468 +#define PCIM_H_IA_RR 0x5
4469 +#if 0
4470 +#define PCI_ADDR_START 0x13000000
4471 +#endif
4472 +
4473 +#define PCI_ADDR_START 0x50000000
4474 +
4475 +#define CPUTOPCI_MEM_WIN 0x02000000
4476 +#define CPUTOPCI_IO_WIN 0x00100000
4477 +#define PCILBA_SIZE_SHFT 2
4478 +#define PCILBA_SIZE_MASK 0x1F
4479 +#define SIZE_256MB 0x1C
4480 +#define SIZE_128MB 0x1B
4481 +#define SIZE_64MB 0x1A
4482 +#define SIZE_32MB 0x19
4483 +#define SIZE_16MB 0x18
4484 +#define SIZE_4MB 0x16
4485 +#define SIZE_2MB 0x15
4486 +#define SIZE_1MB 0x14
4487 +#define KORINA_CONFIG0_ADDR 0x80000000
4488 +#define KORINA_CONFIG1_ADDR 0x80000004
4489 +#define KORINA_CONFIG2_ADDR 0x80000008
4490 +#define KORINA_CONFIG3_ADDR 0x8000000C
4491 +#define KORINA_CONFIG4_ADDR 0x80000010
4492 +#define KORINA_CONFIG5_ADDR 0x80000014
4493 +#define KORINA_CONFIG6_ADDR 0x80000018
4494 +#define KORINA_CONFIG7_ADDR 0x8000001C
4495 +#define KORINA_CONFIG8_ADDR 0x80000020
4496 +#define KORINA_CONFIG9_ADDR 0x80000024
4497 +#define KORINA_CONFIG10_ADDR 0x80000028
4498 +#define KORINA_CONFIG11_ADDR 0x8000002C
4499 +#define KORINA_CONFIG12_ADDR 0x80000030
4500 +#define KORINA_CONFIG13_ADDR 0x80000034
4501 +#define KORINA_CONFIG14_ADDR 0x80000038
4502 +#define KORINA_CONFIG15_ADDR 0x8000003C
4503 +#define KORINA_CONFIG16_ADDR 0x80000040
4504 +#define KORINA_CONFIG17_ADDR 0x80000044
4505 +#define KORINA_CONFIG18_ADDR 0x80000048
4506 +#define KORINA_CONFIG19_ADDR 0x8000004C
4507 +#define KORINA_CONFIG20_ADDR 0x80000050
4508 +#define KORINA_CONFIG21_ADDR 0x80000054
4509 +#define KORINA_CONFIG22_ADDR 0x80000058
4510 +#define KORINA_CONFIG23_ADDR 0x8000005C
4511 +#define KORINA_CONFIG24_ADDR 0x80000060
4512 +#define KORINA_CONFIG25_ADDR 0x80000064
4513 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4514 + PCFG04_command_memena_m | \
4515 + PCFG04_command_bmena_m | \
4516 + PCFG04_command_mwinv_m | \
4517 + PCFG04_command_parena_m | \
4518 + PCFG04_command_serrena_m )
4519 +
4520 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4521 + PCFG04_status_sta_m | \
4522 + PCFG04_status_rta_m | \
4523 + PCFG04_status_rma_m | \
4524 + PCFG04_status_sse_m | \
4525 + PCFG04_status_pe_m)
4526 +
4527 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4528 +
4529 +#define KORINA_REVID 0
4530 +#define KORINA_CLASS_CODE 0
4531 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4532 + KORINA_REVID)
4533 +
4534 +#define KORINA_CACHE_LINE_SIZE 4
4535 +#define KORINA_MASTER_LAT 0x3c
4536 +#define KORINA_HEADER_TYPE 0
4537 +#define KORINA_BIST 0
4538 +
4539 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4540 + (KORINA_HEADER_TYPE<<16) | \
4541 + (KORINA_MASTER_LAT<<8) | \
4542 + KORINA_CACHE_LINE_SIZE )
4543 +
4544 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4545 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4546 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
4547 + internal Registers */
4548 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4549 +
4550 +#define KORINA_CNFG4 KORINA_BAR0
4551 +#define KORINA_CNFG5 KORINA_BAR1
4552 +#define KORINA_CNFG6 KORINA_BAR2
4553 +#define KORINA_CNFG7 KORINA_BAR3
4554 +
4555 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
4556 +#define KORINA_SUBSYSTEM_ID 0x0214
4557 +#define KORINA_CNFG8 0
4558 +#define KORINA_CNFG9 0
4559 +#define KORINA_CNFG10 0
4560 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4561 + KORINA_SUBSYSTEM_ID)
4562 +#define KORINA_INT_LINE 1
4563 +#define KORINA_INT_PIN 1
4564 +#define KORINA_MIN_GNT 8
4565 +#define KORINA_MAX_LAT 0x38
4566 +#define KORINA_CNFG12 0
4567 +#define KORINA_CNFG13 0
4568 +#define KORINA_CNFG14 0
4569 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4570 + (KORINA_MIN_GNT<<16) | \
4571 + (KORINA_INT_PIN<<8) | \
4572 + KORINA_INT_LINE)
4573 +#define KORINA_RETRY_LIMIT 0x80
4574 +#define KORINA_TRDY_LIMIT 0x80
4575 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4576 + KORINA_TRDY_LIMIT)
4577 +#define PCI_PBAxC_R 0x0
4578 +#define PCI_PBAxC_RL 0x1
4579 +#define PCI_PBAxC_RM 0x2
4580 +#define SIZE_SHFT 2
4581 +
4582 +#if defined(__MIPSEB__)
4583 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4584 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4585 + PCIPBAC_pp_m | \
4586 + (SIZE_128MB<<SIZE_SHFT) | \
4587 + PCIPBAC_p_m)
4588 +#else
4589 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4590 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4591 + PCIPBAC_pp_m | \
4592 + (SIZE_128MB<<SIZE_SHFT) | \
4593 + PCIPBAC_p_m)
4594 +#endif
4595 +#define KORINA_CNFG17 KORINA_PBA0C
4596 +#define KORINA_PBA0M 0x0
4597 +#define KORINA_CNFG18 KORINA_PBA0M
4598 +
4599 +#if defined(__MIPSEB__)
4600 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4601 + PCIPBAC_msi_m)
4602 +#else
4603 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4604 + PCIPBAC_msi_m)
4605 +#endif
4606 +#define KORINA_CNFG19 KORINA_PBA1C
4607 +#define KORINA_PBA1M 0x0
4608 +#define KORINA_CNFG20 KORINA_PBA1M
4609 +
4610 +#if defined(__MIPSEB__)
4611 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4612 + PCIPBAC_msi_m)
4613 +#else
4614 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4615 + PCIPBAC_msi_m)
4616 +#endif
4617 +#define KORINA_CNFG21 KORINA_PBA2C
4618 +#define KORINA_PBA2M 0x18000000
4619 +#define KORINA_CNFG22 KORINA_PBA2M
4620 +#define KORINA_PBA3C 0
4621 +#define KORINA_CNFG23 KORINA_PBA3C
4622 +#define KORINA_PBA3M 0
4623 +#define KORINA_CNFG24 KORINA_PBA3M
4624 +
4625 +
4626 +
4627 +#define PCITC_DTIMER_VAL 8
4628 +#define PCITC_RTIMER_VAL 0x10
4629 +
4630 +
4631 +
4632 +
4633 +#endif // __IDT_PCI_H__
4634 +
4635 +
4636 +
4637 diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
4638 --- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100
4639 +++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-06-15 16:26:53.000000000 +0200
4640 @@ -0,0 +1,209 @@
4641 +/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
4642 + *
4643 + * This file is subject to the terms and conditions of the GNU General Public
4644 + * License. See the file "COPYING" in the main directory of this archive
4645 + * for more details.
4646 + */
4647 +#ifndef _PCIKORINA_H
4648 +#define _PCIKORINA_H
4649 +
4650 +
4651 +#define PCI_MSG_VirtualAddress 0xB8088010
4652 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4653 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4654 +
4655 +#define PCIM_SHFT 0x6
4656 +#define PCIM_BIT_LEN 0x7
4657 +#define PCIM_H_EA 0x3
4658 +#define PCIM_H_IA_FIX 0x4
4659 +#define PCIM_H_IA_RR 0x5
4660 +#if 0
4661 +#define PCI_ADDR_START 0x13000000
4662 +#endif
4663 +
4664 +#define PCI_ADDR_START 0x50000000
4665 +
4666 +#define CPUTOPCI_MEM_WIN 0x02000000
4667 +#define CPUTOPCI_IO_WIN 0x00100000
4668 +#define PCILBA_SIZE_SHFT 2
4669 +#define PCILBA_SIZE_MASK 0x1F
4670 +#define SIZE_256MB 0x1C
4671 +#define SIZE_128MB 0x1B
4672 +#define SIZE_64MB 0x1A
4673 +#define SIZE_32MB 0x19
4674 +#define SIZE_16MB 0x18
4675 +#define SIZE_4MB 0x16
4676 +#define SIZE_2MB 0x15
4677 +#define SIZE_1MB 0x14
4678 +#define KORINA_CONFIG0_ADDR 0x80000000
4679 +#define KORINA_CONFIG1_ADDR 0x80000004
4680 +#define KORINA_CONFIG2_ADDR 0x80000008
4681 +#define KORINA_CONFIG3_ADDR 0x8000000C
4682 +#define KORINA_CONFIG4_ADDR 0x80000010
4683 +#define KORINA_CONFIG5_ADDR 0x80000014
4684 +#define KORINA_CONFIG6_ADDR 0x80000018
4685 +#define KORINA_CONFIG7_ADDR 0x8000001C
4686 +#define KORINA_CONFIG8_ADDR 0x80000020
4687 +#define KORINA_CONFIG9_ADDR 0x80000024
4688 +#define KORINA_CONFIG10_ADDR 0x80000028
4689 +#define KORINA_CONFIG11_ADDR 0x8000002C
4690 +#define KORINA_CONFIG12_ADDR 0x80000030
4691 +#define KORINA_CONFIG13_ADDR 0x80000034
4692 +#define KORINA_CONFIG14_ADDR 0x80000038
4693 +#define KORINA_CONFIG15_ADDR 0x8000003C
4694 +#define KORINA_CONFIG16_ADDR 0x80000040
4695 +#define KORINA_CONFIG17_ADDR 0x80000044
4696 +#define KORINA_CONFIG18_ADDR 0x80000048
4697 +#define KORINA_CONFIG19_ADDR 0x8000004C
4698 +#define KORINA_CONFIG20_ADDR 0x80000050
4699 +#define KORINA_CONFIG21_ADDR 0x80000054
4700 +#define KORINA_CONFIG22_ADDR 0x80000058
4701 +#define KORINA_CONFIG23_ADDR 0x8000005C
4702 +#define KORINA_CONFIG24_ADDR 0x80000060
4703 +#define KORINA_CONFIG25_ADDR 0x80000064
4704 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4705 + PCFG04_command_memena_m | \
4706 + PCFG04_command_bmena_m | \
4707 + PCFG04_command_mwinv_m | \
4708 + PCFG04_command_parena_m | \
4709 + PCFG04_command_serrena_m )
4710 +
4711 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4712 + PCFG04_status_sta_m | \
4713 + PCFG04_status_rta_m | \
4714 + PCFG04_status_rma_m | \
4715 + PCFG04_status_sse_m | \
4716 + PCFG04_status_pe_m)
4717 +
4718 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4719 +
4720 +#define KORINA_REVID 0
4721 +#define KORINA_CLASS_CODE 0
4722 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4723 + KORINA_REVID)
4724 +
4725 +#define KORINA_CACHE_LINE_SIZE 4
4726 +#define KORINA_MASTER_LAT 0x3c
4727 +#define KORINA_HEADER_TYPE 0
4728 +#define KORINA_BIST 0
4729 +
4730 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4731 + (KORINA_HEADER_TYPE<<16) | \
4732 + (KORINA_MASTER_LAT<<8) | \
4733 + KORINA_CACHE_LINE_SIZE )
4734 +
4735 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4736 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4737 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia
4738 + internal Registers */
4739 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4740 +
4741 +#define KORINA_CNFG4 KORINA_BAR0
4742 +#define KORINA_CNFG5 KORINA_BAR1
4743 +#define KORINA_CNFG6 KORINA_BAR2
4744 +#define KORINA_CNFG7 KORINA_BAR3
4745 +
4746 +#define KORINA_SUBSYS_VENDOR_ID 0
4747 +#define KORINA_SUBSYSTEM_ID 0
4748 +#define KORINA_CNFG8 0
4749 +#define KORINA_CNFG9 0
4750 +#define KORINA_CNFG10 0
4751 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4752 + KORINA_SUBSYSTEM_ID)
4753 +#define KORINA_INT_LINE 1
4754 +#define KORINA_INT_PIN 1
4755 +#define KORINA_MIN_GNT 8
4756 +#define KORINA_MAX_LAT 0x38
4757 +#define KORINA_CNFG12 0
4758 +#define KORINA_CNFG13 0
4759 +#define KORINA_CNFG14 0
4760 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4761 + (KORINA_MIN_GNT<<16) | \
4762 + (KORINA_INT_PIN<<8) | \
4763 + KORINA_INT_LINE)
4764 +#define KORINA_RETRY_LIMIT 0x80
4765 +#define KORINA_TRDY_LIMIT 0x80
4766 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4767 + KORINA_TRDY_LIMIT)
4768 +#define PCI_PBAxC_R 0x0
4769 +#define PCI_PBAxC_RL 0x1
4770 +#define PCI_PBAxC_RM 0x2
4771 +#define SIZE_SHFT 2
4772 +
4773 +#ifdef __MIPSEB__
4774 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4775 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4776 + PCIPBAC_pp_m | \
4777 + (SIZE_32MB<<SIZE_SHFT) | \
4778 + PCIPBAC_p_m)
4779 +#else
4780 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4781 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4782 + PCIPBAC_pp_m | \
4783 + (SIZE_32MB<<SIZE_SHFT) | \
4784 + PCIPBAC_p_m)
4785 +#endif
4786 +
4787 +#if 0
4788 +
4789 +#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
4790 + ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
4791 + (SIZE_128MB<<SIZE_SHFT))
4792 +#endif
4793 +#define KORINA_CNFG17 KORINA_PBA0C
4794 +#define KORINA_PBA0M 0x0
4795 +#define KORINA_CNFG18 KORINA_PBA0M
4796 +
4797 +#ifdef __MIPSEB__
4798 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4799 + PCIPBAC_msi_m)
4800 +#else
4801 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4802 + PCIPBAC_msi_m)
4803 +
4804 +#endif
4805 +
4806 +#define KORINA_CNFG19 KORINA_PBA1C
4807 +#define KORINA_PBA1M 0x0
4808 +#define KORINA_CNFG20 KORINA_PBA1M
4809 +
4810 +#ifdef __MIPSEB__
4811 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4812 + PCIPBAC_msi_m)
4813 +#else
4814 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4815 + PCIPBAC_msi_m)
4816 +
4817 +#endif
4818 +#define KORINA_CNFG21 KORINA_PBA2C
4819 +#define KORINA_PBA2M 0x18000000
4820 +#define KORINA_CNFG22 KORINA_PBA2M
4821 +#define KORINA_PBA3C 0
4822 +#define KORINA_CNFG23 KORINA_PBA3C
4823 +#define KORINA_PBA3M 0
4824 +#define KORINA_CNFG24 KORINA_PBA3M
4825 +
4826 +
4827 +
4828 +#define PCITC_DTIMER_VAL 8
4829 +#define PCITC_RTIMER_VAL 0x10
4830 +
4831 +
4832 +#endif /* _PCIKORINA_H */
4833 +
4834 +
4835 +
4836 +
4837 +
4838 +
4839 +
4840 +
4841 +
4842 +
4843 +
4844 +
4845 +
4846 +
4847 +
4848 +
4849 +
4850 diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
4851 --- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100
4852 +++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-06-15 16:26:53.000000000 +0200
4853 @@ -0,0 +1,8 @@
4854 +/* Override the default address space for this arch
4855 +*/
4856 +
4857 +#include <linux/pci_regs.h>
4858 +
4859 +//#undef PCI_BASE_ADDRESS_SPACE
4860 +//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
4861 +
4862 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
4863 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
4864 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-06-15 16:27:36.000000000 +0200
4865 @@ -0,0 +1,69 @@
4866 +#ifndef __MIPS_RB_H__
4867 +#define __MIPS_RB_H__
4868 +#include <linux/genhd.h>
4869 +
4870 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
4871 +#define DEV0BASE 0x010000
4872 +#define DEV0MASK 0x010004
4873 +#define DEV0C 0x010008
4874 +#define DEV0TC 0x01000C
4875 +#define DEV1BASE 0x010010
4876 +#define DEV1MASK 0x010014
4877 +#define DEV1C 0x010018
4878 +#define DEV1TC 0x01001C
4879 +#define DEV2BASE 0x010020
4880 +#define DEV2MASK 0x010024
4881 +#define DEV2C 0x010028
4882 +#define DEV2TC 0x01002C
4883 +#define DEV3BASE 0x010030
4884 +#define DEV3MASK 0x010034
4885 +#define DEV3C 0x010038
4886 +#define DEV3TC 0x01003C
4887 +#define BTCS 0x010040
4888 +#define BTCOMPARE 0x010044
4889 +#define GPIOFUNC 0x050000
4890 +#define GPIOCFG 0x050004
4891 +#define GPIOD 0x050008
4892 +#define GPIOILEVEL 0x05000C
4893 +#define GPIOISTAT 0x050010
4894 +#define GPIONMIEN 0x050014
4895 +#define IMASK6 0x038038
4896 +
4897 +#define LO_WPX (1 << 0)
4898 +#define LO_ALE (1 << 1)
4899 +#define LO_CLE (1 << 2)
4900 +#define LO_CEX (1 << 3)
4901 +#define LO_FOFF (1 << 5)
4902 +#define LO_SPICS (1 << 6)
4903 +#define LO_ULED (1 << 7)
4904 +
4905 +typedef enum {
4906 + FUNC = 0x00,
4907 + CFG = 0x04,
4908 + DATA = 0x08,
4909 + ILEVEL = 0x0c,
4910 + ISTAT = 0x10,
4911 + NMIEN = 0x14
4912 +} gpio_func;
4913 +
4914 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
4915 +extern unsigned get434Reg(unsigned regOffs);
4916 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
4917 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
4918 +extern u32 gpio_get(gpio_func func);
4919 +
4920 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
4921 +
4922 +struct korina_device {
4923 + char *name;
4924 + unsigned char mac[6];
4925 + struct net_device *dev;
4926 +};
4927 +
4928 +struct cf_device {
4929 + int gpio_pin;
4930 + void *dev;
4931 + struct gendisk *gd;
4932 +};
4933 +
4934 +#endif
4935 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
4936 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
4937 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-06-15 16:26:53.000000000 +0200
4938 @@ -0,0 +1,126 @@
4939 +/*
4940 + ***************************************************************************
4941 + * Definitions for IDT RC323434 CPU.
4942 + *
4943 + ****************************************************************************
4944 + * Kiran Rao
4945 + *
4946 + * Original form
4947 + ****************************************************************************
4948 + * P. Sadik Oct 08, 2003
4949 + *
4950 + * Started revision history
4951 + * Made IDT_BUS_FREQ a kernel configuration parameter
4952 + ****************************************************************************
4953 + * P. Sadik Oct 10, 2003
4954 + *
4955 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
4956 + * idt_cpu_freq is used everywhere
4957 + ****************************************************************************
4958 + * P. Sadik Oct 20, 2003
4959 + *
4960 + * Removed RC32434_BASE_BAUD
4961 + ****************************************************************************
4962 +*/
4963 +#ifndef _RC32434_H_
4964 +#define _RC32434_H_
4965 +
4966 +#include <linux/config.h>
4967 +#include <linux/delay.h>
4968 +#include <asm/io.h>
4969 +#include <asm/rc32434/timer.h>
4970 +
4971 +#define RC32434_REG_BASE 0x18000000
4972 +
4973 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
4974 +#define timer ((volatile TIM_t) TIM0_VirtualAddress)
4975 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
4976 +
4977 +#define IDT_CLOCK_MULT 2
4978 +#define MIPS_CPU_TIMER_IRQ 7
4979 +/* Interrupt Controller */
4980 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
4981 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
4982 +#define IC_GROUP_OFFSET 0x0C
4983 +
4984 +#define NUM_INTR_GROUPS 5
4985 +/* 16550 UARTs */
4986 +
4987 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
4988 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
4989 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
4990 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
4991 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
4992 +
4993 +
4994 +#ifdef __MIPSEB__
4995 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
4996 +#else
4997 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
4998 +#endif
4999 +
5000 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
5001 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
5002 +
5003 +#define local_readl(addr) __raw_readl(addr)
5004 +#define local_writel(l,addr) __raw_writel(l,addr)
5005 +
5006 +/* cpu pipeline flush */
5007 +static inline void rc32434_sync(void)
5008 +{
5009 + __asm__ volatile ("sync");
5010 +}
5011 +
5012 +static inline void rc32434_sync_udelay(int us)
5013 +{
5014 + __asm__ volatile ("sync");
5015 + udelay(us);
5016 +}
5017 +
5018 +static inline void rc32434_sync_delay(int ms)
5019 +{
5020 + __asm__ volatile ("sync");
5021 + mdelay(ms);
5022 +}
5023 +
5024 +/*
5025 + * C access to CLZ and CLO instructions
5026 + * (count leading zeroes/ones).
5027 + */
5028 +static inline int rc32434_clz(unsigned long val)
5029 +{
5030 + int ret;
5031 + __asm__ volatile (
5032 + ".set\tnoreorder\n\t"
5033 + ".set\tnoat\n\t"
5034 + ".set\tmips32\n\t"
5035 + "clz\t%0,%1\n\t"
5036 + ".set\tmips0\n\t"
5037 + ".set\tat\n\t"
5038 + ".set\treorder"
5039 + : "=r" (ret)
5040 + : "r" (val));
5041 +
5042 + return ret;
5043 +}
5044 +static inline int rc32434_clo(unsigned long val)
5045 +{
5046 + int ret;
5047 + __asm__ volatile (
5048 + ".set\tnoreorder\n\t"
5049 + ".set\tnoat\n\t"
5050 + ".set\tmips32\n\t"
5051 + "clo\t%0,%1\n\t"
5052 + ".set\tmips0\n\t"
5053 + ".set\tat\n\t"
5054 + ".set\treorder"
5055 + : "=r" (ret)
5056 + : "r" (val));
5057 +
5058 + return ret;
5059 +}
5060 +
5061 +extern void cons_putc(char c);
5062 +extern void cons_puts(char *s);
5063 +
5064 +#endif /* _RC32434_H_ */
5065 diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
5066 --- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100
5067 +++ linux.dev/include/asm-mips/rc32434/rst.h 2006-06-15 16:26:53.000000000 +0200
5068 @@ -0,0 +1,105 @@
5069 +#ifndef __IDT_RST_H__
5070 +#define __IDT_RST_H__
5071 +
5072 +/*******************************************************************************
5073 + *
5074 + * Copyright 2002 Integrated Device Technology, Inc.
5075 + * All rights reserved.
5076 + *
5077 + * Reset register definitions.
5078 + *
5079 + * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5080 + *
5081 + * Author : Allen.Stichter@idt.com
5082 + * Date : 20020118
5083 + * Update :
5084 + * $Log: rst.h,v $
5085 + * Revision 1.2 2002/06/06 18:34:05 astichte
5086 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5087 + *
5088 + * Revision 1.1 2002/05/29 17:33:24 sysarch
5089 + * jba File moved from vcode/include/idt/acacia
5090 + *
5091 + *
5092 + ******************************************************************************/
5093 +
5094 +#include <asm/rc32434/types.h>
5095 +
5096 +enum
5097 +{
5098 + RST0_PhysicalAddress = 0x18000000,
5099 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
5100 +
5101 + RST0_VirtualAddress = 0xb8000000,
5102 + RST_VirtualAddress = RST0_VirtualAddress, // Default
5103 +} ;
5104 +
5105 +typedef struct RST_s
5106 +{
5107 + U32 filler [0x0006] ;
5108 + U32 sysid ;
5109 + U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
5110 + U32 reset ;
5111 + U32 bcv ;
5112 + U32 cea ;
5113 +} volatile * RST_t ;
5114 +
5115 +enum
5116 +{
5117 + SYSID_rev_b = 0,
5118 + SYSID_rev_m = 0x000000ff,
5119 + SYSID_imp_b = 8,
5120 + SYSID_imp_m = 0x000fff00,
5121 + SYSID_vendor_b = 20,
5122 + SYSID_vendor_m = 0xfff00000,
5123 +
5124 + BCV_pll_b = 0,
5125 + BCV_pll_m = 0x0000000f,
5126 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
5127 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
5128 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
5129 + BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK.
5130 + BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK.
5131 + BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK.
5132 + BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK.
5133 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
5134 + BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK.
5135 + BCV_pll_Res5_v = 0x9,
5136 + BCV_pll_Res6_v = 0xa,
5137 + BCV_pll_Res7_v = 0xb,
5138 + BCV_pll_Res8_v = 0xc,
5139 + BCV_pll_Res13_v = 0xd,
5140 + BCV_pll_Res14_v = 0xe,
5141 + BCV_pll_Res15_v = 0xf,
5142 + BCV_clkDiv_b = 4,
5143 + BCV_clkDiv_m = 0x00000030,
5144 + BCV_clkDiv_Div1_v = 0x0,
5145 + BCV_clkDiv_Div2_v = 0x1,
5146 + BCV_clkDiv_Div4_v = 0x2,
5147 + BCV_clkDiv_Res3_v = 0x3,
5148 + BCV_bigEndian_b = 6,
5149 + BCV_bigEndian_m = 0x00000040,
5150 + BCV_resetFast_b = 7,
5151 + BCV_resetFast_m = 0x00000080,
5152 + BCV_pciMode_b = 8,
5153 + BCV_pciMode_m = 0x00000100,
5154 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
5155 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
5156 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
5157 + BCV_pciMode_external_v = 3, // host, external arbiter.
5158 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
5159 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
5160 + BCV_pciMode_res6_v = 6,
5161 + BCV_pciMode_res7_v = 7,
5162 + BCV_watchDisable_b = 11,
5163 + BCV_watchDisable_m = 0x00000800,
5164 + BCV_pllTest_b = 12,
5165 + BCV_pllTest_m = 0x00001000,
5166 + BCV_nvramInit_b = 13,
5167 + BCV_nvramInit_m = 0x00002000,
5168 + BCV_clksyncTstMd_b = 14,
5169 + BCV_clksyncTstMd_m = 0x00004000,
5170 + BCV_delayBypass_b = 15,
5171 + BCV_delayByPass_m = 0x00008000,
5172 +} ;
5173 +#endif // __IDT_RST_H__
5174 diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
5175 --- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100
5176 +++ linux.dev/include/asm-mips/rc32434/spi.h 2006-06-15 16:26:53.000000000 +0200
5177 @@ -0,0 +1,100 @@
5178 +#ifndef __IDT_SPI_H__
5179 +#define __IDT_SPI_H__
5180 +
5181 +/*******************************************************************************
5182 + *
5183 + * Copyright 2002 Integrated Device Technology, Inc.
5184 + * All rights reserved.
5185 + *
5186 + * Serial Peripheral Interface register definitions.
5187 + *
5188 + * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5189 + *
5190 + * Author : ryan.holmQVist@idt.com
5191 + * Date : 20011005
5192 + * Update :
5193 + * $Log: spi.h,v $
5194 + * Revision 1.2 2002/06/06 18:34:05 astichte
5195 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5196 + *
5197 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5198 + * jba File moved from vcode/include/idt/acacia
5199 + *
5200 + *
5201 + ******************************************************************************/
5202 +
5203 +#include <asm/rc32434/types.h>
5204 +
5205 +enum
5206 +{
5207 + SPI0_PhysicalAddress = 0x18070000,
5208 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
5209 +
5210 + SPI0_VirtualAddress = 0xb8070000,
5211 + SPI_VirtualAddress = SPI0_VirtualAddress,
5212 +} ;
5213 +
5214 +typedef struct
5215 +{
5216 + U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
5217 + U32 spc ; // spi control reg use SPC_
5218 + U32 sps ; // spi status reg use SPS_
5219 + U32 spd ; // spi data reg use SPD_
5220 + U32 siofunc ; // serial IO function use SIOFUNC_
5221 + U32 siocfg ; // serial IO config use SIOCFG_
5222 + U32 siod; // serial IO data use SIOD_
5223 +} volatile *SPI_t ;
5224 +
5225 +enum
5226 +{
5227 + SPCP_div_b = 0,
5228 + SPCP_div_m = 0x000000ff,
5229 + SPC_spr_b = 0,
5230 + SPC_spr_m = 0x00000003,
5231 + SPC_spr_div2_v = 0,
5232 + SPC_spr_div4_v = 1,
5233 + SPC_spr_div16_v = 2,
5234 + SPC_spr_div32_v = 3,
5235 + SPC_cpha_b = 2,
5236 + SPC_cpha_m = 0x00000004,
5237 + SPC_cpol_b = 3,
5238 + SPC_cpol_m = 0x00000008,
5239 + SPC_mstr_b = 4,
5240 + SPC_mstr_m = 0x00000010,
5241 + SPC_spe_b = 6,
5242 + SPC_spe_m = 0x00000040,
5243 + SPC_spie_b = 7,
5244 + SPC_spie_m = 0x00000080,
5245 +
5246 + SPS_modf_b = 4,
5247 + SPS_modf_m = 0x00000010,
5248 + SPS_wcol_b = 6,
5249 + SPS_wcol_m = 0x00000040,
5250 + SPS_spif_b = 7,
5251 + SPS_spif_m = 0x00000070,
5252 +
5253 + SPD_data_b = 0,
5254 + SPD_data_m = 0x000000ff,
5255 +
5256 + SIOFUNC_sdo_b = 0,
5257 + SIOFUNC_sdo_m = 0x00000001,
5258 + SIOFUNC_sdi_b = 1,
5259 + SIOFUNC_sdi_m = 0x00000002,
5260 + SIOFUNC_sck_b = 2,
5261 + SIOFUNC_sck_m = 0x00000004,
5262 +
5263 + SIOCFG_sdo_b = 0,
5264 + SIOCFG_sdo_m = 0x00000001,
5265 + SIOCFG_sdi_b = 1,
5266 + SIOCFG_sdi_m = 0x00000002,
5267 + SIOCFG_sck_b = 2,
5268 + SIOCFG_sck_m = 0x00000004,
5269 +
5270 + SIOD_sdo_b = 0,
5271 + SIOD_sdo_m = 0x00000001,
5272 + SIOD_sdi_b = 1,
5273 + SIOD_sdi_m = 0x00000002,
5274 + SIOD_sck_b = 2,
5275 + SIOD_sck_m = 0x00000004,
5276 +} ;
5277 +#endif // __IDT_SPI_H__
5278 diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
5279 --- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100
5280 +++ linux.dev/include/asm-mips/rc32434/timer.h 2006-06-15 16:26:53.000000000 +0200
5281 @@ -0,0 +1,91 @@
5282 +/**************************************************************************
5283 + *
5284 + * BRIEF MODULE DESCRIPTION
5285 + * Definitions for timer registers
5286 + *
5287 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5288 + *
5289 + * This program is free software; you can redistribute it and/or modify it
5290 + * under the terms of the GNU General Public License as published by the
5291 + * Free Software Foundation; either version 2 of the License, or (at your
5292 + * option) any later version.
5293 + *
5294 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5295 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5296 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5297 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5298 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5299 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5300 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5301 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5302 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5303 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5304 + *
5305 + * You should have received a copy of the GNU General Public License along
5306 + * with this program; if not, write to the Free Software Foundation, Inc.,
5307 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5308 + *
5309 + *
5310 + **************************************************************************
5311 + * May 2004 rkt,neb.
5312 + *
5313 + * Initial Release
5314 + *
5315 + *
5316 + *
5317 + **************************************************************************
5318 + */
5319 +
5320 +#ifndef __IDT_TIM_H__
5321 +#define __IDT_TIM_H__
5322 +
5323 +enum
5324 +{
5325 + TIM0_PhysicalAddress = 0x18028000,
5326 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5327 +
5328 + TIM0_VirtualAddress = 0xb8028000,
5329 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5330 +} ;
5331 +
5332 +enum
5333 +{
5334 + TIM_Count = 3,
5335 +} ;
5336 +
5337 +struct TIM_CNTR_s
5338 +{
5339 + u32 count ;
5340 + u32 compare ;
5341 + u32 ctc ; //use CTC_
5342 +} ;
5343 +
5344 +typedef struct TIM_s
5345 +{
5346 + struct TIM_CNTR_s tim [TIM_Count] ;
5347 + u32 rcount ; //use RCOUNT_
5348 + u32 rcompare ; //use RCOMPARE_
5349 + u32 rtc ; //use RTC_
5350 +} volatile * TIM_t ;
5351 +
5352 +enum
5353 +{
5354 + CTC_en_b = 0,
5355 + CTC_en_m = 0x00000001,
5356 + CTC_to_b = 1,
5357 + CTC_to_m = 0x00000002,
5358 +
5359 + RCOUNT_count_b = 0,
5360 + RCOUNT_count_m = 0x0000ffff,
5361 + RCOMPARE_compare_b = 0,
5362 + RCOMPARE_compare_m = 0x0000ffff,
5363 + RTC_ce_b = 0,
5364 + RTC_ce_m = 0x00000001,
5365 + RTC_to_b = 1,
5366 + RTC_to_m = 0x00000002,
5367 + RTC_rqe_b = 2,
5368 + RTC_rqe_m = 0x00000004,
5369 +
5370 +} ;
5371 +#endif // __IDT_TIM_H__
5372 +
5373 diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
5374 --- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100
5375 +++ linux.dev/include/asm-mips/rc32434/tim.h 2006-06-15 16:26:53.000000000 +0200
5376 @@ -0,0 +1,78 @@
5377 +#ifndef __IDT_TIM_H__
5378 +#define __IDT_TIM_H__
5379 +
5380 +/*******************************************************************************
5381 + *
5382 + * Copyright 2002 Integrated Device Technology, Inc.
5383 + * All rights reserved.
5384 + *
5385 + * Timer register definition.
5386 + *
5387 + * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5388 + *
5389 + * Author : ryan.holmQVist@idt.com
5390 + * Date : 20011005
5391 + * Update :
5392 + * $Log: tim.h,v $
5393 + * Revision 1.2 2002/06/06 18:34:05 astichte
5394 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5395 + *
5396 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5397 + * jba File moved from vcode/include/idt/acacia
5398 + *
5399 + *
5400 + ******************************************************************************/
5401 +
5402 +
5403 +#include <asm/rc32434/types.h>
5404 +
5405 +enum
5406 +{
5407 + TIM0_PhysicalAddress = 0x18028000,
5408 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5409 +
5410 + TIM0_VirtualAddress = 0xb8028000,
5411 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5412 +} ;
5413 +
5414 +enum
5415 +{
5416 + TIM_Count = 3,
5417 +} ;
5418 +
5419 +struct TIM_CNTR_s
5420 +{
5421 + U32 count ;
5422 + U32 compare ;
5423 + U32 ctc ; //use CTC_
5424 +} ;
5425 +
5426 +typedef struct TIM_s
5427 +{
5428 + struct TIM_CNTR_s tim [TIM_Count] ;
5429 + U32 rcount ; //use RCOUNT_
5430 + U32 rcompare ; //use RCOMPARE_
5431 + U32 rtc ; //use RTC_
5432 +} volatile * TIM_t ;
5433 +
5434 +enum
5435 +{
5436 + CTC_en_b = 0,
5437 + CTC_en_m = 0x00000001,
5438 + CTC_to_b = 1,
5439 + CTC_to_m = 0x00000002,
5440 +
5441 + RCOUNT_count_b = 0,
5442 + RCOUNT_count_m = 0x0000ffff,
5443 + RCOMPARE_compare_b = 0,
5444 + RCOMPARE_compare_m = 0x0000ffff,
5445 + RTC_ce_b = 0,
5446 + RTC_ce_m = 0x00000001,
5447 + RTC_to_b = 1,
5448 + RTC_to_m = 0x00000002,
5449 + RTC_rqe_b = 2,
5450 + RTC_rqe_m = 0x00000004,
5451 +
5452 +} ;
5453 +#endif // __IDT_TIM_H__
5454 +
5455 diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
5456 --- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100
5457 +++ linux.dev/include/asm-mips/rc32434/types.h 2006-06-15 16:26:53.000000000 +0200
5458 @@ -0,0 +1,39 @@
5459 +#ifndef __IDT_TYPES_H__
5460 +#define __IDT_TYPES_H__
5461 +
5462 +/*******************************************************************************
5463 + *
5464 + * Copyright 2002 Integrated Device Technology, Inc.
5465 + * All rights reserved.
5466 + *
5467 + * Common typedefs used in IDT-generated code.
5468 + *
5469 + * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
5470 + *
5471 + * Author : Allen.Stichter@idt.com
5472 + * Date : 20020606
5473 + * Update :
5474 + * $Log: types.h,v $
5475 + * Revision 1.1 2002/06/06 16:16:56 astichte
5476 + * Added
5477 + *
5478 + *
5479 + ******************************************************************************/
5480 +
5481 +typedef unsigned char U8 ;
5482 +typedef signed char S8 ;
5483 +
5484 +typedef unsigned short U16 ;
5485 +typedef signed short S16 ;
5486 +
5487 +typedef unsigned int U32 ;
5488 +typedef signed int S32 ;
5489 +
5490 +typedef unsigned long long U64 ;
5491 +typedef signed long long S64 ;
5492 +
5493 +#ifndef __cplusplus
5494 + typedef U32 bool ; // (false == 0), (true is != false)
5495 +#endif // __cplusplus
5496 +
5497 +#endif // __IDT_TYPES_H__
5498 diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
5499 --- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100
5500 +++ linux.dev/include/asm-mips/rc32434/uart.h 2006-06-15 16:26:53.000000000 +0200
5501 @@ -0,0 +1,178 @@
5502 +#ifndef __IDT_UART_H__
5503 +#define __IDT_UART_H__
5504 +
5505 +/*******************************************************************************
5506 + *
5507 + * Copyright 2002 Integrated Device Technology, Inc.
5508 + * All rights reserved.
5509 + *
5510 + * UART register definitions.
5511 + *
5512 + * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
5513 + *
5514 + * Author : Allen.Stichter@idt.com
5515 + * Date : 20020118
5516 + * Update :
5517 + * $Log: uart.h,v $
5518 + * Revision 1.3 2002/06/06 18:34:05 astichte
5519 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5520 + *
5521 + * Revision 1.2 2002/06/04 17:37:52 astichte
5522 + * Updated register definitions.
5523 + *
5524 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5525 + * jba File moved from vcode/include/idt/acacia
5526 + *
5527 + *
5528 + ******************************************************************************/
5529 +
5530 +#include <asm/rc32434/types.h>
5531 +
5532 +enum
5533 +{
5534 + UART_PhysicalAddress = 0x18058000,
5535 + UART_PhysicalAddress = UART_PhysicalAddress, // Default
5536 +
5537 + UART_VirtualAddress = 0xb8058000,
5538 + UART_VirtualAddress = UART_VirtualAddress, // Default
5539 +} ;
5540 +
5541 +/*
5542 + * Register definitions are in bytes so we can handle endian problems.
5543 + */
5544 +
5545 +typedef struct UART_s
5546 +{
5547 + union
5548 + {
5549 + U32 const uartrb ; // 0x00 - DLAB=0, read.
5550 + U32 uartth ; // 0x00 - DLAB=0, write.
5551 + U32 uartdll ; // 0x00 - DLAB=1, read/write.
5552 + } ;
5553 +
5554 + union
5555 + {
5556 + U32 uartie ; // 0x04 - DLAB=0, read/write.
5557 + U32 uartdlh ; // 0x04 - DLAB=1, read/write.
5558 + } ;
5559 + union
5560 + {
5561 + U32 const uartii ; // 0x08 - DLAB=0, read.
5562 + U32 uartfc ; // 0x08 - DLAB=0, write.
5563 + } ;
5564 +
5565 + U32 uartlc ; // 0x0c
5566 + U32 uartmc ; // 0x10
5567 + U32 uartls ; // 0x14
5568 + U32 uartms ; // 0x18
5569 + U32 uarts ; // 0x1c
5570 +} volatile *UART_t ;
5571 +
5572 +// Reset registers.
5573 +typedef U32 volatile *UARTRR_t ;
5574 +
5575 +enum
5576 +{
5577 + UARTIE_rda_b = 0,
5578 + UARTIE_rda_m = 0x00000001,
5579 + UARTIE_the_b = 1,
5580 + UARTIE_the_m = 0x00000002,
5581 + UARTIE_rls_b = 2,
5582 + UARTIE_rls_m = 0x00000004,
5583 + UARTIE_ems_b = 3,
5584 + UARTIE_ems_m = 0x00000008,
5585 +
5586 + UARTII_pi_b = 0,
5587 + UARTII_pi_m = 0x00000001,
5588 + UARTII_iid_b = 1,
5589 + UARTII_iid_m = 0x0000000e,
5590 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
5591 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
5592 + UARTII_iid_rda_v = 2, // Receive data available
5593 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
5594 + UARTII_iid_res4_v = 4, // reserved.
5595 + UARTII_iid_res5_v = 5, // reserved.
5596 + UARTII_iid_cto_v = 6, // Character timeout.
5597 + UARTII_iid_res7_v = 7, // reserved.
5598 +
5599 + UARTFC_en_b = 0,
5600 + UARTFC_en_m = 0x00000001,
5601 + UARTFC_rr_b = 1,
5602 + UARTFC_rr_m = 0x00000002,
5603 + UARTFC_tr_b = 2,
5604 + UARTFC_tr_m = 0x00000004,
5605 + UARTFC_dms_b = 3,
5606 + UARTFC_dms_m = 0x00000008,
5607 + UARTFC_rt_b = 6,
5608 + UARTFC_rt_m = 0x000000c0,
5609 + UARTFC_rt_1Byte_v = 0,
5610 + UARTFC_rt_4Byte_v = 1,
5611 + UARTFC_rt_8Byte_v = 2,
5612 + UARTFC_rt_14Byte_v = 3,
5613 +
5614 + UARTLC_wls_b = 0,
5615 + UARTLC_wls_m = 0x00000003,
5616 + UARTLC_wls_5Bits_v = 0,
5617 + UARTLC_wls_6Bits_v = 1,
5618 + UARTLC_wls_7Bits_v = 2,
5619 + UARTLC_wls_8Bits_v = 3,
5620 + UARTLC_stb_b = 2,
5621 + UARTLC_stb_m = 0x00000004,
5622 + UARTLC_pen_b = 3,
5623 + UARTLC_pen_m = 0x00000008,
5624 + UARTLC_eps_b = 4,
5625 + UARTLC_eps_m = 0x00000010,
5626 + UARTLC_sp_b = 5,
5627 + UARTLC_sp_m = 0x00000020,
5628 + UARTLC_sb_b = 6,
5629 + UARTLC_sb_m = 0x00000040,
5630 + UARTLC_dlab_b = 7,
5631 + UARTLC_dlab_m = 0x00000080,
5632 +
5633 + UARTMC_dtr_b = 0,
5634 + UARTMC_dtr_m = 0x00000001,
5635 + UARTMC_rts_b = 1,
5636 + UARTMC_rts_m = 0x00000002,
5637 + UARTMC_o1_b = 2,
5638 + UARTMC_o1_m = 0x00000004,
5639 + UARTMC_o2_b = 3,
5640 + UARTMC_o2_m = 0x00000008,
5641 + UARTMC_lp_b = 4,
5642 + UARTMC_lp_m = 0x00000010,
5643 +
5644 + UARTLS_dr_b = 0,
5645 + UARTLS_dr_m = 0x00000001,
5646 + UARTLS_oe_b = 1,
5647 + UARTLS_oe_m = 0x00000002,
5648 + UARTLS_pe_b = 2,
5649 + UARTLS_pe_m = 0x00000004,
5650 + UARTLS_fe_b = 3,
5651 + UARTLS_fe_m = 0x00000008,
5652 + UARTLS_bi_b = 4,
5653 + UARTLS_bi_m = 0x00000010,
5654 + UARTLS_thr_b = 5,
5655 + UARTLS_thr_m = 0x00000020,
5656 + UARTLS_te_b = 6,
5657 + UARTLS_te_m = 0x00000040,
5658 + UARTLS_rfe_b = 7,
5659 + UARTLS_rfe_m = 0x00000080,
5660 +
5661 + UARTMS_dcts_b = 0,
5662 + UARTMS_dcts_m = 0x00000001,
5663 + UARTMS_ddsr_b = 1,
5664 + UARTMS_ddsr_m = 0x00000002,
5665 + UARTMS_teri_b = 2,
5666 + UARTMS_teri_m = 0x00000004,
5667 + UARTMS_ddcd_b = 3,
5668 + UARTMS_ddcd_m = 0x00000008,
5669 + UARTMS_cts_b = 4,
5670 + UARTMS_cts_m = 0x00000010,
5671 + UARTMS_dsr_b = 5,
5672 + UARTMS_dsr_m = 0x00000020,
5673 + UARTMS_ri_b = 6,
5674 + UARTMS_ri_m = 0x00000040,
5675 + UARTMS_dcd_b = 7,
5676 + UARTMS_dcd_m = 0x00000080,
5677 +} ;
5678 +
5679 +#endif // __IDT_UART_H__
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