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[lantiq] remove deadcode from [25072]
[openwrt.git] / target / linux / lantiq / patches / 104-board_xway.patch
1
2 --- /dev/null
3 +++ b/arch/mips/lantiq/xway/Kconfig
4 @@ -0,0 +1,19 @@
5 +if SOC_LANTIQ_XWAY
6 +
7 +menu "Mips Machine"
8 +
9 +config LANTIQ_MACH_EASY50812
10 + bool "Easy50812"
11 + default y
12 +
13 +config LANTIQ_MACH_EASY50712
14 + bool "Easy50712"
15 + default y
16 +
17 +config LANTIQ_MACH_EASY4010
18 + bool "Easy4010"
19 + default y
20 +
21 +endmenu
22 +
23 +endif
24 --- /dev/null
25 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
26 @@ -0,0 +1,116 @@
27 +/*
28 + * This program is free software; you can redistribute it and/or modify it
29 + * under the terms of the GNU General Public License version 2 as published
30 + * by the Free Software Foundation.
31 + *
32 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include <linux/init.h>
36 +#include <linux/module.h>
37 +#include <linux/types.h>
38 +#include <linux/platform_device.h>
39 +#include <linux/mutex.h>
40 +#include <linux/gpio.h>
41 +
42 +#include <xway.h>
43 +
44 +#define LQ_EBU_BUSCON 0x1e7ff
45 +#define LQ_EBU_WP 0x80000000
46 +
47 +static int shadow = 0x0000;
48 +static void __iomem *virt;
49 +
50 +static int
51 +lq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
52 +{
53 + return 0;
54 +}
55 +
56 +static void
57 +lq_ebu_apply(void)
58 +{
59 + unsigned long flags;
60 + spin_lock_irqsave(&ebu_lock, flags);
61 + lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
62 + *((__u16*)virt) = shadow;
63 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
64 + spin_unlock_irqrestore(&ebu_lock, flags);
65 +}
66 +
67 +static void
68 +lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
69 +{
70 + if(value)
71 + shadow |= (1 << offset);
72 + else
73 + shadow &= ~(1 << offset);
74 + lq_ebu_apply();
75 +}
76 +
77 +static struct gpio_chip
78 +lq_ebu_chip =
79 +{
80 + .label = "lq_ebu",
81 + .direction_output = lq_ebu_direction_output,
82 + .set = lq_ebu_set,
83 + .base = 32,
84 + .ngpio = 16,
85 + .can_sleep = 1,
86 + .owner = THIS_MODULE,
87 +};
88 +
89 +static int __devinit
90 +lq_ebu_probe(struct platform_device *pdev)
91 +{
92 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93 + int ret = 0;
94 + if (!res)
95 + return -ENOENT;
96 + res = request_mem_region(res->start, resource_size(res),
97 + dev_name(&pdev->dev));
98 + if (!res)
99 + return -EBUSY;
100 +
101 + /* tell the ebu controller which mem addr we will be using */
102 + lq_w32(pdev->resource->start | 0x1, LQ_EBU_ADDRSEL1);
103 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
104 +
105 + virt = ioremap_nocache(res->start, resource_size(res));
106 + if (!virt)
107 + {
108 + dev_err(&pdev->dev, "Failed to ioremap mem region\n");
109 + ret = -ENOMEM;
110 + goto err_release_mem_region;
111 + }
112 + /* grab the default settings passed form the platform code */
113 + shadow = (unsigned int) pdev->dev.platform_data;
114 +
115 + ret = gpiochip_add(&lq_ebu_chip);
116 + if (!ret)
117 + {
118 + lq_ebu_apply();
119 + return 0;
120 + }
121 +
122 +err_release_mem_region:
123 + release_mem_region(res->start, resource_size(res));
124 + return ret;
125 +}
126 +
127 +static struct platform_driver
128 +lq_ebu_driver = {
129 + .probe = lq_ebu_probe,
130 + .driver = {
131 + .name = "lq_ebu",
132 + .owner = THIS_MODULE,
133 + },
134 +};
135 +
136 +static int __init
137 +init_lq_ebu(void)
138 +{
139 + return platform_driver_register(&lq_ebu_driver);
140 +}
141 +
142 +postcore_initcall(init_lq_ebu);
143 --- /dev/null
144 +++ b/arch/mips/lantiq/xway/gpio_leds.c
145 @@ -0,0 +1,161 @@
146 +/*
147 + * This program is free software; you can redistribute it and/or modify it
148 + * under the terms of the GNU General Public License version 2 as published
149 + * by the Free Software Foundation.
150 + *
151 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
152 + *
153 + */
154 +
155 +#include <linux/slab.h>
156 +#include <linux/init.h>
157 +#include <linux/module.h>
158 +#include <linux/types.h>
159 +#include <linux/platform_device.h>
160 +#include <linux/mutex.h>
161 +#include <linux/gpio.h>
162 +
163 +#include <xway.h>
164 +
165 +#define LQ_STP_BASE 0x1E100BB0
166 +#define LQ_STP_SIZE 0x40
167 +
168 +#define LQ_STP_CON0 0x00
169 +#define LQ_STP_CON1 0x04
170 +#define LQ_STP_CPU0 0x08
171 +#define LQ_STP_CPU1 0x0C
172 +#define LQ_STP_AR 0x10
173 +
174 +#define STP_CON0_SWU (1 << 31)
175 +
176 +#define LQ_STP_2HZ (0)
177 +#define LQ_STP_4HZ (1 << 23)
178 +#define LQ_STP_8HZ (2 << 23)
179 +#define LQ_STP_10HZ (3 << 23)
180 +#define LQ_STP_MASK (0xf << 23)
181 +
182 +#define LQ_STP_UPD_SRC_FPI (1 << 31)
183 +#define LQ_STP_UPD_MASK (3 << 30)
184 +#define LQ_STP_ADSL_SRC (3 << 24)
185 +
186 +#define LQ_STP_GROUP0 (1 << 0)
187 +
188 +#define LQ_STP_RISING 0
189 +#define LQ_STP_FALLING (1 << 26)
190 +#define LQ_STP_EDGE_MASK (1 << 26)
191 +
192 +#define lq_stp_r32(reg) __raw_readl(virt + reg)
193 +#define lq_stp_w32(val, reg) __raw_writel(val, virt + reg)
194 +#define lq_stp_w32_mask(clear, set, reg) \
195 + lq_w32((lq_r32(virt + reg) & ~clear) | set, virt + reg)
196 +
197 +static int shadow = 0xffff;
198 +static void __iomem *virt;
199 +
200 +static int
201 +lq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value)
202 +{
203 + return 0;
204 +}
205 +
206 +static void
207 +lq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
208 +{
209 + if(value)
210 + shadow |= (1 << offset);
211 + else
212 + shadow &= ~(1 << offset);
213 + lq_stp_w32(shadow, LQ_STP_CPU0);
214 +}
215 +
216 +static struct gpio_chip lq_stp_chip =
217 +{
218 + .label = "lq_stp",
219 + .direction_output = lq_stp_direction_output,
220 + .set = lq_stp_set,
221 + .base = 48,
222 + .ngpio = 24,
223 + .can_sleep = 1,
224 + .owner = THIS_MODULE,
225 +};
226 +
227 +static int
228 +lq_stp_hw_init(void)
229 +{
230 + /* the 3 pins used to control the external stp */
231 + lq_gpio_request(4, 1, 0, 1, "stp-st");
232 + lq_gpio_request(5, 1, 0, 1, "stp-d");
233 + lq_gpio_request(6, 1, 0, 1, "stp-sh");
234 +
235 + /* sane defaults */
236 + lq_stp_w32(0, LQ_STP_AR);
237 + lq_stp_w32(0, LQ_STP_CPU0);
238 + lq_stp_w32(0, LQ_STP_CPU1);
239 + lq_stp_w32(STP_CON0_SWU, LQ_STP_CON0);
240 + lq_stp_w32(0, LQ_STP_CON1);
241 +
242 + /* rising or falling edge */
243 + lq_stp_w32_mask(LQ_STP_EDGE_MASK, LQ_STP_FALLING, LQ_STP_CON0);
244 +
245 + /* per default stp 15-0 are set */
246 + lq_stp_w32_mask(0, LQ_STP_GROUP0, LQ_STP_CON1);
247 +
248 + /* stp are update periodically by the FPID */
249 + lq_stp_w32_mask(LQ_STP_UPD_MASK, LQ_STP_UPD_SRC_FPI, LQ_STP_CON1);
250 +
251 + /* set stp update speed */
252 + lq_stp_w32_mask(LQ_STP_MASK, LQ_STP_8HZ, LQ_STP_CON1);
253 +
254 + /* adsl 0 and 1 stp are updated by the arc */
255 + lq_stp_w32_mask(0, LQ_STP_ADSL_SRC, LQ_STP_CON0);
256 +
257 + lq_pmu_enable(PMU_LED);
258 + return 0;
259 +}
260 +
261 +static int
262 +lq_stp_probe(struct platform_device *pdev)
263 +{
264 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 + int ret = 0;
266 + if (!res)
267 + return -ENOENT;
268 + res = request_mem_region(res->start, resource_size(res),
269 + dev_name(&pdev->dev));
270 + if (!res)
271 + return -EBUSY;
272 + virt = ioremap_nocache(res->start, resource_size(res));
273 + if(!virt)
274 + {
275 + ret = -ENOMEM;
276 + goto err_release_mem_region;
277 + }
278 + ret = gpiochip_add(&lq_stp_chip);
279 + if(!ret)
280 + return lq_stp_hw_init();
281 +
282 + iounmap(virt);
283 +err_release_mem_region:
284 + release_mem_region(res->start, resource_size(res));
285 + return ret;
286 +}
287 +
288 +static struct platform_driver lq_stp_driver = {
289 + .probe = lq_stp_probe,
290 + .driver = {
291 + .name = "lq_stp",
292 + .owner = THIS_MODULE,
293 + },
294 +};
295 +
296 +int __init
297 +init_lq_stp(void)
298 +{
299 + int ret = platform_driver_register(&lq_stp_driver);
300 + if (ret)
301 + printk(KERN_INFO
302 + "lq_stp: error registering platfom driver");
303 + return ret;
304 +}
305 +
306 +postcore_initcall(init_lq_stp);
307 --- /dev/null
308 +++ b/arch/mips/lantiq/xway/mach-easy4010.c
309 @@ -0,0 +1,82 @@
310 +/*
311 + * This program is free software; you can redistribute it and/or modify it
312 + * under the terms of the GNU General Public License version 2 as published
313 + * by the Free Software Foundation.
314 + *
315 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
316 + */
317 +
318 +#include <linux/init.h>
319 +#include <linux/platform_device.h>
320 +#include <linux/leds.h>
321 +#include <linux/gpio.h>
322 +#include <linux/gpio_buttons.h>
323 +#include <linux/mtd/mtd.h>
324 +#include <linux/mtd/partitions.h>
325 +#include <linux/mtd/physmap.h>
326 +#include <linux/input.h>
327 +
328 +#include <machine.h>
329 +
330 +#include <xway.h>
331 +#include <lantiq_platform.h>
332 +
333 +#include "devices.h"
334 +
335 +#ifdef CONFIG_MTD_PARTITIONS
336 +static struct mtd_partition easy4010_partitions[] =
337 +{
338 + {
339 + .name = "uboot",
340 + .offset = 0x0,
341 + .size = 0x20000,
342 + },
343 + {
344 + .name = "uboot_env",
345 + .offset = 0x20000,
346 + .size = 0x10000,
347 + },
348 + {
349 + .name = "linux",
350 + .offset = 0x30000,
351 + .size = 0x3D0000,
352 + },
353 +};
354 +#endif
355 +
356 +static struct physmap_flash_data easy4010_flash_data = {
357 +#ifdef CONFIG_MTD_PARTITIONS
358 + .nr_parts = ARRAY_SIZE(easy4010_partitions),
359 + .parts = easy4010_partitions,
360 +#endif
361 +};
362 +
363 +static struct lq_pci_data lq_pci_data = {
364 + .clock = PCI_CLOCK_INT,
365 + .gpio = PCI_GNT1 | PCI_REQ1,
366 + .irq = {
367 + [14] = INT_NUM_IM0_IRL0 + 22,
368 + },
369 +};
370 +
371 +static struct lq_eth_data lq_eth_data = {
372 + .mii_mode = REV_MII_MODE,
373 +};
374 +
375 +static void __init
376 +easy4010_init(void)
377 +{
378 + lq_register_gpio();
379 + lq_register_gpio_stp();
380 + lq_register_asc(0);
381 + lq_register_asc(1);
382 + lq_register_nor(&easy4010_flash_data);
383 + lq_register_wdt();
384 + lq_register_pci(&lq_pci_data);
385 + lq_register_ethernet(&lq_eth_data);
386 +}
387 +
388 +MIPS_MACHINE(LANTIQ_MACH_EASY4010,
389 + "EASY4010",
390 + "EASY4010 Eval Board",
391 + easy4010_init);
392 --- /dev/null
393 +++ b/arch/mips/lantiq/xway/mach-easy50712.c
394 @@ -0,0 +1,82 @@
395 +/*
396 + * This program is free software; you can redistribute it and/or modify it
397 + * under the terms of the GNU General Public License version 2 as published
398 + * by the Free Software Foundation.
399 + *
400 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
401 + */
402 +
403 +#include <linux/init.h>
404 +#include <linux/platform_device.h>
405 +#include <linux/leds.h>
406 +#include <linux/gpio.h>
407 +#include <linux/gpio_buttons.h>
408 +#include <linux/mtd/mtd.h>
409 +#include <linux/mtd/partitions.h>
410 +#include <linux/mtd/physmap.h>
411 +#include <linux/input.h>
412 +
413 +#include <machine.h>
414 +
415 +#include <xway.h>
416 +#include <lantiq_platform.h>
417 +
418 +#include "devices.h"
419 +
420 +#ifdef CONFIG_MTD_PARTITIONS
421 +static struct mtd_partition easy50712_partitions[] =
422 +{
423 + {
424 + .name = "uboot",
425 + .offset = 0x0,
426 + .size = 0x20000,
427 + },
428 + {
429 + .name = "uboot_env",
430 + .offset = 0x20000,
431 + .size = 0x10000,
432 + },
433 + {
434 + .name = "linux",
435 + .offset = 0x30000,
436 + .size = 0x3D0000,
437 + },
438 +};
439 +#endif
440 +
441 +static struct physmap_flash_data easy50712_flash_data = {
442 +#ifdef CONFIG_MTD_PARTITIONS
443 + .nr_parts = ARRAY_SIZE(easy50712_partitions),
444 + .parts = easy50712_partitions,
445 +#endif
446 +};
447 +
448 +static struct lq_pci_data lq_pci_data = {
449 + .clock = PCI_CLOCK_INT,
450 + .gpio = PCI_GNT1 | PCI_REQ1,
451 + .irq = {
452 + [14] = INT_NUM_IM0_IRL0 + 22,
453 + },
454 +};
455 +
456 +static struct lq_eth_data lq_eth_data = {
457 + .mii_mode = REV_MII_MODE,
458 +};
459 +
460 +static void __init
461 +easy50712_init(void)
462 +{
463 + lq_register_asc(0);
464 + lq_register_asc(1);
465 + lq_register_gpio();
466 + lq_register_gpio_stp();
467 + lq_register_nor(&easy50712_flash_data);
468 + lq_register_wdt();
469 + lq_register_pci(&lq_pci_data);
470 + lq_register_ethernet(&lq_eth_data);
471 +}
472 +
473 +MIPS_MACHINE(LANTIQ_MACH_EASY50712,
474 + "EASY50712",
475 + "EASY50712 Eval Board",
476 + easy50712_init);
477 --- /dev/null
478 +++ b/arch/mips/lantiq/xway/mach-easy50812.c
479 @@ -0,0 +1,81 @@
480 +/*
481 + * This program is free software; you can redistribute it and/or modify it
482 + * under the terms of the GNU General Public License version 2 as published
483 + * by the Free Software Foundation.
484 + *
485 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
486 + */
487 +
488 +#include <linux/init.h>
489 +#include <linux/platform_device.h>
490 +#include <linux/leds.h>
491 +#include <linux/gpio.h>
492 +#include <linux/gpio_buttons.h>
493 +#include <linux/mtd/mtd.h>
494 +#include <linux/mtd/partitions.h>
495 +#include <linux/mtd/physmap.h>
496 +#include <linux/input.h>
497 +
498 +#include <machine.h>
499 +
500 +#include <xway.h>
501 +#include <lantiq_platform.h>
502 +
503 +#include "devices.h"
504 +
505 +#ifdef CONFIG_MTD_PARTITIONS
506 +static struct mtd_partition easy50812_partitions[] =
507 +{
508 + {
509 + .name = "uboot",
510 + .offset = 0x0,
511 + .size = 0x40000,
512 + },
513 + {
514 + .name = "uboot_env",
515 + .offset = 0x40000,
516 + .size = 0x10000,
517 + },
518 + {
519 + .name = "linux",
520 + .offset = 0x50000,
521 + .size = 0x3B0000,
522 + },
523 +};
524 +#endif
525 +
526 +static struct physmap_flash_data easy50812_flash_data = {
527 +#ifdef CONFIG_MTD_PARTITIONS
528 + .nr_parts = ARRAY_SIZE(easy50812_partitions),
529 + .parts = easy50812_partitions,
530 +#endif
531 +};
532 +
533 +static struct lq_pci_data lq_pci_data = {
534 + .clock = PCI_CLOCK_INT,
535 + .gpio = PCI_GNT1 | PCI_REQ1,
536 + .irq = {
537 + [14] = INT_NUM_IM0_IRL0 + 22,
538 + },
539 +};
540 +
541 +static struct lq_eth_data lq_eth_data = {
542 + .mii_mode = REV_MII_MODE,
543 +};
544 +
545 +static void __init
546 +easy50812_init(void)
547 +{
548 + lq_register_gpio();
549 + lq_register_asc(0);
550 + lq_register_asc(1);
551 + lq_register_nor(&easy50812_flash_data);
552 + lq_register_wdt();
553 + lq_register_pci(&lq_pci_data);
554 + lq_register_ethernet(&lq_eth_data);
555 +}
556 +
557 +MIPS_MACHINE(LANTIQ_MACH_EASY50812,
558 + "EASY50812",
559 + "EASY50812 Eval Board",
560 + easy50812_init);
561 --- /dev/null
562 +++ b/arch/mips/lantiq/xway/prom.c
563 @@ -0,0 +1,52 @@
564 +/*
565 + * This program is free software; you can redistribute it and/or modify it
566 + * under the terms of the GNU General Public License version 2 as published
567 + * by the Free Software Foundation.
568 + *
569 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
570 + */
571 +
572 +#include <linux/module.h>
573 +#include <linux/clk.h>
574 +#include <asm/bootinfo.h>
575 +#include <asm/time.h>
576 +
577 +#include <xway.h>
578 +
579 +#include "../prom.h"
580 +
581 +#define SOC_DANUBE "Danube"
582 +#define SOC_TWINPASS "Twinpass"
583 +#define SOC_AR9 "AR9"
584 +
585 +void __init
586 +lq_soc_detect(struct lq_soc_info *i)
587 +{
588 + i->partnum = (lq_r32(LQ_MPS_CHIPID) & 0x0FFFFFFF) >> 12;
589 + i->rev = (lq_r32(LQ_MPS_CHIPID) & 0xF0000000) >> 28;
590 + switch (i->partnum)
591 + {
592 + case SOC_ID_DANUBE1:
593 + case SOC_ID_DANUBE2:
594 + i->name = SOC_DANUBE;
595 + i->type = SOC_TYPE_DANUBE;
596 + break;
597 +
598 + case SOC_ID_TWINPASS:
599 + i->name = SOC_TWINPASS;
600 + i->type = SOC_TYPE_DANUBE;
601 + break;
602 +
603 + case SOC_ID_ARX188:
604 + case SOC_ID_ARX168:
605 + case SOC_ID_ARX182:
606 + i->name = SOC_AR9;
607 + i->type = SOC_TYPE_AR9;
608 + break;
609 +
610 + default:
611 + printk(KERN_ERR "unknown chiprev : 0x%08X\n", i->partnum);
612 + while(1) { };
613 + break;
614 + }
615 +}
616 --- /dev/null
617 +++ b/arch/mips/lantiq/xway/devices.c
618 @@ -0,0 +1,278 @@
619 +/*
620 + * This program is free software; you can redistribute it and/or modify it
621 + * under the terms of the GNU General Public License version 2 as published
622 + * by the Free Software Foundation.
623 + *
624 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
625 + */
626 +
627 +#include <linux/init.h>
628 +#include <linux/module.h>
629 +#include <linux/types.h>
630 +#include <linux/string.h>
631 +#include <linux/mtd/physmap.h>
632 +#include <linux/kernel.h>
633 +#include <linux/reboot.h>
634 +#include <linux/platform_device.h>
635 +#include <linux/leds.h>
636 +#include <linux/etherdevice.h>
637 +#include <linux/reboot.h>
638 +#include <linux/time.h>
639 +#include <linux/io.h>
640 +#include <linux/gpio.h>
641 +#include <linux/leds.h>
642 +
643 +#include <asm/bootinfo.h>
644 +#include <asm/irq.h>
645 +
646 +#include <xway.h>
647 +#include <xway_irq.h>
648 +#include <lantiq_platform.h>
649 +
650 +#define IRQ_RES(resname,irq) {.name=#resname,.start=(irq),.flags=IORESOURCE_IRQ}
651 +
652 +/* gpio leds */
653 +static struct gpio_led_platform_data lq_gpio_led_data;
654 +
655 +static struct platform_device lq_gpio_leds =
656 +{
657 + .name = "leds-gpio",
658 + .dev = {
659 + .platform_data = (void *) &lq_gpio_led_data,
660 + }
661 +};
662 +
663 +void __init
664 +lq_register_gpio_leds(struct gpio_led *leds, int cnt)
665 +{
666 + lq_gpio_led_data.leds = leds;
667 + lq_gpio_led_data.num_leds = cnt;
668 + platform_device_register(&lq_gpio_leds);
669 +}
670 +
671 +/* serial to parallel conversion */
672 +static struct resource lq_stp_resource =
673 +{
674 + .name = "stp",
675 + .start = LQ_STP_BASE,
676 + .end = LQ_STP_BASE + LQ_STP_SIZE - 1,
677 + .flags = IORESOURCE_MEM,
678 +};
679 +
680 +void __init
681 +lq_register_gpio_stp(void)
682 +{
683 + platform_device_register_simple("lq_stp", 0, &lq_stp_resource, 1);
684 +}
685 +
686 +/* nor flash */
687 +static struct resource lq_nor_resource =
688 +{
689 + .name = "nor",
690 + .start = LQ_FLASH_START,
691 + .end = LQ_FLASH_START + LQ_FLASH_MAX - 1,
692 + .flags = IORESOURCE_MEM,
693 +};
694 +
695 +static struct platform_device lq_nor =
696 +{
697 + .name = "lq_nor",
698 + .resource = &lq_nor_resource,
699 + .num_resources = 1,
700 +};
701 +
702 +void __init
703 +lq_register_nor(struct physmap_flash_data *data)
704 +{
705 + lq_nor.dev.platform_data = data;
706 + platform_device_register(&lq_nor);
707 +}
708 +
709 +/* watchdog */
710 +static struct resource lq_wdt_resource =
711 +{
712 + .name = "watchdog",
713 + .start = LQ_WDT_BASE,
714 + .end = LQ_WDT_BASE + LQ_WDT_SIZE - 1,
715 + .flags = IORESOURCE_MEM,
716 +};
717 +
718 +void __init
719 +lq_register_wdt(void)
720 +{
721 + platform_device_register_simple("lq_wdt", 0, &lq_wdt_resource, 1);
722 +}
723 +
724 +/* gpio */
725 +static struct resource lq_gpio_resource[] = {
726 + {
727 + .name = "gpio0",
728 + .start = LQ_GPIO0_BASE_ADDR,
729 + .end = LQ_GPIO0_BASE_ADDR + LQ_GPIO_SIZE - 1,
730 + .flags = IORESOURCE_MEM,
731 + }, {
732 + .name = "gpio1",
733 + .start = LQ_GPIO1_BASE_ADDR,
734 + .end = LQ_GPIO1_BASE_ADDR + LQ_GPIO_SIZE - 1,
735 + .flags = IORESOURCE_MEM,
736 + }
737 +};
738 +
739 +void __init
740 +lq_register_gpio(void)
741 +{
742 + platform_device_register_simple("lq_gpio", 0, &lq_gpio_resource[0], 1);
743 + platform_device_register_simple("lq_gpio", 1, &lq_gpio_resource[1], 1);
744 +}
745 +
746 +/* pci */
747 +static struct platform_device lq_pci =
748 +{
749 + .name = "lq_pci",
750 + .num_resources = 0,
751 +};
752 +
753 +void __init
754 +lq_register_pci(struct lq_pci_data *data)
755 +{
756 + lq_pci.dev.platform_data = data;
757 + platform_device_register(&lq_pci);
758 +}
759 +
760 +/* ebu */
761 +static struct resource lq_ebu_resource =
762 +{
763 + .name = "gpio_ebu",
764 + .start = LQ_EBU_GPIO_START,
765 + .end = LQ_EBU_GPIO_START + LQ_EBU_GPIO_SIZE - 1,
766 + .flags = IORESOURCE_MEM,
767 +};
768 +
769 +void __init
770 +lq_register_gpio_ebu(unsigned int value)
771 +{
772 + platform_device_register_simple("lq_ebu", 0, &lq_ebu_resource, 1);
773 +}
774 +
775 +/* ethernet */
776 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
777 +
778 +static int __init
779 +lq_set_ethaddr(char *str)
780 +{
781 + sscanf(&str[8], "0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx",
782 + &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
783 + &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
784 + return 0;
785 +}
786 +__setup("ethaddr=", lq_set_ethaddr);
787 +
788 +static struct resource lq_ethernet_resources =
789 +{
790 + .name = "etop",
791 + .start = LQ_PPE32_BASE_ADDR,
792 + .end = LQ_PPE32_BASE_ADDR + LQ_PPE32_SIZE - 1,
793 + .flags = IORESOURCE_MEM,
794 +};
795 +
796 +static struct platform_device lq_ethernet =
797 +{
798 + .name = "lq_etop",
799 + .resource = &lq_ethernet_resources,
800 + .num_resources = 1,
801 +};
802 +
803 +void __init
804 +lq_register_ethernet(struct lq_eth_data *eth)
805 +{
806 + if(!eth)
807 + return;
808 + if(!eth->mac)
809 + eth->mac = lq_ethaddr;
810 + if(!is_valid_ether_addr(eth->mac))
811 + random_ether_addr(eth->mac);
812 + lq_ethernet.dev.platform_data = eth;
813 + platform_device_register(&lq_ethernet);
814 +}
815 +
816 +/* tapi */
817 +static struct resource mps_resources[] = {
818 + {
819 + .name = "voice-mem",
820 + .flags = IORESOURCE_MEM,
821 + .start = 0x1f107000,
822 + .end = 0x1f1073ff,
823 + },
824 + {
825 + .name = "voice-mailbox",
826 + .flags = IORESOURCE_MEM,
827 + .start = 0x1f200000,
828 + .end = 0x1f2007ff,
829 + },
830 +};
831 +
832 +static struct platform_device mps_device = {
833 + .name = "mps",
834 + .resource = mps_resources,
835 + .num_resources = ARRAY_SIZE(mps_resources),
836 +};
837 +
838 +static struct platform_device vmmc_device = {
839 + .name = "vmmc",
840 + .dev = {
841 + .parent = &mps_device.dev,
842 + },
843 +};
844 +
845 +void __init
846 +lq_register_tapi(void)
847 +{
848 +#define CP1_SIZE (1 << 20)
849 + dma_addr_t dma;
850 + mps_device.dev.platform_data =
851 + (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
852 + platform_device_register(&mps_device);
853 + platform_device_register(&vmmc_device);
854 +}
855 +
856 +/* asc ports */
857 +static struct resource lq_asc0_resources[] =
858 +{
859 + {
860 + .start = LQ_ASC0_BASE,
861 + .end = LQ_ASC0_BASE + LQ_ASC_SIZE - 1,
862 + .flags = IORESOURCE_MEM,
863 + },
864 + IRQ_RES(tx, INT_NUM_IM3_IRL0),
865 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 1),
866 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 2),
867 +};
868 +
869 +static struct resource lq_asc1_resources[] =
870 +{
871 + {
872 + .start = LQ_ASC1_BASE,
873 + .end = LQ_ASC1_BASE + LQ_ASC_SIZE - 1,
874 + .flags = IORESOURCE_MEM,
875 + },
876 + IRQ_RES(tx, INT_NUM_IM3_IRL0 + 8),
877 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 9),
878 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 10),
879 +};
880 +
881 +void __init
882 +lq_register_asc(int port)
883 +{
884 + switch (port) {
885 + case 0:
886 + platform_device_register_simple("lq_asc", 0,
887 + lq_asc0_resources, ARRAY_SIZE(lq_asc0_resources));
888 + break;
889 + case 1:
890 + platform_device_register_simple("lq_asc", 1,
891 + lq_asc1_resources, ARRAY_SIZE(lq_asc1_resources));
892 + break;
893 + default:
894 + break;
895 + }
896 +}
897 --- /dev/null
898 +++ b/arch/mips/lantiq/xway/devices.h
899 @@ -0,0 +1,25 @@
900 +/*
901 + * This program is free software; you can redistribute it and/or modify it
902 + * under the terms of the GNU General Public License version 2 as published
903 + * by the Free Software Foundation.
904 + *
905 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
906 + */
907 +
908 +#ifndef _LQ_DEVICES_H__
909 +#define _LQ_DEVICES_H__
910 +
911 +#include <lantiq_platform.h>
912 +#include <xway_irq.h>
913 +
914 +extern void __init lq_register_gpio(void);
915 +extern void __init lq_register_gpio_stp(void);
916 +extern void __init lq_register_gpio_ebu(unsigned int value);
917 +extern void __init lq_register_gpio_leds(struct gpio_led *leds, int cnt);
918 +extern void __init lq_register_pci(struct lq_pci_data *data);
919 +extern void __init lq_register_nor(struct physmap_flash_data *data);
920 +extern void __init lq_register_wdt(void);
921 +extern void __init lq_register_ethernet(struct lq_eth_data *eth);
922 +extern void __init lq_register_asc(int port);
923 +
924 +#endif
925 --- /dev/null
926 +++ b/arch/mips/lantiq/xway/dma.c
927 @@ -0,0 +1,701 @@
928 +#include <linux/module.h>
929 +#include <linux/init.h>
930 +#include <linux/sched.h>
931 +#include <linux/kernel.h>
932 +#include <linux/slab.h>
933 +#include <linux/string.h>
934 +#include <linux/timer.h>
935 +#include <linux/fs.h>
936 +#include <linux/errno.h>
937 +#include <linux/stat.h>
938 +#include <linux/mm.h>
939 +#include <linux/tty.h>
940 +#include <linux/selection.h>
941 +#include <linux/kmod.h>
942 +#include <linux/vmalloc.h>
943 +#include <linux/interrupt.h>
944 +#include <linux/delay.h>
945 +#include <linux/uaccess.h>
946 +#include <linux/errno.h>
947 +#include <linux/io.h>
948 +
949 +#include <xway.h>
950 +#include <xway_irq.h>
951 +#include <xway_dma.h>
952 +
953 +#define LQ_DMA_CS ((u32 *)(LQ_DMA_BASE_ADDR + 0x18))
954 +#define LQ_DMA_CIE ((u32 *)(LQ_DMA_BASE_ADDR + 0x2C))
955 +#define LQ_DMA_IRNEN ((u32 *)(LQ_DMA_BASE_ADDR + 0xf4))
956 +#define LQ_DMA_CCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x1C))
957 +#define LQ_DMA_CIS ((u32 *)(LQ_DMA_BASE_ADDR + 0x28))
958 +#define LQ_DMA_CDLEN ((u32 *)(LQ_DMA_BASE_ADDR + 0x24))
959 +#define LQ_DMA_PS ((u32 *)(LQ_DMA_BASE_ADDR + 0x40))
960 +#define LQ_DMA_PCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x44))
961 +#define LQ_DMA_CTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x10))
962 +#define LQ_DMA_CPOLL ((u32 *)(LQ_DMA_BASE_ADDR + 0x14))
963 +#define LQ_DMA_CDBA ((u32 *)(LQ_DMA_BASE_ADDR + 0x20))
964 +
965 +/*25 descriptors for each dma channel,4096/8/20=25.xx*/
966 +#define LQ_DMA_DESCRIPTOR_OFFSET 25
967 +
968 +#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
969 +#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
970 +#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
971 +#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
972 +
973 +extern void lq_mask_and_ack_irq(unsigned int irq_nr);
974 +extern void lq_enable_irq(unsigned int irq_nr);
975 +extern void lq_disable_irq(unsigned int irq_nr);
976 +
977 +u64 *g_desc_list;
978 +struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
979 +struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
980 +
981 +static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
982 + { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
983 +
984 +struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
985 + {"PPE", LQ_DMA_RX, 0, LQ_DMA_CH0_INT, 0},
986 + {"PPE", LQ_DMA_TX, 0, LQ_DMA_CH1_INT, 0},
987 + {"PPE", LQ_DMA_RX, 1, LQ_DMA_CH2_INT, 1},
988 + {"PPE", LQ_DMA_TX, 1, LQ_DMA_CH3_INT, 1},
989 + {"PPE", LQ_DMA_RX, 2, LQ_DMA_CH4_INT, 2},
990 + {"PPE", LQ_DMA_TX, 2, LQ_DMA_CH5_INT, 2},
991 + {"PPE", LQ_DMA_RX, 3, LQ_DMA_CH6_INT, 3},
992 + {"PPE", LQ_DMA_TX, 3, LQ_DMA_CH7_INT, 3},
993 + {"DEU", LQ_DMA_RX, 0, LQ_DMA_CH8_INT, 0},
994 + {"DEU", LQ_DMA_TX, 0, LQ_DMA_CH9_INT, 0},
995 + {"DEU", LQ_DMA_RX, 1, LQ_DMA_CH10_INT, 1},
996 + {"DEU", LQ_DMA_TX, 1, LQ_DMA_CH11_INT, 1},
997 + {"SPI", LQ_DMA_RX, 0, LQ_DMA_CH12_INT, 0},
998 + {"SPI", LQ_DMA_TX, 0, LQ_DMA_CH13_INT, 0},
999 + {"SDIO", LQ_DMA_RX, 0, LQ_DMA_CH14_INT, 0},
1000 + {"SDIO", LQ_DMA_TX, 0, LQ_DMA_CH15_INT, 0},
1001 + {"MCTRL0", LQ_DMA_RX, 0, LQ_DMA_CH16_INT, 0},
1002 + {"MCTRL0", LQ_DMA_TX, 0, LQ_DMA_CH17_INT, 0},
1003 + {"MCTRL1", LQ_DMA_RX, 1, LQ_DMA_CH18_INT, 1},
1004 + {"MCTRL1", LQ_DMA_TX, 1, LQ_DMA_CH19_INT, 1}
1005 +};
1006 +
1007 +struct dma_chan_map *chan_map = default_dma_map;
1008 +volatile u32 g_lq_dma_int_status;
1009 +volatile int g_lq_dma_in_process; /* 0=not in process, 1=in process */
1010 +
1011 +void do_dma_tasklet(unsigned long);
1012 +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
1013 +
1014 +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
1015 +{
1016 + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
1017 +
1018 + *byte_offset = 0;
1019 +
1020 + return buffer;
1021 +}
1022 +
1023 +void common_buffer_free(u8 *dataptr, void *opt)
1024 +{
1025 + kfree(dataptr);
1026 +}
1027 +
1028 +void enable_ch_irq(struct dma_channel_info *pCh)
1029 +{
1030 + int chan_no = (int)(pCh - dma_chan);
1031 + unsigned long flag;
1032 +
1033 + local_irq_save(flag);
1034 + lq_w32(chan_no, LQ_DMA_CS);
1035 + lq_w32(0x4a, LQ_DMA_CIE);
1036 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1037 + local_irq_restore(flag);
1038 + lq_enable_irq(pCh->irq);
1039 +}
1040 +
1041 +void disable_ch_irq(struct dma_channel_info *pCh)
1042 +{
1043 + unsigned long flag;
1044 + int chan_no = (int) (pCh - dma_chan);
1045 +
1046 + local_irq_save(flag);
1047 + g_lq_dma_int_status &= ~(1 << chan_no);
1048 + lq_w32(chan_no, LQ_DMA_CS);
1049 + lq_w32(0, LQ_DMA_CIE);
1050 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN);
1051 + local_irq_restore(flag);
1052 + lq_mask_and_ack_irq(pCh->irq);
1053 +}
1054 +
1055 +void open_chan(struct dma_channel_info *pCh)
1056 +{
1057 + unsigned long flag;
1058 + int chan_no = (int)(pCh - dma_chan);
1059 +
1060 + local_irq_save(flag);
1061 + lq_w32(chan_no, LQ_DMA_CS);
1062 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 1, LQ_DMA_CCTRL);
1063 + if (pCh->dir == LQ_DMA_RX)
1064 + enable_ch_irq(pCh);
1065 + local_irq_restore(flag);
1066 +}
1067 +
1068 +void close_chan(struct dma_channel_info *pCh)
1069 +{
1070 + unsigned long flag;
1071 + int chan_no = (int) (pCh - dma_chan);
1072 +
1073 + local_irq_save(flag);
1074 + lq_w32(chan_no, LQ_DMA_CS);
1075 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1076 + disable_ch_irq(pCh);
1077 + local_irq_restore(flag);
1078 +}
1079 +
1080 +void reset_chan(struct dma_channel_info *pCh)
1081 +{
1082 + int chan_no = (int) (pCh - dma_chan);
1083 +
1084 + lq_w32(chan_no, LQ_DMA_CS);
1085 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1086 +}
1087 +
1088 +void rx_chan_intr_handler(int chan_no)
1089 +{
1090 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1091 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1092 + struct rx_desc *rx_desc_p;
1093 + int tmp;
1094 + unsigned long flag;
1095 +
1096 + /*handle command complete interrupt */
1097 + rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
1098 + if (rx_desc_p->status.field.OWN == CPU_OWN
1099 + && rx_desc_p->status.field.C
1100 + && rx_desc_p->status.field.data_length < 1536){
1101 + /* Every thing is correct, then we inform the upper layer */
1102 + pDev->current_rx_chan = pCh->rel_chan_no;
1103 + if (pDev->intr_handler)
1104 + pDev->intr_handler(pDev, RCV_INT);
1105 + pCh->weight--;
1106 + } else {
1107 + local_irq_save(flag);
1108 + tmp = lq_r32(LQ_DMA_CS);
1109 + lq_w32(chan_no, LQ_DMA_CS);
1110 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1111 + lq_w32(tmp, LQ_DMA_CS);
1112 + g_lq_dma_int_status &= ~(1 << chan_no);
1113 + local_irq_restore(flag);
1114 + lq_enable_irq(dma_chan[chan_no].irq);
1115 + }
1116 +}
1117 +
1118 +inline void tx_chan_intr_handler(int chan_no)
1119 +{
1120 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1121 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1122 + int tmp;
1123 + unsigned long flag;
1124 +
1125 + local_irq_save(flag);
1126 + tmp = lq_r32(LQ_DMA_CS);
1127 + lq_w32(chan_no, LQ_DMA_CS);
1128 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1129 + lq_w32(tmp, LQ_DMA_CS);
1130 + g_lq_dma_int_status &= ~(1 << chan_no);
1131 + local_irq_restore(flag);
1132 + pDev->current_tx_chan = pCh->rel_chan_no;
1133 + if (pDev->intr_handler)
1134 + pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
1135 +}
1136 +
1137 +void do_dma_tasklet(unsigned long unused)
1138 +{
1139 + int i;
1140 + int chan_no = 0;
1141 + int budget = DMA_INT_BUDGET;
1142 + int weight = 0;
1143 + unsigned long flag;
1144 +
1145 + while (g_lq_dma_int_status) {
1146 + if (budget-- < 0) {
1147 + tasklet_schedule(&dma_tasklet);
1148 + return;
1149 + }
1150 + chan_no = -1;
1151 + weight = 0;
1152 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1153 + if ((g_lq_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
1154 + if (dma_chan[i].weight > weight) {
1155 + chan_no = i;
1156 + weight = dma_chan[chan_no].weight;
1157 + }
1158 + }
1159 + }
1160 +
1161 + if (chan_no >= 0) {
1162 + if (chan_map[chan_no].dir == LQ_DMA_RX)
1163 + rx_chan_intr_handler(chan_no);
1164 + else
1165 + tx_chan_intr_handler(chan_no);
1166 + } else {
1167 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1168 + dma_chan[i].weight = dma_chan[i].default_weight;
1169 + }
1170 + }
1171 +
1172 + local_irq_save(flag);
1173 + g_lq_dma_in_process = 0;
1174 + if (g_lq_dma_int_status) {
1175 + g_lq_dma_in_process = 1;
1176 + tasklet_schedule(&dma_tasklet);
1177 + }
1178 + local_irq_restore(flag);
1179 +}
1180 +
1181 +irqreturn_t dma_interrupt(int irq, void *dev_id)
1182 +{
1183 + struct dma_channel_info *pCh;
1184 + int chan_no = 0;
1185 + int tmp;
1186 +
1187 + pCh = (struct dma_channel_info *)dev_id;
1188 + chan_no = (int)(pCh - dma_chan);
1189 + if (chan_no < 0 || chan_no > 19)
1190 + BUG();
1191 +
1192 + tmp = lq_r32(LQ_DMA_IRNEN);
1193 + lq_w32(0, LQ_DMA_IRNEN);
1194 + g_lq_dma_int_status |= 1 << chan_no;
1195 + lq_w32(tmp, LQ_DMA_IRNEN);
1196 + lq_mask_and_ack_irq(irq);
1197 +
1198 + if (!g_lq_dma_in_process) {
1199 + g_lq_dma_in_process = 1;
1200 + tasklet_schedule(&dma_tasklet);
1201 + }
1202 +
1203 + return IRQ_HANDLED;
1204 +}
1205 +
1206 +struct dma_device_info *dma_device_reserve(char *dev_name)
1207 +{
1208 + int i;
1209 +
1210 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1211 + if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
1212 + if (dma_devs[i].reserved)
1213 + return NULL;
1214 + dma_devs[i].reserved = 1;
1215 + break;
1216 + }
1217 + }
1218 +
1219 + return &dma_devs[i];
1220 +}
1221 +EXPORT_SYMBOL(dma_device_reserve);
1222 +
1223 +void dma_device_release(struct dma_device_info *dev)
1224 +{
1225 + dev->reserved = 0;
1226 +}
1227 +EXPORT_SYMBOL(dma_device_release);
1228 +
1229 +void dma_device_register(struct dma_device_info *dev)
1230 +{
1231 + int i, j;
1232 + int chan_no = 0;
1233 + u8 *buffer;
1234 + int byte_offset;
1235 + unsigned long flag;
1236 + struct dma_device_info *pDev;
1237 + struct dma_channel_info *pCh;
1238 + struct rx_desc *rx_desc_p;
1239 + struct tx_desc *tx_desc_p;
1240 +
1241 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1242 + pCh = dev->tx_chan[i];
1243 + if (pCh->control == LQ_DMA_CH_ON) {
1244 + chan_no = (int)(pCh - dma_chan);
1245 + for (j = 0; j < pCh->desc_len; j++) {
1246 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1247 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1248 + }
1249 + local_irq_save(flag);
1250 + lq_w32(chan_no, LQ_DMA_CS);
1251 + /* check if the descriptor length is changed */
1252 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1253 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1254 +
1255 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1256 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1257 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1258 + ;
1259 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1260 + lq_w32(0x30100, LQ_DMA_CCTRL); /* reset and enable channel,enable channel later */
1261 + local_irq_restore(flag);
1262 + }
1263 + }
1264 +
1265 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1266 + pCh = dev->rx_chan[i];
1267 + if (pCh->control == LQ_DMA_CH_ON) {
1268 + chan_no = (int)(pCh - dma_chan);
1269 +
1270 + for (j = 0; j < pCh->desc_len; j++) {
1271 + rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
1272 + pDev = (struct dma_device_info *)(pCh->dma_dev);
1273 + buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
1274 + if (!buffer)
1275 + break;
1276 +
1277 + dma_cache_inv((unsigned long) buffer, pCh->packet_size);
1278 +
1279 + rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
1280 + rx_desc_p->status.word = 0;
1281 + rx_desc_p->status.field.byte_offset = byte_offset;
1282 + rx_desc_p->status.field.OWN = DMA_OWN;
1283 + rx_desc_p->status.field.data_length = pCh->packet_size;
1284 + }
1285 +
1286 + local_irq_save(flag);
1287 + lq_w32(chan_no, LQ_DMA_CS);
1288 + /* check if the descriptor length is changed */
1289 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1290 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1291 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1292 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1293 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1294 + ;
1295 + lq_w32(0x0a, LQ_DMA_CIE); /* fix me, should enable all the interrupts here? */
1296 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1297 + lq_w32(0x30000, LQ_DMA_CCTRL);
1298 + local_irq_restore(flag);
1299 + lq_enable_irq(dma_chan[chan_no].irq);
1300 + }
1301 + }
1302 +}
1303 +EXPORT_SYMBOL(dma_device_register);
1304 +
1305 +void dma_device_unregister(struct dma_device_info *dev)
1306 +{
1307 + int i, j;
1308 + int chan_no;
1309 + struct dma_channel_info *pCh;
1310 + struct rx_desc *rx_desc_p;
1311 + struct tx_desc *tx_desc_p;
1312 + unsigned long flag;
1313 +
1314 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1315 + pCh = dev->tx_chan[i];
1316 + if (pCh->control == LQ_DMA_CH_ON) {
1317 + chan_no = (int)(dev->tx_chan[i] - dma_chan);
1318 + local_irq_save(flag);
1319 + lq_w32(chan_no, LQ_DMA_CS);
1320 + pCh->curr_desc = 0;
1321 + pCh->prev_desc = 0;
1322 + pCh->control = LQ_DMA_CH_OFF;
1323 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1324 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1325 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1326 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1327 + ;
1328 + local_irq_restore(flag);
1329 +
1330 + for (j = 0; j < pCh->desc_len; j++) {
1331 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1332 + if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
1333 + || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
1334 + dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
1335 + }
1336 + tx_desc_p->status.field.OWN = CPU_OWN;
1337 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1338 + }
1339 + /* TODO should free buffer that is not transferred by dma */
1340 + }
1341 + }
1342 +
1343 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1344 + pCh = dev->rx_chan[i];
1345 + chan_no = (int)(dev->rx_chan[i] - dma_chan);
1346 + lq_disable_irq(pCh->irq);
1347 +
1348 + local_irq_save(flag);
1349 + g_lq_dma_int_status &= ~(1 << chan_no);
1350 + pCh->curr_desc = 0;
1351 + pCh->prev_desc = 0;
1352 + pCh->control = LQ_DMA_CH_OFF;
1353 +
1354 + lq_w32(chan_no, LQ_DMA_CS);
1355 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1356 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1357 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1358 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1359 + ;
1360 +
1361 + local_irq_restore(flag);
1362 + for (j = 0; j < pCh->desc_len; j++) {
1363 + rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
1364 + if ((rx_desc_p->status.field.OWN == CPU_OWN
1365 + && rx_desc_p->status.field.C)
1366 + || (rx_desc_p->status.field.OWN == DMA_OWN
1367 + && rx_desc_p->status.field.data_length > 0)) {
1368 + dev->buffer_free((u8 *)
1369 + __va(rx_desc_p->Data_Pointer),
1370 + (void *) pCh->opt[j]);
1371 + }
1372 + }
1373 + }
1374 +}
1375 +EXPORT_SYMBOL(dma_device_unregister);
1376 +
1377 +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
1378 +{
1379 + u8 *buf;
1380 + int len;
1381 + int byte_offset = 0;
1382 + void *p = NULL;
1383 + struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
1384 + struct rx_desc *rx_desc_p;
1385 +
1386 + /* get the rx data first */
1387 + rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
1388 + if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
1389 + return 0;
1390 +
1391 + buf = (u8 *) __va(rx_desc_p->Data_Pointer);
1392 + *(u32 *)dataptr = (u32)buf;
1393 + len = rx_desc_p->status.field.data_length;
1394 +
1395 + if (opt)
1396 + *(int *)opt = (int)pCh->opt[pCh->curr_desc];
1397 +
1398 + /* replace with a new allocated buffer */
1399 + buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
1400 +
1401 + if (buf) {
1402 + dma_cache_inv((unsigned long) buf, pCh->packet_size);
1403 + pCh->opt[pCh->curr_desc] = p;
1404 + wmb();
1405 +
1406 + rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
1407 + rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
1408 + wmb();
1409 + } else {
1410 + *(u32 *) dataptr = 0;
1411 + if (opt)
1412 + *(int *) opt = 0;
1413 + len = 0;
1414 + }
1415 +
1416 + /* increase the curr_desc pointer */
1417 + pCh->curr_desc++;
1418 + if (pCh->curr_desc == pCh->desc_len)
1419 + pCh->curr_desc = 0;
1420 +
1421 + return len;
1422 +}
1423 +EXPORT_SYMBOL(dma_device_read);
1424 +
1425 +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
1426 +{
1427 + unsigned long flag;
1428 + u32 tmp, byte_offset;
1429 + struct dma_channel_info *pCh;
1430 + int chan_no;
1431 + struct tx_desc *tx_desc_p;
1432 + local_irq_save(flag);
1433 +
1434 + pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
1435 + chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
1436 +
1437 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1438 + while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
1439 + dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
1440 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1441 + pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
1442 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1443 + }
1444 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
1445 + /* Check whether this descriptor is available */
1446 + if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
1447 + /* if not, the tell the upper layer device */
1448 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1449 + local_irq_restore(flag);
1450 + printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
1451 +
1452 + return 0;
1453 + }
1454 + pCh->opt[pCh->curr_desc] = opt;
1455 + /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
1456 + byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
1457 + dma_cache_wback((unsigned long) dataptr, len);
1458 + wmb();
1459 + tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
1460 + wmb();
1461 + tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
1462 + wmb();
1463 +
1464 + pCh->curr_desc++;
1465 + if (pCh->curr_desc == pCh->desc_len)
1466 + pCh->curr_desc = 0;
1467 +
1468 + /*Check whether this descriptor is available */
1469 + tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
1470 + if (tx_desc_p->status.field.OWN == DMA_OWN) {
1471 + /*if not , the tell the upper layer device */
1472 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1473 + }
1474 +
1475 + lq_w32(chan_no, LQ_DMA_CS);
1476 + tmp = lq_r32(LQ_DMA_CCTRL);
1477 +
1478 + if (!(tmp & 1))
1479 + pCh->open(pCh);
1480 +
1481 + local_irq_restore(flag);
1482 +
1483 + return len;
1484 +}
1485 +EXPORT_SYMBOL(dma_device_write);
1486 +
1487 +int map_dma_chan(struct dma_chan_map *map)
1488 +{
1489 + int i, j;
1490 + int result;
1491 +
1492 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
1493 + strcpy(dma_devs[i].device_name, global_device_name[i]);
1494 +
1495 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1496 + dma_chan[i].irq = map[i].irq;
1497 + result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
1498 + if (result) {
1499 + printk(KERN_WARNING "error, cannot get dma_irq!\n");
1500 + free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
1501 +
1502 + return -EFAULT;
1503 + }
1504 + }
1505 +
1506 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1507 + dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
1508 + dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
1509 + dma_devs[i].max_rx_chan_num = 0;
1510 + dma_devs[i].max_tx_chan_num = 0;
1511 + dma_devs[i].buffer_alloc = &common_buffer_alloc;
1512 + dma_devs[i].buffer_free = &common_buffer_free;
1513 + dma_devs[i].intr_handler = NULL;
1514 + dma_devs[i].tx_burst_len = 4;
1515 + dma_devs[i].rx_burst_len = 4;
1516 + if (i == 0) {
1517 + lq_w32(0, LQ_DMA_PS);
1518 + lq_w32(lq_r32(LQ_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), LQ_DMA_PCTRL); /*enable dma drop */
1519 + }
1520 +
1521 + if (i == 1) {
1522 + lq_w32(1, LQ_DMA_PS);
1523 + lq_w32(0x14, LQ_DMA_PCTRL); /*deu port setting */
1524 + }
1525 +
1526 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1527 + dma_chan[j].byte_offset = 0;
1528 + dma_chan[j].open = &open_chan;
1529 + dma_chan[j].close = &close_chan;
1530 + dma_chan[j].reset = &reset_chan;
1531 + dma_chan[j].enable_irq = &enable_ch_irq;
1532 + dma_chan[j].disable_irq = &disable_ch_irq;
1533 + dma_chan[j].rel_chan_no = map[j].rel_chan_no;
1534 + dma_chan[j].control = LQ_DMA_CH_OFF;
1535 + dma_chan[j].default_weight = LQ_DMA_CH_DEFAULT_WEIGHT;
1536 + dma_chan[j].weight = dma_chan[j].default_weight;
1537 + dma_chan[j].curr_desc = 0;
1538 + dma_chan[j].prev_desc = 0;
1539 + }
1540 +
1541 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1542 + if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
1543 + if (map[j].dir == LQ_DMA_RX) {
1544 + dma_chan[j].dir = LQ_DMA_RX;
1545 + dma_devs[i].max_rx_chan_num++;
1546 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
1547 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
1548 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1549 + } else if (map[j].dir == LQ_DMA_TX) {
1550 + /*TX direction */
1551 + dma_chan[j].dir = LQ_DMA_TX;
1552 + dma_devs[i].max_tx_chan_num++;
1553 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
1554 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
1555 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1556 + } else {
1557 + printk(KERN_WARNING "WRONG DMA MAP!\n");
1558 + }
1559 + }
1560 + }
1561 + }
1562 +
1563 + return 0;
1564 +}
1565 +
1566 +void dma_chip_init(void)
1567 +{
1568 + int i;
1569 +
1570 + /* enable DMA from PMU */
1571 + lq_pmu_enable(PMU_DMA);
1572 +
1573 + /* reset DMA */
1574 + lq_w32(lq_r32(LQ_DMA_CTRL) | 1, LQ_DMA_CTRL);
1575 +
1576 + /* disable all interrupts */
1577 + lq_w32(0, LQ_DMA_IRNEN);
1578 +
1579 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1580 + lq_w32(i, LQ_DMA_CS);
1581 + lq_w32(0x2, LQ_DMA_CCTRL);
1582 + lq_w32(0x80000040, LQ_DMA_CPOLL);
1583 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~0x1, LQ_DMA_CCTRL);
1584 + }
1585 +}
1586 +
1587 +int lq_dma_init(void)
1588 +{
1589 + int i;
1590 +
1591 + dma_chip_init();
1592 +
1593 + if (map_dma_chan(default_dma_map))
1594 + BUG();
1595 +
1596 + g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
1597 +
1598 + if (g_desc_list == NULL) {
1599 + printk(KERN_WARNING "no memory for desriptor\n");
1600 + return -ENOMEM;
1601 + }
1602 +
1603 + memset(g_desc_list, 0, PAGE_SIZE);
1604 +
1605 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1606 + dma_chan[i].desc_base = (u32)g_desc_list + i * LQ_DMA_DESCRIPTOR_OFFSET * 8;
1607 + dma_chan[i].curr_desc = 0;
1608 + dma_chan[i].desc_len = LQ_DMA_DESCRIPTOR_OFFSET;
1609 +
1610 + lq_w32(i, LQ_DMA_CS);
1611 + lq_w32((u32)CPHYSADDR(dma_chan[i].desc_base), LQ_DMA_CDBA);
1612 + lq_w32(dma_chan[i].desc_len, LQ_DMA_CDLEN);
1613 + }
1614 + return 0;
1615 +}
1616 +
1617 +arch_initcall(lq_dma_init);
1618 +
1619 +void dma_cleanup(void)
1620 +{
1621 + int i;
1622 +
1623 + free_page(KSEG0ADDR((unsigned long) g_desc_list));
1624 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1625 + free_irq(dma_chan[i].irq, (void *)&dma_interrupt);
1626 +}
1627 +
1628 +MODULE_LICENSE("GPL");
1629 --- /dev/null
1630 +++ b/arch/mips/lantiq/xway/pmu.c
1631 @@ -0,0 +1,36 @@
1632 +/*
1633 + * This program is free software; you can redistribute it and/or modify it
1634 + * under the terms of the GNU General Public License version 2 as published
1635 + * by the Free Software Foundation.
1636 + *
1637 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1638 + */
1639 +
1640 +#include <linux/kernel.h>
1641 +#include <linux/module.h>
1642 +#include <linux/version.h>
1643 +
1644 +#include <xway.h>
1645 +
1646 +#define LQ_PMU_PWDCR ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
1647 +#define LQ_PMU_PWDSR ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
1648 +
1649 +void
1650 +lq_pmu_enable(unsigned int module)
1651 +{
1652 + int err = 1000000;
1653 +
1654 + lq_w32(lq_r32(LQ_PMU_PWDCR) & ~module, LQ_PMU_PWDCR);
1655 + while (--err && (lq_r32(LQ_PMU_PWDSR) & module));
1656 +
1657 + if (!err)
1658 + panic("activating PMU module failed!");
1659 +}
1660 +EXPORT_SYMBOL(lq_pmu_enable);
1661 +
1662 +void
1663 +lq_pmu_disable(unsigned int module)
1664 +{
1665 + lq_w32(lq_r32(LQ_PMU_PWDCR) | module, LQ_PMU_PWDCR);
1666 +}
1667 +EXPORT_SYMBOL(lq_pmu_disable);
1668 --- /dev/null
1669 +++ b/arch/mips/lantiq/xway/timer.c
1670 @@ -0,0 +1,828 @@
1671 +#include <linux/kernel.h>
1672 +#include <linux/module.h>
1673 +#include <linux/version.h>
1674 +#include <linux/types.h>
1675 +#include <linux/fs.h>
1676 +#include <linux/miscdevice.h>
1677 +#include <linux/init.h>
1678 +#include <linux/uaccess.h>
1679 +#include <linux/unistd.h>
1680 +#include <linux/errno.h>
1681 +#include <linux/interrupt.h>
1682 +#include <linux/sched.h>
1683 +
1684 +#include <asm/irq.h>
1685 +#include <asm/div64.h>
1686 +
1687 +#include <xway.h>
1688 +#include <xway_irq.h>
1689 +#include <lantiq_timer.h>
1690 +
1691 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
1692 +
1693 +#ifdef TIMER1A
1694 +#define FIRST_TIMER TIMER1A
1695 +#else
1696 +#define FIRST_TIMER 2
1697 +#endif
1698 +
1699 +/*
1700 + * GPTC divider is set or not.
1701 + */
1702 +#define GPTU_CLC_RMC_IS_SET 0
1703 +
1704 +/*
1705 + * Timer Interrupt (IRQ)
1706 + */
1707 +/* Must be adjusted when ICU driver is available */
1708 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
1709 +
1710 +/*
1711 + * Bits Operation
1712 + */
1713 +#define GET_BITS(x, msb, lsb) \
1714 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
1715 +#define SET_BITS(x, msb, lsb, value) \
1716 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
1717 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
1718 +
1719 +/*
1720 + * GPTU Register Mapping
1721 + */
1722 +#define LQ_GPTU (KSEG1 + 0x1E100A00)
1723 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
1724 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
1725 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1726 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1727 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1728 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1729 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
1730 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
1731 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
1732 +
1733 +/*
1734 + * Clock Control Register
1735 + */
1736 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
1737 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
1738 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
1739 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
1740 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
1741 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
1742 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
1743 +
1744 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
1745 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
1746 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
1747 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
1748 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
1749 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
1750 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
1751 +
1752 +/*
1753 + * ID Register
1754 + */
1755 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
1756 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
1757 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
1758 +
1759 +/*
1760 + * Control Register of Timer/Counter nX
1761 + * n is the index of block (1 based index)
1762 + * X is either A or B
1763 + */
1764 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
1765 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
1766 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
1767 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
1768 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
1769 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
1770 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
1771 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
1772 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
1773 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
1774 +
1775 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
1776 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
1777 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
1778 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
1779 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
1780 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
1781 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
1782 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
1783 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
1784 +
1785 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
1786 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
1787 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
1788 +
1789 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1790 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1791 +
1792 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
1793 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
1794 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
1795 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
1796 +#define TIMER_FLAG_NONE_EDGE 0x0000
1797 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
1798 +#define TIMER_FLAG_REAL 0x0000
1799 +#define TIMER_FLAG_INVERT 0x0040
1800 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
1801 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
1802 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
1803 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
1804 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
1805 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
1806 +
1807 +struct timer_dev_timer {
1808 + unsigned int f_irq_on;
1809 + unsigned int irq;
1810 + unsigned int flag;
1811 + unsigned long arg1;
1812 + unsigned long arg2;
1813 +};
1814 +
1815 +struct timer_dev {
1816 + struct mutex gptu_mutex;
1817 + unsigned int number_of_timers;
1818 + unsigned int occupation;
1819 + unsigned int f_gptu_on;
1820 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
1821 +};
1822 +
1823 +static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
1824 +static int gptu_open(struct inode *, struct file *);
1825 +static int gptu_release(struct inode *, struct file *);
1826 +
1827 +static struct file_operations gptu_fops = {
1828 + .owner = THIS_MODULE,
1829 + .ioctl = gptu_ioctl,
1830 + .open = gptu_open,
1831 + .release = gptu_release
1832 +};
1833 +
1834 +static struct miscdevice gptu_miscdev = {
1835 + .minor = MISC_DYNAMIC_MINOR,
1836 + .name = "gptu",
1837 + .fops = &gptu_fops,
1838 +};
1839 +
1840 +static struct timer_dev timer_dev;
1841 +
1842 +static irqreturn_t timer_irq_handler(int irq, void *p)
1843 +{
1844 + unsigned int timer;
1845 + unsigned int flag;
1846 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
1847 +
1848 + timer = irq - TIMER_INTERRUPT;
1849 + if (timer < timer_dev.number_of_timers
1850 + && dev_timer == &timer_dev.timer[timer]) {
1851 + /* Clear interrupt. */
1852 + lq_w32(1 << timer, LQ_GPTU_IRNCR);
1853 +
1854 + /* Call user hanler or signal. */
1855 + flag = dev_timer->flag;
1856 + if (!(timer & 0x01)
1857 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1858 + /* 16-bit timer or timer A of 32-bit timer */
1859 + switch (TIMER_FLAG_MASK_HANDLE(flag)) {
1860 + case TIMER_FLAG_CALLBACK_IN_IRQ:
1861 + case TIMER_FLAG_CALLBACK_IN_HB:
1862 + if (dev_timer->arg1)
1863 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
1864 + break;
1865 + case TIMER_FLAG_SIGNAL:
1866 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
1867 + break;
1868 + }
1869 + }
1870 + }
1871 + return IRQ_HANDLED;
1872 +}
1873 +
1874 +static inline void lq_enable_gptu(void)
1875 +{
1876 + lq_pmu_enable(PMU_GPT);
1877 +
1878 + /* Set divider as 1, disable write protection for SPEN, enable module. */
1879 + *LQ_GPTU_CLC =
1880 + GPTU_CLC_SMC_SET(0x00) |
1881 + GPTU_CLC_RMC_SET(0x01) |
1882 + GPTU_CLC_FSOE_SET(0) |
1883 + GPTU_CLC_SBWE_SET(1) |
1884 + GPTU_CLC_EDIS_SET(0) |
1885 + GPTU_CLC_SPEN_SET(0) |
1886 + GPTU_CLC_DISR_SET(0);
1887 +}
1888 +
1889 +static inline void lq_disable_gptu(void)
1890 +{
1891 + lq_w32(0x00, LQ_GPTU_IRNEN);
1892 + lq_w32(0xfff, LQ_GPTU_IRNCR);
1893 +
1894 + /* Set divider as 0, enable write protection for SPEN, disable module. */
1895 + *LQ_GPTU_CLC =
1896 + GPTU_CLC_SMC_SET(0x00) |
1897 + GPTU_CLC_RMC_SET(0x00) |
1898 + GPTU_CLC_FSOE_SET(0) |
1899 + GPTU_CLC_SBWE_SET(0) |
1900 + GPTU_CLC_EDIS_SET(0) |
1901 + GPTU_CLC_SPEN_SET(0) |
1902 + GPTU_CLC_DISR_SET(1);
1903 +
1904 + lq_pmu_disable(PMU_GPT);
1905 +}
1906 +
1907 +int lq_request_timer(unsigned int timer, unsigned int flag,
1908 + unsigned long value, unsigned long arg1, unsigned long arg2)
1909 +{
1910 + int ret = 0;
1911 + unsigned int con_reg, irnen_reg;
1912 + int n, X;
1913 +
1914 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
1915 + return -EINVAL;
1916 +
1917 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
1918 + timer, flag, value);
1919 +
1920 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
1921 + value &= 0xFFFF;
1922 + else
1923 + timer &= ~0x01;
1924 +
1925 + mutex_lock(&timer_dev.gptu_mutex);
1926 +
1927 + /*
1928 + * Allocate timer.
1929 + */
1930 + if (timer < FIRST_TIMER) {
1931 + unsigned int mask;
1932 + unsigned int shift;
1933 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
1934 + unsigned int offset = TIMER2A;
1935 +
1936 + /*
1937 + * Pick up a free timer.
1938 + */
1939 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1940 + mask = 1 << offset;
1941 + shift = 1;
1942 + } else {
1943 + mask = 3 << offset;
1944 + shift = 2;
1945 + }
1946 + for (timer = offset;
1947 + timer < offset + timer_dev.number_of_timers;
1948 + timer += shift, mask <<= shift)
1949 + if (!(timer_dev.occupation & mask)) {
1950 + timer_dev.occupation |= mask;
1951 + break;
1952 + }
1953 + if (timer >= offset + timer_dev.number_of_timers) {
1954 + printk("failed![%d]\n", __LINE__);
1955 + mutex_unlock(&timer_dev.gptu_mutex);
1956 + return -EINVAL;
1957 + } else
1958 + ret = timer;
1959 + } else {
1960 + register unsigned int mask;
1961 +
1962 + /*
1963 + * Check if the requested timer is free.
1964 + */
1965 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
1966 + if ((timer_dev.occupation & mask)) {
1967 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
1968 + __LINE__, mask, timer_dev.occupation);
1969 + mutex_unlock(&timer_dev.gptu_mutex);
1970 + return -EBUSY;
1971 + } else {
1972 + timer_dev.occupation |= mask;
1973 + ret = 0;
1974 + }
1975 + }
1976 +
1977 + /*
1978 + * Prepare control register value.
1979 + */
1980 + switch (TIMER_FLAG_MASK_EDGE(flag)) {
1981 + default:
1982 + case TIMER_FLAG_NONE_EDGE:
1983 + con_reg = GPTU_CON_EDGE_SET(0x00);
1984 + break;
1985 + case TIMER_FLAG_RISE_EDGE:
1986 + con_reg = GPTU_CON_EDGE_SET(0x01);
1987 + break;
1988 + case TIMER_FLAG_FALL_EDGE:
1989 + con_reg = GPTU_CON_EDGE_SET(0x02);
1990 + break;
1991 + case TIMER_FLAG_ANY_EDGE:
1992 + con_reg = GPTU_CON_EDGE_SET(0x03);
1993 + break;
1994 + }
1995 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
1996 + con_reg |=
1997 + TIMER_FLAG_MASK_SRC(flag) ==
1998 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
1999 + GPTU_CON_SRC_EXT_SET(0);
2000 + else
2001 + con_reg |=
2002 + TIMER_FLAG_MASK_SRC(flag) ==
2003 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
2004 + GPTU_CON_SRC_EG_SET(0);
2005 + con_reg |=
2006 + TIMER_FLAG_MASK_SYNC(flag) ==
2007 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
2008 + GPTU_CON_SYNC_SET(1);
2009 + con_reg |=
2010 + TIMER_FLAG_MASK_INVERT(flag) ==
2011 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2012 + con_reg |=
2013 + TIMER_FLAG_MASK_SIZE(flag) ==
2014 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
2015 + GPTU_CON_EXT_SET(1);
2016 + con_reg |=
2017 + TIMER_FLAG_MASK_STOP(flag) ==
2018 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2019 + con_reg |=
2020 + TIMER_FLAG_MASK_TYPE(flag) ==
2021 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
2022 + GPTU_CON_CNT_SET(1);
2023 + con_reg |=
2024 + TIMER_FLAG_MASK_DIR(flag) ==
2025 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2026 +
2027 + /*
2028 + * Fill up running data.
2029 + */
2030 + timer_dev.timer[timer - FIRST_TIMER].flag = flag;
2031 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
2032 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
2033 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2034 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
2035 +
2036 + /*
2037 + * Enable GPTU module.
2038 + */
2039 + if (!timer_dev.f_gptu_on) {
2040 + lq_enable_gptu();
2041 + timer_dev.f_gptu_on = 1;
2042 + }
2043 +
2044 + /*
2045 + * Enable IRQ.
2046 + */
2047 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
2048 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
2049 + timer_dev.timer[timer - FIRST_TIMER].arg1 =
2050 + (unsigned long) find_task_by_vpid((int) arg1);
2051 +
2052 + irnen_reg = 1 << (timer - FIRST_TIMER);
2053 +
2054 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
2055 + || (TIMER_FLAG_MASK_HANDLE(flag) ==
2056 + TIMER_FLAG_CALLBACK_IN_IRQ
2057 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
2058 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2059 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
2060 + }
2061 + } else
2062 + irnen_reg = 0;
2063 +
2064 + /*
2065 + * Write config register, reload value and enable interrupt.
2066 + */
2067 + n = timer >> 1;
2068 + X = timer & 0x01;
2069 + *LQ_GPTU_CON(n, X) = con_reg;
2070 + *LQ_GPTU_RELOAD(n, X) = value;
2071 + /* printk("reload value = %d\n", (u32)value); */
2072 + *LQ_GPTU_IRNEN |= irnen_reg;
2073 +
2074 + mutex_unlock(&timer_dev.gptu_mutex);
2075 + printk("successful!\n");
2076 + return ret;
2077 +}
2078 +EXPORT_SYMBOL(lq_request_timer);
2079 +
2080 +int lq_free_timer(unsigned int timer)
2081 +{
2082 + unsigned int flag;
2083 + unsigned int mask;
2084 + int n, X;
2085 +
2086 + if (!timer_dev.f_gptu_on)
2087 + return -EINVAL;
2088 +
2089 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2090 + return -EINVAL;
2091 +
2092 + mutex_lock(&timer_dev.gptu_mutex);
2093 +
2094 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2095 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2096 + timer &= ~0x01;
2097 +
2098 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2099 + if (((timer_dev.occupation & mask) ^ mask)) {
2100 + mutex_unlock(&timer_dev.gptu_mutex);
2101 + return -EINVAL;
2102 + }
2103 +
2104 + n = timer >> 1;
2105 + X = timer & 0x01;
2106 +
2107 + if (GPTU_CON_EN(n, X))
2108 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2109 +
2110 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
2111 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
2112 +
2113 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
2114 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2115 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
2116 + }
2117 +
2118 + timer_dev.occupation &= ~mask;
2119 + if (!timer_dev.occupation && timer_dev.f_gptu_on) {
2120 + lq_disable_gptu();
2121 + timer_dev.f_gptu_on = 0;
2122 + }
2123 +
2124 + mutex_unlock(&timer_dev.gptu_mutex);
2125 +
2126 + return 0;
2127 +}
2128 +EXPORT_SYMBOL(lq_free_timer);
2129 +
2130 +int lq_start_timer(unsigned int timer, int is_resume)
2131 +{
2132 + unsigned int flag;
2133 + unsigned int mask;
2134 + int n, X;
2135 +
2136 + if (!timer_dev.f_gptu_on)
2137 + return -EINVAL;
2138 +
2139 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2140 + return -EINVAL;
2141 +
2142 + mutex_lock(&timer_dev.gptu_mutex);
2143 +
2144 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2145 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2146 + timer &= ~0x01;
2147 +
2148 + mask = (TIMER_FLAG_MASK_SIZE(flag) ==
2149 + TIMER_FLAG_16BIT ? 1 : 3) << timer;
2150 + if (((timer_dev.occupation & mask) ^ mask)) {
2151 + mutex_unlock(&timer_dev.gptu_mutex);
2152 + return -EINVAL;
2153 + }
2154 +
2155 + n = timer >> 1;
2156 + X = timer & 0x01;
2157 +
2158 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
2159 +
2160 + mutex_unlock(&timer_dev.gptu_mutex);
2161 +
2162 + return 0;
2163 +}
2164 +EXPORT_SYMBOL(lq_start_timer);
2165 +
2166 +int lq_stop_timer(unsigned int timer)
2167 +{
2168 + unsigned int flag;
2169 + unsigned int mask;
2170 + int n, X;
2171 +
2172 + if (!timer_dev.f_gptu_on)
2173 + return -EINVAL;
2174 +
2175 + if (timer < FIRST_TIMER
2176 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2177 + return -EINVAL;
2178 +
2179 + mutex_lock(&timer_dev.gptu_mutex);
2180 +
2181 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2182 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2183 + timer &= ~0x01;
2184 +
2185 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2186 + if (((timer_dev.occupation & mask) ^ mask)) {
2187 + mutex_unlock(&timer_dev.gptu_mutex);
2188 + return -EINVAL;
2189 + }
2190 +
2191 + n = timer >> 1;
2192 + X = timer & 0x01;
2193 +
2194 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2195 +
2196 + mutex_unlock(&timer_dev.gptu_mutex);
2197 +
2198 + return 0;
2199 +}
2200 +EXPORT_SYMBOL(lq_stop_timer);
2201 +
2202 +int lq_reset_counter_flags(u32 timer, u32 flags)
2203 +{
2204 + unsigned int oflag;
2205 + unsigned int mask, con_reg;
2206 + int n, X;
2207 +
2208 + if (!timer_dev.f_gptu_on)
2209 + return -EINVAL;
2210 +
2211 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2212 + return -EINVAL;
2213 +
2214 + mutex_lock(&timer_dev.gptu_mutex);
2215 +
2216 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
2217 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
2218 + timer &= ~0x01;
2219 +
2220 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2221 + if (((timer_dev.occupation & mask) ^ mask)) {
2222 + mutex_unlock(&timer_dev.gptu_mutex);
2223 + return -EINVAL;
2224 + }
2225 +
2226 + switch (TIMER_FLAG_MASK_EDGE(flags)) {
2227 + default:
2228 + case TIMER_FLAG_NONE_EDGE:
2229 + con_reg = GPTU_CON_EDGE_SET(0x00);
2230 + break;
2231 + case TIMER_FLAG_RISE_EDGE:
2232 + con_reg = GPTU_CON_EDGE_SET(0x01);
2233 + break;
2234 + case TIMER_FLAG_FALL_EDGE:
2235 + con_reg = GPTU_CON_EDGE_SET(0x02);
2236 + break;
2237 + case TIMER_FLAG_ANY_EDGE:
2238 + con_reg = GPTU_CON_EDGE_SET(0x03);
2239 + break;
2240 + }
2241 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
2242 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
2243 + else
2244 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
2245 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
2246 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2247 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
2248 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2249 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
2250 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2251 +
2252 + timer_dev.timer[timer - FIRST_TIMER].flag = flags;
2253 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
2254 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
2255 +
2256 + n = timer >> 1;
2257 + X = timer & 0x01;
2258 +
2259 + *LQ_GPTU_CON(n, X) = con_reg;
2260 + smp_wmb();
2261 + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
2262 + mutex_unlock(&timer_dev.gptu_mutex);
2263 + return 0;
2264 +}
2265 +EXPORT_SYMBOL(lq_reset_counter_flags);
2266 +
2267 +int lq_get_count_value(unsigned int timer, unsigned long *value)
2268 +{
2269 + unsigned int flag;
2270 + unsigned int mask;
2271 + int n, X;
2272 +
2273 + if (!timer_dev.f_gptu_on)
2274 + return -EINVAL;
2275 +
2276 + if (timer < FIRST_TIMER
2277 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2278 + return -EINVAL;
2279 +
2280 + mutex_lock(&timer_dev.gptu_mutex);
2281 +
2282 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2283 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2284 + timer &= ~0x01;
2285 +
2286 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2287 + if (((timer_dev.occupation & mask) ^ mask)) {
2288 + mutex_unlock(&timer_dev.gptu_mutex);
2289 + return -EINVAL;
2290 + }
2291 +
2292 + n = timer >> 1;
2293 + X = timer & 0x01;
2294 +
2295 + *value = *LQ_GPTU_COUNT(n, X);
2296 +
2297 + mutex_unlock(&timer_dev.gptu_mutex);
2298 +
2299 + return 0;
2300 +}
2301 +EXPORT_SYMBOL(lq_get_count_value);
2302 +
2303 +u32 lq_cal_divider(unsigned long freq)
2304 +{
2305 + u64 module_freq, fpi = lq_get_fpi_bus_clock(2);
2306 + u32 clock_divider = 1;
2307 + module_freq = fpi * 1000;
2308 + do_div(module_freq, clock_divider * freq);
2309 + return module_freq;
2310 +}
2311 +EXPORT_SYMBOL(lq_cal_divider);
2312 +
2313 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
2314 + int is_ext_src, unsigned int handle_flag, unsigned long arg1,
2315 + unsigned long arg2)
2316 +{
2317 + unsigned long divider;
2318 + unsigned int flag;
2319 +
2320 + divider = lq_cal_divider(freq);
2321 + if (divider == 0)
2322 + return -EINVAL;
2323 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
2324 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
2325 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
2326 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
2327 + | TIMER_FLAG_MASK_HANDLE(handle_flag);
2328 +
2329 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
2330 + timer, freq, divider);
2331 + return lq_request_timer(timer, flag, divider, arg1, arg2);
2332 +}
2333 +EXPORT_SYMBOL(lq_set_timer);
2334 +
2335 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
2336 + unsigned long arg1, unsigned long arg2)
2337 +{
2338 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
2339 + return lq_request_timer(timer, flag, reload, arg1, arg2);
2340 +}
2341 +EXPORT_SYMBOL(lq_set_counter);
2342 +
2343 +static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
2344 + unsigned long arg)
2345 +{
2346 + int ret;
2347 + struct gptu_ioctl_param param;
2348 +
2349 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
2350 + return -EFAULT;
2351 + copy_from_user(&param, (void *) arg, sizeof(param));
2352 +
2353 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
2354 + || GPTU_SET_COUNTER) && param.timer < 2)
2355 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
2356 + && !access_ok(VERIFY_WRITE, arg,
2357 + sizeof(struct gptu_ioctl_param)))
2358 + return -EFAULT;
2359 +
2360 + switch (cmd) {
2361 + case GPTU_REQUEST_TIMER:
2362 + ret = lq_request_timer(param.timer, param.flag, param.value,
2363 + (unsigned long) param.pid,
2364 + (unsigned long) param.sig);
2365 + if (ret > 0) {
2366 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2367 + timer, &ret, sizeof(&ret));
2368 + ret = 0;
2369 + }
2370 + break;
2371 + case GPTU_FREE_TIMER:
2372 + ret = lq_free_timer(param.timer);
2373 + break;
2374 + case GPTU_START_TIMER:
2375 + ret = lq_start_timer(param.timer, param.flag);
2376 + break;
2377 + case GPTU_STOP_TIMER:
2378 + ret = lq_stop_timer(param.timer);
2379 + break;
2380 + case GPTU_GET_COUNT_VALUE:
2381 + ret = lq_get_count_value(param.timer, &param.value);
2382 + if (!ret)
2383 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2384 + value, &param.value,
2385 + sizeof(param.value));
2386 + break;
2387 + case GPTU_CALCULATE_DIVIDER:
2388 + param.value = lq_cal_divider(param.value);
2389 + if (param.value == 0)
2390 + ret = -EINVAL;
2391 + else {
2392 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2393 + value, &param.value,
2394 + sizeof(param.value));
2395 + ret = 0;
2396 + }
2397 + break;
2398 + case GPTU_SET_TIMER:
2399 + ret = lq_set_timer(param.timer, param.value,
2400 + TIMER_FLAG_MASK_STOP(param.flag) !=
2401 + TIMER_FLAG_ONCE ? 1 : 0,
2402 + TIMER_FLAG_MASK_SRC(param.flag) ==
2403 + TIMER_FLAG_EXT_SRC ? 1 : 0,
2404 + TIMER_FLAG_MASK_HANDLE(param.flag) ==
2405 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
2406 + TIMER_FLAG_NO_HANDLE,
2407 + (unsigned long) param.pid,
2408 + (unsigned long) param.sig);
2409 + if (ret > 0) {
2410 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2411 + timer, &ret, sizeof(&ret));
2412 + ret = 0;
2413 + }
2414 + break;
2415 + case GPTU_SET_COUNTER:
2416 + lq_set_counter(param.timer, param.flag, param.value, 0, 0);
2417 + if (ret > 0) {
2418 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2419 + timer, &ret, sizeof(&ret));
2420 + ret = 0;
2421 + }
2422 + break;
2423 + default:
2424 + ret = -ENOTTY;
2425 + }
2426 +
2427 + return ret;
2428 +}
2429 +
2430 +static int gptu_open(struct inode *inode, struct file *file)
2431 +{
2432 + return 0;
2433 +}
2434 +
2435 +static int gptu_release(struct inode *inode, struct file *file)
2436 +{
2437 + return 0;
2438 +}
2439 +
2440 +int __init lq_gptu_init(void)
2441 +{
2442 + int ret;
2443 + unsigned int i;
2444 +
2445 + lq_w32(0, LQ_GPTU_IRNEN);
2446 + lq_w32(0xfff, LQ_GPTU_IRNCR);
2447 +
2448 + memset(&timer_dev, 0, sizeof(timer_dev));
2449 + mutex_init(&timer_dev.gptu_mutex);
2450 +
2451 + lq_enable_gptu();
2452 + timer_dev.number_of_timers = GPTU_ID_CFG * 2;
2453 + lq_disable_gptu();
2454 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
2455 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
2456 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
2457 +
2458 + ret = misc_register(&gptu_miscdev);
2459 + if (ret) {
2460 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
2461 + return ret;
2462 + } else {
2463 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
2464 + }
2465 +
2466 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2467 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
2468 + if (ret) {
2469 + for (; i >= 0; i--)
2470 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
2471 + misc_deregister(&gptu_miscdev);
2472 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
2473 + return ret;
2474 + } else {
2475 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
2476 + disable_irq(timer_dev.timer[i].irq);
2477 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
2478 + }
2479 + }
2480 +
2481 + return 0;
2482 +}
2483 +
2484 +void __exit lq_gptu_exit(void)
2485 +{
2486 + unsigned int i;
2487 +
2488 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2489 + if (timer_dev.timer[i].f_irq_on)
2490 + disable_irq(timer_dev.timer[i].irq);
2491 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
2492 + }
2493 + lq_disable_gptu();
2494 + misc_deregister(&gptu_miscdev);
2495 +}
2496 +
2497 +module_init(lq_gptu_init);
2498 +module_exit(lq_gptu_exit);
2499 --- /dev/null
2500 +++ b/arch/mips/lantiq/xway/timer.h
2501 @@ -0,0 +1,155 @@
2502 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2503 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2504 +
2505 +
2506 +/******************************************************************************
2507 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
2508 +
2509 + No Warranty
2510 + Because the program is licensed free of charge, there is no warranty for
2511 + the program, to the extent permitted by applicable law. Except when
2512 + otherwise stated in writing the copyright holders and/or other parties
2513 + provide the program "as is" without warranty of any kind, either
2514 + expressed or implied, including, but not limited to, the implied
2515 + warranties of merchantability and fitness for a particular purpose. The
2516 + entire risk as to the quality and performance of the program is with
2517 + you. should the program prove defective, you assume the cost of all
2518 + necessary servicing, repair or correction.
2519 +
2520 + In no event unless required by applicable law or agreed to in writing
2521 + will any copyright holder, or any other party who may modify and/or
2522 + redistribute the program as permitted above, be liable to you for
2523 + damages, including any general, special, incidental or consequential
2524 + damages arising out of the use or inability to use the program
2525 + (including but not limited to loss of data or data being rendered
2526 + inaccurate or losses sustained by you or third parties or a failure of
2527 + the program to operate with any other programs), even if such holder or
2528 + other party has been advised of the possibility of such damages.
2529 +******************************************************************************/
2530 +
2531 +
2532 +/*
2533 + * ####################################
2534 + * Definition
2535 + * ####################################
2536 + */
2537 +
2538 +/*
2539 + * Available Timer/Counter Index
2540 + */
2541 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
2542 +#define TIMER_ANY 0x00
2543 +#define TIMER1A TIMER(1, 0)
2544 +#define TIMER1B TIMER(1, 1)
2545 +#define TIMER2A TIMER(2, 0)
2546 +#define TIMER2B TIMER(2, 1)
2547 +#define TIMER3A TIMER(3, 0)
2548 +#define TIMER3B TIMER(3, 1)
2549 +
2550 +/*
2551 + * Flag of Timer/Counter
2552 + * These flags specify the way in which timer is configured.
2553 + */
2554 +/* Bit size of timer/counter. */
2555 +#define TIMER_FLAG_16BIT 0x0000
2556 +#define TIMER_FLAG_32BIT 0x0001
2557 +/* Switch between timer and counter. */
2558 +#define TIMER_FLAG_TIMER 0x0000
2559 +#define TIMER_FLAG_COUNTER 0x0002
2560 +/* Stop or continue when overflowing/underflowing. */
2561 +#define TIMER_FLAG_ONCE 0x0000
2562 +#define TIMER_FLAG_CYCLIC 0x0004
2563 +/* Count up or counter down. */
2564 +#define TIMER_FLAG_UP 0x0000
2565 +#define TIMER_FLAG_DOWN 0x0008
2566 +/* Count on specific level or edge. */
2567 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
2568 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
2569 +#define TIMER_FLAG_RISE_EDGE 0x0010
2570 +#define TIMER_FLAG_FALL_EDGE 0x0020
2571 +#define TIMER_FLAG_ANY_EDGE 0x0030
2572 +/* Signal is syncronous to module clock or not. */
2573 +#define TIMER_FLAG_UNSYNC 0x0000
2574 +#define TIMER_FLAG_SYNC 0x0080
2575 +/* Different interrupt handle type. */
2576 +#define TIMER_FLAG_NO_HANDLE 0x0000
2577 +#if defined(__KERNEL__)
2578 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
2579 +#endif // defined(__KERNEL__)
2580 +#define TIMER_FLAG_SIGNAL 0x0300
2581 +/* Internal clock source or external clock source */
2582 +#define TIMER_FLAG_INT_SRC 0x0000
2583 +#define TIMER_FLAG_EXT_SRC 0x1000
2584 +
2585 +
2586 +/*
2587 + * ioctl Command
2588 + */
2589 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
2590 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
2591 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
2592 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
2593 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
2594 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
2595 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
2596 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
2597 +
2598 +/*
2599 + * Data Type Used to Call ioctl
2600 + */
2601 +struct gptu_ioctl_param {
2602 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2603 + * GPTU_SET_COUNTER, this field is ID of expected *
2604 + * timer/counter. If it's zero, a timer/counter would *
2605 + * be dynamically allocated and ID would be stored in *
2606 + * this field. *
2607 + * In command GPTU_GET_COUNT_VALUE, this field is *
2608 + * ignored. *
2609 + * In other command, this field is ID of timer/counter *
2610 + * allocated. */
2611 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2612 + * GPTU_SET_COUNTER, this field contains flags to *
2613 + * specify how to configure timer/counter. *
2614 + * In command GPTU_START_TIMER, zero indicate start *
2615 + * and non-zero indicate resume timer/counter. *
2616 + * In other command, this field is ignored. */
2617 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
2618 + * init/reload value. *
2619 + * In command GPTU_SET_TIMER, this field contains *
2620 + * frequency (0.001Hz) of timer. *
2621 + * In command GPTU_GET_COUNT_VALUE, current count *
2622 + * value would be stored in this field. *
2623 + * In command GPTU_CALCULATE_DIVIDER, this field *
2624 + * contains frequency wanted, and after calculation, *
2625 + * divider would be stored in this field to overwrite *
2626 + * the frequency. *
2627 + * In other command, this field is ignored. */
2628 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2629 + * if signal is required, this field contains process *
2630 + * ID to which signal would be sent. *
2631 + * In other command, this field is ignored. */
2632 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2633 + * if signal is required, this field contains signal *
2634 + * number which would be sent. *
2635 + * In other command, this field is ignored. */
2636 +};
2637 +
2638 +/*
2639 + * ####################################
2640 + * Data Type
2641 + * ####################################
2642 + */
2643 +typedef void (*timer_callback)(unsigned long arg);
2644 +
2645 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
2646 +extern int ifxmips_free_timer(unsigned int);
2647 +extern int ifxmips_start_timer(unsigned int, int);
2648 +extern int ifxmips_stop_timer(unsigned int);
2649 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
2650 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
2651 +extern u32 ifxmips_cal_divider(unsigned long);
2652 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
2653 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
2654 + u32 reload, unsigned long arg1, unsigned long arg2);
2655 +
2656 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
2657 --- /dev/null
2658 +++ b/arch/mips/lantiq/xway/Makefile
2659 @@ -0,0 +1,5 @@
2660 +obj-y := pmu.o prom.o dma.o timer.o reset.o clk-xway.o
2661 +obj-y += gpio.o gpio_ebu.o gpio_leds.o devices.o
2662 +obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
2663 +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
2664 +obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
2665 --- /dev/null
2666 +++ b/arch/mips/lantiq/xway/clk-xway.c
2667 @@ -0,0 +1,219 @@
2668 +/*
2669 + * This program is free software; you can redistribute it and/or modify it
2670 + * under the terms of the GNU General Public License version 2 as published
2671 + * by the Free Software Foundation.
2672 + *
2673 + * Copyright (C) 2007 Xu Liang, infineon
2674 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2675 + */
2676 +
2677 +#include <linux/io.h>
2678 +#include <linux/module.h>
2679 +#include <linux/init.h>
2680 +#include <linux/clk.h>
2681 +
2682 +#include <asm/time.h>
2683 +#include <asm/irq.h>
2684 +#include <asm/div64.h>
2685 +
2686 +#include <xway.h>
2687 +
2688 +static unsigned int lq_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
2689 +#define DDR_HZ lq_ram_clocks[lq_r32(LQ_CGU_SYS) & 0x3]
2690 +
2691 +#define BASIC_FREQUENCY_1 35328000
2692 +#define BASIC_FREQUENCY_2 36000000
2693 +#define BASIS_REQUENCY_USB 12000000
2694 +
2695 +#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
2696 +
2697 +#define CGU_PLL0_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 31))
2698 +#define CGU_PLL0_BYPASS (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 30))
2699 +#define CGU_PLL0_CFG_DSMSEL (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 28))
2700 +#define CGU_PLL0_CFG_FRAC_EN (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 27))
2701 +#define CGU_PLL1_SRC (lq_r32(LQ_CGU_PLL1_CFG) & (1 << 31))
2702 +#define CGU_PLL2_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL2_CFG) & (1 << 20))
2703 +#define CGU_SYS_FPI_SEL (1 << 6)
2704 +#define CGU_SYS_DDR_SEL 0x3
2705 +#define CGU_PLL0_SRC (1 << 29)
2706 +
2707 +#define CGU_PLL0_CFG_PLLK GET_BITS(*LQ_CGU_PLL0_CFG, 26, 17)
2708 +#define CGU_PLL0_CFG_PLLN GET_BITS(*LQ_CGU_PLL0_CFG, 12, 6)
2709 +#define CGU_PLL0_CFG_PLLM GET_BITS(*LQ_CGU_PLL0_CFG, 5, 2)
2710 +#define CGU_PLL2_SRC GET_BITS(*LQ_CGU_PLL2_CFG, 18, 17)
2711 +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*LQ_CGU_PLL2_CFG, 16, 13)
2712 +
2713 +#define LQ_GPTU_GPT_CLC ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
2714 +#define LQ_CGU_PLL0_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0004))
2715 +#define LQ_CGU_PLL1_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0008))
2716 +#define LQ_CGU_PLL2_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x000C))
2717 +#define LQ_CGU_SYS ((u32 *)(LQ_CGU_BASE_ADDR + 0x0010))
2718 +#define LQ_CGU_UPDATE ((u32 *)(LQ_CGU_BASE_ADDR + 0x0014))
2719 +#define LQ_CGU_IF_CLK ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
2720 +#define LQ_CGU_OSC_CON ((u32 *)(LQ_CGU_BASE_ADDR + 0x001C))
2721 +#define LQ_CGU_SMD ((u32 *)(LQ_CGU_BASE_ADDR + 0x0020))
2722 +#define LQ_CGU_CT1SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0028))
2723 +#define LQ_CGU_CT2SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x002C))
2724 +#define LQ_CGU_PCMCR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0030))
2725 +#define LQ_CGU_PCI_CR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
2726 +#define LQ_CGU_PD_PC ((u32 *)(LQ_CGU_BASE_ADDR + 0x0038))
2727 +#define LQ_CGU_FMR ((u32 *)(LQ_CGU_BASE_ADDR + 0x003C))
2728 +
2729 +static unsigned int lq_get_pll0_fdiv(void);
2730 +
2731 +static inline unsigned int
2732 +get_input_clock(int pll)
2733 +{
2734 + switch (pll) {
2735 + case 0:
2736 + if (lq_r32(LQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
2737 + return BASIS_REQUENCY_USB;
2738 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2739 + return BASIC_FREQUENCY_1;
2740 + else
2741 + return BASIC_FREQUENCY_2;
2742 + case 1:
2743 + if (CGU_PLL1_SRC)
2744 + return BASIS_REQUENCY_USB;
2745 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2746 + return BASIC_FREQUENCY_1;
2747 + else
2748 + return BASIC_FREQUENCY_2;
2749 + case 2:
2750 + switch (CGU_PLL2_SRC) {
2751 + case 0:
2752 + return lq_get_pll0_fdiv();
2753 + case 1:
2754 + return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
2755 + BASIC_FREQUENCY_1 :
2756 + BASIC_FREQUENCY_2;
2757 + case 2:
2758 + return BASIS_REQUENCY_USB;
2759 + }
2760 + default:
2761 + return 0;
2762 + }
2763 +}
2764 +
2765 +static inline unsigned int
2766 +cal_dsm(int pll, unsigned int num, unsigned int den)
2767 +{
2768 + u64 res, clock = get_input_clock(pll);
2769 + res = num * clock;
2770 + do_div(res, den);
2771 + return res;
2772 +}
2773 +
2774 +static inline unsigned int
2775 +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
2776 +{
2777 + unsigned int num = ((N + 1) << 10) + K;
2778 + unsigned int den = (M + 1) << 10;
2779 + return cal_dsm(pll, num, den);
2780 +}
2781 +
2782 +static inline unsigned int
2783 +ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
2784 +{
2785 + unsigned int num = ((N + 1) << 11) + K + 512;
2786 + unsigned int den = (M + 1) << 11;
2787 + return cal_dsm(pll, num, den);
2788 +}
2789 +
2790 +static inline unsigned int
2791 +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
2792 +{
2793 + unsigned int num = K >= 512 ?
2794 + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
2795 + unsigned int den = (M + 1) << 12;
2796 + return cal_dsm(pll, num, den);
2797 +}
2798 +
2799 +static inline unsigned int
2800 +dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
2801 + unsigned int dsmsel, unsigned int phase_div_en)
2802 +{
2803 + if (!dsmsel)
2804 + return mash_dsm(pll, M, N, K);
2805 + else if (!phase_div_en)
2806 + return mash_dsm(pll, M, N, K);
2807 + else
2808 + return ssff_dsm_2(pll, M, N, K);
2809 +}
2810 +
2811 +static inline unsigned int
2812 +lq_get_pll0_fosc(void)
2813 +{
2814 + if (CGU_PLL0_BYPASS)
2815 + return get_input_clock(0);
2816 + else
2817 + return !CGU_PLL0_CFG_FRAC_EN
2818 + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
2819 + CGU_PLL0_PHASE_DIVIDER_ENABLE)
2820 + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
2821 + CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
2822 +}
2823 +
2824 +static unsigned int
2825 +lq_get_pll0_fdiv(void)
2826 +{
2827 + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
2828 + return (lq_get_pll0_fosc() + (div >> 1)) / div;
2829 +}
2830 +
2831 +unsigned int
2832 +lq_get_io_region_clock(void)
2833 +{
2834 + unsigned int ret = lq_get_pll0_fosc();
2835 + switch (lq_r32(LQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
2836 + default:
2837 + case 0:
2838 + return (ret + 1) / 2;
2839 + case 1:
2840 + return (ret * 2 + 2) / 5;
2841 + case 2:
2842 + return (ret + 1) / 3;
2843 + case 3:
2844 + return (ret + 2) / 4;
2845 + }
2846 +}
2847 +EXPORT_SYMBOL(lq_get_io_region_clock);
2848 +
2849 +unsigned int
2850 +lq_get_fpi_bus_clock(int fpi)
2851 +{
2852 + unsigned int ret = lq_get_io_region_clock();
2853 + if ((fpi == 2) && (lq_r32(LQ_CGU_SYS) & CGU_SYS_FPI_SEL))
2854 + ret >>= 1;
2855 + return ret;
2856 +}
2857 +EXPORT_SYMBOL(lq_get_fpi_bus_clock);
2858 +
2859 +unsigned int
2860 +lq_get_cpu_hz(void)
2861 +{
2862 + switch (lq_r32(LQ_CGU_SYS) & 0xc)
2863 + {
2864 + case 0:
2865 + return CLOCK_333M;
2866 + case 4:
2867 + return DDR_HZ;
2868 + case 8:
2869 + return DDR_HZ << 1;
2870 + default:
2871 + return DDR_HZ >> 1;
2872 + }
2873 +}
2874 +EXPORT_SYMBOL(lq_get_cpu_hz);
2875 +
2876 +unsigned int
2877 +lq_get_fpi_hz(void)
2878 +{
2879 + unsigned int ddr_clock = DDR_HZ;
2880 + if (lq_r32(LQ_CGU_SYS) & 0x40)
2881 + return ddr_clock >> 1;
2882 + return ddr_clock;
2883 +}
2884 +EXPORT_SYMBOL(lq_get_fpi_hz);
2885 +
2886 +
2887 --- /dev/null
2888 +++ b/arch/mips/lantiq/xway/gpio.c
2889 @@ -0,0 +1,206 @@
2890 +/*
2891 + * This program is free software; you can redistribute it and/or modify it
2892 + * under the terms of the GNU General Public License version 2 as published
2893 + * by the Free Software Foundation.
2894 + *
2895 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2896 + */
2897 +
2898 +#include <linux/slab.h>
2899 +#include <linux/module.h>
2900 +#include <linux/platform_device.h>
2901 +#include <linux/gpio.h>
2902 +
2903 +#include <lantiq.h>
2904 +
2905 +#define LQ_GPIO0_BASE_ADDR 0x1E100B10
2906 +#define LQ_GPIO1_BASE_ADDR 0x1E100B40
2907 +#define LQ_GPIO_SIZE 0x30
2908 +
2909 +#define LQ_GPIO_OUT 0x00
2910 +#define LQ_GPIO_IN 0x04
2911 +#define LQ_GPIO_DIR 0x08
2912 +#define LQ_GPIO_ALTSEL0 0x0C
2913 +#define LQ_GPIO_ALTSEL1 0x10
2914 +#define LQ_GPIO_OD 0x14
2915 +
2916 +#define PINS_PER_PORT 16
2917 +
2918 +#define lq_gpio_getbit(m, r, p) !!(lq_r32(m + r) & (1 << p))
2919 +#define lq_gpio_setbit(m, r, p) lq_w32_mask(0, (1 << p), m + r)
2920 +#define lq_gpio_clearbit(m, r, p) lq_w32_mask((1 << p), 0, m + r)
2921 +
2922 +struct lq_gpio
2923 +{
2924 + void __iomem *membase;
2925 + struct gpio_chip chip;
2926 +};
2927 +
2928 +int
2929 +gpio_to_irq(unsigned int gpio)
2930 +{
2931 + return -EINVAL;
2932 +}
2933 +EXPORT_SYMBOL(gpio_to_irq);
2934 +
2935 +int
2936 +lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val)
2937 +{
2938 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2939 + if(pin >= (2 * PINS_PER_PORT))
2940 + return -EINVAL;
2941 + if(pin >= PINS_PER_PORT)
2942 + {
2943 + pin -= PINS_PER_PORT;
2944 + membase += LQ_GPIO_SIZE;
2945 + }
2946 + if(val)
2947 + lq_w32_mask(0, (1 << pin), membase + reg);
2948 + else
2949 + lq_w32_mask((1 << pin), 0, membase + reg);
2950 + return 0;
2951 +}
2952 +EXPORT_SYMBOL(lq_gpio_setconfig);
2953 +
2954 +int
2955 +lq_gpio_request(unsigned int pin, unsigned int alt0,
2956 + unsigned int alt1, unsigned int dir, const char *name)
2957 +{
2958 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2959 + if(pin >= (2 * PINS_PER_PORT))
2960 + return -EINVAL;
2961 + if(gpio_request(pin, name))
2962 + {
2963 + printk("failed to register %s gpio\n", name);
2964 + return -EBUSY;
2965 + }
2966 + if(dir)
2967 + gpio_direction_output(pin, 1);
2968 + else
2969 + gpio_direction_input(pin);
2970 + if(pin >= PINS_PER_PORT)
2971 + {
2972 + pin -= PINS_PER_PORT;
2973 + membase += LQ_GPIO_SIZE;
2974 + }
2975 + if(alt0)
2976 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL0, pin);
2977 + else
2978 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL0, pin);
2979 + if(alt1)
2980 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL1, pin);
2981 + else
2982 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL1, pin);
2983 + return 0;
2984 +}
2985 +EXPORT_SYMBOL(lq_gpio_request);
2986 +
2987 +static void
2988 +lq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
2989 +{
2990 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
2991 + if(value)
2992 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
2993 + else
2994 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
2995 +}
2996 +
2997 +static int
2998 +lq_gpio_get(struct gpio_chip *chip, unsigned int offset)
2999 +{
3000 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3001 + return lq_gpio_getbit(lq_gpio->membase, LQ_GPIO_IN, offset);
3002 +}
3003 +
3004 +static int
3005 +lq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
3006 +{
3007 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3008 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3009 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3010 + return 0;
3011 +}
3012 +
3013 +static int
3014 +lq_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
3015 +{
3016 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3017 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3018 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3019 + lq_gpio_set(chip, offset, value);
3020 + return 0;
3021 +}
3022 +
3023 +static int
3024 +lq_gpio_req(struct gpio_chip *chip, unsigned offset)
3025 +{
3026 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3027 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL0, offset);
3028 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL1, offset);
3029 + return 0;
3030 +}
3031 +
3032 +static int
3033 +lq_gpio_probe(struct platform_device *pdev)
3034 +{
3035 + struct lq_gpio *lq_gpio = kzalloc(sizeof(struct lq_gpio), GFP_KERNEL);
3036 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3037 + int ret = 0;
3038 + if(!res)
3039 + {
3040 + ret = -ENOENT;
3041 + goto err_free;
3042 + }
3043 + res = request_mem_region(res->start, resource_size(res),
3044 + dev_name(&pdev->dev));
3045 + if(!res)
3046 + {
3047 + ret = -EBUSY;
3048 + goto err_free;
3049 + }
3050 + lq_gpio->membase = ioremap_nocache(res->start, resource_size(res));
3051 + if(!lq_gpio->membase)
3052 + {
3053 + ret = -ENOMEM;
3054 + goto err_release_mem_region;
3055 + }
3056 + lq_gpio->chip.label = "lq_gpio";
3057 + lq_gpio->chip.direction_input = lq_gpio_direction_input;
3058 + lq_gpio->chip.direction_output = lq_gpio_direction_output;
3059 + lq_gpio->chip.get = lq_gpio_get;
3060 + lq_gpio->chip.set = lq_gpio_set;
3061 + lq_gpio->chip.request = lq_gpio_req;
3062 + lq_gpio->chip.base = PINS_PER_PORT * pdev->id;
3063 + lq_gpio->chip.ngpio = PINS_PER_PORT;
3064 + platform_set_drvdata(pdev, lq_gpio);
3065 + ret = gpiochip_add(&lq_gpio->chip);
3066 + if(!ret)
3067 + return 0;
3068 +
3069 + iounmap(lq_gpio->membase);
3070 +err_release_mem_region:
3071 + release_mem_region(res->start, resource_size(res));
3072 +err_free:
3073 + kfree(lq_gpio);
3074 + return ret;
3075 +}
3076 +
3077 +static struct platform_driver
3078 +lq_gpio_driver = {
3079 + .probe = lq_gpio_probe,
3080 + .driver = {
3081 + .name = "lq_gpio",
3082 + .owner = THIS_MODULE,
3083 + },
3084 +};
3085 +
3086 +int __init
3087 +lq_gpio_init(void)
3088 +{
3089 + int ret = platform_driver_register(&lq_gpio_driver);
3090 + if(ret)
3091 + printk(KERN_INFO "lq_gpio : Error registering platfom driver!");
3092 + return ret;
3093 +}
3094 +
3095 +postcore_initcall(lq_gpio_init);
3096 --- /dev/null
3097 +++ b/arch/mips/lantiq/xway/reset.c
3098 @@ -0,0 +1,53 @@
3099 +/*
3100 + * This program is free software; you can redistribute it and/or modify it
3101 + * under the terms of the GNU General Public License version 2 as published
3102 + * by the Free Software Foundation.
3103 + *
3104 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
3105 + */
3106 +
3107 +#include <linux/init.h>
3108 +#include <linux/io.h>
3109 +#include <linux/pm.h>
3110 +#include <asm/reboot.h>
3111 +
3112 +#include <xway.h>
3113 +
3114 +#define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
3115 +#define LQ_RCU_RST_ALL 0x40000000
3116 +
3117 +static void
3118 +lq_machine_restart(char *command)
3119 +{
3120 + printk(KERN_NOTICE "System restart\n");
3121 + local_irq_disable();
3122 + lq_w32(lq_r32(LQ_RCU_RST) | LQ_RCU_RST_ALL, LQ_RCU_RST);
3123 + for(;;);
3124 +}
3125 +
3126 +static void
3127 +lq_machine_halt(void)
3128 +{
3129 + printk(KERN_NOTICE "System halted.\n");
3130 + local_irq_disable();
3131 + for(;;);
3132 +}
3133 +
3134 +static void
3135 +lq_machine_power_off(void)
3136 +{
3137 + printk(KERN_NOTICE "Please turn off the power now.\n");
3138 + local_irq_disable();
3139 + for(;;);
3140 +}
3141 +
3142 +static int __init
3143 +mips_reboot_setup(void)
3144 +{
3145 + _machine_restart = lq_machine_restart;
3146 + _machine_halt = lq_machine_halt;
3147 + pm_power_off = lq_machine_power_off;
3148 + return 0;
3149 +}
3150 +
3151 +arch_initcall(mips_reboot_setup);
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