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fix asus deluxe serial console (broken by v4 support patch)
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-08-26 13:41:41.689634168 +0200
3 +++ linux.dev/Makefile 2005-08-26 13:44:34.233403528 +0200
4 @@ -17,9 +17,9 @@
5 FINDHPATH = $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
6
7 HOSTCC = gcc
8 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
9 +HOSTCFLAGS = -Wall -Wstrict-prototypes -Os -fomit-frame-pointer
10
11 -CROSS_COMPILE =
12 +CROSS_COMPILE=
13
14 #
15 # Include the make variables (CC, etc...)
16 @@ -91,8 +91,10 @@
17
18 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
19
20 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
21 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
22 -fno-strict-aliasing -fno-common
23 +
24 +
25 ifndef CONFIG_FRAME_POINTER
26 CFLAGS += -fomit-frame-pointer
27 endif
28 @@ -354,7 +356,7 @@
29 @rm -f .ver1
30
31 include/linux/version.h: ./Makefile
32 - @expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
33 + @-expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
34 (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
35 @echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
36 @echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
37 @@ -501,7 +503,7 @@
38 ifdef CONFIG_MODVERSIONS
39 $(MAKE) update-modverfile
40 endif
41 - scripts/mkdep -- `find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print` > .hdepend
42 + (find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print | xargs -r scripts/mkdep -- ) > .hdepend
43 scripts/mkdep -- init/*.c > .depend
44
45 ifdef CONFIG_MODVERSIONS
46 diff -urN linux.old/Rules.make linux.dev/Rules.make
47 --- linux.old/Rules.make 2004-02-18 14:36:30.000000000 +0100
48 +++ linux.dev/Rules.make 2005-08-26 13:44:34.252400640 +0200
49 @@ -176,7 +176,14 @@
50 _modinst__: dummy
51 ifneq "$(strip $(ALL_MOBJS))" ""
52 mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
53 - cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
54 + #@cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
55 + for f in $(ALL_MOBJS) ; do \
56 + $(OBJCOPY) -R __ksymtab -R .comment -R .note -x \
57 + `$(NM) $$f | cut -f3- -d' ' | sed -n \
58 + -e 's/__module_parm_\(.*\)/-K \1/p' \
59 + -e 's/__ks..tab_\(.*\)/-K \1/p'` \
60 + $$f $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)$$f; \
61 + done
62 endif
63
64 .PHONY: modules_install
65 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
66 --- linux.old/arch/mips/Makefile 2005-08-26 13:41:41.690634016 +0200
67 +++ linux.dev/arch/mips/Makefile 2005-08-26 13:44:34.253400488 +0200
68 @@ -46,10 +46,10 @@
69 GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
70 GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
71 GCCFLAGS += $(call check_gcc, -finline-limit=100000,)
72 -LINKFLAGS += -G 0 -static -n
73 -MODFLAGS += -mlong-calls
74 +LINKFLAGS += -G 0 -static -n -nostdlib
75 +MODFLAGS += -mlong-calls -fno-common
76
77 -ifdef CONFIG_DEBUG_INFO
78 +ifdef CONFIG_REMOTE_DEBUG
79 GCCFLAGS += -g
80 ifdef CONFIG_SB1XXX_CORELIS
81 GCCFLAGS += -mno-sched-prolog -fno-omit-frame-pointer
82 @@ -71,13 +71,13 @@
83 set_gccflags = $(shell \
84 while :; do \
85 cpu=$(1); isa=-$(2); \
86 - for gcc_opt in -march= -mcpu=; do \
87 + for gcc_opt in -march= -mtune=; do \
88 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
89 -xc /dev/null > /dev/null 2>&1 && \
90 break 2; \
91 done; \
92 cpu=$(3); isa=-$(4); \
93 - for gcc_opt in -march= -mcpu=; do \
94 + for gcc_opt in -march= -mtune=; do \
95 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
96 -xc /dev/null > /dev/null 2>&1 && \
97 break 2; \
98 @@ -92,7 +92,7 @@
99 fi; \
100 gas_abi=-Wa,-32; gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
101 while :; do \
102 - for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
103 + for gas_opt in -Wa,-march= -Wa,-mtune=; do \
104 $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
105 -o /dev/null -xassembler /dev/null > /dev/null 2>&1 && \
106 break 2; \
107 @@ -174,6 +174,7 @@
108 endif
109
110 AFLAGS += $(GCCFLAGS)
111 +ASFLAGS += $(GCCFLAGS)
112 CFLAGS += $(GCCFLAGS)
113
114 LD += -m $(ld-emul)
115 @@ -727,6 +728,19 @@
116 endif
117
118 #
119 +# Broadcom BCM947XX variants
120 +#
121 +ifdef CONFIG_BCM947XX
122 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
123 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
124 +LOADADDR := 0x80001000
125 +
126 +zImage: vmlinux
127 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
128 +export LOADADDR
129 +endif
130 +
131 +#
132 # Choosing incompatible machines durings configuration will result in
133 # error messages during linking. Select a default linkscript if
134 # none has been choosen above.
135 @@ -779,6 +793,7 @@
136 $(MAKE) -C arch/$(ARCH)/tools clean
137 $(MAKE) -C arch/mips/baget clean
138 $(MAKE) -C arch/mips/lasat clean
139 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
140
141 archmrproper:
142 @$(MAKEBOOT) mrproper
143 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
144 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
145 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-08-26 13:44:34.262399120 +0200
146 @@ -0,0 +1,15 @@
147 +#
148 +# Makefile for the BCM947xx specific kernel interface routines
149 +# under Linux.
150 +#
151 +
152 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
153 +
154 +O_TARGET := bcm947xx.o
155 +
156 +export-objs := nvram_linux.o setup.o
157 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
158 +obj-y += nvram.o nvram_linux.o
159 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
160 +
161 +include $(TOPDIR)/Rules.make
162 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
163 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
164 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-08-26 13:44:34.262399120 +0200
165 @@ -0,0 +1,33 @@
166 +#
167 +# Makefile for Broadcom BCM947XX boards
168 +#
169 +# Copyright 2001-2003, Broadcom Corporation
170 +# All Rights Reserved.
171 +#
172 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
173 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
174 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
175 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
176 +#
177 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
178 +#
179 +
180 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
181 +SYSTEM ?= $(TOPDIR)/vmlinux
182 +
183 +all: vmlinuz
184 +
185 +# Don't build dependencies, this may die if $(CC) isn't gcc
186 +dep:
187 +
188 +# Create a gzipped version named vmlinuz for compatibility
189 +vmlinuz: piggy
190 + gzip -c9 $< > $@
191 +
192 +piggy: $(SYSTEM)
193 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
194 +
195 +mrproper: clean
196 +
197 +clean:
198 + rm -f vmlinuz piggy
199 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
200 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
201 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-08-26 13:44:34.263398968 +0200
202 @@ -0,0 +1,15 @@
203 +#
204 +# Makefile for the BCM947xx specific kernel interface routines
205 +# under Linux.
206 +#
207 +
208 +.S.s:
209 + $(CPP) $(AFLAGS) $< -o $*.s
210 +.S.o:
211 + $(CC) $(AFLAGS) -c $< -o $*.o
212 +
213 +O_TARGET := brcm.o
214 +
215 +obj-y := int-handler.o irq.o
216 +
217 +include $(TOPDIR)/Rules.make
218 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
219 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
220 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-08-26 13:44:34.263398968 +0200
221 @@ -0,0 +1,51 @@
222 +/*
223 + * Generic interrupt handler for Broadcom MIPS boards
224 + *
225 + * Copyright 2004, Broadcom Corporation
226 + * All Rights Reserved.
227 + *
228 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
229 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
230 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
231 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
232 + *
233 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
234 + */
235 +
236 +#include <linux/config.h>
237 +
238 +#include <asm/asm.h>
239 +#include <asm/mipsregs.h>
240 +#include <asm/regdef.h>
241 +#include <asm/stackframe.h>
242 +
243 +/*
244 + * MIPS IRQ Source
245 + * -------- ------
246 + * 0 Software (ignored)
247 + * 1 Software (ignored)
248 + * 2 Combined hardware interrupt (hw0)
249 + * 3 Hardware
250 + * 4 Hardware
251 + * 5 Hardware
252 + * 6 Hardware
253 + * 7 R4k timer
254 + */
255 +
256 + .text
257 + .set noreorder
258 + .set noat
259 + .align 5
260 + NESTED(brcmIRQ, PT_SIZE, sp)
261 + SAVE_ALL
262 + CLI
263 + .set at
264 + .set noreorder
265 +
266 + jal brcm_irq_dispatch
267 + move a0, sp
268 +
269 + j ret_from_irq
270 + nop
271 +
272 + END(brcmIRQ)
273 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
274 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
275 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-08-26 13:44:34.263398968 +0200
276 @@ -0,0 +1,130 @@
277 +/*
278 + * Generic interrupt control functions for Broadcom MIPS boards
279 + *
280 + * Copyright 2004, Broadcom Corporation
281 + * All Rights Reserved.
282 + *
283 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
284 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
285 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
286 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
287 + *
288 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
289 + */
290 +
291 +#include <linux/config.h>
292 +#include <linux/init.h>
293 +#include <linux/kernel.h>
294 +#include <linux/types.h>
295 +#include <linux/interrupt.h>
296 +#include <linux/irq.h>
297 +
298 +#include <asm/irq.h>
299 +#include <asm/mipsregs.h>
300 +#include <asm/gdb-stub.h>
301 +
302 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
303 +
304 +extern asmlinkage void brcmIRQ(void);
305 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
306 +
307 +void
308 +brcm_irq_dispatch(struct pt_regs *regs)
309 +{
310 + u32 cause;
311 +
312 + cause = read_c0_cause() &
313 + read_c0_status() &
314 + CAUSEF_IP;
315 +
316 +#ifdef CONFIG_KERNPROF
317 + change_c0_status(cause | 1, 1);
318 +#else
319 + clear_c0_status(cause);
320 +#endif
321 +
322 + if (cause & CAUSEF_IP7)
323 + do_IRQ(7, regs);
324 + if (cause & CAUSEF_IP2)
325 + do_IRQ(2, regs);
326 + if (cause & CAUSEF_IP3)
327 + do_IRQ(3, regs);
328 + if (cause & CAUSEF_IP4)
329 + do_IRQ(4, regs);
330 + if (cause & CAUSEF_IP5)
331 + do_IRQ(5, regs);
332 + if (cause & CAUSEF_IP6)
333 + do_IRQ(6, regs);
334 +}
335 +
336 +static void
337 +enable_brcm_irq(unsigned int irq)
338 +{
339 + if (irq < 8)
340 + set_c0_status(1 << (irq + 8));
341 + else
342 + set_c0_status(IE_IRQ0);
343 +}
344 +
345 +static void
346 +disable_brcm_irq(unsigned int irq)
347 +{
348 + if (irq < 8)
349 + clear_c0_status(1 << (irq + 8));
350 + else
351 + clear_c0_status(IE_IRQ0);
352 +}
353 +
354 +static void
355 +ack_brcm_irq(unsigned int irq)
356 +{
357 + /* Already done in brcm_irq_dispatch */
358 +}
359 +
360 +static unsigned int
361 +startup_brcm_irq(unsigned int irq)
362 +{
363 + enable_brcm_irq(irq);
364 +
365 + return 0; /* never anything pending */
366 +}
367 +
368 +static void
369 +end_brcm_irq(unsigned int irq)
370 +{
371 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
372 + enable_brcm_irq(irq);
373 +}
374 +
375 +static struct hw_interrupt_type brcm_irq_type = {
376 + typename: "MIPS",
377 + startup: startup_brcm_irq,
378 + shutdown: disable_brcm_irq,
379 + enable: enable_brcm_irq,
380 + disable: disable_brcm_irq,
381 + ack: ack_brcm_irq,
382 + end: end_brcm_irq,
383 + NULL
384 +};
385 +
386 +void __init
387 +init_IRQ(void)
388 +{
389 + int i;
390 +
391 + for (i = 0; i < NR_IRQS; i++) {
392 + irq_desc[i].status = IRQ_DISABLED;
393 + irq_desc[i].action = 0;
394 + irq_desc[i].depth = 1;
395 + irq_desc[i].handler = &brcm_irq_type;
396 + }
397 +
398 + set_except_vector(0, brcmIRQ);
399 + change_c0_status(ST0_IM, ALLINTS);
400 +
401 +#ifdef CONFIG_REMOTE_DEBUG
402 + printk("Breaking into debugger...\n");
403 + set_debug_traps();
404 + breakpoint();
405 +#endif
406 +}
407 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
408 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
409 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-08-26 13:44:34.264398816 +0200
410 @@ -0,0 +1,158 @@
411 +/*
412 + * GPIO char driver
413 + *
414 + * Copyright 2004, Broadcom Corporation
415 + * All Rights Reserved.
416 + *
417 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
418 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
419 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
420 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
421 + *
422 + * $Id: gpio.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
423 + */
424 +
425 +#include <linux/module.h>
426 +#include <linux/init.h>
427 +#include <linux/fs.h>
428 +#include <linux/miscdevice.h>
429 +#include <asm/uaccess.h>
430 +
431 +#include <typedefs.h>
432 +#include <bcmutils.h>
433 +#include <sbutils.h>
434 +#include <bcmdevs.h>
435 +
436 +static void *gpio_sbh;
437 +static int gpio_major;
438 +static devfs_handle_t gpio_dir;
439 +static struct {
440 + char *name;
441 + devfs_handle_t handle;
442 +} gpio_file[] = {
443 + { "in", NULL },
444 + { "out", NULL },
445 + { "outen", NULL },
446 + { "control", NULL }
447 +};
448 +
449 +static int
450 +gpio_open(struct inode *inode, struct file * file)
451 +{
452 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
453 + return -ENODEV;
454 +
455 + MOD_INC_USE_COUNT;
456 + return 0;
457 +}
458 +
459 +static int
460 +gpio_release(struct inode *inode, struct file * file)
461 +{
462 + MOD_DEC_USE_COUNT;
463 + return 0;
464 +}
465 +
466 +static ssize_t
467 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
468 +{
469 + u32 val;
470 +
471 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
472 + case 0:
473 + val = sb_gpioin(gpio_sbh);
474 + break;
475 + case 1:
476 + val = sb_gpioout(gpio_sbh, 0, 0);
477 + break;
478 + case 2:
479 + val = sb_gpioouten(gpio_sbh, 0, 0);
480 + break;
481 + case 3:
482 + val = sb_gpiocontrol(gpio_sbh, 0, 0);
483 + break;
484 + default:
485 + return -ENODEV;
486 + }
487 +
488 + if (put_user(val, (u32 *) buf))
489 + return -EFAULT;
490 +
491 + return sizeof(val);
492 +}
493 +
494 +static ssize_t
495 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
496 +{
497 + u32 val;
498 +
499 + if (get_user(val, (u32 *) buf))
500 + return -EFAULT;
501 +
502 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
503 + case 0:
504 + return -EACCES;
505 + case 1:
506 + sb_gpioout(gpio_sbh, ~0, val);
507 + break;
508 + case 2:
509 + sb_gpioouten(gpio_sbh, ~0, val);
510 + break;
511 + case 3:
512 + sb_gpiocontrol(gpio_sbh, ~0, val);
513 + break;
514 + default:
515 + return -ENODEV;
516 + }
517 +
518 + return sizeof(val);
519 +}
520 +
521 +static struct file_operations gpio_fops = {
522 + owner: THIS_MODULE,
523 + open: gpio_open,
524 + release: gpio_release,
525 + read: gpio_read,
526 + write: gpio_write,
527 +};
528 +
529 +static int __init
530 +gpio_init(void)
531 +{
532 + int i;
533 +
534 + if (!(gpio_sbh = sb_kattach()))
535 + return -ENODEV;
536 +
537 + sb_gpiosetcore(gpio_sbh);
538 +
539 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
540 + return gpio_major;
541 +
542 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
543 +
544 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
545 + gpio_file[i].handle = devfs_register(gpio_dir,
546 + gpio_file[i].name,
547 + DEVFS_FL_DEFAULT, gpio_major, i,
548 + S_IFCHR | S_IRUGO | S_IWUGO,
549 + &gpio_fops, NULL);
550 + }
551 +
552 + return 0;
553 +}
554 +
555 +static void __exit
556 +gpio_exit(void)
557 +{
558 + int i;
559 +
560 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
561 + devfs_unregister(gpio_file[i].handle);
562 + devfs_unregister(gpio_dir);
563 + devfs_unregister_chrdev(gpio_major, "gpio");
564 + sb_detach(gpio_sbh);
565 +}
566 +
567 +module_init(gpio_init);
568 +module_exit(gpio_exit);
569 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
570 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
571 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-08-26 13:44:34.265398664 +0200
572 @@ -0,0 +1,369 @@
573 +/*
574 + * Broadcom device-specific manifest constants.
575 + *
576 + * Copyright 2005, Broadcom Corporation
577 + * All Rights Reserved.
578 + *
579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
583 + * $Id$
584 + */
585 +
586 +#ifndef _BCMDEVS_H
587 +#define _BCMDEVS_H
588 +
589 +
590 +/* Known PCI vendor Id's */
591 +#define VENDOR_EPIGRAM 0xfeda
592 +#define VENDOR_BROADCOM 0x14e4
593 +#define VENDOR_3COM 0x10b7
594 +#define VENDOR_NETGEAR 0x1385
595 +#define VENDOR_DIAMOND 0x1092
596 +#define VENDOR_DELL 0x1028
597 +#define VENDOR_HP 0x0e11
598 +#define VENDOR_APPLE 0x106b
599 +
600 +/* PCI Device Id's */
601 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
602 +#define BCM4211_DEVICE_ID 0x4211
603 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
604 +#define BCM4231_DEVICE_ID 0x4231
605 +
606 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
607 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
608 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
609 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
610 +
611 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
612 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
613 +
614 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
615 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
616 +
617 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
618 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
619 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
620 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
621 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
622 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
623 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
624 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
625 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
626 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
627 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
628 +
629 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
630 +
631 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
632 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
633 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
634 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
635 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
636 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
637 +
638 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
639 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
640 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
641 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
642 +
643 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
644 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
645 +
646 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
647 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
648 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
649 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
650 +
651 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
652 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
653 +#define BCM4306_D11G_ID2 0x4325
654 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
655 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
656 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
657 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
658 +
659 +#define BCM4309_PKG_ID 1 /* 4309 package id */
660 +
661 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
662 +#define BCM4303_PKG_ID 2 /* 4303 package id */
663 +
664 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
665 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
666 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
667 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
668 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
669 +
670 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
671 +
672 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
673 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
674 +
675 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
676 +
677 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
678 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
679 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
680 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
681 +
682 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
683 +
684 +/* Address map */
685 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
686 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
687 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
688 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
689 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
690 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
691 +
692 +/* Core register space */
693 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
694 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
695 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
696 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
697 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
698 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
699 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
700 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
701 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
702 +
703 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
704 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
705 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
706 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
707 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
708 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
709 +
710 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
711 +
712 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
713 +
714 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
715 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
716 +
717 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
718 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
719 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
720 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
721 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
722 +
723 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
724 +
725 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
726 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
727 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
728 +
729 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
730 +
731 +/* PCMCIA vendor Id's */
732 +
733 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
734 +
735 +/* SDIO vendor Id's */
736 +#define VENDOR_BROADCOM_SDIO 0x00BF
737 +
738 +
739 +/* boardflags */
740 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
741 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
742 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
743 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
744 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
745 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
746 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
747 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
748 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
749 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
750 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
751 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
752 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
753 +
754 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
755 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
756 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
757 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
758 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
759 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
760 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
761 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
762 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
763 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
764 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
765 +
766 +/* Bus types */
767 +#define SB_BUS 0 /* Silicon Backplane */
768 +#define PCI_BUS 1 /* PCI target */
769 +#define PCMCIA_BUS 2 /* PCMCIA target */
770 +#define SDIO_BUS 3 /* SDIO target */
771 +#define JTAG_BUS 4 /* JTAG */
772 +
773 +/* Allows optimization for single-bus support */
774 +#ifdef BCMBUSTYPE
775 +#define BUSTYPE(bus) (BCMBUSTYPE)
776 +#else
777 +#define BUSTYPE(bus) (bus)
778 +#endif
779 +
780 +/* power control defines */
781 +#define PLL_DELAY 150 /* 150us pll on delay */
782 +#define FREF_DELAY 200 /* 200us fref change delay */
783 +#define MIN_SLOW_CLK 32 /* 32us Slow clock period */
784 +
785 +/* Reference Board Types */
786 +
787 +#define BU4710_BOARD 0x0400
788 +#define VSIM4710_BOARD 0x0401
789 +#define QT4710_BOARD 0x0402
790 +
791 +#define BU4610_BOARD 0x0403
792 +#define VSIM4610_BOARD 0x0404
793 +
794 +#define BU4307_BOARD 0x0405
795 +#define BCM94301CB_BOARD 0x0406
796 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
797 +#define BCM94301MP_BOARD 0x0407
798 +#define BCM94307MP_BOARD 0x0408
799 +#define BCMAP4307_BOARD 0x0409
800 +
801 +#define BU4309_BOARD 0x040a
802 +#define BCM94309CB_BOARD 0x040b
803 +#define BCM94309MP_BOARD 0x040c
804 +#define BCM4309AP_BOARD 0x040d
805 +
806 +#define BCM94302MP_BOARD 0x040e
807 +
808 +#define VSIM4310_BOARD 0x040f
809 +#define BU4711_BOARD 0x0410
810 +#define BCM94310U_BOARD 0x0411
811 +#define BCM94310AP_BOARD 0x0412
812 +#define BCM94310MP_BOARD 0x0414
813 +
814 +#define BU4306_BOARD 0x0416
815 +#define BCM94306CB_BOARD 0x0417
816 +#define BCM94306MP_BOARD 0x0418
817 +
818 +#define BCM94710D_BOARD 0x041a
819 +#define BCM94710R1_BOARD 0x041b
820 +#define BCM94710R4_BOARD 0x041c
821 +#define BCM94710AP_BOARD 0x041d
822 +
823 +
824 +#define BU2050_BOARD 0x041f
825 +
826 +
827 +#define BCM94309G_BOARD 0x0421
828 +
829 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
830 +
831 +#define BU4704_BOARD 0x0423
832 +#define BU4702_BOARD 0x0424
833 +
834 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
835 +
836 +#define BU4317_BOARD 0x0426
837 +
838 +
839 +#define BCM94702MN_BOARD 0x0428
840 +
841 +/* BCM4702 1U CompactPCI Board */
842 +#define BCM94702CPCI_BOARD 0x0429
843 +
844 +/* BCM4702 with BCM95380 VLAN Router */
845 +#define BCM95380RR_BOARD 0x042a
846 +
847 +/* cb4306 with SiGe PA */
848 +#define BCM94306CBSG_BOARD 0x042b
849 +
850 +/* mp4301 with 2050 radio */
851 +#define BCM94301MPL_BOARD 0x042c
852 +
853 +/* cb4306 with SiGe PA */
854 +#define PCSG94306_BOARD 0x042d
855 +
856 +/* bu4704 with sdram */
857 +#define BU4704SD_BOARD 0x042e
858 +
859 +/* Dual 11a/11g Router */
860 +#define BCM94704AGR_BOARD 0x042f
861 +
862 +/* 11a-only minipci */
863 +#define BCM94308MP_BOARD 0x0430
864 +
865 +
866 +
867 +/* BCM94317 boards */
868 +#define BCM94317CB_BOARD 0x0440
869 +#define BCM94317MP_BOARD 0x0441
870 +#define BCM94317PCMCIA_BOARD 0x0442
871 +#define BCM94317SDIO_BOARD 0x0443
872 +
873 +#define BU4712_BOARD 0x0444
874 +#define BU4712SD_BOARD 0x045d
875 +#define BU4712L_BOARD 0x045f
876 +
877 +/* BCM4712 boards */
878 +#define BCM94712AP_BOARD 0x0445
879 +#define BCM94712P_BOARD 0x0446
880 +
881 +/* BCM4318 boards */
882 +#define BU4318_BOARD 0x0447
883 +#define CB4318_BOARD 0x0448
884 +#define MPG4318_BOARD 0x0449
885 +#define MP4318_BOARD 0x044a
886 +#define SD4318_BOARD 0x044b
887 +
888 +/* Another mp4306 with SiGe */
889 +#define BCM94306P_BOARD 0x044c
890 +
891 +/* CF-like 4317 modules */
892 +#define BCM94317CF_BOARD 0x044d
893 +
894 +/* mp4303 */
895 +#define BCM94303MP_BOARD 0x044e
896 +
897 +/* mpsgh4306 */
898 +#define BCM94306MPSGH_BOARD 0x044f
899 +
900 +/* BRCM 4306 w/ Front End Modules */
901 +#define BCM94306MPM 0x0450
902 +#define BCM94306MPL 0x0453
903 +
904 +/* 4712agr */
905 +#define BCM94712AGR_BOARD 0x0451
906 +
907 +/* The real CF 4317 board */
908 +#define CFI4317_BOARD 0x0452
909 +
910 +/* pcmcia 4303 */
911 +#define PC4303_BOARD 0x0454
912 +
913 +/* 5350K */
914 +#define BCM95350K_BOARD 0x0455
915 +
916 +/* 5350R */
917 +#define BCM95350R_BOARD 0x0456
918 +
919 +/* 4306mplna */
920 +#define BCM94306MPLNA_BOARD 0x0457
921 +
922 +
923 +/* 4306mph */
924 +#define BCM94306MPH_BOARD 0x045b
925 +
926 +/* 4306pciv */
927 +#define BCM94306PCIV_BOARD 0x045c
928 +
929 +#define BU4712SD_BOARD 0x045d
930 +
931 +
932 +#define BU4712L_BOARD 0x045f
933 +#define BCM94712LGR_BOARD 0x0460
934 +
935 +#define BU5352_BOARD 0x0462
936 +#define BCM95352GR_BOARD 0x0467
937 +
938 +/* # of GPIO pins */
939 +#define GPIO_NUMPINS 16
940 +
941 +#endif /* _BCMDEVS_H */
942 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
943 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
944 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-08-26 13:44:34.269398056 +0200
945 @@ -0,0 +1,168 @@
946 +/*
947 + * local version of endian.h - byte order defines
948 + *
949 + * Copyright 2005, Broadcom Corporation
950 + * All Rights Reserved.
951 + *
952 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
953 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
954 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
955 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
956 + *
957 + * $Id$
958 +*/
959 +
960 +#ifndef _BCMENDIAN_H_
961 +#define _BCMENDIAN_H_
962 +
963 +#include <typedefs.h>
964 +
965 +/* Byte swap a 16 bit value */
966 +#define BCMSWAP16(val) \
967 + ((uint16)( \
968 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
969 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
970 +
971 +/* Byte swap a 32 bit value */
972 +#define BCMSWAP32(val) \
973 + ((uint32)( \
974 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
975 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
976 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
977 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
978 +
979 +static INLINE uint16
980 +bcmswap16(uint16 val)
981 +{
982 + return BCMSWAP16(val);
983 +}
984 +
985 +static INLINE uint32
986 +bcmswap32(uint32 val)
987 +{
988 + return BCMSWAP32(val);
989 +}
990 +
991 +/* buf - start of buffer of shorts to swap */
992 +/* len - byte length of buffer */
993 +static INLINE void
994 +bcmswap16_buf(uint16 *buf, uint len)
995 +{
996 + len = len/2;
997 +
998 + while(len--){
999 + *buf = bcmswap16(*buf);
1000 + buf++;
1001 + }
1002 +}
1003 +
1004 +#ifndef hton16
1005 +#ifndef IL_BIGENDIAN
1006 +#define HTON16(i) BCMSWAP16(i)
1007 +#define hton16(i) bcmswap16(i)
1008 +#define hton32(i) bcmswap32(i)
1009 +#define ntoh16(i) bcmswap16(i)
1010 +#define ntoh32(i) bcmswap32(i)
1011 +#define ltoh16(i) (i)
1012 +#define ltoh32(i) (i)
1013 +#define htol16(i) (i)
1014 +#define htol32(i) (i)
1015 +#else
1016 +#define HTON16(i) (i)
1017 +#define hton16(i) (i)
1018 +#define hton32(i) (i)
1019 +#define ntoh16(i) (i)
1020 +#define ntoh32(i) (i)
1021 +#define ltoh16(i) bcmswap16(i)
1022 +#define ltoh32(i) bcmswap32(i)
1023 +#define htol16(i) bcmswap16(i)
1024 +#define htol32(i) bcmswap32(i)
1025 +#endif
1026 +#endif
1027 +
1028 +#ifndef IL_BIGENDIAN
1029 +#define ltoh16_buf(buf, i)
1030 +#define htol16_buf(buf, i)
1031 +#else
1032 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1033 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1034 +#endif
1035 +
1036 +/*
1037 +* load 16-bit value from unaligned little endian byte array.
1038 +*/
1039 +static INLINE uint16
1040 +ltoh16_ua(uint8 *bytes)
1041 +{
1042 + return (bytes[1]<<8)+bytes[0];
1043 +}
1044 +
1045 +/*
1046 +* load 32-bit value from unaligned little endian byte array.
1047 +*/
1048 +static INLINE uint32
1049 +ltoh32_ua(uint8 *bytes)
1050 +{
1051 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1052 +}
1053 +
1054 +/*
1055 +* load 16-bit value from unaligned big(network) endian byte array.
1056 +*/
1057 +static INLINE uint16
1058 +ntoh16_ua(uint8 *bytes)
1059 +{
1060 + return (bytes[0]<<8)+bytes[1];
1061 +}
1062 +
1063 +/*
1064 +* load 32-bit value from unaligned big(network) endian byte array.
1065 +*/
1066 +static INLINE uint32
1067 +ntoh32_ua(uint8 *bytes)
1068 +{
1069 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1070 +}
1071 +
1072 +/* get_ua adapted from Linux asm-mips/unaligned.h */
1073 +#ifdef IL_BIGENDIAN
1074 +#define get_ua(ptr) \
1075 +({ \
1076 + __typeof__(*(ptr)) __val; \
1077 + \
1078 + switch (sizeof(*(ptr))) { \
1079 + case 1: \
1080 + __val = *(uint8 *)ptr; \
1081 + break; \
1082 + case 2: \
1083 + __val = ntoh16_ua((uint8 *)ptr); \
1084 + break; \
1085 + case 4: \
1086 + __val = ntoh32_ua((uint8 *)ptr); \
1087 + break; \
1088 + } \
1089 + \
1090 + __val; \
1091 +})
1092 +#else
1093 +#define get_ua(ptr) \
1094 +({ \
1095 + __typeof__(*(ptr)) __val; \
1096 + \
1097 + switch (sizeof(*(ptr))) { \
1098 + case 1: \
1099 + __val = *(uint8 *)ptr; \
1100 + break; \
1101 + case 2: \
1102 + __val = ltoh16_ua((uint8 *)ptr); \
1103 + break; \
1104 + case 4: \
1105 + __val = ltoh32_ua((uint8 *)ptr); \
1106 + break; \
1107 + } \
1108 + \
1109 + __val; \
1110 +})
1111 +#endif
1112 +
1113 +#endif /* _BCMENDIAN_H_ */
1114 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
1115 --- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1116 +++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-08-26 13:44:34.270397904 +0200
1117 @@ -0,0 +1,229 @@
1118 +/*
1119 + * Hardware-specific definitions for
1120 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1121 + *
1122 + * Copyright 2005, Broadcom Corporation
1123 + * All Rights Reserved.
1124 + *
1125 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1126 + * the contents of this file may not be disclosed to third parties, copied
1127 + * or duplicated in any form, in whole or in part, without the prior
1128 + * written permission of Broadcom Corporation.
1129 + * $Id$
1130 + */
1131 +
1132 +#ifndef _bcmenet_47xx_h_
1133 +#define _bcmenet_47xx_h_
1134 +
1135 +#include <bcmenetmib.h>
1136 +#include <bcmenetrxh.h>
1137 +#include <bcmenetphy.h>
1138 +
1139 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1140 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1141 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1142 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1143 +
1144 +/* power management event wakeup pattern constants */
1145 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1146 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1147 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1148 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1149 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1150 +
1151 +/* cpp contortions to concatenate w/arg prescan */
1152 +#ifndef PAD
1153 +#define _PADLINE(line) pad ## line
1154 +#define _XSTR(line) _PADLINE(line)
1155 +#define PAD _XSTR(__LINE__)
1156 +#endif /* PAD */
1157 +
1158 +/*
1159 + * Host Interface Registers
1160 + */
1161 +typedef volatile struct _bcmenettregs {
1162 + /* Device and Power Control */
1163 + uint32 devcontrol;
1164 + uint32 PAD[2];
1165 + uint32 biststatus;
1166 + uint32 wakeuplength;
1167 + uint32 PAD[3];
1168 +
1169 + /* Interrupt Control */
1170 + uint32 intstatus;
1171 + uint32 intmask;
1172 + uint32 gptimer;
1173 + uint32 PAD[23];
1174 +
1175 + /* Ethernet MAC Address Filtering Control */
1176 + uint32 PAD[2];
1177 + uint32 enetftaddr;
1178 + uint32 enetftdata;
1179 + uint32 PAD[2];
1180 +
1181 + /* Ethernet MAC Control */
1182 + uint32 emactxmaxburstlen;
1183 + uint32 emacrxmaxburstlen;
1184 + uint32 emaccontrol;
1185 + uint32 emacflowcontrol;
1186 +
1187 + uint32 PAD[20];
1188 +
1189 + /* DMA Lazy Interrupt Control */
1190 + uint32 intrecvlazy;
1191 + uint32 PAD[63];
1192 +
1193 + /* DMA engine */
1194 + dmaregs_t dmaregs;
1195 + dmafifo_t dmafifo;
1196 + uint32 PAD[116];
1197 +
1198 + /* EMAC Registers */
1199 + uint32 rxconfig;
1200 + uint32 rxmaxlength;
1201 + uint32 txmaxlength;
1202 + uint32 PAD;
1203 + uint32 mdiocontrol;
1204 + uint32 mdiodata;
1205 + uint32 emacintmask;
1206 + uint32 emacintstatus;
1207 + uint32 camdatalo;
1208 + uint32 camdatahi;
1209 + uint32 camcontrol;
1210 + uint32 enetcontrol;
1211 + uint32 txcontrol;
1212 + uint32 txwatermark;
1213 + uint32 mibcontrol;
1214 + uint32 PAD[49];
1215 +
1216 + /* EMAC MIB counters */
1217 + bcmenetmib_t mib;
1218 +
1219 + uint32 PAD[585];
1220 +
1221 + /* Sonics SiliconBackplane config registers */
1222 + sbconfig_t sbconfig;
1223 +} bcmenetregs_t;
1224 +
1225 +/* device control */
1226 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1227 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1228 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1229 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1230 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1231 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1232 +#define DC_PA_SHIFT 18
1233 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1234 +#define DC_FS_SHIFT 23
1235 +#define DC_FS_4K 0 /* 4Kbytes */
1236 +#define DC_FS_512 1 /* 512bytes */
1237 +
1238 +/* wakeup length */
1239 +#define WL_P0_MASK 0x7f /* pattern 0 */
1240 +#define WL_D0 ((uint32)1 << 7)
1241 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1242 +#define WL_P1_SHIFT 8
1243 +#define WL_D1 ((uint32)1 << 15)
1244 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1245 +#define WL_P2_SHIFT 16
1246 +#define WL_D2 ((uint32)1 << 23)
1247 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1248 +#define WL_P3_SHIFT 24
1249 +#define WL_D3 ((uint32)1 << 31)
1250 +
1251 +/* intstatus and intmask */
1252 +#define I_PME ((uint32)1 << 6) /* power management event */
1253 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1254 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1255 +#define I_PD ((uint32)1 << 11) /* data error */
1256 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1257 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1258 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1259 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1260 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1261 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1262 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1263 +#define I_MW ((uint32)1 << 27) /* mii write */
1264 +#define I_MR ((uint32)1 << 28) /* mii read */
1265 +
1266 +/* emaccontrol */
1267 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1268 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1269 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1270 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1271 +#define EMC_LC_SHIFT 5
1272 +
1273 +/* emacflowcontrol */
1274 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1275 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1276 +
1277 +/* interrupt receive lazy */
1278 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1279 +#define IRL_FC_MASK 0xff000000 /* frame count */
1280 +#define IRL_FC_SHIFT 24 /* frame count */
1281 +
1282 +/* emac receive config */
1283 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1284 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1285 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1286 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1287 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1288 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1289 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1290 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1291 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1292 +
1293 +/* emac mdio control */
1294 +#define MC_MF_MASK 0x7f /* mdc frequency */
1295 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1296 +
1297 +/* emac mdio data */
1298 +#define MD_DATA_MASK 0xffff /* r/w data */
1299 +#define MD_TA_MASK 0x30000 /* turnaround value */
1300 +#define MD_TA_SHIFT 16
1301 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1302 +#define MD_RA_MASK 0x7c0000 /* register address */
1303 +#define MD_RA_SHIFT 18
1304 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1305 +#define MD_PMD_SHIFT 23
1306 +#define MD_OP_MASK 0x30000000 /* opcode */
1307 +#define MD_OP_SHIFT 28
1308 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1309 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1310 +#define MD_SB_MASK 0xc0000000 /* start bits */
1311 +#define MD_SB_SHIFT 30
1312 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1313 +
1314 +/* emac intstatus and intmask */
1315 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1316 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1317 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1318 +
1319 +/* emac cam data high */
1320 +#define CD_V ((uint32)1 << 16) /* valid bit */
1321 +
1322 +/* emac cam control */
1323 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1324 +#define CC_MS ((uint32)1 << 1) /* mask select */
1325 +#define CC_RD ((uint32)1 << 2) /* read */
1326 +#define CC_WR ((uint32)1 << 3) /* write */
1327 +#define CC_INDEX_MASK 0x3f0000 /* index */
1328 +#define CC_INDEX_SHIFT 16
1329 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1330 +
1331 +/* emac ethernet control */
1332 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1333 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1334 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1335 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1336 +
1337 +/* emac transmit control */
1338 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1339 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1340 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1341 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1342 +
1343 +/* emac mib control */
1344 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1345 +
1346 +#endif /* _bcmenet_47xx_h_ */
1347 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
1348 --- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1349 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-08-26 13:44:34.278396688 +0200
1350 @@ -0,0 +1,81 @@
1351 +/*
1352 + * Hardware-specific MIB definition for
1353 + * Broadcom Home Networking Division
1354 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1355 + *
1356 + * Copyright 2005, Broadcom Corporation
1357 + * All Rights Reserved.
1358 + *
1359 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1360 + * the contents of this file may not be disclosed to third parties, copied
1361 + * or duplicated in any form, in whole or in part, without the prior
1362 + * written permission of Broadcom Corporation.
1363 + * $Id$
1364 + */
1365 +
1366 +#ifndef _bcmenetmib_h_
1367 +#define _bcmenetmib_h_
1368 +
1369 +/* cpp contortions to concatenate w/arg prescan */
1370 +#ifndef PAD
1371 +#define _PADLINE(line) pad ## line
1372 +#define _XSTR(line) _PADLINE(line)
1373 +#define PAD _XSTR(__LINE__)
1374 +#endif /* PAD */
1375 +
1376 +/*
1377 + * EMAC MIB Registers
1378 + */
1379 +typedef volatile struct {
1380 + uint32 tx_good_octets;
1381 + uint32 tx_good_pkts;
1382 + uint32 tx_octets;
1383 + uint32 tx_pkts;
1384 + uint32 tx_broadcast_pkts;
1385 + uint32 tx_multicast_pkts;
1386 + uint32 tx_len_64;
1387 + uint32 tx_len_65_to_127;
1388 + uint32 tx_len_128_to_255;
1389 + uint32 tx_len_256_to_511;
1390 + uint32 tx_len_512_to_1023;
1391 + uint32 tx_len_1024_to_max;
1392 + uint32 tx_jabber_pkts;
1393 + uint32 tx_oversize_pkts;
1394 + uint32 tx_fragment_pkts;
1395 + uint32 tx_underruns;
1396 + uint32 tx_total_cols;
1397 + uint32 tx_single_cols;
1398 + uint32 tx_multiple_cols;
1399 + uint32 tx_excessive_cols;
1400 + uint32 tx_late_cols;
1401 + uint32 tx_defered;
1402 + uint32 tx_carrier_lost;
1403 + uint32 tx_pause_pkts;
1404 + uint32 PAD[8];
1405 +
1406 + uint32 rx_good_octets;
1407 + uint32 rx_good_pkts;
1408 + uint32 rx_octets;
1409 + uint32 rx_pkts;
1410 + uint32 rx_broadcast_pkts;
1411 + uint32 rx_multicast_pkts;
1412 + uint32 rx_len_64;
1413 + uint32 rx_len_65_to_127;
1414 + uint32 rx_len_128_to_255;
1415 + uint32 rx_len_256_to_511;
1416 + uint32 rx_len_512_to_1023;
1417 + uint32 rx_len_1024_to_max;
1418 + uint32 rx_jabber_pkts;
1419 + uint32 rx_oversize_pkts;
1420 + uint32 rx_fragment_pkts;
1421 + uint32 rx_missed_pkts;
1422 + uint32 rx_crc_align_errs;
1423 + uint32 rx_undersize;
1424 + uint32 rx_crc_errs;
1425 + uint32 rx_align_errs;
1426 + uint32 rx_symbol_errs;
1427 + uint32 rx_pause_pkts;
1428 + uint32 rx_nonpause_pkts;
1429 +} bcmenetmib_t;
1430 +
1431 +#endif /* _bcmenetmib_h_ */
1432 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
1433 --- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1434 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-08-26 13:44:34.278396688 +0200
1435 @@ -0,0 +1,58 @@
1436 +/*
1437 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1438 + *
1439 + * Copyright 2005, Broadcom Corporation
1440 + * All Rights Reserved.
1441 + *
1442 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1443 + * the contents of this file may not be disclosed to third parties, copied
1444 + * or duplicated in any form, in whole or in part, without the prior
1445 + * written permission of Broadcom Corporation.
1446 + * $Id$
1447 + */
1448 +
1449 +#ifndef _bcmenetphy_h_
1450 +#define _bcmenetphy_h_
1451 +
1452 +/* phy address */
1453 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1454 +#define EPHY_MASK 0x1f
1455 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1456 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1457 +
1458 +/* just a few phy registers */
1459 +#define CTL_RESET (1 << 15) /* reset */
1460 +#define CTL_LOOP (1 << 14) /* loopback */
1461 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1462 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1463 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1464 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1465 +
1466 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1467 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1468 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1469 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1470 +
1471 +/* link partner ability register */
1472 +#define LPA_SLCT 0x001f /* same as advertise selector */
1473 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1474 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1475 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1476 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1477 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1478 +#define LPA_RESV 0x1c00 /* unused */
1479 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1480 +#define LPA_LPACK 0x4000 /* link partner acked us */
1481 +#define LPA_NPAGE 0x8000 /* next page bit */
1482 +
1483 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1484 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1485 +
1486 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1487 +#define STAT_LINK (1 << 2) /* link status */
1488 +#define STAT_JAB (1 << 1) /* jabber detected */
1489 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1490 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1491 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1492 +
1493 +#endif /* _bcmenetphy_h_ */
1494 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
1495 --- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1496 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-08-26 13:44:34.278396688 +0200
1497 @@ -0,0 +1,43 @@
1498 +/*
1499 + * Hardware-specific Receive Data Header for the
1500 + * Broadcom Home Networking Division
1501 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1502 + *
1503 + * Copyright 2005, Broadcom Corporation
1504 + * All Rights Reserved.
1505 + *
1506 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1507 + * the contents of this file may not be disclosed to third parties, copied
1508 + * or duplicated in any form, in whole or in part, without the prior
1509 + * written permission of Broadcom Corporation.
1510 + * $Id$
1511 + */
1512 +
1513 +#ifndef _bcmenetrxh_h_
1514 +#define _bcmenetrxh_h_
1515 +
1516 +/*
1517 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1518 + * with every frame consisting of
1519 + * 16bits of frame length, followed by
1520 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1521 + */
1522 +typedef volatile struct {
1523 + uint16 len;
1524 + uint16 flags;
1525 + uint16 pad[12];
1526 +} bcmenetrxh_t;
1527 +
1528 +#define RXHDR_LEN 28
1529 +
1530 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1531 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1532 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1533 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1534 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1535 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1536 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1537 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1538 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1539 +
1540 +#endif /* _bcmenetrxh_h_ */
1541 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1542 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1543 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-08-26 13:44:34.279396536 +0200
1544 @@ -0,0 +1,132 @@
1545 +/*
1546 + * NVRAM variable manipulation
1547 + *
1548 + * Copyright 2005, Broadcom Corporation
1549 + * All Rights Reserved.
1550 + *
1551 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1552 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1553 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1554 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1555 + *
1556 + * $Id$
1557 + */
1558 +
1559 +#ifndef _bcmnvram_h_
1560 +#define _bcmnvram_h_
1561 +
1562 +#ifndef _LANGUAGE_ASSEMBLY
1563 +
1564 +#include <typedefs.h>
1565 +
1566 +struct nvram_header {
1567 + uint32 magic;
1568 + uint32 len;
1569 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
1570 + uint32 config_refresh; /* 0:15 config, 16:31 refresh */
1571 + uint32 config_ncdl; /* ncdl values for memc */
1572 +};
1573 +
1574 +struct nvram_tuple {
1575 + char *name;
1576 + char *value;
1577 + struct nvram_tuple *next;
1578 +};
1579 +
1580 +/*
1581 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1582 + * platforms.
1583 + */
1584 +extern int BCMINIT(nvram_init)(void *sbh);
1585 +
1586 +/*
1587 + * Disable NVRAM access. May be unnecessary or undefined on certain
1588 + * platforms.
1589 + */
1590 +extern void BCMINIT(nvram_exit)(void);
1591 +
1592 +/*
1593 + * Get the value of an NVRAM variable. The pointer returned may be
1594 + * invalid after a set.
1595 + * @param name name of variable to get
1596 + * @return value of variable or NULL if undefined
1597 + */
1598 +extern char * BCMINIT(nvram_get)(const char *name);
1599 +
1600 +/*
1601 + * Get the value of an NVRAM variable.
1602 + * @param name name of variable to get
1603 + * @return value of variable or NUL if undefined
1604 + */
1605 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1606 +
1607 +/*
1608 + * Match an NVRAM variable.
1609 + * @param name name of variable to match
1610 + * @param match value to compare against value of variable
1611 + * @return TRUE if variable is defined and its value is string equal
1612 + * to match or FALSE otherwise
1613 + */
1614 +static INLINE int
1615 +nvram_match(char *name, char *match) {
1616 + const char *value = BCMINIT(nvram_get)(name);
1617 + return (value && !strcmp(value, match));
1618 +}
1619 +
1620 +/*
1621 + * Inversely match an NVRAM variable.
1622 + * @param name name of variable to match
1623 + * @param match value to compare against value of variable
1624 + * @return TRUE if variable is defined and its value is not string
1625 + * equal to invmatch or FALSE otherwise
1626 + */
1627 +static INLINE int
1628 +nvram_invmatch(char *name, char *invmatch) {
1629 + const char *value = BCMINIT(nvram_get)(name);
1630 + return (value && strcmp(value, invmatch));
1631 +}
1632 +
1633 +/*
1634 + * Set the value of an NVRAM variable. The name and value strings are
1635 + * copied into private storage. Pointers to previously set values
1636 + * may become invalid. The new value may be immediately
1637 + * retrieved but will not be permanently stored until a commit.
1638 + * @param name name of variable to set
1639 + * @param value value of variable
1640 + * @return 0 on success and errno on failure
1641 + */
1642 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1643 +
1644 +/*
1645 + * Unset an NVRAM variable. Pointers to previously set values
1646 + * remain valid until a set.
1647 + * @param name name of variable to unset
1648 + * @return 0 on success and errno on failure
1649 + * NOTE: use nvram_commit to commit this change to flash.
1650 + */
1651 +extern int BCMINIT(nvram_unset)(const char *name);
1652 +
1653 +/*
1654 + * Commit NVRAM variables to permanent storage. All pointers to values
1655 + * may be invalid after a commit.
1656 + * NVRAM values are undefined after a commit.
1657 + * @return 0 on success and errno on failure
1658 + */
1659 +extern int BCMINIT(nvram_commit)(void);
1660 +
1661 +/*
1662 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1663 + * @param buf buffer to store variables
1664 + * @param count size of buffer in bytes
1665 + * @return 0 on success and errno on failure
1666 + */
1667 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1668 +
1669 +#endif /* _LANGUAGE_ASSEMBLY */
1670 +
1671 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1672 +#define NVRAM_VERSION 1
1673 +#define NVRAM_HEADER_SIZE 20
1674 +#define NVRAM_SPACE 0x8000
1675 +
1676 +#endif /* _bcmnvram_h_ */
1677 diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
1678 --- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1679 +++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-08-26 13:44:34.279396536 +0200
1680 @@ -0,0 +1,23 @@
1681 +/*
1682 + * Misc system wide parameters.
1683 + *
1684 + * Copyright 2005, Broadcom Corporation
1685 + * All Rights Reserved.
1686 + *
1687 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1688 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1689 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1690 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1691 + * $Id$
1692 + */
1693 +
1694 +#ifndef _bcmparams_h_
1695 +#define _bcmparams_h_
1696 +
1697 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1698 +
1699 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1700 +
1701 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1702 +
1703 +#endif
1704 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1705 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1706 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-08-26 13:44:34.280396384 +0200
1707 @@ -0,0 +1,22 @@
1708 +/*
1709 + * Misc useful routines to access NIC local SROM/OTP .
1710 + *
1711 + * Copyright 2005, Broadcom Corporation
1712 + * All Rights Reserved.
1713 + *
1714 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1715 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1716 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1717 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1718 + *
1719 + * $Id$
1720 + */
1721 +
1722 +#ifndef _bcmsrom_h_
1723 +#define _bcmsrom_h_
1724 +
1725 +extern int srom_var_init(void *sbh, uint bus, void *curmap, void *osh, char **vars, int *count);
1726 +extern int srom_read(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1727 +extern int srom_write(uint bus, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf);
1728 +
1729 +#endif /* _bcmsrom_h_ */
1730 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1731 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1732 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-08-26 13:44:34.280396384 +0200
1733 @@ -0,0 +1,239 @@
1734 +/*
1735 + * Misc useful os-independent macros and functions.
1736 + *
1737 + * Copyright 2005, Broadcom Corporation
1738 + * All Rights Reserved.
1739 + *
1740 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1741 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1742 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1743 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1744 + * $Id$
1745 + */
1746 +
1747 +#ifndef _bcmutils_h_
1748 +#define _bcmutils_h_
1749 +
1750 +/*** driver-only section ***/
1751 +#ifdef BCMDRIVER
1752 +#include <osl.h>
1753 +
1754 +#define _BCM_U 0x01 /* upper */
1755 +#define _BCM_L 0x02 /* lower */
1756 +#define _BCM_D 0x04 /* digit */
1757 +#define _BCM_C 0x08 /* cntrl */
1758 +#define _BCM_P 0x10 /* punct */
1759 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1760 +#define _BCM_X 0x40 /* hex digit */
1761 +#define _BCM_SP 0x80 /* hard space (0x20) */
1762 +
1763 +extern unsigned char bcm_ctype[];
1764 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1765 +
1766 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1767 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1768 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1769 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1770 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1771 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1772 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1773 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1774 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1775 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1776 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1777 +
1778 +/*
1779 + * Spin at most 'us' microseconds while 'exp' is true.
1780 + * Caller should explicitly test 'exp' when this completes
1781 + * and take appropriate error action if 'exp' is still true.
1782 + */
1783 +#define SPINWAIT(exp, us) { \
1784 + uint countdown = (us) + 9; \
1785 + while ((exp) && (countdown >= 10)) {\
1786 + OSL_DELAY(10); \
1787 + countdown -= 10; \
1788 + } \
1789 +}
1790 +
1791 +/* generic osl packet queue */
1792 +struct pktq {
1793 + void *head; /* first packet to dequeue */
1794 + void *tail; /* last packet to dequeue */
1795 + uint len; /* number of queued packets */
1796 + uint maxlen; /* maximum number of queued packets */
1797 + bool priority; /* enqueue by packet priority */
1798 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1799 +};
1800 +#define DEFAULT_QLEN 128
1801 +
1802 +#define pktq_len(q) ((q)->len)
1803 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1804 +#define pktq_head(q) ((q)->head)
1805 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1806 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1807 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1808 +
1809 +/* externs */
1810 +/* packet */
1811 +extern uint pktcopy(void *drv, void *p, uint offset, int len, uchar *buf);
1812 +extern uint pkttotlen(void *drv, void *);
1813 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1814 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1815 +extern void *pktdeq(struct pktq *q);
1816 +extern void *pktdeqtail(struct pktq *q);
1817 +/* string */
1818 +extern uint bcm_atoi(char *s);
1819 +extern uchar bcm_toupper(uchar c);
1820 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1821 +extern char *bcmstrstr(char *haystack, char *needle);
1822 +extern char *bcmstrcat(char *dest, const char *src);
1823 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1824 +/* ethernet address */
1825 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1826 +extern int bcm_ether_atoe(char *p, char *ea);
1827 +/* delay */
1828 +extern void bcm_mdelay(uint ms);
1829 +/* variable access */
1830 +extern char *getvar(char *vars, char *name);
1831 +extern int getintvar(char *vars, char *name);
1832 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1833 +#define bcmlog(fmt, a1, a2)
1834 +#define bcmdumplog(buf, size) *buf = '\0'
1835 +#define bcmdumplogent(buf, idx) -1
1836 +#endif /* #ifdef BCMDRIVER */
1837 +
1838 +/*** driver/apps-shared section ***/
1839 +#ifndef MIN
1840 +#define MIN(a, b) (((a)<(b))?(a):(b))
1841 +#endif
1842 +
1843 +#ifndef MAX
1844 +#define MAX(a, b) (((a)>(b))?(a):(b))
1845 +#endif
1846 +
1847 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1848 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1849 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1850 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1851 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1852 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1853 +
1854 +/* bit map related macros */
1855 +#ifndef setbit
1856 +#define NBBY 8 /* 8 bits per byte */
1857 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1858 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1859 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1860 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1861 +#endif
1862 +
1863 +#define NBITS(type) (sizeof (type) * 8)
1864 +
1865 +/* crc defines */
1866 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1867 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1868 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1869 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1870 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1871 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1872 +
1873 +/* bcm_format_flags() bit description structure */
1874 +typedef struct bcm_bit_desc {
1875 + uint32 bit;
1876 + char* name;
1877 +} bcm_bit_desc_t;
1878 +
1879 +/* tag_ID/length/value_buffer tuple */
1880 +typedef struct bcm_tlv {
1881 + uint8 id;
1882 + uint8 len;
1883 + uint8 data[1];
1884 +} bcm_tlv_t;
1885 +
1886 +/* Check that bcm_tlv_t fits into the given buflen */
1887 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (buflen) >= 2 + (elt)->len)
1888 +
1889 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1890 +#define ETHER_ADDR_STR_LEN 18
1891 +
1892 +/* unaligned load and store macros */
1893 +#ifdef IL_BIGENDIAN
1894 +static INLINE uint32
1895 +load32_ua(uint8 *a)
1896 +{
1897 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1898 +}
1899 +
1900 +static INLINE void
1901 +store32_ua(uint8 *a, uint32 v)
1902 +{
1903 + a[0] = (v >> 24) & 0xff;
1904 + a[1] = (v >> 16) & 0xff;
1905 + a[2] = (v >> 8) & 0xff;
1906 + a[3] = v & 0xff;
1907 +}
1908 +
1909 +static INLINE uint16
1910 +load16_ua(uint8 *a)
1911 +{
1912 + return ((a[0] << 8) | a[1]);
1913 +}
1914 +
1915 +static INLINE void
1916 +store16_ua(uint8 *a, uint16 v)
1917 +{
1918 + a[0] = (v >> 8) & 0xff;
1919 + a[1] = v & 0xff;
1920 +}
1921 +
1922 +#else
1923 +
1924 +static INLINE uint32
1925 +load32_ua(uint8 *a)
1926 +{
1927 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
1928 +}
1929 +
1930 +static INLINE void
1931 +store32_ua(uint8 *a, uint32 v)
1932 +{
1933 + a[3] = (v >> 24) & 0xff;
1934 + a[2] = (v >> 16) & 0xff;
1935 + a[1] = (v >> 8) & 0xff;
1936 + a[0] = v & 0xff;
1937 +}
1938 +
1939 +static INLINE uint16
1940 +load16_ua(uint8 *a)
1941 +{
1942 + return ((a[1] << 8) | a[0]);
1943 +}
1944 +
1945 +static INLINE void
1946 +store16_ua(uint8 *a, uint16 v)
1947 +{
1948 + a[1] = (v >> 8) & 0xff;
1949 + a[0] = v & 0xff;
1950 +}
1951 +
1952 +#endif
1953 +
1954 +/* externs */
1955 +/* crc */
1956 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
1957 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
1958 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
1959 +/* format/print */
1960 +/* IE parsing */
1961 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
1962 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
1963 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
1964 +
1965 +/* multi-bool data type: set of bools, mbool is true if any is set */
1966 +typedef uint32 mbool;
1967 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
1968 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
1969 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
1970 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
1971 +
1972 +#endif /* _bcmutils_h_ */
1973 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
1974 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
1975 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-08-26 13:44:34.281396232 +0200
1976 @@ -0,0 +1,85 @@
1977 +/*
1978 + * bit manipulation utility functions
1979 + *
1980 + * Copyright 2005, Broadcom Corporation
1981 + * All Rights Reserved.
1982 + *
1983 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1984 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1985 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1986 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1987 + * $Id$
1988 + */
1989 +
1990 +#ifndef _BITFUNCS_H
1991 +#define _BITFUNCS_H
1992 +
1993 +#include <typedefs.h>
1994 +
1995 +/* local prototypes */
1996 +static INLINE uint32 find_msbit(uint32 x);
1997 +
1998 +
1999 +/*
2000 + * find_msbit: returns index of most significant set bit in x, with index
2001 + * range defined as 0-31. NOTE: returns zero if input is zero.
2002 + */
2003 +
2004 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2005 +
2006 +/*
2007 + * Implementation for Pentium processors and gcc. Note that this
2008 + * instruction is actually very slow on some processors (e.g., family 5,
2009 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2010 + * implementation instead.
2011 + */
2012 +static INLINE uint32 find_msbit(uint32 x)
2013 +{
2014 + uint msbit;
2015 + __asm__("bsrl %1,%0"
2016 + :"=r" (msbit)
2017 + :"r" (x));
2018 + return msbit;
2019 +}
2020 +
2021 +#else
2022 +
2023 +/*
2024 + * Generic Implementation
2025 + */
2026 +
2027 +#define DB_POW_MASK16 0xffff0000
2028 +#define DB_POW_MASK8 0x0000ff00
2029 +#define DB_POW_MASK4 0x000000f0
2030 +#define DB_POW_MASK2 0x0000000c
2031 +#define DB_POW_MASK1 0x00000002
2032 +
2033 +static INLINE uint32 find_msbit(uint32 x)
2034 +{
2035 + uint32 temp_x = x;
2036 + uint msbit = 0;
2037 + if (temp_x & DB_POW_MASK16) {
2038 + temp_x >>= 16;
2039 + msbit = 16;
2040 + }
2041 + if (temp_x & DB_POW_MASK8) {
2042 + temp_x >>= 8;
2043 + msbit += 8;
2044 + }
2045 + if (temp_x & DB_POW_MASK4) {
2046 + temp_x >>= 4;
2047 + msbit += 4;
2048 + }
2049 + if (temp_x & DB_POW_MASK2) {
2050 + temp_x >>= 2;
2051 + msbit += 2;
2052 + }
2053 + if (temp_x & DB_POW_MASK1) {
2054 + msbit += 1;
2055 + }
2056 + return(msbit);
2057 +}
2058 +
2059 +#endif
2060 +
2061 +#endif /* _BITFUNCS_H */
2062 diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
2063 --- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2064 +++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-08-26 13:44:34.281396232 +0200
2065 @@ -0,0 +1,184 @@
2066 +/*
2067 + * CFE boot loader OS Abstraction Layer.
2068 + *
2069 + * Copyright 2005, Broadcom Corporation
2070 + * All Rights Reserved.
2071 + *
2072 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2073 + * the contents of this file may not be disclosed to third parties, copied
2074 + * or duplicated in any form, in whole or in part, without the prior
2075 + * written permission of Broadcom Corporation.
2076 + *
2077 + * $Id$
2078 + */
2079 +
2080 +#ifndef _cfe_osl_h_
2081 +#define _cfe_osl_h_
2082 +
2083 +#include <lib_types.h>
2084 +#include <lib_string.h>
2085 +#include <lib_printf.h>
2086 +#include <lib_malloc.h>
2087 +#include <cpu_config.h>
2088 +#include <cfe_timer.h>
2089 +#include <cfe_iocb.h>
2090 +#include <cfe_devfuncs.h>
2091 +#include <addrspace.h>
2092 +
2093 +#include <typedefs.h>
2094 +
2095 +/* dump string */
2096 +extern int (*xprinthook)(const char *str);
2097 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2098 +
2099 +/* assert and panic */
2100 +#define ASSERT(exp) do {} while (0)
2101 +
2102 +/* PCMCIA attribute space access macros */
2103 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2104 + bzero(buf, size)
2105 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2106 + do {} while (0)
2107 +
2108 +/* PCI configuration space access macros */
2109 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2110 + (offset == 8 ? 0 : 0xffffffff)
2111 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2112 + do {} while (0)
2113 +
2114 +/* register access macros */
2115 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2116 +#define rreg32(r) (*(volatile uint32*)(r))
2117 +#ifdef IL_BIGENDIAN
2118 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2119 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2120 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2121 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2122 +#else
2123 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2124 +#define rreg16(r) (*(volatile uint16*)(r))
2125 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2126 +#define rreg8(r) (*(volatile uint8*)(r))
2127 +#endif
2128 +#define R_REG(r) ({ \
2129 + __typeof(*(r)) __osl_v; \
2130 + switch (sizeof(*(r))) { \
2131 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2132 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2133 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2134 + } \
2135 + __osl_v; \
2136 +})
2137 +#define W_REG(r, v) do { \
2138 + switch (sizeof(*(r))) { \
2139 + case sizeof(uint8): wreg8((r), (v)); break; \
2140 + case sizeof(uint16): wreg16((r), (v)); break; \
2141 + case sizeof(uint32): wreg32((r), (v)); break; \
2142 + } \
2143 +} while (0)
2144 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2145 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2146 +
2147 +/* bcopy, bcmp, and bzero */
2148 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2149 +
2150 +#define osl_attach(pdev) (pdev)
2151 +#define osl_detach(osh)
2152 +
2153 +/* general purpose memory allocation */
2154 +#define MALLOC(osh, size) KMALLOC((size),0)
2155 +#define MFREE(osh, addr, size) KFREE((addr))
2156 +#define MALLOCED(osh) (0)
2157 +#define MALLOC_DUMP(osh, buf, sz)
2158 +#define MALLOC_FAILED(osh) (0)
2159 +
2160 +/* uncached virtual address */
2161 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2162 +
2163 +/* host/bus architecture-specific address byte swap */
2164 +#define BUS_SWAP32(v) (v)
2165 +
2166 +/* get processor cycle count */
2167 +#define OSL_GETCYCLES(x) ((x) = 0)
2168 +
2169 +/* microsecond delay */
2170 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2171 +
2172 +/* map/unmap physical to virtual I/O */
2173 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2174 +#define REG_UNMAP(va) do {} while (0)
2175 +
2176 +/* dereference an address that may cause a bus exception */
2177 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2178 +extern int osl_busprobe(uint32 *val, uint32 addr);
2179 +
2180 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2181 +#define DMA_CONSISTENT_ALIGN 4096
2182 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2183 + osl_dma_alloc_consistent((size), (pap))
2184 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2185 + osl_dma_free_consistent((void*)(va))
2186 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2187 +extern void osl_dma_free_consistent(void *va);
2188 +
2189 +/* map/unmap direction */
2190 +#define DMA_TX 1
2191 +#define DMA_RX 2
2192 +
2193 +/* map/unmap shared (dma-able) memory */
2194 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2195 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2196 + PHYSADDR((ulong)(va)); \
2197 +})
2198 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2199 + do {} while (0)
2200 +
2201 +/* shared (dma-able) memory access macros */
2202 +#define R_SM(r) *(r)
2203 +#define W_SM(r, v) (*(r) = (v))
2204 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2205 +
2206 +/* generic packet structure */
2207 +#define LBUFSZ 4096
2208 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2209 +struct lbuf {
2210 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2211 + struct lbuf *link; /* pointer to next lbuf if in a list */
2212 + uchar *head; /* start of buffer */
2213 + uchar *end; /* end of buffer */
2214 + uchar *data; /* start of data */
2215 + uchar *tail; /* end of data */
2216 + uint len; /* nbytes of data */
2217 + void *cookie; /* generic cookie */
2218 +};
2219 +
2220 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2221 +#define PKTBUFSZ 2048
2222 +
2223 +/* packet primitives */
2224 +#define PKTGET(drv, len, send) ((void*)osl_pktget((len)))
2225 +#define PKTFREE(drv, lb, send) osl_pktfree((struct lbuf*)(lb))
2226 +#define PKTDATA(drv, lb) (((struct lbuf*)(lb))->data)
2227 +#define PKTLEN(drv, lb) (((struct lbuf*)(lb))->len)
2228 +#define PKTHEADROOM(drv, lb) (PKTDATA(drv,lb)-(((struct lbuf*)(lb))->head))
2229 +#define PKTTAILROOM(drv, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2230 +#define PKTNEXT(drv, lb) (((struct lbuf*)(lb))->next)
2231 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2232 +#define PKTSETLEN(drv, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2233 +#define PKTPUSH(drv, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2234 +#define PKTPULL(drv, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2235 +#define PKTDUP(drv, lb) osl_pktdup((struct lbuf*)(lb))
2236 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2237 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2238 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2239 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2240 +#define PKTPRIO(lb) (0)
2241 +#define PKTSETPRIO(lb, x) do {} while (0)
2242 +extern struct lbuf *osl_pktget(uint len);
2243 +extern void osl_pktfree(struct lbuf *lb);
2244 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2245 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2246 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2247 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2248 +
2249 +#endif /* _cfe_osl_h_ */
2250 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
2251 --- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2252 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-08-26 13:44:34.282396080 +0200
2253 @@ -0,0 +1,69 @@
2254 +/*
2255 + * Copyright 2005, Broadcom Corporation
2256 + * All Rights Reserved.
2257 + *
2258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2262 + *
2263 + * $Id$
2264 + *
2265 +*/
2266 +
2267 +#ifndef _epivers_h_
2268 +#define _epivers_h_
2269 +
2270 +#ifdef linux
2271 +#include <linux/config.h>
2272 +#endif
2273 +
2274 +/* Vendor Name, ASCII, 32 chars max */
2275 +#ifdef COMPANYNAME
2276 +#define HPNA_VENDOR COMPANYNAME
2277 +#else
2278 +#define HPNA_VENDOR "Broadcom Corporation"
2279 +#endif
2280 +
2281 +/* Driver Date, ASCII, 32 chars max */
2282 +#define HPNA_DRV_BUILD_DATE __DATE__
2283 +
2284 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2285 +#define HPNA_HW_MFG_DATE "Not Specified"
2286 +
2287 +/* See documentation for Device Type values, 32 values max */
2288 +#ifndef HPNA_DEV_TYPE
2289 +
2290 +#if defined(CONFIG_BRCM_VJ)
2291 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2292 +
2293 +#elif defined(CONFIG_BCRM_93725)
2294 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2295 +
2296 +#else
2297 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2298 +
2299 +#endif
2300 +
2301 +#endif /* !HPNA_DEV_TYPE */
2302 +
2303 +
2304 +#define EPI_MAJOR_VERSION 3
2305 +
2306 +#define EPI_MINOR_VERSION 90
2307 +
2308 +#define EPI_RC_NUMBER 23
2309 +
2310 +#define EPI_INCREMENTAL_NUMBER 0
2311 +
2312 +#define EPI_BUILD_NUMBER 0
2313 +
2314 +#define EPI_VERSION 3,90,23,0
2315 +
2316 +#define EPI_VERSION_NUM 0x035a1700
2317 +
2318 +/* Driver Version String, ASCII, 32 chars max */
2319 +#define EPI_VERSION_STR "3.90.23.0"
2320 +#define EPI_ROUTER_VERSION_STR "3.91.23.0"
2321 +
2322 +#endif /* _epivers_h_ */
2323 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
2324 --- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2325 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-08-26 13:44:34.282396080 +0200
2326 @@ -0,0 +1,69 @@
2327 +/*
2328 + * Copyright 2005, Broadcom Corporation
2329 + * All Rights Reserved.
2330 + *
2331 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2332 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2333 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2334 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2335 + *
2336 + * $Id$
2337 + *
2338 +*/
2339 +
2340 +#ifndef _epivers_h_
2341 +#define _epivers_h_
2342 +
2343 +#ifdef linux
2344 +#include <linux/config.h>
2345 +#endif
2346 +
2347 +/* Vendor Name, ASCII, 32 chars max */
2348 +#ifdef COMPANYNAME
2349 +#define HPNA_VENDOR COMPANYNAME
2350 +#else
2351 +#define HPNA_VENDOR "Broadcom Corporation"
2352 +#endif
2353 +
2354 +/* Driver Date, ASCII, 32 chars max */
2355 +#define HPNA_DRV_BUILD_DATE __DATE__
2356 +
2357 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2358 +#define HPNA_HW_MFG_DATE "Not Specified"
2359 +
2360 +/* See documentation for Device Type values, 32 values max */
2361 +#ifndef HPNA_DEV_TYPE
2362 +
2363 +#if defined(CONFIG_BRCM_VJ)
2364 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2365 +
2366 +#elif defined(CONFIG_BCRM_93725)
2367 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2368 +
2369 +#else
2370 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2371 +
2372 +#endif
2373 +
2374 +#endif /* !HPNA_DEV_TYPE */
2375 +
2376 +
2377 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2378 +
2379 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2380 +
2381 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2382 +
2383 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2384 +
2385 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2386 +
2387 +#define EPI_VERSION @EPI_VERSION@
2388 +
2389 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2390 +
2391 +/* Driver Version String, ASCII, 32 chars max */
2392 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2393 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2394 +
2395 +#endif /* _epivers_h_ */
2396 diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
2397 --- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2398 +++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-08-26 13:44:34.283395928 +0200
2399 @@ -0,0 +1,59 @@
2400 +/*
2401 + * Driver-specific socket ioctls
2402 + * used by BSD, Linux, and PSOS
2403 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2404 + *
2405 + * Copyright 2005, Broadcom Corporation
2406 + * All Rights Reserved.
2407 + *
2408 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2409 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2410 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2411 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2412 + *
2413 + * $Id$
2414 + */
2415 +
2416 +#ifndef _etsockio_h_
2417 +#define _etsockio_h_
2418 +
2419 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2420 +
2421 +
2422 +#if defined(linux)
2423 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2424 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2425 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2426 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2427 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2428 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2429 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2430 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2431 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2432 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2433 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2434 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2435 +
2436 +#else /* !linux */
2437 +
2438 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2439 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2440 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2441 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2442 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2443 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2444 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2445 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2446 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2447 +
2448 +#endif
2449 +
2450 +/* arg to SIOCTXGEN */
2451 +struct txg {
2452 + uint32 num; /* number of frames to send */
2453 + uint32 delay; /* delay in microseconds between sending each */
2454 + uint32 size; /* size of ether frame to send */
2455 + uchar buf[1514]; /* starting ether frame data */
2456 +};
2457 +
2458 +#endif
2459 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
2460 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2461 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-08-27 02:56:56.458670688 +0200
2462 @@ -0,0 +1,188 @@
2463 +/*
2464 + * flash.h: Common definitions for flash access.
2465 + *
2466 + * Copyright 2005, Broadcom Corporation
2467 + * All Rights Reserved.
2468 + *
2469 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2470 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2471 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2472 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2473 + *
2474 + * $Id$
2475 + */
2476 +
2477 +/* Types of flashes we know about */
2478 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2479 +
2480 +/* Commands to write/erase the flases */
2481 +typedef struct _flash_cmds{
2482 + flash_type_t type;
2483 + bool need_unlock;
2484 + uint16 pre_erase;
2485 + uint16 erase_block;
2486 + uint16 erase_chip;
2487 + uint16 write_word;
2488 + uint16 write_buf;
2489 + uint16 clear_csr;
2490 + uint16 read_csr;
2491 + uint16 read_id;
2492 + uint16 confirm;
2493 + uint16 read_array;
2494 +} flash_cmds_t;
2495 +
2496 +#define UNLOCK_CMD_WORDS 2
2497 +
2498 +typedef struct _unlock_cmd {
2499 + uint addr[UNLOCK_CMD_WORDS];
2500 + uint16 cmd[UNLOCK_CMD_WORDS];
2501 +} unlock_cmd_t;
2502 +
2503 +/* Flash descriptors */
2504 +typedef struct _flash_desc {
2505 + uint16 mfgid; /* Manufacturer Id */
2506 + uint16 devid; /* Device Id */
2507 + uint size; /* Total size in bytes */
2508 + uint width; /* Device width in bytes */
2509 + flash_type_t type; /* Device type old, S, J */
2510 + uint bsize; /* Block size */
2511 + uint nb; /* Number of blocks */
2512 + uint ff; /* First full block */
2513 + uint lf; /* Last full block */
2514 + uint nsub; /* Number of subblocks */
2515 + uint *subblocks; /* Offsets for subblocks */
2516 + char *desc; /* Description */
2517 +} flash_desc_t;
2518 +
2519 +
2520 +#ifdef DECLARE_FLASHES
2521 +flash_cmds_t sflash_cmd_t =
2522 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2523 +
2524 +flash_cmds_t flash_cmds[] = {
2525 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2526 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2527 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2528 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2529 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2530 + { 0 }
2531 +};
2532 +
2533 +unlock_cmd_t unlock_cmd_amd = {
2534 +#ifdef MIPSEB
2535 +/* addr: */ { 0x0aa8, 0x0556},
2536 +#else
2537 +/* addr: */ { 0x0aaa, 0x0554},
2538 +#endif
2539 +/* data: */ { 0xaa, 0x55}
2540 +};
2541 +
2542 +unlock_cmd_t unlock_cmd_sst = {
2543 +#ifdef MIPSEB
2544 +/* addr: */ { 0xaaa8, 0x5556},
2545 +#else
2546 +/* addr: */ { 0xaaaa, 0x5554},
2547 +#endif
2548 +/* data: */ { 0xaa, 0x55}
2549 +};
2550 +
2551 +#define AMD_CMD 0xaaa
2552 +#define SST_CMD 0xaaaa
2553 +
2554 +/* intel unlock block cmds */
2555 +#define INTEL_UNLOCK1 0x60
2556 +#define INTEL_UNLOCK2 0xD0
2557 +
2558 +/* Just eight blocks of 8KB byte each */
2559 +
2560 +uint blk8x8k[] = { 0x00000000,
2561 + 0x00002000,
2562 + 0x00004000,
2563 + 0x00006000,
2564 + 0x00008000,
2565 + 0x0000a000,
2566 + 0x0000c000,
2567 + 0x0000e000,
2568 + 0x00010000
2569 +};
2570 +
2571 +/* Funky AMD arrangement for 29xx800's */
2572 +uint amd800[] = { 0x00000000, /* 16KB */
2573 + 0x00004000, /* 32KB */
2574 + 0x0000c000, /* 8KB */
2575 + 0x0000e000, /* 8KB */
2576 + 0x00010000, /* 8KB */
2577 + 0x00012000, /* 8KB */
2578 + 0x00014000, /* 32KB */
2579 + 0x0001c000, /* 16KB */
2580 + 0x00020000
2581 +};
2582 +
2583 +/* AMD arrangement for 29xx160's */
2584 +uint amd4112[] = { 0x00000000, /* 32KB */
2585 + 0x00008000, /* 8KB */
2586 + 0x0000a000, /* 8KB */
2587 + 0x0000c000, /* 16KB */
2588 + 0x00010000
2589 +};
2590 +uint amd2114[] = { 0x00000000, /* 16KB */
2591 + 0x00004000, /* 8KB */
2592 + 0x00006000, /* 8KB */
2593 + 0x00008000, /* 32KB */
2594 + 0x00010000
2595 +};
2596 +
2597 +
2598 +flash_desc_t sflash_desc =
2599 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2600 +
2601 +flash_desc_t flashes[] = {
2602 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2603 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2604 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2605 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2606 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2607 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2608 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2609 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2610 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2611 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2612 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2613 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2614 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2615 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2616 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2617 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2618 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2619 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2620 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2621 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2622 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2623 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2624 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2625 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2626 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2627 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2628 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2629 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2630 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2631 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2632 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2633 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2634 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2635 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2636 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2637 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2638 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2639 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2640 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2641 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2642 +};
2643 +
2644 +#else
2645 +
2646 +extern flash_cmds_t flash_cmds[];
2647 +extern unlock_cmd_t unlock_cmd;
2648 +extern flash_desc_t flashes[];
2649 +
2650 +#endif
2651 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
2652 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2653 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-08-26 13:44:34.284395776 +0200
2654 @@ -0,0 +1,27 @@
2655 +/*
2656 + * BCM47XX FLASH driver interface
2657 + *
2658 + * Copyright 2005, Broadcom Corporation
2659 + * All Rights Reserved.
2660 + *
2661 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2662 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2663 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2664 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2665 + * $Id$
2666 + */
2667 +
2668 +#ifndef _flashutl_h_
2669 +#define _flashutl_h_
2670 +
2671 +
2672 +#ifndef _LANGUAGE_ASSEMBLY
2673 +
2674 +int sysFlashInit(char *flash_str);
2675 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2676 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2677 +void nvWrite(unsigned short *data, unsigned int len);
2678 +
2679 +#endif /* _LANGUAGE_ASSEMBLY */
2680 +
2681 +#endif /* _flashutl_h_ */
2682 diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
2683 --- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2684 +++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-08-26 13:44:34.284395776 +0200
2685 @@ -0,0 +1,184 @@
2686 +/*
2687 + * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
2688 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2689 + *
2690 + * Copyright 2005, Broadcom Corporation
2691 + * All Rights Reserved.
2692 + *
2693 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2694 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2695 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2696 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2697 + * $Id$
2698 + */
2699 +
2700 +#ifndef _hnddma_h_
2701 +#define _hnddma_h_
2702 +
2703 +/*
2704 + * Each DMA processor consists of a transmit channel and a receive channel.
2705 + */
2706 +typedef volatile struct {
2707 + /* transmit channel */
2708 + uint32 xmtcontrol; /* enable, et al */
2709 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
2710 + uint32 xmtptr; /* last descriptor posted to chip */
2711 + uint32 xmtstatus; /* current active descriptor, et al */
2712 +
2713 + /* receive channel */
2714 + uint32 rcvcontrol; /* enable, et al */
2715 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
2716 + uint32 rcvptr; /* last descriptor posted to chip */
2717 + uint32 rcvstatus; /* current active descriptor, et al */
2718 +} dmaregs_t;
2719 +
2720 +typedef volatile struct {
2721 + /* diag access */
2722 + uint32 fifoaddr; /* diag address */
2723 + uint32 fifodatalow; /* low 32bits of data */
2724 + uint32 fifodatahigh; /* high 32bits of data */
2725 + uint32 pad; /* reserved */
2726 +} dmafifo_t;
2727 +
2728 +/* transmit channel control */
2729 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
2730 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
2731 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
2732 +#define XC_FL ((uint32)1 << 4) /* flush request */
2733 +
2734 +/* transmit descriptor table pointer */
2735 +#define XP_LD_MASK 0xfff /* last valid descriptor */
2736 +
2737 +/* transmit channel status */
2738 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
2739 +#define XS_XS_MASK 0xf000 /* transmit state */
2740 +#define XS_XS_SHIFT 12
2741 +#define XS_XS_DISABLED 0x0000 /* disabled */
2742 +#define XS_XS_ACTIVE 0x1000 /* active */
2743 +#define XS_XS_IDLE 0x2000 /* idle wait */
2744 +#define XS_XS_STOPPED 0x3000 /* stopped */
2745 +#define XS_XS_SUSP 0x4000 /* suspend pending */
2746 +#define XS_XE_MASK 0xf0000 /* transmit errors */
2747 +#define XS_XE_SHIFT 16
2748 +#define XS_XE_NOERR 0x00000 /* no error */
2749 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
2750 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
2751 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
2752 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
2753 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
2754 +#define XS_AD_SHIFT 20
2755 +
2756 +/* receive channel control */
2757 +#define RC_RE ((uint32)1 << 0) /* receive enable */
2758 +#define RC_RO_MASK 0xfe /* receive frame offset */
2759 +#define RC_RO_SHIFT 1
2760 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
2761 +
2762 +/* receive descriptor table pointer */
2763 +#define RP_LD_MASK 0xfff /* last valid descriptor */
2764 +
2765 +/* receive channel status */
2766 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
2767 +#define RS_RS_MASK 0xf000 /* receive state */
2768 +#define RS_RS_SHIFT 12
2769 +#define RS_RS_DISABLED 0x0000 /* disabled */
2770 +#define RS_RS_ACTIVE 0x1000 /* active */
2771 +#define RS_RS_IDLE 0x2000 /* idle wait */
2772 +#define RS_RS_STOPPED 0x3000 /* reserved */
2773 +#define RS_RE_MASK 0xf0000 /* receive errors */
2774 +#define RS_RE_SHIFT 16
2775 +#define RS_RE_NOERR 0x00000 /* no error */
2776 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
2777 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
2778 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
2779 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
2780 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
2781 +#define RS_AD_SHIFT 20
2782 +
2783 +/* fifoaddr */
2784 +#define FA_OFF_MASK 0xffff /* offset */
2785 +#define FA_SEL_MASK 0xf0000 /* select */
2786 +#define FA_SEL_SHIFT 16
2787 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
2788 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
2789 +#define FA_SEL_RDD 0x40000 /* receive dma data */
2790 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
2791 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
2792 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
2793 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
2794 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
2795 +
2796 +/*
2797 + * DMA Descriptor
2798 + * Descriptors are only read by the hardware, never written back.
2799 + */
2800 +typedef volatile struct {
2801 + uint32 ctrl; /* misc control bits & bufcount */
2802 + uint32 addr; /* data buffer address */
2803 +} dmadd_t;
2804 +
2805 +/*
2806 + * Each descriptor ring must be 4096byte aligned
2807 + * and fit within a single 4096byte page.
2808 + */
2809 +#define DMAMAXRINGSZ 4096
2810 +#define DMARINGALIGN 4096
2811 +
2812 +/* control flags */
2813 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
2814 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
2815 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
2816 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
2817 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
2818 +
2819 +/* control flags in the range [27:20] are core-specific and not defined here */
2820 +#define CTRL_CORE_MASK 0x0ff00000
2821 +
2822 +/* export structure */
2823 +typedef volatile struct {
2824 + /* rx error counters */
2825 + uint rxgiants; /* rx giant frames */
2826 + uint rxnobuf; /* rx out of dma descriptors */
2827 + /* tx error counters */
2828 + uint txnobuf; /* tx out of dma descriptors */
2829 +} hnddma_t;
2830 +
2831 +#ifndef di_t
2832 +#define di_t void
2833 +#endif
2834 +
2835 +/* externs */
2836 +extern void * dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
2837 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
2838 + uint ddoffset, uint dataoffset, uint *msg_level);
2839 +extern void dma_detach(di_t *di);
2840 +extern void dma_txreset(di_t *di);
2841 +extern void dma_rxreset(di_t *di);
2842 +extern void dma_txinit(di_t *di);
2843 +extern bool dma_txenabled(di_t *di);
2844 +extern void dma_rxinit(di_t *di);
2845 +extern void dma_rxenable(di_t *di);
2846 +extern bool dma_rxenabled(di_t *di);
2847 +extern void dma_txsuspend(di_t *di);
2848 +extern void dma_txresume(di_t *di);
2849 +extern bool dma_txsuspended(di_t *di);
2850 +extern bool dma_txstopped(di_t *di);
2851 +extern bool dma_rxstopped(di_t *di);
2852 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2853 +extern int dma_tx(di_t *di, void *p, uint32 coreflags);
2854 +extern void dma_fifoloopbackenable(di_t *di);
2855 +extern void *dma_rx(di_t *di);
2856 +extern void dma_rxfill(di_t *di);
2857 +extern void dma_txreclaim(di_t *di, bool forceall);
2858 +extern void dma_rxreclaim(di_t *di);
2859 +extern uintptr dma_getvar(di_t *di, char *name);
2860 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2861 +extern void *dma_peeknexttxp(di_t *di);
2862 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2863 +extern void dma_txblock(di_t *di);
2864 +extern void dma_txunblock(di_t *di);
2865 +extern uint dma_txactive(di_t *di);
2866 +extern void dma_txrotate(di_t *di);
2867 +
2868 +
2869 +#endif /* _hnddma_h_ */
2870 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
2871 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2872 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-08-26 13:44:34.285395624 +0200
2873 @@ -0,0 +1,16 @@
2874 +/*
2875 + * Alternate include file for HND sbmips.h since CFE also ships with
2876 + * a sbmips.h.
2877 + *
2878 + * Copyright 2005, Broadcom Corporation
2879 + * All Rights Reserved.
2880 + *
2881 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2882 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2883 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2884 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2885 + *
2886 + * $Id$
2887 + */
2888 +
2889 +#include "sbmips.h"
2890 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
2891 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2892 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-08-26 13:44:34.286395472 +0200
2893 @@ -0,0 +1,341 @@
2894 +/*
2895 + * Linux OS Independent Layer
2896 + *
2897 + * Copyright 2005, Broadcom Corporation
2898 + * All Rights Reserved.
2899 + *
2900 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2901 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2902 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2903 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2904 + *
2905 + * $Id$
2906 + */
2907 +
2908 +#ifndef _linux_osl_h_
2909 +#define _linux_osl_h_
2910 +
2911 +#include <typedefs.h>
2912 +
2913 +/* use current 2.4.x calling conventions */
2914 +#include <linuxver.h>
2915 +
2916 +/* assert and panic */
2917 +#define ASSERT(exp) do {} while (0)
2918 +
2919 +/* PCMCIA attribute space access macros */
2920 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2921 +struct pcmcia_dev {
2922 + dev_link_t link; /* PCMCIA device pointer */
2923 + dev_node_t node; /* PCMCIA node structure */
2924 + void *base; /* Mapped attribute memory window */
2925 + size_t size; /* Size of window */
2926 + void *drv; /* Driver data */
2927 +};
2928 +#endif
2929 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2930 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2931 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2932 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2933 +extern void osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size);
2934 +extern void osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size);
2935 +
2936 +/* PCI configuration space access macros */
2937 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2938 + osl_pci_read_config((osh), (offset), (size))
2939 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2940 + osl_pci_write_config((osh), (offset), (size), (val))
2941 +extern uint32 osl_pci_read_config(void *osh, uint size, uint offset);
2942 +extern void osl_pci_write_config(void *osh, uint offset, uint size, uint val);
2943 +
2944 +/* OSL initialization */
2945 +extern void *osl_attach(void *pdev);
2946 +extern void osl_detach(void *osh);
2947 +
2948 +/* host/bus architecture-specific byte swap */
2949 +#define BUS_SWAP32(v) (v)
2950 +
2951 +/* general purpose memory allocation */
2952 +
2953 +#if defined(BCMDBG_MEM)
2954 +
2955 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2956 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2957 +#define MALLOCED(osh) osl_malloced((osh))
2958 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2959 +extern void *osl_debug_malloc(void *osh, uint size, int line, char* file);
2960 +extern void osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file);
2961 +extern char *osl_debug_memdump(void *osh, char *buf, uint sz);
2962 +
2963 +#else
2964 +
2965 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2966 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2967 +#define MALLOCED(osh) osl_malloced((osh))
2968 +
2969 +#endif /* BCMDBG_MEM */
2970 +
2971 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2972 +
2973 +extern void *osl_malloc(void *osh, uint size);
2974 +extern void osl_mfree(void *osh, void *addr, uint size);
2975 +extern uint osl_malloced(void *osh);
2976 +extern uint osl_malloc_failed(void *osh);
2977 +
2978 +/* allocate/free shared (dma-able) consistent memory */
2979 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2980 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2981 + osl_dma_alloc_consistent((osh), (size), (pap))
2982 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2983 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2984 +extern void *osl_dma_alloc_consistent(void *osh, uint size, ulong *pap);
2985 +extern void osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa);
2986 +
2987 +/* map/unmap direction */
2988 +#define DMA_TX 1
2989 +#define DMA_RX 2
2990 +
2991 +/* map/unmap shared (dma-able) memory */
2992 +#define DMA_MAP(osh, va, size, direction, p) \
2993 + osl_dma_map((osh), (va), (size), (direction))
2994 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2995 + osl_dma_unmap((osh), (pa), (size), (direction))
2996 +extern uint osl_dma_map(void *osh, void *va, uint size, int direction);
2997 +extern void osl_dma_unmap(void *osh, uint pa, uint size, int direction);
2998 +
2999 +/* register access macros */
3000 +#if defined(BCMJTAG)
3001 +struct bcmjtag_info;
3002 +extern uint32 bcmjtag_read(struct bcmjtag_info *ejh, uint32 addr, uint size);
3003 +extern void bcmjtag_write(struct bcmjtag_info *ejh, uint32 addr, uint32 val, uint size);
3004 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
3005 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
3006 +#endif
3007 +
3008 +/*
3009 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3010 + * Macros expand to calls to functions defined in linux_osl.c .
3011 + */
3012 +#ifndef BINOSL
3013 +
3014 +/* string library, kernel mode */
3015 +#define printf(fmt, args...) printk(fmt, ## args)
3016 +#include <linux/kernel.h>
3017 +#include <linux/string.h>
3018 +
3019 +/* register access macros */
3020 +#if !defined(BCMJTAG)
3021 +#define R_REG(r) ( \
3022 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3023 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3024 + readl((volatile uint32*)(r)) \
3025 +)
3026 +#define W_REG(r, v) do { \
3027 + switch (sizeof(*(r))) { \
3028 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3029 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3030 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3031 + } \
3032 +} while (0)
3033 +#endif
3034 +
3035 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3036 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3037 +
3038 +/* bcopy, bcmp, and bzero */
3039 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3040 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3041 +#define bzero(b, len) memset((b), '\0', (len))
3042 +
3043 +/* uncached virtual address */
3044 +#ifdef mips
3045 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3046 +#include <asm/addrspace.h>
3047 +#else
3048 +#define OSL_UNCACHED(va) (va)
3049 +#endif
3050 +
3051 +/* get processor cycle count */
3052 +#if defined(mips)
3053 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3054 +#elif defined(__i386__)
3055 +#define OSL_GETCYCLES(x) rdtscl((x))
3056 +#else
3057 +#define OSL_GETCYCLES(x) ((x) = 0)
3058 +#endif
3059 +
3060 +/* dereference an address that may cause a bus exception */
3061 +#ifdef mips
3062 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3063 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3064 +#else
3065 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3066 +#include <asm/paccess.h>
3067 +#endif
3068 +#else
3069 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3070 +#endif
3071 +
3072 +/* map/unmap physical to virtual I/O */
3073 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3074 +#define REG_UNMAP(va) iounmap((void *)(va))
3075 +
3076 +/* microsecond delay */
3077 +#define OSL_DELAY(usec) udelay(usec)
3078 +#include <linux/delay.h>
3079 +
3080 +/* shared (dma-able) memory access macros */
3081 +#define R_SM(r) *(r)
3082 +#define W_SM(r, v) (*(r) = (v))
3083 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3084 +
3085 +/* packet primitives */
3086 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
3087 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
3088 +#define PKTDATA(drv, skb) (((struct sk_buff*)(skb))->data)
3089 +#define PKTLEN(drv, skb) (((struct sk_buff*)(skb))->len)
3090 +#define PKTHEADROOM(drv, skb) (PKTDATA(drv,skb)-(((struct sk_buff*)(skb))->head))
3091 +#define PKTTAILROOM(drv, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3092 +#define PKTNEXT(drv, skb) (((struct sk_buff*)(skb))->next)
3093 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3094 +#define PKTSETLEN(drv, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3095 +#define PKTPUSH(drv, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3096 +#define PKTPULL(drv, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3097 +#define PKTDUP(drv, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3098 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3099 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3100 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3101 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3102 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3103 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3104 +extern void *osl_pktget(void *drv, uint len, bool send);
3105 +extern void osl_pktfree(void *skb);
3106 +
3107 +#else /* BINOSL */
3108 +
3109 +/* string library */
3110 +#ifndef LINUX_OSL
3111 +#undef printf
3112 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3113 +#undef sprintf
3114 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3115 +#undef strcmp
3116 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3117 +#undef strncmp
3118 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3119 +#undef strlen
3120 +#define strlen(s) osl_strlen((s))
3121 +#undef strcpy
3122 +#define strcpy(d, s) osl_strcpy((d), (s))
3123 +#undef strncpy
3124 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3125 +#endif
3126 +extern int osl_printf(const char *format, ...);
3127 +extern int osl_sprintf(char *buf, const char *format, ...);
3128 +extern int osl_strcmp(const char *s1, const char *s2);
3129 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3130 +extern int osl_strlen(char *s);
3131 +extern char* osl_strcpy(char *d, const char *s);
3132 +extern char* osl_strncpy(char *d, const char *s, uint n);
3133 +
3134 +/* register access macros */
3135 +#if !defined(BCMJTAG)
3136 +#define R_REG(r) ( \
3137 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3138 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3139 + osl_readl((volatile uint32*)(r)) \
3140 +)
3141 +#define W_REG(r, v) do { \
3142 + switch (sizeof(*(r))) { \
3143 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3144 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3145 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3146 + } \
3147 +} while (0)
3148 +#endif
3149 +
3150 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3151 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3152 +extern uint8 osl_readb(volatile uint8 *r);
3153 +extern uint16 osl_readw(volatile uint16 *r);
3154 +extern uint32 osl_readl(volatile uint32 *r);
3155 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3156 +extern void osl_writew(uint16 v, volatile uint16 *r);
3157 +extern void osl_writel(uint32 v, volatile uint32 *r);
3158 +
3159 +/* bcopy, bcmp, and bzero */
3160 +extern void bcopy(const void *src, void *dst, int len);
3161 +extern int bcmp(const void *b1, const void *b2, int len);
3162 +extern void bzero(void *b, int len);
3163 +
3164 +/* uncached virtual address */
3165 +#define OSL_UNCACHED(va) osl_uncached((va))
3166 +extern void *osl_uncached(void *va);
3167 +
3168 +/* get processor cycle count */
3169 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3170 +extern uint osl_getcycles(void);
3171 +
3172 +/* dereference an address that may target abort */
3173 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3174 +extern int osl_busprobe(uint32 *val, uint32 addr);
3175 +
3176 +/* map/unmap physical to virtual */
3177 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3178 +#define REG_UNMAP(va) osl_reg_unmap((va))
3179 +extern void *osl_reg_map(uint32 pa, uint size);
3180 +extern void osl_reg_unmap(void *va);
3181 +
3182 +/* microsecond delay */
3183 +#define OSL_DELAY(usec) osl_delay((usec))
3184 +extern void osl_delay(uint usec);
3185 +
3186 +/* shared (dma-able) memory access macros */
3187 +#define R_SM(r) *(r)
3188 +#define W_SM(r, v) (*(r) = (v))
3189 +#define BZERO_SM(r, len) bzero((r), (len))
3190 +
3191 +/* packet primitives */
3192 +#define PKTGET(drv, len, send) osl_pktget((drv), (len), (send))
3193 +#define PKTFREE(drv, skb, send) osl_pktfree((skb))
3194 +#define PKTDATA(drv, skb) osl_pktdata((drv), (skb))
3195 +#define PKTLEN(drv, skb) osl_pktlen((drv), (skb))
3196 +#define PKTHEADROOM(drv, skb) osl_pktheadroom((drv), (skb))
3197 +#define PKTTAILROOM(drv, skb) osl_pkttailroom((drv), (skb))
3198 +#define PKTNEXT(drv, skb) osl_pktnext((drv), (skb))
3199 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3200 +#define PKTSETLEN(drv, skb, len) osl_pktsetlen((drv), (skb), (len))
3201 +#define PKTPUSH(drv, skb, bytes) osl_pktpush((drv), (skb), (bytes))
3202 +#define PKTPULL(drv, skb, bytes) osl_pktpull((drv), (skb), (bytes))
3203 +#define PKTDUP(drv, skb) osl_pktdup((drv), (skb))
3204 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3205 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3206 +#define PKTLINK(skb) osl_pktlink((skb))
3207 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3208 +#define PKTPRIO(skb) osl_pktprio((skb))
3209 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3210 +extern void *osl_pktget(void *drv, uint len, bool send);
3211 +extern void osl_pktfree(void *skb);
3212 +extern uchar *osl_pktdata(void *drv, void *skb);
3213 +extern uint osl_pktlen(void *drv, void *skb);
3214 +extern uint osl_pktheadroom(void *drv, void *skb);
3215 +extern uint osl_pkttailroom(void *drv, void *skb);
3216 +extern void *osl_pktnext(void *drv, void *skb);
3217 +extern void osl_pktsetnext(void *skb, void *x);
3218 +extern void osl_pktsetlen(void *drv, void *skb, uint len);
3219 +extern uchar *osl_pktpush(void *drv, void *skb, int bytes);
3220 +extern uchar *osl_pktpull(void *drv, void *skb, int bytes);
3221 +extern void *osl_pktdup(void *drv, void *skb);
3222 +extern void *osl_pktcookie(void *skb);
3223 +extern void osl_pktsetcookie(void *skb, void *x);
3224 +extern void *osl_pktlink(void *skb);
3225 +extern void osl_pktsetlink(void *skb, void *x);
3226 +extern uint osl_pktprio(void *skb);
3227 +extern void osl_pktsetprio(void *skb, uint x);
3228 +
3229 +#endif /* BINOSL */
3230 +
3231 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3232 +#define PKTBUFSZ 2048
3233 +
3234 +#endif /* _linux_osl_h_ */
3235 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
3236 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3237 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-08-26 13:44:34.287395320 +0200
3238 @@ -0,0 +1,399 @@
3239 +/*
3240 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3241 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3242 + *
3243 + * Copyright 2005, Broadcom Corporation
3244 + * All Rights Reserved.
3245 + *
3246 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3247 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3248 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3249 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3250 + *
3251 + * $Id$
3252 + */
3253 +
3254 +#ifndef _linuxver_h_
3255 +#define _linuxver_h_
3256 +
3257 +#include <linux/config.h>
3258 +#include <linux/version.h>
3259 +
3260 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3261 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3262 +#ifdef __UNDEF_NO_VERSION__
3263 +#undef __NO_VERSION__
3264 +#else
3265 +#define __NO_VERSION__
3266 +#endif
3267 +#endif
3268 +
3269 +#if defined(MODULE) && defined(MODVERSIONS)
3270 +#include <linux/modversions.h>
3271 +#endif
3272 +
3273 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3274 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3275 +#include <linux/malloc.h>
3276 +#else
3277 +#include <linux/slab.h>
3278 +#endif
3279 +
3280 +#include <linux/types.h>
3281 +#include <linux/init.h>
3282 +#include <linux/mm.h>
3283 +#include <linux/string.h>
3284 +#include <linux/pci.h>
3285 +#include <linux/interrupt.h>
3286 +#include <linux/netdevice.h>
3287 +#include <asm/io.h>
3288 +
3289 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3290 +#include <linux/workqueue.h>
3291 +#else
3292 +#include <linux/tqueue.h>
3293 +#ifndef work_struct
3294 +#define work_struct tq_struct
3295 +#endif
3296 +#ifndef INIT_WORK
3297 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3298 +#endif
3299 +#ifndef schedule_work
3300 +#define schedule_work(_work) schedule_task((_work))
3301 +#endif
3302 +#ifndef flush_scheduled_work
3303 +#define flush_scheduled_work() flush_scheduled_tasks()
3304 +#endif
3305 +#endif
3306 +
3307 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3308 +/* Some distributions have their own 2.6.x compatibility layers */
3309 +#ifndef IRQ_NONE
3310 +typedef void irqreturn_t;
3311 +#define IRQ_NONE
3312 +#define IRQ_HANDLED
3313 +#define IRQ_RETVAL(x)
3314 +#endif
3315 +#endif
3316 +
3317 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3318 +
3319 +#include <pcmcia/version.h>
3320 +#include <pcmcia/cs_types.h>
3321 +#include <pcmcia/cs.h>
3322 +#include <pcmcia/cistpl.h>
3323 +#include <pcmcia/cisreg.h>
3324 +#include <pcmcia/ds.h>
3325 +
3326 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3327 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3328 + * does this, but it's not in 2.4 so we do our own for now. */
3329 +static inline void
3330 +cs_error(client_handle_t handle, int func, int ret)
3331 +{
3332 + error_info_t err = { func, ret };
3333 + CardServices(ReportError, handle, &err);
3334 +}
3335 +#endif
3336 +
3337 +#endif /* CONFIG_PCMCIA */
3338 +
3339 +#ifndef __exit
3340 +#define __exit
3341 +#endif
3342 +#ifndef __devexit
3343 +#define __devexit
3344 +#endif
3345 +#ifndef __devinit
3346 +#define __devinit __init
3347 +#endif
3348 +#ifndef __devinitdata
3349 +#define __devinitdata
3350 +#endif
3351 +#ifndef __devexit_p
3352 +#define __devexit_p(x) x
3353 +#endif
3354 +
3355 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3356 +
3357 +#define pci_get_drvdata(dev) (dev)->sysdata
3358 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3359 +
3360 +/*
3361 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3362 + */
3363 +
3364 +struct pci_device_id {
3365 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3366 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3367 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3368 + unsigned long driver_data; /* Data private to the driver */
3369 +};
3370 +
3371 +struct pci_driver {
3372 + struct list_head node;
3373 + char *name;
3374 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3375 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3376 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3377 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3378 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3379 +};
3380 +
3381 +#define MODULE_DEVICE_TABLE(type, name)
3382 +#define PCI_ANY_ID (~0)
3383 +
3384 +/* compatpci.c */
3385 +#define pci_module_init pci_register_driver
3386 +extern int pci_register_driver(struct pci_driver *drv);
3387 +extern void pci_unregister_driver(struct pci_driver *drv);
3388 +
3389 +#endif /* PCI registration */
3390 +
3391 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3392 +#ifdef MODULE
3393 +#define module_init(x) int init_module(void) { return x(); }
3394 +#define module_exit(x) void cleanup_module(void) { x(); }
3395 +#else
3396 +#define module_init(x) __initcall(x);
3397 +#define module_exit(x) __exitcall(x);
3398 +#endif
3399 +#endif
3400 +
3401 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3402 +#define list_for_each(pos, head) \
3403 + for (pos = (head)->next; pos != (head); pos = pos->next)
3404 +#endif
3405 +
3406 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3407 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3408 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3409 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3410 +#endif
3411 +
3412 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3413 +#define pci_enable_device(dev) do { } while (0)
3414 +#endif
3415 +
3416 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3417 +#define net_device device
3418 +#endif
3419 +
3420 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3421 +
3422 +/*
3423 + * DMA mapping
3424 + *
3425 + * See linux/Documentation/DMA-mapping.txt
3426 + */
3427 +
3428 +#ifndef PCI_DMA_TODEVICE
3429 +#define PCI_DMA_TODEVICE 1
3430 +#define PCI_DMA_FROMDEVICE 2
3431 +#endif
3432 +
3433 +typedef u32 dma_addr_t;
3434 +
3435 +/* Pure 2^n version of get_order */
3436 +static inline int get_order(unsigned long size)
3437 +{
3438 + int order;
3439 +
3440 + size = (size-1) >> (PAGE_SHIFT-1);
3441 + order = -1;
3442 + do {
3443 + size >>= 1;
3444 + order++;
3445 + } while (size);
3446 + return order;
3447 +}
3448 +
3449 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3450 + dma_addr_t *dma_handle)
3451 +{
3452 + void *ret;
3453 + int gfp = GFP_ATOMIC | GFP_DMA;
3454 +
3455 + ret = (void *)__get_free_pages(gfp, get_order(size));
3456 +
3457 + if (ret != NULL) {
3458 + memset(ret, 0, size);
3459 + *dma_handle = virt_to_bus(ret);
3460 + }
3461 + return ret;
3462 +}
3463 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3464 + void *vaddr, dma_addr_t dma_handle)
3465 +{
3466 + free_pages((unsigned long)vaddr, get_order(size));
3467 +}
3468 +#ifdef ILSIM
3469 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3470 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3471 +#else
3472 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3473 +#define pci_unmap_single(cookie, address, size, dir)
3474 +#endif
3475 +
3476 +#endif /* DMA mapping */
3477 +
3478 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3479 +
3480 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3481 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3482 +
3483 +/* pcmcia-cs provides its own netdevice compatibility layer */
3484 +#ifndef _COMPAT_NETDEVICE_H
3485 +
3486 +/*
3487 + * SoftNet
3488 + *
3489 + * For pre-softnet kernels we need to tell the upper layer not to
3490 + * re-enter start_xmit() while we are in there. However softnet
3491 + * guarantees not to enter while we are in there so there is no need
3492 + * to do the netif_stop_queue() dance unless the transmit queue really
3493 + * gets stuck. This should also improve performance according to tests
3494 + * done by Aman Singla.
3495 + */
3496 +
3497 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3498 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3499 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3500 +
3501 +static inline void netif_start_queue(struct net_device *dev)
3502 +{
3503 + dev->tbusy = 0;
3504 + dev->interrupt = 0;
3505 + dev->start = 1;
3506 +}
3507 +
3508 +#define netif_queue_stopped(dev) (dev)->tbusy
3509 +#define netif_running(dev) (dev)->start
3510 +
3511 +#endif /* _COMPAT_NETDEVICE_H */
3512 +
3513 +#define netif_device_attach(dev) netif_start_queue(dev)
3514 +#define netif_device_detach(dev) netif_stop_queue(dev)
3515 +
3516 +/* 2.4.x renamed bottom halves to tasklets */
3517 +#define tasklet_struct tq_struct
3518 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3519 +{
3520 + queue_task(tasklet, &tq_immediate);
3521 + mark_bh(IMMEDIATE_BH);
3522 +}
3523 +
3524 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3525 + void (*func)(unsigned long),
3526 + unsigned long data)
3527 +{
3528 + tasklet->next = NULL;
3529 + tasklet->sync = 0;
3530 + tasklet->routine = (void (*)(void *))func;
3531 + tasklet->data = (void *)data;
3532 +}
3533 +#define tasklet_kill(tasklet) {do{} while(0);}
3534 +
3535 +/* 2.4.x introduced del_timer_sync() */
3536 +#define del_timer_sync(timer) del_timer(timer)
3537 +
3538 +#else
3539 +
3540 +#define netif_down(dev)
3541 +
3542 +#endif /* SoftNet */
3543 +
3544 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3545 +
3546 +/*
3547 + * Emit code to initialise a tq_struct's routine and data pointers
3548 + */
3549 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3550 + do { \
3551 + (_tq)->routine = _routine; \
3552 + (_tq)->data = _data; \
3553 + } while (0)
3554 +
3555 +/*
3556 + * Emit code to initialise all of a tq_struct
3557 + */
3558 +#define INIT_TQUEUE(_tq, _routine, _data) \
3559 + do { \
3560 + INIT_LIST_HEAD(&(_tq)->list); \
3561 + (_tq)->sync = 0; \
3562 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3563 + } while (0)
3564 +
3565 +#endif
3566 +
3567 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3568 +
3569 +/* Power management related routines */
3570 +
3571 +static inline int
3572 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3573 +{
3574 + int i;
3575 + if (buffer) {
3576 + for (i = 0; i < 16; i++)
3577 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3578 + }
3579 + return 0;
3580 +}
3581 +
3582 +static inline int
3583 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3584 +{
3585 + int i;
3586 +
3587 + if (buffer) {
3588 + for (i = 0; i < 16; i++)
3589 + pci_write_config_dword(dev,i * 4, buffer[i]);
3590 + }
3591 + /*
3592 + * otherwise, write the context information we know from bootup.
3593 + * This works around a problem where warm-booting from Windows
3594 + * combined with a D3(hot)->D0 transition causes PCI config
3595 + * header data to be forgotten.
3596 + */
3597 + else {
3598 + for (i = 0; i < 6; i ++)
3599 + pci_write_config_dword(dev,
3600 + PCI_BASE_ADDRESS_0 + (i * 4),
3601 + pci_resource_start(dev, i));
3602 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3603 + }
3604 + return 0;
3605 +}
3606 +
3607 +#endif /* PCI power management */
3608 +
3609 +/* Old cp0 access macros deprecated in 2.4.19 */
3610 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3611 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3612 +#endif
3613 +
3614 +/* Module refcount handled internally in 2.6.x */
3615 +#ifndef SET_MODULE_OWNER
3616 +#define SET_MODULE_OWNER(dev) do {} while (0)
3617 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3618 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3619 +#else
3620 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3621 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3622 +#endif
3623 +
3624 +#ifndef SET_NETDEV_DEV
3625 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3626 +#endif
3627 +
3628 +#ifndef HAVE_FREE_NETDEV
3629 +#define free_netdev(dev) kfree(dev)
3630 +#endif
3631 +
3632 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3633 +/* struct packet_type redefined in 2.6.x */
3634 +#define af_packet_priv data
3635 +#endif
3636 +
3637 +#endif /* _linuxver_h_ */
3638 diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
3639 --- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3640 +++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-08-26 13:44:34.287395320 +0200
3641 @@ -0,0 +1,120 @@
3642 +/*
3643 + * HND Minimal OS Abstraction Layer.
3644 + *
3645 + * Copyright 2005, Broadcom Corporation
3646 + * All Rights Reserved.
3647 + *
3648 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3649 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3650 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3651 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3652 + *
3653 + * $Id$
3654 + */
3655 +
3656 +#ifndef _min_osl_h_
3657 +#define _min_osl_h_
3658 +
3659 +#include <typedefs.h>
3660 +#include <sbconfig.h>
3661 +
3662 +/* Cache support */
3663 +extern void caches_on(void);
3664 +extern void blast_dcache(void);
3665 +extern void blast_icache(void);
3666 +
3667 +/* uart output */
3668 +extern void putc(int c);
3669 +
3670 +/* lib functions */
3671 +extern int printf(const char *fmt, ...);
3672 +extern int sprintf(char *buf, const char *fmt, ...);
3673 +extern int strcmp(const char *s1, const char *s2);
3674 +extern int strncmp(const char *s1, const char *s2, uint n);
3675 +extern char *strcpy(char *dest, const char *src);
3676 +extern char *strncpy(char *dest, const char *src, uint n);
3677 +extern uint strlen(const char *s);
3678 +extern char *strchr(const char *str,int c);
3679 +extern char *strrchr(const char *str, int c);
3680 +extern char *strcat(char *d, const char *s);
3681 +extern void *memset(void *dest, int c, uint n);
3682 +extern void *memcpy(void *dest, const void *src, uint n);
3683 +extern int memcmp(const void *s1, const void *s2, uint n);
3684 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3685 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3686 +#define bzero(b, len) memset((b), '\0', (len))
3687 +
3688 +/* assert & debugging */
3689 +#define ASSERT(exp) do {} while (0)
3690 +
3691 +/* PCMCIA attribute space access macros */
3692 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3693 + ASSERT(0)
3694 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3695 + ASSERT(0)
3696 +
3697 +/* PCI configuration space access macros */
3698 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3699 + (offset == 8 ? 0 : 0xffffffff)
3700 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3701 + do {} while (0)
3702 +
3703 +/* register access macros */
3704 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3705 +#define rreg32(r) (*(volatile uint32*)(r))
3706 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3707 +#define rreg16(r) (*(volatile uint16*)(r))
3708 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3709 +#define rreg8(r) (*(volatile uint8*)(r))
3710 +#define R_REG(r) ({ \
3711 + __typeof(*(r)) __osl_v; \
3712 + switch (sizeof(*(r))) { \
3713 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3714 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3715 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3716 + } \
3717 + __osl_v; \
3718 +})
3719 +#define W_REG(r, v) do { \
3720 + switch (sizeof(*(r))) { \
3721 + case sizeof(uint8): wreg8((r), (v)); break; \
3722 + case sizeof(uint16): wreg16((r), (v)); break; \
3723 + case sizeof(uint32): wreg32((r), (v)); break; \
3724 + } \
3725 +} while (0)
3726 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3727 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3728 +
3729 +/* general purpose memory allocation */
3730 +#define MALLOC(osh, size) malloc(size)
3731 +#define MFREE(osh, addr, size) free(addr)
3732 +#define MALLOCED(osh) 0
3733 +#define MALLOC_FAILED(osh) 0
3734 +#define MALLOC_DUMP(osh, buf, sz)
3735 +extern int free(void *ptr);
3736 +extern void *malloc(uint size);
3737 +
3738 +/* uncached virtual address */
3739 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3740 +
3741 +/* host/bus architecture-specific address byte swap */
3742 +#define BUS_SWAP32(v) (v)
3743 +
3744 +/* microsecond delay */
3745 +#define OSL_DELAY(usec) udelay(usec)
3746 +extern void udelay(uint32 usec);
3747 +
3748 +/* map/unmap physical to virtual I/O */
3749 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3750 +#define REG_UNMAP(va) do {} while (0)
3751 +
3752 +/* dereference an address that may cause a bus exception */
3753 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3754 +
3755 +/* Misc stubs */
3756 +#define osl_attach(pdev) (pdev)
3757 +#define osl_detach(osh)
3758 +extern void *osl_init(void);
3759 +extern int getintvar(char *vars, char *name);
3760 +
3761 +#endif /* _min_osl_h_ */
3762 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
3763 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3764 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-08-26 13:44:34.288395168 +0200
3765 @@ -0,0 +1,524 @@
3766 +/*
3767 + * HND Run Time Environment for standalone MIPS programs.
3768 + *
3769 + * Copyright 2005, Broadcom Corporation
3770 + * All Rights Reserved.
3771 + *
3772 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3773 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3774 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3775 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3776 + *
3777 + * $Id$
3778 + */
3779 +
3780 +#ifndef _MISPINC_H
3781 +#define _MISPINC_H
3782 +
3783 +
3784 +/* MIPS defines */
3785 +
3786 +#ifdef _LANGUAGE_ASSEMBLY
3787 +
3788 +/*
3789 + * Symbolic register names for 32 bit ABI
3790 + */
3791 +#define zero $0 /* wired zero */
3792 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3793 +#define v0 $2 /* return value */
3794 +#define v1 $3
3795 +#define a0 $4 /* argument registers */
3796 +#define a1 $5
3797 +#define a2 $6
3798 +#define a3 $7
3799 +#define t0 $8 /* caller saved */
3800 +#define t1 $9
3801 +#define t2 $10
3802 +#define t3 $11
3803 +#define t4 $12
3804 +#define t5 $13
3805 +#define t6 $14
3806 +#define t7 $15
3807 +#define s0 $16 /* callee saved */
3808 +#define s1 $17
3809 +#define s2 $18
3810 +#define s3 $19
3811 +#define s4 $20
3812 +#define s5 $21
3813 +#define s6 $22
3814 +#define s7 $23
3815 +#define t8 $24 /* caller saved */
3816 +#define t9 $25
3817 +#define jp $25 /* PIC jump register */
3818 +#define k0 $26 /* kernel scratch */
3819 +#define k1 $27
3820 +#define gp $28 /* global pointer */
3821 +#define sp $29 /* stack pointer */
3822 +#define fp $30 /* frame pointer */
3823 +#define s8 $30 /* same like fp! */
3824 +#define ra $31 /* return address */
3825 +
3826 +
3827 +/* *********************************************************************
3828 + * CP0 Registers
3829 + ********************************************************************* */
3830 +
3831 +#define C0_INX $0
3832 +#define C0_RAND $1
3833 +#define C0_TLBLO0 $2
3834 +#define C0_TLBLO C0_TLBLO0
3835 +#define C0_TLBLO1 $3
3836 +#define C0_CTEXT $4
3837 +#define C0_PGMASK $5
3838 +#define C0_WIRED $6
3839 +#define C0_BADVADDR $8
3840 +#define C0_COUNT $9
3841 +#define C0_TLBHI $10
3842 +#define C0_COMPARE $11
3843 +#define C0_SR $12
3844 +#define C0_STATUS C0_SR
3845 +#define C0_CAUSE $13
3846 +#define C0_EPC $14
3847 +#define C0_PRID $15
3848 +#define C0_CONFIG $16
3849 +#define C0_LLADDR $17
3850 +#define C0_WATCHLO $18
3851 +#define C0_WATCHHI $19
3852 +#define C0_XCTEXT $20
3853 +#define C0_DIAGNOSTIC $22
3854 +#define C0_BROADCOM C0_DIAGNOSTIC
3855 +#define C0_ECC $26
3856 +#define C0_CACHEERR $27
3857 +#define C0_TAGLO $28
3858 +#define C0_TAGHI $29
3859 +#define C0_ERREPC $30
3860 +#define C0_DESAVE $31
3861 +
3862 +/*
3863 + * LEAF - declare leaf routine
3864 + */
3865 +#define LEAF(symbol) \
3866 + .globl symbol; \
3867 + .align 2; \
3868 + .type symbol,@function; \
3869 + .ent symbol,0; \
3870 +symbol: .frame sp,0,ra
3871 +
3872 +/*
3873 + * END - mark end of function
3874 + */
3875 +#define END(function) \
3876 + .end function; \
3877 + .size function,.-function
3878 +
3879 +#define _ULCAST_
3880 +
3881 +#else
3882 +
3883 +/*
3884 + * The following macros are especially useful for __asm__
3885 + * inline assembler.
3886 + */
3887 +#ifndef __STR
3888 +#define __STR(x) #x
3889 +#endif
3890 +#ifndef STR
3891 +#define STR(x) __STR(x)
3892 +#endif
3893 +
3894 +#define _ULCAST_ (unsigned long)
3895 +
3896 +
3897 +/* *********************************************************************
3898 + * CP0 Registers
3899 + ********************************************************************* */
3900 +
3901 +#define C0_INX 0 /* CP0: TLB Index */
3902 +#define C0_RAND 1 /* CP0: TLB Random */
3903 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3904 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3905 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3906 +#define C0_CTEXT 4 /* CP0: Context */
3907 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3908 +#define C0_WIRED 6 /* CP0: TLB Wired */
3909 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3910 +#define C0_COUNT 9 /* CP0: Count */
3911 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3912 +#define C0_COMPARE 11 /* CP0: Compare */
3913 +#define C0_SR 12 /* CP0: Processor Status */
3914 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3915 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3916 +#define C0_EPC 14 /* CP0: Exception PC */
3917 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3918 +#define C0_CONFIG 16 /* CP0: Config */
3919 +#define C0_LLADDR 17 /* CP0: LLAddr */
3920 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3921 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3922 +#define C0_XCTEXT 20 /* CP0: XContext */
3923 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3924 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3925 +#define C0_ECC 26 /* CP0: ECC */
3926 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3927 +#define C0_TAGLO 28 /* CP0: TagLo */
3928 +#define C0_TAGHI 29 /* CP0: TagHi */
3929 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3930 +#define C0_DESAVE 31 /* CP0: DebugSave */
3931 +
3932 +#endif /* _LANGUAGE_ASSEMBLY */
3933 +
3934 +/*
3935 + * Memory segments (32bit kernel mode addresses)
3936 + */
3937 +#undef KUSEG
3938 +#undef KSEG0
3939 +#undef KSEG1
3940 +#undef KSEG2
3941 +#undef KSEG3
3942 +#define KUSEG 0x00000000
3943 +#define KSEG0 0x80000000
3944 +#define KSEG1 0xa0000000
3945 +#define KSEG2 0xc0000000
3946 +#define KSEG3 0xe0000000
3947 +#define PHYSADDR_MASK 0x1fffffff
3948 +
3949 +/*
3950 + * Map an address to a certain kernel segment
3951 + */
3952 +#undef PHYSADDR
3953 +#undef KSEG0ADDR
3954 +#undef KSEG1ADDR
3955 +#undef KSEG2ADDR
3956 +#undef KSEG3ADDR
3957 +
3958 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3959 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3960 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3961 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3962 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3963 +
3964 +
3965 +#ifndef Index_Invalidate_I
3966 +/*
3967 + * Cache Operations
3968 + */
3969 +#define Index_Invalidate_I 0x00
3970 +#define Index_Writeback_Inv_D 0x01
3971 +#define Index_Invalidate_SI 0x02
3972 +#define Index_Writeback_Inv_SD 0x03
3973 +#define Index_Load_Tag_I 0x04
3974 +#define Index_Load_Tag_D 0x05
3975 +#define Index_Load_Tag_SI 0x06
3976 +#define Index_Load_Tag_SD 0x07
3977 +#define Index_Store_Tag_I 0x08
3978 +#define Index_Store_Tag_D 0x09
3979 +#define Index_Store_Tag_SI 0x0A
3980 +#define Index_Store_Tag_SD 0x0B
3981 +#define Create_Dirty_Excl_D 0x0d
3982 +#define Create_Dirty_Excl_SD 0x0f
3983 +#define Hit_Invalidate_I 0x10
3984 +#define Hit_Invalidate_D 0x11
3985 +#define Hit_Invalidate_SI 0x12
3986 +#define Hit_Invalidate_SD 0x13
3987 +#define Fill_I 0x14
3988 +#define Hit_Writeback_Inv_D 0x15
3989 + /* 0x16 is unused */
3990 +#define Hit_Writeback_Inv_SD 0x17
3991 +#define R5K_Page_Invalidate_S 0x17
3992 +#define Hit_Writeback_I 0x18
3993 +#define Hit_Writeback_D 0x19
3994 + /* 0x1a is unused */
3995 +#define Hit_Writeback_SD 0x1b
3996 + /* 0x1c is unused */
3997 + /* 0x1e is unused */
3998 +#define Hit_Set_Virtual_SI 0x1e
3999 +#define Hit_Set_Virtual_SD 0x1f
4000 +#endif
4001 +
4002 +#ifndef _LANGUAGE_ASSEMBLY
4003 +
4004 +/*
4005 + * Macros to access the system control coprocessor
4006 + */
4007 +
4008 +#define MFC0(source, sel) \
4009 +({ \
4010 + int __res; \
4011 + __asm__ __volatile__( \
4012 + ".set\tnoreorder\n\t" \
4013 + ".set\tnoat\n\t" \
4014 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
4015 + "move\t%0,$1\n\t" \
4016 + ".set\tat\n\t" \
4017 + ".set\treorder" \
4018 + :"=r" (__res) \
4019 + : \
4020 + :"$1"); \
4021 + __res; \
4022 +})
4023 +
4024 +#define MTC0(source, sel, value) \
4025 +do { \
4026 + __asm__ __volatile__( \
4027 + ".set\tnoreorder\n\t" \
4028 + ".set\tnoat\n\t" \
4029 + "move\t$1,%z0\n\t" \
4030 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
4031 + ".set\tat\n\t" \
4032 + ".set\treorder" \
4033 + : \
4034 + :"jr" (value) \
4035 + :"$1"); \
4036 +} while (0)
4037 +
4038 +#define get_c0_count() \
4039 +({ \
4040 + int __res; \
4041 + __asm__ __volatile__( \
4042 + ".set\tnoreorder\n\t" \
4043 + ".set\tnoat\n\t" \
4044 + "mfc0\t%0,$9\n\t" \
4045 + ".set\tat\n\t" \
4046 + ".set\treorder" \
4047 + :"=r" (__res)); \
4048 + __res; \
4049 +})
4050 +
4051 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
4052 +{
4053 + uint lsz, sets, ways;
4054 +
4055 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4056 + if ((lsz = ((config1 >> 19) & 7)))
4057 + lsz = 2 << lsz;
4058 + sets = 64 << ((config1 >> 22) & 7);
4059 + ways = 1 + ((config1 >> 16) & 7);
4060 + *size = lsz * sets * ways;
4061 + *lsize = lsz;
4062 +}
4063 +
4064 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
4065 +{
4066 + uint lsz, sets, ways;
4067 +
4068 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
4069 + if ((lsz = ((config1 >> 10) & 7)))
4070 + lsz = 2 << lsz;
4071 + sets = 64 << ((config1 >> 13) & 7);
4072 + ways = 1 + ((config1 >> 7) & 7);
4073 + *size = lsz * sets * ways;
4074 + *lsize = lsz;
4075 +}
4076 +
4077 +#define cache_unroll(base,op) \
4078 + __asm__ __volatile__(" \
4079 + .set noreorder; \
4080 + .set mips3; \
4081 + cache %1, (%0); \
4082 + .set mips0; \
4083 + .set reorder" \
4084 + : \
4085 + : "r" (base), \
4086 + "i" (op));
4087 +
4088 +#endif /* !_LANGUAGE_ASSEMBLY */
4089 +
4090 +
4091 +/*
4092 + * R4x00 interrupt enable / cause bits
4093 + */
4094 +#undef IE_SW0
4095 +#undef IE_SW1
4096 +#undef IE_IRQ0
4097 +#undef IE_IRQ1
4098 +#undef IE_IRQ2
4099 +#undef IE_IRQ3
4100 +#undef IE_IRQ4
4101 +#undef IE_IRQ5
4102 +#define IE_SW0 (1<< 8)
4103 +#define IE_SW1 (1<< 9)
4104 +#define IE_IRQ0 (1<<10)
4105 +#define IE_IRQ1 (1<<11)
4106 +#define IE_IRQ2 (1<<12)
4107 +#define IE_IRQ3 (1<<13)
4108 +#define IE_IRQ4 (1<<14)
4109 +#define IE_IRQ5 (1<<15)
4110 +
4111 +/*
4112 + * Bitfields in the mips32 cp0 status register
4113 + */
4114 +#define ST0_IE 0x00000001
4115 +#define ST0_EXL 0x00000002
4116 +#define ST0_ERL 0x00000004
4117 +/* already defined
4118 +#define ST0_UM 0x00000010
4119 +#define ST0_SWINT0 0x00000100
4120 +#define ST0_SWINT1 0x00000200
4121 +*/
4122 +#define ST0_HWINT0 0x00000400
4123 +#define ST0_HWINT1 0x00000800
4124 +#define ST0_HWINT2 0x00001000
4125 +#define ST0_HWINT3 0x00002000
4126 +#define ST0_HWINT4 0x00004000
4127 +#define ST0_HWINT5 0x00008000
4128 +#define ST0_IM 0x0000ff00
4129 +#define ST0_NMI 0x00080000
4130 +#define ST0_SR 0x00100000
4131 +#define ST0_TS 0x00200000
4132 +#define ST0_BEV 0x00400000
4133 +#define ST0_RE 0x02000000
4134 +#define ST0_RP 0x08000000
4135 +#define ST0_CU 0xf0000000
4136 +#define ST0_CU0 0x10000000
4137 +#define ST0_CU1 0x20000000
4138 +#define ST0_CU2 0x40000000
4139 +#define ST0_CU3 0x80000000
4140 +
4141 +
4142 +/*
4143 + * Bitfields in the mips32 cp0 cause register
4144 + */
4145 +#define C_EXC 0x0000007c
4146 +#define C_EXC_SHIFT 2
4147 +#define C_INT 0x0000ff00
4148 +#define C_INT_SHIFT 8
4149 +/* already defined
4150 +#define C_SW0 0x00000100
4151 +#define C_SW1 0x00000200
4152 +#define C_IRQ0 0x00000400
4153 +#define C_IRQ1 0x00000800
4154 +#define C_IRQ2 0x00001000
4155 +#define C_IRQ3 0x00002000
4156 +#define C_IRQ4 0x00004000
4157 +#define C_IRQ5 0x00008000
4158 +*/
4159 +#define C_WP 0x00400000
4160 +#define C_IV 0x00800000
4161 +#define C_CE 0x30000000
4162 +#define C_CE_SHIFT 28
4163 +#define C_BD 0x80000000
4164 +
4165 +/* Values in C_EXC */
4166 +#define EXC_INT 0
4167 +#define EXC_TLBM 1
4168 +#define EXC_TLBL 2
4169 +#define EXC_TLBS 3
4170 +#define EXC_AEL 4
4171 +#define EXC_AES 5
4172 +#define EXC_IBE 6
4173 +#define EXC_DBE 7
4174 +#define EXC_SYS 8
4175 +#define EXC_BPT 9
4176 +#define EXC_RI 10
4177 +#define EXC_CU 11
4178 +#define EXC_OV 12
4179 +#define EXC_TR 13
4180 +#define EXC_WATCH 23
4181 +#define EXC_MCHK 24
4182 +
4183 +
4184 +/*
4185 + * Bits in the cp0 config register.
4186 + */
4187 +#define CONF_CM_CACHABLE_NO_WA 0
4188 +#define CONF_CM_CACHABLE_WA 1
4189 +#define CONF_CM_UNCACHED 2
4190 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4191 +#define CONF_CM_CACHABLE_CE 4
4192 +#define CONF_CM_CACHABLE_COW 5
4193 +#define CONF_CM_CACHABLE_CUW 6
4194 +#define CONF_CM_CACHABLE_ACCELERATED 7
4195 +#define CONF_CM_CMASK 7
4196 +#define CONF_CU (_ULCAST_(1) << 3)
4197 +#define CONF_DB (_ULCAST_(1) << 4)
4198 +#define CONF_IB (_ULCAST_(1) << 5)
4199 +#define CONF_SE (_ULCAST_(1) << 12)
4200 +#define CONF_SC (_ULCAST_(1) << 17)
4201 +#define CONF_AC (_ULCAST_(1) << 23)
4202 +#define CONF_HALT (_ULCAST_(1) << 25)
4203 +
4204 +
4205 +/*
4206 + * Bits in the cp0 config register select 1.
4207 + */
4208 +#define CONF1_FP 0x00000001 /* FPU present */
4209 +#define CONF1_EP 0x00000002 /* EJTAG present */
4210 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4211 +#define CONF1_WR 0x00000008 /* Watch registers present */
4212 +#define CONF1_PC 0x00000010 /* Performance counters present */
4213 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4214 +#define CONF1_DA_MASK 0x00000380
4215 +#define CONF1_DA_BASE 1
4216 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4217 +#define CONF1_DL_MASK 0x00001c00
4218 +#define CONF1_DL_BASE 2
4219 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4220 +#define CONF1_DS_MASK 0x0000e000
4221 +#define CONF1_DS_BASE 64
4222 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4223 +#define CONF1_IA_MASK 0x00070000
4224 +#define CONF1_IA_BASE 1
4225 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4226 +#define CONF1_IL_MASK 0x00380000
4227 +#define CONF1_IL_BASE 2
4228 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4229 +#define CONF1_IS_MASK 0x01c00000
4230 +#define CONF1_IS_BASE 64
4231 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4232 +#define CONF1_MS_SHIFT 25
4233 +
4234 +/* PRID register */
4235 +#define PRID_COPT_MASK 0xff000000
4236 +#define PRID_COMP_MASK 0x00ff0000
4237 +#define PRID_IMP_MASK 0x0000ff00
4238 +#define PRID_REV_MASK 0x000000ff
4239 +
4240 +#define PRID_COMP_LEGACY 0x000000
4241 +#define PRID_COMP_MIPS 0x010000
4242 +#define PRID_COMP_BROADCOM 0x020000
4243 +#define PRID_COMP_ALCHEMY 0x030000
4244 +#define PRID_COMP_SIBYTE 0x040000
4245 +#define PRID_IMP_BCM4710 0x4000
4246 +#define PRID_IMP_BCM3302 0x9000
4247 +#define PRID_IMP_BCM3303 0x9100
4248 +#define PRID_IMP_BCM3303 0x9100
4249 +
4250 +#define PRID_IMP_UNKNOWN 0xff00
4251 +
4252 +#define BCM330X(id) \
4253 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4254 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4255 +
4256 +/* Bits in C0_BROADCOM */
4257 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4258 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4259 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4260 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4261 +
4262 +/* PreFetch Cache aka Read Ahead Cache */
4263 +
4264 +#define PFC_CR0 0xff400000 /* control reg 0 */
4265 +#define PFC_CR1 0xff400004 /* control reg 1 */
4266 +
4267 +/*
4268 + * These are the UART port assignments, expressed as offsets from the base
4269 + * register. These assignments should hold for any serial port based on
4270 + * a 8250, 16450, or 16550(A).
4271 + */
4272 +
4273 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4274 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4275 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4276 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4277 +#define UART_LCR 3 /* Out: Line Control Register */
4278 +#define UART_MCR 4 /* Out: Modem Control Register */
4279 +#define UART_LSR 5 /* In: Line Status Register */
4280 +#define UART_MSR 6 /* In: Modem Status Register */
4281 +#define UART_SCR 7 /* I/O: Scratch Register */
4282 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4283 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4284 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4285 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4286 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4287 +
4288 +
4289 +#endif /* _MISPINC_H */
4290 diff -urN linux.old/arch/mips/bcm947xx/include/nvports.h linux.dev/arch/mips/bcm947xx/include/nvports.h
4291 --- linux.old/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4292 +++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-08-26 13:44:34.291394712 +0200
4293 @@ -0,0 +1,55 @@
4294 +/*
4295 + * BCM53xx RoboSwitch utility functions
4296 + *
4297 + * Copyright (C) 2002 Broadcom Corporation
4298 + * $Id$
4299 + */
4300 +
4301 +#ifndef _nvports_h_
4302 +#define _nvports_h_
4303 +
4304 +#define uint32 unsigned long
4305 +#define uint16 unsigned short
4306 +#define uint unsigned int
4307 +#define uint8 unsigned char
4308 +#define uint64 unsigned long long
4309 +
4310 +enum FORCE_PORT {
4311 + FORCE_OFF,
4312 + FORCE_10H,
4313 + FORCE_10F,
4314 + FORCE_100H,
4315 + FORCE_100F,
4316 + FORCE_DOWN,
4317 + POWER_OFF
4318 +};
4319 +
4320 +typedef struct _PORT_ATTRIBS
4321 +{
4322 + uint autoneg;
4323 + uint force;
4324 + uint native;
4325 +} PORT_ATTRIBS;
4326 +
4327 +extern uint
4328 +nvExistsPortAttrib(char *attrib, uint portno);
4329 +
4330 +extern int
4331 +nvExistsAnyForcePortAttrib(uint portno);
4332 +
4333 +extern void
4334 +nvSetPortAttrib(char *attrib, uint portno);
4335 +
4336 +extern void
4337 +nvUnsetPortAttrib(char *attrib, uint portno);
4338 +
4339 +extern void
4340 +nvUnsetAllForcePortAttrib(uint portno);
4341 +
4342 +extern PORT_ATTRIBS
4343 +nvGetSwitchPortAttribs(uint portno);
4344 +
4345 +#endif /* _nvports_h_ */
4346 +
4347 +
4348 +
4349 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
4350 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4351 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-08-26 13:44:34.291394712 +0200
4352 @@ -0,0 +1,39 @@
4353 +/*
4354 + * OS Independent Layer
4355 + *
4356 + * Copyright 2005, Broadcom Corporation
4357 + * All Rights Reserved.
4358 + *
4359 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4360 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4361 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4362 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4363 + * $Id$
4364 + */
4365 +
4366 +#ifndef _osl_h_
4367 +#define _osl_h_
4368 +
4369 +#if defined(linux)
4370 +#include <linux_osl.h>
4371 +#elif defined(NDIS)
4372 +#include <ndis_osl.h>
4373 +#elif defined(_CFE_)
4374 +#include <cfe_osl.h>
4375 +#elif defined(_HNDRTE_)
4376 +#include <hndrte_osl.h>
4377 +#elif defined(_MINOSL_)
4378 +#include <min_osl.h>
4379 +#elif PMON
4380 +#include <pmon_osl.h>
4381 +#elif defined(MACOSX)
4382 +#include <macosx_osl.h>
4383 +#else
4384 +#error "Unsupported OSL requested"
4385 +#endif
4386 +
4387 +/* handy */
4388 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4389 +#define MAXPRIO 7 /* 0-7 */
4390 +
4391 +#endif /* _osl_h_ */
4392 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
4393 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4394 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-08-26 13:44:34.292394560 +0200
4395 @@ -0,0 +1,369 @@
4396 +/*
4397 + * pcicfg.h: PCI configuration constants and structures.
4398 + *
4399 + * Copyright 2005, Broadcom Corporation
4400 + * All Rights Reserved.
4401 + *
4402 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4403 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4404 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4405 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4406 + *
4407 + * $Id$
4408 + */
4409 +
4410 +#ifndef _h_pci_
4411 +#define _h_pci_
4412 +
4413 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4414 +#ifndef PCI_MAX_BUS
4415 +#define PCI_MAX_BUS 0x100
4416 +#endif
4417 +#ifndef PCI_MAX_DEVICES
4418 +#define PCI_MAX_DEVICES 0x20
4419 +#endif
4420 +#ifndef PCI_MAX_FUNCTION
4421 +#define PCI_MAX_FUNCTION 0x8
4422 +#endif
4423 +
4424 +#ifndef PCI_INVALID_VENDORID
4425 +#define PCI_INVALID_VENDORID 0xffff
4426 +#endif
4427 +#ifndef PCI_INVALID_DEVICEID
4428 +#define PCI_INVALID_DEVICEID 0xffff
4429 +#endif
4430 +
4431 +
4432 +/* Convert between bus-slot-function-register and config addresses */
4433 +
4434 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4435 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4436 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4437 +#define PCICFG_OFF_SHIFT 0 /* Bus shift */
4438 +
4439 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4440 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4441 +#define PCICFG_FUN_MASK 7 /* Function mask */
4442 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4443 +
4444 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4445 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4446 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4447 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4448 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4449 +
4450 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4451 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4452 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4453 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4454 +
4455 +
4456 +/* The actual config space */
4457 +
4458 +#define PCI_BAR_MAX 6
4459 +
4460 +#define PCI_ROM_BAR 8
4461 +
4462 +#define PCR_RSVDA_MAX 2
4463 +
4464 +typedef struct _pci_config_regs {
4465 + unsigned short vendor;
4466 + unsigned short device;
4467 + unsigned short command;
4468 + unsigned short status;
4469 + unsigned char rev_id;
4470 + unsigned char prog_if;
4471 + unsigned char sub_class;
4472 + unsigned char base_class;
4473 + unsigned char cache_line_size;
4474 + unsigned char latency_timer;
4475 + unsigned char header_type;
4476 + unsigned char bist;
4477 + unsigned long base[PCI_BAR_MAX];
4478 + unsigned long cardbus_cis;
4479 + unsigned short subsys_vendor;
4480 + unsigned short subsys_id;
4481 + unsigned long baserom;
4482 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4483 + unsigned char int_line;
4484 + unsigned char int_pin;
4485 + unsigned char min_gnt;
4486 + unsigned char max_lat;
4487 + unsigned char dev_dep[192];
4488 +} pci_config_regs;
4489 +
4490 +#define SZPCR (sizeof (pci_config_regs))
4491 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4492 +
4493 +/* A structure for the config registers is nice, but in most
4494 + * systems the config space is not memory mapped, so we need
4495 + * filed offsetts. :-(
4496 + */
4497 +#define PCI_CFG_VID 0
4498 +#define PCI_CFG_DID 2
4499 +#define PCI_CFG_CMD 4
4500 +#define PCI_CFG_STAT 6
4501 +#define PCI_CFG_REV 8
4502 +#define PCI_CFG_PROGIF 9
4503 +#define PCI_CFG_SUBCL 0xa
4504 +#define PCI_CFG_BASECL 0xb
4505 +#define PCI_CFG_CLSZ 0xc
4506 +#define PCI_CFG_LATTIM 0xd
4507 +#define PCI_CFG_HDR 0xe
4508 +#define PCI_CFG_BIST 0xf
4509 +#define PCI_CFG_BAR0 0x10
4510 +#define PCI_CFG_BAR1 0x14
4511 +#define PCI_CFG_BAR2 0x18
4512 +#define PCI_CFG_BAR3 0x1c
4513 +#define PCI_CFG_BAR4 0x20
4514 +#define PCI_CFG_BAR5 0x24
4515 +#define PCI_CFG_CIS 0x28
4516 +#define PCI_CFG_SVID 0x2c
4517 +#define PCI_CFG_SSID 0x2e
4518 +#define PCI_CFG_ROMBAR 0x30
4519 +#define PCI_CFG_INT 0x3c
4520 +#define PCI_CFG_PIN 0x3d
4521 +#define PCI_CFG_MINGNT 0x3e
4522 +#define PCI_CFG_MAXLAT 0x3f
4523 +
4524 +/* Classes and subclasses */
4525 +
4526 +typedef enum {
4527 + PCI_CLASS_OLD = 0,
4528 + PCI_CLASS_DASDI,
4529 + PCI_CLASS_NET,
4530 + PCI_CLASS_DISPLAY,
4531 + PCI_CLASS_MMEDIA,
4532 + PCI_CLASS_MEMORY,
4533 + PCI_CLASS_BRIDGE,
4534 + PCI_CLASS_COMM,
4535 + PCI_CLASS_BASE,
4536 + PCI_CLASS_INPUT,
4537 + PCI_CLASS_DOCK,
4538 + PCI_CLASS_CPU,
4539 + PCI_CLASS_SERIAL,
4540 + PCI_CLASS_INTELLIGENT = 0xe,
4541 + PCI_CLASS_SATELLITE,
4542 + PCI_CLASS_CRYPT,
4543 + PCI_CLASS_DSP,
4544 + PCI_CLASS_MAX
4545 +} pci_classes;
4546 +
4547 +typedef enum {
4548 + PCI_DASDI_SCSI,
4549 + PCI_DASDI_IDE,
4550 + PCI_DASDI_FLOPPY,
4551 + PCI_DASDI_IPI,
4552 + PCI_DASDI_RAID,
4553 + PCI_DASDI_OTHER = 0x80
4554 +} pci_dasdi_subclasses;
4555 +
4556 +typedef enum {
4557 + PCI_NET_ETHER,
4558 + PCI_NET_TOKEN,
4559 + PCI_NET_FDDI,
4560 + PCI_NET_ATM,
4561 + PCI_NET_OTHER = 0x80
4562 +} pci_net_subclasses;
4563 +
4564 +typedef enum {
4565 + PCI_DISPLAY_VGA,
4566 + PCI_DISPLAY_XGA,
4567 + PCI_DISPLAY_3D,
4568 + PCI_DISPLAY_OTHER = 0x80
4569 +} pci_display_subclasses;
4570 +
4571 +typedef enum {
4572 + PCI_MMEDIA_VIDEO,
4573 + PCI_MMEDIA_AUDIO,
4574 + PCI_MMEDIA_PHONE,
4575 + PCI_MEDIA_OTHER = 0x80
4576 +} pci_mmedia_subclasses;
4577 +
4578 +typedef enum {
4579 + PCI_MEMORY_RAM,
4580 + PCI_MEMORY_FLASH,
4581 + PCI_MEMORY_OTHER = 0x80
4582 +} pci_memory_subclasses;
4583 +
4584 +typedef enum {
4585 + PCI_BRIDGE_HOST,
4586 + PCI_BRIDGE_ISA,
4587 + PCI_BRIDGE_EISA,
4588 + PCI_BRIDGE_MC,
4589 + PCI_BRIDGE_PCI,
4590 + PCI_BRIDGE_PCMCIA,
4591 + PCI_BRIDGE_NUBUS,
4592 + PCI_BRIDGE_CARDBUS,
4593 + PCI_BRIDGE_RACEWAY,
4594 + PCI_BRIDGE_OTHER = 0x80
4595 +} pci_bridge_subclasses;
4596 +
4597 +typedef enum {
4598 + PCI_COMM_UART,
4599 + PCI_COMM_PARALLEL,
4600 + PCI_COMM_MULTIUART,
4601 + PCI_COMM_MODEM,
4602 + PCI_COMM_OTHER = 0x80
4603 +} pci_comm_subclasses;
4604 +
4605 +typedef enum {
4606 + PCI_BASE_PIC,
4607 + PCI_BASE_DMA,
4608 + PCI_BASE_TIMER,
4609 + PCI_BASE_RTC,
4610 + PCI_BASE_PCI_HOTPLUG,
4611 + PCI_BASE_OTHER = 0x80
4612 +} pci_base_subclasses;
4613 +
4614 +typedef enum {
4615 + PCI_INPUT_KBD,
4616 + PCI_INPUT_PEN,
4617 + PCI_INPUT_MOUSE,
4618 + PCI_INPUT_SCANNER,
4619 + PCI_INPUT_GAMEPORT,
4620 + PCI_INPUT_OTHER = 0x80
4621 +} pci_input_subclasses;
4622 +
4623 +typedef enum {
4624 + PCI_DOCK_GENERIC,
4625 + PCI_DOCK_OTHER = 0x80
4626 +} pci_dock_subclasses;
4627 +
4628 +typedef enum {
4629 + PCI_CPU_386,
4630 + PCI_CPU_486,
4631 + PCI_CPU_PENTIUM,
4632 + PCI_CPU_ALPHA = 0x10,
4633 + PCI_CPU_POWERPC = 0x20,
4634 + PCI_CPU_MIPS = 0x30,
4635 + PCI_CPU_COPROC = 0x40,
4636 + PCI_CPU_OTHER = 0x80
4637 +} pci_cpu_subclasses;
4638 +
4639 +typedef enum {
4640 + PCI_SERIAL_IEEE1394,
4641 + PCI_SERIAL_ACCESS,
4642 + PCI_SERIAL_SSA,
4643 + PCI_SERIAL_USB,
4644 + PCI_SERIAL_FIBER,
4645 + PCI_SERIAL_SMBUS,
4646 + PCI_SERIAL_OTHER = 0x80
4647 +} pci_serial_subclasses;
4648 +
4649 +typedef enum {
4650 + PCI_INTELLIGENT_I2O,
4651 +} pci_intelligent_subclasses;
4652 +
4653 +typedef enum {
4654 + PCI_SATELLITE_TV,
4655 + PCI_SATELLITE_AUDIO,
4656 + PCI_SATELLITE_VOICE,
4657 + PCI_SATELLITE_DATA,
4658 + PCI_SATELLITE_OTHER = 0x80
4659 +} pci_satellite_subclasses;
4660 +
4661 +typedef enum {
4662 + PCI_CRYPT_NETWORK,
4663 + PCI_CRYPT_ENTERTAINMENT,
4664 + PCI_CRYPT_OTHER = 0x80
4665 +} pci_crypt_subclasses;
4666 +
4667 +typedef enum {
4668 + PCI_DSP_DPIO,
4669 + PCI_DSP_OTHER = 0x80
4670 +} pci_dsp_subclasses;
4671 +
4672 +/* Header types */
4673 +typedef enum {
4674 + PCI_HEADER_NORMAL,
4675 + PCI_HEADER_BRIDGE,
4676 + PCI_HEADER_CARDBUS
4677 +} pci_header_types;
4678 +
4679 +
4680 +/* Overlay for a PCI-to-PCI bridge */
4681 +
4682 +#define PPB_RSVDA_MAX 2
4683 +#define PPB_RSVDD_MAX 8
4684 +
4685 +typedef struct _ppb_config_regs {
4686 + unsigned short vendor;
4687 + unsigned short device;
4688 + unsigned short command;
4689 + unsigned short status;
4690 + unsigned char rev_id;
4691 + unsigned char prog_if;
4692 + unsigned char sub_class;
4693 + unsigned char base_class;
4694 + unsigned char cache_line_size;
4695 + unsigned char latency_timer;
4696 + unsigned char header_type;
4697 + unsigned char bist;
4698 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4699 + unsigned char prim_bus;
4700 + unsigned char sec_bus;
4701 + unsigned char sub_bus;
4702 + unsigned char sec_lat;
4703 + unsigned char io_base;
4704 + unsigned char io_lim;
4705 + unsigned short sec_status;
4706 + unsigned short mem_base;
4707 + unsigned short mem_lim;
4708 + unsigned short pf_mem_base;
4709 + unsigned short pf_mem_lim;
4710 + unsigned long pf_mem_base_hi;
4711 + unsigned long pf_mem_lim_hi;
4712 + unsigned short io_base_hi;
4713 + unsigned short io_lim_hi;
4714 + unsigned short subsys_vendor;
4715 + unsigned short subsys_id;
4716 + unsigned long rsvd_b;
4717 + unsigned char rsvd_c;
4718 + unsigned char int_pin;
4719 + unsigned short bridge_ctrl;
4720 + unsigned char chip_ctrl;
4721 + unsigned char diag_ctrl;
4722 + unsigned short arb_ctrl;
4723 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4724 + unsigned char dev_dep[192];
4725 +} ppb_config_regs;
4726 +
4727 +/* Eveything below is BRCM HND proprietary */
4728 +
4729 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4730 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4731 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4732 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4733 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4734 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4735 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4736 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4737 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4738 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4739 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4740 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4741 +
4742 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4743 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4744 +
4745 +/* PCI_INT_STATUS */
4746 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4747 +
4748 +/* PCI_INT_MASK */
4749 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4750 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4751 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4752 +
4753 +/* PCI_SPROM_CONTROL */
4754 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4755 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4756 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4757 +
4758 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4759 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4760 +
4761 +/* PCI_CFG_CMD_STAT */
4762 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4763 +
4764 +#endif
4765 diff -urN linux.old/arch/mips/bcm947xx/include/pmon_osl.h linux.dev/arch/mips/bcm947xx/include/pmon_osl.h
4766 --- linux.old/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4767 +++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-08-26 13:44:34.293394408 +0200
4768 @@ -0,0 +1,126 @@
4769 +/*
4770 + * MIPS PMON boot loader OS Abstraction Layer.
4771 + *
4772 + * Copyright 2005, Broadcom Corporation
4773 + * All Rights Reserved.
4774 + *
4775 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
4776 + * the contents of this file may not be disclosed to third parties, copied
4777 + * or duplicated in any form, in whole or in part, without the prior
4778 + * written permission of Broadcom Corporation.
4779 + * $Id$
4780 + */
4781 +
4782 +#ifndef _pmon_osl_h_
4783 +#define _pmon_osl_h_
4784 +
4785 +#include <typedefs.h>
4786 +#include <mips.h>
4787 +#include <string.h>
4788 +#include <utypes.h>
4789 +
4790 +extern int printf(char *fmt,...);
4791 +extern int sprintf(char *dst,char *fmt,...);
4792 +
4793 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
4794 +#define REG_MAP(pa, size) phy2k1((pa))
4795 +#define REG_UNMAP(va) /* nop */
4796 +
4797 +/* Common macros */
4798 +
4799 +#define BUSPROBE(val, addr) ((val) = *(addr))
4800 +
4801 +#define ASSERT(exp)
4802 +
4803 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
4804 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
4805 +
4806 +/* kludge */
4807 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
4808 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
4809 +
4810 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
4811 +#define rreg32(r) (*(volatile uint32 *)(r))
4812 +#ifdef IL_BIGENDIAN
4813 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
4814 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
4815 +#else
4816 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
4817 +#define rreg16(r) (*(volatile uint16 *)(r))
4818 +#endif
4819 +
4820 +#include <memory.h>
4821 +#define bcopy(src, dst, len) memcpy(dst, src, len)
4822 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
4823 +#define bzero(b, len) memset(b, '\0', len)
4824 +
4825 +/* register access macros */
4826 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
4827 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
4828 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
4829 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
4830 +
4831 +#define R_SM(r) *(r)
4832 +#define W_SM(r, v) (*(r) = (v))
4833 +#define BZERO_SM(r, len) memset(r, '\0', len)
4834 +
4835 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
4836 +#define BUS_SWAP32(v) (v)
4837 +
4838 +#define OSL_DELAY(usec) delay_us(usec)
4839 +extern void delay_us(uint usec);
4840 +
4841 +#define OSL_GETCYCLES(x) ((x) = 0)
4842 +
4843 +#define osl_attach(pdev) (pdev)
4844 +#define osl_detach(osh)
4845 +
4846 +#define MALLOC(osh, size) malloc(size)
4847 +#define MFREE(osh, addr, size) free(addr)
4848 +#define MALLOCED(osh) (0)
4849 +#define MALLOC_DUMP(osh, buf, sz)
4850 +#define MALLOC_FAILED(osh)
4851 +extern void *malloc();
4852 +extern void free(void *addr);
4853 +
4854 +#define DMA_CONSISTENT_ALIGN sizeof (int)
4855 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
4856 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
4857 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
4858 +#define DMA_TX 0
4859 +#define DMA_RX 1
4860 +
4861 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
4862 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
4863 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
4864 +
4865 +struct lbuf {
4866 + struct lbuf *next; /* pointer to next lbuf on freelist */
4867 + uchar *buf; /* pointer to buffer */
4868 + uint len; /* nbytes of data */
4869 +};
4870 +
4871 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
4872 +#define PKTBUFSZ 2048
4873 +
4874 +/* packet primitives */
4875 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
4876 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
4877 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
4878 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
4879 +#define PKTHEADROOM(drv, lb) (0)
4880 +#define PKTTAILROOM(drv, lb) (0)
4881 +#define PKTNEXT(drv, lb) NULL
4882 +#define PKTSETNEXT(lb, x) ASSERT(0)
4883 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
4884 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
4885 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
4886 +#define PKTDUP(drv, lb) ASSERT(0)
4887 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
4888 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
4889 +#define PKTPRIO(lb) (0)
4890 +#define PKTSETPRIO(lb, x) do {} while (0)
4891 +extern void *et_pktget(void *drv, uint len, bool send);
4892 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
4893 +
4894 +#endif /* _pmon_osl_h_ */
4895 diff -urN linux.old/arch/mips/bcm947xx/include/proto/802.11.h linux.dev/arch/mips/bcm947xx/include/proto/802.11.h
4896 --- linux.old/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
4897 +++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-08-26 13:44:34.295394104 +0200
4898 @@ -0,0 +1,897 @@
4899 +/*
4900 + * Copyright 2005, Broadcom Corporation
4901 + * All Rights Reserved.
4902 + *
4903 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4904 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4905 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4906 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4907 + *
4908 + * Fundamental types and constants relating to 802.11
4909 + *
4910 + * $Id$
4911 + */
4912 +
4913 +#ifndef _802_11_H_
4914 +#define _802_11_H_
4915 +
4916 +#ifndef _TYPEDEFS_H_
4917 +#include <typedefs.h>
4918 +#endif
4919 +
4920 +#ifndef _NET_ETHERNET_H_
4921 +#include <proto/ethernet.h>
4922 +#endif
4923 +
4924 +#include <proto/wpa.h>
4925 +
4926 +
4927 +/* enable structure packing */
4928 +#if defined(__GNUC__)
4929 +#define PACKED __attribute__((packed))
4930 +#else
4931 +#pragma pack(1)
4932 +#define PACKED
4933 +#endif
4934 +
4935 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
4936 +
4937 +/* Generic 802.11 frame constants */
4938 +#define DOT11_A3_HDR_LEN 24
4939 +#define DOT11_A4_HDR_LEN 30
4940 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
4941 +#define DOT11_FCS_LEN 4
4942 +#define DOT11_ICV_LEN 4
4943 +#define DOT11_ICV_AES_LEN 8
4944 +#define DOT11_QOS_LEN 2
4945 +
4946 +#define DOT11_KEY_INDEX_SHIFT 6
4947 +#define DOT11_IV_LEN 4
4948 +#define DOT11_IV_TKIP_LEN 8
4949 +#define DOT11_IV_AES_OCB_LEN 4
4950 +#define DOT11_IV_AES_CCM_LEN 8
4951 +
4952 +/* Includes MIC */
4953 +#define DOT11_MAX_MPDU_BODY_LEN 2304
4954 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
4955 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
4956 + DOT11_QOS_LEN + \
4957 + DOT11_IV_AES_CCM_LEN + \
4958 + DOT11_MAX_MPDU_BODY_LEN + \
4959 + DOT11_ICV_LEN + \
4960 + DOT11_FCS_LEN)
4961 +
4962 +#define DOT11_MAX_SSID_LEN 32
4963 +
4964 +/* dot11RTSThreshold */
4965 +#define DOT11_DEFAULT_RTS_LEN 2347
4966 +#define DOT11_MAX_RTS_LEN 2347
4967 +
4968 +/* dot11FragmentationThreshold */
4969 +#define DOT11_MIN_FRAG_LEN 256
4970 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
4971 +#define DOT11_DEFAULT_FRAG_LEN 2346
4972 +
4973 +/* dot11BeaconPeriod */
4974 +#define DOT11_MIN_BEACON_PERIOD 1
4975 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
4976 +
4977 +/* dot11DTIMPeriod */
4978 +#define DOT11_MIN_DTIM_PERIOD 1
4979 +#define DOT11_MAX_DTIM_PERIOD 0xFF
4980 +
4981 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
4982 +#define DOT11_LLC_SNAP_HDR_LEN 8
4983 +#define DOT11_OUI_LEN 3
4984 +struct dot11_llc_snap_header {
4985 + uint8 dsap; /* always 0xAA */
4986 + uint8 ssap; /* always 0xAA */
4987 + uint8 ctl; /* always 0x03 */
4988 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
4989 + Bridge-Tunnel: 0x00 0x00 0xF8 */
4990 + uint16 type; /* ethertype */
4991 +} PACKED;
4992 +
4993 +/* RFC1042 header used by 802.11 per 802.1H */
4994 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
4995 +
4996 +/* Generic 802.11 MAC header */
4997 +/*
4998 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
4999 + * The fields are defined such that the shorter 1, 2, and 3
5000 + * address headers just use the first k fields.
5001 + */
5002 +struct dot11_header {
5003 + uint16 fc; /* frame control */
5004 + uint16 durid; /* duration/ID */
5005 + struct ether_addr a1; /* address 1 */
5006 + struct ether_addr a2; /* address 2 */
5007 + struct ether_addr a3; /* address 3 */
5008 + uint16 seq; /* sequence control */
5009 + struct ether_addr a4; /* address 4 */
5010 +} PACKED;
5011 +
5012 +/* Control frames */
5013 +
5014 +struct dot11_rts_frame {
5015 + uint16 fc; /* frame control */
5016 + uint16 durid; /* duration/ID */
5017 + struct ether_addr ra; /* receiver address */
5018 + struct ether_addr ta; /* transmitter address */
5019 +} PACKED;
5020 +#define DOT11_RTS_LEN 16
5021 +
5022 +struct dot11_cts_frame {
5023 + uint16 fc; /* frame control */
5024 + uint16 durid; /* duration/ID */
5025 + struct ether_addr ra; /* receiver address */
5026 +} PACKED;
5027 +#define DOT11_CTS_LEN 10
5028 +
5029 +struct dot11_ack_frame {
5030 + uint16 fc; /* frame control */
5031 + uint16 durid; /* duration/ID */
5032 + struct ether_addr ra; /* receiver address */
5033 +} PACKED;
5034 +#define DOT11_ACK_LEN 10
5035 +
5036 +struct dot11_ps_poll_frame {
5037 + uint16 fc; /* frame control */
5038 + uint16 durid; /* AID */
5039 + struct ether_addr bssid; /* receiver address, STA in AP */
5040 + struct ether_addr ta; /* transmitter address */
5041 +} PACKED;
5042 +#define DOT11_PS_POLL_LEN 16
5043 +
5044 +struct dot11_cf_end_frame {
5045 + uint16 fc; /* frame control */
5046 + uint16 durid; /* duration/ID */
5047 + struct ether_addr ra; /* receiver address */
5048 + struct ether_addr bssid; /* transmitter address, STA in AP */
5049 +} PACKED;
5050 +#define DOT11_CS_END_LEN 16
5051 +
5052 +/* Management frame header */
5053 +struct dot11_management_header {
5054 + uint16 fc; /* frame control */
5055 + uint16 durid; /* duration/ID */
5056 + struct ether_addr da; /* receiver address */
5057 + struct ether_addr sa; /* transmitter address */
5058 + struct ether_addr bssid; /* BSS ID */
5059 + uint16 seq; /* sequence control */
5060 +} PACKED;
5061 +#define DOT11_MGMT_HDR_LEN 24
5062 +
5063 +/* Management frame payloads */
5064 +
5065 +struct dot11_bcn_prb {
5066 + uint32 timestamp[2];
5067 + uint16 beacon_interval;
5068 + uint16 capability;
5069 +} PACKED;
5070 +#define DOT11_BCN_PRB_LEN 12
5071 +
5072 +struct dot11_auth {
5073 + uint16 alg; /* algorithm */
5074 + uint16 seq; /* sequence control */
5075 + uint16 status; /* status code */
5076 +} PACKED;
5077 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
5078 +
5079 +struct dot11_assoc_req {
5080 + uint16 capability; /* capability information */
5081 + uint16 listen; /* listen interval */
5082 +} PACKED;
5083 +
5084 +struct dot11_assoc_resp {
5085 + uint16 capability; /* capability information */
5086 + uint16 status; /* status code */
5087 + uint16 aid; /* association ID */
5088 +} PACKED;
5089 +
5090 +struct dot11_action_measure {
5091 + uint8 category;
5092 + uint8 action;
5093 + uint8 token;
5094 + uint8 data[1];
5095 +} PACKED;
5096 +#define DOT11_ACTION_MEASURE_LEN 3
5097 +
5098 +/**************
5099 + 802.11h related definitions.
5100 +**************/
5101 +typedef struct {
5102 + uint8 id;
5103 + uint8 len;
5104 + uint8 power;
5105 +} dot11_power_cnst_t;
5106 +
5107 +typedef struct {
5108 + uint8 min;
5109 + uint8 max;
5110 +} dot11_power_cap_t;
5111 +
5112 +typedef struct {
5113 + uint8 id;
5114 + uint8 len;
5115 + uint8 tx_pwr;
5116 + uint8 margin;
5117 +} dot11_tpc_rep_t;
5118 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
5119 +
5120 +typedef struct {
5121 + uint8 id;
5122 + uint8 len;
5123 + uint8 first_channel;
5124 + uint8 num_channels;
5125 +} dot11_supp_channels_t;
5126 +
5127 +struct dot11_channel_switch {
5128 + uint8 id;
5129 + uint8 len;
5130 + uint8 mode;
5131 + uint8 channel;
5132 + uint8 count;
5133 +} PACKED;
5134 +typedef struct dot11_channel_switch dot11_channel_switch_t;
5135 +
5136 +/* 802.11h Measurement Request/Report IEs */
5137 +/* Measurement Type field */
5138 +#define DOT11_MEASURE_TYPE_BASIC 0
5139 +#define DOT11_MEASURE_TYPE_CCA 1
5140 +#define DOT11_MEASURE_TYPE_RPI 2
5141 +
5142 +/* Measurement Mode field */
5143 +
5144 +/* Measurement Request Modes */
5145 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
5146 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
5147 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
5148 +/* Measurement Report Modes */
5149 +#define DOT11_MEASURE_MODE_LATE (1<<0)
5150 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
5151 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
5152 +/* Basic Measurement Map bits */
5153 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
5154 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
5155 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
5156 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
5157 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
5158 +
5159 +typedef struct {
5160 + uint8 id;
5161 + uint8 len;
5162 + uint8 token;
5163 + uint8 mode;
5164 + uint8 type;
5165 + uint8 channel;
5166 + uint8 start_time[8];
5167 + uint16 duration;
5168 +} dot11_meas_req_t;
5169 +#define DOT11_MNG_IE_MREQ_LEN 14
5170 +/* length of Measure Request IE data not including variable len */
5171 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5172 +
5173 +struct dot11_meas_rep {
5174 + uint8 id;
5175 + uint8 len;
5176 + uint8 token;
5177 + uint8 mode;
5178 + uint8 type;
5179 + union
5180 + {
5181 + struct {
5182 + uint8 channel;
5183 + uint8 start_time[8];
5184 + uint16 duration;
5185 + uint8 map;
5186 + } PACKED basic;
5187 + uint8 data[1];
5188 + } PACKED rep;
5189 +} PACKED;
5190 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5191 +
5192 +/* length of Measure Report IE data not including variable len */
5193 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5194 +
5195 +struct dot11_meas_rep_basic {
5196 + uint8 channel;
5197 + uint8 start_time[8];
5198 + uint16 duration;
5199 + uint8 map;
5200 +} PACKED;
5201 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5202 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5203 +
5204 +struct dot11_quiet {
5205 + uint8 id;
5206 + uint8 len;
5207 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5208 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5209 + uint16 duration;/* Length of quiet period, in TU's */
5210 + uint16 offset; /* TU's offset from TBTT in Count field */
5211 +} PACKED;
5212 +typedef struct dot11_quiet dot11_quiet_t;
5213 +
5214 +typedef struct {
5215 + uint8 channel;
5216 + uint8 map;
5217 +} chan_map_tuple_t;
5218 +
5219 +typedef struct {
5220 + uint8 id;
5221 + uint8 len;
5222 + uint8 eaddr[ETHER_ADDR_LEN];
5223 + uint8 interval;
5224 + chan_map_tuple_t map[1];
5225 +} dot11_ibss_dfs_t;
5226 +
5227 +/* WME Elements */
5228 +#define WME_OUI "\x00\x50\xf2"
5229 +#define WME_VER 1
5230 +#define WME_TYPE 2
5231 +#define WME_SUBTYPE_IE 0 /* Information Element */
5232 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5233 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5234 +
5235 +/* WME Access Category Indices (ACIs) */
5236 +#define AC_BE 0 /* Best Effort */
5237 +#define AC_BK 1 /* Background */
5238 +#define AC_VI 2 /* Video */
5239 +#define AC_VO 3 /* Voice */
5240 +#define AC_MAX 4
5241 +
5242 +/* WME Information Element (IE) */
5243 +struct wme_ie {
5244 + uint8 oui[3];
5245 + uint8 type;
5246 + uint8 subtype;
5247 + uint8 version;
5248 + uint8 acinfo;
5249 +} PACKED;
5250 +typedef struct wme_ie wme_ie_t;
5251 +#define WME_IE_LEN 7
5252 +
5253 +struct wme_acparam {
5254 + uint8 ACI;
5255 + uint8 ECW;
5256 + uint16 TXOP; /* stored in network order (ls octet first) */
5257 +} PACKED;
5258 +typedef struct wme_acparam wme_acparam_t;
5259 +
5260 +/* WME Parameter Element (PE) */
5261 +struct wme_params {
5262 + uint8 oui[3];
5263 + uint8 type;
5264 + uint8 subtype;
5265 + uint8 version;
5266 + uint8 acinfo;
5267 + uint8 rsvd;
5268 + wme_acparam_t acparam[4];
5269 +} PACKED;
5270 +typedef struct wme_params wme_params_t;
5271 +#define WME_PARAMS_IE_LEN 24
5272 +
5273 +/* acinfo */
5274 +#define WME_COUNT_MASK 0x0f
5275 +/* ACI */
5276 +#define WME_AIFS_MASK 0x0f
5277 +#define WME_ACM_MASK 0x10
5278 +#define WME_ACI_MASK 0x60
5279 +#define WME_ACI_SHIFT 5
5280 +/* ECW */
5281 +#define WME_CWMIN_MASK 0x0f
5282 +#define WME_CWMAX_MASK 0xf0
5283 +#define WME_CWMAX_SHIFT 4
5284 +
5285 +#define WME_TXOP_UNITS 32
5286 +
5287 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5288 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5289 +#define WME_AC_BK_ACI_STA 0x27
5290 +#define WME_AC_BK_ECW_STA 0xA4
5291 +#define WME_AC_BK_TXOP_STA 0x0000
5292 +#define WME_AC_BE_ACI_STA 0x03
5293 +#define WME_AC_BE_ECW_STA 0xA4
5294 +#define WME_AC_BE_TXOP_STA 0x0000
5295 +#define WME_AC_VI_ACI_STA 0x42
5296 +#define WME_AC_VI_ECW_STA 0x43
5297 +#define WME_AC_VI_TXOP_STA 0x005e
5298 +#define WME_AC_VO_ACI_STA 0x62
5299 +#define WME_AC_VO_ECW_STA 0x32
5300 +#define WME_AC_VO_TXOP_STA 0x002f
5301 +
5302 +#define WME_AC_BK_ACI_AP 0x27
5303 +#define WME_AC_BK_ECW_AP 0xA4
5304 +#define WME_AC_BK_TXOP_AP 0x0000
5305 +#define WME_AC_BE_ACI_AP 0x03
5306 +#define WME_AC_BE_ECW_AP 0x64
5307 +#define WME_AC_BE_TXOP_AP 0x0000
5308 +#define WME_AC_VI_ACI_AP 0x41
5309 +#define WME_AC_VI_ECW_AP 0x43
5310 +#define WME_AC_VI_TXOP_AP 0x005e
5311 +#define WME_AC_VO_ACI_AP 0x61
5312 +#define WME_AC_VO_ECW_AP 0x32
5313 +#define WME_AC_VO_TXOP_AP 0x002f
5314 +
5315 +/* WME Traffic Specification (TSPEC) element */
5316 +#define WME_SUBTYPE_TSPEC 2
5317 +#define WME_TSPEC_HDR_LEN 2
5318 +#define WME_TSPEC_BODY_OFF 2
5319 +struct wme_tspec {
5320 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5321 + uint8 type; /* WME_TYPE */
5322 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5323 + uint8 version; /* WME_VERSION */
5324 + uint16 ts_info; /* TS Info */
5325 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5326 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5327 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5328 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5329 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5330 + uint32 service_start; /* Service Start Time (us) */
5331 + uint32 min_rate; /* Minimum Data Rate (bps) */
5332 + uint32 mean_rate; /* Mean Data Rate (bps) */
5333 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5334 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5335 + uint32 peak_rate; /* Peak Data Rate (bps) */
5336 + uint32 delay_bound; /* Delay Bound (us) */
5337 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5338 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5339 +} PACKED;
5340 +typedef struct wme_tspec wme_tspec_t;
5341 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5342 +
5343 +/* ts_info */
5344 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5345 +#define TS_INFO_PRIO_SHIFT_HI 11
5346 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5347 +#define TS_INFO_PRIO_SHIFT_LO 1
5348 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5349 +#define TS_INFO_CONTENTION_SHIFT 7
5350 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5351 +#define TS_INFO_DIRECTION_SHIFT 5
5352 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5353 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5354 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5355 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5356 +
5357 +/* nom_msdu_size */
5358 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5359 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5360 +
5361 +/* surplus_bandwidth */
5362 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5363 +#define INTEGER_SHIFT 13
5364 +#define FRACTION_MASK 0x1FFF
5365 +
5366 +/* Management Notification Frame */
5367 +struct dot11_management_notification {
5368 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5369 + uint8 action;
5370 + uint8 token;
5371 + uint8 status;
5372 + uint8 data[1]; /* Elements */
5373 +} PACKED;
5374 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5375 +
5376 +/* WME Action Codes */
5377 +#define WME_SETUP_REQUEST 0
5378 +#define WME_SETUP_RESPONSE 1
5379 +#define WME_TEARDOWN 2
5380 +
5381 +/* WME Setup Response Status Codes */
5382 +#define WME_ADMISSION_ACCEPTED 0
5383 +#define WME_INVALID_PARAMETERS 1
5384 +#define WME_ADMISSION_REFUSED 3
5385 +
5386 +/* Macro to take a pointer to a beacon or probe response
5387 + * header and return the char* pointer to the SSID info element
5388 + */
5389 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5390 +
5391 +/* Authentication frame payload constants */
5392 +#define DOT11_OPEN_SYSTEM 0
5393 +#define DOT11_SHARED_KEY 1
5394 +#define DOT11_CHALLENGE_LEN 128
5395 +
5396 +/* Frame control macros */
5397 +#define FC_PVER_MASK 0x3
5398 +#define FC_PVER_SHIFT 0
5399 +#define FC_TYPE_MASK 0xC
5400 +#define FC_TYPE_SHIFT 2
5401 +#define FC_SUBTYPE_MASK 0xF0
5402 +#define FC_SUBTYPE_SHIFT 4
5403 +#define FC_TODS 0x100
5404 +#define FC_TODS_SHIFT 8
5405 +#define FC_FROMDS 0x200
5406 +#define FC_FROMDS_SHIFT 9
5407 +#define FC_MOREFRAG 0x400
5408 +#define FC_MOREFRAG_SHIFT 10
5409 +#define FC_RETRY 0x800
5410 +#define FC_RETRY_SHIFT 11
5411 +#define FC_PM 0x1000
5412 +#define FC_PM_SHIFT 12
5413 +#define FC_MOREDATA 0x2000
5414 +#define FC_MOREDATA_SHIFT 13
5415 +#define FC_WEP 0x4000
5416 +#define FC_WEP_SHIFT 14
5417 +#define FC_ORDER 0x8000
5418 +#define FC_ORDER_SHIFT 15
5419 +
5420 +/* sequence control macros */
5421 +#define SEQNUM_SHIFT 4
5422 +#define FRAGNUM_MASK 0xF
5423 +
5424 +/* Frame Control type/subtype defs */
5425 +
5426 +/* FC Types */
5427 +#define FC_TYPE_MNG 0
5428 +#define FC_TYPE_CTL 1
5429 +#define FC_TYPE_DATA 2
5430 +
5431 +/* Management Subtypes */
5432 +#define FC_SUBTYPE_ASSOC_REQ 0
5433 +#define FC_SUBTYPE_ASSOC_RESP 1
5434 +#define FC_SUBTYPE_REASSOC_REQ 2
5435 +#define FC_SUBTYPE_REASSOC_RESP 3
5436 +#define FC_SUBTYPE_PROBE_REQ 4
5437 +#define FC_SUBTYPE_PROBE_RESP 5
5438 +#define FC_SUBTYPE_BEACON 8
5439 +#define FC_SUBTYPE_ATIM 9
5440 +#define FC_SUBTYPE_DISASSOC 10
5441 +#define FC_SUBTYPE_AUTH 11
5442 +#define FC_SUBTYPE_DEAUTH 12
5443 +#define FC_SUBTYPE_ACTION 13
5444 +
5445 +/* Control Subtypes */
5446 +#define FC_SUBTYPE_PS_POLL 10
5447 +#define FC_SUBTYPE_RTS 11
5448 +#define FC_SUBTYPE_CTS 12
5449 +#define FC_SUBTYPE_ACK 13
5450 +#define FC_SUBTYPE_CF_END 14
5451 +#define FC_SUBTYPE_CF_END_ACK 15
5452 +
5453 +/* Data Subtypes */
5454 +#define FC_SUBTYPE_DATA 0
5455 +#define FC_SUBTYPE_DATA_CF_ACK 1
5456 +#define FC_SUBTYPE_DATA_CF_POLL 2
5457 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5458 +#define FC_SUBTYPE_NULL 4
5459 +#define FC_SUBTYPE_CF_ACK 5
5460 +#define FC_SUBTYPE_CF_POLL 6
5461 +#define FC_SUBTYPE_CF_ACK_POLL 7
5462 +#define FC_SUBTYPE_QOS_DATA 8
5463 +#define FC_SUBTYPE_QOS_NULL 12
5464 +
5465 +/* type-subtype combos */
5466 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5467 +
5468 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5469 +
5470 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5471 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5472 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5473 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5474 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5475 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5476 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5477 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5478 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5479 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5480 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5481 +
5482 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5483 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5484 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5485 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5486 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5487 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5488 +
5489 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5490 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5491 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5492 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5493 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5494 +
5495 +/* QoS Control Field */
5496 +
5497 +/* 802.1D Tag */
5498 +#define QOS_PRIO_SHIFT 0
5499 +#define QOS_PRIO_MASK 0x0007
5500 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5501 +
5502 +/* Ack Policy (0 means Acknowledge) */
5503 +#define QOS_ACK_SHIFT 5
5504 +#define QOS_ACK_MASK 0x0060
5505 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5506 +
5507 +/* Management Frames */
5508 +
5509 +/* Management Frame Constants */
5510 +
5511 +/* Fixed fields */
5512 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5513 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5514 +#define DOT11_MNG_BEACON_INT_LEN 2
5515 +#define DOT11_MNG_CAP_LEN 2
5516 +#define DOT11_MNG_AP_ADDR_LEN 6
5517 +#define DOT11_MNG_LISTEN_INT_LEN 2
5518 +#define DOT11_MNG_REASON_LEN 2
5519 +#define DOT11_MNG_AID_LEN 2
5520 +#define DOT11_MNG_STATUS_LEN 2
5521 +#define DOT11_MNG_TIMESTAMP_LEN 8
5522 +
5523 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5524 +#define DOT11_AID_MASK 0x3fff
5525 +
5526 +/* Reason Codes */
5527 +#define DOT11_RC_RESERVED 0
5528 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5529 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5530 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5531 + leaving (or has left) IBSS or ESS */
5532 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5533 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5534 + all currently associated stations */
5535 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5536 + nonauthenticated station */
5537 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5538 + nonassociated station */
5539 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5540 + leaving (or has left) BSS */
5541 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5542 + not authenticated with responding station */
5543 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5544 +
5545 +/* Status Codes */
5546 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5547 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5548 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5549 + in the Capability Information field */
5550 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5551 + confirm that association exists */
5552 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5553 + the scope of this standard */
5554 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5555 + specified authentication algorithm */
5556 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5557 + authentication transaction sequence number
5558 + out of expected sequence */
5559 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5560 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5561 + for next frame in sequence */
5562 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5563 + handle additional associated stations */
5564 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5565 + not supporting all of the data rates in the
5566 + BSSBasicRateSet parameter */
5567 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5568 + not supporting the Short Preamble option */
5569 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5570 + not supporting the PBCC Modulation option */
5571 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5572 + not supporting the Channel Agility option */
5573 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5574 + capability is required. */
5575 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5576 + Power Cap element is unacceptable. */
5577 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5578 + Supported Channel element is unacceptable */
5579 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5580 + not supporting the Short Slot Time option */
5581 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5582 + not supporting the ER-PBCC Modulation option */
5583 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5584 + not supporting the DSS-OFDM option */
5585 +
5586 +/* Info Elts, length of INFORMATION portion of Info Elts */
5587 +#define DOT11_MNG_DS_PARAM_LEN 1
5588 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5589 +
5590 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5591 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5592 +#define DOT11_MNG_TIM_FIXED_LEN 3
5593 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5594 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5595 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5596 +#define DOT11_MNG_TIM_PVB 3
5597 +
5598 +/* TLV defines */
5599 +#define TLV_TAG_OFF 0
5600 +#define TLV_LEN_OFF 1
5601 +#define TLV_HDR_LEN 2
5602 +#define TLV_BODY_OFF 2
5603 +
5604 +/* Management Frame Information Element IDs */
5605 +#define DOT11_MNG_SSID_ID 0
5606 +#define DOT11_MNG_RATES_ID 1
5607 +#define DOT11_MNG_FH_PARMS_ID 2
5608 +#define DOT11_MNG_DS_PARMS_ID 3
5609 +#define DOT11_MNG_CF_PARMS_ID 4
5610 +#define DOT11_MNG_TIM_ID 5
5611 +#define DOT11_MNG_IBSS_PARMS_ID 6
5612 +#define DOT11_MNG_COUNTRY_ID 7
5613 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5614 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5615 +#define DOT11_MNG_REQUEST_ID 10
5616 +#define DOT11_MNG_CHALLENGE_ID 16
5617 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5618 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5619 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5620 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5621 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5622 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5623 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5624 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5625 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5626 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5627 +#define DOT11_MNG_ERP_ID 42
5628 +#define DOT11_MNG_NONERP_ID 47
5629 +#define DOT11_MNG_RSN_ID 48
5630 +#define DOT11_MNG_EXT_RATES_ID 50
5631 +#define DOT11_MNG_WPA_ID 221
5632 +#define DOT11_MNG_PROPR_ID 221
5633 +
5634 +/* ERP info element bit values */
5635 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5636 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5637 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5638 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5639 +
5640 +/* Capability Information Field */
5641 +#define DOT11_CAP_ESS 0x0001
5642 +#define DOT11_CAP_IBSS 0x0002
5643 +#define DOT11_CAP_POLLABLE 0x0004
5644 +#define DOT11_CAP_POLL_RQ 0x0008
5645 +#define DOT11_CAP_PRIVACY 0x0010
5646 +#define DOT11_CAP_SHORT 0x0020
5647 +#define DOT11_CAP_PBCC 0x0040
5648 +#define DOT11_CAP_AGILITY 0x0080
5649 +#define DOT11_CAP_SPECTRUM 0x0100
5650 +#define DOT11_CAP_SHORTSLOT 0x0400
5651 +#define DOT11_CAP_CCK_OFDM 0x2000
5652 +
5653 +/* Action Frame Constants */
5654 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5655 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5656 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5657 +
5658 +#define DOT11_ACTION_ID_M_REQ 0
5659 +#define DOT11_ACTION_ID_M_REP 1
5660 +#define DOT11_ACTION_ID_TPC_REQ 2
5661 +#define DOT11_ACTION_ID_TPC_REP 3
5662 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5663 +
5664 +/* MLME Enumerations */
5665 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5666 +#define DOT11_BSSTYPE_INDEPENDENT 1
5667 +#define DOT11_BSSTYPE_ANY 2
5668 +#define DOT11_SCANTYPE_ACTIVE 0
5669 +#define DOT11_SCANTYPE_PASSIVE 1
5670 +
5671 +/* 802.11 A PHY constants */
5672 +#define APHY_SLOT_TIME 9
5673 +#define APHY_SIFS_TIME 16
5674 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5675 +#define APHY_PREAMBLE_TIME 16
5676 +#define APHY_SIGNAL_TIME 4
5677 +#define APHY_SYMBOL_TIME 4
5678 +#define APHY_SERVICE_NBITS 16
5679 +#define APHY_TAIL_NBITS 6
5680 +#define APHY_CWMIN 15
5681 +
5682 +/* 802.11 B PHY constants */
5683 +#define BPHY_SLOT_TIME 20
5684 +#define BPHY_SIFS_TIME 10
5685 +#define BPHY_DIFS_TIME 50
5686 +#define BPHY_PLCP_TIME 192
5687 +#define BPHY_PLCP_SHORT_TIME 96
5688 +#define BPHY_CWMIN 31
5689 +
5690 +/* 802.11 G constants */
5691 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5692 +
5693 +#define PHY_CWMAX 1023
5694 +
5695 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5696 +
5697 +/* dot11Counters Table - 802.11 spec., Annex D */
5698 +typedef struct d11cnt {
5699 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5700 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5701 + uint32 txfail; /* dot11FailedCount */
5702 + uint32 txretry; /* dot11RetryCount */
5703 + uint32 txretrie; /* dot11MultipleRetryCount */
5704 + uint32 rxdup; /* dot11FrameduplicateCount */
5705 + uint32 txrts; /* dot11RTSSuccessCount */
5706 + uint32 txnocts; /* dot11RTSFailureCount */
5707 + uint32 txnoack; /* dot11ACKFailureCount */
5708 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5709 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5710 + uint32 rxcrc; /* dot11FCSErrorCount */
5711 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5712 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5713 +} d11cnt_t;
5714 +
5715 +/* BRCM OUI */
5716 +#define BRCM_OUI "\x00\x10\x18"
5717 +
5718 +/* BRCM info element */
5719 +struct brcm_ie {
5720 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5721 + uchar len;
5722 + uchar oui[3];
5723 + uchar ver;
5724 + uchar assoc; /* # of assoc STAs */
5725 + uchar flags; /* misc flags */
5726 +} PACKED;
5727 +#define BRCM_IE_LEN 8
5728 +typedef struct brcm_ie brcm_ie_t;
5729 +#define BRCM_IE_VER 2
5730 +#define BRCM_IE_LEGACY_AES_VER 1
5731 +
5732 +/* brcm_ie flags */
5733 +#define BRF_ABCAP 0x1 /* afterburner capable */
5734 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5735 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5736 +
5737 +
5738 +/* OUI for BRCM proprietary IE */
5739 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5740 +
5741 +/* Vendor IE structure */
5742 +struct vndr_ie {
5743 + uchar id;
5744 + uchar len;
5745 + uchar oui [3];
5746 + uchar data [1]; /* Variable size data */
5747 +}PACKED;
5748 +typedef struct vndr_ie vndr_ie_t;
5749 +
5750 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
5751 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
5752 +#define VNDR_IE_MAX_LEN 256
5753 +
5754 +/* WPA definitions */
5755 +#define WPA_VERSION 1
5756 +#define WPA_OUI "\x00\x50\xF2"
5757 +
5758 +#define WPA2_VERSION 1
5759 +#define WPA2_VERSION_LEN 2
5760 +#define WPA2_OUI "\x00\x0F\xAC"
5761 +
5762 +#define WPA_OUI_LEN 3
5763 +
5764 +/* RSN authenticated key managment suite */
5765 +#define RSN_AKM_NONE 0 /* None (IBSS) */
5766 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
5767 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
5768 +
5769 +
5770 +/* Key related defines */
5771 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
5772 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
5773 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
5774 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
5775 +
5776 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
5777 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
5778 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
5779 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
5780 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
5781 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
5782 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
5783 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
5784 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
5785 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
5786 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
5787 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
5788 +#define AES_KEY_SIZE 16 /* size of AES key */
5789 +
5790 +#undef PACKED
5791 +#if !defined(__GNUC__)
5792 +#pragma pack()
5793 +#endif
5794 +
5795 +#endif /* _802_11_H_ */
5796 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h
5797 --- linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
5798 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-08-26 13:44:34.295394104 +0200
5799 @@ -0,0 +1,97 @@
5800 +/*
5801 + * Broadcom Ethernettype protocol definitions
5802 + *
5803 + * Copyright 2005, Broadcom Corporation
5804 + * All Rights Reserved.
5805 + *
5806 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5807 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5808 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5809 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5810 + *
5811 + */
5812 +
5813 +/*
5814 + * Broadcom Ethernet protocol defines
5815 + *
5816 + */
5817 +
5818 +#ifndef _BCMETH_H_
5819 +#define _BCMETH_H_
5820 +
5821 +/* enable structure packing */
5822 +#if defined(__GNUC__)
5823 +#define PACKED __attribute__((packed))
5824 +#else
5825 +#pragma pack(1)
5826 +#define PACKED
5827 +#endif
5828 +
5829 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
5830 +
5831 +/*
5832 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
5833 + * in one of two formats: (only subtypes 32768-65535 are in use now)
5834 + *
5835 + * subtypes 0-32767:
5836 + * 8 bit subtype (0-127)
5837 + * 8 bit length in bytes (0-255)
5838 + *
5839 + * subtypes 32768-65535:
5840 + * 16 bit big-endian subtype
5841 + * 16 bit big-endian length in bytes (0-65535)
5842 + *
5843 + * length is the number of additional bytes beyond the 4 or 6 byte header
5844 + *
5845 + * Reserved values:
5846 + * 0 reserved
5847 + * 5-15 reserved for iLine protocol assignments
5848 + * 17-126 reserved, assignable
5849 + * 127 reserved
5850 + * 32768 reserved
5851 + * 32769-65534 reserved, assignable
5852 + * 65535 reserved
5853 + */
5854 +
5855 +/*
5856 + * While adding the subtypes and their specific processing code make sure
5857 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
5858 + */
5859 +
5860 +#define BCMILCP_SUBTYPE_RATE 1
5861 +#define BCMILCP_SUBTYPE_LINK 2
5862 +#define BCMILCP_SUBTYPE_CSA 3
5863 +#define BCMILCP_SUBTYPE_LARQ 4
5864 +#define BCMILCP_SUBTYPE_VENDOR 5
5865 +#define BCMILCP_SUBTYPE_FLH 17
5866 +
5867 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
5868 +#define BCMILCP_SUBTYPE_CERT 32770
5869 +#define BCMILCP_SUBTYPE_SES 32771
5870 +
5871 +
5872 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
5873 +#define BCMILCP_BCM_SUBTYPE_WPA 1
5874 +#define BCMILCP_BCM_SUBTYPE_EAPOL 2
5875 +#define BCMILCP_BCM_SUBTYPE_SES 3
5876 +
5877 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
5878 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
5879 +
5880 +typedef struct bcmeth_bcm_hdr
5881 +{
5882 + uint16 subtype; /* Vendor specific..32769*/
5883 + uint16 length;
5884 + uint8 version; /* Version is 0*/
5885 + uint8 oui[3]; /* Broadcom OUI*/
5886 + /* user specific Data */
5887 + uint16 usr_subtype;
5888 +} PACKED bcmeth_bcm_hdr_t;
5889 +
5890 +
5891 +#undef PACKED
5892 +#if !defined(__GNUC__)
5893 +#pragma pack()
5894 +#endif
5895 +
5896 +#endif
5897 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
5898 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
5899 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-08-26 13:44:34.296393952 +0200
5900 @@ -0,0 +1,161 @@
5901 +/*******************************************************************************
5902 + * $Id$
5903 + * Copyright 2005, Broadcom Corporation
5904 + * All Rights Reserved.
5905 + *
5906 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5907 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5908 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5909 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5910 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
5911 + ******************************************************************************/
5912 +
5913 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
5914 +#define _NET_ETHERNET_H_
5915 +
5916 +#ifndef _TYPEDEFS_H_
5917 +#include "typedefs.h"
5918 +#endif
5919 +
5920 +/* enable structure packing */
5921 +#if defined(__GNUC__)
5922 +#define PACKED __attribute__((packed))
5923 +#else
5924 +#pragma pack(1)
5925 +#define PACKED
5926 +#endif
5927 +
5928 +/*
5929 + * The number of bytes in an ethernet (MAC) address.
5930 + */
5931 +#define ETHER_ADDR_LEN 6
5932 +
5933 +/*
5934 + * The number of bytes in the type field.
5935 + */
5936 +#define ETHER_TYPE_LEN 2
5937 +
5938 +/*
5939 + * The number of bytes in the trailing CRC field.
5940 + */
5941 +#define ETHER_CRC_LEN 4
5942 +
5943 +/*
5944 + * The length of the combined header.
5945 + */
5946 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
5947 +
5948 +/*
5949 + * The minimum packet length.
5950 + */
5951 +#define ETHER_MIN_LEN 64
5952 +
5953 +/*
5954 + * The minimum packet user data length.
5955 + */
5956 +#define ETHER_MIN_DATA 46
5957 +
5958 +/*
5959 + * The maximum packet length.
5960 + */
5961 +#define ETHER_MAX_LEN 1518
5962 +
5963 +/*
5964 + * The maximum packet user data length.
5965 + */
5966 +#define ETHER_MAX_DATA 1500
5967 +
5968 +/* ether types */
5969 +#define ETHER_TYPE_IP 0x0800 /* IP */
5970 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
5971 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
5972 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
5973 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
5974 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
5975 +
5976 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
5977 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
5978 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
5979 +
5980 +/* ether header */
5981 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
5982 +#define ETHER_SRC_OFFSET 6 /* src address offset */
5983 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
5984 +
5985 +/*
5986 + * A macro to validate a length with
5987 + */
5988 +#define ETHER_IS_VALID_LEN(foo) \
5989 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
5990 +
5991 +
5992 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
5993 +/*
5994 + * Structure of a 10Mb/s Ethernet header.
5995 + */
5996 +struct ether_header {
5997 + uint8 ether_dhost[ETHER_ADDR_LEN];
5998 + uint8 ether_shost[ETHER_ADDR_LEN];
5999 + uint16 ether_type;
6000 +} PACKED;
6001 +
6002 +/*
6003 + * Structure of a 48-bit Ethernet address.
6004 + */
6005 +struct ether_addr {
6006 + uint8 octet[ETHER_ADDR_LEN];
6007 +} PACKED;
6008 +#endif
6009 +
6010 +/*
6011 + * Takes a pointer, returns true if a 48-bit multicast address
6012 + * (including broadcast, since it is all ones)
6013 + */
6014 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
6015 +
6016 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
6017 +#define ether_cmp(a, b) ( \
6018 + !(((short*)a)[0] == ((short*)b)[0]) | \
6019 + !(((short*)a)[1] == ((short*)b)[1]) | \
6020 + !(((short*)a)[2] == ((short*)b)[2]))
6021 +
6022 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
6023 +#define ether_copy(s, d) { \
6024 + ((short*)d)[0] = ((short*)s)[0]; \
6025 + ((short*)d)[1] = ((short*)s)[1]; \
6026 + ((short*)d)[2] = ((short*)s)[2]; }
6027 +
6028 +/*
6029 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
6030 + */
6031 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
6032 + ((uint8 *)(ea))[1] & \
6033 + ((uint8 *)(ea))[2] & \
6034 + ((uint8 *)(ea))[3] & \
6035 + ((uint8 *)(ea))[4] & \
6036 + ((uint8 *)(ea))[5]) == 0xff)
6037 +
6038 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
6039 +
6040 +/*
6041 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
6042 + */
6043 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
6044 + ((uint8 *)(ea))[1] | \
6045 + ((uint8 *)(ea))[2] | \
6046 + ((uint8 *)(ea))[3] | \
6047 + ((uint8 *)(ea))[4] | \
6048 + ((uint8 *)(ea))[5]) == 0)
6049 +
6050 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
6051 +#define DSCP_MASK 0xFC /* upper 6 bits */
6052 +#define DSCP_SHIFT 2
6053 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
6054 +#define DSCP_WME_PRI_SHIFT 5
6055 +
6056 +#undef PACKED
6057 +#if !defined(__GNUC__)
6058 +#pragma pack()
6059 +#endif
6060 +
6061 +#endif /* _NET_ETHERNET_H_ */
6062 diff -urN linux.old/arch/mips/bcm947xx/include/proto/vlan.h linux.dev/arch/mips/bcm947xx/include/proto/vlan.h
6063 --- linux.old/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
6064 +++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-08-26 13:44:34.296393952 +0200
6065 @@ -0,0 +1,50 @@
6066 +/*
6067 + * 802.1Q VLAN protocol definitions
6068 + *
6069 + * Copyright 2005, Broadcom Corporation
6070 + * All Rights Reserved.
6071 + *
6072 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6073 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6074 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6075 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6076 + *
6077 + * $Id$
6078 + */
6079 +
6080 +#ifndef _vlan_h_
6081 +#define _vlan_h_
6082 +
6083 +/* enable structure packing */
6084 +#if defined(__GNUC__)
6085 +#define PACKED __attribute__((packed))
6086 +#else
6087 +#pragma pack(1)
6088 +#define PACKED
6089 +#endif
6090 +
6091 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
6092 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
6093 +#define VLAN_PRI_SHIFT 13 /* user priority */
6094 +
6095 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
6096 +
6097 +#define VLAN_TAG_LEN 4
6098 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
6099 +
6100 +struct ethervlan_header {
6101 + uint8 ether_dhost[ETHER_ADDR_LEN];
6102 + uint8 ether_shost[ETHER_ADDR_LEN];
6103 + uint16 vlan_type; /* 0x8100 */
6104 + uint16 vlan_tag; /* priority, cfi and vid */
6105 + uint16 ether_type;
6106 +};
6107 +
6108 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
6109 +
6110 +#undef PACKED
6111 +#if !defined(__GNUC__)
6112 +#pragma pack()
6113 +#endif
6114 +
6115 +#endif /* _vlan_h_ */
6116 diff -urN linux.old/arch/mips/bcm947xx/include/proto/wpa.h linux.dev/arch/mips/bcm947xx/include/proto/wpa.h
6117 --- linux.old/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
6118 +++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-08-26 13:44:34.297393800 +0200
6119 @@ -0,0 +1,140 @@
6120 +/*
6121 + * Fundamental types and constants relating to WPA
6122 + *
6123 + * Copyright 2005, Broadcom Corporation
6124 + * All Rights Reserved.
6125 + *
6126 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6127 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6128 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6129 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6130 + *
6131 + * $Id$
6132 + */
6133 +
6134 +#ifndef _proto_wpa_h_
6135 +#define _proto_wpa_h_
6136 +
6137 +#include <typedefs.h>
6138 +#include <proto/ethernet.h>
6139 +
6140 +/* enable structure packing */
6141 +#if defined(__GNUC__)
6142 +#define PACKED __attribute__((packed))
6143 +#else
6144 +#pragma pack(1)
6145 +#define PACKED
6146 +#endif
6147 +
6148 +/* Reason Codes */
6149 +
6150 +/* 10 and 11 are from TGh. */
6151 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
6152 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
6153 +/* 12 is unused */
6154 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
6155 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
6156 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
6157 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
6158 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
6159 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
6160 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6161 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6162 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6163 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6164 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6165 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6166 +
6167 +#define WPA2_PMKID_LEN 16
6168 +
6169 +/* WPA IE fixed portion */
6170 +typedef struct
6171 +{
6172 + uint8 tag; /* TAG */
6173 + uint8 length; /* TAG length */
6174 + uint8 oui[3]; /* IE OUI */
6175 + uint8 oui_type; /* OUI type */
6176 + struct {
6177 + uint8 low;
6178 + uint8 high;
6179 + } PACKED version; /* IE version */
6180 +} PACKED wpa_ie_fixed_t;
6181 +#define WPA_IE_OUITYPE_LEN 4
6182 +#define WPA_IE_FIXED_LEN 8
6183 +#define WPA_IE_TAG_FIXED_LEN 6
6184 +
6185 +typedef struct {
6186 + uint8 tag; /* TAG */
6187 + uint8 length; /* TAG length */
6188 + struct {
6189 + uint8 low;
6190 + uint8 high;
6191 + } PACKED version; /* IE version */
6192 +} PACKED wpa_rsn_ie_fixed_t;
6193 +#define WPA_RSN_IE_FIXED_LEN 4
6194 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6195 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6196 +
6197 +/* WPA suite/multicast suite */
6198 +typedef struct
6199 +{
6200 + uint8 oui[3];
6201 + uint8 type;
6202 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6203 +#define WPA_SUITE_LEN 4
6204 +
6205 +/* WPA unicast suite list/key management suite list */
6206 +typedef struct
6207 +{
6208 + struct {
6209 + uint8 low;
6210 + uint8 high;
6211 + } PACKED count;
6212 + wpa_suite_t list[1];
6213 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6214 +#define WPA_IE_SUITE_COUNT_LEN 2
6215 +typedef struct
6216 +{
6217 + struct {
6218 + uint8 low;
6219 + uint8 high;
6220 + } PACKED count;
6221 + wpa_pmkid_t list[1];
6222 +} PACKED wpa_pmkid_list_t;
6223 +
6224 +/* WPA cipher suites */
6225 +#define WPA_CIPHER_NONE 0 /* None */
6226 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6227 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6228 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6229 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6230 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6231 +
6232 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6233 + (cipher) == WPA_CIPHER_WEP_40 || \
6234 + (cipher) == WPA_CIPHER_WEP_104 || \
6235 + (cipher) == WPA_CIPHER_TKIP || \
6236 + (cipher) == WPA_CIPHER_AES_OCB || \
6237 + (cipher) == WPA_CIPHER_AES_CCM)
6238 +
6239 +/* WPA TKIP countermeasures parameters */
6240 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6241 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6242 +
6243 +/* WPA capabilities defined in 802.11i */
6244 +#define WPA_CAP_4_REPLAY_CNTRS 2
6245 +#define WPA_CAP_16_REPLAY_CNTRS 3
6246 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6247 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6248 +
6249 +/* WPA Specific defines */
6250 +#define WPA_CAP_LEN 2
6251 +
6252 +#define WPA_CAP_WPA2_PREAUTH 1
6253 +
6254 +#undef PACKED
6255 +#if !defined(__GNUC__)
6256 +#pragma pack()
6257 +#endif
6258 +
6259 +#endif /* _proto_wpa_h_ */
6260 diff -urN linux.old/arch/mips/bcm947xx/include/rts/crc.h linux.dev/arch/mips/bcm947xx/include/rts/crc.h
6261 --- linux.old/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6262 +++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-08-26 13:44:34.297393800 +0200
6263 @@ -0,0 +1,69 @@
6264 +/*******************************************************************************
6265 + * $Id$
6266 + * Copyright 2005, Broadcom Corporation
6267 + * All Rights Reserved.
6268 + *
6269 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6270 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6271 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6272 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6273 + * crc.h - a function to compute crc for iLine10 headers
6274 + ******************************************************************************/
6275 +
6276 +#ifndef _RTS_CRC_H_
6277 +#define _RTS_CRC_H_ 1
6278 +
6279 +#include "typedefs.h"
6280 +
6281 +#ifdef __cplusplus
6282 +extern "C" {
6283 +#endif
6284 +
6285 +
6286 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6287 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6288 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6289 +
6290 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6291 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6292 +
6293 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6294 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6295 +
6296 +void hcs(uint8 *, uint);
6297 +uint8 crc8(uint8 *, uint, uint8);
6298 +uint16 crc16(uint8 *, uint, uint16);
6299 +uint32 crc32(uint8 *, uint, uint32);
6300 +
6301 +/* macros for common usage */
6302 +
6303 +#define APPEND_CRC8(pbytes, nbytes) \
6304 +do { \
6305 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6306 + (pbytes)[(nbytes)] = tmp; \
6307 + (nbytes) += 1; \
6308 +} while (0)
6309 +
6310 +#define APPEND_CRC16(pbytes, nbytes) \
6311 +do { \
6312 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6313 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6314 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6315 + (nbytes) += 2; \
6316 +} while (0)
6317 +
6318 +#define APPEND_CRC32(pbytes, nbytes) \
6319 +do { \
6320 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6321 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6322 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6323 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6324 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6325 + (nbytes) += 4; \
6326 +} while (0)
6327 +
6328 +#ifdef __cplusplus
6329 +}
6330 +#endif
6331 +
6332 +#endif /* _RTS_CRC_H_ */
6333 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6334 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6335 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-08-26 13:44:34.298393648 +0200
6336 @@ -0,0 +1,394 @@
6337 +/*
6338 + * SiliconBackplane Chipcommon core hardware definitions.
6339 + *
6340 + * The chipcommon core provides chip identification, SB control,
6341 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6342 + * gpio interface, extbus, and support for serial and parallel flashes.
6343 + *
6344 + * $Id$
6345 + * Copyright 2005, Broadcom Corporation
6346 + * All Rights Reserved.
6347 + *
6348 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6349 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6350 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6351 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6352 + *
6353 + */
6354 +
6355 +#ifndef _SBCHIPC_H
6356 +#define _SBCHIPC_H
6357 +
6358 +
6359 +#ifndef _LANGUAGE_ASSEMBLY
6360 +
6361 +/* cpp contortions to concatenate w/arg prescan */
6362 +#ifndef PAD
6363 +#define _PADLINE(line) pad ## line
6364 +#define _XSTR(line) _PADLINE(line)
6365 +#define PAD _XSTR(__LINE__)
6366 +#endif /* PAD */
6367 +
6368 +typedef volatile struct {
6369 + uint32 chipid; /* 0x0 */
6370 + uint32 capabilities;
6371 + uint32 corecontrol; /* corerev >= 1 */
6372 + uint32 bist;
6373 +
6374 + /* OTP */
6375 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6376 + uint32 otpcontrol;
6377 + uint32 otpprog;
6378 + uint32 PAD;
6379 +
6380 + /* Interrupt control */
6381 + uint32 intstatus; /* 0x20 */
6382 + uint32 intmask;
6383 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6384 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6385 +
6386 + /* Jtag Master */
6387 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6388 + uint32 jtagir;
6389 + uint32 jtagdr;
6390 + uint32 jtagctrl;
6391 +
6392 + /* serial flash interface registers */
6393 + uint32 flashcontrol; /* 0x40 */
6394 + uint32 flashaddress;
6395 + uint32 flashdata;
6396 + uint32 PAD[1];
6397 +
6398 + /* Silicon backplane configuration broadcast control */
6399 + uint32 broadcastaddress; /* 0x50 */
6400 + uint32 broadcastdata;
6401 + uint32 PAD[2];
6402 +
6403 + /* gpio - cleared only by power-on-reset */
6404 + uint32 gpioin; /* 0x60 */
6405 + uint32 gpioout;
6406 + uint32 gpioouten;
6407 + uint32 gpiocontrol;
6408 + uint32 gpiointpolarity;
6409 + uint32 gpiointmask;
6410 + uint32 PAD[2];
6411 +
6412 + /* Watchdog timer */
6413 + uint32 watchdog; /* 0x80 */
6414 + uint32 PAD[3];
6415 +
6416 + /* clock control */
6417 + uint32 clockcontrol_n; /* 0x90 */
6418 + uint32 clockcontrol_sb; /* aka m0 */
6419 + uint32 clockcontrol_pci; /* aka m1 */
6420 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6421 + uint32 clockcontrol_mips; /* aka m3 */
6422 + uint32 clkdiv; /* corerev >= 3 */
6423 + uint32 PAD[2];
6424 +
6425 + /* pll delay registers (corerev >= 4) */
6426 + uint32 pll_on_delay; /* 0xb0 */
6427 + uint32 fref_sel_delay;
6428 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6429 + uint32 PAD[1];
6430 +
6431 + /* Instaclock registers (corerev >= 10) */
6432 + uint32 system_clk_ctl; /* 0xc0 */
6433 + uint32 clkstatestretch;
6434 + uint32 PAD[14];
6435 +
6436 + /* ExtBus control registers (corerev >= 3) */
6437 + uint32 pcmcia_config; /* 0x100 */
6438 + uint32 pcmcia_memwait;
6439 + uint32 pcmcia_attrwait;
6440 + uint32 pcmcia_iowait;
6441 + uint32 ide_config;
6442 + uint32 ide_memwait;
6443 + uint32 ide_attrwait;
6444 + uint32 ide_iowait;
6445 + uint32 prog_config;
6446 + uint32 prog_waitcount;
6447 + uint32 flash_config;
6448 + uint32 flash_waitcount;
6449 + uint32 PAD[116];
6450 +
6451 + /* uarts */
6452 + uint8 uart0data; /* 0x300 */
6453 + uint8 uart0imr;
6454 + uint8 uart0fcr;
6455 + uint8 uart0lcr;
6456 + uint8 uart0mcr;
6457 + uint8 uart0lsr;
6458 + uint8 uart0msr;
6459 + uint8 uart0scratch;
6460 + uint8 PAD[248]; /* corerev >= 1 */
6461 +
6462 + uint8 uart1data; /* 0x400 */
6463 + uint8 uart1imr;
6464 + uint8 uart1fcr;
6465 + uint8 uart1lcr;
6466 + uint8 uart1mcr;
6467 + uint8 uart1lsr;
6468 + uint8 uart1msr;
6469 + uint8 uart1scratch;
6470 +} chipcregs_t;
6471 +
6472 +#endif /* _LANGUAGE_ASSEMBLY */
6473 +
6474 +#define CC_CHIPID 0
6475 +#define CC_CAPABILITIES 4
6476 +#define CC_JTAGCMD 0x30
6477 +#define CC_JTAGIR 0x34
6478 +#define CC_JTAGDR 0x38
6479 +#define CC_JTAGCTRL 0x3c
6480 +#define CC_CLKDIV 0xa4
6481 +#define CC_OTP 0x800
6482 +
6483 +/* chipid */
6484 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6485 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6486 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6487 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6488 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6489 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6490 +#define CID_CC_SHIFT 24
6491 +
6492 +/* capabilities */
6493 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6494 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6495 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6496 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6497 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6498 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6499 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6500 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6501 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6502 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6503 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6504 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6505 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6506 +
6507 +/* PLL type */
6508 +#define PLL_NONE 0x00000000
6509 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6510 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6511 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6512 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6513 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6514 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6515 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6516 +
6517 +/* corecontrol */
6518 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6519 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6520 +
6521 +/* jtagcmd */
6522 +#define JCMD_START 0x80000000
6523 +#define JCMD_BUSY 0x80000000
6524 +#define JCMD_PAUSE 0x40000000
6525 +#define JCMD0_ACC_MASK 0x0000f000
6526 +#define JCMD0_ACC_IRDR 0x00000000
6527 +#define JCMD0_ACC_DR 0x00001000
6528 +#define JCMD0_ACC_IR 0x00002000
6529 +#define JCMD0_ACC_RESET 0x00003000
6530 +#define JCMD0_ACC_IRPDR 0x00004000
6531 +#define JCMD0_ACC_PDR 0x00005000
6532 +#define JCMD0_IRW_MASK 0x00000f00
6533 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6534 +#define JCMD_ACC_IRDR 0x00000000
6535 +#define JCMD_ACC_DR 0x00010000
6536 +#define JCMD_ACC_IR 0x00020000
6537 +#define JCMD_ACC_RESET 0x00030000
6538 +#define JCMD_ACC_IRPDR 0x00040000
6539 +#define JCMD_ACC_PDR 0x00050000
6540 +#define JCMD_IRW_MASK 0x00001f00
6541 +#define JCMD_IRW_SHIFT 8
6542 +#define JCMD_DRW_MASK 0x0000003f
6543 +
6544 +/* jtagctrl */
6545 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6546 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6547 +#define JCTRL_EN 1 /* Enable Jtag master */
6548 +
6549 +/* Fields in clkdiv */
6550 +#define CLKD_SFLASH 0x0f000000
6551 +#define CLKD_SFLASH_SHIFT 24
6552 +#define CLKD_OTP 0x000f0000
6553 +#define CLKD_OTP_SHIFT 16
6554 +#define CLKD_JTAG 0x00000f00
6555 +#define CLKD_JTAG_SHIFT 8
6556 +#define CLKD_UART 0x000000ff
6557 +
6558 +/* intstatus/intmask */
6559 +#define CI_GPIO 0x00000001 /* gpio intr */
6560 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6561 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6562 +
6563 +/* slow_clk_ctl */
6564 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6565 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6566 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6567 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6568 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6569 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6570 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6571 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6572 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6573 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6574 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
6575 +#define SCC_CD_SHF 16 /* CLockDivider shift */
6576 +
6577 +/* sys_clk_ctl */
6578 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6579 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6580 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6581 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6582 +#define SYCC_HR 0x00000010 /* Force HT */
6583 +#define SYCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
6584 +#define SYCC_CD_SHF 16 /* CLockDivider shift */
6585 +
6586 +/* clockcontrol_n */
6587 +#define CN_N1_MASK 0x3f /* n1 control */
6588 +#define CN_N2_MASK 0x3f00 /* n2 control */
6589 +#define CN_N2_SHIFT 8
6590 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6591 +#define CN_PLLC_SHIFT 16
6592 +
6593 +/* clockcontrol_sb/pci/uart */
6594 +#define CC_M1_MASK 0x3f /* m1 control */
6595 +#define CC_M2_MASK 0x3f00 /* m2 control */
6596 +#define CC_M2_SHIFT 8
6597 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6598 +#define CC_M3_SHIFT 16
6599 +#define CC_MC_MASK 0x1f000000 /* mux control */
6600 +#define CC_MC_SHIFT 24
6601 +
6602 +/* N3M Clock control values for 125Mhz */
6603 +#define CC_125_N 0x0802 /* Default values for bcm4310 */
6604 +#define CC_125_M 0x04020009
6605 +#define CC_125_M25 0x11090009
6606 +#define CC_125_M33 0x11090005
6607 +
6608 +/* N3M Clock control magic field values */
6609 +#define CC_F6_2 0x02 /* A factor of 2 in */
6610 +#define CC_F6_3 0x03 /* 6-bit fields like */
6611 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6612 +#define CC_F6_5 0x09
6613 +#define CC_F6_6 0x11
6614 +#define CC_F6_7 0x21
6615 +
6616 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6617 +
6618 +#define CC_MC_BYPASS 0x08
6619 +#define CC_MC_M1 0x04
6620 +#define CC_MC_M1M2 0x02
6621 +#define CC_MC_M1M2M3 0x01
6622 +#define CC_MC_M1M3 0x11
6623 +
6624 +/* Type 2 Clock control magic field values */
6625 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6626 +#define CC_T2M2_BIAS 3 /* m2 bias */
6627 +
6628 +#define CC_T2MC_M1BYP 1
6629 +#define CC_T2MC_M2BYP 2
6630 +#define CC_T2MC_M3BYP 4
6631 +
6632 +/* Type 6 Clock control magic field values */
6633 +#define CC_T6_MMASK 1 /* bits of interest in m */
6634 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6635 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6636 +#define SB2MIPS_T6(sb) (2 * (sb))
6637 +
6638 +/* Common clock base */
6639 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6640 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6641 +
6642 +/* Flash types in the chipcommon capabilities register */
6643 +#define FLASH_NONE 0x000 /* No flash */
6644 +#define SFLASH_ST 0x100 /* ST serial flash */
6645 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6646 +#define PFLASH 0x700 /* Parallel flash */
6647 +
6648 +/* Bits in the config registers */
6649 +#define CC_CFG_EN 0x0001 /* Enable */
6650 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6651 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
6652 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
6653 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
6654 +#define CC_CFG_EM_IDE 0x000a /* IDE */
6655 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6656 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6657 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6658 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6659 +
6660 +/* Start/busy bit in flashcontrol */
6661 +#define SFLASH_START 0x80000000
6662 +#define SFLASH_BUSY SFLASH_START
6663 +
6664 +/* flashcontrol opcodes for ST flashes */
6665 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6666 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6667 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6668 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6669 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6670 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6671 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6672 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6673 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6674 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6675 +
6676 +/* Status register bits for ST flashes */
6677 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6678 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6679 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6680 +#define SFLASH_ST_BP_SHIFT 2
6681 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6682 +
6683 +/* flashcontrol opcodes for Atmel flashes */
6684 +#define SFLASH_AT_READ 0x07e8
6685 +#define SFLASH_AT_PAGE_READ 0x07d2
6686 +#define SFLASH_AT_BUF1_READ
6687 +#define SFLASH_AT_BUF2_READ
6688 +#define SFLASH_AT_STATUS 0x01d7
6689 +#define SFLASH_AT_BUF1_WRITE 0x0384
6690 +#define SFLASH_AT_BUF2_WRITE 0x0387
6691 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6692 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6693 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6694 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6695 +#define SFLASH_AT_PAGE_ERASE 0x0281
6696 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6697 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6698 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6699 +#define SFLASH_AT_BUF1_LOAD 0x0253
6700 +#define SFLASH_AT_BUF2_LOAD 0x0255
6701 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6702 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6703 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6704 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6705 +
6706 +/* Status register bits for Atmel flashes */
6707 +#define SFLASH_AT_READY 0x80
6708 +#define SFLASH_AT_MISMATCH 0x40
6709 +#define SFLASH_AT_ID_MASK 0x38
6710 +#define SFLASH_AT_ID_SHIFT 3
6711 +
6712 +/* OTP conventions */
6713 +#define OTP_HWBASE 0
6714 +#define OTP_SWLIM 256
6715 +#define OTP_CIDBASE 256
6716 +#define OTP_CIDLIM 260
6717 +
6718 +#define OTP_BOUNDARY 252
6719 +#define OTP_HWSIGN 253
6720 +#define OTP_SWSIGN 254
6721 +#define OTP_CIDSIGN 255
6722 +
6723 +#define OTP_CID 256
6724 +#define OTP_PKG 257
6725 +#define OTP_FID 258
6726 +
6727 +#define OTP_SIGNATURE 0x578a
6728 +#define OTP_MAGIC 0x4e56
6729 +
6730 +#endif /* _SBCHIPC_H */
6731 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6732 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6733 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-08-26 13:44:34.299393496 +0200
6734 @@ -0,0 +1,324 @@
6735 +/*
6736 + * Broadcom SiliconBackplane hardware register definitions.
6737 + *
6738 + * Copyright 2005, Broadcom Corporation
6739 + * All Rights Reserved.
6740 + *
6741 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6742 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6743 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6744 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6745 + * $Id$
6746 + */
6747 +
6748 +#ifndef _SBCONFIG_H
6749 +#define _SBCONFIG_H
6750 +
6751 +/* cpp contortions to concatenate w/arg prescan */
6752 +#ifndef PAD
6753 +#define _PADLINE(line) pad ## line
6754 +#define _XSTR(line) _PADLINE(line)
6755 +#define PAD _XSTR(__LINE__)
6756 +#endif
6757 +
6758 +/*
6759 + * SiliconBackplane Address Map.
6760 + * All regions may not exist on all chips.
6761 + */
6762 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6763 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6764 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6765 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6766 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6767 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6768 +
6769 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6770 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6771 +
6772 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6773 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
6774 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
6775 +
6776 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6777 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6778 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6779 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6780 +
6781 +/* enumeration space related defs */
6782 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6783 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6784 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6785 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6786 +
6787 +/* mips address */
6788 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6789 +
6790 +/*
6791 + * Sonics Configuration Space Registers.
6792 + */
6793 +#define SBIPSFLAG 0x08
6794 +#define SBTPSFLAG 0x18
6795 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6796 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6797 +#define SBADMATCH3 0x60
6798 +#define SBADMATCH2 0x68
6799 +#define SBADMATCH1 0x70
6800 +#define SBIMSTATE 0x90
6801 +#define SBINTVEC 0x94
6802 +#define SBTMSTATELOW 0x98
6803 +#define SBTMSTATEHIGH 0x9c
6804 +#define SBBWA0 0xa0
6805 +#define SBIMCONFIGLOW 0xa8
6806 +#define SBIMCONFIGHIGH 0xac
6807 +#define SBADMATCH0 0xb0
6808 +#define SBTMCONFIGLOW 0xb8
6809 +#define SBTMCONFIGHIGH 0xbc
6810 +#define SBBCONFIG 0xc0
6811 +#define SBBSTATE 0xc8
6812 +#define SBACTCNFG 0xd8
6813 +#define SBFLAGST 0xe8
6814 +#define SBIDLOW 0xf8
6815 +#define SBIDHIGH 0xfc
6816 +
6817 +#ifndef _LANGUAGE_ASSEMBLY
6818 +
6819 +typedef volatile struct _sbconfig {
6820 + uint32 PAD[2];
6821 + uint32 sbipsflag; /* initiator port ocp slave flag */
6822 + uint32 PAD[3];
6823 + uint32 sbtpsflag; /* target port ocp slave flag */
6824 + uint32 PAD[11];
6825 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6826 + uint32 PAD;
6827 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6828 + uint32 PAD[3];
6829 + uint32 sbadmatch3; /* address match3 */
6830 + uint32 PAD;
6831 + uint32 sbadmatch2; /* address match2 */
6832 + uint32 PAD;
6833 + uint32 sbadmatch1; /* address match1 */
6834 + uint32 PAD[7];
6835 + uint32 sbimstate; /* initiator agent state */
6836 + uint32 sbintvec; /* interrupt mask */
6837 + uint32 sbtmstatelow; /* target state */
6838 + uint32 sbtmstatehigh; /* target state */
6839 + uint32 sbbwa0; /* bandwidth allocation table0 */
6840 + uint32 PAD;
6841 + uint32 sbimconfiglow; /* initiator configuration */
6842 + uint32 sbimconfighigh; /* initiator configuration */
6843 + uint32 sbadmatch0; /* address match0 */
6844 + uint32 PAD;
6845 + uint32 sbtmconfiglow; /* target configuration */
6846 + uint32 sbtmconfighigh; /* target configuration */
6847 + uint32 sbbconfig; /* broadcast configuration */
6848 + uint32 PAD;
6849 + uint32 sbbstate; /* broadcast state */
6850 + uint32 PAD[3];
6851 + uint32 sbactcnfg; /* activate configuration */
6852 + uint32 PAD[3];
6853 + uint32 sbflagst; /* current sbflags */
6854 + uint32 PAD[3];
6855 + uint32 sbidlow; /* identification */
6856 + uint32 sbidhigh; /* identification */
6857 +} sbconfig_t;
6858 +
6859 +#endif /* _LANGUAGE_ASSEMBLY */
6860 +
6861 +/* sbipsflag */
6862 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6863 +#define SBIPS_INT1_SHIFT 0
6864 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6865 +#define SBIPS_INT2_SHIFT 8
6866 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6867 +#define SBIPS_INT3_SHIFT 16
6868 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6869 +#define SBIPS_INT4_SHIFT 24
6870 +
6871 +/* sbtpsflag */
6872 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6873 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6874 +
6875 +/* sbtmerrlog */
6876 +#define SBTMEL_CM 0x00000007 /* command */
6877 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6878 +#define SBTMEL_EC 0x0f000000 /* error code */
6879 +#define SBTMEL_ME 0x80000000 /* multiple error */
6880 +
6881 +/* sbimstate */
6882 +#define SBIM_PC 0xf /* pipecount */
6883 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6884 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6885 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6886 +#define SBIM_AP_TK 0x20 /* use token only */
6887 +#define SBIM_AP_RSV 0x30 /* reserved */
6888 +#define SBIM_IBE 0x20000 /* inbanderror */
6889 +#define SBIM_TO 0x40000 /* timeout */
6890 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6891 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6892 +
6893 +/* sbtmstatelow */
6894 +#define SBTML_RESET 0x1 /* reset */
6895 +#define SBTML_REJ 0x2 /* reject */
6896 +#define SBTML_CLK 0x10000 /* clock enable */
6897 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6898 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6899 +#define SBTML_PE 0x40000000 /* pme enable */
6900 +#define SBTML_BE 0x80000000 /* bist enable */
6901 +
6902 +/* sbtmstatehigh */
6903 +#define SBTMH_SERR 0x1 /* serror */
6904 +#define SBTMH_INT 0x2 /* interrupt */
6905 +#define SBTMH_BUSY 0x4 /* busy */
6906 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6907 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6908 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6909 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6910 +#define SBTMH_BISTD 0x80000000 /* bist done */
6911 +
6912 +/* sbbwa0 */
6913 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6914 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6915 +#define SBBWA_TAB1_SHIFT 16
6916 +
6917 +/* sbimconfiglow */
6918 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6919 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6920 +#define SBIMCL_RTO_SHIFT 4
6921 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6922 +#define SBIMCL_CID_SHIFT 16
6923 +
6924 +/* sbimconfighigh */
6925 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6926 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6927 +#define SBIMCH_TEM_SHIFT 4
6928 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6929 +#define SBIMCH_BEM_SHIFT 6
6930 +
6931 +/* sbadmatch0 */
6932 +#define SBAM_TYPE_MASK 0x3 /* address type */
6933 +#define SBAM_AD64 0x4 /* reserved */
6934 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6935 +#define SBAM_ADINT0_SHIFT 3
6936 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6937 +#define SBAM_ADINT1_SHIFT 3
6938 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6939 +#define SBAM_ADINT2_SHIFT 3
6940 +#define SBAM_ADEN 0x400 /* enable */
6941 +#define SBAM_ADNEG 0x800 /* negative decode */
6942 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6943 +#define SBAM_BASE0_SHIFT 8
6944 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6945 +#define SBAM_BASE1_SHIFT 12
6946 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6947 +#define SBAM_BASE2_SHIFT 16
6948 +
6949 +/* sbtmconfiglow */
6950 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6951 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6952 +#define SBTMCL_CO_SHIFT 11
6953 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6954 +#define SBTMCL_IF_SHIFT 18
6955 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6956 +#define SBTMCL_IM_SHIFT 24
6957 +
6958 +/* sbtmconfighigh */
6959 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6960 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6961 +#define SBTMCH_RM_SHIFT 2
6962 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6963 +#define SBTMCH_SM_SHIFT 4
6964 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6965 +#define SBTMCH_EM_SHIFT 8
6966 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6967 +#define SBTMCH_IM_SHIFT 10
6968 +
6969 +/* sbbconfig */
6970 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6971 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6972 +#define SBBC_MAX0_SHIFT 16
6973 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6974 +#define SBBC_MAX1_SHIFT 20
6975 +
6976 +/* sbbstate */
6977 +#define SBBS_SRD 0x1 /* st reg disable */
6978 +#define SBBS_HRD 0x2 /* hold reg disable */
6979 +
6980 +/* sbidlow */
6981 +#define SBIDL_CS_MASK 0x3 /* config space */
6982 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6983 +#define SBIDL_AR_SHIFT 3
6984 +#define SBIDL_SYNCH 0x40 /* sync */
6985 +#define SBIDL_INIT 0x80 /* initiator */
6986 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6987 +#define SBIDL_MINLAT_SHIFT 8
6988 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6989 +#define SBIDL_MAXLAT_SHIFT 12
6990 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6991 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6992 +#define SBIDL_CW_SHIFT 18
6993 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6994 +#define SBIDL_TP_SHIFT 20
6995 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6996 +#define SBIDL_IP_SHIFT 24
6997 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6998 +#define SBIDL_RV_SHIFT 28
6999 +
7000 +/* sbidhigh */
7001 +#define SBIDH_RC_MASK 0xf /* revision code*/
7002 +#define SBIDH_CC_MASK 0xfff0 /* core code */
7003 +#define SBIDH_CC_SHIFT 4
7004 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
7005 +#define SBIDH_VC_SHIFT 16
7006 +
7007 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
7008 +
7009 +/* vendor codes */
7010 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
7011 +
7012 +/* core codes */
7013 +#define SB_CC 0x800 /* chipcommon core */
7014 +#define SB_ILINE20 0x801 /* iline20 core */
7015 +#define SB_SDRAM 0x803 /* sdram core */
7016 +#define SB_PCI 0x804 /* pci core */
7017 +#define SB_MIPS 0x805 /* mips core */
7018 +#define SB_ENET 0x806 /* enet mac core */
7019 +#define SB_CODEC 0x807 /* v90 codec core */
7020 +#define SB_USB 0x808 /* usb 1.1 host/device core */
7021 +#define SB_ADSL 0x809 /* ADSL core */
7022 +#define SB_ILINE100 0x80a /* iline100 core */
7023 +#define SB_IPSEC 0x80b /* ipsec core */
7024 +#define SB_PCMCIA 0x80d /* pcmcia core */
7025 +#define SB_SOCRAM 0x80e /* internal memory core */
7026 +#define SB_MEMC 0x80f /* memc sdram core */
7027 +#define SB_EXTIF 0x811 /* external interface core */
7028 +#define SB_D11 0x812 /* 802.11 MAC core */
7029 +#define SB_MIPS33 0x816 /* mips3302 core */
7030 +#define SB_USB11H 0x817 /* usb 1.1 host core */
7031 +#define SB_USB11D 0x818 /* usb 1.1 device core */
7032 +#define SB_USB20H 0x819 /* usb 2.0 host core */
7033 +#define SB_USB20D 0x81a /* usb 2.0 device core */
7034 +#define SB_SDIOH 0x81b /* sdio host core */
7035 +#define SB_ROBO 0x81c /* roboswitch core */
7036 +#define SB_ATA100 0x81d /* parallel ATA core */
7037 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
7038 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
7039 +
7040 +/* Not really related to Silicon Backplane, but a couple of software
7041 + * conventions for the use the flash space:
7042 + */
7043 +
7044 +/* Minumum amount of flash we support */
7045 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
7046 +
7047 +/* A boot/binary may have an embedded block that describes its size */
7048 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
7049 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
7050 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
7051 +#define BISZ_TXTST_IDX 1 /* 1: text start */
7052 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
7053 +#define BISZ_DATAST_IDX 3 /* 3: text start */
7054 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
7055 +#define BISZ_BSSST_IDX 5 /* 5: text start */
7056 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
7057 +
7058 +#endif /* _SBCONFIG_H */
7059 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
7060 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
7061 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-08-26 13:44:34.300393344 +0200
7062 @@ -0,0 +1,242 @@
7063 +/*
7064 + * Hardware-specific External Interface I/O core definitions
7065 + * for the BCM47xx family of SiliconBackplane-based chips.
7066 + *
7067 + * The External Interface core supports a total of three external chip selects
7068 + * supporting external interfaces. One of the external chip selects is
7069 + * used for Flash, one is used for PCMCIA, and the other may be
7070 + * programmed to support either a synchronous interface or an
7071 + * asynchronous interface. The asynchronous interface can be used to
7072 + * support external devices such as UARTs and the BCM2019 Bluetooth
7073 + * baseband processor.
7074 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7075 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7076 + *
7077 + * Copyright 2005, Broadcom Corporation
7078 + * All Rights Reserved.
7079 + *
7080 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7081 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7082 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7083 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7084 + * $Id$
7085 + */
7086 +
7087 +#ifndef _SBEXTIF_H
7088 +#define _SBEXTIF_H
7089 +
7090 +/* external interface address space */
7091 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
7092 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
7093 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
7094 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
7095 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
7096 +
7097 +/* cpp contortions to concatenate w/arg prescan */
7098 +#ifndef PAD
7099 +#define _PADLINE(line) pad ## line
7100 +#define _XSTR(line) _PADLINE(line)
7101 +#define PAD _XSTR(__LINE__)
7102 +#endif /* PAD */
7103 +
7104 +/*
7105 + * The multiple instances of output and output enable registers
7106 + * are present to allow driver software for multiple cores to control
7107 + * gpio outputs without needing to share a single register pair.
7108 + */
7109 +struct gpiouser {
7110 + uint32 out;
7111 + uint32 outen;
7112 +};
7113 +#define NGPIOUSER 5
7114 +
7115 +typedef volatile struct {
7116 + uint32 corecontrol;
7117 + uint32 extstatus;
7118 + uint32 PAD[2];
7119 +
7120 + /* pcmcia control registers */
7121 + uint32 pcmcia_config;
7122 + uint32 pcmcia_memwait;
7123 + uint32 pcmcia_attrwait;
7124 + uint32 pcmcia_iowait;
7125 +
7126 + /* programmable interface control registers */
7127 + uint32 prog_config;
7128 + uint32 prog_waitcount;
7129 +
7130 + /* flash control registers */
7131 + uint32 flash_config;
7132 + uint32 flash_waitcount;
7133 + uint32 PAD[4];
7134 +
7135 + uint32 watchdog;
7136 +
7137 + /* clock control */
7138 + uint32 clockcontrol_n;
7139 + uint32 clockcontrol_sb;
7140 + uint32 clockcontrol_pci;
7141 + uint32 clockcontrol_mii;
7142 + uint32 PAD[3];
7143 +
7144 + /* gpio */
7145 + uint32 gpioin;
7146 + struct gpiouser gpio[NGPIOUSER];
7147 + uint32 PAD;
7148 + uint32 ejtagouten;
7149 + uint32 gpiointpolarity;
7150 + uint32 gpiointmask;
7151 + uint32 PAD[153];
7152 +
7153 + uint8 uartdata;
7154 + uint8 PAD[3];
7155 + uint8 uartimer;
7156 + uint8 PAD[3];
7157 + uint8 uartfcr;
7158 + uint8 PAD[3];
7159 + uint8 uartlcr;
7160 + uint8 PAD[3];
7161 + uint8 uartmcr;
7162 + uint8 PAD[3];
7163 + uint8 uartlsr;
7164 + uint8 PAD[3];
7165 + uint8 uartmsr;
7166 + uint8 PAD[3];
7167 + uint8 uartscratch;
7168 + uint8 PAD[3];
7169 +} extifregs_t;
7170 +
7171 +/* corecontrol */
7172 +#define CC_UE (1 << 0) /* uart enable */
7173 +
7174 +/* extstatus */
7175 +#define ES_EM (1 << 0) /* endian mode (ro) */
7176 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7177 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7178 +
7179 +/* gpio bit mask */
7180 +#define GPIO_BIT0 (1 << 0)
7181 +#define GPIO_BIT1 (1 << 1)
7182 +#define GPIO_BIT2 (1 << 2)
7183 +#define GPIO_BIT3 (1 << 3)
7184 +#define GPIO_BIT4 (1 << 4)
7185 +#define GPIO_BIT5 (1 << 5)
7186 +#define GPIO_BIT6 (1 << 6)
7187 +#define GPIO_BIT7 (1 << 7)
7188 +
7189 +
7190 +/* pcmcia/prog/flash_config */
7191 +#define CF_EN (1 << 0) /* enable */
7192 +#define CF_EM_MASK 0xe /* mode */
7193 +#define CF_EM_SHIFT 1
7194 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7195 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7196 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7197 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7198 +#define CF_BS (1 << 5) /* byteswap */
7199 +#define CF_CD_MASK 0xc0 /* clock divider */
7200 +#define CF_CD_SHIFT 6
7201 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7202 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7203 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7204 +#define CF_CE (1 << 8) /* clock enable */
7205 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7206 +
7207 +/* pcmcia_memwait */
7208 +#define PM_W0_MASK 0x3f /* waitcount0 */
7209 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7210 +#define PM_W1_SHIFT 8
7211 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7212 +#define PM_W2_SHIFT 16
7213 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7214 +#define PM_W3_SHIFT 24
7215 +
7216 +/* pcmcia_attrwait */
7217 +#define PA_W0_MASK 0x3f /* waitcount0 */
7218 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7219 +#define PA_W1_SHIFT 8
7220 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7221 +#define PA_W2_SHIFT 16
7222 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7223 +#define PA_W3_SHIFT 24
7224 +
7225 +/* pcmcia_iowait */
7226 +#define PI_W0_MASK 0x3f /* waitcount0 */
7227 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7228 +#define PI_W1_SHIFT 8
7229 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7230 +#define PI_W2_SHIFT 16
7231 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7232 +#define PI_W3_SHIFT 24
7233 +
7234 +/* prog_waitcount */
7235 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7236 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7237 +#define PW_W1_SHIFT 8
7238 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7239 +#define PW_W2_SHIFT 16
7240 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7241 +#define PW_W3_SHIFT 24
7242 +
7243 +#define PW_W0 0x0000000c
7244 +#define PW_W1 0x00000a00
7245 +#define PW_W2 0x00020000
7246 +#define PW_W3 0x01000000
7247 +
7248 +/* flash_waitcount */
7249 +#define FW_W0_MASK 0x1f /* waitcount0 */
7250 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7251 +#define FW_W1_SHIFT 8
7252 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7253 +#define FW_W2_SHIFT 16
7254 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7255 +#define FW_W3_SHIFT 24
7256 +
7257 +/* watchdog */
7258 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7259 +
7260 +/* clockcontrol_n */
7261 +#define CN_N1_MASK 0x3f /* n1 control */
7262 +#define CN_N2_MASK 0x3f00 /* n2 control */
7263 +#define CN_N2_SHIFT 8
7264 +
7265 +/* clockcontrol_sb/pci/mii */
7266 +#define CC_M1_MASK 0x3f /* m1 control */
7267 +#define CC_M2_MASK 0x3f00 /* m2 control */
7268 +#define CC_M2_SHIFT 8
7269 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7270 +#define CC_M3_SHIFT 16
7271 +#define CC_MC_MASK 0x1f000000 /* mux control */
7272 +#define CC_MC_SHIFT 24
7273 +
7274 +/* Clock control default values */
7275 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7276 +#define CC_DEF_100 0x04020011
7277 +#define CC_DEF_33 0x11030011
7278 +#define CC_DEF_25 0x11050011
7279 +
7280 +/* Clock control values for 125Mhz */
7281 +#define CC_125_N 0x0802
7282 +#define CC_125_M 0x04020009
7283 +#define CC_125_M25 0x11090009
7284 +#define CC_125_M33 0x11090005
7285 +
7286 +/* Clock control magic field values */
7287 +#define CC_F6_2 0x02 /* A factor of 2 in */
7288 +#define CC_F6_3 0x03 /* 6-bit fields like */
7289 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7290 +#define CC_F6_5 0x09
7291 +#define CC_F6_6 0x11
7292 +#define CC_F6_7 0x21
7293 +
7294 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7295 +
7296 +#define CC_MC_BYPASS 0x08
7297 +#define CC_MC_M1 0x04
7298 +#define CC_MC_M1M2 0x02
7299 +#define CC_MC_M1M2M3 0x01
7300 +#define CC_MC_M1M3 0x11
7301 +
7302 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7303 +
7304 +#endif /* _SBEXTIF_H */
7305 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7306 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7307 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-08-26 13:44:34.300393344 +0200
7308 @@ -0,0 +1,147 @@
7309 +/*
7310 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7311 + *
7312 + * Copyright 2005, Broadcom Corporation
7313 + * All Rights Reserved.
7314 + *
7315 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7316 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7317 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7318 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7319 + *
7320 + * $Id$
7321 + */
7322 +
7323 +#ifndef _SBMEMC_H
7324 +#define _SBMEMC_H
7325 +
7326 +#ifdef _LANGUAGE_ASSEMBLY
7327 +
7328 +#define MEMC_CONTROL 0x00
7329 +#define MEMC_CONFIG 0x04
7330 +#define MEMC_REFRESH 0x08
7331 +#define MEMC_BISTSTAT 0x0c
7332 +#define MEMC_MODEBUF 0x10
7333 +#define MEMC_BKCLS 0x14
7334 +#define MEMC_PRIORINV 0x18
7335 +#define MEMC_DRAMTIM 0x1c
7336 +#define MEMC_INTSTAT 0x20
7337 +#define MEMC_INTMASK 0x24
7338 +#define MEMC_INTINFO 0x28
7339 +#define MEMC_NCDLCTL 0x30
7340 +#define MEMC_RDNCDLCOR 0x34
7341 +#define MEMC_WRNCDLCOR 0x38
7342 +#define MEMC_MISCDLYCTL 0x3c
7343 +#define MEMC_DQSGATENCDL 0x40
7344 +#define MEMC_SPARE 0x44
7345 +#define MEMC_TPADDR 0x48
7346 +#define MEMC_TPDATA 0x4c
7347 +#define MEMC_BARRIER 0x50
7348 +#define MEMC_CORE 0x54
7349 +
7350 +
7351 +#else
7352 +
7353 +/* Sonics side: MEMC core registers */
7354 +typedef volatile struct sbmemcregs {
7355 + uint32 control;
7356 + uint32 config;
7357 + uint32 refresh;
7358 + uint32 biststat;
7359 + uint32 modebuf;
7360 + uint32 bkcls;
7361 + uint32 priorinv;
7362 + uint32 dramtim;
7363 + uint32 intstat;
7364 + uint32 intmask;
7365 + uint32 intinfo;
7366 + uint32 reserved1;
7367 + uint32 ncdlctl;
7368 + uint32 rdncdlcor;
7369 + uint32 wrncdlcor;
7370 + uint32 miscdlyctl;
7371 + uint32 dqsgatencdl;
7372 + uint32 spare;
7373 + uint32 tpaddr;
7374 + uint32 tpdata;
7375 + uint32 barrier;
7376 + uint32 core;
7377 +} sbmemcregs_t;
7378 +
7379 +#endif
7380 +
7381 +/* MEMC Core Init values (OCP ID 0x80f) */
7382 +
7383 +/* For sdr: */
7384 +#define MEMC_SD_CONFIG_INIT 0x00048000
7385 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7386 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7387 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7388 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7389 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7390 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7391 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7392 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7393 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7394 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7395 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7396 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7397 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7398 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7399 +
7400 +
7401 +/* This is for SDRM8X8X4 */
7402 +#define MEMC_SDR_INIT 0x0008
7403 +#define MEMC_SDR_MODE 0x32
7404 +#define MEMC_SDR_NCDL 0x00020032
7405 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7406 +
7407 +/* For ddr: */
7408 +#define MEMC_CONFIG_INIT 0x00048000
7409 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7410 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7411 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7412 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7413 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7414 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7415 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7416 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7417 +#define MEMC_NCDLCTL_INIT 0x00002001
7418 +#define MEMC_CONTROL_INIT0 0x00000002
7419 +#define MEMC_CONTROL_INIT1 0x00000008
7420 +#define MEMC_MODEBUF_INIT0 0x00004000
7421 +#define MEMC_CONTROL_INIT2 0x00000010
7422 +#define MEMC_MODEBUF_INIT1 0x00000100
7423 +#define MEMC_CONTROL_INIT3 0x00000010
7424 +#define MEMC_CONTROL_INIT4 0x00000008
7425 +#define MEMC_REFRESH_INIT 0x0000840f
7426 +#define MEMC_CONTROL_INIT5 0x00000004
7427 +#define MEMC_MODEBUF_INIT2 0x00000000
7428 +#define MEMC_CONTROL_INIT6 0x00000010
7429 +#define MEMC_CONTROL_INIT7 0x00000001
7430 +
7431 +
7432 +/* This is for DDRM16X16X2 */
7433 +#define MEMC_DDR_INIT 0x0009
7434 +#define MEMC_DDR_MODE 0x62
7435 +#define MEMC_DDR_NCDL 0x0005050a
7436 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7437 +
7438 +/* mask for sdr/ddr calibration registers */
7439 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7440 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7441 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7442 +
7443 +/* masks for miscdlyctl registers */
7444 +#define MEMC_MISC_SM_MASK 0x30000000
7445 +#define MEMC_MISC_SM_SHIFT 28
7446 +#define MEMC_MISC_SD_MASK 0x0f000000
7447 +#define MEMC_MISC_SD_SHIFT 24
7448 +
7449 +/* hw threshhold for calculating wr/rd for sdr memc */
7450 +#define MEMC_CD_THRESHOLD 128
7451 +
7452 +/* Low bit of init register says if memc is ddr or sdr */
7453 +#define MEMC_CONFIG_DDR 0x00000001
7454 +
7455 +#endif /* _SBMEMC_H */
7456 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
7457 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
7458 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-08-26 13:44:34.301393192 +0200
7459 @@ -0,0 +1,60 @@
7460 +/*
7461 + * Broadcom SiliconBackplane MIPS definitions
7462 + *
7463 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7464 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7465 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7466 + * interface. The core revision is stored in the SB ID register in SB
7467 + * configuration space.
7468 + *
7469 + * Copyright 2005, Broadcom Corporation
7470 + * All Rights Reserved.
7471 + *
7472 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7473 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7474 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7475 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7476 + *
7477 + * $Id$
7478 + */
7479 +
7480 +#ifndef _SBMIPS_H
7481 +#define _SBMIPS_H
7482 +
7483 +#ifndef _LANGUAGE_ASSEMBLY
7484 +
7485 +/* cpp contortions to concatenate w/arg prescan */
7486 +#ifndef PAD
7487 +#define _PADLINE(line) pad ## line
7488 +#define _XSTR(line) _PADLINE(line)
7489 +#define PAD _XSTR(__LINE__)
7490 +#endif /* PAD */
7491 +
7492 +typedef volatile struct {
7493 + uint32 corecontrol;
7494 + uint32 PAD[2];
7495 + uint32 biststatus;
7496 + uint32 PAD[4];
7497 + uint32 intstatus;
7498 + uint32 intmask;
7499 + uint32 timer;
7500 +} mipsregs_t;
7501 +
7502 +extern uint32 sb_flag(void *sbh);
7503 +extern uint sb_irq(void *sbh);
7504 +
7505 +extern void BCMINIT(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
7506 +
7507 +extern void *sb_jtagm_init(void *sbh, uint clkd, bool exttap);
7508 +extern void sb_jtagm_disable(void *h);
7509 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
7510 +extern void BCMINIT(sb_mips_init)(void *sbh);
7511 +extern uint32 BCMINIT(sb_mips_clock)(void *sbh);
7512 +extern bool BCMINIT(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
7513 +
7514 +extern uint32 BCMINIT(sb_memc_get_ncdl)(void *sbh);
7515 +extern uint32 BCMINIT(sb_mips_get_pfc)(void *sbh);
7516 +
7517 +#endif /* _LANGUAGE_ASSEMBLY */
7518 +
7519 +#endif /* _SBMIPS_H */
7520 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7521 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7522 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-08-26 13:44:34.301393192 +0200
7523 @@ -0,0 +1,117 @@
7524 +/*
7525 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
7526 + *
7527 + * $Id$
7528 + * Copyright 2005, Broadcom Corporation
7529 + * All Rights Reserved.
7530 + *
7531 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7532 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7533 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7534 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7535 + */
7536 +
7537 +#ifndef _SBPCI_H
7538 +#define _SBPCI_H
7539 +
7540 +/* cpp contortions to concatenate w/arg prescan */
7541 +#ifndef PAD
7542 +#define _PADLINE(line) pad ## line
7543 +#define _XSTR(line) _PADLINE(line)
7544 +#define PAD _XSTR(__LINE__)
7545 +#endif
7546 +
7547 +/* Sonics side: PCI core and host control registers */
7548 +typedef struct sbpciregs {
7549 + uint32 control; /* PCI control */
7550 + uint32 PAD[3];
7551 + uint32 arbcontrol; /* PCI arbiter control */
7552 + uint32 PAD[3];
7553 + uint32 intstatus; /* Interrupt status */
7554 + uint32 intmask; /* Interrupt mask */
7555 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7556 + uint32 PAD[9];
7557 + uint32 bcastaddr; /* Sonics broadcast address */
7558 + uint32 bcastdata; /* Sonics broadcast data */
7559 + uint32 PAD[2];
7560 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7561 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7562 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7563 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7564 + uint32 PAD[36];
7565 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7566 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7567 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7568 + uint32 PAD[445];
7569 + uint16 sprom[36]; /* SPROM shadow Area */
7570 + uint32 PAD[46];
7571 +} sbpciregs_t;
7572 +
7573 +/* PCI control */
7574 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7575 +#define PCI_RST 0x02 /* Value driven out to pin */
7576 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7577 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7578 +
7579 +/* PCI arbiter control */
7580 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7581 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7582 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
7583 +#define PCI_PARKID_SHIFT 1
7584 +#define PCI_PARKID_LAST 0 /* Last requestor */
7585 +#define PCI_PARKID_4710 1 /* 4710 */
7586 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
7587 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
7588 +
7589 +/* Interrupt status/mask */
7590 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7591 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7592 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7593 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7594 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7595 +
7596 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7597 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7598 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7599 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7600 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7601 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7602 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7603 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7604 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7605 +
7606 +/* Sonics broadcast address */
7607 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7608 +
7609 +/* Sonics to PCI translation types */
7610 +#define SBTOPCI0_MASK 0xfc000000
7611 +#define SBTOPCI1_MASK 0xfc000000
7612 +#define SBTOPCI2_MASK 0xc0000000
7613 +#define SBTOPCI_MEM 0
7614 +#define SBTOPCI_IO 1
7615 +#define SBTOPCI_CFG0 2
7616 +#define SBTOPCI_CFG1 3
7617 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7618 +#define SBTOPCI_BURST 0x8 /* burst enable */
7619 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7620 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7621 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7622 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7623 +
7624 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
7625 +#define cap_list rsvd_a[0]
7626 +#define bar0_window dev_dep[0x80 - 0x40]
7627 +#define bar1_window dev_dep[0x84 - 0x40]
7628 +#define sprom_control dev_dep[0x88 - 0x40]
7629 +
7630 +#ifndef _LANGUAGE_ASSEMBLY
7631 +
7632 +extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
7633 +extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
7634 +extern void sbpci_ban(uint16 core);
7635 +extern int sbpci_init(void *sbh);
7636 +extern void sbpci_check(void *sbh);
7637 +
7638 +#endif /* !_LANGUAGE_ASSEMBLY */
7639 +
7640 +#endif /* _SBPCI_H */
7641 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7642 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7643 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-08-26 13:44:34.302393040 +0200
7644 @@ -0,0 +1,139 @@
7645 +/*
7646 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7647 + *
7648 + * $Id$
7649 + * Copyright 2005, Broadcom Corporation
7650 + * All Rights Reserved.
7651 + *
7652 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7653 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7654 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7655 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7656 + */
7657 +
7658 +#ifndef _SBPCMCIA_H
7659 +#define _SBPCMCIA_H
7660 +
7661 +
7662 +/* All the addresses that are offsets in attribute space are divided
7663 + * by two to account for the fact that odd bytes are invalid in
7664 + * attribute space and our read/write routines make the space appear
7665 + * as if they didn't exist. Still we want to show the original numbers
7666 + * as documented in the hnd_pcmcia core manual.
7667 + */
7668 +
7669 +/* PCMCIA Function Configuration Registers */
7670 +#define PCMCIA_FCR (0x700 / 2)
7671 +
7672 +#define FCR0_OFF 0
7673 +#define FCR1_OFF (0x40 / 2)
7674 +#define FCR2_OFF (0x80 / 2)
7675 +#define FCR3_OFF (0xc0 / 2)
7676 +
7677 +#define PCMCIA_FCR0 (0x700 / 2)
7678 +#define PCMCIA_FCR1 (0x740 / 2)
7679 +#define PCMCIA_FCR2 (0x780 / 2)
7680 +#define PCMCIA_FCR3 (0x7c0 / 2)
7681 +
7682 +/* Standard PCMCIA FCR registers */
7683 +
7684 +#define PCMCIA_COR 0
7685 +
7686 +#define COR_RST 0x80
7687 +#define COR_LEV 0x40
7688 +#define COR_IRQEN 0x04
7689 +#define COR_BLREN 0x01
7690 +#define COR_FUNEN 0x01
7691 +
7692 +
7693 +#define PCICIA_FCSR (2 / 2)
7694 +#define PCICIA_PRR (4 / 2)
7695 +#define PCICIA_SCR (6 / 2)
7696 +#define PCICIA_ESR (8 / 2)
7697 +
7698 +
7699 +#define PCM_MEMOFF 0x0000
7700 +#define F0_MEMOFF 0x1000
7701 +#define F1_MEMOFF 0x2000
7702 +#define F2_MEMOFF 0x3000
7703 +#define F3_MEMOFF 0x4000
7704 +
7705 +/* Memory base in the function fcr's */
7706 +#define MEM_ADDR0 (0x728 / 2)
7707 +#define MEM_ADDR1 (0x72a / 2)
7708 +#define MEM_ADDR2 (0x72c / 2)
7709 +
7710 +/* PCMCIA base plus Srom access in fcr0: */
7711 +#define PCMCIA_ADDR0 (0x072e / 2)
7712 +#define PCMCIA_ADDR1 (0x0730 / 2)
7713 +#define PCMCIA_ADDR2 (0x0732 / 2)
7714 +
7715 +#define MEM_SEG (0x0734 / 2)
7716 +#define SROM_CS (0x0736 / 2)
7717 +#define SROM_DATAL (0x0738 / 2)
7718 +#define SROM_DATAH (0x073a / 2)
7719 +#define SROM_ADDRL (0x073c / 2)
7720 +#define SROM_ADDRH (0x073e / 2)
7721 +
7722 +/* Values for srom_cs: */
7723 +#define SROM_IDLE 0
7724 +#define SROM_WRITE 1
7725 +#define SROM_READ 2
7726 +#define SROM_WEN 4
7727 +#define SROM_WDS 7
7728 +#define SROM_DONE 8
7729 +
7730 +/* CIS stuff */
7731 +
7732 +/* The CIS stops where the FCRs start */
7733 +#define CIS_SIZE PCMCIA_FCR
7734 +
7735 +/* Standard tuples we know about */
7736 +
7737 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7738 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7739 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7740 +
7741 +/* Function extensions for LANs */
7742 +
7743 +#define LAN_TECH 1 /* Technology type */
7744 +#define LAN_SPEED 2 /* Raw bit rate */
7745 +#define LAN_MEDIA 3 /* Transmission media */
7746 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7747 +#define LAN_CONN 5 /* Connector standard */
7748 +
7749 +
7750 +/* CFTable */
7751 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7752 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7753 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7754 +
7755 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7756 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7757 + */
7758 +
7759 +#define CISTPL_BRCM_HNBU 0x80
7760 +
7761 +/* Subtypes of BRCM_HNBU: */
7762 +
7763 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
7764 + * device id and chiprev
7765 + */
7766 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
7767 +#define HNBU_PAPARMS 0x03 /* Eleven bytes PA parameters */
7768 +#define HNBU_OEM 0x04 /* Eight bytes OEM data */
7769 +#define HNBU_CC 0x05 /* Default country code */
7770 +#define HNBU_AA 0x06 /* Antennas available */
7771 +#define HNBU_AG 0x07 /* Antenna gain */
7772 +#define HNBU_BOARDFLAGS 0x08 /* board flags */
7773 +#define HNBU_LED 0x09 /* LED set */
7774 +
7775 +
7776 +/* sbtmstatelow */
7777 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7778 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7779 +
7780 +/* sbtmstatehigh */
7781 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7782 +
7783 +#endif /* _SBPCMCIA_H */
7784 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7785 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7786 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-08-26 13:44:34.302393040 +0200
7787 @@ -0,0 +1,75 @@
7788 +/*
7789 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7790 + *
7791 + * Copyright 2005, Broadcom Corporation
7792 + * All Rights Reserved.
7793 + *
7794 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7795 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7796 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7797 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7798 + * $Id$
7799 + */
7800 +
7801 +#ifndef _SBSDRAM_H
7802 +#define _SBSDRAM_H
7803 +
7804 +#ifndef _LANGUAGE_ASSEMBLY
7805 +
7806 +/* Sonics side: SDRAM core registers */
7807 +typedef volatile struct sbsdramregs {
7808 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7809 + uint32 config; /* Initializes external SDRAM mode register */
7810 + uint32 refresh; /* Controls external SDRAM refresh rate */
7811 + uint32 pad1;
7812 + uint32 pad2;
7813 +} sbsdramregs_t;
7814 +
7815 +#endif
7816 +
7817 +/* SDRAM initialization control (initcontrol) register bits */
7818 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7819 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7820 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7821 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7822 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7823 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7824 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7825 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7826 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7827 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7828 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7829 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7830 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7831 +
7832 +/* SDRAM configuration (config) register bits */
7833 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7834 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7835 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7836 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7837 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7838 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7839 +
7840 +/* SDRAM refresh control (refresh) register bits */
7841 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7842 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7843 +
7844 +/* SDRAM Core default Init values (OCP ID 0x803) */
7845 +#define SDRAM_INIT MEM4MX16X2
7846 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7847 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7848 +
7849 +#define MEM1MX16 0x009 /* 2 MB */
7850 +#define MEM1MX16X2 0x409 /* 4 MB */
7851 +#define MEM2MX8X2 0x809 /* 4 MB */
7852 +#define MEM2MX8X4 0xc09 /* 8 MB */
7853 +#define MEM2MX32 0x439 /* 8 MB */
7854 +#define MEM4MX16 0x019 /* 8 MB */
7855 +#define MEM4MX16X2 0x419 /* 16 MB */
7856 +#define MEM8MX8X2 0x819 /* 16 MB */
7857 +#define MEM8MX16 0x829 /* 16 MB */
7858 +#define MEM4MX32 0x429 /* 16 MB */
7859 +#define MEM8MX8X4 0xc19 /* 32 MB */
7860 +#define MEM8MX16X2 0xc29 /* 32 MB */
7861 +
7862 +#endif /* _SBSDRAM_H */
7863 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7864 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7865 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-08-26 13:44:34.303392888 +0200
7866 @@ -0,0 +1,37 @@
7867 +/*
7868 + * BCM47XX Sonics SiliconBackplane embedded ram core
7869 + *
7870 + * Copyright 2005, Broadcom Corporation
7871 + * All Rights Reserved.
7872 + *
7873 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7874 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7875 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7876 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7877 + *
7878 + * $Id$
7879 + */
7880 +
7881 +#ifndef _SBSOCRAM_H
7882 +#define _SBSOCRAM_H
7883 +
7884 +#define SOCRAM_MEMSIZE 0x00
7885 +#define SOCRAM_BISTSTAT 0x0c
7886 +
7887 +
7888 +#ifndef _LANGUAGE_ASSEMBLY
7889 +
7890 +/* Memcsocram core registers */
7891 +typedef volatile struct sbsocramregs {
7892 + uint32 memsize;
7893 + uint32 biststat;
7894 +} sbsocramregs_t;
7895 +
7896 +#endif
7897 +
7898 +/* Them memory size is 2 to the power of the following
7899 + * base added to the contents of the memsize register.
7900 + */
7901 +#define SOCRAM_MEMSIZE_BASESHIFT 16
7902 +
7903 +#endif /* _SBSOCRAM_H */
7904 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7905 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7906 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-08-26 13:44:34.303392888 +0200
7907 @@ -0,0 +1,87 @@
7908 +/*
7909 + * Misc utility routines for accessing chip-specific features
7910 + * of Broadcom HNBU SiliconBackplane-based chips.
7911 + *
7912 + * Copyright 2005, Broadcom Corporation
7913 + * All Rights Reserved.
7914 + *
7915 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7916 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7917 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7918 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7919 + *
7920 + * $Id$
7921 + */
7922 +
7923 +#ifndef _sbutils_h_
7924 +#define _sbutils_h_
7925 +
7926 +/*
7927 + * Many of the routines below take an 'sbh' handle as their first arg.
7928 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
7929 + * At any one time, the sbh is logically focused on one particular sb core
7930 + * (the "current core").
7931 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
7932 + */
7933 +
7934 +/* exported externs */
7935 +extern void * BCMINIT(sb_attach)(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
7936 +extern void * BCMINIT(sb_kattach)(void);
7937 +extern void sb_detach(void *sbh);
7938 +extern uint BCMINIT(sb_chip)(void *sbh);
7939 +extern uint BCMINIT(sb_chiprev)(void *sbh);
7940 +extern uint BCMINIT(sb_chipcrev)(void *sbh);
7941 +extern uint BCMINIT(sb_chippkg)(void *sbh);
7942 +extern uint BCMINIT(sb_pcirev)(void *sbh);
7943 +extern uint BCMINIT(sb_pcmciarev)(void *sbh);
7944 +extern uint BCMINIT(sb_boardvendor)(void *sbh);
7945 +extern uint BCMINIT(sb_boardtype)(void *sbh);
7946 +extern uint sb_bus(void *sbh);
7947 +extern uint sb_corelist(void *sbh, uint coreid[]);
7948 +extern uint sb_coreid(void *sbh);
7949 +extern uint sb_coreidx(void *sbh);
7950 +extern uint sb_coreunit(void *sbh);
7951 +extern uint sb_corevendor(void *sbh);
7952 +extern uint sb_corerev(void *sbh);
7953 +extern void *sb_osh(void *sbh);
7954 +extern void *sb_coreregs(void *sbh);
7955 +extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
7956 +extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
7957 +extern bool sb_iscoreup(void *sbh);
7958 +extern void *sb_setcoreidx(void *sbh, uint coreidx);
7959 +extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
7960 +extern void sb_commit(void *sbh);
7961 +extern uint32 sb_base(uint32 admatch);
7962 +extern uint32 sb_size(uint32 admatch);
7963 +extern void sb_core_reset(void *sbh, uint32 bits);
7964 +extern void sb_core_tofixup(void *sbh);
7965 +extern void sb_core_disable(void *sbh, uint32 bits);
7966 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
7967 +extern uint32 sb_clock(void *sbh);
7968 +extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
7969 +extern void sb_pcmcia_init(void *sbh);
7970 +extern void sb_watchdog(void *sbh, uint ticks);
7971 +extern void *sb_gpiosetcore(void *sbh);
7972 +extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
7973 +extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
7974 +extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
7975 +extern uint32 sb_gpioin(void *sbh);
7976 +extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
7977 +extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
7978 +extern void sb_pwrctl_init(void *sbh);
7979 +extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
7980 +extern bool sb_pwrctl_clk(void *sbh, uint mode);
7981 +extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
7982 +extern int sb_pwrctl_slowclk(void *sbh, bool set, uint *div);
7983 +extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
7984 +
7985 +/* pwrctl xtal what flags */
7986 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
7987 +#define PLL 0x2 /* main chip pll */
7988 +
7989 +/* pwrctl clk mode */
7990 +#define CLK_FAST 0 /* force fast (pll) clock */
7991 +#define CLK_SLOW 1 /* force slow clock */
7992 +#define CLK_DYNAMIC 2 /* enable dynamic power control */
7993 +
7994 +#endif /* _sbutils_h_ */
7995 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
7996 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
7997 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-08-26 13:44:34.304392736 +0200
7998 @@ -0,0 +1,36 @@
7999 +/*
8000 + * Broadcom SiliconBackplane chipcommon serial flash interface
8001 + *
8002 + * Copyright 2005, Broadcom Corporation
8003 + * All Rights Reserved.
8004 + *
8005 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8006 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8007 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8008 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8009 + *
8010 + * $Id$
8011 + */
8012 +
8013 +#ifndef _sflash_h_
8014 +#define _sflash_h_
8015 +
8016 +#include <typedefs.h>
8017 +#include <sbchipc.h>
8018 +
8019 +struct sflash {
8020 + uint blocksize; /* Block size */
8021 + uint numblocks; /* Number of blocks */
8022 + uint32 type; /* Type */
8023 + uint size; /* Total size in bytes */
8024 +};
8025 +
8026 +/* Utility functions */
8027 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8028 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8029 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8030 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8031 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8032 +extern struct sflash * sflash_init(chipcregs_t *cc);
8033 +
8034 +#endif /* _sflash_h_ */
8035 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8036 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8037 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-08-26 13:44:34.304392736 +0200
8038 @@ -0,0 +1,33 @@
8039 +/*
8040 + * TRX image file header format.
8041 + *
8042 + * Copyright 2005, Broadcom Corporation
8043 + * All Rights Reserved.
8044 + *
8045 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8046 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8047 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8048 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8049 + *
8050 + * $Id$
8051 + */
8052 +
8053 +#include <typedefs.h>
8054 +
8055 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8056 +#define TRX_VERSION 1
8057 +#define TRX_MAX_LEN 0x3A0000
8058 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8059 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8060 +#define TRX_MAX_OFFSET 3
8061 +
8062 +struct trx_header {
8063 + uint32 magic; /* "HDR0" */
8064 + uint32 len; /* Length of file including header */
8065 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8066 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8067 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8068 +};
8069 +
8070 +/* Compatibility */
8071 +typedef struct trx_header TRXHDR, *PTRXHDR;
8072 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8073 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8074 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-08-26 13:44:34.305392584 +0200
8075 @@ -0,0 +1,322 @@
8076 +/*
8077 + * Copyright 2005, Broadcom Corporation
8078 + * All Rights Reserved.
8079 + *
8080 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8081 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8082 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8083 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8084 + * $Id$
8085 + */
8086 +
8087 +#ifndef _TYPEDEFS_H_
8088 +#define _TYPEDEFS_H_
8089 +
8090 +
8091 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8092 + * typedef file "site_typedefs.h".
8093 + *
8094 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8095 + * section of this file makes inferences about the compile environment
8096 + * based on defined symbols and possibly compiler pragmas.
8097 + *
8098 + * Following these two sections is the "Default Typedefs"
8099 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8100 + * defined. This section has a default set of typedefs and a few
8101 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8102 + */
8103 +
8104 +#ifdef SITE_TYPEDEFS
8105 +
8106 +/*******************************************************************************
8107 + * Site Specific Typedefs
8108 + *******************************************************************************/
8109 +
8110 +#include "site_typedefs.h"
8111 +
8112 +#else
8113 +
8114 +/*******************************************************************************
8115 + * Inferred Typedefs
8116 + *******************************************************************************/
8117 +
8118 +/* Infer the compile environment based on preprocessor symbols and pramas.
8119 + * Override type definitions as needed, and include configuration dependent
8120 + * header files to define types.
8121 + */
8122 +
8123 +#ifdef __cplusplus
8124 +
8125 +#define TYPEDEF_BOOL
8126 +#ifndef FALSE
8127 +#define FALSE false
8128 +#endif
8129 +#ifndef TRUE
8130 +#define TRUE true
8131 +#endif
8132 +
8133 +#else /* ! __cplusplus */
8134 +
8135 +#if defined(_WIN32)
8136 +
8137 +#define TYPEDEF_BOOL
8138 +typedef unsigned char bool; /* consistent w/BOOL */
8139 +
8140 +#endif /* _WIN32 */
8141 +
8142 +#endif /* ! __cplusplus */
8143 +
8144 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8145 +#if defined(_WIN64)
8146 +#include <basetsd.h>
8147 +#define TYPEDEF_UINTPTR
8148 +typedef ULONG_PTR uintptr;
8149 +#endif
8150 +
8151 +#ifdef _MSC_VER /* Microsoft C */
8152 +#define TYPEDEF_INT64
8153 +#define TYPEDEF_UINT64
8154 +typedef signed __int64 int64;
8155 +typedef unsigned __int64 uint64;
8156 +#endif
8157 +
8158 +#if defined(MACOSX) && defined(KERNEL)
8159 +#define TYPEDEF_BOOL
8160 +#endif
8161 +
8162 +
8163 +#if defined(linux)
8164 +#define TYPEDEF_UINT
8165 +#define TYPEDEF_USHORT
8166 +#define TYPEDEF_ULONG
8167 +#endif
8168 +
8169 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8170 +#define TYPEDEF_UINT
8171 +#define TYPEDEF_USHORT
8172 +#endif
8173 +
8174 +
8175 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8176 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8177 +#define TYPEDEF_INT64
8178 +#define TYPEDEF_UINT64
8179 +#endif
8180 +
8181 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8182 + * for singned or unsigned */
8183 +#if defined(__ICL)
8184 +
8185 +#define TYPEDEF_INT64
8186 +
8187 +#if defined(__STDC__)
8188 +#define TYPEDEF_UINT64
8189 +#endif
8190 +
8191 +#endif /* __ICL */
8192 +
8193 +
8194 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
8195 +
8196 +/* pick up ushort & uint from standard types.h */
8197 +#if defined(linux) && defined(__KERNEL__)
8198 +
8199 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8200 +
8201 +#else
8202 +
8203 +#include <sys/types.h>
8204 +
8205 +#endif
8206 +
8207 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
8208 +
8209 +#if defined(MACOSX) && defined(KERNEL)
8210 +#include <IOKit/IOTypes.h>
8211 +#endif
8212 +
8213 +
8214 +/* use the default typedefs in the next section of this file */
8215 +#define USE_TYPEDEF_DEFAULTS
8216 +
8217 +#endif /* SITE_TYPEDEFS */
8218 +
8219 +
8220 +/*******************************************************************************
8221 + * Default Typedefs
8222 + *******************************************************************************/
8223 +
8224 +#ifdef USE_TYPEDEF_DEFAULTS
8225 +#undef USE_TYPEDEF_DEFAULTS
8226 +
8227 +#ifndef TYPEDEF_BOOL
8228 +typedef /*@abstract@*/ unsigned char bool;
8229 +#endif
8230 +
8231 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
8232 +
8233 +#ifndef TYPEDEF_UCHAR
8234 +typedef unsigned char uchar;
8235 +#endif
8236 +
8237 +#ifndef TYPEDEF_USHORT
8238 +typedef unsigned short ushort;
8239 +#endif
8240 +
8241 +#ifndef TYPEDEF_UINT
8242 +typedef unsigned int uint;
8243 +#endif
8244 +
8245 +#ifndef TYPEDEF_ULONG
8246 +typedef unsigned long ulong;
8247 +#endif
8248 +
8249 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
8250 +
8251 +#ifndef TYPEDEF_UINT8
8252 +typedef unsigned char uint8;
8253 +#endif
8254 +
8255 +#ifndef TYPEDEF_UINT16
8256 +typedef unsigned short uint16;
8257 +#endif
8258 +
8259 +#ifndef TYPEDEF_UINT32
8260 +typedef unsigned int uint32;
8261 +#endif
8262 +
8263 +#ifndef TYPEDEF_UINT64
8264 +typedef unsigned long long uint64;
8265 +#endif
8266 +
8267 +#ifndef TYPEDEF_UINTPTR
8268 +typedef unsigned int uintptr;
8269 +#endif
8270 +
8271 +#ifndef TYPEDEF_INT8
8272 +typedef signed char int8;
8273 +#endif
8274 +
8275 +#ifndef TYPEDEF_INT16
8276 +typedef signed short int16;
8277 +#endif
8278 +
8279 +#ifndef TYPEDEF_INT32
8280 +typedef signed int int32;
8281 +#endif
8282 +
8283 +#ifndef TYPEDEF_INT64
8284 +typedef signed long long int64;
8285 +#endif
8286 +
8287 +/*----------------------- define float32/64, float_t -----------------------*/
8288 +
8289 +#ifndef TYPEDEF_FLOAT32
8290 +typedef float float32;
8291 +#endif
8292 +
8293 +#ifndef TYPEDEF_FLOAT64
8294 +typedef double float64;
8295 +#endif
8296 +
8297 +/*
8298 + * abstracted floating point type allows for compile time selection of
8299 + * single or double precision arithmetic. Compiling with -DFLOAT32
8300 + * selects single precision; the default is double precision.
8301 + */
8302 +
8303 +#ifndef TYPEDEF_FLOAT_T
8304 +
8305 +#if defined(FLOAT32)
8306 +typedef float32 float_t;
8307 +#else /* default to double precision floating point */
8308 +typedef float64 float_t;
8309 +#endif
8310 +
8311 +#endif /* TYPEDEF_FLOAT_T */
8312 +
8313 +/*----------------------- define macro values -----------------------------*/
8314 +
8315 +#ifndef FALSE
8316 +#define FALSE 0
8317 +#endif
8318 +
8319 +#ifndef TRUE
8320 +#define TRUE 1
8321 +#endif
8322 +
8323 +#ifndef NULL
8324 +#define NULL 0
8325 +#endif
8326 +
8327 +#ifndef OFF
8328 +#define OFF 0
8329 +#endif
8330 +
8331 +#ifndef ON
8332 +#define ON 1
8333 +#endif
8334 +
8335 +#define AUTO (-1)
8336 +
8337 +/* Reclaiming text and data :
8338 + The following macros specify special linker sections that can be reclaimed
8339 + after a system is considered 'up'.
8340 + */
8341 +#if defined(__GNUC__) && defined(BCMRECLAIM)
8342 +extern bool bcmreclaimed;
8343 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
8344 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
8345 +#define BCMINIT(_id) _id##_ini
8346 +#else
8347 +#define BCMINITDATA(_data) _data
8348 +#define BCMINITFN(_fn) _fn
8349 +#define BCMINIT(_id) _id
8350 +#define bcmreclaimed 0
8351 +#endif
8352 +
8353 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
8354 +
8355 +#ifndef PTRSZ
8356 +#define PTRSZ sizeof (char*)
8357 +#endif
8358 +
8359 +#ifndef INLINE
8360 +
8361 +#ifdef _MSC_VER
8362 +
8363 +#define INLINE __inline
8364 +
8365 +#elif __GNUC__
8366 +
8367 +#define INLINE __inline__
8368 +
8369 +#else
8370 +
8371 +#define INLINE
8372 +
8373 +#endif /* _MSC_VER */
8374 +
8375 +#endif /* INLINE */
8376 +
8377 +#undef TYPEDEF_BOOL
8378 +#undef TYPEDEF_UCHAR
8379 +#undef TYPEDEF_USHORT
8380 +#undef TYPEDEF_UINT
8381 +#undef TYPEDEF_ULONG
8382 +#undef TYPEDEF_UINT8
8383 +#undef TYPEDEF_UINT16
8384 +#undef TYPEDEF_UINT32
8385 +#undef TYPEDEF_UINT64
8386 +#undef TYPEDEF_UINTPTR
8387 +#undef TYPEDEF_INT8
8388 +#undef TYPEDEF_INT16
8389 +#undef TYPEDEF_INT32
8390 +#undef TYPEDEF_INT64
8391 +#undef TYPEDEF_FLOAT32
8392 +#undef TYPEDEF_FLOAT64
8393 +#undef TYPEDEF_FLOAT_T
8394 +
8395 +#endif /* USE_TYPEDEF_DEFAULTS */
8396 +
8397 +#endif /* _TYPEDEFS_H_ */
8398 diff -urN linux.old/arch/mips/bcm947xx/include/wlioctl.h linux.dev/arch/mips/bcm947xx/include/wlioctl.h
8399 --- linux.old/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
8400 +++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-08-26 13:44:34.307392280 +0200
8401 @@ -0,0 +1,825 @@
8402 +/*
8403 + * Custom OID/ioctl definitions for
8404 + * Broadcom 802.11abg Networking Device Driver
8405 + *
8406 + * Definitions subject to change without notice.
8407 + *
8408 + * Copyright 2005, Broadcom Corporation
8409 + * All Rights Reserved.
8410 + *
8411 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8412 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8413 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8414 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8415 + *
8416 + * $Id$
8417 + */
8418 +
8419 +#ifndef _wlioctl_h_
8420 +#define _wlioctl_h_
8421 +
8422 +#include <typedefs.h>
8423 +#include <proto/ethernet.h>
8424 +#include <proto/802.11.h>
8425 +
8426 +/* require default structure packing */
8427 +#if !defined(__GNUC__)
8428 +#pragma pack(push,8)
8429 +#endif
8430 +
8431 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
8432 +
8433 +typedef struct wl_rateset {
8434 + uint32 count; /* # rates in this set */
8435 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
8436 +} wl_rateset_t;
8437 +
8438 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
8439 +#define WL_CHANSPEC_BAND_MASK 0xf000
8440 +#define WL_CHANSPEC_BAND_SHIFT 12
8441 +#define WL_CHANSPEC_BAND_A 0x1000
8442 +#define WL_CHANSPEC_BAND_B 0x2000
8443 +
8444 +/*
8445 + * Per-bss information structure.
8446 + */
8447 +
8448 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
8449 +
8450 +typedef struct wl_bss_info {
8451 + uint32 version; /* version field */
8452 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
8453 + struct ether_addr BSSID;
8454 + uint16 beacon_period; /* units are Kusec */
8455 + uint16 capability; /* Capability information */
8456 + uint8 SSID_len;
8457 + uint8 SSID[32];
8458 + struct {
8459 + uint count; /* # rates in this set */
8460 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
8461 + } rateset; /* supported rates */
8462 + uint8 channel; /* Channel no. */
8463 + uint16 atim_window; /* units are Kusec */
8464 + uint8 dtim_period; /* DTIM period */
8465 + int16 RSSI; /* receive signal strength (in dBm) */
8466 + int8 phy_noise; /* noise (in dBm) */
8467 + uint32 ie_length; /* byte length of Information Elements */
8468 + /* variable length Information Elements */
8469 +} wl_bss_info_t;
8470 +
8471 +typedef struct wlc_ssid {
8472 + uint32 SSID_len;
8473 + uchar SSID[32];
8474 +} wlc_ssid_t;
8475 +
8476 +typedef struct wl_scan_params {
8477 + wlc_ssid_t ssid; /* default is {0, ""} */
8478 + struct ether_addr bssid;/* default is bcast */
8479 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
8480 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
8481 + int32 nprobes; /* -1 use default, number of probes per channel */
8482 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
8483 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
8484 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
8485 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
8486 + uint16 channel_list[1]; /* list of chanspecs */
8487 +} wl_scan_params_t;
8488 +/* size of wl_scan_params not including variable length array */
8489 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
8490 +
8491 +typedef struct wl_scan_results {
8492 + uint32 buflen;
8493 + uint32 version;
8494 + uint32 count;
8495 + wl_bss_info_t bss_info[1];
8496 +} wl_scan_results_t;
8497 +/* size of wl_scan_results not including variable length array */
8498 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
8499 +
8500 +/* uint32 list */
8501 +typedef struct wl_uint32_list {
8502 + /* in - # of elements, out - # of entries */
8503 + uint32 count;
8504 + /* variable length uint32 list */
8505 + uint32 element[1];
8506 +} wl_uint32_list_t;
8507 +
8508 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
8509 +
8510 +typedef struct wl_channels_in_country {
8511 + uint32 buflen;
8512 + uint32 band;
8513 + char country_abbrev[WLC_CNTRY_BUF_SZ];
8514 + uint32 count;
8515 + uint32 channel[1];
8516 +} wl_channels_in_country_t;
8517 +
8518 +typedef struct wl_country_list {
8519 + uint32 buflen;
8520 + uint32 band_set;
8521 + uint32 band;
8522 + uint32 count;
8523 + char country_abbrev[1];
8524 +} wl_country_list_t;
8525 +
8526 +#define WL_RM_TYPE_BASIC 1
8527 +#define WL_RM_TYPE_CCA 2
8528 +#define WL_RM_TYPE_RPI 3
8529 +
8530 +#define WL_RM_FLAG_PARALLEL (1<<0)
8531 +
8532 +#define WL_RM_FLAG_LATE (1<<1)
8533 +#define WL_RM_FLAG_INCAPABLE (1<<2)
8534 +#define WL_RM_FLAG_REFUSED (1<<3)
8535 +
8536 +typedef struct wl_rm_req_elt {
8537 + int8 type;
8538 + int8 flags;
8539 + uint16 chanspec;
8540 + uint32 token; /* token for this measurement */
8541 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
8542 + uint32 tsf_l; /* TSF low 32-bits */
8543 + uint32 dur; /* TUs */
8544 +} wl_rm_req_elt_t;
8545 +
8546 +typedef struct wl_rm_req {
8547 + uint32 token; /* overall measurement set token */
8548 + uint32 count; /* number of measurement reqests */
8549 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
8550 +} wl_rm_req_t;
8551 +#define WL_RM_REQ_FIXED_LEN 8
8552 +
8553 +typedef struct wl_rm_rep_elt {
8554 + int8 type;
8555 + int8 flags;
8556 + uint16 chanspec;
8557 + uint32 token; /* token for this measurement */
8558 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
8559 + uint32 tsf_l; /* TSF low 32-bits */
8560 + uint32 dur; /* TUs */
8561 + uint32 len; /* byte length of data block */
8562 + uint8 data[1]; /* variable length data block */
8563 +} wl_rm_rep_elt_t;
8564 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
8565 +
8566 +#define WL_RPI_REP_BIN_NUM 8
8567 +typedef struct wl_rm_rpi_rep {
8568 + uint8 rpi[WL_RPI_REP_BIN_NUM];
8569 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
8570 +} wl_rm_rpi_rep_t;
8571 +
8572 +typedef struct wl_rm_rep {
8573 + uint32 token; /* overall measurement set token */
8574 + uint32 len; /* length of measurement report block */
8575 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
8576 +} wl_rm_rep_t;
8577 +#define WL_RM_REP_FIXED_LEN 8
8578 +
8579 +
8580 +#if defined(BCMSUP_PSK)
8581 +typedef enum sup_auth_status {
8582 + WLC_SUP_DISCONNECTED = 0,
8583 + WLC_SUP_CONNECTING,
8584 + WLC_SUP_IDREQUIRED,
8585 + WLC_SUP_AUTHENTICATING,
8586 + WLC_SUP_AUTHENTICATED,
8587 + WLC_SUP_KEYXCHANGE,
8588 + WLC_SUP_KEYED
8589 +} sup_auth_status_t;
8590 +#endif /* BCMCCX | BCMSUP_PSK */
8591 +
8592 +/* Enumerate crypto algorithms */
8593 +#define CRYPTO_ALGO_OFF 0
8594 +#define CRYPTO_ALGO_WEP1 1
8595 +#define CRYPTO_ALGO_TKIP 2
8596 +#define CRYPTO_ALGO_WEP128 3
8597 +#define CRYPTO_ALGO_AES_CCM 4
8598 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
8599 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
8600 +#define CRYPTO_ALGO_NALG 7
8601 +
8602 +#define WSEC_GEN_MIC_ERROR 0x0001
8603 +#define WSEC_GEN_REPLAY 0x0002
8604 +
8605 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
8606 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
8607 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
8608 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
8609 +
8610 +typedef struct wl_wsec_key {
8611 + uint32 index; /* key index */
8612 + uint32 len; /* key length */
8613 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
8614 + uint32 pad_1[18];
8615 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
8616 + uint32 flags; /* misc flags */
8617 + uint32 pad_2[2];
8618 + int pad_3;
8619 + int iv_initialized; /* has IV been initialized already? */
8620 + int pad_4;
8621 + /* Rx IV */
8622 + struct {
8623 + uint32 hi; /* upper 32 bits of IV */
8624 + uint16 lo; /* lower 16 bits of IV */
8625 + } rxiv;
8626 + uint32 pad_5[2];
8627 + struct ether_addr ea; /* per station */
8628 +} wl_wsec_key_t;
8629 +
8630 +
8631 +#define WSEC_MIN_PSK_LEN 8
8632 +#define WSEC_MAX_PSK_LEN 64
8633 +
8634 +/* Flag for key material needing passhash'ing */
8635 +#define WSEC_PASSPHRASE (1<<0)
8636 +
8637 +/* recepticle for WLC_SET_WSEC_PMK parameter */
8638 +typedef struct {
8639 + ushort key_len; /* octets in key material */
8640 + ushort flags; /* key handling qualification */
8641 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
8642 +} wsec_pmk_t;
8643 +
8644 +/* wireless security bitvec */
8645 +#define WEP_ENABLED 1
8646 +#define TKIP_ENABLED 2
8647 +#define AES_ENABLED 4
8648 +#define WSEC_SWFLAG 8
8649 +
8650 +/* WPA authentication mode bitvec */
8651 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
8652 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
8653 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
8654 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
8655 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
8656 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
8657 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
8658 +
8659 +typedef struct wl_led_info {
8660 + uint32 index; /* led index */
8661 + uint32 behavior;
8662 + bool activehi;
8663 +} wl_led_info_t;
8664 +
8665 +/*
8666 + * definitions for driver messages passed from WL to NAS.
8667 + */
8668 +/* Use this to recognize wpa and 802.1x driver messages. */
8669 +static const uint8 wl_wpa_snap_template[] =
8670 + { 0xaa, 0xaa, 0x03, 0x00, 0x90, 0x4c };
8671 +
8672 +#define WL_WPA_MSG_IFNAME_MAX 16
8673 +
8674 +/* WPA driver message */
8675 +typedef struct wl_wpa_header {
8676 + struct ether_header eth;
8677 + struct dot11_llc_snap_header snap;
8678 + uint8 version;
8679 + uint8 type;
8680 + /* version 2 additions */
8681 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8682 + /* version specific data */
8683 + /* uint8 data[1]; */
8684 +} wl_wpa_header_t;
8685 +
8686 +#define WL_WPA_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
8687 +
8688 +/* WPA driver message ethertype - private between wlc and nas */
8689 +#define WL_WPA_ETHER_TYPE 0x9999
8690 +
8691 +/* WPA driver message current version */
8692 +#define WL_WPA_MSG_VERSION 2
8693 +
8694 +/* Type field values for the 802.2 driver messages for WPA. */
8695 +#define WLC_ASSOC_MSG 1
8696 +#define WLC_DISASSOC_MSG 2
8697 +#define WLC_PTK_MIC_MSG 3
8698 +#define WLC_GTK_MIC_MSG 4
8699 +
8700 +/* 802.1x driver message */
8701 +typedef struct wl_eapol_header {
8702 + struct ether_header eth;
8703 + struct dot11_llc_snap_header snap;
8704 + uint8 version;
8705 + uint8 reserved;
8706 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8707 + /* version specific data */
8708 + /* uint8 802_1x_msg[1]; */
8709 +} wl_eapol_header_t;
8710 +
8711 +#define WL_EAPOL_HEADER_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN + 2 + WL_WPA_MSG_IFNAME_MAX)
8712 +
8713 +/* 802.1x driver message ethertype - private between wlc and nas */
8714 +#define WL_EAPOL_ETHER_TYPE 0x999A
8715 +
8716 +/* 802.1x driver message current version */
8717 +#define WL_EAPOL_MSG_VERSION 1
8718 +
8719 +#define WL_SECPVT_DATA_LEN (ETHER_HDR_LEN + 4 + WL_WPA_MSG_IFNAME_MAX)
8720 +
8721 +/* message header for the private data exchange between nas and wl*/
8722 +typedef struct wl_secpvt_data {
8723 + struct ether_header eth; /* use the Type field in the eth header with the private type*/
8724 + uint8 version;
8725 + uint8 sub_type;
8726 + uint16 data_len;
8727 + char ifname[WL_WPA_MSG_IFNAME_MAX];
8728 + /* version specific data */
8729 + /* uint8 802_1x_msg[1]; */
8730 +}wl_secpvt_data_t;
8731 +
8732 +
8733 +/* srom read/write struct passed through ioctl */
8734 +typedef struct {
8735 + uint byteoff; /* byte offset */
8736 + uint nbytes; /* number of bytes */
8737 + uint16 buf[1];
8738 +} srom_rw_t;
8739 +
8740 +/* R_REG and W_REG struct passed through ioctl */
8741 +typedef struct {
8742 + uint32 byteoff; /* byte offset of the field in d11regs_t */
8743 + uint32 val; /* read/write value of the field */
8744 + uint32 size; /* sizeof the field */
8745 +} rw_reg_t;
8746 +
8747 +/* Structure used by GET/SET_ATTEN ioctls */
8748 +typedef struct {
8749 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
8750 + uint16 bb; /* Baseband attenuation */
8751 + uint16 radio; /* Radio attenuation */
8752 + uint16 txctl1; /* Radio TX_CTL1 value */
8753 +} atten_t;
8754 +
8755 +/* Used to get specific STA parameters */
8756 +typedef struct {
8757 + uint32 val;
8758 + struct ether_addr ea;
8759 +} scb_val_t;
8760 +
8761 +/* Event data type */
8762 +typedef struct {
8763 + uint msg; /* Message (see below) */
8764 + struct ether_addr *addr; /* Station address (if applicable) */
8765 + uint status; /* Status code (see below) */
8766 + uint reason; /* Reason code (if applicable) */
8767 + uint auth_type; /* WLC_E_AUTH */
8768 + bool link; /* WLC_E_LINK */
8769 + bool group; /* WLC_E_MIC_ERROR */
8770 + bool flush_txq; /* WLC_E_MIC_ERROR */
8771 +} wlc_event_t;
8772 +
8773 +typedef struct {
8774 + uint16 ver; /* version of this struct */
8775 + uint16 len; /* length in bytes of this structure */
8776 + uint16 cap; /* sta's advertized capabilities */
8777 + uint32 flags; /* flags defined below */
8778 + uint32 idle; /* time since data pkt rx'd from sta */
8779 + struct ether_addr ea; /* Station address */
8780 + wl_rateset_t rateset; /* rateset in use */
8781 + uint32 in; /* seconds elapsed since associated */
8782 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
8783 +} sta_info_t;
8784 +
8785 +#define WL_STA_VER 2
8786 +
8787 +/* flags fields */
8788 +#define WL_STA_BRCM 0x01
8789 +#define WL_STA_WME 0x02
8790 +#define WL_STA_ABCAP 0x04
8791 +#define WL_STA_AUTHE 0x08
8792 +#define WL_STA_ASSOC 0x10
8793 +#define WL_STA_AUTHO 0x20
8794 +#define WL_STA_WDS 0x40
8795 +#define WL_WDS_LINKUP 0x80
8796 +
8797 +/* Event messages */
8798 +#define WLC_E_SET_SSID 1
8799 +#define WLC_E_JOIN 2
8800 +#define WLC_E_START 3
8801 +#define WLC_E_AUTH 4
8802 +#define WLC_E_AUTH_IND 5
8803 +#define WLC_E_DEAUTH 6
8804 +#define WLC_E_DEAUTH_IND 7
8805 +#define WLC_E_ASSOC 8
8806 +#define WLC_E_ASSOC_IND 9
8807 +#define WLC_E_REASSOC 10
8808 +#define WLC_E_REASSOC_IND 11
8809 +#define WLC_E_DISASSOC 12
8810 +#define WLC_E_DISASSOC_IND 13
8811 +#define WLC_E_QUIET_START 14 /* 802.11h Quiet period started */
8812 +#define WLC_E_QUIET_END 15 /* 802.11h Quiet period ended */
8813 +#define WLC_E_GOT_BEACONS 16
8814 +#define WLC_E_LINK 17 /* Link indication */
8815 +#define WLC_E_MIC_ERROR 18 /* TKIP MIC error occurred */
8816 +#define WLC_E_NDIS_LINK 19 /* NDIS style link indication */
8817 +#define WLC_E_ROAM 20
8818 +#define WLC_E_TXFAIL 21 /* dot11FailedCount (txfail) */
8819 +#define WLC_E_LAST 22
8820 +
8821 +/* Event status codes */
8822 +#define WLC_E_STATUS_SUCCESS 0
8823 +#define WLC_E_STATUS_FAIL 1
8824 +#define WLC_E_STATUS_TIMEOUT 2
8825 +#define WLC_E_STATUS_NO_NETWORKS 3
8826 +#define WLC_E_STATUS_ABORT 4
8827 +
8828 +typedef struct wlc_event_cb {
8829 + uint msg; /* Event message or 0 for all */
8830 + void (*fn)(void *, wlc_event_t *); /* Callback function */
8831 + void *context; /* Passed to callback function */
8832 + struct wlc_event_cb *next; /* Next in the chain */
8833 +} wlc_event_cb_t;
8834 +
8835 +/*
8836 + * Country locale determines which channels are available to us.
8837 + */
8838 +typedef enum _wlc_locale {
8839 + WLC_WW = 0, /* Worldwide */
8840 + WLC_THA, /* Thailand */
8841 + WLC_ISR, /* Israel */
8842 + WLC_JDN, /* Jordan */
8843 + WLC_PRC, /* China */
8844 + WLC_JPN, /* Japan */
8845 + WLC_FCC, /* USA */
8846 + WLC_EUR, /* Europe */
8847 + WLC_USL, /* US Low Band only */
8848 + WLC_JPH, /* Japan High Band only */
8849 + WLC_ALL, /* All the channels in this band */
8850 + WLC_11D, /* Represents locale recieved by 11d beacons */
8851 + WLC_LAST_LOCALE,
8852 + WLC_UNDEFINED_LOCALE = 0xf
8853 +} wlc_locale_t;
8854 +
8855 +/* channel encoding */
8856 +typedef struct channel_info {
8857 + int hw_channel;
8858 + int target_channel;
8859 + int scan_channel;
8860 +} channel_info_t;
8861 +
8862 +/* For ioctls that take a list of MAC addresses */
8863 +struct maclist {
8864 + uint count; /* number of MAC addresses */
8865 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
8866 +};
8867 +
8868 +/* get pkt count struct passed through ioctl */
8869 +typedef struct get_pktcnt {
8870 + uint rx_good_pkt;
8871 + uint rx_bad_pkt;
8872 + uint tx_good_pkt;
8873 + uint tx_bad_pkt;
8874 +} get_pktcnt_t;
8875 +
8876 +/* Linux network driver ioctl encoding */
8877 +typedef struct wl_ioctl {
8878 + uint cmd; /* common ioctl definition */
8879 + void *buf; /* pointer to user buffer */
8880 + uint len; /* length of user buffer */
8881 + bool set; /* get or set request (optional) */
8882 + uint used; /* bytes read or written (optional) */
8883 + uint needed; /* bytes needed (optional) */
8884 +} wl_ioctl_t;
8885 +
8886 +/*
8887 + * Structure for passing hardware and software
8888 + * revision info up from the driver.
8889 + */
8890 +typedef struct wlc_rev_info {
8891 + uint vendorid; /* PCI vendor id */
8892 + uint deviceid; /* device id of chip */
8893 + uint radiorev; /* radio revision */
8894 + uint chiprev; /* chip revision */
8895 + uint corerev; /* core revision */
8896 + uint boardid; /* board identifier (usu. PCI sub-device id) */
8897 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
8898 + uint boardrev; /* board revision */
8899 + uint driverrev; /* driver version */
8900 + uint ucoderev; /* microcode version */
8901 + uint bus; /* bus type */
8902 + uint chipnum; /* chip number */
8903 +} wlc_rev_info_t;
8904 +
8905 +/* check this magic number */
8906 +#define WLC_IOCTL_MAGIC 0x14e46c77
8907 +
8908 +/* bump this number if you change the ioctl interface */
8909 +#define WLC_IOCTL_VERSION 1
8910 +
8911 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
8912 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
8913 +
8914 +/* common ioctl definitions */
8915 +#define WLC_GET_MAGIC 0
8916 +#define WLC_GET_VERSION 1
8917 +#define WLC_UP 2
8918 +#define WLC_DOWN 3
8919 +#define WLC_DUMP 6
8920 +#define WLC_GET_MSGLEVEL 7
8921 +#define WLC_SET_MSGLEVEL 8
8922 +#define WLC_GET_PROMISC 9
8923 +#define WLC_SET_PROMISC 10
8924 +#define WLC_GET_RATE 12
8925 +#define WLC_SET_RATE 13
8926 +#define WLC_GET_INSTANCE 14
8927 +#define WLC_GET_FRAG 15
8928 +#define WLC_SET_FRAG 16
8929 +#define WLC_GET_RTS 17
8930 +#define WLC_SET_RTS 18
8931 +#define WLC_GET_INFRA 19
8932 +#define WLC_SET_INFRA 20
8933 +#define WLC_GET_AUTH 21
8934 +#define WLC_SET_AUTH 22
8935 +#define WLC_GET_BSSID 23
8936 +#define WLC_SET_BSSID 24
8937 +#define WLC_GET_SSID 25
8938 +#define WLC_SET_SSID 26
8939 +#define WLC_RESTART 27
8940 +#define WLC_GET_CHANNEL 29
8941 +#define WLC_SET_CHANNEL 30
8942 +#define WLC_GET_SRL 31
8943 +#define WLC_SET_SRL 32
8944 +#define WLC_GET_LRL 33
8945 +#define WLC_SET_LRL 34
8946 +#define WLC_GET_PLCPHDR 35
8947 +#define WLC_SET_PLCPHDR 36
8948 +#define WLC_GET_RADIO 37
8949 +#define WLC_SET_RADIO 38
8950 +#define WLC_GET_PHYTYPE 39
8951 +#define WLC_GET_WEP 42
8952 +#define WLC_SET_WEP 43
8953 +#define WLC_GET_KEY 44
8954 +#define WLC_SET_KEY 45
8955 +#define WLC_SCAN 50
8956 +#define WLC_SCAN_RESULTS 51
8957 +#define WLC_DISASSOC 52
8958 +#define WLC_REASSOC 53
8959 +#define WLC_GET_ROAM_TRIGGER 54
8960 +#define WLC_SET_ROAM_TRIGGER 55
8961 +#define WLC_GET_TXANT 61
8962 +#define WLC_SET_TXANT 62
8963 +#define WLC_GET_ANTDIV 63
8964 +#define WLC_SET_ANTDIV 64
8965 +#define WLC_GET_TXPWR 65
8966 +#define WLC_SET_TXPWR 66
8967 +#define WLC_GET_CLOSED 67
8968 +#define WLC_SET_CLOSED 68
8969 +#define WLC_GET_MACLIST 69
8970 +#define WLC_SET_MACLIST 70
8971 +#define WLC_GET_RATESET 71
8972 +#define WLC_SET_RATESET 72
8973 +#define WLC_GET_LOCALE 73
8974 +#define WLC_SET_LOCALE 74
8975 +#define WLC_GET_BCNPRD 75
8976 +#define WLC_SET_BCNPRD 76
8977 +#define WLC_GET_DTIMPRD 77
8978 +#define WLC_SET_DTIMPRD 78
8979 +#define WLC_GET_SROM 79
8980 +#define WLC_SET_SROM 80
8981 +#define WLC_GET_WEP_RESTRICT 81
8982 +#define WLC_SET_WEP_RESTRICT 82
8983 +#define WLC_GET_COUNTRY 83
8984 +#define WLC_SET_COUNTRY 84
8985 +#define WLC_GET_REVINFO 98
8986 +#define WLC_GET_MACMODE 105
8987 +#define WLC_SET_MACMODE 106
8988 +#define WLC_GET_GMODE 109
8989 +#define WLC_SET_GMODE 110
8990 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
8991 +#define WLC_GET_SCANSUPPRESS 115
8992 +#define WLC_SET_SCANSUPPRESS 116
8993 +#define WLC_GET_AP 117
8994 +#define WLC_SET_AP 118
8995 +#define WLC_GET_EAP_RESTRICT 119
8996 +#define WLC_SET_EAP_RESTRICT 120
8997 +#define WLC_GET_WDSLIST 123
8998 +#define WLC_SET_WDSLIST 124
8999 +#define WLC_GET_RSSI 127
9000 +#define WLC_GET_WSEC 133
9001 +#define WLC_SET_WSEC 134
9002 +#define WLC_GET_BSS_INFO 136
9003 +#define WLC_GET_LAZYWDS 138
9004 +#define WLC_SET_LAZYWDS 139
9005 +#define WLC_GET_BANDLIST 140
9006 +#define WLC_GET_BAND 141
9007 +#define WLC_SET_BAND 142
9008 +#define WLC_GET_SHORTSLOT 144
9009 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
9010 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
9011 +#define WLC_GET_SHORTSLOT_RESTRICT 147
9012 +#define WLC_SET_SHORTSLOT_RESTRICT 148
9013 +#define WLC_GET_GMODE_PROTECTION 149
9014 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
9015 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
9016 +#define WLC_UPGRADE 152
9017 +#define WLC_GET_MRATE 153
9018 +#define WLC_SET_MRATE 154
9019 +#define WLC_GET_ASSOCLIST 159
9020 +#define WLC_GET_CLK 160
9021 +#define WLC_SET_CLK 161
9022 +#define WLC_GET_UP 162
9023 +#define WLC_OUT 163
9024 +#define WLC_GET_WPA_AUTH 164
9025 +#define WLC_SET_WPA_AUTH 165
9026 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
9027 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
9028 +#define WLC_GET_PHYLIST 180
9029 +#define WLC_GET_KEY_SEQ 183
9030 +#define WLC_GET_GMODE_PROTECTION_CTS 198
9031 +#define WLC_SET_GMODE_PROTECTION_CTS 199
9032 +#define WLC_GET_PIOMODE 203
9033 +#define WLC_SET_PIOMODE 204
9034 +#define WLC_SET_LED 209
9035 +#define WLC_GET_LED 210
9036 +#define WLC_GET_CHANNEL_SEL 215
9037 +#define WLC_START_CHANNEL_SEL 216
9038 +#define WLC_GET_VALID_CHANNELS 217
9039 +#define WLC_GET_FAKEFRAG 218
9040 +#define WLC_SET_FAKEFRAG 219
9041 +#define WLC_GET_WET 230
9042 +#define WLC_SET_WET 231
9043 +#define WLC_GET_KEY_PRIMARY 235
9044 +#define WLC_SET_KEY_PRIMARY 236
9045 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
9046 +#define WLC_SET_CS_SCAN_TIMER 248
9047 +#define WLC_GET_CS_SCAN_TIMER 249
9048 +#define WLC_CURRENT_PWR 256
9049 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
9050 +#define WLC_GET_COUNTRY_LIST 261
9051 +#define WLC_GET_VAR 262 /* get value of named variable */
9052 +#define WLC_SET_VAR 263 /* set named variable to value */
9053 +#define WLC_NVRAM_GET 264
9054 +#define WLC_NVRAM_SET 265
9055 +#define WLC_SET_WSEC_PMK 268
9056 +#define WLC_GET_AUTH_MODE 269
9057 +#define WLC_SET_AUTH_MODE 270
9058 +#define WLC_LAST 273 /* do not change - use get_var/set_var */
9059 +
9060 +/*
9061 + * Minor kludge alert:
9062 + * Duplicate a few definitions that irelay requires from epiioctl.h here
9063 + * so caller doesn't have to include this file and epiioctl.h .
9064 + * If this grows any more, it would be time to move these irelay-specific
9065 + * definitions out of the epiioctl.h and into a separate driver common file.
9066 + */
9067 +#ifndef EPICTRL_COOKIE
9068 +#define EPICTRL_COOKIE 0xABADCEDE
9069 +#endif
9070 +
9071 +/* vx wlc ioctl's offset */
9072 +#define CMN_IOCTL_OFF 0x180
9073 +
9074 +/*
9075 + * custom OID support
9076 + *
9077 + * 0xFF - implementation specific OID
9078 + * 0xE4 - first byte of Broadcom PCI vendor ID
9079 + * 0x14 - second byte of Broadcom PCI vendor ID
9080 + * 0xXX - the custom OID number
9081 + */
9082 +
9083 +/* begin 0x1f values beyond the start of the ET driver range. */
9084 +#define WL_OID_BASE 0xFFE41420
9085 +
9086 +/* NDIS overrides */
9087 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
9088 +
9089 +#define WL_DECRYPT_STATUS_SUCCESS 1
9090 +#define WL_DECRYPT_STATUS_FAILURE 2
9091 +#define WL_DECRYPT_STATUS_UNKNOWN 3
9092 +
9093 +/* allows user-mode app to poll the status of USB image upgrade */
9094 +#define WLC_UPGRADE_SUCCESS 0
9095 +#define WLC_UPGRADE_PENDING 1
9096 +
9097 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
9098 +#define WL_RADIO_SW_DISABLE (1<<0)
9099 +#define WL_RADIO_HW_DISABLE (1<<1)
9100 +#define WL_RADIO_UNASSOC_DISABLE (1<<2)
9101 +
9102 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
9103 +#define WL_TXPWR_OVERRIDE (1<<31)
9104 +
9105 +
9106 +/* Bus types */
9107 +#define WL_SB_BUS 0 /* Silicon Backplane */
9108 +#define WL_PCI_BUS 1 /* PCI target */
9109 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
9110 +
9111 +/* band types */
9112 +#define WLC_BAND_AUTO 0 /* auto-select */
9113 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
9114 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
9115 +
9116 +/* MAC list modes */
9117 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
9118 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
9119 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
9120 +
9121 +/*
9122 + *
9123 + */
9124 +#define GMODE_LEGACY_B 0
9125 +#define GMODE_AUTO 1
9126 +#define GMODE_ONLY 2
9127 +#define GMODE_B_DEFERRED 3
9128 +#define GMODE_PERFORMANCE 4
9129 +#define GMODE_LRS 5
9130 +#define GMODE_MAX 6
9131 +
9132 +/* values for PLCPHdr_override */
9133 +#define WLC_PLCP_AUTO -1
9134 +#define WLC_PLCP_SHORT 0
9135 +#define WLC_PLCP_LONG 1
9136 +
9137 +/* values for g_protection_override */
9138 +#define WLC_G_PROTECTION_AUTO -1
9139 +#define WLC_G_PROTECTION_OFF 0
9140 +#define WLC_G_PROTECTION_ON 1
9141 +
9142 +/* values for g_protection_control */
9143 +#define WLC_G_PROTECTION_CTL_OFF 0
9144 +#define WLC_G_PROTECTION_CTL_LOCAL 1
9145 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
9146 +
9147 +/* Values for PM */
9148 +#define PM_OFF 0
9149 +#define PM_MAX 1
9150 +#define PM_FAST 2
9151 +
9152 +
9153 +
9154 +
9155 +
9156 +/* 802.11h enforcement levels */
9157 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
9158 +#define SPECT_MNGMT_LOOSE 1 /* qllow scan lists to contain non-11h AP */
9159 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
9160 +
9161 +
9162 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
9163 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
9164 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
9165 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
9166 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
9167 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
9168 +
9169 +
9170 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
9171 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
9172 +
9173 +/* led per-pin behaviors */
9174 +#define WL_LED_OFF 0 /* always off */
9175 +#define WL_LED_ON 1 /* always on */
9176 +#define WL_LED_ACTIVITY 2 /* activity */
9177 +#define WL_LED_RADIO 3 /* radio enabled */
9178 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
9179 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
9180 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
9181 +#define WL_LED_WI1 7
9182 +#define WL_LED_WI2 8
9183 +#define WL_LED_WI3 9
9184 +#define WL_LED_ASSOC 10 /* associated state indicator */
9185 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
9186 +#define WL_LED_NUMBEHAVIOR 12
9187 +
9188 +/* led behavior numeric value format */
9189 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
9190 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
9191 +
9192 +
9193 +/* WDS link local endpoint WPA role */
9194 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
9195 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
9196 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
9197 +
9198 +/* Structures and constants used for "vndr_ie" IOVar interface */
9199 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
9200 +
9201 +/* 802.11 Mgmt Packet flags */
9202 +#define VNDR_IE_BEACON_FLAG 0x1
9203 +#define VNDR_IE_PRBRSP_FLAG 0x2
9204 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
9205 +#define VNDR_IE_AUTHRSP_FLAG 0x8
9206 +
9207 +typedef struct vndr_ie_info {
9208 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
9209 + vndr_ie_t vndr_ie_data; /* vendor IE data */
9210 +} vndr_ie_info_t;
9211 +
9212 +typedef struct vndr_ie_buf {
9213 + int iecount; /* number of entries in the vndr_ie_list[] array */
9214 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
9215 +} vndr_ie_buf_t;
9216 +
9217 +typedef struct vndr_ie_setbuf {
9218 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
9219 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
9220 +} vndr_ie_setbuf_t;
9221 +
9222 +#if !defined(__GNUC__)
9223 +#pragma pack(pop)
9224 +#endif
9225 +
9226 +#endif /* _wlioctl_h_ */
9227 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
9228 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
9229 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-08-26 13:44:34.307392280 +0200
9230 @@ -0,0 +1,321 @@
9231 +/*
9232 + * NVRAM variable manipulation (common)
9233 + *
9234 + * Copyright 2004, Broadcom Corporation
9235 + * All Rights Reserved.
9236 + *
9237 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9238 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9239 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9240 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9241 + *
9242 + * $Id$
9243 + */
9244 +
9245 +#include <typedefs.h>
9246 +#include <osl.h>
9247 +#include <bcmendian.h>
9248 +#include <bcmnvram.h>
9249 +#include <bcmutils.h>
9250 +#include <sbsdram.h>
9251 +
9252 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
9253 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
9254 +extern int BCMINIT(_nvram_read)(void *buf);
9255 +
9256 +char * BCMINIT(_nvram_get)(const char *name);
9257 +int BCMINIT(_nvram_set)(const char *name, const char *value);
9258 +int BCMINIT(_nvram_unset)(const char *name);
9259 +int BCMINIT(_nvram_getall)(char *buf, int count);
9260 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
9261 +int BCMINIT(_nvram_init)(void);
9262 +void BCMINIT(_nvram_exit)(void);
9263 +
9264 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
9265 +static struct nvram_tuple * nvram_dead;
9266 +
9267 +/* Free all tuples. Should be locked. */
9268 +static void
9269 +BCMINITFN(nvram_free)(void)
9270 +{
9271 + uint i;
9272 + struct nvram_tuple *t, *next;
9273 +
9274 + /* Free hash table */
9275 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9276 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
9277 + next = t->next;
9278 + BCMINIT(_nvram_free)(t);
9279 + }
9280 + BCMINIT(nvram_hash)[i] = NULL;
9281 + }
9282 +
9283 + /* Free dead table */
9284 + for (t = nvram_dead; t; t = next) {
9285 + next = t->next;
9286 + BCMINIT(_nvram_free)(t);
9287 + }
9288 + nvram_dead = NULL;
9289 +
9290 + /* Indicate to per-port code that all tuples have been freed */
9291 + BCMINIT(_nvram_free)(NULL);
9292 +}
9293 +
9294 +/* String hash */
9295 +static INLINE uint
9296 +hash(const char *s)
9297 +{
9298 + uint hash = 0;
9299 +
9300 + while (*s)
9301 + hash = 31 * hash + *s++;
9302 +
9303 + return hash;
9304 +}
9305 +
9306 +/* (Re)initialize the hash table. Should be locked. */
9307 +static int
9308 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
9309 +{
9310 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
9311 +
9312 + /* (Re)initialize hash table */
9313 + BCMINIT(nvram_free)();
9314 +
9315 + /* Parse and set "name=value\0 ... \0\0" */
9316 + name = (char *) &header[1];
9317 + end = (char *) header + NVRAM_SPACE - 2;
9318 + end[0] = end[1] = '\0';
9319 + for (; *name; name = value + strlen(value) + 1) {
9320 + if (!(eq = strchr(name, '=')))
9321 + break;
9322 + *eq = '\0';
9323 + value = eq + 1;
9324 + BCMINIT(_nvram_set)(name, value);
9325 + *eq = '=';
9326 + }
9327 +
9328 + /* Set special SDRAM parameters */
9329 + if (!BCMINIT(_nvram_get)("sdram_init")) {
9330 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
9331 + BCMINIT(_nvram_set)("sdram_init", buf);
9332 + }
9333 + if (!BCMINIT(_nvram_get)("sdram_config")) {
9334 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
9335 + BCMINIT(_nvram_set)("sdram_config", buf);
9336 + }
9337 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
9338 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
9339 + BCMINIT(_nvram_set)("sdram_refresh", buf);
9340 + }
9341 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
9342 + sprintf(buf, "0x%08X", header->config_ncdl);
9343 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
9344 + }
9345 +
9346 + return 0;
9347 +}
9348 +
9349 +/* Get the value of an NVRAM variable. Should be locked. */
9350 +char *
9351 +BCMINITFN(_nvram_get)(const char *name)
9352 +{
9353 + uint i;
9354 + struct nvram_tuple *t;
9355 + char *value;
9356 +
9357 + if (!name)
9358 + return NULL;
9359 +
9360 + /* Hash the name */
9361 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9362 +
9363 + /* Find the associated tuple in the hash table */
9364 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
9365 +
9366 + value = t ? t->value : NULL;
9367 +
9368 + return value;
9369 +}
9370 +
9371 +/* Get the value of an NVRAM variable. Should be locked. */
9372 +int
9373 +BCMINITFN(_nvram_set)(const char *name, const char *value)
9374 +{
9375 + uint i;
9376 + struct nvram_tuple *t, *u, **prev;
9377 +
9378 + /* Hash the name */
9379 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9380 +
9381 + /* Find the associated tuple in the hash table */
9382 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
9383 +
9384 + /* (Re)allocate tuple */
9385 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
9386 + return -12; /* -ENOMEM */
9387 +
9388 + /* Value reallocated */
9389 + if (t && t == u)
9390 + return 0;
9391 +
9392 + /* Move old tuple to the dead table */
9393 + if (t) {
9394 + *prev = t->next;
9395 + t->next = nvram_dead;
9396 + nvram_dead = t;
9397 + }
9398 +
9399 + /* Add new tuple to the hash table */
9400 + u->next = BCMINIT(nvram_hash)[i];
9401 + BCMINIT(nvram_hash)[i] = u;
9402 +
9403 + return 0;
9404 +}
9405 +
9406 +/* Unset the value of an NVRAM variable. Should be locked. */
9407 +int
9408 +BCMINITFN(_nvram_unset)(const char *name)
9409 +{
9410 + uint i;
9411 + struct nvram_tuple *t, **prev;
9412 +
9413 + if (!name)
9414 + return 0;
9415 +
9416 + /* Hash the name */
9417 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
9418 +
9419 + /* Find the associated tuple in the hash table */
9420 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
9421 +
9422 + /* Move it to the dead table */
9423 + if (t) {
9424 + *prev = t->next;
9425 + t->next = nvram_dead;
9426 + nvram_dead = t;
9427 + }
9428 +
9429 + return 0;
9430 +}
9431 +
9432 +/* Get all NVRAM variables. Should be locked. */
9433 +int
9434 +BCMINITFN(_nvram_getall)(char *buf, int count)
9435 +{
9436 + uint i;
9437 + struct nvram_tuple *t;
9438 + int len = 0;
9439 +
9440 + bzero(buf, count);
9441 +
9442 + /* Write name=value\0 ... \0\0 */
9443 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9444 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
9445 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
9446 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
9447 + else
9448 + break;
9449 + }
9450 + }
9451 +
9452 + return 0;
9453 +}
9454 +
9455 +/* Regenerate NVRAM. Should be locked. */
9456 +int
9457 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
9458 +{
9459 + char *init, *config, *refresh, *ncdl;
9460 + char *ptr, *end;
9461 + int i;
9462 + struct nvram_tuple *t;
9463 + struct nvram_header tmp;
9464 + uint8 crc;
9465 +
9466 + /* Regenerate header */
9467 + header->magic = NVRAM_MAGIC;
9468 + header->crc_ver_init = (NVRAM_VERSION << 8);
9469 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
9470 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
9471 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
9472 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
9473 + header->crc_ver_init |= SDRAM_INIT << 16;
9474 + header->config_refresh = SDRAM_CONFIG;
9475 + header->config_refresh |= SDRAM_REFRESH << 16;
9476 + header->config_ncdl = 0;
9477 + } else {
9478 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
9479 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
9480 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
9481 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
9482 + }
9483 +
9484 + /* Clear data area */
9485 + ptr = (char *) header + sizeof(struct nvram_header);
9486 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
9487 +
9488 + /* Leave space for a double NUL at the end */
9489 + end = (char *) header + NVRAM_SPACE - 2;
9490 +
9491 + /* Write out all tuples */
9492 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
9493 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
9494 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
9495 + break;
9496 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
9497 + }
9498 + }
9499 +
9500 + /* End with a double NUL */
9501 + ptr += 2;
9502 +
9503 + /* Set new length */
9504 + header->len = ROUNDUP(ptr - (char *) header, 4);
9505 +
9506 + /* Little-endian CRC8 over the last 11 bytes of the header */
9507 + tmp.crc_ver_init = htol32(header->crc_ver_init);
9508 + tmp.config_refresh = htol32(header->config_refresh);
9509 + tmp.config_ncdl = htol32(header->config_ncdl);
9510 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
9511 +
9512 + /* Continue CRC8 over data bytes */
9513 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
9514 +
9515 + /* Set new CRC8 */
9516 + header->crc_ver_init |= crc;
9517 +
9518 + /* Reinitialize hash table */
9519 + return BCMINIT(nvram_rehash)(header);
9520 +}
9521 +
9522 +/* Initialize hash table. Should be locked. */
9523 +int
9524 +BCMINITFN(_nvram_init)(void)
9525 +{
9526 + struct nvram_header *header;
9527 + int ret;
9528 + void *osh;
9529 +
9530 + /* get kernel osl handler */
9531 + osh = osl_attach(NULL);
9532 +
9533 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
9534 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
9535 + return -12; /* -ENOMEM */
9536 + }
9537 +
9538 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
9539 + header->magic == NVRAM_MAGIC)
9540 + BCMINIT(nvram_rehash)(header);
9541 +
9542 + MFREE(osh, header, NVRAM_SPACE);
9543 + return ret;
9544 +}
9545 +
9546 +/* Free hash table. Should be locked. */
9547 +void
9548 +BCMINITFN(_nvram_exit)(void)
9549 +{
9550 + BCMINIT(nvram_free)();
9551 +}
9552 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
9553 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
9554 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-08-26 13:44:34.308392128 +0200
9555 @@ -0,0 +1,617 @@
9556 +/*
9557 + * NVRAM variable manipulation (Linux kernel half)
9558 + *
9559 + * Copyright 2004, Broadcom Corporation
9560 + * All Rights Reserved.
9561 + *
9562 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9563 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9564 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9565 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9566 + *
9567 + * $Id$
9568 + */
9569 +
9570 +#include <linux/config.h>
9571 +#include <linux/init.h>
9572 +#include <linux/module.h>
9573 +#include <linux/kernel.h>
9574 +#include <linux/string.h>
9575 +#include <linux/interrupt.h>
9576 +#include <linux/spinlock.h>
9577 +#include <linux/slab.h>
9578 +#include <linux/bootmem.h>
9579 +#include <linux/wrapper.h>
9580 +#include <linux/fs.h>
9581 +#include <linux/miscdevice.h>
9582 +#include <linux/mtd/mtd.h>
9583 +#include <asm/addrspace.h>
9584 +#include <asm/io.h>
9585 +#include <asm/uaccess.h>
9586 +
9587 +#include <typedefs.h>
9588 +#include <bcmendian.h>
9589 +#include <bcmnvram.h>
9590 +#include <bcmutils.h>
9591 +#include <sbconfig.h>
9592 +#include <sbchipc.h>
9593 +#include <sbutils.h>
9594 +#include <sbmips.h>
9595 +
9596 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
9597 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
9598 +
9599 +#ifdef MODULE
9600 +
9601 +#define early_nvram_get(name) nvram_get(name)
9602 +
9603 +#else /* !MODULE */
9604 +
9605 +/* Global SB handle */
9606 +extern void *bcm947xx_sbh;
9607 +extern spinlock_t bcm947xx_sbh_lock;
9608 +
9609 +/* Convenience */
9610 +#define sbh bcm947xx_sbh
9611 +#define sbh_lock bcm947xx_sbh_lock
9612 +#define KB * 1024
9613 +#define MB * 1024 * 1024
9614 +
9615 +/* Probe for NVRAM header */
9616 +static void __init
9617 +early_nvram_init(void)
9618 +{
9619 + struct nvram_header *header;
9620 + chipcregs_t *cc;
9621 + int i;
9622 + uint32 base, off, lim;
9623 +
9624 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
9625 + base = KSEG1ADDR(SB_FLASH2);
9626 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
9627 + case PFLASH:
9628 + lim = SB_FLASH2_SZ;
9629 + break;
9630 +
9631 + case SFLASH_ST:
9632 + case SFLASH_AT:
9633 + case FLASH_NONE:
9634 + default:
9635 + return;
9636 + }
9637 + } else {
9638 + /* extif assumed, Stop at 4 MB */
9639 + base = KSEG1ADDR(SB_FLASH1);
9640 + lim = SB_FLASH1_SZ;
9641 + }
9642 +
9643 + off = FLASH_MIN;
9644 + while (off <= lim) {
9645 + /* Windowed flash access */
9646 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9647 + if (header->magic == NVRAM_MAGIC) {
9648 + u32 *src = (u32 *) header;
9649 + u32 *dst = (u32 *) nvram_buf;
9650 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9651 + *dst++ = *src++;
9652 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9653 + *dst++ = ltoh32(*src++);
9654 + return;
9655 + }
9656 +
9657 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9658 + if (off == 1 KB)
9659 + break;
9660 + else if (off == 4 KB)
9661 + off = 1 KB;
9662 + else if (off == lim)
9663 + off = 4 KB;
9664 + else
9665 + off <<= 1;
9666 + }
9667 +}
9668 +
9669 +/* Early (before mm or mtd) read-only access to NVRAM */
9670 +static char * __init
9671 +early_nvram_get(const char *name)
9672 +{
9673 + char *var, *value, *end, *eq;
9674 +
9675 + if (!name)
9676 + return NULL;
9677 +
9678 + if (!nvram_buf[0])
9679 + early_nvram_init();
9680 +
9681 + /* Look for name=value and return value */
9682 + var = &nvram_buf[sizeof(struct nvram_header)];
9683 + end = nvram_buf + sizeof(nvram_buf) - 2;
9684 + end[0] = end[1] = '\0';
9685 + for (; *var; var = value + strlen(value) + 1) {
9686 + if (!(eq = strchr(var, '=')))
9687 + break;
9688 + value = eq + 1;
9689 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9690 + return value;
9691 + }
9692 +
9693 + return NULL;
9694 +}
9695 +
9696 +#endif /* !MODULE */
9697 +
9698 +extern char * _nvram_get(const char *name);
9699 +extern int _nvram_set(const char *name, const char *value);
9700 +extern int _nvram_unset(const char *name);
9701 +extern int _nvram_getall(char *buf, int count);
9702 +extern int _nvram_commit(struct nvram_header *header);
9703 +extern int _nvram_init(void);
9704 +extern void _nvram_exit(void);
9705 +
9706 +/* Globals */
9707 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9708 +static struct semaphore nvram_sem;
9709 +static unsigned long nvram_offset = 0;
9710 +static int nvram_major = -1;
9711 +static devfs_handle_t nvram_handle = NULL;
9712 +static struct mtd_info *nvram_mtd = NULL;
9713 +
9714 +int
9715 +_nvram_read(char *buf)
9716 +{
9717 + struct nvram_header *header = (struct nvram_header *) buf;
9718 + size_t len;
9719 +
9720 + if (!nvram_mtd ||
9721 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9722 + len != NVRAM_SPACE ||
9723 + header->magic != NVRAM_MAGIC) {
9724 + /* Maybe we can recover some data from early initialization */
9725 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9726 + }
9727 +
9728 + return 0;
9729 +}
9730 +
9731 +struct nvram_tuple *
9732 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9733 +{
9734 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9735 + return NULL;
9736 +
9737 + if (!t) {
9738 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9739 + return NULL;
9740 +
9741 + /* Copy name */
9742 + t->name = (char *) &t[1];
9743 + strcpy(t->name, name);
9744 +
9745 + t->value = NULL;
9746 + }
9747 +
9748 + /* Copy value */
9749 + if (!t->value || strcmp(t->value, value)) {
9750 + t->value = &nvram_buf[nvram_offset];
9751 + strcpy(t->value, value);
9752 + nvram_offset += strlen(value) + 1;
9753 + }
9754 +
9755 + return t;
9756 +}
9757 +
9758 +void
9759 +_nvram_free(struct nvram_tuple *t)
9760 +{
9761 + if (!t)
9762 + nvram_offset = 0;
9763 + else
9764 + kfree(t);
9765 +}
9766 +
9767 +int
9768 +nvram_set(const char *name, const char *value)
9769 +{
9770 + unsigned long flags;
9771 + int ret;
9772 + struct nvram_header *header;
9773 +
9774 + spin_lock_irqsave(&nvram_lock, flags);
9775 + if ((ret = _nvram_set(name, value))) {
9776 + /* Consolidate space and try again */
9777 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9778 + if (_nvram_commit(header) == 0)
9779 + ret = _nvram_set(name, value);
9780 + kfree(header);
9781 + }
9782 + }
9783 + spin_unlock_irqrestore(&nvram_lock, flags);
9784 +
9785 + return ret;
9786 +}
9787 +
9788 +char *
9789 +real_nvram_get(const char *name)
9790 +{
9791 + unsigned long flags;
9792 + char *value;
9793 +
9794 + spin_lock_irqsave(&nvram_lock, flags);
9795 + value = _nvram_get(name);
9796 + spin_unlock_irqrestore(&nvram_lock, flags);
9797 +
9798 + return value;
9799 +}
9800 +
9801 +char *
9802 +nvram_get(const char *name)
9803 +{
9804 + if (nvram_major >= 0)
9805 + return real_nvram_get(name);
9806 + else
9807 + return early_nvram_get(name);
9808 +}
9809 +
9810 +int
9811 +nvram_unset(const char *name)
9812 +{
9813 + unsigned long flags;
9814 + int ret;
9815 +
9816 + spin_lock_irqsave(&nvram_lock, flags);
9817 + ret = _nvram_unset(name);
9818 + spin_unlock_irqrestore(&nvram_lock, flags);
9819 +
9820 + return ret;
9821 +}
9822 +
9823 +static void
9824 +erase_callback(struct erase_info *done)
9825 +{
9826 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9827 + wake_up(wait_q);
9828 +}
9829 +
9830 +int
9831 +nvram_commit(void)
9832 +{
9833 + char *buf;
9834 + size_t erasesize, len;
9835 + unsigned int i;
9836 + int ret;
9837 + struct nvram_header *header;
9838 + unsigned long flags;
9839 + u_int32_t offset;
9840 + DECLARE_WAITQUEUE(wait, current);
9841 + wait_queue_head_t wait_q;
9842 + struct erase_info erase;
9843 +
9844 + if (!nvram_mtd) {
9845 + printk("nvram_commit: NVRAM not found\n");
9846 + return -ENODEV;
9847 + }
9848 +
9849 + if (in_interrupt()) {
9850 + printk("nvram_commit: not committing in interrupt\n");
9851 + return -EINVAL;
9852 + }
9853 +
9854 + /* Backup sector blocks to be erased */
9855 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9856 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9857 + printk("nvram_commit: out of memory\n");
9858 + return -ENOMEM;
9859 + }
9860 +
9861 + down(&nvram_sem);
9862 +
9863 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9864 + offset = nvram_mtd->size - erasesize;
9865 + len = 0;
9866 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9867 + if (ret || len != i) {
9868 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9869 + ret = -EIO;
9870 + goto done;
9871 + }
9872 + header = (struct nvram_header *)(buf + i);
9873 + } else {
9874 + offset = nvram_mtd->size - NVRAM_SPACE;
9875 + header = (struct nvram_header *)buf;
9876 + }
9877 +
9878 + /* Regenerate NVRAM */
9879 + spin_lock_irqsave(&nvram_lock, flags);
9880 + ret = _nvram_commit(header);
9881 + spin_unlock_irqrestore(&nvram_lock, flags);
9882 + if (ret)
9883 + goto done;
9884 +
9885 + /* Erase sector blocks */
9886 + init_waitqueue_head(&wait_q);
9887 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9888 + erase.mtd = nvram_mtd;
9889 + erase.addr = offset;
9890 + erase.len = nvram_mtd->erasesize;
9891 + erase.callback = erase_callback;
9892 + erase.priv = (u_long) &wait_q;
9893 +
9894 + set_current_state(TASK_INTERRUPTIBLE);
9895 + add_wait_queue(&wait_q, &wait);
9896 +
9897 + /* Unlock sector blocks */
9898 + if (nvram_mtd->unlock)
9899 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9900 +
9901 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9902 + set_current_state(TASK_RUNNING);
9903 + remove_wait_queue(&wait_q, &wait);
9904 + printk("nvram_commit: erase error\n");
9905 + goto done;
9906 + }
9907 +
9908 + /* Wait for erase to finish */
9909 + schedule();
9910 + remove_wait_queue(&wait_q, &wait);
9911 + }
9912 +
9913 + /* Write partition up to end of data area */
9914 + offset = nvram_mtd->size - erasesize;
9915 + i = erasesize - NVRAM_SPACE + header->len;
9916 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9917 + if (ret || len != i) {
9918 + printk("nvram_commit: write error\n");
9919 + ret = -EIO;
9920 + goto done;
9921 + }
9922 +
9923 + offset = nvram_mtd->size - erasesize;
9924 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9925 +
9926 + done:
9927 + up(&nvram_sem);
9928 + kfree(buf);
9929 + return ret;
9930 +}
9931 +
9932 +int
9933 +nvram_getall(char *buf, int count)
9934 +{
9935 + unsigned long flags;
9936 + int ret;
9937 +
9938 + spin_lock_irqsave(&nvram_lock, flags);
9939 + ret = _nvram_getall(buf, count);
9940 + spin_unlock_irqrestore(&nvram_lock, flags);
9941 +
9942 + return ret;
9943 +}
9944 +
9945 +EXPORT_SYMBOL(nvram_get);
9946 +EXPORT_SYMBOL(nvram_getall);
9947 +EXPORT_SYMBOL(nvram_set);
9948 +EXPORT_SYMBOL(nvram_unset);
9949 +EXPORT_SYMBOL(nvram_commit);
9950 +
9951 +/* User mode interface below */
9952 +
9953 +static ssize_t
9954 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9955 +{
9956 + char tmp[100], *name = tmp, *value;
9957 + ssize_t ret;
9958 + unsigned long off;
9959 +
9960 + if (count > sizeof(tmp)) {
9961 + if (!(name = kmalloc(count, GFP_KERNEL)))
9962 + return -ENOMEM;
9963 + }
9964 +
9965 + if (copy_from_user(name, buf, count)) {
9966 + ret = -EFAULT;
9967 + goto done;
9968 + }
9969 +
9970 + if (*name == '\0') {
9971 + /* Get all variables */
9972 + ret = nvram_getall(name, count);
9973 + if (ret == 0) {
9974 + if (copy_to_user(buf, name, count)) {
9975 + ret = -EFAULT;
9976 + goto done;
9977 + }
9978 + ret = count;
9979 + }
9980 + } else {
9981 + if (!(value = nvram_get(name))) {
9982 + ret = 0;
9983 + goto done;
9984 + }
9985 +
9986 + /* Provide the offset into mmap() space */
9987 + off = (unsigned long) value - (unsigned long) nvram_buf;
9988 +
9989 + if (put_user(off, (unsigned long *) buf)) {
9990 + ret = -EFAULT;
9991 + goto done;
9992 + }
9993 +
9994 + ret = sizeof(unsigned long);
9995 + }
9996 +
9997 + flush_cache_all();
9998 +
9999 +done:
10000 + if (name != tmp)
10001 + kfree(name);
10002 +
10003 + return ret;
10004 +}
10005 +
10006 +static ssize_t
10007 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
10008 +{
10009 + char tmp[100], *name = tmp, *value;
10010 + ssize_t ret;
10011 +
10012 + if (count > sizeof(tmp)) {
10013 + if (!(name = kmalloc(count, GFP_KERNEL)))
10014 + return -ENOMEM;
10015 + }
10016 +
10017 + if (copy_from_user(name, buf, count)) {
10018 + ret = -EFAULT;
10019 + goto done;
10020 + }
10021 +
10022 + value = name;
10023 + name = strsep(&value, "=");
10024 + if (value)
10025 + ret = nvram_set(name, value) ? : count;
10026 + else
10027 + ret = nvram_unset(name) ? : count;
10028 +
10029 + done:
10030 + if (name != tmp)
10031 + kfree(name);
10032 +
10033 + return ret;
10034 +}
10035 +
10036 +static int
10037 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
10038 +{
10039 + if (cmd != NVRAM_MAGIC)
10040 + return -EINVAL;
10041 + return nvram_commit();
10042 +}
10043 +
10044 +static int
10045 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
10046 +{
10047 + unsigned long offset = virt_to_phys(nvram_buf);
10048 +
10049 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
10050 + vma->vm_page_prot))
10051 + return -EAGAIN;
10052 +
10053 + return 0;
10054 +}
10055 +
10056 +static int
10057 +dev_nvram_open(struct inode *inode, struct file * file)
10058 +{
10059 + MOD_INC_USE_COUNT;
10060 + return 0;
10061 +}
10062 +
10063 +static int
10064 +dev_nvram_release(struct inode *inode, struct file * file)
10065 +{
10066 + MOD_DEC_USE_COUNT;
10067 + return 0;
10068 +}
10069 +
10070 +static struct file_operations dev_nvram_fops = {
10071 + owner: THIS_MODULE,
10072 + open: dev_nvram_open,
10073 + release: dev_nvram_release,
10074 + read: dev_nvram_read,
10075 + write: dev_nvram_write,
10076 + ioctl: dev_nvram_ioctl,
10077 + mmap: dev_nvram_mmap,
10078 +};
10079 +
10080 +static void
10081 +dev_nvram_exit(void)
10082 +{
10083 + int order = 0;
10084 + struct page *page, *end;
10085 +
10086 + if (nvram_handle)
10087 + devfs_unregister(nvram_handle);
10088 +
10089 + if (nvram_major >= 0)
10090 + devfs_unregister_chrdev(nvram_major, "nvram");
10091 +
10092 + if (nvram_mtd)
10093 + put_mtd_device(nvram_mtd);
10094 +
10095 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
10096 + order++;
10097 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
10098 + for (page = virt_to_page(nvram_buf); page <= end; page++)
10099 + mem_map_unreserve(page);
10100 +
10101 + _nvram_exit();
10102 +}
10103 +
10104 +static int __init
10105 +dev_nvram_init(void)
10106 +{
10107 + int order = 0, ret = 0;
10108 + struct page *page, *end;
10109 + unsigned int i;
10110 +
10111 + /* Allocate and reserve memory to mmap() */
10112 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
10113 + order++;
10114 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
10115 + for (page = virt_to_page(nvram_buf); page <= end; page++)
10116 + mem_map_reserve(page);
10117 +
10118 +#ifdef CONFIG_MTD
10119 + /* Find associated MTD device */
10120 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
10121 + nvram_mtd = get_mtd_device(NULL, i);
10122 + if (nvram_mtd) {
10123 + if (!strcmp(nvram_mtd->name, "nvram") &&
10124 + nvram_mtd->size >= NVRAM_SPACE)
10125 + break;
10126 + put_mtd_device(nvram_mtd);
10127 + }
10128 + }
10129 + if (i >= MAX_MTD_DEVICES)
10130 + nvram_mtd = NULL;
10131 +#endif
10132 +
10133 + /* Initialize hash table lock */
10134 + spin_lock_init(&nvram_lock);
10135 +
10136 + /* Initialize commit semaphore */
10137 + init_MUTEX(&nvram_sem);
10138 +
10139 + /* Register char device */
10140 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
10141 + ret = nvram_major;
10142 + goto err;
10143 + }
10144 +
10145 + /* Initialize hash table */
10146 + _nvram_init();
10147 +
10148 + /* Create /dev/nvram handle */
10149 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
10150 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
10151 +
10152 + /* Set the SDRAM NCDL value into NVRAM if not already done */
10153 + if (getintvar(NULL, "sdram_ncdl") == 0) {
10154 + unsigned int ncdl;
10155 + char buf[] = "0x00000000";
10156 +
10157 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
10158 + sprintf(buf, "0x%08x", ncdl);
10159 + nvram_set("sdram_ncdl", buf);
10160 + nvram_commit();
10161 + }
10162 + }
10163 +
10164 + return 0;
10165 +
10166 + err:
10167 + dev_nvram_exit();
10168 + return ret;
10169 +}
10170 +
10171 +module_init(dev_nvram_init);
10172 +module_exit(dev_nvram_exit);
10173 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
10174 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
10175 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-08-26 13:44:34.309391976 +0200
10176 @@ -0,0 +1,355 @@
10177 +/*
10178 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
10179 + *
10180 + * Copyright 2004, Broadcom Corporation
10181 + * All Rights Reserved.
10182 + *
10183 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10184 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10185 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10186 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10187 + *
10188 + * $Id$
10189 + */
10190 +
10191 +#include <linux/config.h>
10192 +#include <linux/types.h>
10193 +#include <linux/kernel.h>
10194 +#include <linux/sched.h>
10195 +#include <linux/pci.h>
10196 +#include <linux/init.h>
10197 +#include <linux/delay.h>
10198 +#include <asm/io.h>
10199 +#include <asm/irq.h>
10200 +#include <asm/paccess.h>
10201 +
10202 +#include <typedefs.h>
10203 +#include <bcmutils.h>
10204 +#include <sbconfig.h>
10205 +#include <sbpci.h>
10206 +#include <pcicfg.h>
10207 +#include <sbutils.h>
10208 +#include <bcmdevs.h>
10209 +#include <bcmnvram.h>
10210 +
10211 +/* Global SB handle */
10212 +extern void *bcm947xx_sbh;
10213 +extern spinlock_t bcm947xx_sbh_lock;
10214 +
10215 +/* Convenience */
10216 +#define sbh bcm947xx_sbh
10217 +#define sbh_lock bcm947xx_sbh_lock
10218 +
10219 +static int
10220 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
10221 +{
10222 + unsigned long flags;
10223 + int ret;
10224 +
10225 + spin_lock_irqsave(&sbh_lock, flags);
10226 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10227 + spin_unlock_irqrestore(&sbh_lock, flags);
10228 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10229 +}
10230 +
10231 +static int
10232 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
10233 +{
10234 + unsigned long flags;
10235 + int ret;
10236 +
10237 + spin_lock_irqsave(&sbh_lock, flags);
10238 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10239 + spin_unlock_irqrestore(&sbh_lock, flags);
10240 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10241 +}
10242 +
10243 +static int
10244 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
10245 +{
10246 + unsigned long flags;
10247 + int ret;
10248 +
10249 + spin_lock_irqsave(&sbh_lock, flags);
10250 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
10251 + spin_unlock_irqrestore(&sbh_lock, flags);
10252 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10253 +}
10254 +
10255 +static int
10256 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
10257 +{
10258 + unsigned long flags;
10259 + int ret;
10260 +
10261 + spin_lock_irqsave(&sbh_lock, flags);
10262 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10263 + spin_unlock_irqrestore(&sbh_lock, flags);
10264 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10265 +}
10266 +
10267 +static int
10268 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
10269 +{
10270 + unsigned long flags;
10271 + int ret;
10272 +
10273 + spin_lock_irqsave(&sbh_lock, flags);
10274 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10275 + spin_unlock_irqrestore(&sbh_lock, flags);
10276 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10277 +}
10278 +
10279 +static int
10280 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
10281 +{
10282 + unsigned long flags;
10283 + int ret;
10284 +
10285 + spin_lock_irqsave(&sbh_lock, flags);
10286 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
10287 + spin_unlock_irqrestore(&sbh_lock, flags);
10288 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
10289 +}
10290 +
10291 +static struct pci_ops pcibios_ops = {
10292 + sbpci_read_config_byte,
10293 + sbpci_read_config_word,
10294 + sbpci_read_config_dword,
10295 + sbpci_write_config_byte,
10296 + sbpci_write_config_word,
10297 + sbpci_write_config_dword
10298 +};
10299 +
10300 +
10301 +void __init
10302 +pcibios_init(void)
10303 +{
10304 + ulong flags;
10305 +
10306 + if (!(sbh = sb_kattach()))
10307 + panic("sb_kattach failed");
10308 + spin_lock_init(&sbh_lock);
10309 +
10310 + spin_lock_irqsave(&sbh_lock, flags);
10311 + sbpci_init(sbh);
10312 + spin_unlock_irqrestore(&sbh_lock, flags);
10313 +
10314 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
10315 +
10316 + mdelay(300); //By Joey for Atheros Card
10317 +
10318 + /* Scan the SB bus */
10319 + pci_scan_bus(0, &pcibios_ops, NULL);
10320 +
10321 +}
10322 +
10323 +char * __init
10324 +pcibios_setup(char *str)
10325 +{
10326 + if (!strncmp(str, "ban=", 4)) {
10327 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
10328 + return NULL;
10329 + }
10330 +
10331 + return (str);
10332 +}
10333 +
10334 +static u32 pci_iobase = 0x100;
10335 +static u32 pci_membase = SB_PCI_DMA;
10336 +
10337 +void __init
10338 +pcibios_fixup_bus(struct pci_bus *b)
10339 +{
10340 + struct list_head *ln;
10341 + struct pci_dev *d;
10342 + struct resource *res;
10343 + int pos, size;
10344 + u32 *base;
10345 + u8 irq;
10346 +
10347 + printk("PCI: Fixing up bus %d\n", b->number);
10348 +
10349 + /* Fix up SB */
10350 + if (b->number == 0) {
10351 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
10352 + d = pci_dev_b(ln);
10353 + /* Fix up interrupt lines */
10354 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
10355 + d->irq = irq + 2;
10356 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
10357 + }
10358 + }
10359 +
10360 + /* Fix up external PCI */
10361 + else {
10362 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
10363 + d = pci_dev_b(ln);
10364 + /* Fix up resource bases */
10365 + for (pos = 0; pos < 6; pos++) {
10366 + res = &d->resource[pos];
10367 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
10368 + if (res->end) {
10369 + size = res->end - res->start + 1;
10370 + if (*base & (size - 1))
10371 + *base = (*base + size) & ~(size - 1);
10372 + res->start = *base;
10373 + res->end = res->start + size - 1;
10374 + *base += size;
10375 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
10376 + }
10377 + /* Fix up PCI bridge BAR0 only */
10378 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
10379 + break;
10380 + }
10381 + /* Fix up interrupt lines */
10382 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
10383 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
10384 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
10385 + }
10386 + }
10387 +}
10388 +
10389 +unsigned int
10390 +pcibios_assign_all_busses(void)
10391 +{
10392 + return 1;
10393 +}
10394 +
10395 +void
10396 +pcibios_align_resource(void *data, struct resource *res,
10397 + unsigned long size, unsigned long align)
10398 +{
10399 +}
10400 +
10401 +int
10402 +pcibios_enable_resources(struct pci_dev *dev)
10403 +{
10404 + u16 cmd, old_cmd;
10405 + int idx;
10406 + struct resource *r;
10407 +
10408 + /* External PCI only */
10409 + if (dev->bus->number == 0)
10410 + return 0;
10411 +
10412 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
10413 + old_cmd = cmd;
10414 + for(idx=0; idx<6; idx++) {
10415 + r = &dev->resource[idx];
10416 + if (r->flags & IORESOURCE_IO)
10417 + cmd |= PCI_COMMAND_IO;
10418 + if (r->flags & IORESOURCE_MEM)
10419 + cmd |= PCI_COMMAND_MEMORY;
10420 + }
10421 + if (dev->resource[PCI_ROM_RESOURCE].start)
10422 + cmd |= PCI_COMMAND_MEMORY;
10423 + if (cmd != old_cmd) {
10424 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
10425 + pci_write_config_word(dev, PCI_COMMAND, cmd);
10426 + }
10427 + return 0;
10428 +}
10429 +
10430 +int
10431 +pcibios_enable_device(struct pci_dev *dev, int mask)
10432 +{
10433 + ulong flags;
10434 + uint coreidx;
10435 +
10436 + /* External PCI device enable */
10437 + if (dev->bus->number != 0)
10438 + return pcibios_enable_resources(dev);
10439 +
10440 + /* These cores come out of reset enabled */
10441 + if (dev->device == SB_MIPS ||
10442 + dev->device == SB_MIPS33 ||
10443 + dev->device == SB_EXTIF ||
10444 + dev->device == SB_CC)
10445 + return 0;
10446 +
10447 + spin_lock_irqsave(&sbh_lock, flags);
10448 + coreidx = sb_coreidx(sbh);
10449 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
10450 + return PCIBIOS_DEVICE_NOT_FOUND;
10451 +
10452 + /*
10453 + * The USB core requires a special bit to be set during core
10454 + * reset to enable host (OHCI) mode. Resetting the SB core in
10455 + * pcibios_enable_device() is a hack for compatibility with
10456 + * vanilla usb-ohci so that it does not have to know about
10457 + * SB. A driver that wants to use the USB core in device mode
10458 + * should know about SB and should reset the bit back to 0
10459 + * after calling pcibios_enable_device().
10460 + */
10461 + if (sb_coreid(sbh) == SB_USB) {
10462 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
10463 + sb_core_reset(sbh, 1 << 29);
10464 + } else
10465 + sb_core_reset(sbh, 0);
10466 +
10467 + sb_setcoreidx(sbh, coreidx);
10468 + spin_unlock_irqrestore(&sbh_lock, flags);
10469 +
10470 + return 0;
10471 +}
10472 +
10473 +void
10474 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
10475 + struct resource *res, int resource)
10476 +{
10477 + unsigned long where, size;
10478 + u32 reg;
10479 +
10480 + /* External PCI only */
10481 + if (dev->bus->number == 0)
10482 + return;
10483 +
10484 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
10485 + size = res->end - res->start;
10486 + pci_read_config_dword(dev, where, &reg);
10487 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
10488 + pci_write_config_dword(dev, where, reg);
10489 +}
10490 +
10491 +static void __init
10492 +quirk_sbpci_bridge(struct pci_dev *dev)
10493 +{
10494 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
10495 + return;
10496 +
10497 + printk("PCI: Fixing up bridge\n");
10498 +
10499 + /* Enable PCI bridge bus mastering and memory space */
10500 + pci_set_master(dev);
10501 + pcibios_enable_resources(dev);
10502 +
10503 + /* Enable PCI bridge BAR1 prefetch and burst */
10504 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
10505 +}
10506 +
10507 +struct pci_fixup pcibios_fixups[] = {
10508 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
10509 + { 0 }
10510 +};
10511 +
10512 +/*
10513 + * If we set up a device for bus mastering, we need to check the latency
10514 + * timer as certain crappy BIOSes forget to set it properly.
10515 + */
10516 +unsigned int pcibios_max_latency = 255;
10517 +
10518 +void pcibios_set_master(struct pci_dev *dev)
10519 +{
10520 + u8 lat;
10521 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10522 + if (lat < 16)
10523 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10524 + else if (lat > pcibios_max_latency)
10525 + lat = pcibios_max_latency;
10526 + else
10527 + return;
10528 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10529 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10530 +}
10531 +
10532 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10533 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10534 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-08-26 13:44:34.310391824 +0200
10535 @@ -0,0 +1,41 @@
10536 +/*
10537 + * Early initialization code for BCM94710 boards
10538 + *
10539 + * Copyright 2004, Broadcom Corporation
10540 + * All Rights Reserved.
10541 + *
10542 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10543 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10544 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10545 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10546 + *
10547 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10548 + */
10549 +
10550 +#include <linux/config.h>
10551 +#include <linux/init.h>
10552 +#include <linux/kernel.h>
10553 +#include <linux/types.h>
10554 +#include <asm/bootinfo.h>
10555 +
10556 +void __init
10557 +prom_init(int argc, const char **argv)
10558 +{
10559 + unsigned long mem;
10560 +
10561 + mips_machgroup = MACH_GROUP_BRCM;
10562 + mips_machtype = MACH_BCM947XX;
10563 +
10564 + /* Figure out memory size by finding aliases */
10565 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10566 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10567 + *(unsigned long *)(prom_init))
10568 + break;
10569 + }
10570 + add_memory_region(0, mem, BOOT_MEM_RAM);
10571 +}
10572 +
10573 +void __init
10574 +prom_free_prom_memory(void)
10575 +{
10576 +}
10577 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10578 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10579 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-08-30 14:47:52.836470168 +0200
10580 @@ -0,0 +1,1040 @@
10581 +/*
10582 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10583 + *
10584 + * Copyright 2005, Broadcom Corporation
10585 + * All Rights Reserved.
10586 + *
10587 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10588 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10589 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10590 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10591 + *
10592 + * $Id: sbmips.c,v 1.3 2005/03/07 08:35:32 kanki Exp $
10593 + */
10594 +
10595 +#include <typedefs.h>
10596 +#include <osl.h>
10597 +#include <sbutils.h>
10598 +#include <bcmdevs.h>
10599 +#include <bcmnvram.h>
10600 +#include <bcmutils.h>
10601 +#include <hndmips.h>
10602 +#include <sbconfig.h>
10603 +#include <sbextif.h>
10604 +#include <sbchipc.h>
10605 +#include <sbmemc.h>
10606 +#include <mipsinc.h>
10607 +
10608 +/*
10609 + * Returns TRUE if an external UART exists at the given base
10610 + * register.
10611 + */
10612 +static bool
10613 +BCMINITFN(serial_exists)(uint8 *regs)
10614 +{
10615 + uint8 save_mcr, status1;
10616 +
10617 + save_mcr = R_REG(&regs[UART_MCR]);
10618 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
10619 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
10620 + W_REG(&regs[UART_MCR], save_mcr);
10621 +
10622 + return (status1 == 0x90);
10623 +}
10624 +
10625 +/*
10626 + * Initializes UART access. The callback function will be called once
10627 + * per found UART.
10628 + */
10629 +void
10630 +BCMINITFN(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
10631 +{
10632 + void *regs;
10633 + ulong base;
10634 + uint irq;
10635 + int i, n;
10636 +
10637 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
10638 + extifregs_t *eir = (extifregs_t *) regs;
10639 + sbconfig_t *sb;
10640 +
10641 + /* Determine external UART register base */
10642 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
10643 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
10644 +
10645 + /* Determine IRQ */
10646 + irq = sb_irq(sbh);
10647 +
10648 + /* Disable GPIO interrupt initially */
10649 + W_REG(&eir->gpiointpolarity, 0);
10650 + W_REG(&eir->gpiointmask, 0);
10651 +
10652 + /* Search for external UARTs */
10653 + n = 2;
10654 + for (i = 0; i < 2; i++) {
10655 + regs = (void *) REG_MAP(base + (i * 8), 8);
10656 + if (BCMINIT(serial_exists)(regs)) {
10657 + /* Set GPIO 1 to be the external UART IRQ */
10658 + W_REG(&eir->gpiointmask, 2);
10659 + if (add)
10660 + add(regs, irq, 13500000, 0);
10661 + }
10662 + }
10663 +
10664 + /* Add internal UART if enabled */
10665 + if (R_REG(&eir->corecontrol) & CC_UE)
10666 + if (add)
10667 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
10668 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
10669 + chipcregs_t *cc = (chipcregs_t *) regs;
10670 + uint32 rev, cap, pll, baud_base, div;
10671 +
10672 + /* Determine core revision and capabilities */
10673 + rev = sb_corerev(sbh);
10674 + cap = R_REG(&cc->capabilities);
10675 + pll = cap & CAP_PLL_MASK;
10676 +
10677 + /* Determine IRQ */
10678 + irq = sb_irq(sbh);
10679 +
10680 + if (pll == PLL_TYPE1) {
10681 + /* PLL clock */
10682 + baud_base = sb_clock_rate(pll,
10683 + R_REG(&cc->clockcontrol_n),
10684 + R_REG(&cc->clockcontrol_m2));
10685 + div = 1;
10686 + } else {
10687 + if (rev >= 11) {
10688 + /* Fixed ALP clock */
10689 + baud_base = 20000000;
10690 + div = 1;
10691 + /* Set the override bit so we don't divide it */
10692 + W_REG(&cc->corecontrol, CC_UARTCLKO);
10693 + } else if ((rev >= 3) && (pll == PLL_TYPE6)) {
10694 + /* Fixed ALP clock */
10695 + baud_base = 20000000;
10696 + div = 2;
10697 + /* Set the override bit so we don't divide it */
10698 + W_REG(&cc->corecontrol, CC_UARTCLKO);
10699 + W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
10700 + } else if (rev >= 3) {
10701 + /* Internal backplane clock */
10702 + baud_base = sb_clock(sbh);
10703 + div = 2; /* Minimum divisor */
10704 + W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
10705 + } else {
10706 + /* Fixed internal backplane clock */
10707 + baud_base = 88000000;
10708 + div = 48;
10709 + }
10710 +
10711 + /* Clock source depends on strapping if UartClkOverride is unset */
10712 + if ((rev > 0) &&
10713 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
10714 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
10715 + /* Internal divided backplane clock */
10716 + baud_base /= div;
10717 + } else {
10718 + /* Assume external clock of 1.8432 MHz */
10719 + baud_base = 1843200;
10720 + }
10721 + }
10722 + }
10723 +
10724 + /* Add internal UARTs */
10725 + n = cap & CAP_UARTS_MASK;
10726 + for (i = 0; i < n; i++) {
10727 + /* Register offset changed after revision 0 */
10728 + if (rev)
10729 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
10730 + else
10731 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
10732 +
10733 + if (add)
10734 + add(regs, irq, baud_base, 0);
10735 + }
10736 + }
10737 +}
10738 +
10739 +/*
10740 + * Initialize jtag master and return handle for
10741 + * jtag_rwreg. Returns NULL on failure.
10742 + */
10743 +void *
10744 +sb_jtagm_init(void *sbh, uint clkd, bool exttap)
10745 +{
10746 + void *regs;
10747 +
10748 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10749 + chipcregs_t *cc = (chipcregs_t *) regs;
10750 + uint32 tmp;
10751 +
10752 + /*
10753 + * Determine jtagm availability from
10754 + * core revision and capabilities.
10755 + */
10756 + tmp = sb_corerev(sbh);
10757 + /*
10758 + * Corerev 10 has jtagm, but the only chip
10759 + * with it does not have a mips, and
10760 + * the layout of the jtagcmd register is
10761 + * different. We'll only accept >= 11.
10762 + */
10763 + if (tmp < 11)
10764 + return (NULL);
10765 +
10766 + tmp = R_REG(&cc->capabilities);
10767 + if ((tmp & CAP_JTAGP) == 0)
10768 + return (NULL);
10769 +
10770 + /* Set clock divider if requested */
10771 + if (clkd != 0) {
10772 + tmp = R_REG(&cc->clkdiv);
10773 + tmp = (tmp & ~CLKD_JTAG) |
10774 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
10775 + W_REG(&cc->clkdiv, tmp);
10776 + }
10777 +
10778 + /* Enable jtagm */
10779 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
10780 + W_REG(&cc->jtagctrl, tmp);
10781 + }
10782 +
10783 + return (regs);
10784 +}
10785 +
10786 +void
10787 +sb_jtagm_disable(void *h)
10788 +{
10789 + chipcregs_t *cc = (chipcregs_t *)h;
10790 +
10791 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
10792 +}
10793 +
10794 +/*
10795 + * Read/write a jtag register. Assumes a target with
10796 + * 8 bit IR and 32 bit DR.
10797 + */
10798 +#define IRWIDTH 8
10799 +#define DRWIDTH 32
10800 +uint32
10801 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
10802 +{
10803 + chipcregs_t *cc = (chipcregs_t *) h;
10804 + uint32 tmp;
10805 +
10806 + W_REG(&cc->jtagir, ir);
10807 + W_REG(&cc->jtagdr, dr);
10808 + tmp = JCMD_START | JCMD_ACC_IRDR |
10809 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
10810 + (DRWIDTH - 1);
10811 + W_REG(&cc->jtagcmd, tmp);
10812 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
10813 + /* OSL_DELAY(1); */
10814 + }
10815 +
10816 + tmp = R_REG(&cc->jtagdr);
10817 + return (tmp);
10818 +}
10819 +
10820 +/* Returns the SB interrupt flag of the current core. */
10821 +uint32
10822 +sb_flag(void *sbh)
10823 +{
10824 + void *regs;
10825 + sbconfig_t *sb;
10826 +
10827 + regs = sb_coreregs(sbh);
10828 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10829 +
10830 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
10831 +}
10832 +
10833 +static const uint32 sbips_int_mask[] = {
10834 + 0,
10835 + SBIPS_INT1_MASK,
10836 + SBIPS_INT2_MASK,
10837 + SBIPS_INT3_MASK,
10838 + SBIPS_INT4_MASK
10839 +};
10840 +
10841 +static const uint32 sbips_int_shift[] = {
10842 + 0,
10843 + 0,
10844 + SBIPS_INT2_SHIFT,
10845 + SBIPS_INT3_SHIFT,
10846 + SBIPS_INT4_SHIFT
10847 +};
10848 +
10849 +/*
10850 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10851 + * 0 is returned.
10852 + */
10853 +uint
10854 +sb_irq(void *sbh)
10855 +{
10856 + uint idx;
10857 + void *regs;
10858 + sbconfig_t *sb;
10859 + uint32 flag, sbipsflag;
10860 + uint irq = 0;
10861 +
10862 + flag = sb_flag(sbh);
10863 +
10864 + idx = sb_coreidx(sbh);
10865 +
10866 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10867 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10868 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10869 +
10870 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10871 + sbipsflag = R_REG(&sb->sbipsflag);
10872 + for (irq = 1; irq <= 4; irq++) {
10873 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10874 + break;
10875 + }
10876 + if (irq == 5)
10877 + irq = 0;
10878 + }
10879 +
10880 + sb_setcoreidx(sbh, idx);
10881 +
10882 + return irq;
10883 +}
10884 +
10885 +/* Clears the specified MIPS IRQ. */
10886 +static void
10887 +BCMINITFN(sb_clearirq)(void *sbh, uint irq)
10888 +{
10889 + void *regs;
10890 + sbconfig_t *sb;
10891 +
10892 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10893 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10894 + ASSERT(regs);
10895 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10896 +
10897 + if (irq == 0)
10898 + W_REG(&sb->sbintvec, 0);
10899 + else
10900 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
10901 +}
10902 +
10903 +/*
10904 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10905 + * IRQ 0 may be assigned more than once.
10906 + */
10907 +static void
10908 +BCMINITFN(sb_setirq)(void *sbh, uint irq, uint coreid, uint coreunit)
10909 +{
10910 + void *regs;
10911 + sbconfig_t *sb;
10912 + uint32 flag;
10913 +
10914 + regs = sb_setcore(sbh, coreid, coreunit);
10915 + ASSERT(regs);
10916 + flag = sb_flag(sbh);
10917 +
10918 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10919 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10920 + ASSERT(regs);
10921 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10922 +
10923 + if (irq == 0)
10924 + OR_REG(&sb->sbintvec, 1 << flag);
10925 + else {
10926 + flag <<= sbips_int_shift[irq];
10927 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10928 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
10929 + W_REG(&sb->sbipsflag, flag);
10930 + }
10931 +}
10932 +
10933 +/*
10934 + * Initializes clocks and interrupts. SB and NVRAM access must be
10935 + * initialized prior to calling.
10936 + */
10937 +void
10938 +BCMINITFN(sb_mips_init)(void *sbh)
10939 +{
10940 + ulong hz, ns, tmp;
10941 + extifregs_t *eir;
10942 + chipcregs_t *cc;
10943 + char *value;
10944 + uint irq;
10945 +
10946 + /* Figure out current SB clock speed */
10947 + if ((hz = sb_clock(sbh)) == 0)
10948 + hz = 100000000;
10949 + ns = 1000000000 / hz;
10950 +
10951 + /* Setup external interface timing */
10952 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10953 + /* Initialize extif so we can get to the LEDs and external UART */
10954 + W_REG(&eir->prog_config, CF_EN);
10955 +
10956 + /* Set timing for the flash */
10957 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10958 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10959 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10960 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10961 +
10962 + /* Set programmable interface timing for external uart */
10963 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10964 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10965 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10966 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10967 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10968 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10969 +//==================================tallest===============================================
10970 + /* set register for external IO to control LED. */
10971 + W_REG(&cc->prog_config, 0x11);
10972 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10973 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10974 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
10975 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10976 +//========================================================================================
10977 + /* Set timing for the flash */
10978 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10979 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10980 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10981 +
10982 + // Added by Chen-I for 5365
10983 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
10984 + {
10985 + W_REG(&cc->flash_waitcount, tmp);
10986 + W_REG(&cc->pcmcia_memwait, tmp);
10987 + }
10988 + else
10989 + {
10990 + if (sb_corerev(sbh) < 9)
10991 + W_REG(&cc->flash_waitcount, tmp);
10992 +
10993 + if ( (sb_corerev(sbh) < 9) ||
10994 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0) ) {
10995 + W_REG(&cc->pcmcia_memwait, tmp);
10996 + }
10997 + }
10998 +
10999 + // Added by Chen-I & Yen for enabling 5350 EXTIF
11000 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
11001 + {
11002 + /* Set programmable interface timing for external uart */
11003 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
11004 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
11005 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
11006 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
11007 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
11008 + //printf("===========config_REG=%d\n", R_REG(&cc->prog_config));
11009 + //printf("-----------config_REG_addr=%x\n", &cc->prog_config);
11010 + //printf("===========waitcount_REG=%d\n", R_REG(&cc->prog_waitcount));
11011 + //printf("-----------waitcount_REG=%x\n", &cc->prog_waitcount);
11012 + }
11013 + }
11014 +
11015 + /* Chip specific initialization */
11016 + switch (BCMINIT(sb_chip)(sbh)) {
11017 + case BCM4710_DEVICE_ID:
11018 + /* Clear interrupt map */
11019 + for (irq = 0; irq <= 4; irq++)
11020 + BCMINIT(sb_clearirq)(sbh, irq);
11021 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
11022 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
11023 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
11024 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
11025 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
11026 + ASSERT(eir);
11027 + value = BCMINIT(nvram_get)("et0phyaddr");
11028 + if (value && !strcmp(value, "31")) {
11029 + /* Enable internal UART */
11030 + W_REG(&eir->corecontrol, CC_UE);
11031 + /* Give USB its own interrupt */
11032 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
11033 + } else {
11034 + /* Disable internal UART */
11035 + W_REG(&eir->corecontrol, 0);
11036 + /* Give Ethernet its own interrupt */
11037 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
11038 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
11039 + }
11040 + break;
11041 + case BCM4310_DEVICE_ID:
11042 + MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
11043 + break;
11044 + case BCM5350_DEVICE_ID:
11045 + /* Clear interrupt map */
11046 + for (irq = 0; irq <= 4; irq++)
11047 + BCMINIT(sb_clearirq)(sbh, irq);
11048 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
11049 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
11050 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
11051 + BCMINIT(sb_setirq)(sbh, 3, SB_IPSEC, 0);
11052 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
11053 + break;
11054 + }
11055 +}
11056 +
11057 +uint32
11058 +BCMINITFN(sb_mips_clock)(void *sbh)
11059 +{
11060 + extifregs_t *eir;
11061 + chipcregs_t *cc;
11062 + uint32 n, m;
11063 + uint idx;
11064 + uint32 pll_type, rate = 0;
11065 +
11066 + /* get index of the current core */
11067 + idx = sb_coreidx(sbh);
11068 + pll_type = PLL_TYPE1;
11069 +
11070 + /* switch to extif or chipc core */
11071 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
11072 + n = R_REG(&eir->clockcontrol_n);
11073 + m = R_REG(&eir->clockcontrol_sb);
11074 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
11075 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
11076 + n = R_REG(&cc->clockcontrol_n);
11077 + if ((pll_type == PLL_TYPE2) ||
11078 + (pll_type == PLL_TYPE4) ||
11079 + (pll_type == PLL_TYPE6) ||
11080 + (pll_type == PLL_TYPE7))
11081 + m = R_REG(&cc->clockcontrol_mips);
11082 + else if (pll_type == PLL_TYPE5) {
11083 + rate = 200000000;
11084 + goto out;
11085 + }
11086 + else if (pll_type == PLL_TYPE3) {
11087 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
11088 + rate = 200000000;
11089 + goto out;
11090 + } else
11091 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
11092 + } else
11093 + m = R_REG(&cc->clockcontrol_sb);
11094 + } else
11095 + goto out;
11096 +
11097 + // Added by Chen-I for 5365
11098 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
11099 + rate = 100000000;
11100 + else
11101 + /* calculate rate */
11102 + rate = sb_clock_rate(pll_type, n, m);
11103 +
11104 + if (pll_type == PLL_TYPE6)
11105 + rate = SB2MIPS_T6(rate);
11106 +
11107 +out:
11108 + /* switch back to previous core */
11109 + sb_setcoreidx(sbh, idx);
11110 +
11111 + return rate;
11112 +}
11113 +
11114 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
11115 +
11116 +static void
11117 +BCMINITFN(handler)(void)
11118 +{
11119 + /* Step 11 */
11120 + __asm__ (
11121 + ".set\tmips32\n\t"
11122 + "ssnop\n\t"
11123 + "ssnop\n\t"
11124 + /* Disable interrupts */
11125 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
11126 + "mfc0 $15, $12\n\t"
11127 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
11128 + "li $14, -31746\n\t"
11129 + "and $15, $15, $14\n\t"
11130 + "mtc0 $15, $12\n\t"
11131 + "eret\n\t"
11132 + "nop\n\t"
11133 + "nop\n\t"
11134 + ".set\tmips0"
11135 + );
11136 +}
11137 +
11138 +/* The following MUST come right after handler() */
11139 +static void
11140 +BCMINITFN(afterhandler)(void)
11141 +{
11142 +}
11143 +
11144 +/*
11145 + * Set the MIPS, backplane and PCI clocks as closely as possible.
11146 + */
11147 +bool
11148 +BCMINITFN(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
11149 +{
11150 + extifregs_t *eir = NULL;
11151 + chipcregs_t *cc = NULL;
11152 + mipsregs_t *mipsr = NULL;
11153 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
11154 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
11155 + uint32 pll_type, sync_mode;
11156 + uint ic_size, ic_lsize;
11157 + uint idx, i;
11158 + typedef struct {
11159 + uint32 mipsclock;
11160 + uint16 n;
11161 + uint32 sb;
11162 + uint32 pci33;
11163 + uint32 pci25;
11164 + } n3m_table_t;
11165 + static n3m_table_t BCMINITDATA(type1_table)[] = {
11166 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
11167 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
11168 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
11169 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
11170 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
11171 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
11172 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
11173 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
11174 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
11175 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
11176 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
11177 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
11178 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
11179 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
11180 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
11181 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
11182 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
11183 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
11184 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
11185 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
11186 + };
11187 + typedef struct {
11188 + uint32 mipsclock;
11189 + uint16 n;
11190 + uint32 m2; /* that is the clockcontrol_m2 */
11191 + } type3_table_t;
11192 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
11193 + { 150000000, 0x311, 0x4020005 },
11194 + { 200000000, 0x311, 0x4020003 },
11195 + };
11196 + typedef struct {
11197 + uint32 mipsclock;
11198 + uint32 sbclock;
11199 + uint16 n;
11200 + uint32 sb;
11201 + uint32 pci33;
11202 + uint32 m2;
11203 + uint32 m3;
11204 + uint32 ratio_cfg;
11205 + uint32 ratio_parm;
11206 + } n4m_table_t;
11207 +
11208 + static n4m_table_t BCMINITDATA(type2_table)[] = {
11209 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11210 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
11211 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
11212 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
11213 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
11214 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
11215 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11216 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
11217 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
11218 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
11219 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11220 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11221 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
11222 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11223 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
11224 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
11225 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
11226 + };
11227 +
11228 + static n4m_table_t BCMINITDATA(type4_table)[] = {
11229 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
11230 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11231 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
11232 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11233 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
11234 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11235 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11236 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
11237 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
11238 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11239 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
11240 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
11241 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
11242 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
11243 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
11244 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
11245 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
11246 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
11247 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
11248 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
11249 + };
11250 +
11251 + static n4m_table_t BCMINITDATA(type7_table)[] = {
11252 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
11253 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
11254 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11255 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
11256 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
11257 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11258 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11259 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11260 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
11261 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
11262 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
11263 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
11264 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
11265 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
11266 + };
11267 +
11268 + ulong start, end, dst;
11269 + bool ret = FALSE;
11270 +
11271 + /* get index of the current core */
11272 + idx = sb_coreidx(sbh);
11273 + clockcontrol_m2 = NULL;
11274 +
11275 + /* switch to extif or chipc core */
11276 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
11277 + pll_type = PLL_TYPE1;
11278 + clockcontrol_n = &eir->clockcontrol_n;
11279 + clockcontrol_sb = &eir->clockcontrol_sb;
11280 + clockcontrol_pci = &eir->clockcontrol_pci;
11281 + clockcontrol_m2 = &cc->clockcontrol_m2;
11282 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
11283 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
11284 + if (pll_type == PLL_TYPE6) {
11285 + clockcontrol_n = NULL;
11286 + clockcontrol_sb = NULL;
11287 + clockcontrol_pci = NULL;
11288 + } else {
11289 + clockcontrol_n = &cc->clockcontrol_n;
11290 + clockcontrol_sb = &cc->clockcontrol_sb;
11291 + clockcontrol_pci = &cc->clockcontrol_pci;
11292 + clockcontrol_m2 = &cc->clockcontrol_m2;
11293 + }
11294 + } else
11295 + goto done;
11296 +
11297 + if (pll_type == PLL_TYPE6) {
11298 + /* Silence compilers */
11299 + orig_n = orig_sb = orig_pci = 0;
11300 + } else {
11301 + /* Store the current clock register values */
11302 + orig_n = R_REG(clockcontrol_n);
11303 + orig_sb = R_REG(clockcontrol_sb);
11304 + orig_pci = R_REG(clockcontrol_pci);
11305 + }
11306 +
11307 + if (pll_type == PLL_TYPE1) {
11308 + /* Keep the current PCI clock if not specified */
11309 + if (pciclock == 0) {
11310 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
11311 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
11312 + }
11313 +
11314 + /* Search for the closest MIPS clock less than or equal to a preferred value */
11315 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
11316 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
11317 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
11318 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
11319 + break;
11320 + }
11321 + if (i == 0) {
11322 + ret = FALSE;
11323 + goto done;
11324 + } else {
11325 + ret = TRUE;
11326 + i--;
11327 + }
11328 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
11329 +
11330 + /* No PLL change */
11331 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
11332 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
11333 + (orig_pci == BCMINIT(type1_table)[i].pci33))
11334 + goto done;
11335 +
11336 + /* Set the PLL controls */
11337 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
11338 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
11339 + if (pciclock == 25000000)
11340 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
11341 + else
11342 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
11343 +
11344 + /* Reset */
11345 + sb_watchdog(sbh, 1);
11346 +
11347 + while (1);
11348 + } else if ((pll_type == PLL_TYPE3) &&
11349 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
11350 + /* 5350 */
11351 + /* Search for the closest MIPS clock less than or equal to a preferred value */
11352 +
11353 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
11354 + if (type3_table[i].mipsclock > mipsclock)
11355 + break;
11356 + }
11357 + if (i == 0) {
11358 + ret = FALSE;
11359 + goto done;
11360 + } else {
11361 + ret = TRUE;
11362 + i--;
11363 + }
11364 + ASSERT(type3_table[i].mipsclock <= mipsclock);
11365 +
11366 + /* No PLL change */
11367 + orig_m2 = R_REG(&cc->clockcontrol_m2);
11368 + if ((orig_n == type3_table[i].n) &&
11369 + (orig_m2 == type3_table[i].m2)) {
11370 + goto done;
11371 + }
11372 +
11373 + /* Set the PLL controls */
11374 + W_REG(clockcontrol_n, type3_table[i].n);
11375 + W_REG(clockcontrol_m2, type3_table[i].m2);
11376 +
11377 + /* Reset */
11378 + sb_watchdog(sbh, 1);
11379 + while (1);
11380 + } else if ((pll_type == PLL_TYPE2) ||
11381 + (pll_type == PLL_TYPE4) ||
11382 + (pll_type == PLL_TYPE6) ||
11383 + (pll_type == PLL_TYPE7)) {
11384 + n4m_table_t *table = NULL, *te;
11385 + uint tabsz = 0;
11386 +
11387 + ASSERT(cc);
11388 +
11389 + orig_mips = R_REG(&cc->clockcontrol_mips);
11390 +
11391 + if (pll_type == PLL_TYPE6) {
11392 + uint32 new_mips = 0;
11393 +
11394 + ret = TRUE;
11395 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
11396 + new_mips = CC_T6_MMASK;
11397 +
11398 + if (orig_mips == new_mips)
11399 + goto done;
11400 +
11401 + W_REG(&cc->clockcontrol_mips, new_mips);
11402 + goto end_fill;
11403 + }
11404 +
11405 + if (pll_type == PLL_TYPE2) {
11406 + table = BCMINIT(type2_table);
11407 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
11408 + } else if (pll_type == PLL_TYPE4) {
11409 + table = BCMINIT(type4_table);
11410 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
11411 + } else if (pll_type == PLL_TYPE7) {
11412 + table = BCMINIT(type7_table);
11413 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
11414 + } else
11415 + ASSERT((char *)"No table for plltype" == NULL);
11416 +
11417 + /* Store the current clock register values */
11418 + orig_m2 = R_REG(&cc->clockcontrol_m2);
11419 + orig_ratio_parm = 0;
11420 + orig_ratio_cfg = 0;
11421 +
11422 + /* Look up current ratio */
11423 + for (i = 0; i < tabsz; i++) {
11424 + if ((orig_n == table[i].n) &&
11425 + (orig_sb == table[i].sb) &&
11426 + (orig_pci == table[i].pci33) &&
11427 + (orig_m2 == table[i].m2) &&
11428 + (orig_mips == table[i].m3)) {
11429 + orig_ratio_parm = table[i].ratio_parm;
11430 + orig_ratio_cfg = table[i].ratio_cfg;
11431 + break;
11432 + }
11433 + }
11434 +
11435 + /* Search for the closest MIPS clock greater or equal to a preferred value */
11436 + for (i = 0; i < tabsz; i++) {
11437 + ASSERT(table[i].mipsclock ==
11438 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
11439 + if ((mipsclock <= table[i].mipsclock) &&
11440 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
11441 + break;
11442 + }
11443 + if (i == tabsz) {
11444 + ret = FALSE;
11445 + goto done;
11446 + } else {
11447 + te = &table[i];
11448 + ret = TRUE;
11449 + }
11450 +
11451 + /* No PLL change */
11452 + if ((orig_n == te->n) &&
11453 + (orig_sb == te->sb) &&
11454 + (orig_pci == te->pci33) &&
11455 + (orig_m2 == te->m2) &&
11456 + (orig_mips == te->m3))
11457 + goto done;
11458 +
11459 + /* Set the PLL controls */
11460 + W_REG(clockcontrol_n, te->n);
11461 + W_REG(clockcontrol_sb, te->sb);
11462 + W_REG(clockcontrol_pci, te->pci33);
11463 + W_REG(&cc->clockcontrol_m2, te->m2);
11464 + W_REG(&cc->clockcontrol_mips, te->m3);
11465 +
11466 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
11467 + if ((pll_type == PLL_TYPE7) &&
11468 + (te->sb != te->m2) &&
11469 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
11470 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
11471 +
11472 + /* No ratio change */
11473 + if (orig_ratio_parm == te->ratio_parm)
11474 + goto end_fill;
11475 +
11476 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11477 +
11478 + /* Preload the code into the cache */
11479 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
11480 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
11481 + while (start < end) {
11482 + cache_unroll(start, Fill_I);
11483 + start += ic_lsize;
11484 + }
11485 +
11486 + /* Copy the handler */
11487 + start = (ulong) &BCMINIT(handler);
11488 + end = (ulong) &BCMINIT(afterhandler);
11489 + dst = KSEG1ADDR(0x180);
11490 + for (i = 0; i < (end - start); i += 4)
11491 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
11492 +
11493 + /* Preload handler into the cache one line at a time */
11494 + for (i = 0; i < (end - start); i += 4)
11495 + cache_unroll(dst + i, Fill_I);
11496 +
11497 + /* Clear BEV bit */
11498 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
11499 +
11500 + /* Enable interrupts */
11501 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
11502 +
11503 + /* Enable MIPS timer interrupt */
11504 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
11505 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
11506 + ASSERT(mipsr);
11507 + W_REG(&mipsr->intmask, 1);
11508 +
11509 + start_fill:
11510 + /* step 1, set clock ratios */
11511 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
11512 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
11513 +
11514 + /* step 2: program timer intr */
11515 + W_REG(&mipsr->timer, 100);
11516 + (void) R_REG(&mipsr->timer);
11517 +
11518 + /* step 3, switch to async */
11519 + sync_mode = MFC0(C0_BROADCOM, 4);
11520 + MTC0(C0_BROADCOM, 4, 1 << 22);
11521 +
11522 + /* step 4, set cfg active */
11523 + MTC0(C0_BROADCOM, 2, 0x9);
11524 +
11525 +
11526 + /* steps 5 & 6 */
11527 + __asm__ __volatile__ (
11528 + ".set\tmips3\n\t"
11529 + "wait\n\t"
11530 + ".set\tmips0"
11531 + );
11532 +
11533 + /* step 7, clear cfg_active */
11534 + MTC0(C0_BROADCOM, 2, 0);
11535 +
11536 + /* Additional Step: set back to orig sync mode */
11537 + MTC0(C0_BROADCOM, 4, sync_mode);
11538 +
11539 + /* step 8, fake soft reset */
11540 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
11541 +
11542 + end_fill:
11543 + /* step 9 set watchdog timer */
11544 + sb_watchdog(sbh, 20);
11545 + (void) R_REG(&cc->chipid);
11546 +
11547 + /* step 11 */
11548 + __asm__ __volatile__ (
11549 + ".set\tmips3\n\t"
11550 + "sync\n\t"
11551 + "wait\n\t"
11552 + ".set\tmips0"
11553 + );
11554 + while (1);
11555 + }
11556 +
11557 +done:
11558 + /* switch back to previous core */
11559 + sb_setcoreidx(sbh, idx);
11560 +
11561 + return ret;
11562 +}
11563 +
11564 +
11565 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11566 +uint32
11567 +BCMINITFN(sb_memc_get_ncdl)(void *sbh)
11568 +{
11569 + sbmemcregs_t *memc;
11570 + uint32 ret = 0;
11571 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11572 + uint idx, rev;
11573 +
11574 + idx = sb_coreidx(sbh);
11575 +
11576 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11577 + if (memc == 0)
11578 + goto out;
11579 +
11580 + rev = sb_corerev(sbh);
11581 +
11582 + config = R_REG(&memc->config);
11583 + wr = R_REG(&memc->wrncdlcor);
11584 + rd = R_REG(&memc->rdncdlcor);
11585 + misc = R_REG(&memc->miscdlyctl);
11586 + dqsg = R_REG(&memc->dqsgatencdl);
11587 +
11588 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11589 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11590 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11591 +
11592 + if (config & MEMC_CONFIG_DDR) {
11593 + ret = (wr << 16) | (rd << 8) | dqsg;
11594 + } else {
11595 + if ((rev > 0) || (sb_chip(sbh) == BCM5365_DEVICE_ID))
11596 + cd = rd;
11597 + else
11598 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11599 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11600 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11601 + ret = (sm << 16) | (sd << 8) | cd;
11602 + }
11603 +
11604 +out:
11605 + /* switch back to previous core */
11606 + sb_setcoreidx(sbh, idx);
11607 +
11608 + return ret;
11609 +}
11610 +
11611 +/* returns the PFC values to be used based on the chip ID*/
11612 +
11613 +uint32
11614 +BCMINITFN(sb_mips_get_pfc)(void *sbh)
11615 +{
11616 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
11617 + return 0x11;
11618 + else
11619 + return 0x15;
11620 +}
11621 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11622 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11623 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-08-26 13:44:34.313391368 +0200
11624 @@ -0,0 +1,588 @@
11625 +/*
11626 + * Low-Level PCI and SB support for BCM47xx
11627 + *
11628 + * Copyright 2005, Broadcom Corporation
11629 + * All Rights Reserved.
11630 + *
11631 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11632 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11633 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11634 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11635 + *
11636 + * $Id: sbpci.c,v 1.7 2005/03/07 08:35:32 kanki Exp $
11637 + */
11638 +
11639 +#include <typedefs.h>
11640 +#include <pcicfg.h>
11641 +#include <bcmdevs.h>
11642 +#include <sbconfig.h>
11643 +#include <sbpci.h>
11644 +#include <osl.h>
11645 +#include <bcmendian.h>
11646 +#include <bcmutils.h>
11647 +#include <sbutils.h>
11648 +#include <bcmnvram.h>
11649 +#include <hndmips.h>
11650 +
11651 +/* Can free sbpci_init() memory after boot */
11652 +#ifndef linux
11653 +#define __init
11654 +#endif
11655 +
11656 +/* Emulated configuration space */
11657 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11658 +
11659 +/* Banned cores */
11660 +static uint16 pci_ban[32] = { 0 };
11661 +static uint pci_banned = 0;
11662 +
11663 +/* CardBus mode */
11664 +static bool cardbus = FALSE;
11665 +
11666 +/* Disable PCI host core */
11667 +static bool pci_disabled = FALSE;
11668 +
11669 +/*
11670 + * Functions for accessing external PCI configuration space
11671 + */
11672 +
11673 +/* Assume one-hot slot wiring */
11674 +#define PCI_SLOT_MAX 16
11675 +
11676 +static uint32
11677 +config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
11678 +{
11679 + uint coreidx;
11680 + sbpciregs_t *regs;
11681 + uint32 addr = 0;
11682 +
11683 + /* CardBusMode supports only one device */
11684 + if (cardbus && dev > 1)
11685 + return 0;
11686 +
11687 + coreidx = sb_coreidx(sbh);
11688 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11689 +
11690 + /* Type 0 transaction */
11691 + if (bus == 1) {
11692 + /* Skip unwired slots */
11693 + if (dev < PCI_SLOT_MAX) {
11694 + /* Slide the PCI window to the appropriate slot */
11695 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
11696 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
11697 + (func << 8) | (off & ~3);
11698 + }
11699 + }
11700 +
11701 + /* Type 1 transaction */
11702 + else {
11703 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
11704 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
11705 + }
11706 +
11707 + sb_setcoreidx(sbh, coreidx);
11708 +
11709 + return addr;
11710 +}
11711 +
11712 +static int
11713 +extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11714 +{
11715 + uint32 addr, *reg = NULL, val;
11716 + int ret = 0;
11717 +
11718 + if (pci_disabled ||
11719 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
11720 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
11721 + BUSPROBE(val, reg))
11722 + val = 0xffffffff;
11723 +
11724 + val >>= 8 * (off & 3);
11725 + if (len == 4)
11726 + *((uint32 *) buf) = val;
11727 + else if (len == 2)
11728 + *((uint16 *) buf) = (uint16) val;
11729 + else if (len == 1)
11730 + *((uint8 *) buf) = (uint8) val;
11731 + else
11732 + ret = -1;
11733 +
11734 + if (reg)
11735 + REG_UNMAP(reg);
11736 +
11737 + return ret;
11738 +}
11739 +
11740 +static int
11741 +extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11742 +{
11743 + uint32 addr, *reg = NULL, val;
11744 + int ret = 0;
11745 +
11746 + if (pci_disabled ||
11747 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
11748 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
11749 + BUSPROBE(val, reg))
11750 + goto done;
11751 +
11752 + if (len == 4)
11753 + val = *((uint32 *) buf);
11754 + else if (len == 2) {
11755 + val &= ~(0xffff << (8 * (off & 3)));
11756 + val |= *((uint16 *) buf) << (8 * (off & 3));
11757 + } else if (len == 1) {
11758 + val &= ~(0xff << (8 * (off & 3)));
11759 + val |= *((uint8 *) buf) << (8 * (off & 3));
11760 + } else
11761 + ret = -1;
11762 +
11763 + W_REG(reg, val);
11764 +
11765 + done:
11766 + if (reg)
11767 + REG_UNMAP(reg);
11768 +
11769 + return ret;
11770 +}
11771 +
11772 +/*
11773 + * Functions for accessing translated SB configuration space
11774 + */
11775 +
11776 +static int
11777 +sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11778 +{
11779 + pci_config_regs *cfg;
11780 +
11781 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
11782 + return -1;
11783 + cfg = &sb_config_regs[dev];
11784 +
11785 + ASSERT(ISALIGNED(off, len));
11786 + ASSERT(ISALIGNED((uintptr)buf, len));
11787 +
11788 + if (len == 4)
11789 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11790 + else if (len == 2)
11791 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11792 + else if (len == 1)
11793 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11794 + else
11795 + return -1;
11796 +
11797 + return 0;
11798 +}
11799 +
11800 +static int
11801 +sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11802 +{
11803 + uint coreidx, n;
11804 + void *regs;
11805 + sbconfig_t *sb;
11806 + pci_config_regs *cfg;
11807 +
11808 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
11809 + return -1;
11810 + cfg = &sb_config_regs[dev];
11811 +
11812 + ASSERT(ISALIGNED(off, len));
11813 + ASSERT(ISALIGNED((uintptr)buf, len));
11814 +
11815 + /* Emulate BAR sizing */
11816 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
11817 + len == 4 && *((uint32 *) buf) == ~0) {
11818 + coreidx = sb_coreidx(sbh);
11819 + if ((regs = sb_setcoreidx(sbh, dev))) {
11820 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11821 + /* Highest numbered address match register */
11822 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11823 + if (off == OFFSETOF(pci_config_regs, base[0]))
11824 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
11825 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
11826 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
11827 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
11828 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
11829 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
11830 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
11831 + }
11832 + sb_setcoreidx(sbh, coreidx);
11833 + return 0;
11834 + }
11835 +
11836 + if (len == 4)
11837 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11838 + else if (len == 2)
11839 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11840 + else if (len == 1)
11841 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11842 + else
11843 + return -1;
11844 +
11845 + return 0;
11846 +}
11847 +
11848 +int
11849 +sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11850 +{
11851 + if (bus == 0)
11852 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11853 + else
11854 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11855 +}
11856 +
11857 +int
11858 +sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11859 +{
11860 + if (bus == 0)
11861 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11862 + else
11863 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11864 +}
11865 +
11866 +void
11867 +sbpci_ban(uint16 core)
11868 +{
11869 + if (pci_banned < ARRAYSIZE(pci_ban))
11870 + pci_ban[pci_banned++] = core;
11871 +}
11872 +
11873 +static int
11874 +sbpci_init_pci(void *sbh)
11875 +{
11876 + uint chip, chiprev, chippkg, host;
11877 + uint32 boardflags;
11878 + sbpciregs_t *pci;
11879 + sbconfig_t *sb;
11880 + int CT4712_WR;
11881 + uint32 val;
11882 +
11883 + chip = sb_chip(sbh);
11884 + chiprev = sb_chiprev(sbh);
11885 + chippkg = sb_chippkg(sbh);
11886 +
11887 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11888 + printf("PCI: no core\n");
11889 + pci_disabled = TRUE;
11890 + return -1;
11891 + }
11892 + sb_core_reset(sbh, 0);
11893 +
11894 + boardflags = (uint32) getintvar(NULL, "boardflags");
11895 +
11896 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
11897 + pci_disabled = TRUE;
11898 +
11899 + /*
11900 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11901 + * PCI is bonded out, some boards may leave the pins
11902 + * floating.
11903 + */
11904 + if (((chip == BCM4712_DEVICE_ID) &&
11905 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11906 + (chippkg == BCM4712MID_PKG_ID))) ||
11907 + (boardflags & BFL_NOPCI))
11908 + pci_disabled = TRUE;
11909 +
11910 + /*
11911 + * If the PCI core should not be touched (disabled, not bonded
11912 + * out, or pins floating), do not even attempt to access core
11913 + * registers. Otherwise, try to determine if it is in host
11914 + * mode.
11915 + */
11916 + if (pci_disabled)
11917 + host = 0;
11918 + else
11919 + host = !BUSPROBE(val, &pci->control);
11920 +
11921 + if (!host) {
11922 + /* Disable PCI interrupts in client mode */
11923 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11924 + W_REG(&sb->sbintvec, 0);
11925 +
11926 + /* Disable the PCI bridge in client mode */
11927 + sbpci_ban(SB_PCI);
11928 + printf("PCI: Disabled\n");
11929 + } else {
11930 + /* Reset the external PCI bus and enable the clock */
11931 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
11932 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
11933 + OSL_DELAY(150); /* delay > 100 us */
11934 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
11935 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
11936 + OSL_DELAY(1); /* delay 1 us */
11937 +
11938 + /* Enable CardBusMode */
11939 + cardbus = nvram_match("cardbus", "1");
11940 + if (cardbus) {
11941 + printf("PCI: Enabling CardBus\n");
11942 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11943 + sb_gpioout(sbh, 1, 1);
11944 + sb_gpioouten(sbh, 1, 1);
11945 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
11946 + }
11947 +
11948 + /* 64 MB I/O access window */
11949 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
11950 + /* 64 MB configuration access window */
11951 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
11952 + /* 1 GB memory access window */
11953 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11954 +
11955 + /* Enable PCI bridge BAR0 prefetch and burst */
11956 + val = 6;
11957 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
11958 +
11959 + /* Enable PCI interrupts */
11960 + W_REG(&pci->intmask, PCI_INTA);
11961 + }
11962 +
11963 + return 0;
11964 +}
11965 +
11966 +static int
11967 +sbpci_init_cores(void *sbh)
11968 +{
11969 + uint chip, chiprev, chippkg, coreidx, i;
11970 + sbconfig_t *sb;
11971 + pci_config_regs *cfg;
11972 + void *regs;
11973 + char varname[8];
11974 + uint wlidx = 0;
11975 + uint16 vendor, core;
11976 + uint8 class, subclass, progif;
11977 + uint32 val;
11978 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
11979 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
11980 +
11981 + chip = sb_chip(sbh);
11982 + chiprev = sb_chiprev(sbh);
11983 + chippkg = sb_chippkg(sbh);
11984 + coreidx = sb_coreidx(sbh);
11985 +
11986 + /* Scan the SB bus */
11987 + bzero(sb_config_regs, sizeof(sb_config_regs));
11988 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
11989 + cfg->vendor = 0xffff;
11990 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
11991 + continue;
11992 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11993 +
11994 + /* Read ID register and parse vendor and core */
11995 + val = R_REG(&sb->sbidhigh);
11996 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
11997 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
11998 + progif = 0;
11999 +
12000 + /* Check if this core is banned */
12001 + for (i = 0; i < pci_banned; i++)
12002 + if (core == pci_ban[i])
12003 + break;
12004 + if (i < pci_banned)
12005 + continue;
12006 +
12007 + /* Known vendor translations */
12008 + switch (vendor) {
12009 + case SB_VEND_BCM:
12010 + vendor = VENDOR_BROADCOM;
12011 + break;
12012 + }
12013 +
12014 + /* Determine class based on known core codes */
12015 + switch (core) {
12016 + case SB_ILINE20:
12017 + class = PCI_CLASS_NET;
12018 + subclass = PCI_NET_ETHER;
12019 + core = BCM47XX_ILINE_ID;
12020 + break;
12021 + case SB_ILINE100:
12022 + class = PCI_CLASS_NET;
12023 + subclass = PCI_NET_ETHER;
12024 + core = BCM4610_ILINE_ID;
12025 + break;
12026 + case SB_ENET:
12027 + class = PCI_CLASS_NET;
12028 + subclass = PCI_NET_ETHER;
12029 + core = BCM47XX_ENET_ID;
12030 + break;
12031 + case SB_SDRAM:
12032 + case SB_MEMC:
12033 + class = PCI_CLASS_MEMORY;
12034 + subclass = PCI_MEMORY_RAM;
12035 + break;
12036 + case SB_PCI:
12037 + class = PCI_CLASS_BRIDGE;
12038 + subclass = PCI_BRIDGE_PCI;
12039 + break;
12040 + case SB_MIPS:
12041 + case SB_MIPS33:
12042 + class = PCI_CLASS_CPU;
12043 + subclass = PCI_CPU_MIPS;
12044 + break;
12045 + case SB_CODEC:
12046 + class = PCI_CLASS_COMM;
12047 + subclass = PCI_COMM_MODEM;
12048 + core = BCM47XX_V90_ID;
12049 + break;
12050 + case SB_USB:
12051 + class = PCI_CLASS_SERIAL;
12052 + subclass = PCI_SERIAL_USB;
12053 + progif = 0x10; /* OHCI */
12054 + core = BCM47XX_USB_ID;
12055 + break;
12056 + case SB_USB11H:
12057 + class = PCI_CLASS_SERIAL;
12058 + subclass = PCI_SERIAL_USB;
12059 + progif = 0x10; /* OHCI */
12060 + core = BCM47XX_USBH_ID;
12061 + break;
12062 + case SB_USB11D:
12063 + class = PCI_CLASS_SERIAL;
12064 + subclass = PCI_SERIAL_USB;
12065 + core = BCM47XX_USBD_ID;
12066 + break;
12067 + case SB_IPSEC:
12068 + class = PCI_CLASS_CRYPT;
12069 + subclass = PCI_CRYPT_NETWORK;
12070 + core = BCM47XX_IPSEC_ID;
12071 + break;
12072 + case SB_ROBO:
12073 + class = PCI_CLASS_NET;
12074 + subclass = PCI_NET_OTHER;
12075 + core = BCM47XX_ROBO_ID;
12076 + break;
12077 + case SB_EXTIF:
12078 + case SB_CC:
12079 + class = PCI_CLASS_MEMORY;
12080 + subclass = PCI_MEMORY_FLASH;
12081 + break;
12082 + case SB_D11:
12083 + class = PCI_CLASS_NET;
12084 + subclass = PCI_NET_OTHER;
12085 + /* Let an nvram variable override this */
12086 + sprintf(varname, "wl%did", wlidx);
12087 + wlidx++;
12088 + if ((core = getintvar(NULL, varname)) == 0) {
12089 + if (chip == BCM4712_DEVICE_ID) {
12090 + if (chippkg == BCM4712SMALL_PKG_ID)
12091 + core = BCM4306_D11G_ID;
12092 + else
12093 + core = BCM4306_D11DUAL_ID;
12094 + } else {
12095 + /* 4310 */
12096 + core = BCM4310_D11B_ID;
12097 + }
12098 + }
12099 + break;
12100 +
12101 + default:
12102 + class = subclass = progif = 0xff;
12103 + break;
12104 + }
12105 +
12106 + /* Supported translations */
12107 + cfg->vendor = htol16(vendor);
12108 + cfg->device = htol16(core);
12109 + cfg->rev_id = chiprev;
12110 + cfg->prog_if = progif;
12111 + cfg->sub_class = subclass;
12112 + cfg->base_class = class;
12113 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
12114 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
12115 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
12116 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
12117 + cfg->base[4] = 0;
12118 + cfg->base[5] = 0;
12119 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
12120 + cfg->header_type = PCI_HEADER_BRIDGE;
12121 + else
12122 + cfg->header_type = PCI_HEADER_NORMAL;
12123 + /* Save core interrupt flag */
12124 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
12125 + /* Default to MIPS shared interrupt 0 */
12126 + cfg->int_line = 0;
12127 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
12128 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
12129 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
12130 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12131 + val = R_REG(&sb->sbipsflag);
12132 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
12133 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
12134 + break;
12135 + }
12136 + if (cfg->int_line > 4)
12137 + cfg->int_line = 0;
12138 + }
12139 + /* Emulated core */
12140 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
12141 + }
12142 +
12143 + sb_setcoreidx(sbh, coreidx);
12144 + return 0;
12145 +}
12146 +
12147 +int __init
12148 +sbpci_init(void *sbh)
12149 +{
12150 + sbpci_init_pci(sbh);
12151 + sbpci_init_cores(sbh);
12152 + return 0;
12153 +}
12154 +
12155 +void
12156 +sbpci_check(void *sbh)
12157 +{
12158 + uint coreidx;
12159 + sbpciregs_t *pci;
12160 + uint32 sbtopci1;
12161 + uint32 buf[64], *ptr, i;
12162 + ulong pa;
12163 + volatile uint j;
12164 +
12165 + coreidx = sb_coreidx(sbh);
12166 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
12167 +
12168 + /* Clear the test array */
12169 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
12170 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
12171 + memset(ptr, 0, sizeof(buf));
12172 +
12173 + /* Point PCI window 1 to memory */
12174 + sbtopci1 = R_REG(&pci->sbtopci1);
12175 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
12176 +
12177 + /* Fill the test array via PCI window 1 */
12178 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
12179 + for (i = 0; i < ARRAYSIZE(buf); i++) {
12180 + for (j = 0; j < 2; j++);
12181 + W_REG(&ptr[i], i);
12182 + }
12183 + REG_UNMAP(ptr);
12184 +
12185 + /* Restore PCI window 1 */
12186 + W_REG(&pci->sbtopci1, sbtopci1);
12187 +
12188 + /* Check the test array */
12189 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
12190 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
12191 + for (i = 0; i < ARRAYSIZE(buf); i++) {
12192 + if (ptr[i] != i)
12193 + break;
12194 + }
12195 +
12196 + /* Change the clock if the test fails */
12197 + if (i < ARRAYSIZE(buf)) {
12198 + uint32 req, cur;
12199 +
12200 + cur = sb_clock(sbh);
12201 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
12202 + for (req = 104000000; req < 176000000; req += 4000000) {
12203 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
12204 + /* This will only reset if the clocks are valid and have changed */
12205 + sb_mips_setclock(sbh, req, 0, 0);
12206 + }
12207 + /* Should not reach here */
12208 + ASSERT(0);
12209 + }
12210 +
12211 + sb_setcoreidx(sbh, coreidx);
12212 +}
12213 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
12214 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
12215 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-08-26 13:44:34.313391368 +0200
12216 @@ -0,0 +1,261 @@
12217 +/*
12218 + * Generic setup routines for Broadcom MIPS boards
12219 + *
12220 + * Copyright 2004, Broadcom Corporation
12221 + * All Rights Reserved.
12222 + *
12223 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12224 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12225 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12226 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12227 + *
12228 + * $Id: setup.c,v 1.2 2005/04/02 12:12:57 wbx Exp $
12229 + */
12230 +
12231 +#include <linux/config.h>
12232 +#include <linux/init.h>
12233 +#include <linux/kernel.h>
12234 +#include <linux/serialP.h>
12235 +#include <linux/ide.h>
12236 +#include <asm/bootinfo.h>
12237 +#include <asm/time.h>
12238 +#include <asm/reboot.h>
12239 +
12240 +#ifdef CONFIG_MTD_PARTITIONS
12241 +#include <linux/mtd/mtd.h>
12242 +#include <linux/mtd/partitions.h>
12243 +#endif
12244 +
12245 +#include <typedefs.h>
12246 +#include <bcmutils.h>
12247 +#include <bcmnvram.h>
12248 +#include <sbmips.h>
12249 +#include <sbutils.h>
12250 +#include <trxhdr.h>
12251 +
12252 +extern void bcm947xx_time_init(void);
12253 +extern void bcm947xx_timer_setup(struct irqaction *irq);
12254 +extern void check_enable_mips_pfc(int val);
12255 +
12256 +#ifdef CONFIG_REMOTE_DEBUG
12257 +extern void set_debug_traps(void);
12258 +extern void rs_kgdb_hook(struct serial_state *);
12259 +extern void breakpoint(void);
12260 +#endif
12261 +
12262 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
12263 +extern struct ide_ops std_ide_ops;
12264 +#endif
12265 +
12266 +/* Global SB handle */
12267 +void *bcm947xx_sbh = NULL;
12268 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
12269 +EXPORT_SYMBOL(bcm947xx_sbh);
12270 +EXPORT_SYMBOL(bcm947xx_sbh_lock);
12271 +
12272 +/* Convenience */
12273 +#define sbh bcm947xx_sbh
12274 +#define sbh_lock bcm947xx_sbh_lock
12275 +
12276 +/* Kernel command line */
12277 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
12278 +
12279 +void
12280 +bcm947xx_machine_restart(char *command)
12281 +{
12282 + printk("Please stand by while rebooting the system...\n");
12283 +
12284 + /* Set the watchdog timer to reset immediately */
12285 + __cli();
12286 + sb_watchdog(sbh, 1);
12287 + while (1);
12288 +}
12289 +
12290 +void
12291 +bcm947xx_machine_halt(void)
12292 +{
12293 + printk("System halted\n");
12294 +
12295 + /* Disable interrupts and watchdog and spin forever */
12296 + __cli();
12297 + sb_watchdog(sbh, 0);
12298 + while (1);
12299 +}
12300 +
12301 +#ifdef CONFIG_SERIAL
12302 +
12303 +static struct serial_struct rs = {
12304 + line: 0,
12305 + flags: ASYNC_BOOT_AUTOCONF,
12306 + io_type: SERIAL_IO_MEM,
12307 +};
12308 +
12309 +static void __init
12310 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
12311 +{
12312 + rs.iomem_base = regs;
12313 + rs.irq = irq + 2;
12314 + rs.baud_base = baud_base / 16;
12315 + rs.iomem_reg_shift = reg_shift;
12316 +
12317 + early_serial_setup(&rs);
12318 +
12319 + rs.line++;
12320 +}
12321 +
12322 +static void __init
12323 +serial_setup(void *sbh)
12324 +{
12325 + sb_serial_init(sbh, serial_add);
12326 +
12327 +#ifdef CONFIG_REMOTE_DEBUG
12328 + /* Use the last port for kernel debugging */
12329 + if (rs.iomem_base)
12330 + rs_kgdb_hook(&rs);
12331 +#endif
12332 +}
12333 +
12334 +#endif /* CONFIG_SERIAL */
12335 +
12336 +void __init
12337 +brcm_setup(void)
12338 +{
12339 + char *value;
12340 + uint pfc_val;
12341 +
12342 + /* Get global SB handle */
12343 + sbh = sb_kattach();
12344 +
12345 + /* Initialize clocks and interrupts */
12346 + sb_mips_init(sbh);
12347 +
12348 + /*
12349 + * Now that the sbh is inited set the proper PFC value
12350 + */
12351 + pfc_val = sb_mips_get_pfc(sbh);
12352 + printk("Setting the PFC value as 0x%x\n", pfc_val);
12353 + check_enable_mips_pfc(pfc_val);
12354 +
12355 +#ifdef CONFIG_SERIAL
12356 + /* Initialize UARTs */
12357 + serial_setup(sbh);
12358 +#endif
12359 +
12360 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
12361 + ide_ops = &std_ide_ops;
12362 +#endif
12363 +
12364 + /* Override default command line arguments */
12365 + value = nvram_get("kernel_cmdline");
12366 + if (value && strlen(value) && strncmp(value, "empty", 5))
12367 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
12368 +
12369 +
12370 + /* Generic setup */
12371 + _machine_restart = bcm947xx_machine_restart;
12372 + _machine_halt = bcm947xx_machine_halt;
12373 + _machine_power_off = bcm947xx_machine_halt;
12374 +
12375 + board_time_init = bcm947xx_time_init;
12376 + board_timer_setup = bcm947xx_timer_setup;
12377 +}
12378 +
12379 +const char *
12380 +get_system_type(void)
12381 +{
12382 + return "Broadcom BCM947XX";
12383 +}
12384 +
12385 +void __init
12386 +bus_error_init(void)
12387 +{
12388 +}
12389 +
12390 +#ifdef CONFIG_MTD_PARTITIONS
12391 +
12392 +static struct mtd_partition bcm947xx_parts[] = {
12393 + { name: "pmon", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
12394 + { name: "linux", offset: 0, size: 0, },
12395 + { name: "rootfs", offset: 0, size: 0, },
12396 + { name: "nvram", offset: 0, size: 0, },
12397 + { name: "OpenWrt", offset: 0, size: 0, },
12398 + { name: NULL, },
12399 +};
12400 +
12401 +static int __init
12402 +find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
12403 +{
12404 + struct trx_header *trx;
12405 + unsigned char buf[512];
12406 + int off;
12407 + size_t len;
12408 +
12409 + trx = (struct trx_header *) buf;
12410 +
12411 + for (off = (256*1024); off < size; off += mtd->erasesize) {
12412 + memset(buf, 0xe5, sizeof(buf));
12413 +
12414 + /*
12415 + * Read into buffer
12416 + */
12417 + if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
12418 + len != sizeof(buf))
12419 + continue;
12420 +
12421 + /* found a TRX header */
12422 + if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
12423 + part->offset = le32_to_cpu(trx->offsets[2]) ? :
12424 + le32_to_cpu(trx->offsets[1]);
12425 + part->size = le32_to_cpu(trx->len);
12426 +
12427 + part->size -= part->offset;
12428 + part->offset += off;
12429 +
12430 + goto done;
12431 + }
12432 + }
12433 +
12434 + printk(KERN_NOTICE
12435 + "%s: Couldn't find root filesystem\n",
12436 + mtd->name);
12437 + return -1;
12438 +
12439 + done:
12440 + return part->size;
12441 +}
12442 +
12443 +struct mtd_partition * __init
12444 +init_mtd_partitions(struct mtd_info *mtd, size_t size)
12445 +{
12446 +
12447 + /* boot loader */
12448 + bcm947xx_parts[0].offset=0;
12449 + bcm947xx_parts[0].size=256*1024;
12450 +
12451 + /* nvram */
12452 + bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
12453 + bcm947xx_parts[3].size = size - bcm947xx_parts[3].offset;
12454 +
12455 + /* Size linux (kernel and rootfs) */
12456 + bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
12457 + bcm947xx_parts[1].size = bcm947xx_parts[3].offset - bcm947xx_parts[1].offset;
12458 +
12459 + /* Find and size rootfs */
12460 + if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
12461 + /* entirely jffs2 */
12462 + bcm947xx_parts[2].size = bcm947xx_parts[3].offset - bcm947xx_parts[2].offset;
12463 + bcm947xx_parts[4].name = NULL;
12464 + } else {
12465 + /* legacy setup */
12466 + /* calculate leftover flash, and assign it to the jffs2 partition */
12467 + bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + bcm947xx_parts[2].size;
12468 + bcm947xx_parts[4].offset = ROUNDUP(bcm947xx_parts[4].offset, mtd->erasesize);
12469 + bcm947xx_parts[4].size = bcm947xx_parts[3].offset - bcm947xx_parts[4].offset;
12470 + }
12471 +
12472 + return bcm947xx_parts;
12473 +}
12474 +
12475 +EXPORT_SYMBOL(init_mtd_partitions);
12476 +
12477 +#endif
12478 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
12479 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
12480 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-08-26 13:44:34.314391216 +0200
12481 @@ -0,0 +1,117 @@
12482 +/*
12483 + * Copyright 2004, Broadcom Corporation
12484 + * All Rights Reserved.
12485 + *
12486 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12487 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12488 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12489 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12490 + *
12491 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
12492 + */
12493 +#include <linux/config.h>
12494 +#include <linux/init.h>
12495 +#include <linux/kernel.h>
12496 +#include <linux/sched.h>
12497 +#include <linux/serial_reg.h>
12498 +#include <linux/interrupt.h>
12499 +#include <asm/addrspace.h>
12500 +#include <asm/io.h>
12501 +#include <asm/time.h>
12502 +
12503 +#include <typedefs.h>
12504 +#include <bcmnvram.h>
12505 +#include <sbconfig.h>
12506 +#include <sbextif.h>
12507 +#include <sbutils.h>
12508 +#include <sbmips.h>
12509 +
12510 +/* Global SB handle */
12511 +extern void *bcm947xx_sbh;
12512 +extern spinlock_t bcm947xx_sbh_lock;
12513 +
12514 +/* Convenience */
12515 +#define sbh bcm947xx_sbh
12516 +#define sbh_lock bcm947xx_sbh_lock
12517 +
12518 +extern int panic_timeout;
12519 +static int watchdog = 0;
12520 +static u8 *mcr = NULL;
12521 +
12522 +void __init
12523 +bcm947xx_time_init(void)
12524 +{
12525 + unsigned int hz;
12526 + extifregs_t *eir;
12527 +
12528 + /*
12529 + * Use deterministic values for initial counter interrupt
12530 + * so that calibrate delay avoids encountering a counter wrap.
12531 + */
12532 + write_c0_count(0);
12533 + write_c0_compare(0xffff);
12534 +
12535 + if (!(hz = sb_mips_clock(sbh)))
12536 + hz = 100000000;
12537 +
12538 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
12539 + (hz + 500000) / 1000000);
12540 +
12541 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
12542 + mips_hpt_frequency = hz / 2;
12543 +
12544 + /* Set watchdog interval in ms */
12545 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
12546 +
12547 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
12548 + if (watchdog > 0) {
12549 + if (watchdog < 3000)
12550 + watchdog = 3000;
12551 + }
12552 +
12553 +
12554 + /* Set panic timeout in seconds */
12555 + panic_timeout = watchdog / 1000;
12556 +
12557 + /* Setup blink */
12558 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
12559 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
12560 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
12561 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
12562 + }
12563 +}
12564 +
12565 +static void
12566 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
12567 +{
12568 + /* Generic MIPS timer code */
12569 + timer_interrupt(irq, dev_id, regs);
12570 +
12571 + /* Set the watchdog timer to reset after the specified number of ms */
12572 + if (watchdog > 0)
12573 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
12574 +
12575 +#ifdef CONFIG_HWSIM
12576 + (*((int *)0xa0000f1c))++;
12577 +#else
12578 + /* Blink one of the LEDs in the external UART */
12579 + if (mcr && !(jiffies % (HZ/2)))
12580 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
12581 +#endif
12582 +}
12583 +
12584 +static struct irqaction bcm947xx_timer_irqaction = {
12585 + bcm947xx_timer_interrupt,
12586 + SA_INTERRUPT,
12587 + 0,
12588 + "timer",
12589 + NULL,
12590 + NULL
12591 +};
12592 +
12593 +void __init
12594 +bcm947xx_timer_setup(struct irqaction *irq)
12595 +{
12596 + /* Enable the timer interrupt */
12597 + setup_irq(7, &bcm947xx_timer_irqaction);
12598 +}
12599 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
12600 --- linux.old/arch/mips/config-shared.in 2005-08-26 13:41:43.371378504 +0200
12601 +++ linux.dev/arch/mips/config-shared.in 2005-08-26 13:44:34.315391064 +0200
12602 @@ -208,6 +208,14 @@
12603 fi
12604 define_bool CONFIG_MIPS_RTC y
12605 fi
12606 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
12607 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
12608 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12609 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
12610 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
12611 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
12612 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
12613 +fi
12614 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
12615 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
12616 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
12617 @@ -229,6 +237,11 @@
12618 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
12619
12620 #
12621 +# Provide an option for a default kernel command line
12622 +#
12623 +string 'Default kernel command string' CONFIG_CMDLINE ""
12624 +
12625 +#
12626 # Select some configuration options automatically based on user selections.
12627 #
12628 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
12629 @@ -554,6 +567,13 @@
12630 define_bool CONFIG_SWAP_IO_SPACE_L y
12631 define_bool CONFIG_BOOT_ELF32 y
12632 fi
12633 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12634 + define_bool CONFIG_PCI y
12635 + define_bool CONFIG_NONCOHERENT_IO y
12636 + define_bool CONFIG_NEW_TIME_C y
12637 + define_bool CONFIG_NEW_IRQ y
12638 + define_bool CONFIG_HND y
12639 +fi
12640 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
12641 define_bool CONFIG_ARC32 y
12642 define_bool CONFIG_ARC_MEMORY y
12643 @@ -1042,7 +1062,11 @@
12644
12645 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
12646 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
12647 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
12648 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
12649 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
12650 +else
12651 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
12652 +fi
12653 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
12654 if [ "$CONFIG_KGDB" = "y" ]; then
12655 define_bool CONFIG_DEBUG_INFO y
12656 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
12657 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-08-26 13:41:41.803616840 +0200
12658 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-08-26 13:44:34.316390912 +0200
12659 @@ -163,7 +163,7 @@
12660
12661 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
12662 {
12663 - switch (c->processor_id & 0xff00) {
12664 + switch (c->processor_id & PRID_IMP_MASK) {
12665 case PRID_IMP_R2000:
12666 c->cputype = CPU_R2000;
12667 c->isa_level = MIPS_CPU_ISA_I;
12668 @@ -173,7 +173,7 @@
12669 c->tlbsize = 64;
12670 break;
12671 case PRID_IMP_R3000:
12672 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
12673 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
12674 if (cpu_has_confreg())
12675 c->cputype = CPU_R3081E;
12676 else
12677 @@ -188,12 +188,12 @@
12678 break;
12679 case PRID_IMP_R4000:
12680 if (read_c0_config() & CONF_SC) {
12681 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
12682 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
12683 c->cputype = CPU_R4400PC;
12684 else
12685 c->cputype = CPU_R4000PC;
12686 } else {
12687 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
12688 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
12689 c->cputype = CPU_R4400SC;
12690 else
12691 c->cputype = CPU_R4000SC;
12692 @@ -439,7 +439,7 @@
12693 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
12694 {
12695 decode_config1(c);
12696 - switch (c->processor_id & 0xff00) {
12697 + switch (c->processor_id & PRID_IMP_MASK) {
12698 case PRID_IMP_4KC:
12699 c->cputype = CPU_4KC;
12700 c->isa_level = MIPS_CPU_ISA_M32;
12701 @@ -480,10 +480,10 @@
12702 {
12703 decode_config1(c);
12704 c->options |= MIPS_CPU_PREFETCH;
12705 - switch (c->processor_id & 0xff00) {
12706 + switch (c->processor_id & PRID_IMP_MASK) {
12707 case PRID_IMP_AU1_REV1:
12708 case PRID_IMP_AU1_REV2:
12709 - switch ((c->processor_id >> 24) & 0xff) {
12710 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
12711 case 0:
12712 c->cputype = CPU_AU1000;
12713 break;
12714 @@ -511,10 +511,34 @@
12715 }
12716 }
12717
12718 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
12719 +{
12720 + decode_config1(c);
12721 + c->options |= MIPS_CPU_PREFETCH;
12722 + switch (c->processor_id & PRID_IMP_MASK) {
12723 + case PRID_IMP_BCM4710:
12724 + c->cputype = CPU_BCM4710;
12725 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12726 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12727 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
12728 + break;
12729 + case PRID_IMP_4KC:
12730 + case PRID_IMP_BCM3302:
12731 + c->cputype = CPU_BCM3302;
12732 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
12733 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
12734 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
12735 + break;
12736 + default:
12737 + c->cputype = CPU_UNKNOWN;
12738 + break;
12739 + }
12740 +}
12741 +
12742 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
12743 {
12744 decode_config1(c);
12745 - switch (c->processor_id & 0xff00) {
12746 + switch (c->processor_id & PRID_IMP_MASK) {
12747 case PRID_IMP_SB1:
12748 c->cputype = CPU_SB1;
12749 c->isa_level = MIPS_CPU_ISA_M64;
12750 @@ -536,7 +560,7 @@
12751 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
12752 {
12753 decode_config1(c);
12754 - switch (c->processor_id & 0xff00) {
12755 + switch (c->processor_id & PRID_IMP_MASK) {
12756 case PRID_IMP_SR71000:
12757 c->cputype = CPU_SR71000;
12758 c->isa_level = MIPS_CPU_ISA_M64;
12759 @@ -561,7 +585,7 @@
12760 c->cputype = CPU_UNKNOWN;
12761
12762 c->processor_id = read_c0_prid();
12763 - switch (c->processor_id & 0xff0000) {
12764 + switch (c->processor_id & PRID_COMP_MASK) {
12765
12766 case PRID_COMP_LEGACY:
12767 cpu_probe_legacy(c);
12768 @@ -572,6 +596,9 @@
12769 case PRID_COMP_ALCHEMY:
12770 cpu_probe_alchemy(c);
12771 break;
12772 + case PRID_COMP_BROADCOM:
12773 + cpu_probe_broadcom(c);
12774 + break;
12775 case PRID_COMP_SIBYTE:
12776 cpu_probe_sibyte(c);
12777 break;
12778 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
12779 --- linux.old/arch/mips/kernel/head.S 2005-08-26 13:41:41.804616688 +0200
12780 +++ linux.dev/arch/mips/kernel/head.S 2005-08-26 13:44:34.317390760 +0200
12781 @@ -28,12 +28,20 @@
12782 #include <asm/mipsregs.h>
12783 #include <asm/stackframe.h>
12784
12785 +#ifdef CONFIG_BCM4710
12786 +#undef eret
12787 +#define eret nop; nop; eret
12788 +#endif
12789 +
12790 .text
12791 + j kernel_entry
12792 + nop
12793 +
12794 /*
12795 * Reserved space for exception handlers.
12796 * Necessary for machines which link their kernels at KSEG0.
12797 */
12798 - .fill 0x400
12799 + .fill 0x3f4
12800
12801 /* The following two symbols are used for kernel profiling. */
12802 EXPORT(stext)
12803 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
12804 --- linux.old/arch/mips/kernel/proc.c 2005-01-19 15:09:29.000000000 +0100
12805 +++ linux.dev/arch/mips/kernel/proc.c 2005-08-26 13:44:34.318390608 +0200
12806 @@ -78,9 +78,10 @@
12807 [CPU_AU1550] "Au1550",
12808 [CPU_24K] "MIPS 24K",
12809 [CPU_AU1200] "Au1200",
12810 + [CPU_BCM4710] "BCM4710",
12811 + [CPU_BCM3302] "BCM3302",
12812 };
12813
12814 -
12815 static int show_cpuinfo(struct seq_file *m, void *v)
12816 {
12817 unsigned int version = current_cpu_data.processor_id;
12818 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
12819 --- linux.old/arch/mips/kernel/setup.c 2005-08-26 13:41:41.805616536 +0200
12820 +++ linux.dev/arch/mips/kernel/setup.c 2005-08-26 13:44:34.318390608 +0200
12821 @@ -493,6 +493,7 @@
12822 void swarm_setup(void);
12823 void hp_setup(void);
12824 void au1x00_setup(void);
12825 + void brcm_setup(void);
12826 void frame_info_init(void);
12827
12828 frame_info_init();
12829 @@ -691,6 +692,11 @@
12830 pmc_yosemite_setup();
12831 break;
12832 #endif
12833 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
12834 + case MACH_GROUP_BRCM:
12835 + brcm_setup();
12836 + break;
12837 +#endif
12838 default:
12839 panic("Unsupported architecture");
12840 }
12841 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
12842 --- linux.old/arch/mips/kernel/traps.c 2005-08-26 13:41:41.806616384 +0200
12843 +++ linux.dev/arch/mips/kernel/traps.c 2005-08-26 13:44:34.321390152 +0200
12844 @@ -920,6 +920,7 @@
12845 void __init trap_init(void)
12846 {
12847 extern char except_vec1_generic;
12848 + extern char except_vec2_generic;
12849 extern char except_vec3_generic, except_vec3_r4000;
12850 extern char except_vec_ejtag_debug;
12851 extern char except_vec4;
12852 @@ -927,6 +928,7 @@
12853
12854 /* Copy the generic exception handler code to it's final destination. */
12855 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
12856 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
12857
12858 /*
12859 * Setup default vectors
12860 @@ -985,6 +987,12 @@
12861 set_except_vector(13, handle_tr);
12862 set_except_vector(22, handle_mdmx);
12863
12864 + if (current_cpu_data.cputype == CPU_SB1) {
12865 + /* Enable timer interrupt and scd mapped interrupt */
12866 + clear_c0_status(0xf000);
12867 + set_c0_status(0xc00);
12868 + }
12869 +
12870 if (cpu_has_fpu && !cpu_has_nofpuex)
12871 set_except_vector(15, handle_fpe);
12872
12873 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
12874 --- linux.old/arch/mips/mm/c-r4k.c 2005-08-26 13:41:41.825613496 +0200
12875 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-08-26 13:44:34.322390000 +0200
12876 @@ -1118,3 +1118,47 @@
12877 build_clear_page();
12878 build_copy_page();
12879 }
12880 +
12881 +#ifdef CONFIG_BCM4704
12882 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
12883 +{
12884 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
12885 + int i;
12886 + for (i = 0; i < nbytes; i += ic_lsize)
12887 + fill_icache_line((addr + i));
12888 +}
12889 +
12890 +/*
12891 + * This must be run from the cache on 4704A0
12892 + * so there are no mips core BIU ops in progress
12893 + * when the PFC is enabled.
12894 + */
12895 +#define PFC_CR0 0xff400000 /* control reg 0 */
12896 +#define PFC_CR1 0xff400004 /* control reg 1 */
12897 +static void __init enable_pfc(u32 mode)
12898 +{
12899 + /* write range */
12900 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
12901 +
12902 + /* enable */
12903 + *(volatile u32 *)PFC_CR0 = mode;
12904 +}
12905 +#endif
12906 +
12907 +
12908 +void check_enable_mips_pfc(int val)
12909 +{
12910 +
12911 +#ifdef CONFIG_BCM4704
12912 + struct cpuinfo_mips *c = &current_cpu_data;
12913 +
12914 + /* enable prefetch cache */
12915 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
12916 + && (read_c0_diag() & (1 << 29))) {
12917 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
12918 + enable_pfc(val);
12919 + }
12920 +#endif
12921 +}
12922 +
12923 +
12924 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
12925 --- linux.old/arch/mips/pci/Makefile 2005-01-19 15:09:29.000000000 +0100
12926 +++ linux.dev/arch/mips/pci/Makefile 2005-08-26 13:44:34.323389848 +0200
12927 @@ -13,7 +13,9 @@
12928 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
12929 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
12930 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
12931 +ifndef CONFIG_BCM947XX
12932 obj-y += pci.o
12933 +endif
12934 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
12935
12936 include $(TOPDIR)/Rules.make
12937 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
12938 --- linux.old/drivers/char/serial.c 2005-08-26 13:41:41.952594192 +0200
12939 +++ linux.dev/drivers/char/serial.c 2005-08-26 13:44:34.340387264 +0200
12940 @@ -444,6 +444,10 @@
12941 return inb(info->port+1);
12942 #endif
12943 case SERIAL_IO_MEM:
12944 +#ifdef CONFIG_BCM4310
12945 + readb((unsigned long) info->iomem_base +
12946 + (UART_SCR<<info->iomem_reg_shift));
12947 +#endif
12948 return readb((unsigned long) info->iomem_base +
12949 (offset<<info->iomem_reg_shift));
12950 default:
12951 @@ -464,6 +468,9 @@
12952 case SERIAL_IO_MEM:
12953 writeb(value, (unsigned long) info->iomem_base +
12954 (offset<<info->iomem_reg_shift));
12955 +#ifdef CONFIG_BCM4704
12956 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
12957 +#endif
12958 break;
12959 default:
12960 outb(value, info->port+offset);
12961 @@ -5996,6 +6003,13 @@
12962 * Divisor, bytesize and parity
12963 */
12964 state = rs_table + co->index;
12965 + /*
12966 + * Safe guard: state structure must have been initialized
12967 + */
12968 + if (state->iomem_base == NULL) {
12969 + printk("!unable to setup serial console!\n");
12970 + return -1;
12971 + }
12972 if (doflow)
12973 state->flags |= ASYNC_CONS_FLOW;
12974 info = &async_sercons;
12975 diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
12976 --- linux.old/drivers/mtd/maps/Config.in 2005-08-26 13:41:41.963592520 +0200
12977 +++ linux.dev/drivers/mtd/maps/Config.in 2005-08-26 13:44:34.345386504 +0200
12978 @@ -48,6 +48,7 @@
12979 fi
12980
12981 if [ "$CONFIG_MIPS" = "y" ]; then
12982 + dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
12983 dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
12984 dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
12985 dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
12986 diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
12987 --- linux.old/drivers/mtd/maps/Makefile 2005-08-26 13:41:41.963592520 +0200
12988 +++ linux.dev/drivers/mtd/maps/Makefile 2005-08-26 13:44:34.346386352 +0200
12989 @@ -3,6 +3,8 @@
12990 #
12991 # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
12992
12993 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
12994 +
12995 BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
12996
12997 ifeq ($(BELOW25),y)
12998 @@ -10,6 +12,7 @@
12999 endif
13000
13001 # Chip mappings
13002 +obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
13003 obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
13004 obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
13005 obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
13006 diff -urN linux.old/drivers/mtd/maps/bcm947xx-flash.c linux.dev/drivers/mtd/maps/bcm947xx-flash.c
13007 --- linux.old/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
13008 +++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-08-26 13:44:34.346386352 +0200
13009 @@ -0,0 +1,236 @@
13010 +/*
13011 + * Flash mapping for BCM947XX boards
13012 + *
13013 + * Copyright 2004, Broadcom Corporation
13014 + * All Rights Reserved.
13015 + *
13016 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13017 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13018 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13019 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13020 + *
13021 + * $Id: bcm947xx-flash.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
13022 + */
13023 +
13024 +#include <linux/module.h>
13025 +#include <linux/types.h>
13026 +#include <linux/kernel.h>
13027 +#include <asm/io.h>
13028 +#include <linux/mtd/mtd.h>
13029 +#include <linux/mtd/map.h>
13030 +#include <linux/mtd/partitions.h>
13031 +#include <linux/config.h>
13032 +
13033 +#include <typedefs.h>
13034 +#include <bcmnvram.h>
13035 +#include <bcmutils.h>
13036 +#include <sbconfig.h>
13037 +#include <sbchipc.h>
13038 +#include <sbutils.h>
13039 +#include <trxhdr.h>
13040 +
13041 +/* Global SB handle */
13042 +extern void *bcm947xx_sbh;
13043 +extern spinlock_t bcm947xx_sbh_lock;
13044 +
13045 +/* Convenience */
13046 +#define sbh bcm947xx_sbh
13047 +#define sbh_lock bcm947xx_sbh_lock
13048 +
13049 +#ifdef CONFIG_MTD_PARTITIONS
13050 +extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
13051 +#endif
13052 +
13053 +#define WINDOW_ADDR 0x1fc00000
13054 +#define WINDOW_SIZE 0x400000
13055 +#define BUSWIDTH 2
13056 +
13057 +/* e.g., flash=2M or flash=4M */
13058 +static int flash = 0;
13059 +MODULE_PARM(flash, "i");
13060 +static int __init
13061 +bcm947xx_setup(char *str)
13062 +{
13063 + flash = memparse(str, &str);
13064 + return 1;
13065 +}
13066 +__setup("flash=", bcm947xx_setup);
13067 +
13068 +static struct mtd_info *bcm947xx_mtd;
13069 +
13070 +__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
13071 +{
13072 + if (map->map_priv_2 == 1)
13073 + return __raw_readb(map->map_priv_1 + ofs);
13074 +
13075 + u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
13076 + if (ofs & 1)
13077 + return ((val >> 8) & 0xff);
13078 + else
13079 + return (val & 0xff);
13080 +}
13081 +
13082 +__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
13083 +{
13084 + return __raw_readw(map->map_priv_1 + ofs);
13085 +}
13086 +
13087 +__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
13088 +{
13089 + return __raw_readl(map->map_priv_1 + ofs);
13090 +}
13091 +
13092 +void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
13093 +{
13094 + if (len==1) {
13095 + memcpy_fromio(to, map->map_priv_1 + from, len);
13096 + } else {
13097 + int i;
13098 + u16 *dest = (u16 *) to;
13099 + u16 *src = (u16 *) (map->map_priv_1 + from);
13100 + for (i = 0; i < (len / 2); i++) {
13101 + dest[i] = src[i];
13102 + }
13103 + if (len & 1)
13104 + *((u8 *)dest+len-1) = src[i] & 0xff;
13105 + }
13106 +}
13107 +
13108 +void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
13109 +{
13110 + __raw_writeb(d, map->map_priv_1 + adr);
13111 + mb();
13112 +}
13113 +
13114 +void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
13115 +{
13116 + __raw_writew(d, map->map_priv_1 + adr);
13117 + mb();
13118 +}
13119 +
13120 +void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
13121 +{
13122 + __raw_writel(d, map->map_priv_1 + adr);
13123 + mb();
13124 +}
13125 +
13126 +void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
13127 +{
13128 + memcpy_toio(map->map_priv_1 + to, from, len);
13129 +}
13130 +
13131 +struct map_info bcm947xx_map = {
13132 + name: "Physically mapped flash",
13133 + size: WINDOW_SIZE,
13134 + buswidth: BUSWIDTH,
13135 + read8: bcm947xx_map_read8,
13136 + read16: bcm947xx_map_read16,
13137 + read32: bcm947xx_map_read32,
13138 + copy_from: bcm947xx_map_copy_from,
13139 + write8: bcm947xx_map_write8,
13140 + write16: bcm947xx_map_write16,
13141 + write32: bcm947xx_map_write32,
13142 + copy_to: bcm947xx_map_copy_to
13143 +};
13144 +
13145 +#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
13146 +#define init_bcm947xx_map init_module
13147 +#define cleanup_bcm947xx_map cleanup_module
13148 +#endif
13149 +
13150 +mod_init_t init_bcm947xx_map(void)
13151 +{
13152 + ulong flags;
13153 + uint coreidx;
13154 + chipcregs_t *cc;
13155 + uint32 fltype;
13156 + uint window_addr = 0, window_size = 0;
13157 + size_t size;
13158 + int ret = 0;
13159 +#ifdef CONFIG_MTD_PARTITIONS
13160 + struct mtd_partition *parts;
13161 + int i;
13162 +#endif
13163 +
13164 + spin_lock_irqsave(&sbh_lock, flags);
13165 + coreidx = sb_coreidx(sbh);
13166 +
13167 + /* Check strapping option if chipcommon exists */
13168 + if ((cc = sb_setcore(sbh, SB_CC, 0))) {
13169 + fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
13170 + if (fltype == PFLASH) {
13171 + bcm947xx_map.map_priv_2 = 1;
13172 + window_addr = 0x1c000000;
13173 + bcm947xx_map.size = window_size = 32 * 1024 * 1024;
13174 + if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
13175 + bcm947xx_map.buswidth = 1;
13176 + }
13177 + } else {
13178 + fltype = PFLASH;
13179 + bcm947xx_map.map_priv_2 = 0;
13180 + window_addr = WINDOW_ADDR;
13181 + window_size = WINDOW_SIZE;
13182 + }
13183 +
13184 + sb_setcoreidx(sbh, coreidx);
13185 + spin_unlock_irqrestore(&sbh_lock, flags);
13186 +
13187 + if (fltype != PFLASH) {
13188 + printk(KERN_ERR "pflash: found no supported devices\n");
13189 + ret = -ENODEV;
13190 + goto fail;
13191 + }
13192 +
13193 + bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
13194 + if (!bcm947xx_map.map_priv_1) {
13195 + printk(KERN_ERR "pflash: ioremap failed\n");
13196 + ret = -EIO;
13197 + goto fail;
13198 + }
13199 +
13200 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
13201 + printk(KERN_ERR "pflash: cfi_probe failed\n");
13202 + ret = -ENXIO;
13203 + goto fail;
13204 + }
13205 +
13206 + bcm947xx_mtd->module = THIS_MODULE;
13207 +
13208 + /* Allow size override for testing */
13209 + size = flash ? : bcm947xx_mtd->size;
13210 +
13211 + printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
13212 +
13213 +#ifdef CONFIG_MTD_PARTITIONS
13214 + parts = init_mtd_partitions(bcm947xx_mtd, size);
13215 + for (i = 0; parts[i].name; i++);
13216 + ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
13217 + if (ret) {
13218 + printk(KERN_ERR "pflash: add_mtd_partitions failed\n");
13219 + goto fail;
13220 + }
13221 +#endif
13222 +
13223 + return 0;
13224 +
13225 + fail:
13226 + if (bcm947xx_mtd)
13227 + map_destroy(bcm947xx_mtd);
13228 + if (bcm947xx_map.map_priv_1)
13229 + iounmap((void *) bcm947xx_map.map_priv_1);
13230 + bcm947xx_map.map_priv_1 = 0;
13231 + return ret;
13232 +}
13233 +
13234 +mod_exit_t cleanup_bcm947xx_map(void)
13235 +{
13236 +#ifdef CONFIG_MTD_PARTITIONS
13237 + del_mtd_partitions(bcm947xx_mtd);
13238 +#endif
13239 + map_destroy(bcm947xx_mtd);
13240 + iounmap((void *) bcm947xx_map.map_priv_1);
13241 + bcm947xx_map.map_priv_1 = 0;
13242 +}
13243 +
13244 +module_init(init_bcm947xx_map);
13245 +module_exit(cleanup_bcm947xx_map);
13246 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
13247 --- linux.old/drivers/net/Config.in 2005-08-26 13:41:43.481361784 +0200
13248 +++ linux.dev/drivers/net/Config.in 2005-08-26 13:44:34.358384528 +0200
13249 @@ -2,6 +2,8 @@
13250 # Network device configuration
13251 #
13252
13253 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
13254 +
13255 source drivers/net/arcnet/Config.in
13256
13257 tristate 'Dummy net driver support' CONFIG_DUMMY
13258 @@ -174,6 +176,7 @@
13259
13260 dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
13261 dep_tristate ' Broadcom 4400 ethernet support (EXPERIMENTAL)' CONFIG_B44 $CONFIG_PCI $CONFIG_EXPERIMENTAL
13262 + dep_tristate ' Proprietary Broadcom 10/100 Ethernet support' CONFIG_ET $CONFIG_PCI
13263 dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
13264 dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
13265 if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
13266 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
13267 --- linux.old/drivers/net/Makefile 2005-08-26 13:41:43.082422432 +0200
13268 +++ linux.dev/drivers/net/Makefile 2005-08-26 13:44:34.370382704 +0200
13269 @@ -3,6 +3,8 @@
13270 # Makefile for the Linux network (ethercard) device drivers.
13271 #
13272
13273 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
13274 +
13275 obj-y :=
13276 obj-m :=
13277 obj-n :=
13278 @@ -39,6 +41,9 @@
13279 obj-$(CONFIG_ISDN) += slhc.o
13280 endif
13281
13282 +subdir-$(CONFIG_HND) += hnd
13283 +subdir-$(CONFIG_ET) += et
13284 +subdir-$(CONFIG_WL) += wl
13285 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
13286 subdir-$(CONFIG_NET_WIRELESS) += wireless
13287 subdir-$(CONFIG_TULIP) += tulip
13288 @@ -69,6 +74,16 @@
13289 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
13290 obj-$(CONFIG_SUNGEM) += sungem.o
13291
13292 +ifeq ($(CONFIG_HND),y)
13293 + obj-y += hnd/hnd.o
13294 +endif
13295 +ifeq ($(CONFIG_ET),y)
13296 + obj-y += et/et.o
13297 +endif
13298 +ifeq ($(CONFIG_WL),y)
13299 + obj-y += wl/wl.o
13300 +endif
13301 +
13302 obj-$(CONFIG_MACE) += mace.o
13303 obj-$(CONFIG_BMAC) += bmac.o
13304 obj-$(CONFIG_GMAC) += gmac.o
13305 @@ -266,6 +281,7 @@
13306 endif
13307 endif
13308
13309 +
13310 include $(TOPDIR)/Rules.make
13311
13312 clean:
13313 diff -urN linux.old/drivers/net/et/Makefile linux.dev/drivers/net/et/Makefile
13314 --- linux.old/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
13315 +++ linux.dev/drivers/net/et/Makefile 2005-08-26 13:44:34.371382552 +0200
13316 @@ -0,0 +1,21 @@
13317 +#
13318 +# Makefile for the Broadcom et driver
13319 +#
13320 +# Copyright 2004, Broadcom Corporation
13321 +# All Rights Reserved.
13322 +#
13323 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13324 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13325 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13326 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13327 +#
13328 +# $Id: Makefile,v 1.1 2005/03/16 13:50:00 wbx Exp $
13329 +#
13330 +
13331 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCM47XX_CHOPS -DDMA -DBCMDRIVER
13332 +
13333 +O_TARGET := et.o
13334 +obj-y := et_linux.o etc.o etc47xx.o etc_robo.o etc_adm.o
13335 +obj-m := $(O_TARGET)
13336 +
13337 +include $(TOPDIR)/Rules.make
13338 diff -urN linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
13339 --- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
13340 +++ linux.dev/drivers/net/hnd/Makefile 2005-08-26 13:44:34.371382552 +0200
13341 @@ -0,0 +1,19 @@
13342 +#
13343 +# Makefile for the BCM47xx specific kernel interface routines
13344 +# under Linux.
13345 +#
13346 +
13347 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
13348 +
13349 +O_TARGET := hnd.o
13350 +
13351 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
13352 +
13353 +export-objs := shared_ksyms.o
13354 +obj-y := shared_ksyms.o $(HND_OBJS)
13355 +obj-m := $(O_TARGET)
13356 +
13357 +include $(TOPDIR)/Rules.make
13358 +
13359 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
13360 + sh -e $< $(HND_OBJS) > $@
13361 diff -urN linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
13362 --- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
13363 +++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-08-26 13:44:34.372382400 +0200
13364 @@ -0,0 +1,714 @@
13365 +/*
13366 + * Misc useful routines to access NIC SROM/OTP .
13367 + *
13368 + * Copyright 2004, Broadcom Corporation
13369 + * All Rights Reserved.
13370 + *
13371 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13372 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13373 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13374 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13375 + * $Id$
13376 + */
13377 +
13378 +#include <typedefs.h>
13379 +#include <osl.h>
13380 +#include <bcmutils.h>
13381 +#include <bcmsrom.h>
13382 +#include <bcmdevs.h>
13383 +#include <bcmendian.h>
13384 +#include <sbpcmcia.h>
13385 +#include <pcicfg.h>
13386 +#include <sbutils.h>
13387 +
13388 +#include <proto/ethernet.h> /* for sprom content groking */
13389 +
13390 +#define VARS_MAX 4096 /* should be reduced */
13391 +
13392 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
13393 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
13394 +
13395 +static int initvars_srom_pci(void *osh, void *curmap, char **vars, int *count);
13396 +static int initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count);
13397 +static int srom_parsecis(void *osh, uint8 *cis, char **vars, int *count);
13398 +static int sprom_cmd_pcmcia(void *osh, uint8 cmd);
13399 +static int sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data);
13400 +static int sprom_write_pcmcia(void *osh, uint16 addr, uint16 data);
13401 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
13402 +
13403 +/*
13404 + * Initialize local vars from the right source for this platform.
13405 + * Return 0 on success, nonzero on error.
13406 + */
13407 +int
13408 +srom_var_init(void *sbh, uint bustype, void *curmap, void *osh, char **vars, int *count)
13409 +{
13410 + ASSERT(bustype == BUSTYPE(bustype));
13411 + if (vars == NULL)
13412 + return (0);
13413 +
13414 + switch (BUSTYPE(bustype)) {
13415 + case SB_BUS:
13416 + /* These two could be asserts ... */
13417 + *vars = NULL;
13418 + *count = 0;
13419 + return(0);
13420 +
13421 + case PCI_BUS:
13422 + ASSERT(curmap); /* can not be NULL */
13423 + return(initvars_srom_pci(osh, curmap, vars, count));
13424 +
13425 + case PCMCIA_BUS:
13426 + return(initvars_cis_pcmcia(sbh, curmap, osh, vars, count));
13427 +
13428 +
13429 + default:
13430 + ASSERT(0);
13431 + }
13432 + return (-1);
13433 +}
13434 +
13435 +/* support only 16-bit word read from srom */
13436 +int
13437 +srom_read(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
13438 +{
13439 + void *srom;
13440 + uint i, off, nw;
13441 +
13442 + ASSERT(bustype == BUSTYPE(bustype));
13443 +
13444 + /* check input - 16-bit access only */
13445 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
13446 + return 1;
13447 +
13448 + off = byteoff / 2;
13449 + nw = nbytes / 2;
13450 +
13451 + if (BUSTYPE(bustype) == PCI_BUS) {
13452 + if (!curmap)
13453 + return 1;
13454 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
13455 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
13456 + return 1;
13457 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
13458 + for (i = 0; i < nw; i++) {
13459 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
13460 + return 1;
13461 + }
13462 + } else {
13463 + return 1;
13464 + }
13465 +
13466 + return 0;
13467 +}
13468 +
13469 +/* support only 16-bit word write into srom */
13470 +int
13471 +srom_write(uint bustype, void *curmap, void *osh, uint byteoff, uint nbytes, uint16 *buf)
13472 +{
13473 + uint16 *srom;
13474 + uint i, off, nw, crc_range;
13475 + uint16 image[SPROM_SIZE], *p;
13476 + uint8 crc;
13477 + volatile uint32 val32;
13478 +
13479 + ASSERT(bustype == BUSTYPE(bustype));
13480 +
13481 + /* check input - 16-bit access only */
13482 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
13483 + return 1;
13484 +
13485 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
13486 +
13487 + /* if changes made inside crc cover range */
13488 + if (byteoff < crc_range) {
13489 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
13490 + /* read data including entire first 64 words from srom */
13491 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
13492 + return 1;
13493 + /* make changes */
13494 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
13495 + /* calculate crc */
13496 + htol16_buf(image, crc_range);
13497 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
13498 + ltoh16_buf(image, crc_range);
13499 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
13500 + p = image;
13501 + off = 0;
13502 + } else {
13503 + p = buf;
13504 + off = byteoff / 2;
13505 + nw = nbytes / 2;
13506 + }
13507 +
13508 + if (BUSTYPE(bustype) == PCI_BUS) {
13509 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
13510 + /* enable writes to the SPROM */
13511 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
13512 + val32 |= SPROM_WRITEEN;
13513 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
13514 + bcm_mdelay(WRITE_ENABLE_DELAY);
13515 + /* write srom */
13516 + for (i = 0; i < nw; i++) {
13517 + W_REG(&srom[off + i], p[i]);
13518 + bcm_mdelay(WRITE_WORD_DELAY);
13519 + }
13520 + /* disable writes to the SPROM */
13521 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
13522 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
13523 + /* enable writes to the SPROM */
13524 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
13525 + return 1;
13526 + bcm_mdelay(WRITE_ENABLE_DELAY);
13527 + /* write srom */
13528 + for (i = 0; i < nw; i++) {
13529 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
13530 + bcm_mdelay(WRITE_WORD_DELAY);
13531 + }
13532 + /* disable writes to the SPROM */
13533 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
13534 + return 1;
13535 + } else {
13536 + return 1;
13537 + }
13538 +
13539 + bcm_mdelay(WRITE_ENABLE_DELAY);
13540 + return 0;
13541 +}
13542 +
13543 +
13544 +static int
13545 +srom_parsecis(void *osh, uint8 *cis, char **vars, int *count)
13546 +{
13547 + char eabuf[32];
13548 + char *vp, *base;
13549 + uint8 tup, tlen, sromrev = 1;
13550 + int i, j;
13551 + uint varsize;
13552 + bool ag_init = FALSE;
13553 + uint16 w;
13554 +
13555 + ASSERT(vars);
13556 + ASSERT(count);
13557 +
13558 + base = vp = MALLOC(osh, VARS_MAX);
13559 + ASSERT(vp);
13560 +
13561 + i = 0;
13562 + do {
13563 + tup = cis[i++];
13564 + tlen = cis[i++];
13565 + if ((i + tlen) >= CIS_SIZE)
13566 + break;
13567 +
13568 + switch (tup) {
13569 + case CISTPL_MANFID:
13570 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
13571 + vp++;
13572 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
13573 + vp++;
13574 + break;
13575 +
13576 + case CISTPL_FUNCE:
13577 + if (cis[i] == LAN_NID) {
13578 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
13579 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
13580 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
13581 + vp++;
13582 + }
13583 + break;
13584 +
13585 + case CISTPL_CFTABLE:
13586 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
13587 + vp++;
13588 + break;
13589 +
13590 + case CISTPL_BRCM_HNBU:
13591 + switch (cis[i]) {
13592 + case HNBU_CHIPID:
13593 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
13594 + vp++;
13595 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
13596 + vp++;
13597 + if (tlen == 7) {
13598 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
13599 + vp++;
13600 + }
13601 + break;
13602 +
13603 + case HNBU_BOARDREV:
13604 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
13605 + vp++;
13606 + break;
13607 +
13608 + case HNBU_AA:
13609 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
13610 + vp++;
13611 + break;
13612 +
13613 + case HNBU_AG:
13614 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
13615 + vp++;
13616 + ag_init = TRUE;
13617 + break;
13618 +
13619 + case HNBU_CC:
13620 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
13621 + vp++;
13622 + break;
13623 +
13624 + case HNBU_PAPARMS:
13625 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + tlen - 1]);
13626 + vp++;
13627 + if (tlen == 9) {
13628 + /* New version */
13629 + for (j = 0; j < 3; j++) {
13630 + vp += sprintf(vp, "pa0b%d=%d", j,
13631 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
13632 + vp++;
13633 + }
13634 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
13635 + vp++;
13636 + }
13637 + break;
13638 +
13639 + case HNBU_OEM:
13640 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
13641 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
13642 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
13643 + vp++;
13644 + break;
13645 + case HNBU_BOARDFLAGS:
13646 + w = (cis[i + 2] << 8) + cis[i + 1];
13647 + if (w == 0xffff) w = 0;
13648 + vp += sprintf(vp, "boardflags=%d", w);
13649 + vp++;
13650 + break;
13651 + case HNBU_LED:
13652 + if (cis[i + 1] != 0xff) {
13653 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
13654 + vp++;
13655 + }
13656 + if (cis[i + 2] != 0xff) {
13657 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
13658 + vp++;
13659 + }
13660 + if (cis[i + 3] != 0xff) {
13661 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
13662 + vp++;
13663 + }
13664 + if (cis[i + 4] != 0xff) {
13665 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
13666 + vp++;
13667 + }
13668 + break;
13669 + }
13670 + break;
13671 +
13672 + }
13673 + i += tlen;
13674 + } while (tup != 0xff);
13675 +
13676 + /* Set the srom version */
13677 + vp += sprintf(vp, "sromrev=%d", sromrev);
13678 + vp++;
13679 +
13680 + /* For now just set boardflags2 to zero */
13681 + vp += sprintf(vp, "boardflags2=0");
13682 + vp++;
13683 +
13684 + /* if there is no antenna gain field, set default */
13685 + if (ag_init == FALSE) {
13686 + vp += sprintf(vp, "ag0=%d", 0xff);
13687 + vp++;
13688 + }
13689 +
13690 + /* final nullbyte terminator */
13691 + *vp++ = '\0';
13692 + varsize = (uint)(vp - base);
13693 +
13694 + ASSERT((vp - base) < VARS_MAX);
13695 +
13696 + if (varsize == VARS_MAX) {
13697 + *vars = base;
13698 + } else {
13699 + vp = MALLOC(osh, varsize);
13700 + ASSERT(vp);
13701 + bcopy(base, vp, varsize);
13702 + MFREE(osh, base, VARS_MAX);
13703 + *vars = vp;
13704 + }
13705 + *count = varsize;
13706 +
13707 + return (0);
13708 +}
13709 +
13710 +
13711 +/* set PCMCIA sprom command register */
13712 +static int
13713 +sprom_cmd_pcmcia(void *osh, uint8 cmd)
13714 +{
13715 + uint8 status = 0;
13716 + uint wait_cnt = 1000;
13717 +
13718 + /* write sprom command register */
13719 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
13720 +
13721 + /* wait status */
13722 + while (wait_cnt--) {
13723 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
13724 + if (status & SROM_DONE)
13725 + return 0;
13726 + }
13727 +
13728 + return 1;
13729 +}
13730 +
13731 +/* read a word from the PCMCIA srom */
13732 +static int
13733 +sprom_read_pcmcia(void *osh, uint16 addr, uint16 *data)
13734 +{
13735 + uint8 addr_l, addr_h, data_l, data_h;
13736 +
13737 + addr_l = (uint8)((addr * 2) & 0xff);
13738 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
13739 +
13740 + /* set address */
13741 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
13742 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
13743 +
13744 + /* do read */
13745 + if (sprom_cmd_pcmcia(osh, SROM_READ))
13746 + return 1;
13747 +
13748 + /* read data */
13749 + data_h = data_l = 0;
13750 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
13751 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
13752 +
13753 + *data = (data_h << 8) | data_l;
13754 + return 0;
13755 +}
13756 +
13757 +/* write a word to the PCMCIA srom */
13758 +static int
13759 +sprom_write_pcmcia(void *osh, uint16 addr, uint16 data)
13760 +{
13761 + uint8 addr_l, addr_h, data_l, data_h;
13762 +
13763 + addr_l = (uint8)((addr * 2) & 0xff);
13764 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
13765 + data_l = (uint8)(data & 0xff);
13766 + data_h = (uint8)((data >> 8) & 0xff);
13767 +
13768 + /* set address */
13769 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
13770 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
13771 +
13772 + /* write data */
13773 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
13774 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
13775 +
13776 + /* do write */
13777 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
13778 +}
13779 +
13780 +/*
13781 + * Read in and validate sprom.
13782 + * Return 0 on success, nonzero on error.
13783 + */
13784 +static int
13785 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
13786 +{
13787 + uint8 chk8;
13788 + uint i;
13789 +
13790 + /* read the sprom */
13791 + for (i = 0; i < nwords; i++)
13792 + buf[i] = R_REG(&sprom[wordoff + i]);
13793 +
13794 + if (check_crc) {
13795 + /* fixup the endianness so crc8 will pass */
13796 + htol16_buf(buf, nwords * 2);
13797 + if ((chk8 = hndcrc8((uchar*)buf, nwords * 2, CRC8_INIT_VALUE)) != CRC8_GOOD_VALUE)
13798 + return (1);
13799 + /* now correct the endianness of the byte array */
13800 + ltoh16_buf(buf, nwords * 2);
13801 + }
13802 +
13803 + return (0);
13804 +}
13805 +
13806 +/*
13807 + * Initialize nonvolatile variable table from sprom.
13808 + * Return 0 on success, nonzero on error.
13809 + */
13810 +
13811 +static int
13812 +initvars_srom_pci(void *osh, void *curmap, char **vars, int *count)
13813 +{
13814 + uint16 w, b[64];
13815 + uint8 sromrev;
13816 + struct ether_addr ea;
13817 + char eabuf[32];
13818 + uint32 bfl;
13819 + int c, woff, i;
13820 + char *vp, *base;
13821 +
13822 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE))
13823 + return (-1);
13824 +
13825 + /* top word of sprom contains version and crc8 */
13826 + sromrev = b[63] & 0xff;
13827 + /* bcm4401 sroms misprogrammed */
13828 + if (sromrev == 0x10)
13829 + sromrev = 1;
13830 + if ((sromrev != 1) && (sromrev != 2))
13831 + return (-2);
13832 +
13833 + ASSERT(vars);
13834 + ASSERT(count);
13835 +
13836 + base = vp = MALLOC(osh, VARS_MAX);
13837 + ASSERT(vp);
13838 +
13839 + vp += sprintf(vp, "sromrev=%d", sromrev);
13840 + vp++;
13841 +
13842 + if (sromrev >= 2) {
13843 + /* New section takes over the 4th hardware function space */
13844 +
13845 + /* Word 29 is max power 11a high/low */
13846 + w = b[29];
13847 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
13848 + vp++;
13849 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
13850 + vp++;
13851 +
13852 + /* Words 30-32 set the 11alow pa settings,
13853 + * 33-35 are the 11ahigh ones.
13854 + */
13855 + for (i = 0; i < 3; i++) {
13856 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
13857 + vp++;
13858 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
13859 + vp++;
13860 + }
13861 + w = b[59];
13862 + if (w == 0)
13863 + vp += sprintf(vp, "ccode=");
13864 + else
13865 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
13866 + vp++;
13867 +
13868 + }
13869 +
13870 + /* parameter section of sprom starts at byte offset 72 */
13871 + woff = 72/2;
13872 +
13873 + /* first 6 bytes are il0macaddr */
13874 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13875 + ea.octet[1] = b[woff] & 0xff;
13876 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13877 + ea.octet[3] = b[woff+1] & 0xff;
13878 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13879 + ea.octet[5] = b[woff+2] & 0xff;
13880 + woff += ETHER_ADDR_LEN/2 ;
13881 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13882 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
13883 + vp++;
13884 +
13885 + /* next 6 bytes are et0macaddr */
13886 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13887 + ea.octet[1] = b[woff] & 0xff;
13888 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13889 + ea.octet[3] = b[woff+1] & 0xff;
13890 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13891 + ea.octet[5] = b[woff+2] & 0xff;
13892 + woff += ETHER_ADDR_LEN/2 ;
13893 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13894 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
13895 + vp++;
13896 +
13897 + /* next 6 bytes are et1macaddr */
13898 + ea.octet[0] = (b[woff] >> 8) & 0xff;
13899 + ea.octet[1] = b[woff] & 0xff;
13900 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
13901 + ea.octet[3] = b[woff+1] & 0xff;
13902 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
13903 + ea.octet[5] = b[woff+2] & 0xff;
13904 + woff += ETHER_ADDR_LEN/2 ;
13905 + bcm_ether_ntoa((uchar*)&ea, eabuf);
13906 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
13907 + vp++;
13908 +
13909 + /*
13910 + * Enet phy settings one or two singles or a dual
13911 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
13912 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
13913 + * Bit 14 : Mdio for enet0
13914 + * Bit 15 : Mdio for enet1
13915 + */
13916 + w = b[woff];
13917 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
13918 + vp++;
13919 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
13920 + vp++;
13921 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
13922 + vp++;
13923 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
13924 + vp++;
13925 +
13926 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
13927 + w = b[46];
13928 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
13929 + vp++;
13930 +
13931 + if (sromrev > 1)
13932 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
13933 + else
13934 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
13935 + vp++;
13936 +
13937 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
13938 + vp++;
13939 +
13940 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
13941 + vp++;
13942 +
13943 + /* Words 47-49 set the (wl) pa settings */
13944 + woff = 47;
13945 +
13946 + for (i = 0; i < 3; i++) {
13947 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
13948 + vp++;
13949 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
13950 + vp++;
13951 + }
13952 +
13953 + /*
13954 + * Words 50-51 set the customer-configured wl led behavior.
13955 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
13956 + * LED behavior values defined in wlioctl.h .
13957 + */
13958 + w = b[50];
13959 + if ((w != 0) && (w != 0xffff)) {
13960 + /* gpio0 */
13961 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
13962 + vp++;
13963 +
13964 + /* gpio1 */
13965 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
13966 + vp++;
13967 + }
13968 + w = b[51];
13969 + if ((w != 0) && (w != 0xffff)) {
13970 + /* gpio2 */
13971 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
13972 + vp++;
13973 +
13974 + /* gpio3 */
13975 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
13976 + vp++;
13977 + }
13978 +
13979 + /* Word 52 is max power 0/1 */
13980 + w = b[52];
13981 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
13982 + vp++;
13983 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
13984 + vp++;
13985 +
13986 + /* Word 56 is idle tssi target 0/1 */
13987 + w = b[56];
13988 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
13989 + vp++;
13990 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
13991 + vp++;
13992 +
13993 + /* Word 57 is boardflags, if not programmed make it zero */
13994 + bfl = (uint32)b[57];
13995 + if (bfl == 0xffff) bfl = 0;
13996 + if (sromrev > 1) {
13997 + /* Word 28 is boardflags2 */
13998 + bfl |= (uint32)b[28] << 16;
13999 + }
14000 + vp += sprintf(vp, "boardflags=%d", bfl);
14001 + vp++;
14002 +
14003 + /* Word 58 is antenna gain 0/1 */
14004 + w = b[58];
14005 + vp += sprintf(vp, "ag0=%d", w & 0xff);
14006 + vp++;
14007 +
14008 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
14009 + vp++;
14010 +
14011 + if (sromrev == 1) {
14012 + /* set the oem string */
14013 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
14014 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
14015 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
14016 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
14017 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
14018 + vp++;
14019 + } else {
14020 + /* Word 60 OFDM tx power offset from CCK level */
14021 + /* OFDM Power Offset - opo */
14022 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
14023 + vp++;
14024 + }
14025 +
14026 + /* final nullbyte terminator */
14027 + *vp++ = '\0';
14028 +
14029 + c = (int)(vp - base);
14030 + ASSERT((vp - base) <= VARS_MAX);
14031 +
14032 + if (c == VARS_MAX) {
14033 + *vars = base;
14034 + } else {
14035 + vp = MALLOC(osh, c);
14036 + ASSERT(vp);
14037 + bcopy(base, vp, c);
14038 + MFREE(osh, base, VARS_MAX);
14039 + *vars = vp;
14040 + }
14041 + *count = c;
14042 +
14043 + return (0);
14044 +}
14045 +
14046 +/*
14047 + * Read the cis and call parsecis to initialize the vars.
14048 + * Return 0 on success, nonzero on error.
14049 + */
14050 +static int
14051 +initvars_cis_pcmcia(void *sbh, void *curmap, void *osh, char **vars, int *count)
14052 +{
14053 + uint8 *cis = NULL;
14054 + int rc;
14055 + uint data_sz;
14056 +
14057 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
14058 +
14059 + if ((cis = MALLOC(osh, data_sz)) == NULL)
14060 + return (-2);
14061 +
14062 + if (sb_pcmciarev(sbh) == 1) {
14063 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
14064 + MFREE(osh, cis, data_sz);
14065 + return (-1);
14066 + }
14067 + /* fix up endianess for 16-bit data vs 8-bit parsing */
14068 + ltoh16_buf((uint16 *)cis, data_sz);
14069 + } else
14070 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
14071 +
14072 + rc = srom_parsecis(osh, cis, vars, count);
14073 +
14074 + MFREE(osh, cis, data_sz);
14075 +
14076 + return (rc);
14077 +}
14078 +
14079 diff -urN linux.old/drivers/net/hnd/bcmutils.c linux.dev/drivers/net/hnd/bcmutils.c
14080 --- linux.old/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
14081 +++ linux.dev/drivers/net/hnd/bcmutils.c 2005-08-26 13:44:34.374382096 +0200
14082 @@ -0,0 +1,862 @@
14083 +/*
14084 + * Misc useful OS-independent routines.
14085 + *
14086 + * Copyright 2004, Broadcom Corporation
14087 + * All Rights Reserved.
14088 + *
14089 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14090 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14091 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14092 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14093 + * $Id$
14094 + */
14095 +
14096 +#include <typedefs.h>
14097 +#include <osl.h>
14098 +#include <bcmnvram.h>
14099 +#include <bcmutils.h>
14100 +#include <bcmendian.h>
14101 +#include <bcmdevs.h>
14102 +
14103 +#ifdef BCMDRIVER
14104 +/* copy a pkt buffer chain into a buffer */
14105 +uint
14106 +pktcopy(void *drv, void *p, uint offset, int len, uchar *buf)
14107 +{
14108 + uint n, ret = 0;
14109 +
14110 + if (len < 0)
14111 + len = 4096; /* "infinite" */
14112 +
14113 + /* skip 'offset' bytes */
14114 + for (; p && offset; p = PKTNEXT(drv, p)) {
14115 + if (offset < (uint)PKTLEN(drv, p))
14116 + break;
14117 + offset -= PKTLEN(drv, p);
14118 + }
14119 +
14120 + if (!p)
14121 + return 0;
14122 +
14123 + /* copy the data */
14124 + for (; p && len; p = PKTNEXT(drv, p)) {
14125 + n = MIN((uint)PKTLEN(drv, p) - offset, (uint)len);
14126 + bcopy(PKTDATA(drv, p) + offset, buf, n);
14127 + buf += n;
14128 + len -= n;
14129 + ret += n;
14130 + offset = 0;
14131 + }
14132 +
14133 + return ret;
14134 +}
14135 +
14136 +/* return total length of buffer chain */
14137 +uint
14138 +pkttotlen(void *drv, void *p)
14139 +{
14140 + uint total;
14141 +
14142 + total = 0;
14143 + for (; p; p = PKTNEXT(drv, p))
14144 + total += PKTLEN(drv, p);
14145 + return (total);
14146 +}
14147 +
14148 +void
14149 +pktq_init(struct pktq *q, uint maxlen, const bool prio_map[])
14150 +{
14151 + q->head = q->tail = NULL;
14152 + q->maxlen = maxlen;
14153 + q->len = 0;
14154 + if (prio_map) {
14155 + q->priority = TRUE;
14156 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
14157 + }
14158 + else
14159 + q->priority = FALSE;
14160 +}
14161 +
14162 +/* should always check pktq_full before calling pktenq */
14163 +void
14164 +pktenq(struct pktq *q, void *p, bool lifo)
14165 +{
14166 + void *next, *prev;
14167 +
14168 + /* allow 10 pkts slack */
14169 + ASSERT(q->len < (q->maxlen + 10));
14170 +
14171 + /* Queueing chains not allowed */
14172 + ASSERT(PKTLINK(p) == NULL);
14173 +
14174 + /* Queue is empty */
14175 + if (q->tail == NULL) {
14176 + ASSERT(q->head == NULL);
14177 + q->head = q->tail = p;
14178 + }
14179 +
14180 + /* Insert at head or tail */
14181 + else if (q->priority == FALSE) {
14182 + /* Insert at head (LIFO) */
14183 + if (lifo) {
14184 + PKTSETLINK(p, q->head);
14185 + q->head = p;
14186 + }
14187 + /* Insert at tail (FIFO) */
14188 + else {
14189 + ASSERT(PKTLINK(q->tail) == NULL);
14190 + PKTSETLINK(q->tail, p);
14191 + PKTSETLINK(p, NULL);
14192 + q->tail = p;
14193 + }
14194 + }
14195 +
14196 + /* Insert by priority */
14197 + else {
14198 + /* legal priorities 0-7 */
14199 + ASSERT(PKTPRIO(p) <= MAXPRIO);
14200 +
14201 + ASSERT(q->head);
14202 + ASSERT(q->tail);
14203 + /* Shortcut to insertion at tail */
14204 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
14205 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
14206 + prev = q->tail;
14207 + next = NULL;
14208 + }
14209 + /* Insert at head or in the middle */
14210 + else {
14211 + prev = NULL;
14212 + next = q->head;
14213 + }
14214 + /* Walk the queue */
14215 + for (; next; prev = next, next = PKTLINK(next)) {
14216 + /* Priority queue invariant */
14217 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
14218 + /* Insert at head of string of packets of same priority (LIFO) */
14219 + if (lifo) {
14220 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
14221 + break;
14222 + }
14223 + /* Insert at tail of string of packets of same priority (FIFO) */
14224 + else {
14225 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
14226 + break;
14227 + }
14228 + }
14229 + /* Insert at tail */
14230 + if (next == NULL) {
14231 + ASSERT(PKTLINK(q->tail) == NULL);
14232 + PKTSETLINK(q->tail, p);
14233 + PKTSETLINK(p, NULL);
14234 + q->tail = p;
14235 + }
14236 + /* Insert in the middle */
14237 + else if (prev) {
14238 + PKTSETLINK(prev, p);
14239 + PKTSETLINK(p, next);
14240 + }
14241 + /* Insert at head */
14242 + else {
14243 + PKTSETLINK(p, q->head);
14244 + q->head = p;
14245 + }
14246 + }
14247 +
14248 + /* List invariants after insertion */
14249 + ASSERT(q->head);
14250 + ASSERT(PKTLINK(q->tail) == NULL);
14251 +
14252 + q->len++;
14253 +}
14254 +
14255 +/* dequeue packet at head */
14256 +void*
14257 +pktdeq(struct pktq *q)
14258 +{
14259 + void *p;
14260 +
14261 + if ((p = q->head)) {
14262 + ASSERT(q->tail);
14263 + q->head = PKTLINK(p);
14264 + PKTSETLINK(p, NULL);
14265 + q->len--;
14266 + if (q->head == NULL)
14267 + q->tail = NULL;
14268 + }
14269 + else {
14270 + ASSERT(q->tail == NULL);
14271 + }
14272 +
14273 + return (p);
14274 +}
14275 +
14276 +/* dequeue packet at tail */
14277 +void*
14278 +pktdeqtail(struct pktq *q)
14279 +{
14280 + void *p;
14281 + void *next, *prev;
14282 +
14283 + if (q->head == q->tail) { /* last packet on queue or queue empty */
14284 + p = q->head;
14285 + q->head = q->tail = NULL;
14286 + q->len = 0;
14287 + return(p);
14288 + }
14289 +
14290 + /* start walk at head */
14291 + prev = NULL;
14292 + next = q->head;
14293 +
14294 + /* Walk the queue to find prev of q->tail */
14295 + for (; next; prev = next, next = PKTLINK(next)) {
14296 + if (next == q->tail)
14297 + break;
14298 + }
14299 +
14300 + ASSERT(prev);
14301 +
14302 + PKTSETLINK(prev, NULL);
14303 + q->tail = prev;
14304 + q->len--;
14305 + p = next;
14306 +
14307 + return (p);
14308 +}
14309 +
14310 +unsigned char bcm_ctype[] = {
14311 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
14312 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
14313 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
14314 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
14315 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
14316 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
14317 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
14318 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
14319 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
14320 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
14321 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
14322 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
14323 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
14324 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
14325 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
14326 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
14327 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
14328 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
14329 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
14330 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
14331 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
14332 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
14333 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
14334 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
14335 +};
14336 +
14337 +uchar
14338 +bcm_toupper(uchar c)
14339 +{
14340 + if (bcm_islower(c))
14341 + c -= 'a'-'A';
14342 + return (c);
14343 +}
14344 +
14345 +ulong
14346 +bcm_strtoul(char *cp, char **endp, uint base)
14347 +{
14348 + ulong result, value;
14349 + bool minus;
14350 +
14351 + minus = FALSE;
14352 +
14353 + while (bcm_isspace(*cp))
14354 + cp++;
14355 +
14356 + if (cp[0] == '+')
14357 + cp++;
14358 + else if (cp[0] == '-') {
14359 + minus = TRUE;
14360 + cp++;
14361 + }
14362 +
14363 + if (base == 0) {
14364 + if (cp[0] == '0') {
14365 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
14366 + base = 16;
14367 + cp = &cp[2];
14368 + } else {
14369 + base = 8;
14370 + cp = &cp[1];
14371 + }
14372 + } else
14373 + base = 10;
14374 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
14375 + cp = &cp[2];
14376 + }
14377 +
14378 + result = 0;
14379 +
14380 + while (bcm_isxdigit(*cp) &&
14381 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
14382 + result = result*base + value;
14383 + cp++;
14384 + }
14385 +
14386 + if (minus)
14387 + result = (ulong)(result * -1);
14388 +
14389 + if (endp)
14390 + *endp = (char *)cp;
14391 +
14392 + return (result);
14393 +}
14394 +
14395 +uint
14396 +bcm_atoi(char *s)
14397 +{
14398 + uint n;
14399 +
14400 + n = 0;
14401 +
14402 + while (bcm_isdigit(*s))
14403 + n = (n * 10) + *s++ - '0';
14404 + return (n);
14405 +}
14406 +
14407 +/* return pointer to location of substring 'needle' in 'haystack' */
14408 +char*
14409 +bcmstrstr(char *haystack, char *needle)
14410 +{
14411 + int len, nlen;
14412 + int i;
14413 +
14414 + if ((haystack == NULL) || (needle == NULL))
14415 + return (haystack);
14416 +
14417 + nlen = strlen(needle);
14418 + len = strlen(haystack) - nlen + 1;
14419 +
14420 + for (i = 0; i < len; i++)
14421 + if (bcmp(needle, &haystack[i], nlen) == 0)
14422 + return (&haystack[i]);
14423 + return (NULL);
14424 +}
14425 +
14426 +char*
14427 +bcmstrcat(char *dest, const char *src)
14428 +{
14429 + strcpy(&dest[strlen(dest)], src);
14430 + return (dest);
14431 +}
14432 +
14433 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
14434 +/* registry routine buffer preparation utility functions:
14435 + * parameter order is like strncpy, but returns count
14436 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
14437 + */
14438 +ulong
14439 +wchar2ascii(
14440 + char *abuf,
14441 + ushort *wbuf,
14442 + ushort wbuflen,
14443 + ulong abuflen
14444 +)
14445 +{
14446 + ulong copyct = 1;
14447 + ushort i;
14448 +
14449 + if (abuflen == 0)
14450 + return 0;
14451 +
14452 + /* wbuflen is in bytes */
14453 + wbuflen /= sizeof(ushort);
14454 +
14455 + for (i = 0; i < wbuflen; ++i) {
14456 + if (--abuflen == 0)
14457 + break;
14458 + *abuf++ = (char) *wbuf++;
14459 + ++copyct;
14460 + }
14461 + *abuf = '\0';
14462 +
14463 + return copyct;
14464 +}
14465 +#endif
14466 +
14467 +char*
14468 +bcm_ether_ntoa(char *ea, char *buf)
14469 +{
14470 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
14471 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
14472 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
14473 + return (buf);
14474 +}
14475 +
14476 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
14477 +int
14478 +bcm_ether_atoe(char *p, char *ea)
14479 +{
14480 + int i = 0;
14481 +
14482 + for (;;) {
14483 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
14484 + if (!*p++ || i == 6)
14485 + break;
14486 + }
14487 +
14488 + return (i == 6);
14489 +}
14490 +
14491 +void
14492 +bcm_mdelay(uint ms)
14493 +{
14494 + uint i;
14495 +
14496 + for (i = 0; i < ms; i++) {
14497 + OSL_DELAY(1000);
14498 + }
14499 +}
14500 +
14501 +/*
14502 + * Search the name=value vars for a specific one and return its value.
14503 + * Returns NULL if not found.
14504 + */
14505 +char*
14506 +getvar(char *vars, char *name)
14507 +{
14508 + char *s;
14509 + int len;
14510 +
14511 + len = strlen(name);
14512 +
14513 + /* first look in vars[] */
14514 + for (s = vars; s && *s; ) {
14515 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
14516 + return (&s[len+1]);
14517 +
14518 + while (*s++)
14519 + ;
14520 + }
14521 +
14522 + /* then query nvram */
14523 + return (BCMINIT(nvram_get)(name));
14524 +}
14525 +
14526 +/*
14527 + * Search the vars for a specific one and return its value as
14528 + * an integer. Returns 0 if not found.
14529 + */
14530 +int
14531 +getintvar(char *vars, char *name)
14532 +{
14533 + char *val;
14534 +
14535 + if ((val = getvar(vars, name)) == NULL)
14536 + return (0);
14537 +
14538 + return (bcm_strtoul(val, NULL, 0));
14539 +}
14540 +
14541 +/* Return gpio pin number assigned to the named pin */
14542 +/*
14543 +* Variable should be in format:
14544 +*
14545 +* gpio<N>=pin_name
14546 +*
14547 +* 'def_pin' is returned if there is no such variable found.
14548 +*/
14549 +uint
14550 +getgpiopin(char *vars, char *pin_name, uint def_pin)
14551 +{
14552 + char name[] = "gpioXXXX";
14553 + char *val;
14554 + uint pin;
14555 +
14556 + /* Go thru all possibilities till a match in pin name */
14557 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
14558 + sprintf(name, "gpio%d", pin);
14559 + val = getvar(vars, name);
14560 + if (val && !strcmp(val, pin_name))
14561 + return pin;
14562 + }
14563 + return def_pin;
14564 +}
14565 +
14566 +#endif /* #ifdef BCMDRIVER */
14567 +
14568 +/*******************************************************************************
14569 + * crc8
14570 + *
14571 + * Computes a crc8 over the input data using the polynomial:
14572 + *
14573 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
14574 + *
14575 + * The caller provides the initial value (either CRC8_INIT_VALUE
14576 + * or the previous returned value) to allow for processing of
14577 + * discontiguous blocks of data. When generating the CRC the
14578 + * caller is responsible for complementing the final return value
14579 + * and inserting it into the byte stream. When checking, a final
14580 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
14581 + *
14582 + * Reference: Dallas Semiconductor Application Note 27
14583 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
14584 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
14585 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
14586 + *
14587 + ******************************************************************************/
14588 +
14589 +static uint8 crc8_table[256] = {
14590 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
14591 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
14592 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
14593 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
14594 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
14595 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
14596 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
14597 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
14598 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
14599 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
14600 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
14601 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
14602 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
14603 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
14604 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
14605 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
14606 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
14607 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
14608 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
14609 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
14610 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
14611 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
14612 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
14613 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
14614 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
14615 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
14616 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
14617 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
14618 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
14619 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
14620 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
14621 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
14622 +};
14623 +
14624 +#define CRC_INNER_LOOP(n, c, x) \
14625 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
14626 +
14627 +uint8
14628 +hndcrc8(
14629 + uint8 *pdata, /* pointer to array of data to process */
14630 + uint nbytes, /* number of input data bytes to process */
14631 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
14632 +)
14633 +{
14634 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
14635 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
14636 + while (nbytes-- > 0)
14637 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
14638 +
14639 + return crc;
14640 +}
14641 +
14642 +/*******************************************************************************
14643 + * crc16
14644 + *
14645 + * Computes a crc16 over the input data using the polynomial:
14646 + *
14647 + * x^16 + x^12 +x^5 + 1
14648 + *
14649 + * The caller provides the initial value (either CRC16_INIT_VALUE
14650 + * or the previous returned value) to allow for processing of
14651 + * discontiguous blocks of data. When generating the CRC the
14652 + * caller is responsible for complementing the final return value
14653 + * and inserting it into the byte stream. When checking, a final
14654 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
14655 + *
14656 + * Reference: Dallas Semiconductor Application Note 27
14657 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
14658 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
14659 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
14660 + *
14661 + ******************************************************************************/
14662 +
14663 +static uint16 crc16_table[256] = {
14664 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
14665 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
14666 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
14667 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
14668 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
14669 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
14670 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
14671 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
14672 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
14673 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
14674 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
14675 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
14676 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
14677 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
14678 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
14679 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
14680 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
14681 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
14682 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
14683 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
14684 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
14685 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
14686 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
14687 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
14688 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
14689 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
14690 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
14691 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
14692 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
14693 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
14694 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
14695 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
14696 +};
14697 +
14698 +uint16
14699 +hndcrc16(
14700 + uint8 *pdata, /* pointer to array of data to process */
14701 + uint nbytes, /* number of input data bytes to process */
14702 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
14703 +)
14704 +{
14705 + while (nbytes-- > 0)
14706 + CRC_INNER_LOOP(16, crc, *pdata++);
14707 + return crc;
14708 +}
14709 +
14710 +static uint32 crc32_table[256] = {
14711 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
14712 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
14713 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
14714 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
14715 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
14716 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
14717 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
14718 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
14719 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
14720 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
14721 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
14722 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
14723 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
14724 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
14725 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
14726 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
14727 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
14728 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
14729 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
14730 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
14731 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
14732 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
14733 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
14734 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
14735 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
14736 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
14737 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
14738 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
14739 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
14740 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
14741 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
14742 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
14743 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
14744 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
14745 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
14746 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
14747 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
14748 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
14749 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
14750 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
14751 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
14752 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
14753 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
14754 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
14755 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
14756 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
14757 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
14758 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
14759 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
14760 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
14761 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
14762 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
14763 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
14764 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
14765 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
14766 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
14767 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
14768 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
14769 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
14770 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
14771 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
14772 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
14773 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
14774 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
14775 +};
14776 +
14777 +uint32
14778 +hndcrc32(
14779 + uint8 *pdata, /* pointer to array of data to process */
14780 + uint nbytes, /* number of input data bytes to process */
14781 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
14782 +)
14783 +{
14784 + uint8 *pend;
14785 +#ifdef __mips__
14786 + uint8 tmp[4];
14787 + ulong *tptr = (ulong *)tmp;
14788 +
14789 + /* in case the beginning of the buffer isn't aligned */
14790 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
14791 + nbytes -= (pend - pdata);
14792 + while (pdata < pend)
14793 + CRC_INNER_LOOP(32, crc, *pdata++);
14794 +
14795 + /* handle bulk of data as 32-bit words */
14796 + pend = pdata + (nbytes & 0xfffffffc);
14797 + while (pdata < pend) {
14798 + *tptr = *((ulong *)pdata)++;
14799 + CRC_INNER_LOOP(32, crc, tmp[0]);
14800 + CRC_INNER_LOOP(32, crc, tmp[1]);
14801 + CRC_INNER_LOOP(32, crc, tmp[2]);
14802 + CRC_INNER_LOOP(32, crc, tmp[3]);
14803 + }
14804 +
14805 + /* 1-3 bytes at end of buffer */
14806 + pend = pdata + (nbytes & 0x03);
14807 + while (pdata < pend)
14808 + CRC_INNER_LOOP(32, crc, *pdata++);
14809 +#else
14810 + pend = pdata + nbytes;
14811 + while (pdata < pend)
14812 + CRC_INNER_LOOP(32, crc, *pdata++);
14813 +#endif
14814 +
14815 + return crc;
14816 +}
14817 +
14818 +#ifdef notdef
14819 +#define CLEN 1499
14820 +#define CBUFSIZ (CLEN+4)
14821 +#define CNBUFS 5
14822 +
14823 +void testcrc32(void)
14824 +{
14825 + uint j,k,l;
14826 + uint8 *buf;
14827 + uint len[CNBUFS];
14828 + uint32 crcr;
14829 + uint32 crc32tv[CNBUFS] =
14830 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
14831 +
14832 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
14833 +
14834 + /* step through all possible alignments */
14835 + for (l=0;l<=4;l++) {
14836 + for (j=0; j<CNBUFS; j++) {
14837 + len[j] = CLEN;
14838 + for (k=0; k<len[j]; k++)
14839 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
14840 + }
14841 +
14842 + for (j=0; j<CNBUFS; j++) {
14843 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
14844 + ASSERT(crcr == crc32tv[j]);
14845 + }
14846 + }
14847 +
14848 + MFREE(buf, CBUFSIZ*CNBUFS);
14849 + return;
14850 +}
14851 +#endif
14852 +
14853 +
14854 +/*
14855 + * Advance from the current 1-byte tag/1-byte length/variable-length value
14856 + * triple, to the next, returning a pointer to the next.
14857 + */
14858 +bcm_tlv_t *
14859 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
14860 +{
14861 + int len;
14862 +
14863 + /* validate current elt */
14864 + if (*buflen < 2) {
14865 + return NULL;
14866 + }
14867 +
14868 + len = elt->len;
14869 +
14870 + /* validate remaining buflen */
14871 + if (*buflen >= (2 + len + 2)) {
14872 + elt = (bcm_tlv_t*)(elt->data + len);
14873 + *buflen -= (2 + len);
14874 + } else {
14875 + elt = NULL;
14876 + }
14877 +
14878 + return elt;
14879 +}
14880 +
14881 +/*
14882 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
14883 + * triples, returning a pointer to the substring whose first element
14884 + * matches tag
14885 + */
14886 +bcm_tlv_t *
14887 +bcm_parse_tlvs(void *buf, int buflen, uint key)
14888 +{
14889 + bcm_tlv_t *elt;
14890 + int totlen;
14891 +
14892 + elt = (bcm_tlv_t*)buf;
14893 + totlen = buflen;
14894 +
14895 + /* find tagged parameter */
14896 + while (totlen >= 2) {
14897 + int len = elt->len;
14898 +
14899 + /* validate remaining totlen */
14900 + if ((elt->id == key) && (totlen >= (len + 2)))
14901 + return (elt);
14902 +
14903 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
14904 + totlen -= (len + 2);
14905 + }
14906 +
14907 + return NULL;
14908 +}
14909 +
14910 +/*
14911 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
14912 + * triples, returning a pointer to the substring whose first element
14913 + * matches tag. Stop parsing when we see an element whose ID is greater
14914 + * than the target key.
14915 + */
14916 +bcm_tlv_t *
14917 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
14918 +{
14919 + bcm_tlv_t *elt;
14920 + int totlen;
14921 +
14922 + elt = (bcm_tlv_t*)buf;
14923 + totlen = buflen;
14924 +
14925 + /* find tagged parameter */
14926 + while (totlen >= 2) {
14927 + uint id = elt->id;
14928 + int len = elt->len;
14929 +
14930 + /* Punt if we start seeing IDs > than target key */
14931 + if (id > key)
14932 + return(NULL);
14933 +
14934 + /* validate remaining totlen */
14935 + if ((id == key) && (totlen >= (len + 2)))
14936 + return (elt);
14937 +
14938 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
14939 + totlen -= (len + 2);
14940 + }
14941 + return NULL;
14942 +}
14943 +
14944 +
14945 diff -urN linux.old/drivers/net/hnd/hnddma.c linux.dev/drivers/net/hnd/hnddma.c
14946 --- linux.old/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
14947 +++ linux.dev/drivers/net/hnd/hnddma.c 2005-08-26 13:44:34.375381944 +0200
14948 @@ -0,0 +1,865 @@
14949 +/*
14950 + * Generic Broadcom Home Networking Division (HND) DMA module.
14951 + * This supports the following chips: BCM42xx, 44xx, 47xx .
14952 + *
14953 + * Copyright 2004, Broadcom Corporation
14954 + * All Rights Reserved.
14955 + *
14956 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14957 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14958 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14959 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14960 + *
14961 + * $Id$
14962 + */
14963 +
14964 +#include <typedefs.h>
14965 +#include <osl.h>
14966 +#include <bcmendian.h>
14967 +#include <sbconfig.h>
14968 +#include <bcmutils.h>
14969 +
14970 +struct dma_info; /* forward declaration */
14971 +#define di_t struct dma_info
14972 +#include <hnddma.h>
14973 +
14974 +/* debug/trace */
14975 +#define DMA_ERROR(args)
14976 +#define DMA_TRACE(args)
14977 +
14978 +/* default dma message level(if input msg_level pointer is null in dma_attach()) */
14979 +static uint dma_msg_level = 0;
14980 +
14981 +#define MAXNAMEL 8
14982 +#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
14983 +
14984 +/* dma engine software state */
14985 +typedef struct dma_info {
14986 + hnddma_t hnddma; /* exported structure */
14987 + uint *msg_level; /* message level pointer */
14988 +
14989 + char name[MAXNAMEL]; /* callers name for diag msgs */
14990 + void *drv; /* driver handle */
14991 + void *osh; /* os handle */
14992 + dmaregs_t *regs; /* dma engine registers */
14993 +
14994 + dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
14995 + uint txin; /* index of next descriptor to reclaim */
14996 + uint txout; /* index of next descriptor to post */
14997 + uint txavail; /* # free tx descriptors */
14998 + void **txp; /* pointer to parallel array of pointers to packets */
14999 + ulong txdpa; /* physical address of descriptor ring */
15000 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
15001 + uint txdalloc; /* #bytes allocated for the ring */
15002 +
15003 + dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
15004 + uint rxin; /* index of next descriptor to reclaim */
15005 + uint rxout; /* index of next descriptor to post */
15006 + void **rxp; /* pointer to parallel array of pointers to packets */
15007 + ulong rxdpa; /* physical address of descriptor ring */
15008 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
15009 + uint rxdalloc; /* #bytes allocated for the ring */
15010 +
15011 + /* tunables */
15012 + uint ntxd; /* # tx descriptors */
15013 + uint nrxd; /* # rx descriptors */
15014 + uint rxbufsize; /* rx buffer size in bytes */
15015 + uint nrxpost; /* # rx buffers to keep posted */
15016 + uint rxoffset; /* rxcontrol offset */
15017 + uint ddoffset; /* add to get dma address of descriptor ring */
15018 + uint dataoffset; /* add to get dma address of data buffer */
15019 +} dma_info_t;
15020 +
15021 +/* descriptor bumping macros */
15022 +#define XXD(x, n) ((x) & ((n) - 1))
15023 +#define TXD(x) XXD((x), di->ntxd)
15024 +#define RXD(x) XXD((x), di->nrxd)
15025 +#define NEXTTXD(i) TXD(i + 1)
15026 +#define PREVTXD(i) TXD(i - 1)
15027 +#define NEXTRXD(i) RXD(i + 1)
15028 +#define NTXDACTIVE(h, t) TXD(t - h)
15029 +#define NRXDACTIVE(h, t) RXD(t - h)
15030 +
15031 +/* macros to convert between byte offsets and indexes */
15032 +#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
15033 +#define I2B(index) ((index) * sizeof (dmadd_t))
15034 +
15035 +/*
15036 + * This assume the largest i/o address is, in fact, the pci big window
15037 + * and that the pci core sb2pcitranslation2 register has been left with
15038 + * the default 0x0 pci base address.
15039 + */
15040 +#define MAXDMAADDR SB_PCI_DMA_SZ
15041 +#define DMA_ADDRESSABLE(x) !((x) & ~(MAXDMAADDR - 1))
15042 +
15043 +/* prototypes */
15044 +
15045 +void*
15046 +dma_attach(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
15047 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
15048 +{
15049 + dma_info_t *di;
15050 + uint size;
15051 + void *va;
15052 +
15053 + ASSERT(ntxd <= MAXDD);
15054 + ASSERT(ISPOWEROF2(ntxd));
15055 + ASSERT(nrxd <= MAXDD);
15056 + ASSERT(ISPOWEROF2(nrxd));
15057 +
15058 + /* allocate private info structure */
15059 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
15060 + return (NULL);
15061 + }
15062 + bzero((char*)di, sizeof (dma_info_t));
15063 +
15064 + /* allocate tx packet pointer vector */
15065 + if (ntxd) {
15066 + size = ntxd * sizeof (void*);
15067 + if ((di->txp = MALLOC(osh, size)) == NULL)
15068 + goto fail;
15069 + bzero((char*)di->txp, size);
15070 + }
15071 +
15072 + /* allocate rx packet pointer vector */
15073 + if (nrxd) {
15074 + size = nrxd * sizeof (void*);
15075 + if ((di->rxp = MALLOC(osh, size)) == NULL)
15076 + goto fail;
15077 + bzero((char*)di->rxp, size);
15078 + }
15079 +
15080 + /* set message level */
15081 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
15082 +
15083 + DMA_TRACE(("%s: dma_attach: drv %p osh %p regs %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, drv, osh, regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
15084 +
15085 + /* make a private copy of our callers name */
15086 + strncpy(di->name, name, MAXNAMEL);
15087 + di->name[MAXNAMEL-1] = '\0';
15088 +
15089 + di->drv = drv;
15090 + di->osh = osh;
15091 + di->regs = regs;
15092 +
15093 + /* allocate transmit descriptor ring */
15094 + if (ntxd) {
15095 + /* only need ntxd descriptors but it must be DMARINGALIGNed */
15096 + size = ntxd * sizeof (dmadd_t);
15097 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, DMARINGALIGN))
15098 + size += DMARINGALIGN;
15099 + if ((va = DMA_ALLOC_CONSISTENT(osh, size, &di->txdpa)) == NULL)
15100 + goto fail;
15101 + di->txd = (dmadd_t*) ROUNDUP((uintptr)va, DMARINGALIGN);
15102 + di->txdalign = (uint)((int8*)di->txd - (int8*)va);
15103 + di->txdpa += di->txdalign;
15104 + di->txdalloc = size;
15105 + ASSERT(ISALIGNED((uintptr)di->txd, DMARINGALIGN));
15106 + ASSERT(DMA_ADDRESSABLE(di->txdpa));
15107 + }
15108 +
15109 + /* allocate receive descriptor ring */
15110 + if (nrxd) {
15111 + /* only need nrxd descriptors but it must be DMARINGALIGNed */
15112 + size = nrxd * sizeof (dmadd_t);
15113 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, DMARINGALIGN))
15114 + size += DMARINGALIGN;
15115 + if ((va = DMA_ALLOC_CONSISTENT(osh, size, &di->rxdpa)) == NULL)
15116 + goto fail;
15117 + di->rxd = (dmadd_t*) ROUNDUP((uintptr)va, DMARINGALIGN);
15118 + di->rxdalign = (uint)((int8*)di->rxd - (int8*)va);
15119 + di->rxdpa += di->rxdalign;
15120 + di->rxdalloc = size;
15121 + ASSERT(ISALIGNED((uintptr)di->rxd, DMARINGALIGN));
15122 + ASSERT(DMA_ADDRESSABLE(di->rxdpa));
15123 + }
15124 +
15125 + /* save tunables */
15126 + di->ntxd = ntxd;
15127 + di->nrxd = nrxd;
15128 + di->rxbufsize = rxbufsize;
15129 + di->nrxpost = nrxpost;
15130 + di->rxoffset = rxoffset;
15131 + di->ddoffset = ddoffset;
15132 + di->dataoffset = dataoffset;
15133 +
15134 + return ((void*)di);
15135 +
15136 +fail:
15137 + dma_detach((void*)di);
15138 + return (NULL);
15139 +}
15140 +
15141 +/* may be called with core in reset */
15142 +void
15143 +dma_detach(dma_info_t *di)
15144 +{
15145 + if (di == NULL)
15146 + return;
15147 +
15148 + DMA_TRACE(("%s: dma_detach\n", di->name));
15149 +
15150 + /* shouldn't be here if descriptors are unreclaimed */
15151 + ASSERT(di->txin == di->txout);
15152 + ASSERT(di->rxin == di->rxout);
15153 +
15154 + /* free dma descriptor rings */
15155 + if (di->txd)
15156 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd - di->txdalign),
15157 + di->txdalloc, (di->txdpa - di->txdalign));
15158 + if (di->rxd)
15159 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd - di->rxdalign),
15160 + di->rxdalloc, (di->rxdpa - di->rxdalign));
15161 +
15162 + /* free packet pointer vectors */
15163 + if (di->txp)
15164 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
15165 + if (di->rxp)
15166 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
15167 +
15168 + /* free our private info structure */
15169 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
15170 +}
15171 +
15172 +
15173 +void
15174 +dma_txreset(dma_info_t *di)
15175 +{
15176 + uint32 status;
15177 +
15178 + DMA_TRACE(("%s: dma_txreset\n", di->name));
15179 +
15180 + /* suspend tx DMA first */
15181 + W_REG(&di->regs->xmtcontrol, XC_SE);
15182 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
15183 + status != XS_XS_IDLE &&
15184 + status != XS_XS_STOPPED,
15185 + 10000);
15186 +
15187 + W_REG(&di->regs->xmtcontrol, 0);
15188 + SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
15189 + 10000);
15190 +
15191 + if (status != XS_XS_DISABLED) {
15192 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
15193 + }
15194 +
15195 + /* wait for the last transaction to complete */
15196 + OSL_DELAY(300);
15197 +}
15198 +
15199 +void
15200 +dma_rxreset(dma_info_t *di)
15201 +{
15202 + uint32 status;
15203 +
15204 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
15205 +
15206 + W_REG(&di->regs->rcvcontrol, 0);
15207 + SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
15208 + 10000);
15209 +
15210 + if (status != RS_RS_DISABLED) {
15211 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
15212 + }
15213 +}
15214 +
15215 +void
15216 +dma_txinit(dma_info_t *di)
15217 +{
15218 + DMA_TRACE(("%s: dma_txinit\n", di->name));
15219 +
15220 + di->txin = di->txout = 0;
15221 + di->txavail = di->ntxd - 1;
15222 +
15223 + /* clear tx descriptor ring */
15224 + BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
15225 +
15226 + W_REG(&di->regs->xmtcontrol, XC_XE);
15227 + W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
15228 +}
15229 +
15230 +bool
15231 +dma_txenabled(dma_info_t *di)
15232 +{
15233 + uint32 xc;
15234 +
15235 + /* If the chip is dead, it is not enabled :-) */
15236 + xc = R_REG(&di->regs->xmtcontrol);
15237 + return ((xc != 0xffffffff) && (xc & XC_XE));
15238 +}
15239 +
15240 +void
15241 +dma_txsuspend(dma_info_t *di)
15242 +{
15243 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
15244 + OR_REG(&di->regs->xmtcontrol, XC_SE);
15245 +}
15246 +
15247 +void
15248 +dma_txresume(dma_info_t *di)
15249 +{
15250 + DMA_TRACE(("%s: dma_txresume\n", di->name));
15251 + AND_REG(&di->regs->xmtcontrol, ~XC_SE);
15252 +}
15253 +
15254 +bool
15255 +dma_txsuspended(dma_info_t *di)
15256 +{
15257 + if (!(R_REG(&di->regs->xmtcontrol) & XC_SE))
15258 + return 0;
15259 +
15260 + if ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) != XS_XS_IDLE)
15261 + return 0;
15262 +
15263 + OSL_DELAY(2);
15264 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_IDLE);
15265 +}
15266 +
15267 +bool
15268 +dma_txstopped(dma_info_t *di)
15269 +{
15270 + return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
15271 +}
15272 +
15273 +bool
15274 +dma_rxstopped(dma_info_t *di)
15275 +{
15276 + return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
15277 +}
15278 +
15279 +void
15280 +dma_fifoloopbackenable(dma_info_t *di)
15281 +{
15282 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
15283 + OR_REG(&di->regs->xmtcontrol, XC_LE);
15284 +}
15285 +
15286 +void
15287 +dma_rxinit(dma_info_t *di)
15288 +{
15289 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
15290 +
15291 + di->rxin = di->rxout = 0;
15292 +
15293 + /* clear rx descriptor ring */
15294 + BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
15295 +
15296 + dma_rxenable(di);
15297 + W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
15298 +}
15299 +
15300 +void
15301 +dma_rxenable(dma_info_t *di)
15302 +{
15303 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
15304 + W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
15305 +}
15306 +
15307 +bool
15308 +dma_rxenabled(dma_info_t *di)
15309 +{
15310 + uint32 rc;
15311 +
15312 + rc = R_REG(&di->regs->rcvcontrol);
15313 + return ((rc != 0xffffffff) && (rc & RC_RE));
15314 +}
15315 +
15316 +/*
15317 + * The BCM47XX family supports full 32bit dma engine buffer addressing so
15318 + * dma buffers can cross 4 Kbyte page boundaries.
15319 + */
15320 +int
15321 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
15322 +{
15323 + void *p, *next;
15324 + uchar *data;
15325 + uint len;
15326 + uint txout;
15327 + uint32 ctrl;
15328 + uint32 pa;
15329 +
15330 + DMA_TRACE(("%s: dma_txfast\n", di->name));
15331 +
15332 + txout = di->txout;
15333 + ctrl = 0;
15334 +
15335 + /*
15336 + * Walk the chain of packet buffers
15337 + * allocating and initializing transmit descriptor entries.
15338 + */
15339 + for (p = p0; p; p = next) {
15340 + data = PKTDATA(di->drv, p);
15341 + len = PKTLEN(di->drv, p);
15342 + next = PKTNEXT(di->drv, p);
15343 +
15344 + /* return nonzero if out of tx descriptors */
15345 + if (NEXTTXD(txout) == di->txin)
15346 + goto outoftxd;
15347 +
15348 + if (len == 0)
15349 + continue;
15350 +
15351 + /* get physical address of buffer start */
15352 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
15353 + ASSERT(DMA_ADDRESSABLE(pa));
15354 +
15355 + /* build the descriptor control value */
15356 + ctrl = len & CTRL_BC_MASK;
15357 +
15358 + ctrl |= coreflags;
15359 +
15360 + if (p == p0)
15361 + ctrl |= CTRL_SOF;
15362 + if (next == NULL)
15363 + ctrl |= (CTRL_IOC | CTRL_EOF);
15364 + if (txout == (di->ntxd - 1))
15365 + ctrl |= CTRL_EOT;
15366 +
15367 + /* init the tx descriptor */
15368 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
15369 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
15370 +
15371 + ASSERT(di->txp[txout] == NULL);
15372 +
15373 + txout = NEXTTXD(txout);
15374 + }
15375 +
15376 + /* if last txd eof not set, fix it */
15377 + if (!(ctrl & CTRL_EOF))
15378 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
15379 +
15380 + /* save the packet */
15381 + di->txp[PREVTXD(txout)] = p0;
15382 +
15383 + /* bump the tx descriptor index */
15384 + di->txout = txout;
15385 +
15386 + /* kick the chip */
15387 + W_REG(&di->regs->xmtptr, I2B(txout));
15388 +
15389 + /* tx flow control */
15390 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15391 +
15392 + return (0);
15393 +
15394 +outoftxd:
15395 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
15396 + PKTFREE(di->drv, p0, TRUE);
15397 + di->txavail = 0;
15398 + di->hnddma.txnobuf++;
15399 + return (-1);
15400 +}
15401 +
15402 +#define PAGESZ 4096
15403 +#define PAGEBASE(x) ((uintptr)(x) & ~4095)
15404 +
15405 +/*
15406 + * Just like above except go through the extra effort of splitting
15407 + * buffers that cross 4Kbyte boundaries into multiple tx descriptors.
15408 + */
15409 +int
15410 +dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
15411 +{
15412 + void *p, *next;
15413 + uchar *data;
15414 + uint plen, len;
15415 + uchar *page, *start, *end;
15416 + uint txout;
15417 + uint32 ctrl;
15418 + uint32 pa;
15419 +
15420 + DMA_TRACE(("%s: dma_tx\n", di->name));
15421 +
15422 + txout = di->txout;
15423 + ctrl = 0;
15424 +
15425 + /*
15426 + * Walk the chain of packet buffers
15427 + * splitting those that cross 4 Kbyte boundaries
15428 + * allocating and initializing transmit descriptor entries.
15429 + */
15430 + for (p = p0; p; p = next) {
15431 + data = PKTDATA(di->drv, p);
15432 + plen = PKTLEN(di->drv, p);
15433 + next = PKTNEXT(di->drv, p);
15434 +
15435 + if (plen == 0)
15436 + continue;
15437 +
15438 + for (page = (uchar*)PAGEBASE(data);
15439 + page <= (uchar*)PAGEBASE(data + plen - 1);
15440 + page += PAGESZ) {
15441 +
15442 + /* return nonzero if out of tx descriptors */
15443 + if (NEXTTXD(txout) == di->txin)
15444 + goto outoftxd;
15445 +
15446 + start = (page == (uchar*)PAGEBASE(data))? data: page;
15447 + end = (page == (uchar*)PAGEBASE(data + plen))?
15448 + (data + plen): (page + PAGESZ);
15449 + len = (uint)(end - start);
15450 +
15451 + /* build the descriptor control value */
15452 + ctrl = len & CTRL_BC_MASK;
15453 +
15454 + ctrl |= coreflags;
15455 +
15456 + if ((p == p0) && (start == data))
15457 + ctrl |= CTRL_SOF;
15458 + if ((next == NULL) && (end == (data + plen)))
15459 + ctrl |= (CTRL_IOC | CTRL_EOF);
15460 + if (txout == (di->ntxd - 1))
15461 + ctrl |= CTRL_EOT;
15462 +
15463 + /* get physical address of buffer start */
15464 + pa = (uint32) DMA_MAP(di->osh, start, len, DMA_TX, p);
15465 + ASSERT(DMA_ADDRESSABLE(pa));
15466 +
15467 + /* init the tx descriptor */
15468 + W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
15469 + W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
15470 +
15471 + ASSERT(di->txp[txout] == NULL);
15472 +
15473 + txout = NEXTTXD(txout);
15474 + }
15475 + }
15476 +
15477 + /* if last txd eof not set, fix it */
15478 + if (!(ctrl & CTRL_EOF))
15479 + W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
15480 +
15481 + /* save the packet */
15482 + di->txp[PREVTXD(txout)] = p0;
15483 +
15484 + /* bump the tx descriptor index */
15485 + di->txout = txout;
15486 +
15487 + /* kick the chip */
15488 + W_REG(&di->regs->xmtptr, I2B(txout));
15489 +
15490 + /* tx flow control */
15491 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15492 +
15493 + return (0);
15494 +
15495 +outoftxd:
15496 + DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
15497 + PKTFREE(di->drv, p0, TRUE);
15498 + di->txavail = 0;
15499 + di->hnddma.txnobuf++;
15500 + return (-1);
15501 +}
15502 +
15503 +/* returns a pointer to the next frame received, or NULL if there are no more */
15504 +void*
15505 +dma_rx(dma_info_t *di)
15506 +{
15507 + void *p;
15508 + uint len;
15509 + int skiplen = 0;
15510 +
15511 + while ((p = dma_getnextrxp(di, FALSE))) {
15512 + /* skip giant packets which span multiple rx descriptors */
15513 + if (skiplen > 0) {
15514 + skiplen -= di->rxbufsize;
15515 + if (skiplen < 0)
15516 + skiplen = 0;
15517 + PKTFREE(di->drv, p, FALSE);
15518 + continue;
15519 + }
15520 +
15521 + len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
15522 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
15523 +
15524 + /* bad frame length check */
15525 + if (len > (di->rxbufsize - di->rxoffset)) {
15526 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
15527 + if (len > 0)
15528 + skiplen = len - (di->rxbufsize - di->rxoffset);
15529 + PKTFREE(di->drv, p, FALSE);
15530 + di->hnddma.rxgiants++;
15531 + continue;
15532 + }
15533 +
15534 + /* set actual length */
15535 + PKTSETLEN(di->drv, p, (di->rxoffset + len));
15536 +
15537 + break;
15538 + }
15539 +
15540 + return (p);
15541 +}
15542 +
15543 +/* post receive buffers */
15544 +void
15545 +dma_rxfill(dma_info_t *di)
15546 +{
15547 + void *p;
15548 + uint rxin, rxout;
15549 + uint ctrl;
15550 + uint n;
15551 + uint i;
15552 + uint32 pa;
15553 + uint rxbufsize;
15554 +
15555 + /*
15556 + * Determine how many receive buffers we're lacking
15557 + * from the full complement, allocate, initialize,
15558 + * and post them, then update the chip rx lastdscr.
15559 + */
15560 +
15561 + rxin = di->rxin;
15562 + rxout = di->rxout;
15563 + rxbufsize = di->rxbufsize;
15564 +
15565 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
15566 +
15567 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
15568 +
15569 + for (i = 0; i < n; i++) {
15570 + if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
15571 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
15572 + di->hnddma.rxnobuf++;
15573 + break;
15574 + }
15575 +
15576 + *(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
15577 +
15578 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
15579 + ASSERT(ISALIGNED(pa, 4));
15580 + ASSERT(DMA_ADDRESSABLE(pa));
15581 +
15582 + /* save the free packet pointer */
15583 + ASSERT(di->rxp[rxout] == NULL);
15584 + di->rxp[rxout] = p;
15585 +
15586 + /* prep the descriptor control value */
15587 + ctrl = rxbufsize;
15588 + if (rxout == (di->nrxd - 1))
15589 + ctrl |= CTRL_EOT;
15590 +
15591 + /* init the rx descriptor */
15592 + W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
15593 + W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
15594 +
15595 + rxout = NEXTRXD(rxout);
15596 + }
15597 +
15598 + di->rxout = rxout;
15599 +
15600 + /* update the chip lastdscr pointer */
15601 + W_REG(&di->regs->rcvptr, I2B(rxout));
15602 +}
15603 +
15604 +void
15605 +dma_txreclaim(dma_info_t *di, bool forceall)
15606 +{
15607 + void *p;
15608 +
15609 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
15610 +
15611 + while ((p = dma_getnexttxp(di, forceall)))
15612 + PKTFREE(di->drv, p, TRUE);
15613 +}
15614 +
15615 +/*
15616 + * Reclaim next completed txd (txds if using chained buffers) and
15617 + * return associated packet.
15618 + * If 'force' is true, reclaim txd(s) and return associated packet
15619 + * regardless of the value of the hardware "curr" pointer.
15620 + */
15621 +void*
15622 +dma_getnexttxp(dma_info_t *di, bool forceall)
15623 +{
15624 + uint start, end, i;
15625 + void *txp;
15626 +
15627 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
15628 +
15629 + txp = NULL;
15630 +
15631 + start = di->txin;
15632 + if (forceall)
15633 + end = di->txout;
15634 + else
15635 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
15636 +
15637 + if ((start == 0) && (end > di->txout))
15638 + goto bogus;
15639 +
15640 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
15641 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
15642 + (BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
15643 + W_SM(&di->txd[i].addr, 0xdeadbeef);
15644 + txp = di->txp[i];
15645 + di->txp[i] = NULL;
15646 + }
15647 +
15648 + di->txin = i;
15649 +
15650 + /* tx flow control */
15651 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15652 +
15653 + return (txp);
15654 +
15655 +bogus:
15656 +/*
15657 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
15658 + start, end, di->txout, forceall));
15659 +*/
15660 + return (NULL);
15661 +}
15662 +
15663 +/* like getnexttxp but no reclaim */
15664 +void*
15665 +dma_peeknexttxp(dma_info_t *di)
15666 +{
15667 + uint end, i;
15668 +
15669 + end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
15670 +
15671 + for (i = di->txin; i != end; i = NEXTTXD(i))
15672 + if (di->txp[i])
15673 + return (di->txp[i]);
15674 +
15675 + return (NULL);
15676 +}
15677 +
15678 +void
15679 +dma_rxreclaim(dma_info_t *di)
15680 +{
15681 + void *p;
15682 +
15683 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
15684 +
15685 + while ((p = dma_getnextrxp(di, TRUE)))
15686 + PKTFREE(di->drv, p, FALSE);
15687 +}
15688 +
15689 +void *
15690 +dma_getnextrxp(dma_info_t *di, bool forceall)
15691 +{
15692 + uint i;
15693 + void *rxp;
15694 +
15695 + /* if forcing, dma engine must be disabled */
15696 + ASSERT(!forceall || !dma_rxenabled(di));
15697 +
15698 + i = di->rxin;
15699 +
15700 + /* return if no packets posted */
15701 + if (i == di->rxout)
15702 + return (NULL);
15703 +
15704 + /* ignore curr if forceall */
15705 + if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
15706 + return (NULL);
15707 +
15708 + /* get the packet pointer that corresponds to the rx descriptor */
15709 + rxp = di->rxp[i];
15710 + ASSERT(rxp);
15711 + di->rxp[i] = NULL;
15712 +
15713 + /* clear this packet from the descriptor ring */
15714 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
15715 + di->rxbufsize, DMA_RX, rxp);
15716 + W_SM(&di->rxd[i].addr, 0xdeadbeef);
15717 +
15718 + di->rxin = NEXTRXD(i);
15719 +
15720 + return (rxp);
15721 +}
15722 +
15723 +
15724 +uintptr
15725 +dma_getvar(dma_info_t *di, char *name)
15726 +{
15727 + if (!strcmp(name, "&txavail"))
15728 + return ((uintptr) &di->txavail);
15729 + else {
15730 + ASSERT(0);
15731 + }
15732 + return (0);
15733 +}
15734 +
15735 +void
15736 +dma_txblock(dma_info_t *di)
15737 +{
15738 + di->txavail = 0;
15739 +}
15740 +
15741 +void
15742 +dma_txunblock(dma_info_t *di)
15743 +{
15744 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15745 +}
15746 +
15747 +uint
15748 +dma_txactive(dma_info_t *di)
15749 +{
15750 + return (NTXDACTIVE(di->txin, di->txout));
15751 +}
15752 +
15753 +/*
15754 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
15755 + */
15756 +void
15757 +dma_txrotate(di_t *di)
15758 +{
15759 + uint ad;
15760 + uint nactive;
15761 + uint rot;
15762 + uint old, new;
15763 + uint32 w;
15764 + uint first, last;
15765 +
15766 + ASSERT(dma_txsuspended(di));
15767 +
15768 + nactive = dma_txactive(di);
15769 + ad = B2I((R_REG(&di->regs->xmtstatus) & XS_AD_MASK) >> XS_AD_SHIFT);
15770 + rot = TXD(ad - di->txin);
15771 +
15772 + ASSERT(rot < di->ntxd);
15773 +
15774 + /* full-ring case is a lot harder - don't worry about this */
15775 + if (rot >= (di->ntxd - nactive)) {
15776 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
15777 + return;
15778 + }
15779 +
15780 + first = di->txin;
15781 + last = PREVTXD(di->txout);
15782 +
15783 + /* move entries starting at last and moving backwards to first */
15784 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
15785 + new = TXD(old + rot);
15786 +
15787 + /*
15788 + * Move the tx dma descriptor.
15789 + * EOT is set only in the last entry in the ring.
15790 + */
15791 + w = R_SM(&di->txd[old].ctrl) & ~CTRL_EOT;
15792 + if (new == (di->ntxd - 1))
15793 + w |= CTRL_EOT;
15794 + W_SM(&di->txd[new].ctrl, w);
15795 + W_SM(&di->txd[new].addr, R_SM(&di->txd[old].addr));
15796 +
15797 + /* zap the old tx dma descriptor address field */
15798 + W_SM(&di->txd[old].addr, 0xdeadbeef);
15799 +
15800 + /* move the corresponding txp[] entry */
15801 + ASSERT(di->txp[new] == NULL);
15802 + di->txp[new] = di->txp[old];
15803 + di->txp[old] = NULL;
15804 + }
15805 +
15806 + /* update txin and txout */
15807 + di->txin = ad;
15808 + di->txout = TXD(di->txout + rot);
15809 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
15810 +
15811 + /* kick the chip */
15812 + W_REG(&di->regs->xmtptr, I2B(di->txout));
15813 +}
15814 diff -urN linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
15815 --- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
15816 +++ linux.dev/drivers/net/hnd/linux_osl.c 2005-08-26 13:44:34.376381792 +0200
15817 @@ -0,0 +1,640 @@
15818 +/*
15819 + * Linux OS Independent Layer
15820 + *
15821 + * Copyright 2004, Broadcom Corporation
15822 + * All Rights Reserved.
15823 + *
15824 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15825 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15826 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15827 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15828 + *
15829 + * $Id$
15830 + */
15831 +
15832 +#define LINUX_OSL
15833 +
15834 +#include <typedefs.h>
15835 +#include <bcmendian.h>
15836 +#include <linux/module.h>
15837 +#include <linuxver.h>
15838 +#include <linux_osl.h>
15839 +#include <bcmutils.h>
15840 +#include <linux/delay.h>
15841 +#ifdef mips
15842 +#include <asm/paccess.h>
15843 +#endif
15844 +#include <pcicfg.h>
15845 +
15846 +#define PCI_CFG_RETRY 10
15847 +
15848 +#define OS_HANDLE_MAGIC 0x1234abcd
15849 +#define BCM_MEM_FILENAME_LEN 24
15850 +
15851 +typedef struct bcm_mem_link {
15852 + struct bcm_mem_link *prev;
15853 + struct bcm_mem_link *next;
15854 + uint size;
15855 + int line;
15856 + char file[BCM_MEM_FILENAME_LEN];
15857 +} bcm_mem_link_t;
15858 +
15859 +typedef struct os_handle {
15860 + uint magic;
15861 + void *pdev;
15862 + uint malloced;
15863 + uint failed;
15864 + bcm_mem_link_t *dbgmem_list;
15865 +} os_handle_t;
15866 +
15867 +void *
15868 +osl_attach(void *pdev)
15869 +{
15870 + os_handle_t *osh;
15871 +
15872 + osh = kmalloc(sizeof(os_handle_t), GFP_ATOMIC);
15873 + ASSERT(osh);
15874 +
15875 + osh->magic = OS_HANDLE_MAGIC;
15876 + osh->malloced = 0;
15877 + osh->failed = 0;
15878 + osh->dbgmem_list = NULL;
15879 + osh->pdev = pdev;
15880 +
15881 + return osh;
15882 +}
15883 +
15884 +void
15885 +osl_detach(void *osh)
15886 +{
15887 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15888 + kfree(osh);
15889 +}
15890 +
15891 +void*
15892 +osl_pktget(void *drv, uint len, bool send)
15893 +{
15894 + struct sk_buff *skb;
15895 +
15896 + if ((skb = dev_alloc_skb(len)) == NULL)
15897 + return (NULL);
15898 +
15899 + skb_put(skb, len);
15900 +
15901 + /* ensure the cookie field is cleared */
15902 + PKTSETCOOKIE(skb, NULL);
15903 +
15904 + return ((void*) skb);
15905 +}
15906 +
15907 +void
15908 +osl_pktfree(void *p)
15909 +{
15910 + struct sk_buff *skb, *nskb;
15911 +
15912 + skb = (struct sk_buff*) p;
15913 +
15914 + /* perversion: we use skb->next to chain multi-skb packets */
15915 + while (skb) {
15916 + nskb = skb->next;
15917 + skb->next = NULL;
15918 + if (skb->destructor) {
15919 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
15920 + dev_kfree_skb_any(skb);
15921 + } else {
15922 + /* can free immediately (even in_irq()) if destructor does not exist */
15923 + dev_kfree_skb(skb);
15924 + }
15925 + skb = nskb;
15926 + }
15927 +}
15928 +
15929 +uint32
15930 +osl_pci_read_config(void *osh, uint offset, uint size)
15931 +{
15932 + struct pci_dev *pdev;
15933 + uint val;
15934 + uint retry=PCI_CFG_RETRY;
15935 +
15936 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15937 +
15938 + /* only 4byte access supported */
15939 + ASSERT(size == 4);
15940 +
15941 + pdev = ((os_handle_t *)osh)->pdev;
15942 + do {
15943 + pci_read_config_dword(pdev, offset, &val);
15944 + if (val != 0xffffffff)
15945 + break;
15946 + } while (retry--);
15947 +
15948 +
15949 + return (val);
15950 +}
15951 +
15952 +void
15953 +osl_pci_write_config(void *osh, uint offset, uint size, uint val)
15954 +{
15955 + struct pci_dev *pdev;
15956 + uint retry=PCI_CFG_RETRY;
15957 +
15958 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
15959 +
15960 + /* only 4byte access supported */
15961 + ASSERT(size == 4);
15962 +
15963 + pdev = ((os_handle_t *)osh)->pdev;
15964 +
15965 + do {
15966 + pci_write_config_dword(pdev, offset, val);
15967 + if (offset!=PCI_BAR0_WIN)
15968 + break;
15969 + if (osl_pci_read_config(osh,offset,size) == val)
15970 + break;
15971 + } while (retry--);
15972 +
15973 +}
15974 +
15975 +static void
15976 +osl_pcmcia_attr(void *osh, uint offset, char *buf, int size, bool write)
15977 +{
15978 +}
15979 +
15980 +void
15981 +osl_pcmcia_read_attr(void *osh, uint offset, void *buf, int size)
15982 +{
15983 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
15984 +}
15985 +
15986 +void
15987 +osl_pcmcia_write_attr(void *osh, uint offset, void *buf, int size)
15988 +{
15989 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
15990 +}
15991 +
15992 +
15993 +#ifdef BCMDBG_MEM
15994 +
15995 +void*
15996 +osl_debug_malloc(void *osh, uint size, int line, char* file)
15997 +{
15998 + bcm_mem_link_t *p;
15999 + char* basename;
16000 + os_handle_t *h = (os_handle_t *)osh;
16001 +
16002 + if (size == 0) {
16003 + return NULL;
16004 + }
16005 +
16006 + p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size);
16007 + if (p == NULL)
16008 + return p;
16009 +
16010 + p->size = size;
16011 + p->line = line;
16012 +
16013 + basename = strrchr(file, '/');
16014 + /* skip the '/' */
16015 + if (basename)
16016 + basename++;
16017 +
16018 + if (!basename)
16019 + basename = file;
16020 +
16021 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
16022 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
16023 +
16024 + /* link this block */
16025 + p->prev = NULL;
16026 + p->next = h->dbgmem_list;
16027 + if (p->next)
16028 + p->next->prev = p;
16029 + h->dbgmem_list = p;
16030 +
16031 + return p + 1;
16032 +}
16033 +
16034 +void
16035 +osl_debug_mfree(void *osh, void *addr, uint size, int line, char* file)
16036 +{
16037 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
16038 + os_handle_t *h = (os_handle_t *)osh;
16039 +
16040 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16041 +
16042 + if (p->size == 0) {
16043 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
16044 + (uint)addr, size, line, file);
16045 + return;
16046 + }
16047 +
16048 + if (p->size != size) {
16049 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
16050 + size, p->size, (uint)addr, line, file);
16051 + return;
16052 + }
16053 +
16054 + /* unlink this block */
16055 + if (p->prev)
16056 + p->prev->next = p->next;
16057 + if (p->next)
16058 + p->next->prev = p->prev;
16059 + if (h->dbgmem_list == p)
16060 + h->dbgmem_list = p->next;
16061 + p->next = p->prev = NULL;
16062 +
16063 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
16064 +}
16065 +
16066 +char*
16067 +osl_debug_memdump(void *osh, char *buf, uint sz)
16068 +{
16069 + bcm_mem_link_t *p;
16070 + char *obuf;
16071 + os_handle_t *h = (os_handle_t *)osh;
16072 +
16073 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16074 + obuf = buf;
16075 +
16076 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
16077 + for (p = h->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
16078 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
16079 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
16080 +
16081 + return (obuf);
16082 +}
16083 +
16084 +#endif /* BCMDBG_MEM */
16085 +
16086 +void*
16087 +osl_malloc(void *osh, uint size)
16088 +{
16089 + os_handle_t *h = (os_handle_t *)osh;
16090 + void *addr;
16091 +
16092 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16093 + h->malloced += size;
16094 + addr = kmalloc(size, GFP_ATOMIC);
16095 + if (!addr)
16096 + h->failed++;
16097 + return (addr);
16098 +}
16099 +
16100 +void
16101 +osl_mfree(void *osh, void *addr, uint size)
16102 +{
16103 + os_handle_t *h = (os_handle_t *)osh;
16104 +
16105 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16106 + h->malloced -= size;
16107 + kfree(addr);
16108 +}
16109 +
16110 +uint
16111 +osl_malloced(void *osh)
16112 +{
16113 + os_handle_t *h = (os_handle_t *)osh;
16114 +
16115 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16116 + return (h->malloced);
16117 +}
16118 +
16119 +uint osl_malloc_failed(void *osh)
16120 +{
16121 + os_handle_t *h = (os_handle_t *)osh;
16122 +
16123 + ASSERT((h && (h->magic == OS_HANDLE_MAGIC)));
16124 + return (h->failed);
16125 +}
16126 +
16127 +void*
16128 +osl_dma_alloc_consistent(void *osh, uint size, ulong *pap)
16129 +{
16130 + struct pci_dev *dev;
16131 +
16132 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
16133 +
16134 + dev = ((os_handle_t *)osh)->pdev;
16135 + return (pci_alloc_consistent(dev, size, (dma_addr_t*)pap));
16136 +}
16137 +
16138 +void
16139 +osl_dma_free_consistent(void *osh, void *va, uint size, ulong pa)
16140 +{
16141 + struct pci_dev *dev;
16142 +
16143 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
16144 +
16145 + dev = ((os_handle_t *)osh)->pdev;
16146 + pci_free_consistent(dev, size, va, (dma_addr_t)pa);
16147 +}
16148 +
16149 +uint
16150 +osl_dma_map(void *osh, void *va, uint size, int direction)
16151 +{
16152 + int dir;
16153 + struct pci_dev *dev;
16154 +
16155 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
16156 +
16157 + dev = ((os_handle_t *)osh)->pdev;
16158 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
16159 + return (pci_map_single(dev, va, size, dir));
16160 +}
16161 +
16162 +void
16163 +osl_dma_unmap(void *osh, uint pa, uint size, int direction)
16164 +{
16165 + int dir;
16166 + struct pci_dev *dev;
16167 +
16168 + ASSERT((osh && (((os_handle_t *)osh)->magic == OS_HANDLE_MAGIC)));
16169 +
16170 + dev = ((os_handle_t *)osh)->pdev;
16171 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
16172 + pci_unmap_single(dev, (uint32)pa, size, dir);
16173 +}
16174 +
16175 +#if defined(BINOSL)
16176 +void
16177 +osl_assert(char *exp, char *file, int line)
16178 +{
16179 + char tempbuf[255];
16180 +
16181 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
16182 + panic(tempbuf);
16183 +}
16184 +#endif /* BCMDBG || BINOSL */
16185 +
16186 +/*
16187 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
16188 + */
16189 +#ifdef BINOSL
16190 +
16191 +int
16192 +osl_printf(const char *format, ...)
16193 +{
16194 + va_list args;
16195 + char buf[1024];
16196 + int len;
16197 +
16198 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
16199 + va_start(args, format);
16200 + len = vsprintf(buf, format, args);
16201 + va_end(args);
16202 +
16203 + if (len > sizeof (buf)) {
16204 + printk("osl_printf: buffer overrun\n");
16205 + return (0);
16206 + }
16207 +
16208 + return (printk(buf));
16209 +}
16210 +
16211 +int
16212 +osl_sprintf(char *buf, const char *format, ...)
16213 +{
16214 + va_list args;
16215 + int rc;
16216 +
16217 + va_start(args, format);
16218 + rc = vsprintf(buf, format, args);
16219 + va_end(args);
16220 + return (rc);
16221 +}
16222 +
16223 +int
16224 +osl_strcmp(const char *s1, const char *s2)
16225 +{
16226 + return (strcmp(s1, s2));
16227 +}
16228 +
16229 +int
16230 +osl_strncmp(const char *s1, const char *s2, uint n)
16231 +{
16232 + return (strncmp(s1, s2, n));
16233 +}
16234 +
16235 +int
16236 +osl_strlen(char *s)
16237 +{
16238 + return (strlen(s));
16239 +}
16240 +
16241 +char*
16242 +osl_strcpy(char *d, const char *s)
16243 +{
16244 + return (strcpy(d, s));
16245 +}
16246 +
16247 +char*
16248 +osl_strncpy(char *d, const char *s, uint n)
16249 +{
16250 + return (strncpy(d, s, n));
16251 +}
16252 +
16253 +void
16254 +bcopy(const void *src, void *dst, int len)
16255 +{
16256 + memcpy(dst, src, len);
16257 +}
16258 +
16259 +int
16260 +bcmp(const void *b1, const void *b2, int len)
16261 +{
16262 + return (memcmp(b1, b2, len));
16263 +}
16264 +
16265 +void
16266 +bzero(void *b, int len)
16267 +{
16268 + memset(b, '\0', len);
16269 +}
16270 +
16271 +uint32
16272 +osl_readl(volatile uint32 *r)
16273 +{
16274 + return (readl(r));
16275 +}
16276 +
16277 +uint16
16278 +osl_readw(volatile uint16 *r)
16279 +{
16280 + return (readw(r));
16281 +}
16282 +
16283 +uint8
16284 +osl_readb(volatile uint8 *r)
16285 +{
16286 + return (readb(r));
16287 +}
16288 +
16289 +void
16290 +osl_writel(uint32 v, volatile uint32 *r)
16291 +{
16292 + writel(v, r);
16293 +}
16294 +
16295 +void
16296 +osl_writew(uint16 v, volatile uint16 *r)
16297 +{
16298 + writew(v, r);
16299 +}
16300 +
16301 +void
16302 +osl_writeb(uint8 v, volatile uint8 *r)
16303 +{
16304 + writeb(v, r);
16305 +}
16306 +
16307 +void *
16308 +osl_uncached(void *va)
16309 +{
16310 +#ifdef mips
16311 + return ((void*)KSEG1ADDR(va));
16312 +#else
16313 + return ((void*)va);
16314 +#endif
16315 +}
16316 +
16317 +uint
16318 +osl_getcycles(void)
16319 +{
16320 + uint cycles;
16321 +
16322 +#if defined(mips)
16323 + cycles = read_c0_count() * 2;
16324 +#elif defined(__i386__)
16325 + rdtscl(cycles);
16326 +#else
16327 + cycles = 0;
16328 +#endif
16329 + return cycles;
16330 +}
16331 +
16332 +void *
16333 +osl_reg_map(uint32 pa, uint size)
16334 +{
16335 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
16336 +}
16337 +
16338 +void
16339 +osl_reg_unmap(void *va)
16340 +{
16341 + iounmap(va);
16342 +}
16343 +
16344 +int
16345 +osl_busprobe(uint32 *val, uint32 addr)
16346 +{
16347 +#ifdef mips
16348 + return get_dbe(*val, (uint32*)addr);
16349 +#else
16350 + *val = readl(addr);
16351 + return 0;
16352 +#endif
16353 +}
16354 +
16355 +void
16356 +osl_delay(uint usec)
16357 +{
16358 + udelay(usec);
16359 +}
16360 +
16361 +uchar*
16362 +osl_pktdata(void *drv, void *skb)
16363 +{
16364 + return (((struct sk_buff*)skb)->data);
16365 +}
16366 +
16367 +uint
16368 +osl_pktlen(void *drv, void *skb)
16369 +{
16370 + return (((struct sk_buff*)skb)->len);
16371 +}
16372 +
16373 +uint
16374 +osl_pktheadroom(void *drv, void *skb)
16375 +{
16376 + return (uint) skb_headroom((struct sk_buff *) skb);
16377 +}
16378 +
16379 +uint
16380 +osl_pkttailroom(void *drv, void *skb)
16381 +{
16382 + return (uint) skb_tailroom((struct sk_buff *) skb);
16383 +}
16384 +
16385 +void*
16386 +osl_pktnext(void *drv, void *skb)
16387 +{
16388 + return (((struct sk_buff*)skb)->next);
16389 +}
16390 +
16391 +void
16392 +osl_pktsetnext(void *skb, void *x)
16393 +{
16394 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
16395 +}
16396 +
16397 +void
16398 +osl_pktsetlen(void *drv, void *skb, uint len)
16399 +{
16400 + __skb_trim((struct sk_buff*)skb, len);
16401 +}
16402 +
16403 +uchar*
16404 +osl_pktpush(void *drv, void *skb, int bytes)
16405 +{
16406 + return (skb_push((struct sk_buff*)skb, bytes));
16407 +}
16408 +
16409 +uchar*
16410 +osl_pktpull(void *drv, void *skb, int bytes)
16411 +{
16412 + return (skb_pull((struct sk_buff*)skb, bytes));
16413 +}
16414 +
16415 +void*
16416 +osl_pktdup(void *drv, void *skb)
16417 +{
16418 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
16419 +}
16420 +
16421 +void*
16422 +osl_pktcookie(void *skb)
16423 +{
16424 + return ((void*)((struct sk_buff*)skb)->csum);
16425 +}
16426 +
16427 +void
16428 +osl_pktsetcookie(void *skb, void *x)
16429 +{
16430 + ((struct sk_buff*)skb)->csum = (uint)x;
16431 +}
16432 +
16433 +void*
16434 +osl_pktlink(void *skb)
16435 +{
16436 + return (((struct sk_buff*)skb)->prev);
16437 +}
16438 +
16439 +void
16440 +osl_pktsetlink(void *skb, void *x)
16441 +{
16442 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
16443 +}
16444 +
16445 +uint
16446 +osl_pktprio(void *skb)
16447 +{
16448 + return (((struct sk_buff*)skb)->priority);
16449 +}
16450 +
16451 +void
16452 +osl_pktsetprio(void *skb, uint x)
16453 +{
16454 + ((struct sk_buff*)skb)->priority = x;
16455 +}
16456 +
16457 +#endif /* BINOSL */
16458 diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
16459 --- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
16460 +++ linux.dev/drivers/net/hnd/sbutils.c 2005-08-30 15:09:39.322854048 +0200
16461 @@ -0,0 +1,2063 @@
16462 +/*
16463 + * Misc utility routines for accessing chip-specific features
16464 + * of the SiliconBackplane-based Broadcom chips.
16465 + *
16466 + * Copyright 2005, Broadcom Corporation
16467 + * All Rights Reserved.
16468 + *
16469 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16470 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16471 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16472 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16473 + * $Id: sbutils.c,v 1.6 2005/03/07 08:35:32 kanki Exp $
16474 + */
16475 +
16476 +#include <typedefs.h>
16477 +#include <osl.h>
16478 +#include <bcmutils.h>
16479 +#include <bcmdevs.h>
16480 +#include <sbconfig.h>
16481 +#include <sbchipc.h>
16482 +#include <sbpci.h>
16483 +#include <pcicfg.h>
16484 +#include <sbpcmcia.h>
16485 +#include <sbextif.h>
16486 +#include <sbutils.h>
16487 +#include <bcmsrom.h>
16488 +
16489 +/* debug/trace */
16490 +#define SB_ERROR(args)
16491 +
16492 +
16493 +#define CLOCK_BASE_5350 12500000 /* Specific to 5350*/
16494 +
16495 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
16496 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
16497 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
16498 +
16499 +/* misc sb info needed by some of the routines */
16500 +typedef struct sb_info {
16501 + uint chip; /* chip number */
16502 + uint chiprev; /* chip revision */
16503 + uint chippkg; /* chip package option */
16504 + uint boardtype; /* board type */
16505 + uint boardvendor; /* board vendor id */
16506 + uint bustype; /* what bus type we are going through */
16507 +
16508 + void *osh; /* osl os handle */
16509 + void *sdh; /* bcmsdh handle */
16510 +
16511 + void *curmap; /* current regs va */
16512 + void *regs[SB_MAXCORES]; /* other regs va */
16513 +
16514 + uint curidx; /* current core index */
16515 + uint dev_coreid; /* the core provides driver functions */
16516 + uint pciidx; /* pci core index */
16517 + uint pcirev; /* pci core rev */
16518 +
16519 + uint pcmciaidx; /* pcmcia core index */
16520 + uint pcmciarev; /* pcmcia core rev */
16521 + bool memseg; /* flag to toggle MEM_SEG register */
16522 +
16523 + uint ccrev; /* chipc core rev */
16524 +
16525 + uint gpioidx; /* gpio control core index */
16526 + uint gpioid; /* gpio control coretype */
16527 +
16528 + uint numcores; /* # discovered cores */
16529 + uint coreid[SB_MAXCORES]; /* id of each core */
16530 +
16531 + void *intr_arg; /* interrupt callback function arg */
16532 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
16533 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
16534 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
16535 +} sb_info_t;
16536 +
16537 +/* local prototypes */
16538 +static void* BCMINIT(sb_doattach)(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
16539 +static void BCMINIT(sb_scan)(sb_info_t *si);
16540 +static uint sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val);
16541 +static uint _sb_coreidx(void *sbh);
16542 +static uint sb_findcoreidx(void *sbh, uint coreid, uint coreunit);
16543 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
16544 +static uint BCMINIT(sb_chip2numcores)(uint chip);
16545 +
16546 +#define SB_INFO(sbh) (sb_info_t*)sbh
16547 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
16548 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
16549 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
16550 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
16551 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
16552 +#define BADIDX (SB_MAXCORES+1)
16553 +#define NOREV (SBIDH_RC_MASK + 1)
16554 +
16555 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
16556 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
16557 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
16558 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
16559 +
16560 +/*
16561 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
16562 + * after core switching to avoid invalid register accesss inside ISR.
16563 + */
16564 +#define INTR_OFF(si, intr_val) \
16565 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
16566 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
16567 +#define INTR_RESTORE(si, intr_val) \
16568 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
16569 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
16570 +
16571 +/* power control defines */
16572 +#define LPOMINFREQ 25000 /* low power oscillator min */
16573 +#define LPOMAXFREQ 43000 /* low power oscillator max */
16574 +#define XTALMINFREQ 19800000 /* 20mhz - 1% */
16575 +#define XTALMAXFREQ 20200000 /* 20mhz + 1% */
16576 +#define PCIMINFREQ 25000000 /* 25mhz */
16577 +#define PCIMAXFREQ 34000000 /* 33mhz + fudge */
16578 +#define SCC_DEF_DIV 0 /* default slow clock divider */
16579 +
16580 +#define XTAL_ON_DELAY 1000 /* Xtal power on delay in us */
16581 +
16582 +#define SCC_LOW2FAST_LIMIT 5000 /* turn on fast clock time, in unit of ms */
16583 +
16584 +static uint32
16585 +sb_read_sbreg(void *sbh, volatile uint32 *sbr)
16586 +{
16587 + sb_info_t *si;
16588 + uint8 tmp;
16589 + uint32 val, intr_val = 0;
16590 +
16591 + si = SB_INFO(sbh);
16592 +
16593 + /*
16594 + * compact flash only has 11 bits address, while we needs 12 bits address.
16595 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
16596 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
16597 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
16598 + */
16599 + if(si->memseg) {
16600 + INTR_OFF(si, intr_val);
16601 + tmp = 1;
16602 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16603 + (uintptr)sbr &= ~(1 << 11); /* mask out bit 11*/
16604 + }
16605 +
16606 + val = R_REG(sbr);
16607 +
16608 + if(si->memseg) {
16609 + tmp = 0;
16610 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16611 + INTR_RESTORE(si, intr_val);
16612 + }
16613 +
16614 + return (val);
16615 +}
16616 +
16617 +static void
16618 +sb_write_sbreg(void *sbh, volatile uint32 *sbr, uint32 v)
16619 +{
16620 + sb_info_t *si;
16621 + uint8 tmp;
16622 + volatile uint32 dummy;
16623 + uint32 intr_val = 0;
16624 +
16625 + si = SB_INFO(sbh);
16626 +
16627 + /*
16628 + * compact flash only has 11 bits address, while we needs 12 bits address.
16629 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
16630 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
16631 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
16632 + */
16633 + if(si->memseg) {
16634 + INTR_OFF(si, intr_val);
16635 + tmp = 1;
16636 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16637 + (uintptr)sbr &= ~(1 << 11); /* mask out bit 11 */
16638 + }
16639 +
16640 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16641 +#ifdef IL_BIGENDIAN
16642 + dummy = R_REG(sbr);
16643 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
16644 + dummy = R_REG(sbr);
16645 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
16646 +#else
16647 + dummy = R_REG(sbr);
16648 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
16649 + dummy = R_REG(sbr);
16650 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
16651 +#endif
16652 + } else
16653 + W_REG(sbr, v);
16654 +
16655 + if(si->memseg) {
16656 + tmp = 0;
16657 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
16658 + INTR_RESTORE(si, intr_val);
16659 + }
16660 +}
16661 +
16662 +/*
16663 + * Allocate a sb handle.
16664 + * devid - pci device id (used to determine chip#)
16665 + * osh - opaque OS handle
16666 + * regs - virtual address of initial core registers
16667 + * bustype - pci/pcmcia/sb/sdio/etc
16668 + * vars - pointer to a pointer area for "environment" variables
16669 + * varsz - pointer to int to return the size of the vars
16670 + */
16671 +void*
16672 +BCMINITFN(sb_attach)(uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
16673 +{
16674 + sb_info_t *si;
16675 +
16676 + /* alloc sb_info_t */
16677 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
16678 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
16679 + return (NULL);
16680 + }
16681 +
16682 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
16683 + MFREE(osh, si, sizeof (sb_info_t));
16684 + return (NULL);
16685 + }
16686 + return si;
16687 +}
16688 +
16689 +/* Using sb_kattach depends on SB_BUS support, either implicit */
16690 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
16691 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
16692 +
16693 +/* global kernel resource */
16694 +static sb_info_t ksi;
16695 +
16696 +/* generic kernel variant of sb_attach() */
16697 +void*
16698 +BCMINITFN(sb_kattach)()
16699 +{
16700 + uint32 *regs;
16701 + char *unused;
16702 + int varsz;
16703 +
16704 + if (ksi.curmap == NULL) {
16705 + uint32 cid;
16706 +
16707 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
16708 + cid = R_REG((uint32 *)regs);
16709 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
16710 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
16711 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
16712 + uint32 *scc, val;
16713 +
16714 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
16715 + val = R_REG(scc);
16716 + SB_ERROR((" initial scc = 0x%x\n", val));
16717 + val |= SCC_SS_XTAL;
16718 + W_REG(scc, val);
16719 + }
16720 +
16721 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
16722 + SB_BUS, NULL, &unused, &varsz) == NULL) {
16723 + return NULL;
16724 + }
16725 + }
16726 +
16727 + return &ksi;
16728 +}
16729 +#endif
16730 +
16731 +static void*
16732 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz)
16733 +{
16734 + uint origidx;
16735 + chipcregs_t *cc;
16736 + uint32 w;
16737 + int res;
16738 +
16739 + ASSERT(GOODREGS(regs));
16740 +
16741 + bzero((uchar*)si, sizeof (sb_info_t));
16742 +
16743 + si->pciidx = si->gpioidx = BADIDX;
16744 +
16745 + si->osh = osh;
16746 + si->curmap = regs;
16747 + si->sdh = sdh;
16748 +
16749 + /* check to see if we are a sb core mimic'ing a pci core */
16750 + if (bustype == PCI_BUS) {
16751 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
16752 + bustype = SB_BUS;
16753 + else
16754 + bustype = PCI_BUS;
16755 + }
16756 +
16757 + si->bustype = bustype;
16758 + if (si->bustype != BUSTYPE(si->bustype)) {
16759 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
16760 + si->bustype, BUSTYPE(si->bustype)));
16761 + return NULL;
16762 + }
16763 +
16764 + /* need to set memseg flag for CF card first before any sb registers access */
16765 + if (BUSTYPE(si->bustype) == PCMCIA_BUS)
16766 + si->memseg = TRUE;
16767 +
16768 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
16769 + if (BUSTYPE(si->bustype) == PCI_BUS)
16770 + sb_pwrctl_xtal((void*)si, XTAL|PLL, ON);
16771 +
16772 + /* initialize current core index value */
16773 + si->curidx = _sb_coreidx((void*)si);
16774 + if (si->curidx == BADIDX) {
16775 + return NULL;
16776 + }
16777 +
16778 + /* keep and reuse the initial register mapping */
16779 + origidx = si->curidx;
16780 + if (BUSTYPE(si->bustype) == SB_BUS)
16781 + si->regs[origidx] = regs;
16782 +
16783 + /* is core-0 a chipcommon core? */
16784 + si->numcores = 1;
16785 + cc = (chipcregs_t*) sb_setcoreidx((void*)si, 0);
16786 + if (sb_coreid((void*)si) != SB_CC)
16787 + cc = NULL;
16788 +
16789 + /* determine chip id and rev */
16790 + if (cc) {
16791 + /* chip common core found! */
16792 + si->chip = R_REG(&cc->chipid) & CID_ID_MASK;
16793 + si->chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
16794 + si->chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
16795 + } else {
16796 + /* The only pcmcia chip without a chipcommon core is a 4301 */
16797 + if (BUSTYPE(si->bustype) == PCMCIA_BUS)
16798 + devid = BCM4301_DEVICE_ID;
16799 +
16800 + /* no chip common core -- must convert device id to chip id */
16801 + if ((si->chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
16802 + SB_ERROR(("sb_attach: unrecognized device id 0x%04x\n", devid));
16803 + return NULL;
16804 + }
16805 + }
16806 +
16807 + /* get chipcommon rev */
16808 + si->ccrev = cc ? sb_corerev((void*)si) : NOREV;
16809 +
16810 + /* determine numcores */
16811 + if (cc && ((si->ccrev == 4) || (si->ccrev >= 6)))
16812 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
16813 + else
16814 + si->numcores = BCMINIT(sb_chip2numcores)(si->chip);
16815 +
16816 + /* return to original core */
16817 + sb_setcoreidx((void*)si, origidx);
16818 +
16819 + /* sanity checks */
16820 + ASSERT(si->chip);
16821 +
16822 + /* scan for cores */
16823 + BCMINIT(sb_scan)(si);
16824 +
16825 + /* srom_var_init() depends on sb_scan() info */
16826 + if ((res = srom_var_init(si, si->bustype, si->curmap, osh, vars, varsz))) {
16827 + SB_ERROR(("sb_attach: srom_var_init failed: bad srom\n"));
16828 + return (NULL);
16829 + }
16830 +
16831 + if (cc == NULL) {
16832 + /*
16833 + * The chip revision number is hardwired into all
16834 + * of the pci function config rev fields and is
16835 + * independent from the individual core revision numbers.
16836 + * For example, the "A0" silicon of each chip is chip rev 0.
16837 + * For PCMCIA we get it from the CIS instead.
16838 + */
16839 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16840 + ASSERT(vars);
16841 + si->chiprev = getintvar(*vars, "chiprev");
16842 + } else if (BUSTYPE(si->bustype) == PCI_BUS) {
16843 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
16844 + si->chiprev = w & 0xff;
16845 + } else
16846 + si->chiprev = 0;
16847 + }
16848 +
16849 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
16850 + w = getintvar(*vars, "regwindowsz");
16851 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
16852 + }
16853 +
16854 + /* gpio control core is required */
16855 + if (!GOODIDX(si->gpioidx)) {
16856 + SB_ERROR(("sb_attach: gpio control core not found\n"));
16857 + return NULL;
16858 + }
16859 +
16860 + /* get boardtype and boardrev */
16861 + switch (BUSTYPE(si->bustype)) {
16862 + case PCI_BUS:
16863 + /* do a pci config read to get subsystem id and subvendor id */
16864 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
16865 + si->boardvendor = w & 0xffff;
16866 + si->boardtype = (w >> 16) & 0xffff;
16867 + break;
16868 +
16869 + case PCMCIA_BUS:
16870 + case SDIO_BUS:
16871 + si->boardvendor = getintvar(*vars, "manfid");
16872 + si->boardtype = getintvar(*vars, "prodid");
16873 + break;
16874 +
16875 + case SB_BUS:
16876 + si->boardvendor = VENDOR_BROADCOM;
16877 + si->boardtype = 0xffff;
16878 + break;
16879 + }
16880 +
16881 + if (si->boardtype == 0) {
16882 + SB_ERROR(("sb_attach: unknown board type\n"));
16883 + ASSERT(si->boardtype);
16884 + }
16885 +
16886 +
16887 + return ((void*)si);
16888 +}
16889 +
16890 +uint
16891 +sb_coreid(void *sbh)
16892 +{
16893 + sb_info_t *si;
16894 + sbconfig_t *sb;
16895 +
16896 + si = SB_INFO(sbh);
16897 + sb = REGS2SB(si->curmap);
16898 +
16899 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
16900 +}
16901 +
16902 +uint
16903 +sb_coreidx(void *sbh)
16904 +{
16905 + sb_info_t *si;
16906 +
16907 + si = SB_INFO(sbh);
16908 + return (si->curidx);
16909 +}
16910 +
16911 +/* return current index of core */
16912 +static uint
16913 +_sb_coreidx(void *sbh)
16914 +{
16915 + sb_info_t *si;
16916 + sbconfig_t *sb;
16917 + uint32 sbaddr = 0;
16918 +
16919 + si = SB_INFO(sbh);
16920 + ASSERT(si);
16921 +
16922 + switch (BUSTYPE(si->bustype)) {
16923 + case SB_BUS:
16924 + sb = REGS2SB(si->curmap);
16925 + sbaddr = sb_base(R_SBREG(sbh, &sb->sbadmatch0));
16926 + break;
16927 +
16928 + case PCI_BUS:
16929 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
16930 + break;
16931 +
16932 + case PCMCIA_BUS: {
16933 + uint8 tmp = 0;
16934 +
16935 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
16936 + sbaddr = (uint)tmp << 12;
16937 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
16938 + sbaddr |= (uint)tmp << 16;
16939 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
16940 + sbaddr |= (uint)tmp << 24;
16941 + break;
16942 + }
16943 + default:
16944 + ASSERT(0);
16945 + }
16946 +
16947 + if (!GOODCOREADDR(sbaddr))
16948 + return BADIDX;
16949 +
16950 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
16951 +}
16952 +
16953 +uint
16954 +sb_corevendor(void *sbh)
16955 +{
16956 + sb_info_t *si;
16957 + sbconfig_t *sb;
16958 +
16959 + si = SB_INFO(sbh);
16960 + sb = REGS2SB(si->curmap);
16961 +
16962 + return ((R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
16963 +}
16964 +
16965 +uint
16966 +sb_corerev(void *sbh)
16967 +{
16968 + sb_info_t *si;
16969 + sbconfig_t *sb;
16970 +
16971 + si = SB_INFO(sbh);
16972 + sb = REGS2SB(si->curmap);
16973 +
16974 + return (R_SBREG(sbh, &(sb)->sbidhigh) & SBIDH_RC_MASK);
16975 +}
16976 +
16977 +void *
16978 +sb_osh(void *sbh)
16979 +{
16980 + sb_info_t *si;
16981 +
16982 + si = SB_INFO(sbh);
16983 + return si->osh;
16984 +}
16985 +
16986 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
16987 +
16988 +/* set/clear sbtmstatelow core-specific flags */
16989 +uint32
16990 +sb_coreflags(void *sbh, uint32 mask, uint32 val)
16991 +{
16992 + sb_info_t *si;
16993 + sbconfig_t *sb;
16994 + uint32 w;
16995 +
16996 + si = SB_INFO(sbh);
16997 + sb = REGS2SB(si->curmap);
16998 +
16999 + ASSERT((val & ~mask) == 0);
17000 + ASSERT((mask & ~SBTML_ALLOW) == 0);
17001 +
17002 + /* mask and set */
17003 + if (mask || val) {
17004 + w = (R_SBREG(sbh, &sb->sbtmstatelow) & ~mask) | val;
17005 + W_SBREG(sbh, &sb->sbtmstatelow, w);
17006 + }
17007 +
17008 + /* return the new value */
17009 + return (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_ALLOW);
17010 +}
17011 +
17012 +/* set/clear sbtmstatehigh core-specific flags */
17013 +uint32
17014 +sb_coreflagshi(void *sbh, uint32 mask, uint32 val)
17015 +{
17016 + sb_info_t *si;
17017 + sbconfig_t *sb;
17018 + uint32 w;
17019 +
17020 + si = SB_INFO(sbh);
17021 + sb = REGS2SB(si->curmap);
17022 +
17023 + ASSERT((val & ~mask) == 0);
17024 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
17025 +
17026 + /* mask and set */
17027 + if (mask || val) {
17028 + w = (R_SBREG(sbh, &sb->sbtmstatehigh) & ~mask) | val;
17029 + W_SBREG(sbh, &sb->sbtmstatehigh, w);
17030 + }
17031 +
17032 + /* return the new value */
17033 + return (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
17034 +}
17035 +
17036 +bool
17037 +sb_iscoreup(void *sbh)
17038 +{
17039 + sb_info_t *si;
17040 + sbconfig_t *sb;
17041 +
17042 + si = SB_INFO(sbh);
17043 + sb = REGS2SB(si->curmap);
17044 +
17045 + return ((R_SBREG(sbh, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK);
17046 +}
17047 +
17048 +/*
17049 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
17050 + * switch back to the original core, and return the new value.
17051 + */
17052 +static uint
17053 +sb_corereg(void *sbh, uint coreidx, uint regoff, uint mask, uint val)
17054 +{
17055 + sb_info_t *si;
17056 + uint origidx;
17057 + uint32 *r;
17058 + uint w;
17059 + uint intr_val = 0;
17060 +
17061 + ASSERT(GOODIDX(coreidx));
17062 + ASSERT(regoff < SB_CORE_SIZE);
17063 + ASSERT((val & ~mask) == 0);
17064 +
17065 + si = SB_INFO(sbh);
17066 +
17067 + INTR_OFF(si, intr_val);
17068 +
17069 + /* save current core index */
17070 + origidx = sb_coreidx(sbh);
17071 +
17072 + /* switch core */
17073 + r = (uint32*) ((uchar*) sb_setcoreidx(sbh, coreidx) + regoff);
17074 +
17075 + /* mask and set */
17076 + if (mask || val) {
17077 + if (regoff >= SBCONFIGOFF) {
17078 + w = (R_SBREG(sbh, r) & ~mask) | val;
17079 + W_SBREG(sbh, r, w);
17080 + } else {
17081 + w = (R_REG(r) & ~mask) | val;
17082 + W_REG(r, w);
17083 + }
17084 + }
17085 +
17086 + /* readback */
17087 + if (regoff >= SBCONFIGOFF)
17088 + w = R_SBREG(sbh, r);
17089 + else
17090 + w = R_REG(r);
17091 +
17092 + /* restore core index */
17093 + if (origidx != coreidx)
17094 + sb_setcoreidx(sbh, origidx);
17095 +
17096 + INTR_RESTORE(si, intr_val);
17097 + return (w);
17098 +}
17099 +
17100 +/* scan the sb enumerated space to identify all cores */
17101 +static void
17102 +BCMINITFN(sb_scan)(sb_info_t *si)
17103 +{
17104 + void *sbh;
17105 + uint origidx;
17106 + uint i;
17107 +
17108 + sbh = (void*) si;
17109 +
17110 + /* numcores should already be set */
17111 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
17112 +
17113 + /* save current core index */
17114 + origidx = sb_coreidx(sbh);
17115 +
17116 + si->pciidx = si->pcmciaidx = si->gpioidx = BADIDX;
17117 + si->pcirev = si->pcmciarev = NOREV;
17118 +
17119 + for (i = 0; i < si->numcores; i++) {
17120 + sb_setcoreidx(sbh, i);
17121 + si->coreid[i] = sb_coreid(sbh);
17122 +
17123 + if (si->coreid[i] == SB_PCI) {
17124 + si->pciidx = i;
17125 + si->pcirev = sb_corerev(sbh);
17126 +
17127 + } else if (si->coreid[i] == SB_PCMCIA) {
17128 + si->pcmciaidx = i;
17129 + si->pcmciarev = sb_corerev(sbh);
17130 + }
17131 + }
17132 +
17133 + /*
17134 + * Find the gpio "controlling core" type and index.
17135 + * Precedence:
17136 + * - if there's a chip common core - use that
17137 + * - else if there's a pci core (rev >= 2) - use that
17138 + * - else there had better be an extif core (4710 only)
17139 + */
17140 + if (GOODIDX(sb_findcoreidx(sbh, SB_CC, 0))) {
17141 + si->gpioidx = sb_findcoreidx(sbh, SB_CC, 0);
17142 + si->gpioid = SB_CC;
17143 + } else if (GOODIDX(si->pciidx) && (si->pcirev >= 2)) {
17144 + si->gpioidx = si->pciidx;
17145 + si->gpioid = SB_PCI;
17146 + } else if (sb_findcoreidx(sbh, SB_EXTIF, 0)) {
17147 + si->gpioidx = sb_findcoreidx(sbh, SB_EXTIF, 0);
17148 + si->gpioid = SB_EXTIF;
17149 + } else
17150 + ASSERT(si->gpioidx != BADIDX);
17151 +
17152 + /* return to original core index */
17153 + sb_setcoreidx(sbh, origidx);
17154 +}
17155 +
17156 +/* may be called with core in reset */
17157 +void
17158 +sb_detach(void *sbh)
17159 +{
17160 + sb_info_t *si;
17161 + uint idx;
17162 +
17163 + si = SB_INFO(sbh);
17164 +
17165 + if (si == NULL)
17166 + return;
17167 +
17168 + if (BUSTYPE(si->bustype) == SB_BUS)
17169 + for (idx = 0; idx < SB_MAXCORES; idx++)
17170 + if (si->regs[idx]) {
17171 + REG_UNMAP(si->regs[idx]);
17172 + si->regs[idx] = NULL;
17173 + }
17174 +
17175 + MFREE(si->osh, si, sizeof (sb_info_t));
17176 +}
17177 +
17178 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
17179 +static uint
17180 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
17181 +{
17182 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
17183 + return (BCM4710_DEVICE_ID);
17184 + if ((pcidev >= BCM4610_DEVICE_ID) && (pcidev <= BCM4610_USB_ID))
17185 + return (BCM4610_DEVICE_ID);
17186 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
17187 + return (BCM4402_DEVICE_ID);
17188 + if (pcidev == BCM4401_ENET_ID)
17189 + return (BCM4402_DEVICE_ID);
17190 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
17191 + return (BCM4307_DEVICE_ID);
17192 + if (pcidev == BCM4301_DEVICE_ID)
17193 + return (BCM4301_DEVICE_ID);
17194 +
17195 + return (0);
17196 +}
17197 +
17198 +/* convert chip number to number of i/o cores */
17199 +static uint
17200 +BCMINITFN(sb_chip2numcores)(uint chip)
17201 +{
17202 + if (chip == 0x4710)
17203 + return (9);
17204 + if (chip == 0x4610)
17205 + return (9);
17206 + if (chip == 0x4402)
17207 + return (3);
17208 + if ((chip == 0x4307) || (chip == 0x4301))
17209 + return (5);
17210 + if (chip == 0x4310)
17211 + return (8);
17212 + if (chip == 0x4306) /* < 4306c0 */
17213 + return (6);
17214 + if (chip == 0x4704)
17215 + return (9);
17216 + if (chip == 0x5365)
17217 + return (7);
17218 +
17219 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
17220 + ASSERT(0);
17221 + return (1);
17222 +}
17223 +
17224 +/* return index of coreid or BADIDX if not found */
17225 +static uint
17226 +sb_findcoreidx(void *sbh, uint coreid, uint coreunit)
17227 +{
17228 + sb_info_t *si;
17229 + uint found;
17230 + uint i;
17231 +
17232 + si = SB_INFO(sbh);
17233 + found = 0;
17234 +
17235 + for (i = 0; i < si->numcores; i++)
17236 + if (si->coreid[i] == coreid) {
17237 + if (found == coreunit)
17238 + return (i);
17239 + found++;
17240 + }
17241 +
17242 + return (BADIDX);
17243 +}
17244 +
17245 +/*
17246 + * this function changes logical "focus" to the indiciated core,
17247 + * must be called with interrupt off.
17248 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
17249 + */
17250 +void*
17251 +sb_setcoreidx(void *sbh, uint coreidx)
17252 +{
17253 + sb_info_t *si;
17254 + uint32 sbaddr;
17255 + uint8 tmp;
17256 +
17257 + si = SB_INFO(sbh);
17258 +
17259 + if (coreidx >= si->numcores)
17260 + return (NULL);
17261 +
17262 + /*
17263 + * If the user has provided an interrupt mask enabled function,
17264 + * then assert interrupts are disabled before switching the core.
17265 + */
17266 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
17267 +
17268 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
17269 +
17270 + switch (BUSTYPE(si->bustype)) {
17271 + case SB_BUS:
17272 + /* map new one */
17273 + if (!si->regs[coreidx]) {
17274 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
17275 + ASSERT(GOODREGS(si->regs[coreidx]));
17276 + }
17277 + si->curmap = si->regs[coreidx];
17278 + break;
17279 +
17280 + case PCI_BUS:
17281 + /* point bar0 window */
17282 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
17283 + break;
17284 +
17285 + case PCMCIA_BUS:
17286 + tmp = (sbaddr >> 12) & 0x0f;
17287 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
17288 + tmp = (sbaddr >> 16) & 0xff;
17289 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
17290 + tmp = (sbaddr >> 24) & 0xff;
17291 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
17292 + break;
17293 + }
17294 +
17295 + si->curidx = coreidx;
17296 +
17297 + return (si->curmap);
17298 +}
17299 +
17300 +/*
17301 + * this function changes logical "focus" to the indiciated core,
17302 + * must be called with interrupt off.
17303 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
17304 + */
17305 +void*
17306 +sb_setcore(void *sbh, uint coreid, uint coreunit)
17307 +{
17308 + sb_info_t *si;
17309 + uint idx;
17310 +
17311 + si = SB_INFO(sbh);
17312 +
17313 + idx = sb_findcoreidx(sbh, coreid, coreunit);
17314 + if (!GOODIDX(idx))
17315 + return (NULL);
17316 +
17317 + return (sb_setcoreidx(sbh, idx));
17318 +}
17319 +
17320 +/* return chip number */
17321 +uint
17322 +BCMINITFN(sb_chip)(void *sbh)
17323 +{
17324 + sb_info_t *si;
17325 +
17326 + si = SB_INFO(sbh);
17327 + return (si->chip);
17328 +}
17329 +
17330 +/* return chip revision number */
17331 +uint
17332 +BCMINITFN(sb_chiprev)(void *sbh)
17333 +{
17334 + sb_info_t *si;
17335 +
17336 + si = SB_INFO(sbh);
17337 + return (si->chiprev);
17338 +}
17339 +
17340 +/* return chip common revision number */
17341 +uint
17342 +BCMINITFN(sb_chipcrev)(void *sbh)
17343 +{
17344 + sb_info_t *si;
17345 +
17346 + si = SB_INFO(sbh);
17347 + return (si->ccrev);
17348 +}
17349 +
17350 +/* return chip package option */
17351 +uint
17352 +BCMINITFN(sb_chippkg)(void *sbh)
17353 +{
17354 + sb_info_t *si;
17355 +
17356 + si = SB_INFO(sbh);
17357 + return (si->chippkg);
17358 +}
17359 +
17360 +/* return PCI core rev. */
17361 +uint
17362 +BCMINITFN(sb_pcirev)(void *sbh)
17363 +{
17364 + sb_info_t *si;
17365 +
17366 + si = SB_INFO(sbh);
17367 + return (si->pcirev);
17368 +}
17369 +
17370 +/* return PCMCIA core rev. */
17371 +uint
17372 +BCMINITFN(sb_pcmciarev)(void *sbh)
17373 +{
17374 + sb_info_t *si;
17375 +
17376 + si = SB_INFO(sbh);
17377 + return (si->pcmciarev);
17378 +}
17379 +
17380 +/* return board vendor id */
17381 +uint
17382 +BCMINITFN(sb_boardvendor)(void *sbh)
17383 +{
17384 + sb_info_t *si;
17385 +
17386 + si = SB_INFO(sbh);
17387 + return (si->boardvendor);
17388 +}
17389 +
17390 +/* return boardtype */
17391 +uint
17392 +BCMINITFN(sb_boardtype)(void *sbh)
17393 +{
17394 + sb_info_t *si;
17395 + char *var;
17396 +
17397 + si = SB_INFO(sbh);
17398 +
17399 + if (BUSTYPE(si->bustype) == SB_BUS && si->boardtype == 0xffff) {
17400 + /* boardtype format is a hex string */
17401 + si->boardtype = getintvar(NULL, "boardtype");
17402 +
17403 + /* backward compatibility for older boardtype string format */
17404 + if ((si->boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
17405 + if (!strcmp(var, "bcm94710dev"))
17406 + si->boardtype = BCM94710D_BOARD;
17407 + else if (!strcmp(var, "bcm94710ap"))
17408 + si->boardtype = BCM94710AP_BOARD;
17409 + else if (!strcmp(var, "bcm94310u"))
17410 + si->boardtype = BCM94310U_BOARD;
17411 + else if (!strcmp(var, "bu4711"))
17412 + si->boardtype = BU4711_BOARD;
17413 + else if (!strcmp(var, "bu4710"))
17414 + si->boardtype = BU4710_BOARD;
17415 + else if (!strcmp(var, "bcm94702mn"))
17416 + si->boardtype = BCM94702MN_BOARD;
17417 + else if (!strcmp(var, "bcm94710r1"))
17418 + si->boardtype = BCM94710R1_BOARD;
17419 + else if (!strcmp(var, "bcm94710r4"))
17420 + si->boardtype = BCM94710R4_BOARD;
17421 + else if (!strcmp(var, "bcm94702cpci"))
17422 + si->boardtype = BCM94702CPCI_BOARD;
17423 + else if (!strcmp(var, "bcm95380_rr"))
17424 + si->boardtype = BCM95380RR_BOARD;
17425 + }
17426 + }
17427 +
17428 + return (si->boardtype);
17429 +}
17430 +
17431 +/* return bus type of sdh device */
17432 +uint
17433 +sb_bus(void *sbh)
17434 +{
17435 + sb_info_t *si;
17436 +
17437 + si = SB_INFO(sbh);
17438 + return (si->bustype);
17439 +}
17440 +
17441 +/* return list of found cores */
17442 +uint
17443 +sb_corelist(void *sbh, uint coreid[])
17444 +{
17445 + sb_info_t *si;
17446 +
17447 + si = SB_INFO(sbh);
17448 +
17449 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
17450 + return (si->numcores);
17451 +}
17452 +
17453 +/* return current register mapping */
17454 +void *
17455 +sb_coreregs(void *sbh)
17456 +{
17457 + sb_info_t *si;
17458 +
17459 + si = SB_INFO(sbh);
17460 + ASSERT(GOODREGS(si->curmap));
17461 +
17462 + return (si->curmap);
17463 +}
17464 +
17465 +
17466 +/* do buffered registers update */
17467 +void
17468 +sb_commit(void *sbh)
17469 +{
17470 + sb_info_t *si;
17471 + uint origidx;
17472 + uint intr_val = 0;
17473 +
17474 + si = SB_INFO(sbh);
17475 +
17476 + origidx = si->curidx;
17477 + ASSERT(GOODIDX(origidx));
17478 +
17479 + INTR_OFF(si, intr_val);
17480 +
17481 + /* switch over to chipcommon core if there is one, else use pci */
17482 + if (si->ccrev != NOREV) {
17483 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
17484 +
17485 + /* do the buffer registers update */
17486 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
17487 + W_REG(&ccregs->broadcastdata, 0x0);
17488 + } else if (si->pciidx != BADIDX) {
17489 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
17490 +
17491 + /* do the buffer registers update */
17492 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
17493 + W_REG(&pciregs->bcastdata, 0x0);
17494 + } else {
17495 + ASSERT((si->ccrev != NOREV) && (si->pciidx != BADIDX));
17496 + }
17497 +
17498 + /* restore core index */
17499 + sb_setcoreidx(sbh, origidx);
17500 + INTR_RESTORE(si, intr_val);
17501 +}
17502 +
17503 +/* reset and re-enable a core */
17504 +void
17505 +sb_core_reset(void *sbh, uint32 bits)
17506 +{
17507 + sb_info_t *si;
17508 + sbconfig_t *sb;
17509 + volatile uint32 dummy;
17510 +
17511 + si = SB_INFO(sbh);
17512 + ASSERT(GOODREGS(si->curmap));
17513 + sb = REGS2SB(si->curmap);
17514 +
17515 + /*
17516 + * Must do the disable sequence first to work for arbitrary current core state.
17517 + */
17518 + sb_core_disable(sbh, bits);
17519 +
17520 + /*
17521 + * Now do the initialization sequence.
17522 + */
17523 +
17524 + /* set reset while enabling the clock and forcing them on throughout the core */
17525 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
17526 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17527 +
17528 + if (sb_coreid(sbh) == SB_ILINE100) {
17529 + bcm_mdelay(50);
17530 + } else {
17531 + OSL_DELAY(1);
17532 + }
17533 +
17534 + if (R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_SERR) {
17535 + W_SBREG(sbh, &sb->sbtmstatehigh, 0);
17536 + }
17537 + if ((dummy = R_SBREG(sbh, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
17538 + AND_SBREG(sbh, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
17539 + }
17540 +
17541 + /* clear reset and allow it to propagate throughout the core */
17542 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
17543 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17544 + OSL_DELAY(1);
17545 +
17546 + /* leave clock enabled */
17547 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | bits));
17548 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17549 + OSL_DELAY(1);
17550 +}
17551 +
17552 +void
17553 +sb_core_tofixup(void *sbh)
17554 +{
17555 + sb_info_t *si;
17556 + sbconfig_t *sb;
17557 +
17558 + si = SB_INFO(sbh);
17559 +
17560 + if ((si->pciidx == BADIDX) || (si->pcirev >= 5))
17561 + return;
17562 +
17563 + ASSERT(GOODREGS(si->curmap));
17564 + sb = REGS2SB(si->curmap);
17565 +
17566 + if (BUSTYPE(si->bustype) == SB_BUS) {
17567 + SET_SBREG(sbh, &sb->sbimconfiglow,
17568 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17569 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
17570 + } else {
17571 + if (sb_coreid(sbh) == SB_PCI) {
17572 + SET_SBREG(sbh, &sb->sbimconfiglow,
17573 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17574 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
17575 + } else {
17576 + SET_SBREG(sbh, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
17577 + }
17578 + }
17579 +
17580 + sb_commit(sbh);
17581 +}
17582 +
17583 +void
17584 +sb_core_disable(void *sbh, uint32 bits)
17585 +{
17586 + sb_info_t *si;
17587 + volatile uint32 dummy;
17588 + sbconfig_t *sb;
17589 +
17590 + si = SB_INFO(sbh);
17591 +
17592 + ASSERT(GOODREGS(si->curmap));
17593 + sb = REGS2SB(si->curmap);
17594 +
17595 + /* if core is already in reset, just return */
17596 + if (R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_RESET)
17597 + return;
17598 +
17599 + /* if clocks are not enabled, put into reset and return */
17600 + if ((R_SBREG(sbh, &sb->sbtmstatelow) & SBTML_CLK) == 0)
17601 + goto disable;
17602 +
17603 + /* set the target reject bit and spin until busy is clear */
17604 + W_SBREG(sbh, &sb->sbtmstatelow, (SBTML_CLK | SBTML_REJ));
17605 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17606 + OSL_DELAY(1);
17607 + SPINWAIT((R_SBREG(sbh, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
17608 +
17609 + if (R_SBREG(sbh, &sb->sbidlow) & SBIDL_INIT) {
17610 + OR_SBREG(sbh, &sb->sbimstate, SBIM_RJ);
17611 + dummy = R_SBREG(sbh, &sb->sbimstate);
17612 + OSL_DELAY(1);
17613 + SPINWAIT((R_SBREG(sbh, &sb->sbimstate) & SBIM_BY), 100000);
17614 + }
17615 +
17616 + /* set reset and reject while enabling the clocks */
17617 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET));
17618 + dummy = R_SBREG(sbh, &sb->sbtmstatelow);
17619 + OSL_DELAY(10);
17620 +
17621 + /* don't forget to clear the initiator reject bit */
17622 + if (R_SBREG(sbh, &sb->sbidlow) & SBIDL_INIT)
17623 + AND_SBREG(sbh, &sb->sbimstate, ~SBIM_RJ);
17624 +
17625 +disable:
17626 + /* leave reset and reject asserted */
17627 + W_SBREG(sbh, &sb->sbtmstatelow, (bits | SBTML_REJ | SBTML_RESET));
17628 + OSL_DELAY(1);
17629 +}
17630 +
17631 +void
17632 +sb_watchdog(void *sbh, uint ticks)
17633 +{
17634 + sb_info_t *si = SB_INFO(sbh);
17635 +
17636 + /* instant NMI */
17637 + switch (si->gpioid) {
17638 + case SB_CC:
17639 + sb_corereg(sbh, si->gpioidx, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
17640 + break;
17641 + case SB_EXTIF:
17642 + sb_corereg(sbh, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
17643 + break;
17644 + }
17645 +}
17646 +
17647 +/* initialize the pcmcia core */
17648 +void
17649 +sb_pcmcia_init(void *sbh)
17650 +{
17651 + sb_info_t *si;
17652 + uint8 cor;
17653 +
17654 + si = SB_INFO(sbh);
17655 +
17656 + /* enable d11 mac interrupts */
17657 + if (si->chip == BCM4301_DEVICE_ID) {
17658 + /* Have to use FCR2 in 4301 */
17659 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
17660 + cor |= COR_IRQEN | COR_FUNEN;
17661 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
17662 + } else {
17663 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
17664 + cor |= COR_IRQEN | COR_FUNEN;
17665 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
17666 + }
17667 +
17668 +}
17669 +
17670 +
17671 +/*
17672 + * Configure the pci core for pci client (NIC) action
17673 + * and get appropriate dma offset value.
17674 + * coremask is the bitvec of cores by index to be enabled.
17675 + */
17676 +void
17677 +sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask)
17678 +{
17679 + sb_info_t *si;
17680 + sbconfig_t *sb;
17681 + sbpciregs_t *pciregs;
17682 + uint32 sbflag;
17683 + uint32 w;
17684 + uint idx;
17685 +
17686 + si = SB_INFO(sbh);
17687 +
17688 + if (dmaoffset)
17689 + *dmaoffset = 0;
17690 +
17691 + /* if not pci bus, we're done */
17692 + if (BUSTYPE(si->bustype) != PCI_BUS)
17693 + return;
17694 +
17695 + ASSERT(si->pciidx != BADIDX);
17696 +
17697 + /* get current core index */
17698 + idx = si->curidx;
17699 +
17700 + /* we interrupt on this backplane flag number */
17701 + ASSERT(GOODREGS(si->curmap));
17702 + sb = REGS2SB(si->curmap);
17703 + sbflag = R_SBREG(sbh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
17704 +
17705 + /* switch over to pci core */
17706 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->pciidx);
17707 + sb = REGS2SB(pciregs);
17708 +
17709 + /*
17710 + * Enable sb->pci interrupts. Assume
17711 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
17712 + */
17713 + if (si->pcirev < 6) {
17714 + /* set sbintvec bit for our flag number */
17715 + OR_SBREG(sbh, &sb->sbintvec, (1 << sbflag));
17716 + } else {
17717 + /* pci config write to set this core bit in PCIIntMask */
17718 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
17719 + w |= (coremask << PCI_SBIM_SHIFT);
17720 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
17721 + }
17722 +
17723 + /* enable prefetch and bursts for dma big window */
17724 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
17725 +
17726 + /* enable read multiple for dma big window */
17727 + if (si->pcirev >= 11)
17728 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
17729 +
17730 + if (si->pcirev < 5) {
17731 + SET_SBREG(sbh, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
17732 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
17733 + sb_commit(sbh);
17734 + }
17735 +
17736 + /* switch back to previous core */
17737 + sb_setcoreidx(sbh, idx);
17738 +
17739 + /* use large sb pci dma window */
17740 + if (dmaoffset)
17741 + *dmaoffset = SB_PCI_DMA;
17742 +}
17743 +
17744 +uint32
17745 +sb_base(uint32 admatch)
17746 +{
17747 + uint32 base;
17748 + uint type;
17749 +
17750 + type = admatch & SBAM_TYPE_MASK;
17751 + ASSERT(type < 3);
17752 +
17753 + base = 0;
17754 +
17755 + if (type == 0) {
17756 + base = admatch & SBAM_BASE0_MASK;
17757 + } else if (type == 1) {
17758 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17759 + base = admatch & SBAM_BASE1_MASK;
17760 + } else if (type == 2) {
17761 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17762 + base = admatch & SBAM_BASE2_MASK;
17763 + }
17764 +
17765 + return (base);
17766 +}
17767 +
17768 +uint32
17769 +sb_size(uint32 admatch)
17770 +{
17771 + uint32 size;
17772 + uint type;
17773 +
17774 + type = admatch & SBAM_TYPE_MASK;
17775 + ASSERT(type < 3);
17776 +
17777 + size = 0;
17778 +
17779 + if (type == 0) {
17780 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
17781 + } else if (type == 1) {
17782 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17783 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
17784 + } else if (type == 2) {
17785 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
17786 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
17787 + }
17788 +
17789 + return (size);
17790 +}
17791 +
17792 +/* return the core-type instantiation # of the current core */
17793 +uint
17794 +sb_coreunit(void *sbh)
17795 +{
17796 + sb_info_t *si;
17797 + uint idx;
17798 + uint coreid;
17799 + uint coreunit;
17800 + uint i;
17801 +
17802 + si = SB_INFO(sbh);
17803 + coreunit = 0;
17804 +
17805 + idx = si->curidx;
17806 +
17807 + ASSERT(GOODREGS(si->curmap));
17808 + coreid = sb_coreid(sbh);
17809 +
17810 + /* count the cores of our type */
17811 + for (i = 0; i < idx; i++)
17812 + if (si->coreid[i] == coreid)
17813 + coreunit++;
17814 +
17815 + return (coreunit);
17816 +}
17817 +
17818 +static INLINE uint32
17819 +factor6(uint32 x)
17820 +{
17821 + switch (x) {
17822 + case CC_F6_2: return 2;
17823 + case CC_F6_3: return 3;
17824 + case CC_F6_4: return 4;
17825 + case CC_F6_5: return 5;
17826 + case CC_F6_6: return 6;
17827 + case CC_F6_7: return 7;
17828 + default: return 0;
17829 + }
17830 +}
17831 +
17832 +/* calculate the speed the SB would run at given a set of clockcontrol values */
17833 +uint32
17834 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
17835 +{
17836 + uint32 n1, n2, clock, m1, m2, m3, mc;
17837 +
17838 + n1 = n & CN_N1_MASK;
17839 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
17840 +
17841 + if (pll_type == PLL_TYPE6) {
17842 + if (m & CC_T6_MMASK)
17843 + return CC_T6_M1;
17844 + else
17845 + return CC_T6_M0;
17846 + } else if ((pll_type == PLL_TYPE1) ||
17847 + (pll_type == PLL_TYPE3) ||
17848 + (pll_type == PLL_TYPE4) ||
17849 + (pll_type == PLL_TYPE7)) {
17850 + n1 = factor6(n1);
17851 + n2 += CC_F5_BIAS;
17852 + } else if (pll_type == PLL_TYPE2) {
17853 + n1 += CC_T2_BIAS;
17854 + n2 += CC_T2_BIAS;
17855 + ASSERT((n1 >= 2) && (n1 <= 7));
17856 + ASSERT((n2 >= 5) && (n2 <= 23));
17857 + } else if (pll_type == PLL_TYPE5) {
17858 + return (100000000);
17859 + } else
17860 + ASSERT((pll_type >= PLL_TYPE1) && (pll_type <= PLL_TYPE4));
17861 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
17862 + if ((pll_type == PLL_TYPE3) ||
17863 + (pll_type == PLL_TYPE7)) {
17864 + clock = CC_CLOCK_BASE2 * n1 * n2;
17865 + }
17866 + else
17867 + clock = CC_CLOCK_BASE1 * n1 * n2;
17868 +
17869 + if (clock == 0)
17870 + return 0;
17871 +
17872 + m1 = m & CC_M1_MASK;
17873 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
17874 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
17875 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
17876 +
17877 + if ((pll_type == PLL_TYPE1) ||
17878 + (pll_type == PLL_TYPE3) ||
17879 + (pll_type == PLL_TYPE4) ||
17880 + (pll_type == PLL_TYPE7)) {
17881 + m1 = factor6(m1);
17882 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
17883 + m2 += CC_F5_BIAS;
17884 + else
17885 + m2 = factor6(m2);
17886 + m3 = factor6(m3);
17887 +
17888 + switch (mc) {
17889 + case CC_MC_BYPASS: return (clock);
17890 + case CC_MC_M1: return (clock / m1);
17891 + case CC_MC_M1M2: return (clock / (m1 * m2));
17892 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
17893 + case CC_MC_M1M3: return (clock / (m1 * m3));
17894 + default: return (0);
17895 + }
17896 + } else {
17897 + ASSERT(pll_type == PLL_TYPE2);
17898 +
17899 + m1 += CC_T2_BIAS;
17900 + m2 += CC_T2M2_BIAS;
17901 + m3 += CC_T2_BIAS;
17902 + ASSERT((m1 >= 2) && (m1 <= 7));
17903 + ASSERT((m2 >= 3) && (m2 <= 10));
17904 + ASSERT((m3 >= 2) && (m3 <= 7));
17905 +
17906 + if ((mc & CC_T2MC_M1BYP) == 0)
17907 + clock /= m1;
17908 + if ((mc & CC_T2MC_M2BYP) == 0)
17909 + clock /= m2;
17910 + if ((mc & CC_T2MC_M3BYP) == 0)
17911 + clock /= m3;
17912 +
17913 + return(clock);
17914 + }
17915 +}
17916 +
17917 +/* returns the current speed the SB is running at */
17918 +uint32
17919 +sb_clock(void *sbh)
17920 +{
17921 + sb_info_t *si;
17922 + extifregs_t *eir;
17923 + chipcregs_t *cc;
17924 + uint32 n, m;
17925 + uint idx;
17926 + uint32 pll_type, rate;
17927 + uint intr_val = 0;
17928 +
17929 + si = SB_INFO(sbh);
17930 + idx = si->curidx;
17931 + pll_type = PLL_TYPE1;
17932 +
17933 + INTR_OFF(si, intr_val);
17934 +
17935 + /* switch to extif or chipc core */
17936 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
17937 + n = R_REG(&eir->clockcontrol_n);
17938 + m = R_REG(&eir->clockcontrol_sb);
17939 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
17940 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
17941 + n = R_REG(&cc->clockcontrol_n);
17942 + if (pll_type == PLL_TYPE6)
17943 + m = R_REG(&cc->clockcontrol_mips);
17944 + else if ((pll_type == PLL_TYPE3) && (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID))
17945 + m = R_REG(&cc->clockcontrol_m2);
17946 + else
17947 + m = R_REG(&cc->clockcontrol_sb);
17948 + } else {
17949 + INTR_RESTORE(si, intr_val);
17950 + return 0;
17951 + }
17952 +
17953 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) {
17954 + rate = 100000000;
17955 + } else {
17956 + /* calculate rate */
17957 + rate = sb_clock_rate(pll_type, n, m);
17958 + if (pll_type == PLL_TYPE3)
17959 + rate = rate / 2;
17960 + }
17961 +
17962 +
17963 + /* switch back to previous core */
17964 + sb_setcoreidx(sbh, idx);
17965 +
17966 + INTR_RESTORE(si, intr_val);
17967 +
17968 + return rate;
17969 +}
17970 +
17971 +/* change logical "focus" to the gpio core for optimized access */
17972 +void*
17973 +sb_gpiosetcore(void *sbh)
17974 +{
17975 + sb_info_t *si;
17976 +
17977 + si = SB_INFO(sbh);
17978 +
17979 + return (sb_setcoreidx(sbh, si->gpioidx));
17980 +}
17981 +
17982 +/* mask&set gpiocontrol bits */
17983 +uint32
17984 +sb_gpiocontrol(void *sbh, uint32 mask, uint32 val)
17985 +{
17986 + sb_info_t *si;
17987 + uint regoff;
17988 +
17989 + si = SB_INFO(sbh);
17990 + regoff = 0;
17991 +
17992 + switch (si->gpioid) {
17993 + case SB_CC:
17994 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
17995 + break;
17996 +
17997 + case SB_PCI:
17998 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
17999 + break;
18000 +
18001 + case SB_EXTIF:
18002 + return (0);
18003 + }
18004 +
18005 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
18006 +}
18007 +
18008 +/* mask&set gpio output enable bits */
18009 +uint32
18010 +sb_gpioouten(void *sbh, uint32 mask, uint32 val)
18011 +{
18012 + sb_info_t *si;
18013 + uint regoff;
18014 +
18015 + si = SB_INFO(sbh);
18016 + regoff = 0;
18017 +
18018 + switch (si->gpioid) {
18019 + case SB_CC:
18020 + regoff = OFFSETOF(chipcregs_t, gpioouten);
18021 + break;
18022 +
18023 + case SB_PCI:
18024 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
18025 + break;
18026 +
18027 + case SB_EXTIF:
18028 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
18029 + break;
18030 + }
18031 +
18032 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
18033 +}
18034 +
18035 +/* mask&set gpio output bits */
18036 +uint32
18037 +sb_gpioout(void *sbh, uint32 mask, uint32 val)
18038 +{
18039 + sb_info_t *si;
18040 + uint regoff;
18041 +
18042 + si = SB_INFO(sbh);
18043 + regoff = 0;
18044 +
18045 + switch (si->gpioid) {
18046 + case SB_CC:
18047 + regoff = OFFSETOF(chipcregs_t, gpioout);
18048 + break;
18049 +
18050 + case SB_PCI:
18051 + regoff = OFFSETOF(sbpciregs_t, gpioout);
18052 + break;
18053 +
18054 + case SB_EXTIF:
18055 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
18056 + break;
18057 + }
18058 +
18059 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
18060 +}
18061 +
18062 +/* return the current gpioin register value */
18063 +uint32
18064 +sb_gpioin(void *sbh)
18065 +{
18066 + sb_info_t *si;
18067 + uint regoff;
18068 +
18069 + si = SB_INFO(sbh);
18070 + regoff = 0;
18071 +
18072 + switch (si->gpioid) {
18073 + case SB_CC:
18074 + regoff = OFFSETOF(chipcregs_t, gpioin);
18075 + break;
18076 +
18077 + case SB_PCI:
18078 + regoff = OFFSETOF(sbpciregs_t, gpioin);
18079 + break;
18080 +
18081 + case SB_EXTIF:
18082 + regoff = OFFSETOF(extifregs_t, gpioin);
18083 + break;
18084 + }
18085 +
18086 + return (sb_corereg(sbh, si->gpioidx, regoff, 0, 0));
18087 +}
18088 +
18089 +/* mask&set gpio interrupt polarity bits */
18090 +uint32
18091 +sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val)
18092 +{
18093 + sb_info_t *si;
18094 + uint regoff;
18095 +
18096 + si = SB_INFO(sbh);
18097 + regoff = 0;
18098 +
18099 + switch (si->gpioid) {
18100 + case SB_CC:
18101 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
18102 + break;
18103 +
18104 + case SB_PCI:
18105 + /* pci gpio implementation does not support interrupt polarity */
18106 + ASSERT(0);
18107 + break;
18108 +
18109 + case SB_EXTIF:
18110 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
18111 + break;
18112 + }
18113 +
18114 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
18115 +}
18116 +
18117 +/* mask&set gpio interrupt mask bits */
18118 +uint32
18119 +sb_gpiointmask(void *sbh, uint32 mask, uint32 val)
18120 +{
18121 + sb_info_t *si;
18122 + uint regoff;
18123 +
18124 + si = SB_INFO(sbh);
18125 + regoff = 0;
18126 +
18127 + switch (si->gpioid) {
18128 + case SB_CC:
18129 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
18130 + break;
18131 +
18132 + case SB_PCI:
18133 + /* pci gpio implementation does not support interrupt mask */
18134 + ASSERT(0);
18135 + break;
18136 +
18137 + case SB_EXTIF:
18138 + regoff = OFFSETOF(extifregs_t, gpiointmask);
18139 + break;
18140 + }
18141 +
18142 + return (sb_corereg(sbh, si->gpioidx, regoff, mask, val));
18143 +}
18144 +
18145 +
18146 +/*
18147 + * Return the slow clock source.
18148 + * Three sources of SLOW CLOCK: LPO, Xtal, PCI
18149 + */
18150 +static uint
18151 +sb_slowclk_src(void *sbh)
18152 +{
18153 + sb_info_t *si;
18154 + chipcregs_t *cc;
18155 + uint32 v;
18156 +
18157 + si = SB_INFO(sbh);
18158 +
18159 + ASSERT(sb_coreid(sbh) == SB_CC);
18160 +
18161 + if (si->ccrev < 6) {
18162 + switch (BUSTYPE(si->bustype)) {
18163 + case PCMCIA_BUS: return (SCC_SS_XTAL);
18164 + case PCI_BUS:
18165 + v = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
18166 + if (v & PCI_CFG_GPIO_SCS)
18167 + return (SCC_SS_PCI);
18168 + else
18169 + return (SCC_SS_XTAL);
18170 + default: return (SCC_SS_XTAL);
18171 + }
18172 + } else if (si->ccrev < 10) {
18173 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
18174 + v = R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
18175 + return (v);
18176 + } else {
18177 + return (SCC_SS_XTAL);
18178 + }
18179 +}
18180 +
18181 +/*
18182 + * Return the slowclock min or max frequency.
18183 + * Three sources of SLOW CLOCK:
18184 + * 1. On Chip LPO - 32khz or 160khz
18185 + * 2. On Chip Xtal OSC - 20mhz/4*(divider+1)
18186 + * 3. External PCI clock - 66mhz/4*(divider+1)
18187 + */
18188 +static uint
18189 +sb_slowclk_freq(void *sbh, bool max)
18190 +{
18191 + sb_info_t *si;
18192 + chipcregs_t *cc;
18193 + uint32 slowclk;
18194 + uint div;
18195 +
18196 + si = SB_INFO(sbh);
18197 +
18198 + ASSERT(sb_coreid(sbh) == SB_CC);
18199 +
18200 + cc = (chipcregs_t*) sb_setcoreidx(sbh, si->curidx);
18201 +
18202 + /* shouldn't be here unless we've established the chip has dynamic power control */
18203 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
18204 +
18205 + slowclk = sb_slowclk_src(sbh);
18206 + if (si->ccrev < 6) {
18207 + if (slowclk == SCC_SS_PCI)
18208 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
18209 + else
18210 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
18211 + } else if (si->ccrev < 10) {
18212 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
18213 + if (slowclk == SCC_SS_LPO)
18214 + return (max? LPOMAXFREQ : LPOMINFREQ);
18215 + else if (slowclk == SCC_SS_XTAL)
18216 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
18217 + else if (slowclk == SCC_SS_PCI)
18218 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
18219 + else
18220 + ASSERT(0);
18221 + } else {
18222 + /* Chipc rev 10 is InstaClock */
18223 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHF;
18224 + div = 4 * (div + 1);
18225 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
18226 + }
18227 + return (0);
18228 +}
18229 +
18230 +static void
18231 +sb_pwrctl_setdelay(void *sbh, void *chipcregs)
18232 +{
18233 + sb_info_t *si;
18234 + chipcregs_t * cc;
18235 + uint slowmaxfreq, pll_delay, slowclk;
18236 + uint pll_on_delay, fref_sel_delay;
18237 +
18238 + si = SB_INFO(sbh);
18239 + pll_delay = PLL_DELAY;
18240 +
18241 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
18242 + * since the xtal will also be powered down by dynamic power control logic.
18243 + */
18244 + slowclk = sb_slowclk_src(sbh);
18245 + if (slowclk != SCC_SS_XTAL)
18246 + pll_delay += XTAL_ON_DELAY;
18247 +
18248 + /* Starting with 4318 it is ILP that is used for the delays */
18249 + slowmaxfreq = sb_slowclk_freq(sbh, (si->ccrev >= 10) ? FALSE : TRUE);
18250 +
18251 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
18252 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
18253 +
18254 + cc = (chipcregs_t *)chipcregs;
18255 + W_REG(&cc->pll_on_delay, pll_on_delay);
18256 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
18257 +}
18258 +
18259 +/* set or get slow clock divider */
18260 +int
18261 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
18262 +{
18263 + sb_info_t *si;
18264 + uint origidx;
18265 + chipcregs_t *cc;
18266 + uint intr_val = 0;
18267 + uint err = 0;
18268 +
18269 + si = SB_INFO(sbh);
18270 +
18271 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
18272 + if (si->ccrev < 6)
18273 + return 1;
18274 +
18275 + /* chipcommon cores rev10 are a whole new ball game */
18276 + if (si->ccrev >= 10)
18277 + return 1;
18278 +
18279 + if (set && ((*div % 4) || (*div < 4)))
18280 + return 2;
18281 +
18282 + INTR_OFF(si, intr_val);
18283 + origidx = si->curidx;
18284 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
18285 + ASSERT(cc != NULL);
18286 +
18287 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
18288 + err = 3;
18289 + goto done;
18290 + }
18291 +
18292 + if (set) {
18293 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHF));
18294 + sb_pwrctl_setdelay(sbh, (void *)cc);
18295 + } else
18296 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHF) + 1);
18297 +
18298 +done:
18299 + sb_setcoreidx(sbh, origidx);
18300 + INTR_RESTORE(si, intr_val);
18301 + return err;
18302 +}
18303 +
18304 +/* initialize power control delay registers */
18305 +void
18306 +sb_pwrctl_init(void *sbh)
18307 +{
18308 + sb_info_t *si;
18309 + uint origidx;
18310 + chipcregs_t *cc;
18311 +
18312 + si = SB_INFO(sbh);
18313 +
18314 + origidx = si->curidx;
18315 +
18316 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
18317 + return;
18318 +
18319 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18320 + goto done;
18321 +
18322 + /* 4317pc does not work with SlowClock less than 5Mhz */
18323 + if (BUSTYPE(si->bustype) == PCMCIA_BUS) {
18324 + if ((si->ccrev >= 6) && (si->ccrev < 10))
18325 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (SCC_DEF_DIV << SCC_CD_SHF));
18326 + }
18327 +
18328 + sb_pwrctl_setdelay(sbh, (void *)cc);
18329 +
18330 +done:
18331 + sb_setcoreidx(sbh, origidx);
18332 +}
18333 +
18334 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
18335 +uint16
18336 +sb_pwrctl_fast_pwrup_delay(void *sbh)
18337 +{
18338 + sb_info_t *si;
18339 + uint origidx;
18340 + chipcregs_t *cc;
18341 + uint slowminfreq;
18342 + uint16 fpdelay;
18343 + uint intr_val = 0;
18344 +
18345 + si = SB_INFO(sbh);
18346 + fpdelay = 0;
18347 + origidx = si->curidx;
18348 +
18349 + if (BUSTYPE(si->bustype) == SB_BUS)
18350 + goto done;
18351 +
18352 + INTR_OFF(si, intr_val);
18353 +
18354 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
18355 + goto done;
18356 +
18357 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18358 + goto done;
18359 +
18360 + slowminfreq = sb_slowclk_freq(sbh, FALSE);
18361 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
18362 +
18363 +done:
18364 + sb_setcoreidx(sbh, origidx);
18365 + INTR_RESTORE(si, intr_val);
18366 + return (fpdelay);
18367 +}
18368 +
18369 +/* turn primary xtal and/or pll off/on */
18370 +int
18371 +sb_pwrctl_xtal(void *sbh, uint what, bool on)
18372 +{
18373 + sb_info_t *si;
18374 + uint32 in, out, outen;
18375 +
18376 + si = SB_INFO(sbh);
18377 +
18378 + switch (BUSTYPE(si->bustype)) {
18379 +
18380 +
18381 + case PCMCIA_BUS:
18382 + return (0);
18383 +
18384 +
18385 + case PCI_BUS:
18386 +
18387 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
18388 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
18389 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
18390 +
18391 + /*
18392 + * Avoid glitching the clock if GPRS is already using it.
18393 + * We can't actually read the state of the PLLPD so we infer it
18394 + * by the value of XTAL_PU which *is* readable via gpioin.
18395 + */
18396 + if (on && (in & PCI_CFG_GPIO_XTAL))
18397 + return (0);
18398 +
18399 + if (what & XTAL)
18400 + outen |= PCI_CFG_GPIO_XTAL;
18401 + if (what & PLL)
18402 + outen |= PCI_CFG_GPIO_PLL;
18403 +
18404 + if (on) {
18405 + /* turn primary xtal on */
18406 + if (what & XTAL) {
18407 + out |= PCI_CFG_GPIO_XTAL;
18408 + if (what & PLL)
18409 + out |= PCI_CFG_GPIO_PLL;
18410 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18411 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
18412 + OSL_DELAY(XTAL_ON_DELAY);
18413 + }
18414 +
18415 + /* turn pll on */
18416 + if (what & PLL) {
18417 + out &= ~PCI_CFG_GPIO_PLL;
18418 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18419 + OSL_DELAY(2000);
18420 + }
18421 + } else {
18422 + if (what & XTAL)
18423 + out &= ~PCI_CFG_GPIO_XTAL;
18424 + if (what & PLL)
18425 + out |= PCI_CFG_GPIO_PLL;
18426 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
18427 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
18428 + }
18429 +
18430 + default:
18431 + return (-1);
18432 + }
18433 +
18434 + return (0);
18435 +}
18436 +
18437 +/* set dynamic power control mode (forceslow, forcefast, dynamic) */
18438 +/* returns true if ignore pll off is set and false if it is not */
18439 +bool
18440 +sb_pwrctl_clk(void *sbh, uint mode)
18441 +{
18442 + sb_info_t *si;
18443 + uint origidx;
18444 + chipcregs_t *cc;
18445 + uint32 scc;
18446 + bool forcefastclk=FALSE;
18447 + uint intr_val = 0;
18448 +
18449 + si = SB_INFO(sbh);
18450 +
18451 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
18452 + if (si->ccrev < 6)
18453 + return (FALSE);
18454 +
18455 + /* chipcommon cores rev10 are a whole new ball game */
18456 + if (si->ccrev >= 10)
18457 + return (FALSE);
18458 +
18459 + INTR_OFF(si, intr_val);
18460 +
18461 + origidx = si->curidx;
18462 +
18463 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
18464 + ASSERT(cc != NULL);
18465 +
18466 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
18467 + goto done;
18468 +
18469 + switch (mode) {
18470 + case CLK_FAST: /* force fast (pll) clock */
18471 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
18472 + sb_pwrctl_xtal(sbh, XTAL, ON);
18473 +
18474 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
18475 + break;
18476 +
18477 + case CLK_SLOW: /* force slow clock */
18478 + if ((BUSTYPE(si->bustype) == SDIO_BUS) || (BUSTYPE(si->bustype) == PCMCIA_BUS))
18479 + return (-1);
18480 +
18481 + if (si->ccrev >= 6)
18482 + OR_REG(&cc->slow_clk_ctl, SCC_FS);
18483 + break;
18484 +
18485 + case CLK_DYNAMIC: /* enable dynamic power control */
18486 + scc = R_REG(&cc->slow_clk_ctl);
18487 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
18488 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
18489 + scc |= SCC_XC;
18490 + W_REG(&cc->slow_clk_ctl, scc);
18491 +
18492 + /* for dynamic control, we have to release our xtal_pu "force on" */
18493 + if (scc & SCC_XC)
18494 + sb_pwrctl_xtal(sbh, XTAL, OFF);
18495 + break;
18496 + }
18497 +
18498 + /* Is the h/w forcing the use of the fast clk */
18499 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
18500 +
18501 +done:
18502 + sb_setcoreidx(sbh, origidx);
18503 + INTR_RESTORE(si, intr_val);
18504 + return (forcefastclk);
18505 +}
18506 +
18507 +/* register driver interrupt disabling and restoring callback functions */
18508 +void
18509 +sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
18510 +{
18511 + sb_info_t *si;
18512 +
18513 + si = SB_INFO(sbh);
18514 + si->intr_arg = intr_arg;
18515 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
18516 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
18517 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
18518 + /* save current core id. when this function called, the current core
18519 + * must be the core which provides driver functions(il, et, wl, etc.)
18520 + */
18521 + si->dev_coreid = si->coreid[si->curidx];
18522 +}
18523 +
18524 +
18525 diff -urN linux.old/drivers/net/hnd/shared_ksyms.sh linux.dev/drivers/net/hnd/shared_ksyms.sh
18526 --- linux.old/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
18527 +++ linux.dev/drivers/net/hnd/shared_ksyms.sh 2005-08-26 13:44:34.406377232 +0200
18528 @@ -0,0 +1,21 @@
18529 +#!/bin/sh
18530 +#
18531 +# Copyright 2004, Broadcom Corporation
18532 +# All Rights Reserved.
18533 +#
18534 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18535 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18536 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18537 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18538 +#
18539 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
18540 +#
18541 +
18542 +cat <<EOF
18543 +#include <linux/config.h>
18544 +#include <linux/module.h>
18545 +EOF
18546 +
18547 +for file in $* ; do
18548 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
18549 +done
18550 diff -urN linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
18551 --- linux.old/drivers/net/wireless/Config.in 2004-11-17 12:54:21.000000000 +0100
18552 +++ linux.dev/drivers/net/wireless/Config.in 2005-08-26 13:44:34.427374040 +0200
18553 @@ -13,6 +13,7 @@
18554 fi
18555
18556 if [ "$CONFIG_PCI" = "y" ]; then
18557 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
18558 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18559 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18560 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
18561 diff -urN linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
18562 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
18563 +++ linux.dev/drivers/net/wl/Makefile 2005-08-26 13:44:34.427374040 +0200
18564 @@ -0,0 +1,26 @@
18565 +#
18566 +# Makefile for the Broadcom wl driver
18567 +#
18568 +# Copyright 2004, Broadcom Corporation
18569 +# All Rights Reserved.
18570 +#
18571 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18572 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18573 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18574 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18575 +#
18576 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
18577 +
18578 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
18579 +
18580 +O_TARGET := wl.o
18581 +
18582 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
18583 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
18584 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
18585 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
18586 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
18587 +
18588 +obj-m := $(O_TARGET)
18589 +
18590 +include $(TOPDIR)/Rules.make
18591 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
18592 --- linux.old/drivers/parport/Config.in 2004-02-18 14:36:31.000000000 +0100
18593 +++ linux.dev/drivers/parport/Config.in 2005-08-26 13:44:34.428373888 +0200
18594 @@ -11,6 +11,7 @@
18595 tristate 'Parallel port support' CONFIG_PARPORT
18596 if [ "$CONFIG_PARPORT" != "n" ]; then
18597 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
18598 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
18599 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
18600 if [ "$CONFIG_SERIAL" = "m" ]; then
18601 define_tristate CONFIG_PARPORT_PC_CML1 m
18602 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
18603 --- linux.old/drivers/parport/Makefile 2004-08-08 01:26:05.000000000 +0200
18604 +++ linux.dev/drivers/parport/Makefile 2005-08-26 13:44:34.428373888 +0200
18605 @@ -22,6 +22,7 @@
18606
18607 obj-$(CONFIG_PARPORT) += parport.o
18608 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
18609 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
18610 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
18611 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
18612 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
18613 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
18614 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
18615 +++ linux.dev/drivers/parport/parport_splink.c 2005-08-26 13:44:34.429373736 +0200
18616 @@ -0,0 +1,345 @@
18617 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
18618 + *
18619 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
18620 + * Based on parport_pc source
18621 + */
18622 +
18623 +#include <linux/config.h>
18624 +#include <linux/module.h>
18625 +#include <linux/init.h>
18626 +#include <linux/ioport.h>
18627 +#include <linux/kernel.h>
18628 +#include <linux/slab.h>
18629 +#include <linux/parport.h>
18630 +#include <linux/parport_pc.h>
18631 +
18632 +#define SPLINK_ADDRESS 0xBF800010
18633 +
18634 +#undef DEBUG
18635 +
18636 +#ifdef DEBUG
18637 +#define DPRINTK printk
18638 +#else
18639 +#define DPRINTK(stuff...)
18640 +#endif
18641 +
18642 +
18643 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
18644 + * it doesn't do any extra masking. */
18645 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
18646 + unsigned char mask,
18647 + unsigned char val)
18648 +{
18649 + struct parport_pc_private *priv = p->physport->private_data;
18650 + unsigned char *io = (unsigned char *) p->base;
18651 + unsigned char ctr = priv->ctr;
18652 +#ifdef DEBUG_PARPORT
18653 + printk (KERN_DEBUG
18654 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
18655 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
18656 +#endif
18657 + ctr = (ctr & ~mask) ^ val;
18658 + ctr &= priv->ctr_writable; /* only write writable bits. */
18659 + *(io+2) = ctr;
18660 + priv->ctr = ctr; /* Update soft copy */
18661 + return ctr;
18662 +}
18663 +
18664 +
18665 +
18666 +static void parport_splink_data_forward (struct parport *p)
18667 +{
18668 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
18669 + __parport_splink_frob_control (p, 0x20, 0);
18670 +}
18671 +
18672 +static void parport_splink_data_reverse (struct parport *p)
18673 +{
18674 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
18675 + __parport_splink_frob_control (p, 0x20, 0x20);
18676 +}
18677 +
18678 +/*
18679 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
18680 +{
18681 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
18682 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
18683 +}
18684 +*/
18685 +
18686 +static void parport_splink_enable_irq(struct parport *p)
18687 +{
18688 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
18689 + __parport_splink_frob_control (p, 0x10, 0x10);
18690 +}
18691 +
18692 +static void parport_splink_disable_irq(struct parport *p)
18693 +{
18694 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
18695 + __parport_splink_frob_control (p, 0x10, 0);
18696 +}
18697 +
18698 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
18699 +{
18700 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
18701 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
18702 + if (dev->irq_func &&
18703 + dev->port->irq != PARPORT_IRQ_NONE)
18704 + /* Set ackIntEn */
18705 + s->u.pc.ctr |= 0x10;
18706 +}
18707 +
18708 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
18709 +{
18710 + const struct parport_pc_private *priv = p->physport->private_data;
18711 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
18712 + s->u.pc.ctr = priv->ctr;
18713 +}
18714 +
18715 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
18716 +{
18717 + struct parport_pc_private *priv = p->physport->private_data;
18718 + unsigned char *io = (unsigned char *) p->base;
18719 + unsigned char ctr = s->u.pc.ctr;
18720 +
18721 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
18722 + *(io+2) = ctr;
18723 + priv->ctr = ctr;
18724 +}
18725 +
18726 +static void parport_splink_setup_interrupt(void) {
18727 + return;
18728 +}
18729 +
18730 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
18731 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
18732 + unsigned char *io = (unsigned char *) p->base;
18733 + *io = d;
18734 +}
18735 +
18736 +static unsigned char parport_splink_read_data(struct parport *p) {
18737 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
18738 + unsigned char *io = (unsigned char *) p->base;
18739 + return *io;
18740 +}
18741 +
18742 +static void parport_splink_write_control(struct parport *p, unsigned char d)
18743 +{
18744 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18745 + PARPORT_CONTROL_AUTOFD |
18746 + PARPORT_CONTROL_INIT |
18747 + PARPORT_CONTROL_SELECT);
18748 +
18749 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
18750 + /* Take this out when drivers have adapted to the newer interface. */
18751 + if (d & 0x20) {
18752 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
18753 + p->name, p->cad->name);
18754 + parport_splink_data_reverse (p);
18755 + }
18756 +
18757 + __parport_splink_frob_control (p, wm, d & wm);
18758 +}
18759 +
18760 +static unsigned char parport_splink_read_control(struct parport *p)
18761 +{
18762 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18763 + PARPORT_CONTROL_AUTOFD |
18764 + PARPORT_CONTROL_INIT |
18765 + PARPORT_CONTROL_SELECT);
18766 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
18767 + const struct parport_pc_private *priv = p->physport->private_data;
18768 + return priv->ctr & wm; /* Use soft copy */
18769 +}
18770 +
18771 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
18772 + unsigned char val)
18773 +{
18774 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
18775 + PARPORT_CONTROL_AUTOFD |
18776 + PARPORT_CONTROL_INIT |
18777 + PARPORT_CONTROL_SELECT);
18778 +
18779 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
18780 + /* Take this out when drivers have adapted to the newer interface. */
18781 + if (mask & 0x20) {
18782 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
18783 + p->name, p->cad->name,
18784 + (val & 0x20) ? "reverse" : "forward");
18785 + if (val & 0x20)
18786 + parport_splink_data_reverse (p);
18787 + else
18788 + parport_splink_data_forward (p);
18789 + }
18790 +
18791 + /* Restrict mask and val to control lines. */
18792 + mask &= wm;
18793 + val &= wm;
18794 +
18795 + return __parport_splink_frob_control (p, mask, val);
18796 +}
18797 +
18798 +static unsigned char parport_splink_read_status(struct parport *p)
18799 +{
18800 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
18801 + unsigned char *io = (unsigned char *) p->base;
18802 + return *(io+1);
18803 +}
18804 +
18805 +static void parport_splink_inc_use_count(void)
18806 +{
18807 +#ifdef MODULE
18808 + MOD_INC_USE_COUNT;
18809 +#endif
18810 +}
18811 +
18812 +static void parport_splink_dec_use_count(void)
18813 +{
18814 +#ifdef MODULE
18815 + MOD_DEC_USE_COUNT;
18816 +#endif
18817 +}
18818 +
18819 +static struct parport_operations parport_splink_ops =
18820 +{
18821 + parport_splink_write_data,
18822 + parport_splink_read_data,
18823 +
18824 + parport_splink_write_control,
18825 + parport_splink_read_control,
18826 + parport_splink_frob_control,
18827 +
18828 + parport_splink_read_status,
18829 +
18830 + parport_splink_enable_irq,
18831 + parport_splink_disable_irq,
18832 +
18833 + parport_splink_data_forward,
18834 + parport_splink_data_reverse,
18835 +
18836 + parport_splink_init_state,
18837 + parport_splink_save_state,
18838 + parport_splink_restore_state,
18839 +
18840 + parport_splink_inc_use_count,
18841 + parport_splink_dec_use_count,
18842 +
18843 + parport_ieee1284_epp_write_data,
18844 + parport_ieee1284_epp_read_data,
18845 + parport_ieee1284_epp_write_addr,
18846 + parport_ieee1284_epp_read_addr,
18847 +
18848 + parport_ieee1284_ecp_write_data,
18849 + parport_ieee1284_ecp_read_data,
18850 + parport_ieee1284_ecp_write_addr,
18851 +
18852 + parport_ieee1284_write_compat,
18853 + parport_ieee1284_read_nibble,
18854 + parport_ieee1284_read_byte,
18855 +};
18856 +
18857 +/* --- Initialisation code -------------------------------- */
18858 +
18859 +static struct parport *parport_splink_probe_port (unsigned long int base)
18860 +{
18861 + struct parport_pc_private *priv;
18862 + struct parport_operations *ops;
18863 + struct parport *p;
18864 +
18865 + if (check_mem_region(base, 3)) {
18866 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
18867 + return NULL;
18868 + }
18869 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
18870 + if (!priv) {
18871 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
18872 + return NULL;
18873 + }
18874 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
18875 + if (!ops) {
18876 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
18877 + base);
18878 + kfree (priv);
18879 + return NULL;
18880 + }
18881 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
18882 + priv->ctr = 0xc;
18883 + priv->ctr_writable = 0xff;
18884 +
18885 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
18886 + PARPORT_DMA_NONE, ops))) {
18887 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
18888 + base);
18889 + kfree (priv);
18890 + kfree (ops);
18891 + return NULL;
18892 + }
18893 +
18894 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
18895 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
18896 + p->private_data = priv;
18897 +
18898 + parport_proc_register(p);
18899 + request_mem_region (p->base, 3, p->name);
18900 +
18901 + /* Done probing. Now put the port into a sensible start-up state. */
18902 + parport_splink_write_data(p, 0);
18903 + parport_splink_data_forward (p);
18904 +
18905 + /* Now that we've told the sharing engine about the port, and
18906 + found out its characteristics, let the high-level drivers
18907 + know about it. */
18908 + parport_announce_port (p);
18909 +
18910 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
18911 + base);
18912 + return p;
18913 +}
18914 +
18915 +static void parport_splink_unregister_port(struct parport *p) {
18916 + struct parport_pc_private *priv = p->private_data;
18917 + struct parport_operations *ops = p->ops;
18918 +
18919 + if (p->irq != PARPORT_IRQ_NONE)
18920 + free_irq(p->irq, p);
18921 + release_mem_region(p->base, 3);
18922 + parport_proc_unregister(p);
18923 + kfree (priv);
18924 + parport_unregister_port(p);
18925 + kfree (ops);
18926 +}
18927 +
18928 +
18929 +int parport_splink_init(void)
18930 +{
18931 + int ret;
18932 +
18933 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
18934 + parport_splink_setup_interrupt();
18935 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
18936 +
18937 + return ret;
18938 +}
18939 +
18940 +void parport_splink_cleanup(void) {
18941 + struct parport *p = parport_enumerate(), *tmp;
18942 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
18943 + if (p->size) {
18944 + if (p->modes & PARPORT_MODE_PCSPP) {
18945 + while(p) {
18946 + tmp = p->next;
18947 + parport_splink_unregister_port(p);
18948 + p = tmp;
18949 + }
18950 + }
18951 + }
18952 +}
18953 +
18954 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
18955 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
18956 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
18957 +MODULE_LICENSE("GPL");
18958 +
18959 +module_init(parport_splink_init)
18960 +module_exit(parport_splink_cleanup)
18961 +
18962 diff -urN linux.old/drivers/pcmcia/Makefile linux.dev/drivers/pcmcia/Makefile
18963 --- linux.old/drivers/pcmcia/Makefile 2005-08-26 13:41:42.048579600 +0200
18964 +++ linux.dev/drivers/pcmcia/Makefile 2005-08-26 13:44:34.430373584 +0200
18965 @@ -74,6 +74,10 @@
18966 au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o
18967 au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
18968
18969 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
18970 +bcm4710_ss-objs := bcm4710_generic.o
18971 +bcm4710_ss-objs += bcm4710_pcmcia.o
18972 +
18973 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
18974 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
18975 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
18976 @@ -112,5 +116,8 @@
18977 au1x00_ss.o: $(au1000_ss-objs-y)
18978 $(LD) -r -o $@ $(au1000_ss-objs-y)
18979
18980 +bcm4710_ss.o: $(bcm4710_ss-objs)
18981 + $(LD) -r -o $@ $(bcm4710_ss-objs)
18982 +
18983 yenta_socket.o: $(yenta_socket-objs)
18984 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
18985 diff -urN linux.old/drivers/pcmcia/bcm4710_generic.c linux.dev/drivers/pcmcia/bcm4710_generic.c
18986 --- linux.old/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
18987 +++ linux.dev/drivers/pcmcia/bcm4710_generic.c 2005-08-26 13:44:34.432373280 +0200
18988 @@ -0,0 +1,912 @@
18989 +/*
18990 + *
18991 + * bcm47xx pcmcia driver
18992 + *
18993 + * Copyright 2004, Broadcom Corporation
18994 + * All Rights Reserved.
18995 + *
18996 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18997 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18998 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18999 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19000 + *
19001 + * Based on sa1100_generic.c from www.handhelds.org,
19002 + * and au1000_generic.c from oss.sgi.com.
19003 + *
19004 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
19005 + */
19006 +#include <linux/module.h>
19007 +#include <linux/init.h>
19008 +#include <linux/config.h>
19009 +#include <linux/delay.h>
19010 +#include <linux/ioport.h>
19011 +#include <linux/kernel.h>
19012 +#include <linux/tqueue.h>
19013 +#include <linux/timer.h>
19014 +#include <linux/mm.h>
19015 +#include <linux/proc_fs.h>
19016 +#include <linux/version.h>
19017 +#include <linux/types.h>
19018 +#include <linux/vmalloc.h>
19019 +
19020 +#include <pcmcia/version.h>
19021 +#include <pcmcia/cs_types.h>
19022 +#include <pcmcia/cs.h>
19023 +#include <pcmcia/ss.h>
19024 +#include <pcmcia/bulkmem.h>
19025 +#include <pcmcia/cistpl.h>
19026 +#include <pcmcia/bus_ops.h>
19027 +#include "cs_internal.h"
19028 +
19029 +#include <asm/io.h>
19030 +#include <asm/irq.h>
19031 +#include <asm/system.h>
19032 +
19033 +#include <typedefs.h>
19034 +#include <bcm4710.h>
19035 +#include <sbextif.h>
19036 +
19037 +#include "bcm4710pcmcia.h"
19038 +
19039 +#ifdef PCMCIA_DEBUG
19040 +static int pc_debug = PCMCIA_DEBUG;
19041 +#endif
19042 +
19043 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
19044 +
19045 +/* This structure maintains housekeeping state for each socket, such
19046 + * as the last known values of the card detect pins, or the Card Services
19047 + * callback value associated with the socket:
19048 + */
19049 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
19050 +static int socket_count;
19051 +
19052 +
19053 +/* Returned by the low-level PCMCIA interface: */
19054 +static struct pcmcia_low_level *pcmcia_low_level;
19055 +
19056 +/* Event poll timer structure */
19057 +static struct timer_list poll_timer;
19058 +
19059 +
19060 +/* Prototypes for routines which are used internally: */
19061 +
19062 +static int bcm47xx_pcmcia_driver_init(void);
19063 +static void bcm47xx_pcmcia_driver_shutdown(void);
19064 +static void bcm47xx_pcmcia_task_handler(void *data);
19065 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
19066 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
19067 +static struct tq_struct bcm47xx_pcmcia_task;
19068 +
19069 +#ifdef CONFIG_PROC_FS
19070 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
19071 + off_t pos, int count, int *eof, void *data);
19072 +#endif
19073 +
19074 +
19075 +/* Prototypes for operations which are exported to the
19076 + * in-kernel PCMCIA core:
19077 + */
19078 +
19079 +static int bcm47xx_pcmcia_init(unsigned int sock);
19080 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
19081 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
19082 + void (*handler)(void *, unsigned int), void *info);
19083 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
19084 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
19085 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
19086 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
19087 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
19088 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
19089 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
19090 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
19091 +#ifdef CONFIG_PROC_FS
19092 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
19093 +#endif
19094 +
19095 +static struct pccard_operations bcm47xx_pcmcia_operations = {
19096 + bcm47xx_pcmcia_init,
19097 + bcm47xx_pcmcia_suspend,
19098 + bcm47xx_pcmcia_register_callback,
19099 + bcm47xx_pcmcia_inquire_socket,
19100 + bcm47xx_pcmcia_get_status,
19101 + bcm47xx_pcmcia_get_socket,
19102 + bcm47xx_pcmcia_set_socket,
19103 + bcm47xx_pcmcia_get_io_map,
19104 + bcm47xx_pcmcia_set_io_map,
19105 + bcm47xx_pcmcia_get_mem_map,
19106 + bcm47xx_pcmcia_set_mem_map,
19107 +#ifdef CONFIG_PROC_FS
19108 + bcm47xx_pcmcia_proc_setup
19109 +#endif
19110 +};
19111 +
19112 +
19113 +/*
19114 + * bcm47xx_pcmcia_driver_init()
19115 + *
19116 + * This routine performs a basic sanity check to ensure that this
19117 + * kernel has been built with the appropriate board-specific low-level
19118 + * PCMCIA support, performs low-level PCMCIA initialization, registers
19119 + * this socket driver with Card Services, and then spawns the daemon
19120 + * thread which is the real workhorse of the socket driver.
19121 + *
19122 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
19123 + * on the low-level kernel interface.
19124 + *
19125 + * Returns: 0 on success, -1 on error
19126 + */
19127 +static int __init bcm47xx_pcmcia_driver_init(void)
19128 +{
19129 + servinfo_t info;
19130 + struct pcmcia_init pcmcia_init;
19131 + struct pcmcia_state state;
19132 + unsigned int i;
19133 + unsigned long tmp;
19134 +
19135 +
19136 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
19137 +
19138 + CardServices(GetCardServicesInfo, &info);
19139 +
19140 + if (info.Revision != CS_RELEASE_CODE) {
19141 + printk(KERN_ERR "Card Services release codes do not match\n");
19142 + return -1;
19143 + }
19144 +
19145 +#ifdef CONFIG_BCM4710
19146 + pcmcia_low_level=&bcm4710_pcmcia_ops;
19147 +#else
19148 +#error Unsupported Broadcom BCM47XX board.
19149 +#endif
19150 +
19151 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
19152 +
19153 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
19154 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
19155 + return -EIO;
19156 + } else {
19157 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
19158 + }
19159 +
19160 + pcmcia_socket =
19161 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
19162 + GFP_KERNEL);
19163 + memset(pcmcia_socket, 0,
19164 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
19165 + if (!pcmcia_socket) {
19166 + printk(KERN_ERR "Card Services can't get memory \n");
19167 + return -1;
19168 + }
19169 +
19170 + for (i = 0; i < socket_count; i++) {
19171 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
19172 + printk(KERN_ERR "Unable to get PCMCIA status\n");
19173 + return -EIO;
19174 + }
19175 + pcmcia_socket[i].k_state = state;
19176 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
19177 +
19178 + if (i == 0) {
19179 + pcmcia_socket[i].virt_io =
19180 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
19181 + /* Substract ioport base which gets added by in/out */
19182 + pcmcia_socket[i].virt_io -= mips_io_port_base;
19183 + pcmcia_socket[i].phys_attr =
19184 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
19185 + pcmcia_socket[i].phys_mem =
19186 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
19187 + } else {
19188 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
19189 + return 1;
19190 + }
19191 + }
19192 +
19193 + /* Only advertise as many sockets as we can detect: */
19194 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
19195 + printk(KERN_ERR "Unable to register socket service routine\n");
19196 + return -ENXIO;
19197 + }
19198 +
19199 + /* Start the event poll timer.
19200 + * It will reschedule by itself afterwards.
19201 + */
19202 + bcm47xx_pcmcia_poll_event(0);
19203 +
19204 + DEBUG(1, "bcm4710: initialization complete\n");
19205 + return 0;
19206 +
19207 +}
19208 +
19209 +module_init(bcm47xx_pcmcia_driver_init);
19210 +
19211 +
19212 +/*
19213 + * bcm47xx_pcmcia_driver_shutdown()
19214 + *
19215 + * Invokes the low-level kernel service to free IRQs associated with this
19216 + * socket controller and reset GPIO edge detection.
19217 + */
19218 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
19219 +{
19220 + int i;
19221 +
19222 + del_timer_sync(&poll_timer);
19223 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
19224 + pcmcia_low_level->shutdown();
19225 + flush_scheduled_tasks();
19226 + for (i = 0; i < socket_count; i++) {
19227 + if (pcmcia_socket[i].virt_io)
19228 + iounmap((void *)pcmcia_socket[i].virt_io);
19229 + if (pcmcia_socket[i].phys_attr)
19230 + iounmap((void *)pcmcia_socket[i].phys_attr);
19231 + if (pcmcia_socket[i].phys_mem)
19232 + iounmap((void *)pcmcia_socket[i].phys_mem);
19233 + }
19234 + DEBUG(1, "bcm4710: shutdown complete\n");
19235 +}
19236 +
19237 +module_exit(bcm47xx_pcmcia_driver_shutdown);
19238 +
19239 +/*
19240 + * bcm47xx_pcmcia_init()
19241 + * We perform all of the interesting initialization tasks in
19242 + * bcm47xx_pcmcia_driver_init().
19243 + *
19244 + * Returns: 0
19245 + */
19246 +static int bcm47xx_pcmcia_init(unsigned int sock)
19247 +{
19248 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
19249 +
19250 + return 0;
19251 +}
19252 +
19253 +/*
19254 + * bcm47xx_pcmcia_suspend()
19255 + *
19256 + * We don't currently perform any actions on a suspend.
19257 + *
19258 + * Returns: 0
19259 + */
19260 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
19261 +{
19262 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
19263 +
19264 + return 0;
19265 +}
19266 +
19267 +
19268 +/*
19269 + * bcm47xx_pcmcia_events()
19270 + *
19271 + * Helper routine to generate a Card Services event mask based on
19272 + * state information obtained from the kernel low-level PCMCIA layer
19273 + * in a recent (and previous) sampling. Updates `prev_state'.
19274 + *
19275 + * Returns: an event mask for the given socket state.
19276 + */
19277 +static inline unsigned
19278 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
19279 + struct pcmcia_state *prev_state,
19280 + unsigned int mask, unsigned int flags)
19281 +{
19282 + unsigned int events=0;
19283 +
19284 + if (state->bvd1 != prev_state->bvd1) {
19285 +
19286 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
19287 +
19288 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
19289 + }
19290 +
19291 + if (state->bvd2 != prev_state->bvd2) {
19292 +
19293 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
19294 +
19295 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
19296 + }
19297 +
19298 + if (state->detect != prev_state->detect) {
19299 +
19300 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
19301 +
19302 + events |= mask & SS_DETECT;
19303 + }
19304 +
19305 +
19306 + if (state->ready != prev_state->ready) {
19307 +
19308 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
19309 +
19310 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
19311 + }
19312 +
19313 + if (events != 0) {
19314 + DEBUG(2, "events: %s%s%s%s%s\n",
19315 + (events & SS_DETECT) ? "DETECT " : "",
19316 + (events & SS_READY) ? "READY " : "",
19317 + (events & SS_BATDEAD) ? "BATDEAD " : "",
19318 + (events & SS_BATWARN) ? "BATWARN " : "",
19319 + (events & SS_STSCHG) ? "STSCHG " : "");
19320 + }
19321 +
19322 + *prev_state=*state;
19323 + return events;
19324 +}
19325 +
19326 +
19327 +/*
19328 + * bcm47xx_pcmcia_task_handler()
19329 + *
19330 + * Processes serviceable socket events using the "eventd" thread context.
19331 + *
19332 + * Event processing (specifically, the invocation of the Card Services event
19333 + * callback) occurs in this thread rather than in the actual interrupt
19334 + * handler due to the use of scheduling operations in the PCMCIA core.
19335 + */
19336 +static void bcm47xx_pcmcia_task_handler(void *data)
19337 +{
19338 + struct pcmcia_state state;
19339 + int i, events, irq_status;
19340 +
19341 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
19342 +
19343 + for (i = 0; i < socket_count; i++) {
19344 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
19345 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
19346 +
19347 + events = bcm47xx_pcmcia_events(&state,
19348 + &pcmcia_socket[i].k_state,
19349 + pcmcia_socket[i].cs_state.csc_mask,
19350 + pcmcia_socket[i].cs_state.flags);
19351 +
19352 + if (pcmcia_socket[i].handler != NULL) {
19353 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
19354 + events);
19355 + }
19356 + }
19357 +}
19358 +
19359 +static struct tq_struct bcm47xx_pcmcia_task = {
19360 + routine: bcm47xx_pcmcia_task_handler
19361 +};
19362 +
19363 +
19364 +/*
19365 + * bcm47xx_pcmcia_poll_event()
19366 + *
19367 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
19368 + */
19369 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
19370 +{
19371 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
19372 +
19373 + poll_timer.function = bcm47xx_pcmcia_poll_event;
19374 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
19375 + add_timer(&poll_timer);
19376 + schedule_task(&bcm47xx_pcmcia_task);
19377 +}
19378 +
19379 +
19380 +/*
19381 + * bcm47xx_pcmcia_interrupt()
19382 + *
19383 + * Service routine for socket driver interrupts (requested by the
19384 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
19385 + *
19386 + * The actual interrupt-servicing work is performed by
19387 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
19388 + * handling code performs scheduling operations which cannot be
19389 + * executed from within an interrupt context.
19390 + */
19391 +static void
19392 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
19393 +{
19394 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
19395 + schedule_task(&bcm47xx_pcmcia_task);
19396 +}
19397 +
19398 +
19399 +/*
19400 + * bcm47xx_pcmcia_register_callback()
19401 + *
19402 + * Implements the register_callback() operation for the in-kernel
19403 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
19404 + * the function pointer `handler' is not NULL, remember the callback
19405 + * location in the state for `sock', and increment the usage counter
19406 + * for the driver module. (The callback is invoked from the interrupt
19407 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
19408 + * of interesting events.) Otherwise, clear the callback pointer in the
19409 + * socket state and decrement the module usage count.
19410 + *
19411 + * Returns: 0
19412 + */
19413 +static int
19414 +bcm47xx_pcmcia_register_callback(unsigned int sock,
19415 + void (*handler)(void *, unsigned int), void *info)
19416 +{
19417 + if (handler == NULL) {
19418 + pcmcia_socket[sock].handler = NULL;
19419 + MOD_DEC_USE_COUNT;
19420 + } else {
19421 + MOD_INC_USE_COUNT;
19422 + pcmcia_socket[sock].handler = handler;
19423 + pcmcia_socket[sock].handler_info = info;
19424 + }
19425 + return 0;
19426 +}
19427 +
19428 +
19429 +/*
19430 + * bcm47xx_pcmcia_inquire_socket()
19431 + *
19432 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
19433 + * service (formerly SS_InquireSocket in Card Services). Of note is
19434 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
19435 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
19436 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
19437 + * resource database check. (Mapped memory is set up within the socket
19438 + * driver itself.)
19439 + *
19440 + * In conjunction with the STATIC_MAP capability is a new field,
19441 + * `io_offset', recommended by David Hinds. Rather than go through
19442 + * the SetIOMap interface (which is not quite suited for communicating
19443 + * window locations up from the socket driver), we just pass up
19444 + * an offset which is applied to client-requested base I/O addresses
19445 + * in alloc_io_space().
19446 + *
19447 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
19448 + */
19449 +static int
19450 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
19451 +{
19452 + struct pcmcia_irq_info irq_info;
19453 +
19454 + if (sock >= socket_count) {
19455 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
19456 + return -1;
19457 + }
19458 +
19459 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
19460 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
19461 + * general, the mapped * addresses of the PCMCIA memory regions
19462 + * will not be within 0xffff, setting force_low would be
19463 + * undesirable.
19464 + *
19465 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
19466 + * resource database; we instead pass up physical address ranges
19467 + * and allow other parts of Card Services to deal with remapping.
19468 + *
19469 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
19470 + * not 32-bit CardBus devices.
19471 + */
19472 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
19473 +
19474 + irq_info.sock = sock;
19475 + irq_info.irq = -1;
19476 +
19477 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
19478 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
19479 + return -1;
19480 + }
19481 +
19482 + cap->irq_mask = 0;
19483 + cap->map_size = PAGE_SIZE;
19484 + cap->pci_irq = irq_info.irq;
19485 + cap->io_offset = pcmcia_socket[sock].virt_io;
19486 +
19487 + return 0;
19488 +}
19489 +
19490 +
19491 +/*
19492 + * bcm47xx_pcmcia_get_status()
19493 + *
19494 + * Implements the get_status() operation for the in-kernel PCMCIA
19495 + * service (formerly SS_GetStatus in Card Services). Essentially just
19496 + * fills in bits in `status' according to internal driver state or
19497 + * the value of the voltage detect chipselect register.
19498 + *
19499 + * As a debugging note, during card startup, the PCMCIA core issues
19500 + * three set_socket() commands in a row the first with RESET deasserted,
19501 + * the second with RESET asserted, and the last with RESET deasserted
19502 + * again. Following the third set_socket(), a get_status() command will
19503 + * be issued. The kernel is looking for the SS_READY flag (see
19504 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
19505 + *
19506 + * Returns: 0
19507 + */
19508 +static int
19509 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
19510 +{
19511 + struct pcmcia_state state;
19512 +
19513 +
19514 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
19515 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
19516 + return -1;
19517 + }
19518 +
19519 + pcmcia_socket[sock].k_state = state;
19520 +
19521 + *status = state.detect ? SS_DETECT : 0;
19522 +
19523 + *status |= state.ready ? SS_READY : 0;
19524 +
19525 + /* The power status of individual sockets is not available
19526 + * explicitly from the hardware, so we just remember the state
19527 + * and regurgitate it upon request:
19528 + */
19529 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
19530 +
19531 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
19532 + *status |= state.bvd1 ? SS_STSCHG : 0;
19533 + else {
19534 + if (state.bvd1 == 0)
19535 + *status |= SS_BATDEAD;
19536 + else if (state.bvd2 == 0)
19537 + *status |= SS_BATWARN;
19538 + }
19539 +
19540 + *status |= state.vs_3v ? SS_3VCARD : 0;
19541 +
19542 + *status |= state.vs_Xv ? SS_XVCARD : 0;
19543 +
19544 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
19545 + (*status&SS_DETECT)?"DETECT ":"",
19546 + (*status&SS_READY)?"READY ":"",
19547 + (*status&SS_BATDEAD)?"BATDEAD ":"",
19548 + (*status&SS_BATWARN)?"BATWARN ":"",
19549 + (*status&SS_POWERON)?"POWERON ":"",
19550 + (*status&SS_STSCHG)?"STSCHG ":"",
19551 + (*status&SS_3VCARD)?"3VCARD ":"",
19552 + (*status&SS_XVCARD)?"XVCARD ":"");
19553 +
19554 + return 0;
19555 +}
19556 +
19557 +
19558 +/*
19559 + * bcm47xx_pcmcia_get_socket()
19560 + *
19561 + * Implements the get_socket() operation for the in-kernel PCMCIA
19562 + * service (formerly SS_GetSocket in Card Services). Not a very
19563 + * exciting routine.
19564 + *
19565 + * Returns: 0
19566 + */
19567 +static int
19568 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
19569 +{
19570 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
19571 +
19572 + /* This information was given to us in an earlier call to set_socket(),
19573 + * so we're just regurgitating it here:
19574 + */
19575 + *state = pcmcia_socket[sock].cs_state;
19576 + return 0;
19577 +}
19578 +
19579 +
19580 +/*
19581 + * bcm47xx_pcmcia_set_socket()
19582 + *
19583 + * Implements the set_socket() operation for the in-kernel PCMCIA
19584 + * service (formerly SS_SetSocket in Card Services). We more or
19585 + * less punt all of this work and let the kernel handle the details
19586 + * of power configuration, reset, &c. We also record the value of
19587 + * `state' in order to regurgitate it to the PCMCIA core later.
19588 + *
19589 + * Returns: 0
19590 + */
19591 +static int
19592 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
19593 +{
19594 + struct pcmcia_configure configure;
19595 +
19596 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
19597 + "\tVcc %d Vpp %d irq %d\n",
19598 + (state->csc_mask == 0) ? "<NONE>" : "",
19599 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
19600 + (state->csc_mask & SS_READY) ? "READY " : "",
19601 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
19602 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
19603 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
19604 + (state->flags == 0) ? "<NONE>" : "",
19605 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
19606 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
19607 + (state->flags & SS_RESET) ? "RESET " : "",
19608 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
19609 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
19610 + state->Vcc, state->Vpp, state->io_irq);
19611 +
19612 + configure.sock = sock;
19613 + configure.vcc = state->Vcc;
19614 + configure.vpp = state->Vpp;
19615 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
19616 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
19617 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
19618 +
19619 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
19620 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
19621 + return -1;
19622 + }
19623 +
19624 + pcmcia_socket[sock].cs_state = *state;
19625 + return 0;
19626 +}
19627 +
19628 +
19629 +/*
19630 + * bcm47xx_pcmcia_get_io_map()
19631 + *
19632 + * Implements the get_io_map() operation for the in-kernel PCMCIA
19633 + * service (formerly SS_GetIOMap in Card Services). Just returns an
19634 + * I/O map descriptor which was assigned earlier by a set_io_map().
19635 + *
19636 + * Returns: 0 on success, -1 if the map index was out of range
19637 + */
19638 +static int
19639 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
19640 +{
19641 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
19642 +
19643 + if (map->map >= MAX_IO_WIN) {
19644 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19645 + __FUNCTION__, map->map);
19646 + return -1;
19647 + }
19648 +
19649 + *map = pcmcia_socket[sock].io_map[map->map];
19650 + return 0;
19651 +}
19652 +
19653 +
19654 +/*
19655 + * bcm47xx_pcmcia_set_io_map()
19656 + *
19657 + * Implements the set_io_map() operation for the in-kernel PCMCIA
19658 + * service (formerly SS_SetIOMap in Card Services). We configure
19659 + * the map speed as requested, but override the address ranges
19660 + * supplied by Card Services.
19661 + *
19662 + * Returns: 0 on success, -1 on error
19663 + */
19664 +int
19665 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
19666 +{
19667 + unsigned int speed;
19668 + unsigned long start;
19669 +
19670 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
19671 + "\tflags: %s%s%s%s%s%s%s%s\n",
19672 + map->map, map->speed, map->start, map->stop,
19673 + (map->flags == 0) ? "<NONE>" : "",
19674 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
19675 + (map->flags & MAP_16BIT) ? "16BIT " : "",
19676 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
19677 + (map->flags & MAP_0WS) ? "0WS " : "",
19678 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
19679 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
19680 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
19681 +
19682 + if (map->map >= MAX_IO_WIN) {
19683 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19684 + __FUNCTION__, map->map);
19685 + return -1;
19686 + }
19687 +
19688 + if (map->flags & MAP_ACTIVE) {
19689 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
19690 + pcmcia_socket[sock].speed_io = speed;
19691 + }
19692 +
19693 + start = map->start;
19694 +
19695 + if (map->stop == 1) {
19696 + map->stop = PAGE_SIZE - 1;
19697 + }
19698 +
19699 + map->start = pcmcia_socket[sock].virt_io;
19700 + map->stop = map->start + (map->stop - start);
19701 + pcmcia_socket[sock].io_map[map->map] = *map;
19702 + DEBUG(2, "set_io_map %d start %x stop %x\n",
19703 + map->map, map->start, map->stop);
19704 + return 0;
19705 +}
19706 +
19707 +
19708 +/*
19709 + * bcm47xx_pcmcia_get_mem_map()
19710 + *
19711 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
19712 + * service (formerly SS_GetMemMap in Card Services). Just returns a
19713 + * memory map descriptor which was assigned earlier by a
19714 + * set_mem_map() request.
19715 + *
19716 + * Returns: 0 on success, -1 if the map index was out of range
19717 + */
19718 +static int
19719 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
19720 +{
19721 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
19722 +
19723 + if (map->map >= MAX_WIN) {
19724 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19725 + __FUNCTION__, map->map);
19726 + return -1;
19727 + }
19728 +
19729 + *map = pcmcia_socket[sock].mem_map[map->map];
19730 + return 0;
19731 +}
19732 +
19733 +
19734 +/*
19735 + * bcm47xx_pcmcia_set_mem_map()
19736 + *
19737 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
19738 + * service (formerly SS_SetMemMap in Card Services). We configure
19739 + * the map speed as requested, but override the address ranges
19740 + * supplied by Card Services.
19741 + *
19742 + * Returns: 0 on success, -1 on error
19743 + */
19744 +static int
19745 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
19746 +{
19747 + unsigned int speed;
19748 + unsigned long start;
19749 + u_long flags;
19750 +
19751 + if (map->map >= MAX_WIN) {
19752 + printk(KERN_ERR "%s(): map (%d) out of range\n",
19753 + __FUNCTION__, map->map);
19754 + return -1;
19755 + }
19756 +
19757 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
19758 + "\tsys_stop %#lx\n\tcard_start %#x\n"
19759 + "\tflags: %s%s%s%s%s%s%s%s\n",
19760 + map->map, map->speed, map->sys_start, map->sys_stop,
19761 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
19762 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
19763 + (map->flags & MAP_16BIT) ? "16BIT " : "",
19764 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
19765 + (map->flags & MAP_0WS) ? "0WS " : "",
19766 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
19767 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
19768 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
19769 +
19770 + if (map->flags & MAP_ACTIVE) {
19771 + /* When clients issue RequestMap, the access speed is not always
19772 + * properly configured:
19773 + */
19774 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
19775 +
19776 + /* TBD */
19777 + if (map->flags & MAP_ATTRIB) {
19778 + pcmcia_socket[sock].speed_attr = speed;
19779 + } else {
19780 + pcmcia_socket[sock].speed_mem = speed;
19781 + }
19782 + }
19783 +
19784 + save_flags(flags);
19785 + cli();
19786 + start = map->sys_start;
19787 +
19788 + if (map->sys_stop == 0)
19789 + map->sys_stop = PAGE_SIZE - 1;
19790 +
19791 + if (map->flags & MAP_ATTRIB) {
19792 + map->sys_start = pcmcia_socket[sock].phys_attr +
19793 + map->card_start;
19794 + } else {
19795 + map->sys_start = pcmcia_socket[sock].phys_mem +
19796 + map->card_start;
19797 + }
19798 +
19799 + map->sys_stop = map->sys_start + (map->sys_stop - start);
19800 + pcmcia_socket[sock].mem_map[map->map] = *map;
19801 + restore_flags(flags);
19802 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
19803 + map->map, map->sys_start, map->sys_stop,
19804 + map->card_start);
19805 + return 0;
19806 +}
19807 +
19808 +
19809 +#if defined(CONFIG_PROC_FS)
19810 +
19811 +/*
19812 + * bcm47xx_pcmcia_proc_setup()
19813 + *
19814 + * Implements the proc_setup() operation for the in-kernel PCMCIA
19815 + * service (formerly SS_ProcSetup in Card Services).
19816 + *
19817 + * Returns: 0 on success, -1 on error
19818 + */
19819 +static void
19820 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
19821 +{
19822 + struct proc_dir_entry *entry;
19823 +
19824 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
19825 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
19826 + return;
19827 + }
19828 +
19829 + entry->read_proc = bcm47xx_pcmcia_proc_status;
19830 + entry->data = (void *)sock;
19831 +}
19832 +
19833 +
19834 +/*
19835 + * bcm47xx_pcmcia_proc_status()
19836 + *
19837 + * Implements the /proc/bus/pccard/??/status file.
19838 + *
19839 + * Returns: the number of characters added to the buffer
19840 + */
19841 +static int
19842 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
19843 + int count, int *eof, void *data)
19844 +{
19845 + char *p = buf;
19846 + unsigned int sock = (unsigned int)data;
19847 +
19848 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
19849 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
19850 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
19851 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
19852 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
19853 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
19854 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
19855 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
19856 +
19857 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
19858 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
19859 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
19860 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
19861 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
19862 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
19863 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
19864 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
19865 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
19866 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
19867 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
19868 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
19869 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
19870 +
19871 + p += sprintf(p, "mask : %s%s%s%s%s\n",
19872 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
19873 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
19874 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
19875 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
19876 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
19877 +
19878 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
19879 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
19880 + "SS_PWR_AUTO " : "",
19881 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
19882 + "SS_IOCARD " : "",
19883 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
19884 + "SS_RESET " : "",
19885 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
19886 + "SS_SPKR_ENA " : "",
19887 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
19888 + "SS_OUTPUT_ENA " : "");
19889 +
19890 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
19891 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
19892 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
19893 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
19894 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
19895 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
19896 + return p-buf;
19897 +}
19898 +
19899 +
19900 +#endif /* defined(CONFIG_PROC_FS) */
19901 diff -urN linux.old/drivers/pcmcia/bcm4710_pcmcia.c linux.dev/drivers/pcmcia/bcm4710_pcmcia.c
19902 --- linux.old/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
19903 +++ linux.dev/drivers/pcmcia/bcm4710_pcmcia.c 2005-08-26 13:44:34.433373128 +0200
19904 @@ -0,0 +1,266 @@
19905 +/*
19906 + * BCM4710 specific pcmcia routines.
19907 + *
19908 + * Copyright 2004, Broadcom Corporation
19909 + * All Rights Reserved.
19910 + *
19911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19915 + *
19916 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
19917 + */
19918 +#include <linux/module.h>
19919 +#include <linux/init.h>
19920 +#include <linux/config.h>
19921 +#include <linux/delay.h>
19922 +#include <linux/ioport.h>
19923 +#include <linux/kernel.h>
19924 +#include <linux/tqueue.h>
19925 +#include <linux/timer.h>
19926 +#include <linux/mm.h>
19927 +#include <linux/proc_fs.h>
19928 +#include <linux/version.h>
19929 +#include <linux/types.h>
19930 +#include <linux/pci.h>
19931 +
19932 +#include <pcmcia/version.h>
19933 +#include <pcmcia/cs_types.h>
19934 +#include <pcmcia/cs.h>
19935 +#include <pcmcia/ss.h>
19936 +#include <pcmcia/bulkmem.h>
19937 +#include <pcmcia/cistpl.h>
19938 +#include <pcmcia/bus_ops.h>
19939 +#include "cs_internal.h"
19940 +
19941 +#include <asm/io.h>
19942 +#include <asm/irq.h>
19943 +#include <asm/system.h>
19944 +
19945 +
19946 +#include <typedefs.h>
19947 +#include <bcmdevs.h>
19948 +#include <bcm4710.h>
19949 +#include <sbconfig.h>
19950 +#include <sbextif.h>
19951 +
19952 +#include "bcm4710pcmcia.h"
19953 +
19954 +/* Use a static var for irq dev_id */
19955 +static int bcm47xx_pcmcia_dev_id;
19956 +
19957 +/* Do we think we have a card or not? */
19958 +static int bcm47xx_pcmcia_present = 0;
19959 +
19960 +
19961 +static void bcm4710_pcmcia_reset(void)
19962 +{
19963 + extifregs_t *eir;
19964 + unsigned long s;
19965 + uint32 out0, out1, outen;
19966 +
19967 +
19968 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
19969 +
19970 + save_and_cli(s);
19971 +
19972 + /* Use gpio7 to reset the pcmcia slot */
19973 + outen = readl(&eir->gpio[0].outen);
19974 + outen |= BCM47XX_PCMCIA_RESET;
19975 + out0 = readl(&eir->gpio[0].out);
19976 + out0 &= ~(BCM47XX_PCMCIA_RESET);
19977 + out1 = out0 | BCM47XX_PCMCIA_RESET;
19978 +
19979 + writel(out0, &eir->gpio[0].out);
19980 + writel(outen, &eir->gpio[0].outen);
19981 + mdelay(1);
19982 + writel(out1, &eir->gpio[0].out);
19983 + mdelay(1);
19984 + writel(out0, &eir->gpio[0].out);
19985 +
19986 + restore_flags(s);
19987 +}
19988 +
19989 +
19990 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
19991 +{
19992 + struct pci_dev *pdev;
19993 + extifregs_t *eir;
19994 + uint32 outen, intp, intm, tmp;
19995 + uint16 *attrsp;
19996 + int rc = 0, i;
19997 + extern unsigned long bcm4710_cpu_cycle;
19998 +
19999 +
20000 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
20001 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
20002 + return -ENODEV;
20003 + }
20004 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
20005 +
20006 + /* Initialize the pcmcia i/f: 16bit no swap */
20007 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
20008 +
20009 +#ifdef notYet
20010 +
20011 + /* Set the timing for memory accesses */
20012 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
20013 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
20014 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
20015 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
20016 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
20017 +
20018 + /* Set the timing for I/O accesses */
20019 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
20020 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
20021 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
20022 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
20023 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
20024 +
20025 + /* Set the timing for attribute accesses */
20026 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
20027 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
20028 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
20029 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
20030 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
20031 +
20032 +#endif
20033 + /* Make sure gpio0 and gpio5 are inputs */
20034 + outen = readl(&eir->gpio[0].outen);
20035 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
20036 + writel(outen, &eir->gpio[0].outen);
20037 +
20038 + /* Issue a reset to the pcmcia socket */
20039 + bcm4710_pcmcia_reset();
20040 +
20041 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
20042 + /* Setup gpio5 to be the STSCHG interrupt */
20043 + intp = readl(&eir->gpiointpolarity);
20044 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
20045 + intm = readl(&eir->gpiointmask);
20046 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
20047 +#endif
20048 +
20049 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
20050 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
20051 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
20052 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
20053 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
20054 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
20055 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
20056 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
20057 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
20058 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
20059 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
20060 +
20061 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
20062 + /* Request pcmcia interrupt */
20063 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
20064 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
20065 +#endif
20066 +
20067 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
20068 + tmp = readw(&attrsp[0]);
20069 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
20070 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
20071 + bcm47xx_pcmcia_present = 0;
20072 + } else {
20073 + bcm47xx_pcmcia_present = 1;
20074 + }
20075 +
20076 + /* There's only one socket */
20077 + return 1;
20078 +}
20079 +
20080 +static int bcm4710_pcmcia_shutdown(void)
20081 +{
20082 + extifregs_t *eir;
20083 + uint32 intm;
20084 +
20085 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
20086 +
20087 + /* Disable the pcmcia i/f */
20088 + writel(0, &eir->pcmcia_config);
20089 +
20090 + /* Reset gpio's */
20091 + intm = readl(&eir->gpiointmask);
20092 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
20093 +
20094 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
20095 +
20096 + return 0;
20097 +}
20098 +
20099 +static int
20100 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
20101 +{
20102 + extifregs_t *eir;
20103 +
20104 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
20105 +
20106 +
20107 + if (sock != 0) {
20108 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
20109 + return -1;
20110 + }
20111 +
20112 + if (bcm47xx_pcmcia_present) {
20113 + state->detect = 1;
20114 + state->ready = 1;
20115 + state->bvd1 = 1;
20116 + state->bvd2 = 1;
20117 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
20118 + state->vs_3v = 0;
20119 + state->vs_Xv = 0;
20120 + } else {
20121 + state->detect = 0;
20122 + state->ready = 0;
20123 + }
20124 +
20125 + return 1;
20126 +}
20127 +
20128 +
20129 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
20130 +{
20131 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
20132 +
20133 + info->irq = BCM47XX_PCMCIA_IRQ;
20134 +
20135 + return 0;
20136 +}
20137 +
20138 +
20139 +static int
20140 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
20141 +{
20142 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
20143 +
20144 +
20145 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
20146 + configure->vpp, configure->output, configure->speaker, configure->reset);
20147 +
20148 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
20149 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
20150 + configure->vpp);
20151 + }
20152 +
20153 + if (configure->reset) {
20154 + /* Issue a reset to the pcmcia socket */
20155 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
20156 + bcm4710_pcmcia_reset();
20157 + }
20158 +
20159 +
20160 + return 0;
20161 +}
20162 +
20163 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
20164 + bcm4710_pcmcia_init,
20165 + bcm4710_pcmcia_shutdown,
20166 + bcm4710_pcmcia_socket_state,
20167 + bcm4710_pcmcia_get_irq_info,
20168 + bcm4710_pcmcia_configure_socket
20169 +};
20170 +
20171 diff -urN linux.old/drivers/pcmcia/bcm4710pcmcia.h linux.dev/drivers/pcmcia/bcm4710pcmcia.h
20172 --- linux.old/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
20173 +++ linux.dev/drivers/pcmcia/bcm4710pcmcia.h 2005-08-26 13:44:34.433373128 +0200
20174 @@ -0,0 +1,118 @@
20175 +/*
20176 + *
20177 + * bcm47xx pcmcia driver
20178 + *
20179 + * Copyright 2004, Broadcom Corporation
20180 + * All Rights Reserved.
20181 + *
20182 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
20183 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
20184 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
20185 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
20186 + *
20187 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
20188 + * from www.handhelds.org,
20189 + * and au1000_generic.c from oss.sgi.com.
20190 + *
20191 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
20192 + */
20193 +
20194 +#if !defined(_BCM4710PCMCIA_H)
20195 +#define _BCM4710PCMCIA_H
20196 +
20197 +#include <pcmcia/cs_types.h>
20198 +#include <pcmcia/ss.h>
20199 +#include <pcmcia/bulkmem.h>
20200 +#include <pcmcia/cistpl.h>
20201 +#include "cs_internal.h"
20202 +
20203 +
20204 +/* The 47xx can only support one socket */
20205 +#define BCM47XX_PCMCIA_MAX_SOCK 1
20206 +
20207 +/* In the bcm947xx gpio's are used for some pcmcia functions */
20208 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
20209 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
20210 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
20211 +
20212 +#define BCM47XX_PCMCIA_IRQ 2
20213 +
20214 +/* The socket driver actually works nicely in interrupt-driven form,
20215 + * so the (relatively infrequent) polling is "just to be sure."
20216 + */
20217 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
20218 +
20219 +#define BCM47XX_PCMCIA_IO_SPEED (255)
20220 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
20221 +
20222 +
20223 +struct pcmcia_state {
20224 + unsigned detect: 1,
20225 + ready: 1,
20226 + bvd1: 1,
20227 + bvd2: 1,
20228 + wrprot: 1,
20229 + vs_3v: 1,
20230 + vs_Xv: 1;
20231 +};
20232 +
20233 +
20234 +struct pcmcia_configure {
20235 + unsigned sock: 8,
20236 + vcc: 8,
20237 + vpp: 8,
20238 + output: 1,
20239 + speaker: 1,
20240 + reset: 1;
20241 +};
20242 +
20243 +struct pcmcia_irq_info {
20244 + unsigned int sock;
20245 + unsigned int irq;
20246 +};
20247 +
20248 +/* This structure encapsulates per-socket state which we might need to
20249 + * use when responding to a Card Services query of some kind.
20250 + */
20251 +struct bcm47xx_pcmcia_socket {
20252 + socket_state_t cs_state;
20253 + struct pcmcia_state k_state;
20254 + unsigned int irq;
20255 + void (*handler)(void *, unsigned int);
20256 + void *handler_info;
20257 + pccard_io_map io_map[MAX_IO_WIN];
20258 + pccard_mem_map mem_map[MAX_WIN];
20259 + ioaddr_t virt_io, phys_attr, phys_mem;
20260 + unsigned short speed_io, speed_attr, speed_mem;
20261 +};
20262 +
20263 +struct pcmcia_init {
20264 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
20265 +};
20266 +
20267 +struct pcmcia_low_level {
20268 + int (*init)(struct pcmcia_init *);
20269 + int (*shutdown)(void);
20270 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
20271 + int (*get_irq_info)(struct pcmcia_irq_info *);
20272 + int (*configure_socket)(const struct pcmcia_configure *);
20273 +};
20274 +
20275 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
20276 +
20277 +/* I/O pins replacing memory pins
20278 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
20279 + *
20280 + * These signals change meaning when going from memory-only to
20281 + * memory-or-I/O interface:
20282 + */
20283 +#define iostschg bvd1
20284 +#define iospkr bvd2
20285 +
20286 +
20287 +/*
20288 + * Declaration for implementation specific low_level operations.
20289 + */
20290 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
20291 +
20292 +#endif /* !defined(_BCM4710PCMCIA_H) */
20293 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
20294 --- linux.old/include/asm-mips/bootinfo.h 2005-08-26 13:41:42.329536888 +0200
20295 +++ linux.dev/include/asm-mips/bootinfo.h 2005-08-26 13:44:34.447371000 +0200
20296 @@ -37,6 +37,7 @@
20297 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
20298 #define MACH_GROUP_LASAT 21
20299 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
20300 +#define MACH_GROUP_BRCM 23 /* Broadcom */
20301
20302 /*
20303 * Valid machtype values for group unknown (low order halfword of mips_machtype)
20304 @@ -197,6 +198,15 @@
20305 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
20306
20307 /*
20308 + * Valid machtypes for group Broadcom
20309 + */
20310 +#define MACH_BCM93725 0
20311 +#define MACH_BCM93725_VJ 1
20312 +#define MACH_BCM93730 2
20313 +#define MACH_BCM947XX 3
20314 +#define MACH_BCM933XX 4
20315 +
20316 +/*
20317 * Valid machtype for group TITAN
20318 */
20319 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
20320 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
20321 --- linux.old/include/asm-mips/cpu.h 2005-01-19 15:10:11.000000000 +0100
20322 +++ linux.dev/include/asm-mips/cpu.h 2005-08-26 13:44:34.455369784 +0200
20323 @@ -22,6 +22,11 @@
20324 spec.
20325 */
20326
20327 +#define PRID_COPT_MASK 0xff000000
20328 +#define PRID_COMP_MASK 0x00ff0000
20329 +#define PRID_IMP_MASK 0x0000ff00
20330 +#define PRID_REV_MASK 0x000000ff
20331 +
20332 #define PRID_COMP_LEGACY 0x000000
20333 #define PRID_COMP_MIPS 0x010000
20334 #define PRID_COMP_BROADCOM 0x020000
20335 @@ -58,6 +63,7 @@
20336 #define PRID_IMP_RM7000 0x2700
20337 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
20338 #define PRID_IMP_RM9000 0x3400
20339 +#define PRID_IMP_BCM4710 0x4000
20340 #define PRID_IMP_R5432 0x5400
20341 #define PRID_IMP_R5500 0x5500
20342 #define PRID_IMP_4KC 0x8000
20343 @@ -66,10 +72,16 @@
20344 #define PRID_IMP_4KEC 0x8400
20345 #define PRID_IMP_4KSC 0x8600
20346 #define PRID_IMP_25KF 0x8800
20347 +#define PRID_IMP_BCM3302 0x9000
20348 +#define PRID_IMP_BCM3303 0x9100
20349 #define PRID_IMP_24K 0x9300
20350
20351 #define PRID_IMP_UNKNOWN 0xff00
20352
20353 +#define BCM330X(id) \
20354 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
20355 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
20356 +
20357 /*
20358 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
20359 */
20360 @@ -174,7 +186,9 @@
20361 #define CPU_AU1550 57
20362 #define CPU_24K 58
20363 #define CPU_AU1200 59
20364 -#define CPU_LAST 59
20365 +#define CPU_BCM4710 60
20366 +#define CPU_BCM3302 61
20367 +#define CPU_LAST 61
20368
20369 /*
20370 * ISA Level encodings
20371 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
20372 --- linux.old/include/asm-mips/r4kcache.h 2004-02-18 14:36:32.000000000 +0100
20373 +++ linux.dev/include/asm-mips/r4kcache.h 2005-08-26 13:44:34.457369480 +0200
20374 @@ -567,4 +567,17 @@
20375 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
20376 }
20377
20378 +extern inline void fill_icache_line(unsigned long addr)
20379 +{
20380 + __asm__ __volatile__(
20381 + ".set noreorder\n\t"
20382 + ".set mips3\n\t"
20383 + "cache %1, (%0)\n\t"
20384 + ".set mips0\n\t"
20385 + ".set reorder"
20386 + :
20387 + : "r" (addr),
20388 + "i" (Fill));
20389 +}
20390 +
20391 #endif /* __ASM_R4KCACHE_H */
20392 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
20393 --- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
20394 +++ linux.dev/include/asm-mips/serial.h 2005-08-26 13:44:34.459369176 +0200
20395 @@ -223,6 +223,13 @@
20396 #define TXX927_SERIAL_PORT_DEFNS
20397 #endif
20398
20399 +#ifdef CONFIG_BCM947XX
20400 +/* reserve 4 ports to be configured at runtime */
20401 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
20402 +#else
20403 +#define BCM947XX_SERIAL_PORT_DEFNS
20404 +#endif
20405 +
20406 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
20407 #define STD_SERIAL_PORT_DEFNS \
20408 /* UART CLK PORT IRQ FLAGS */ \
20409 @@ -470,6 +477,7 @@
20410 #define SERIAL_PORT_DFNS \
20411 ATLAS_SERIAL_PORT_DEFNS \
20412 AU1000_SERIAL_PORT_DEFNS \
20413 + BCM947XX_SERIAL_PORT_DEFNS \
20414 COBALT_SERIAL_PORT_DEFNS \
20415 DDB5477_SERIAL_PORT_DEFNS \
20416 EV96100_SERIAL_PORT_DEFNS \
20417 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
20418 --- linux.old/init/do_mounts.c 2005-08-26 13:41:42.608494480 +0200
20419 +++ linux.dev/init/do_mounts.c 2005-08-26 13:44:34.481365832 +0200
20420 @@ -254,7 +254,13 @@
20421 { "ftlb", 0x2c08 },
20422 { "ftlc", 0x2c10 },
20423 { "ftld", 0x2c18 },
20424 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
20425 { "mtdblock", 0x1f00 },
20426 + { "mtdblock0",0x1f00 },
20427 + { "mtdblock1",0x1f01 },
20428 + { "mtdblock2",0x1f02 },
20429 + { "mtdblock3",0x1f03 },
20430 +#endif
20431 { "nb", 0x2b00 },
20432 { NULL, 0 }
20433 };
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