target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch

   1 --- a/arch/mips/ath79/mach-db120.c
   2 +++ b/arch/mips/ath79/mach-db120.c
   3 @@ -2,7 +2,7 @@
   4   * Atheros DB120 reference board support
   5   *
   6   * Copyright (c) 2011 Qualcomm Atheros
   7 - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
   8 + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   9   *
  10   * All rights reserved.
  11   *
  12 @@ -38,16 +38,25 @@
  13   */
  14
  15  #include <linux/pci.h>
  16 +#include <linux/phy.h>
  17 +#include <linux/platform_device.h>
  18  #include <linux/ath9k_platform.h>
  19 +#include <linux/ar8216_platform.h>
  20
  21 -#include "machtypes.h"
  22 +#include <asm/mach-ath79/ar71xx_regs.h>
  23 +
  24 +#include "common.h"
  25 +#include "dev-ap9x-pci.h"
  26 +#include "dev-eth.h"
  27  #include "dev-gpio-buttons.h"
  28  #include "dev-leds-gpio.h"
  29 +#include "dev-m25p80.h"
  30  #include "dev-spi.h"
  31  #include "dev-usb.h"
  32  #include "dev-wmac.h"
  33 -#include "pci.h"
  34 +#include "machtypes.h"
  35
  36 +#define DB120_GPIO_LED_USB             11
  37  #define DB120_GPIO_LED_WLAN_5G         12
  38  #define DB120_GPIO_LED_WLAN_2G         13
  39  #define DB120_GPIO_LED_STATUS          14
  40 @@ -58,8 +67,10 @@
  41  #define DB120_KEYS_POLL_INTERVAL       20      /* msecs */
  42  #define DB120_KEYS_DEBOUNCE_INTERVAL   (3 * DB120_KEYS_POLL_INTERVAL)
  43
  44 -#define DB120_WMAC_CALDATA_OFFSET 0x1000
  45 -#define DB120_PCIE_CALDATA_OFFSET 0x5000
  46 +#define DB120_MAC0_OFFSET              0
  47 +#define DB120_MAC1_OFFSET              6
  48 +#define DB120_WMAC_CALDATA_OFFSET      0x1000
  49 +#define DB120_PCIE_CALDATA_OFFSET      0x5000
  50
  51  static struct gpio_led db120_leds_gpio[] __initdata = {
  52         {
  53 @@ -82,6 +93,11 @@ static struct gpio_led db120_leds_gpio[]
  54                 .gpio           = DB120_GPIO_LED_WLAN_2G,
  55                 .active_low     = 1,
  56         },
  57 +       {
  58 +               .name           = "db120:green:usb",
  59 +               .gpio           = DB120_GPIO_LED_USB,
  60 +               .active_low     = 1,
  61 +       }
  62  };
  63
  64  static struct gpio_keys_button db120_gpio_keys[] __initdata = {
  65 @@ -95,66 +111,90 @@ static struct gpio_keys_button db120_gpi
  66         },
  67  };
  68
  69 -static struct ath79_spi_controller_data db120_spi0_data = {
  70 -       .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  71 -       .cs_line = 0,
  72 +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
  73 +       .mode = AR8327_PAD_MAC_RGMII,
  74 +       .txclk_delay_en = true,
  75 +       .rxclk_delay_en = true,
  76 +       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  77 +       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  78  };
  79
  80 -static struct spi_board_info db120_spi_info[] = {
  81 -       {
  82 -               .bus_num        = 0,
  83 -               .chip_select    = 0,
  84 -               .max_speed_hz   = 25000000,
  85 -               .modalias       = "s25sl064a",
  86 -               .controller_data = &db120_spi0_data,
  87 +static struct ar8327_platform_data db120_ar8327_data = {
  88 +       .pad0_cfg = &db120_ar8327_pad0_cfg,
  89 +       .cpuport_cfg = {
  90 +               .force_link = 1,
  91 +               .speed = AR8327_PORT_SPEED_1000,
  92 +               .duplex = 1,
  93 +               .txpause = 1,
  94 +               .rxpause = 1,
  95         }
  96  };
  97
  98 -static struct ath79_spi_platform_data db120_spi_data = {
  99 -       .bus_num        = 0,
 100 -       .num_chipselect = 1,
 101 +static struct mdio_board_info db120_mdio0_info[] = {
 102 +       {
 103 +               .bus_id = "ag71xx-mdio.0",
 104 +               .phy_addr = 0,
 105 +               .platform_data = &db120_ar8327_data,
 106 +       },
 107  };
 108
 109 -#ifdef CONFIG_PCI
 110 -static struct ath9k_platform_data db120_ath9k_data;
 111 -
 112 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
 113 +static void __init db120_gmac_setup(void)
 114  {
 115 -       switch (PCI_SLOT(dev->devfn)) {
 116 -       case 0:
 117 -               dev->dev.platform_data = &db120_ath9k_data;
 118 -               break;
 119 -       }
 120 +       void __iomem *base;
 121 +       u32 t;
 122
 123 -       return 0;
 124 -}
 125 +       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 126
 127 -static void __init db120_pci_init(u8 *eeprom)
 128 -{
 129 -       memcpy(db120_ath9k_data.eeprom_data, eeprom,
 130 -              sizeof(db120_ath9k_data.eeprom_data));
 131 +       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 132 +       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
 133 +              AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
 134 +       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
 135 +
 136 +       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 137
 138 -       ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 139 -       ath79_register_pci();
 140 +       iounmap(base);
 141  }
 142 -#else
 143 -static inline void db120_pci_init(void) {}
 144 -#endif /* CONFIG_PCI */
 145
 146  static void __init db120_setup(void)
 147  {
 148         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 149
 150 +       ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
 151 +       ath79_register_m25p80(NULL);
 152 +
 153         ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
 154                                  db120_leds_gpio);
 155         ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
 156                                         ARRAY_SIZE(db120_gpio_keys),
 157                                         db120_gpio_keys);
 158 -       ath79_register_spi(&db120_spi_data, db120_spi_info,
 159 -                          ARRAY_SIZE(db120_spi_info));
 160         ath79_register_usb();
 161         ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
 162 -       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 163 +       ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
 164 +
 165 +       db120_gmac_setup();
 166 +
 167 +       ath79_register_mdio(1, 0x0);
 168 +       ath79_register_mdio(0, 0x0);
 169 +
 170 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
 171 +
 172 +       mdiobus_register_board_info(db120_mdio0_info,
 173 +                                   ARRAY_SIZE(db120_mdio0_info));
 174 +
 175 +       /* GMAC0 is connected to an AR8327 switch */
 176 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 177 +       ath79_eth0_data.phy_mask = BIT(0);
 178 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 179 +       ath79_eth0_pll_data.pll_1000 = 0x06000000;
 180 +       ath79_register_eth(0);
 181 +
 182 +       /* GMAC1 is connected to the internal switch */
 183 +       ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
 184 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 185 +       ath79_eth1_data.speed = SPEED_1000;
 186 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 187 +
 188 +       ath79_register_eth(1);
 189  }
 190
 191  MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 192 --- a/arch/mips/ath79/Kconfig
 193 +++ b/arch/mips/ath79/Kconfig
 194 @@ -31,9 +31,11 @@ config ATH79_MACH_AP81
 195  config ATH79_MACH_DB120
 196         bool "Atheros DB120 reference board"
 197         select SOC_AR934X
 198 +       select ATH79_DEV_AP9X_PCI if PCI
 199 +       select ATH79_DEV_ETH
 200         select ATH79_DEV_GPIO_BUTTONS
 201         select ATH79_DEV_LEDS_GPIO
 202 -       select ATH79_DEV_SPI
 203 +       select ATH79_DEV_M25P80
 204         select ATH79_DEV_USB
 205         select ATH79_DEV_WMAC
 206         help