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[rb532] refresh patches
[openwrt.git] / target / linux / ixp4xx / patches-2.6.28 / 210-npe_hss.patch
1 --- a/drivers/net/wan/Kconfig
2 +++ b/drivers/net/wan/Kconfig
3 @@ -333,6 +333,15 @@ config DSCC4_PCI_RST
4
5 Say Y if your card supports this feature.
6
7 +config IXP4XX_HSS
8 + tristate "IXP4xx HSS (synchronous serial port) support"
9 + depends on HDLC && ARM && ARCH_IXP4XX
10 + select IXP4XX_NPE
11 + select IXP4XX_QMGR
12 + help
13 + Say Y here if you want to use built-in HSS ports
14 + on IXP4xx processor.
15 +
16 config DLCI
17 tristate "Frame Relay DLCI support"
18 ---help---
19 --- a/drivers/net/wan/Makefile
20 +++ b/drivers/net/wan/Makefile
21 @@ -41,6 +41,7 @@ obj-$(CONFIG_C101) += c101.o
22 obj-$(CONFIG_WANXL) += wanxl.o
23 obj-$(CONFIG_PCI200SYN) += pci200syn.o
24 obj-$(CONFIG_PC300TOO) += pc300too.o
25 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
26
27 clean-files := wanxlfw.inc
28 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
29 --- /dev/null
30 +++ b/drivers/net/wan/ixp4xx_hss.c
31 @@ -0,0 +1,2886 @@
32 +/*
33 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
34 + *
35 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
36 + *
37 + * This program is free software; you can redistribute it and/or modify it
38 + * under the terms of version 2 of the GNU General Public License
39 + * as published by the Free Software Foundation.
40 + */
41 +
42 +#include <linux/bitops.h>
43 +#include <linux/cdev.h>
44 +#include <linux/dma-mapping.h>
45 +#include <linux/dmapool.h>
46 +#include <linux/fs.h>
47 +#include <linux/io.h>
48 +#include <linux/kernel.h>
49 +#include <linux/hdlc.h>
50 +#include <linux/platform_device.h>
51 +#include <linux/poll.h>
52 +#include <asm/arch/npe.h>
53 +#include <asm/arch/qmgr.h>
54 +
55 +#define DEBUG_QUEUES 0
56 +#define DEBUG_DESC 0
57 +#define DEBUG_RX 0
58 +#define DEBUG_TX 0
59 +#define DEBUG_PKT_BYTES 0
60 +#define DEBUG_CLOSE 0
61 +#define DEBUG_FRAMER 0
62 +
63 +#define DRV_NAME "ixp4xx_hss"
64 +
65 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
66 +#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
67 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
68 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
69 +
70 +#define RX_DESCS 16 /* also length of all RX queues */
71 +#define TX_DESCS 16 /* also length of all TX queues */
72 +
73 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
74 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
75 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
76 +#define HSS_COUNT 2
77 +#define MIN_FRAME_SIZE 16 /* bits */
78 +#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
79 +#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
80 +#define MAX_CHAN_DEVICES 32
81 +#define CHANNEL_HDLC 0xFE
82 +#define CHANNEL_UNUSED 0xFF
83 +
84 +#define NAPI_WEIGHT 16
85 +#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
86 +#define CHAN_RX_FRAMES 64
87 +#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
88 +#define CHAN_TX_LIST_FRAMES 16 /* bytes/channel per list, 16 - 48 */
89 +#define CHAN_TX_LISTS 8
90 +#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
91 +#define CHAN_QUEUE_LEN 16 /* minimum possible */
92 +
93 +
94 +/* Queue IDs */
95 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
96 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
97 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
98 +#define HSS0_PKT_TX1_QUEUE 15
99 +#define HSS0_PKT_TX2_QUEUE 16
100 +#define HSS0_PKT_TX3_QUEUE 17
101 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
102 +#define HSS0_PKT_RXFREE1_QUEUE 19
103 +#define HSS0_PKT_RXFREE2_QUEUE 20
104 +#define HSS0_PKT_RXFREE3_QUEUE 21
105 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
106 +
107 +#define HSS1_CHL_RXTRIG_QUEUE 10
108 +#define HSS1_PKT_RX_QUEUE 0
109 +#define HSS1_PKT_TX0_QUEUE 5
110 +#define HSS1_PKT_TX1_QUEUE 6
111 +#define HSS1_PKT_TX2_QUEUE 7
112 +#define HSS1_PKT_TX3_QUEUE 8
113 +#define HSS1_PKT_RXFREE0_QUEUE 1
114 +#define HSS1_PKT_RXFREE1_QUEUE 2
115 +#define HSS1_PKT_RXFREE2_QUEUE 3
116 +#define HSS1_PKT_RXFREE3_QUEUE 4
117 +#define HSS1_PKT_TXDONE_QUEUE 9
118 +
119 +#define NPE_PKT_MODE_HDLC 0
120 +#define NPE_PKT_MODE_RAW 1
121 +#define NPE_PKT_MODE_56KMODE 2
122 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
123 +
124 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
125 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
126 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
127 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
128 +
129 +
130 +/* hss_config, PCRs */
131 +/* Frame sync sampling, default = active low */
132 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
133 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
134 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
135 +
136 +/* Frame sync pin: input (default) or output generated off a given clk edge */
137 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
138 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
139 +
140 +/* Frame and data clock sampling on edge, default = falling */
141 +#define PCR_FCLK_EDGE_RISING 0x08000000
142 +#define PCR_DCLK_EDGE_RISING 0x04000000
143 +
144 +/* Clock direction, default = input */
145 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
146 +
147 +/* Generate/Receive frame pulses, default = enabled */
148 +#define PCR_FRM_PULSE_DISABLED 0x01000000
149 +
150 + /* Data rate is full (default) or half the configured clk speed */
151 +#define PCR_HALF_CLK_RATE 0x00200000
152 +
153 +/* Invert data between NPE and HSS FIFOs? (default = no) */
154 +#define PCR_DATA_POLARITY_INVERT 0x00100000
155 +
156 +/* TX/RX endianness, default = LSB */
157 +#define PCR_MSB_ENDIAN 0x00080000
158 +
159 +/* Normal (default) / open drain mode (TX only) */
160 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
161 +
162 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
163 +#define PCR_SOF_NO_FBIT 0x00020000
164 +
165 +/* Drive data pins? */
166 +#define PCR_TX_DATA_ENABLE 0x00010000
167 +
168 +/* Voice 56k type: drive the data pins low (default), high, high Z */
169 +#define PCR_TX_V56K_HIGH 0x00002000
170 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
171 +
172 +/* Unassigned type: drive the data pins low (default), high, high Z */
173 +#define PCR_TX_UNASS_HIGH 0x00000800
174 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
175 +
176 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
177 +#define PCR_TX_FB_HIGH_IMP 0x00000400
178 +
179 +/* 56k data endiannes - which bit unused: high (default) or low */
180 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
181 +
182 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
183 +#define PCR_TX_56KS_56K_DATA 0x00000100
184 +
185 +/* hss_config, cCR */
186 +/* Number of packetized clients, default = 1 */
187 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
188 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
189 +
190 +/* default = no loopback */
191 +#define CCR_LOOPBACK 0x02000000
192 +
193 +/* HSS number, default = 0 (first) */
194 +#define CCR_SECOND_HSS 0x01000000
195 +
196 +
197 +/* hss_config, clkCR: main:10, num:10, denom:12 */
198 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
199 +
200 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
201 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
202 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
203 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
204 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
205 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
206 +
207 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
208 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
209 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
210 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
211 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
212 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
213 +
214 +
215 +/* hss_config, LUT entries */
216 +#define TDMMAP_UNASSIGNED 0
217 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
218 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
219 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
220 +
221 +/* offsets into HSS config */
222 +#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
223 +#define HSS_CONFIG_RX_PCR 0x04
224 +#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
225 +#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
226 +#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
227 +#define HSS_CONFIG_RX_FCR 0x14
228 +#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
229 +#define HSS_CONFIG_RX_LUT 0x38
230 +
231 +
232 +/* NPE command codes */
233 +/* writes the ConfigWord value to the location specified by offset */
234 +#define PORT_CONFIG_WRITE 0x40
235 +
236 +/* triggers the NPE to load the contents of the configuration table */
237 +#define PORT_CONFIG_LOAD 0x41
238 +
239 +/* triggers the NPE to return an HssErrorReadResponse message */
240 +#define PORT_ERROR_READ 0x42
241 +
242 +/* reset NPE internal status and enable the HssChannelized operation */
243 +#define CHAN_FLOW_ENABLE 0x43
244 +#define CHAN_FLOW_DISABLE 0x44
245 +#define CHAN_IDLE_PATTERN_WRITE 0x45
246 +#define CHAN_NUM_CHANS_WRITE 0x46
247 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
248 +#define CHAN_RX_BUF_CFG_WRITE 0x48
249 +#define CHAN_TX_BLK_CFG_WRITE 0x49
250 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
251 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
252 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
253 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
254 +
255 +/* downloads the gainWord value for a timeslot switching channel associated
256 + with bypassNum */
257 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
258 +
259 +/* triggers the NPE to reset internal status and enable the HssPacketized
260 + operation for the flow specified by pPipe */
261 +#define PKT_PIPE_FLOW_ENABLE 0x50
262 +#define PKT_PIPE_FLOW_DISABLE 0x51
263 +#define PKT_NUM_PIPES_WRITE 0x52
264 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
265 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
266 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
267 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
268 +#define PKT_PIPE_MODE_WRITE 0x57
269 +
270 +/* HDLC packet status values - desc->status */
271 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
272 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
273 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
274 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
275 + this packet (if buf_len < pkt_len) */
276 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
277 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
278 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
279 +
280 +
281 +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
282 +enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
283 +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
284 +
285 +#ifdef __ARMEB__
286 +typedef struct sk_buff buffer_t;
287 +#define free_buffer dev_kfree_skb
288 +#define free_buffer_irq dev_kfree_skb_irq
289 +#else
290 +typedef void buffer_t;
291 +#define free_buffer kfree
292 +#define free_buffer_irq kfree
293 +#endif
294 +
295 +struct chan_device {
296 + struct cdev cdev;
297 + struct device *dev;
298 + struct port *port;
299 + unsigned int open_count, excl_open;
300 + unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
301 + unsigned long errors_bitmap;
302 + u8 id, chan_count;
303 + u8 log_channels[MAX_CHANNELS];
304 +};
305 +
306 +struct port {
307 + struct device *dev;
308 + struct npe *npe;
309 + struct net_device *netdev;
310 + struct napi_struct napi;
311 + struct hss_plat_info *plat;
312 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
313 + struct desc *desc_tab; /* coherent */
314 + u32 desc_tab_phys;
315 + unsigned int id;
316 + atomic_t chan_tx_irq_number, chan_rx_irq_number;
317 + wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
318 + u8 hdlc_cfg;
319 +
320 + /* the following fields must be protected by npe_lock */
321 + enum mode mode;
322 + unsigned int clock_type, clock_rate, loopback;
323 + unsigned int frame_size, frame_sync_offset;
324 +
325 + struct chan_device *chan_devices[MAX_CHAN_DEVICES];
326 + u8 *chan_buf;
327 + u32 chan_tx_buf_phys, chan_rx_buf_phys;
328 + unsigned int chan_open_count, hdlc_open;
329 + unsigned int chan_started, initialized, just_set_offset;
330 + enum alignment aligned, carrier;
331 + unsigned int chan_last_rx, chan_last_tx;
332 + /* assigned channels, may be invalid with given frame length or mode */
333 + u8 channels[MAX_CHANNELS];
334 + int msg_count;
335 +};
336 +
337 +/* NPE message structure */
338 +struct msg {
339 +#ifdef __ARMEB__
340 + u8 cmd, unused, hss_port, index;
341 + union {
342 + struct { u8 data8a, data8b, data8c, data8d; };
343 + struct { u16 data16a, data16b; };
344 + struct { u32 data32; };
345 + };
346 +#else
347 + u8 index, hss_port, unused, cmd;
348 + union {
349 + struct { u8 data8d, data8c, data8b, data8a; };
350 + struct { u16 data16b, data16a; };
351 + struct { u32 data32; };
352 + };
353 +#endif
354 +};
355 +
356 +/* HDLC packet descriptor */
357 +struct desc {
358 + u32 next; /* pointer to next buffer, unused */
359 +
360 +#ifdef __ARMEB__
361 + u16 buf_len; /* buffer length */
362 + u16 pkt_len; /* packet length */
363 + u32 data; /* pointer to data buffer in RAM */
364 + u8 status;
365 + u8 error_count;
366 + u16 __reserved;
367 +#else
368 + u16 pkt_len; /* packet length */
369 + u16 buf_len; /* buffer length */
370 + u32 data; /* pointer to data buffer in RAM */
371 + u16 __reserved;
372 + u8 error_count;
373 + u8 status;
374 +#endif
375 + u32 __reserved1[4];
376 +};
377 +
378 +
379 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
380 + (n) * sizeof(struct desc))
381 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
382 +
383 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
384 + ((n) + RX_DESCS) * sizeof(struct desc))
385 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
386 +
387 +#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES)
388 +#define chan_tx_lists_len(port) (port->frame_size / 8 * CHAN_TX_LISTS * \
389 + sizeof(u32))
390 +#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES)
391 +
392 +#define chan_tx_buf(port) ((port)->chan_buf)
393 +#define chan_tx_lists(port) (chan_tx_buf(port) + chan_tx_buf_len(port))
394 +#define chan_rx_buf(port) (chan_tx_lists(port) + chan_tx_lists_len(port))
395 +
396 +#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys + \
397 + chan_tx_buf_len(port))
398 +
399 +static int hss_prepare_chan(struct port *port);
400 +void hss_chan_stop(struct port *port);
401 +
402 +/*****************************************************************************
403 + * global variables
404 + ****************************************************************************/
405 +
406 +static struct class *hss_class;
407 +static int chan_major;
408 +static int ports_open;
409 +static struct dma_pool *dma_pool;
410 +static spinlock_t npe_lock;
411 +
412 +static const struct {
413 + int tx, txdone, rx, rxfree, chan;
414 +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
415 + HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
416 + {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
417 + HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
418 +};
419 +
420 +/*****************************************************************************
421 + * utility functions
422 + ****************************************************************************/
423 +
424 +static inline struct port* dev_to_port(struct net_device *dev)
425 +{
426 + return dev_to_hdlc(dev)->priv;
427 +}
428 +
429 +static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
430 +{
431 + return container_of(inode->i_cdev, struct chan_device, cdev);
432 +}
433 +
434 +#ifndef __ARMEB__
435 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
436 +{
437 + int i;
438 + for (i = 0; i < cnt; i++)
439 + dest[i] = swab32(src[i]);
440 +}
441 +#endif
442 +
443 +static int get_number(const char **buf, size_t *len, unsigned int *ptr,
444 + unsigned int min, unsigned int max)
445 +{
446 + char *endp;
447 + unsigned long val = simple_strtoul(*buf, &endp, 10);
448 +
449 + if (endp == *buf || endp - *buf > *len || val < min || val > max)
450 + return -EINVAL;
451 + *len -= endp - *buf;
452 + *buf = endp;
453 + *ptr = val;
454 + return 0;
455 +}
456 +
457 +static int parse_channels(const char **buf, size_t *len, u8 *channels)
458 +{
459 + unsigned int ch, next = 0;
460 +
461 + if (*len && (*buf)[*len - 1] == '\n')
462 + (*len)--;
463 +
464 + memset(channels, 0, MAX_CHANNELS);
465 +
466 + if (!*len)
467 + return 0;
468 +
469 + /* Format: "A,B-C,...", A > B > C */
470 + while (1) {
471 + if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
472 + return -EINVAL;
473 + channels[ch] = 1;
474 + next = ch + 1;
475 + if (!*len)
476 + break;
477 + if (**buf == ',') {
478 + (*buf)++;
479 + (*len)--;
480 + continue;
481 + }
482 + if (**buf != '-')
483 + return -EINVAL;
484 + (*buf)++;
485 + (*len)--;
486 + if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
487 + return -EINVAL;
488 + while (next <= ch)
489 + channels[next++] = 1;
490 + if (!*len)
491 + break;
492 + if (**buf != ',')
493 + return -EINVAL;
494 + (*buf)++;
495 + (*len)--;
496 + }
497 + return 1;
498 +}
499 +
500 +static size_t print_channels(struct port *port, char *buf, u8 id)
501 +{
502 + unsigned int ch, cnt = 0;
503 + size_t len = 0;
504 +
505 + for (ch = 0; ch < MAX_CHANNELS; ch++)
506 + if (port->channels[ch] == id) {
507 + if (cnt == 0) {
508 + sprintf(buf + len, "%s%u", len ? "," : "", ch);
509 + len += strlen(buf + len);
510 + }
511 + cnt++;
512 + } else {
513 + if (cnt > 1) {
514 + sprintf(buf + len, "-%u", ch - 1);
515 + len += strlen(buf + len);
516 + }
517 + cnt = 0;
518 + }
519 + if (cnt > 1) {
520 + sprintf(buf + len, "-%u", ch - 1);
521 + len += strlen(buf + len);
522 + }
523 +
524 + buf[len++] = '\n';
525 + return len;
526 +}
527 +
528 +static inline unsigned int sub_offset(unsigned int a, unsigned int b,
529 + unsigned int modulo)
530 +{
531 + return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
532 +}
533 +
534 +/*****************************************************************************
535 + * HSS access
536 + ****************************************************************************/
537 +
538 +static void hss_config_load(struct port *port)
539 +{
540 + struct msg msg;
541 +
542 + do {
543 + memset(&msg, 0, sizeof(msg));
544 + msg.cmd = PORT_CONFIG_LOAD;
545 + msg.hss_port = port->id;
546 + if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
547 + break;
548 + if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
549 + break;
550 +
551 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
552 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
553 + break;
554 +
555 + /* HDLC may stop working without this */
556 + npe_recv_message(port->npe, &msg, "FLUSH_IT");
557 + return;
558 + } while (0);
559 +
560 + printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
561 + port->id);
562 + BUG();
563 +}
564 +
565 +static void hss_config_set_pcr(struct port *port)
566 +{
567 + struct msg msg;
568 +
569 + do {
570 + memset(&msg, 0, sizeof(msg));
571 + msg.cmd = PORT_CONFIG_WRITE;
572 + msg.hss_port = port->id;
573 + msg.index = HSS_CONFIG_TX_PCR;
574 + msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
575 + PCR_TX_DATA_ENABLE;
576 + if (port->frame_size % 8 == 0)
577 + msg.data32 |= PCR_SOF_NO_FBIT;
578 + if (port->clock_type == CLOCK_INT)
579 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
580 + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
581 + break;
582 +
583 + msg.index = HSS_CONFIG_RX_PCR;
584 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
585 + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
586 + break;
587 + return;
588 + } while (0);
589 +
590 + printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
591 + BUG();
592 +}
593 +
594 +static void hss_config_set_hdlc_cfg(struct port *port)
595 +{
596 + struct msg msg;
597 +
598 + memset(&msg, 0, sizeof(msg));
599 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
600 + msg.hss_port = port->id;
601 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
602 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
603 + if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
604 + printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
605 + " configuration\n", port->id);
606 + BUG();
607 + }
608 +}
609 +
610 +static void hss_config_set_core(struct port *port)
611 +{
612 + struct msg msg;
613 +
614 + memset(&msg, 0, sizeof(msg));
615 + msg.cmd = PORT_CONFIG_WRITE;
616 + msg.hss_port = port->id;
617 + msg.index = HSS_CONFIG_CORE_CR;
618 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
619 + (port->id ? CCR_SECOND_HSS : 0);
620 + if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
621 + printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
622 + " register\n", port->id);
623 + BUG();
624 + }
625 +}
626 +
627 +static void hss_config_set_line(struct port *port)
628 +{
629 + struct msg msg;
630 +
631 + hss_config_set_pcr(port);
632 + hss_config_set_core(port);
633 +
634 + memset(&msg, 0, sizeof(msg));
635 + msg.cmd = PORT_CONFIG_WRITE;
636 + msg.hss_port = port->id;
637 + msg.index = HSS_CONFIG_CLOCK_CR;
638 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
639 + if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
640 + printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
641 + " register\n", port->id);
642 + BUG();
643 + }
644 +}
645 +
646 +static void hss_config_set_rx_frame(struct port *port)
647 +{
648 + struct msg msg;
649 +
650 + memset(&msg, 0, sizeof(msg));
651 + msg.cmd = PORT_CONFIG_WRITE;
652 + msg.hss_port = port->id;
653 + msg.index = HSS_CONFIG_RX_FCR;
654 + msg.data16a = port->frame_sync_offset;
655 + msg.data16b = port->frame_size - 1;
656 + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
657 + printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
658 + " and offset\n", port->id);
659 + BUG();
660 + }
661 +}
662 +
663 +static void hss_config_set_frame(struct port *port)
664 +{
665 + struct msg msg;
666 +
667 + memset(&msg, 0, sizeof(msg));
668 + msg.cmd = PORT_CONFIG_WRITE;
669 + msg.hss_port = port->id;
670 + msg.index = HSS_CONFIG_TX_FCR;
671 + msg.data16a = TX_FRAME_SYNC_OFFSET;
672 + msg.data16b = port->frame_size - 1;
673 + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
674 + printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
675 + " and offset\n", port->id);
676 + BUG();
677 + }
678 + hss_config_set_rx_frame(port);
679 +}
680 +
681 +static void hss_config_set_lut(struct port *port)
682 +{
683 + struct msg msg;
684 + int chan_count = 0, log_chan = 0, i, ch;
685 + u32 lut[MAX_CHANNELS / 4];
686 +
687 + memset(lut, 0, sizeof(lut));
688 + for (i = 0; i < MAX_CHAN_DEVICES; i++)
689 + if (port->chan_devices[i])
690 + port->chan_devices[i]->chan_count = 0;
691 +
692 + memset(&msg, 0, sizeof(msg));
693 + msg.cmd = PORT_CONFIG_WRITE;
694 + msg.hss_port = port->id;
695 +
696 + for (ch = 0; ch < MAX_CHANNELS; ch++) {
697 + struct chan_device *chdev = NULL;
698 + unsigned int entry;
699 +
700 + if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
701 + chdev = port->chan_devices[port->channels[ch]];
702 +
703 + if (port->mode == MODE_G704 && ch == 0)
704 + entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
705 + else if (port->mode == MODE_HDLC ||
706 + port->channels[ch] == CHANNEL_HDLC)
707 + entry = TDMMAP_HDLC;
708 + else if (chdev && chdev->open_count) {
709 + entry = TDMMAP_VOICE64K;
710 + chdev->log_channels[chdev->chan_count++] = log_chan;
711 + } else
712 + entry = TDMMAP_UNASSIGNED;
713 + if (entry == TDMMAP_VOICE64K) {
714 + chan_count++;
715 + log_chan++;
716 + }
717 +
718 + msg.data32 >>= 2;
719 + msg.data32 |= entry << 30;
720 +
721 + if (ch % 16 == 15) {
722 + msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
723 + if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
724 + break;
725 +
726 + msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
727 + if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
728 + break;
729 + }
730 + }
731 + if (ch != MAX_CHANNELS) {
732 + printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
733 + " table\n", port->id);
734 + BUG();
735 + }
736 +
737 + hss_config_set_frame(port);
738 +
739 + if (!chan_count)
740 + return;
741 +
742 + memset(&msg, 0, sizeof(msg));
743 + msg.cmd = CHAN_NUM_CHANS_WRITE;
744 + msg.hss_port = port->id;
745 + msg.data8a = chan_count;
746 + if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
747 + printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
748 + port->id);
749 + BUG();
750 + }
751 +
752 + /* don't leak data */
753 + // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
754 + if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
755 + for (i = 0; i < CHAN_TX_FRAMES; i += 4)
756 + *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
757 +
758 + for (i = 0; i < CHAN_TX_LISTS; i++) {
759 + u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
760 + u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
761 + for (ch = 0; ch < chan_count; ch++)
762 + list[ch] = phys + ch * CHAN_TX_FRAMES;
763 + }
764 + dma_sync_single(port->dev, port->chan_tx_buf_phys,
765 + chan_tx_buf_len(port) + chan_tx_lists_len(port),
766 + DMA_TO_DEVICE);
767 +}
768 +
769 +static u32 hss_config_get_status(struct port *port)
770 +{
771 + struct msg msg;
772 +
773 + do {
774 + memset(&msg, 0, sizeof(msg));
775 + msg.cmd = PORT_ERROR_READ;
776 + msg.hss_port = port->id;
777 + if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
778 + break;
779 + if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
780 + break;
781 +
782 + return msg.data32;
783 + } while (0);
784 +
785 + printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
786 + BUG();
787 +}
788 +
789 +static void hss_config_start_chan(struct port *port)
790 +{
791 + struct msg msg;
792 +
793 + port->chan_last_tx = 0;
794 + port->chan_last_rx = 0;
795 +
796 + do {
797 + memset(&msg, 0, sizeof(msg));
798 + msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
799 + msg.hss_port = port->id;
800 + msg.data32 = port->chan_rx_buf_phys;
801 + if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
802 + break;
803 +
804 + memset(&msg, 0, sizeof(msg));
805 + msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
806 + msg.hss_port = port->id;
807 + msg.data32 = chan_tx_lists_phys(port);
808 + if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
809 + break;
810 +
811 + memset(&msg, 0, sizeof(msg));
812 + msg.cmd = CHAN_FLOW_ENABLE;
813 + msg.hss_port = port->id;
814 + if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
815 + break;
816 + port->chan_started = 1;
817 + return;
818 + } while (0);
819 +
820 + printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
821 + port->id);
822 + BUG();
823 +}
824 +
825 +static void hss_config_stop_chan(struct port *port)
826 +{
827 + struct msg msg;
828 +
829 + if (!port->chan_started)
830 + return;
831 +
832 + memset(&msg, 0, sizeof(msg));
833 + msg.cmd = CHAN_FLOW_DISABLE;
834 + msg.hss_port = port->id;
835 + if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
836 + printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
837 + port->id);
838 + BUG();
839 + }
840 + hss_config_get_status(port); /* make sure it's halted */
841 +}
842 +
843 +static void hss_config_start_hdlc(struct port *port)
844 +{
845 + struct msg msg;
846 +
847 + memset(&msg, 0, sizeof(msg));
848 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
849 + msg.hss_port = port->id;
850 + msg.data32 = 0;
851 + if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
852 + printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
853 + port->id);
854 + BUG();
855 + }
856 +}
857 +
858 +static void hss_config_stop_hdlc(struct port *port)
859 +{
860 + struct msg msg;
861 +
862 + memset(&msg, 0, sizeof(msg));
863 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
864 + msg.hss_port = port->id;
865 + if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
866 + printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
867 + port->id);
868 + BUG();
869 + }
870 + hss_config_get_status(port); /* make sure it's halted */
871 +}
872 +
873 +static int hss_config_load_firmware(struct port *port)
874 +{
875 + struct msg msg;
876 +
877 + if (port->initialized)
878 + return 0;
879 +
880 + if (!npe_running(port->npe)) {
881 + int err;
882 + if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
883 + port->dev)))
884 + return err;
885 + }
886 +
887 + do {
888 + /* HSS main configuration */
889 + hss_config_set_line(port);
890 +
891 + hss_config_set_frame(port);
892 +
893 + /* HDLC mode configuration */
894 + memset(&msg, 0, sizeof(msg));
895 + msg.cmd = PKT_NUM_PIPES_WRITE;
896 + msg.hss_port = port->id;
897 + msg.data8a = PKT_NUM_PIPES;
898 + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
899 + break;
900 +
901 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
902 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
903 + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
904 + break;
905 +
906 + msg.cmd = PKT_PIPE_MODE_WRITE;
907 + msg.data8a = NPE_PKT_MODE_HDLC;
908 + /* msg.data8b = inv_mask */
909 + /* msg.data8c = or_mask */
910 + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
911 + break;
912 +
913 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
914 + msg.data16a = HDLC_MAX_MRU; /* including CRC */
915 + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
916 + break;
917 +
918 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
919 + msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
920 + if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
921 + break;
922 +
923 + /* Channelized operation settings */
924 + memset(&msg, 0, sizeof(msg));
925 + msg.cmd = CHAN_TX_BLK_CFG_WRITE;
926 + msg.hss_port = port->id;
927 + msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
928 + msg.data8a = msg.data8b / 4;
929 + msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
930 + msg.data8c = msg.data8d / 4;
931 + if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
932 + break;
933 +
934 + memset(&msg, 0, sizeof(msg));
935 + msg.cmd = CHAN_RX_BUF_CFG_WRITE;
936 + msg.hss_port = port->id;
937 + msg.data8a = CHAN_RX_TRIGGER / 8;
938 + msg.data8b = CHAN_RX_FRAMES;
939 + if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
940 + break;
941 +
942 + memset(&msg, 0, sizeof(msg));
943 + msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
944 + msg.hss_port = port->id;
945 + msg.data8a = CHAN_TX_LISTS;
946 + if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
947 + break;
948 +
949 + port->initialized = 1;
950 + return 0;
951 + } while (0);
952 +
953 + printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
954 + BUG();
955 +}
956 +
957 +/*****************************************************************************
958 + * packetized (HDLC) operation
959 + ****************************************************************************/
960 +
961 +static inline void debug_pkt(struct net_device *dev, const char *func,
962 + u8 *data, int len)
963 +{
964 +#if DEBUG_PKT_BYTES
965 + int i;
966 +
967 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
968 + for (i = 0; i < len; i++) {
969 + if (i >= DEBUG_PKT_BYTES)
970 + break;
971 + printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
972 + }
973 + printk(KERN_DEBUG "\n");
974 +#endif
975 +}
976 +
977 +
978 +static inline void debug_desc(u32 phys, struct desc *desc)
979 +{
980 +#if DEBUG_DESC
981 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
982 + phys, desc->next, desc->buf_len, desc->pkt_len,
983 + desc->data, desc->status, desc->error_count);
984 +#endif
985 +}
986 +
987 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
988 +{
989 +#if DEBUG_QUEUES
990 + static struct {
991 + int queue;
992 + char *name;
993 + } names[] = {
994 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
995 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
996 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
997 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
998 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
999 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
1000 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
1001 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
1002 + };
1003 + int i;
1004 +
1005 + for (i = 0; i < ARRAY_SIZE(names); i++)
1006 + if (names[i].queue == queue)
1007 + break;
1008 +
1009 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1010 + i < ARRAY_SIZE(names) ? names[i].name : "",
1011 + is_get ? "->" : "<-", phys);
1012 +#endif
1013 +}
1014 +
1015 +static inline u32 queue_get_entry(unsigned int queue)
1016 +{
1017 + u32 phys = qmgr_get_entry(queue);
1018 + debug_queue(queue, 1, phys);
1019 + return phys;
1020 +}
1021 +
1022 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1023 + int is_tx)
1024 +{
1025 + u32 phys, tab_phys, n_desc;
1026 + struct desc *tab;
1027 +
1028 + if (!(phys = queue_get_entry(queue)))
1029 + return -1;
1030 +
1031 + BUG_ON(phys & 0x1F);
1032 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1033 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1034 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1035 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1036 + debug_desc(phys, &tab[n_desc]);
1037 + BUG_ON(tab[n_desc].next);
1038 + return n_desc;
1039 +}
1040 +
1041 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1042 + struct desc *desc)
1043 +{
1044 + debug_queue(queue, 0, phys);
1045 + debug_desc(phys, desc);
1046 + BUG_ON(phys & 0x1F);
1047 + qmgr_put_entry(queue, phys);
1048 + BUG_ON(qmgr_stat_overflow(queue));
1049 +}
1050 +
1051 +
1052 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1053 +{
1054 +#ifdef __ARMEB__
1055 + dma_unmap_single(&port->netdev->dev, desc->data,
1056 + desc->buf_len, DMA_TO_DEVICE);
1057 +#else
1058 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1059 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1060 + DMA_TO_DEVICE);
1061 +#endif
1062 +}
1063 +
1064 +
1065 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
1066 +{
1067 + struct net_device *netdev = pdev;
1068 + struct port *port = dev_to_port(netdev);
1069 + unsigned long flags;
1070 +
1071 + spin_lock_irqsave(&npe_lock, flags);
1072 + port->carrier = carrier;
1073 + if (!port->loopback) {
1074 + if (carrier)
1075 + netif_carrier_on(netdev);
1076 + else
1077 + netif_carrier_off(netdev);
1078 + }
1079 + spin_unlock_irqrestore(&npe_lock, flags);
1080 +}
1081 +
1082 +static void hss_hdlc_rx_irq(void *pdev)
1083 +{
1084 + struct net_device *dev = pdev;
1085 + struct port *port = dev_to_port(dev);
1086 +
1087 +#if DEBUG_RX
1088 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
1089 +#endif
1090 + qmgr_disable_irq(queue_ids[port->id].rx);
1091 + netif_rx_schedule(dev, &port->napi);
1092 +}
1093 +
1094 +static int hss_hdlc_poll(struct napi_struct *napi, int budget)
1095 +{
1096 + struct port *port = container_of(napi, struct port, napi);
1097 + struct net_device *dev = port->netdev;
1098 + unsigned int rxq = queue_ids[port->id].rx;
1099 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
1100 + struct net_device_stats *stats = hdlc_stats(dev);
1101 + int received = 0;
1102 +
1103 +#if DEBUG_RX
1104 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
1105 +#endif
1106 +
1107 + while (received < budget) {
1108 + struct sk_buff *skb;
1109 + struct desc *desc;
1110 + int n;
1111 +#ifdef __ARMEB__
1112 + struct sk_buff *temp;
1113 + u32 phys;
1114 +#endif
1115 +
1116 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1117 + received = 0; /* No packet received */
1118 +#if DEBUG_RX
1119 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1120 + " netif_rx_complete\n", dev->name);
1121 +#endif
1122 + netif_rx_complete(dev, napi);
1123 + qmgr_enable_irq(rxq);
1124 + if (!qmgr_stat_empty(rxq) &&
1125 + netif_rx_reschedule(dev, napi)) {
1126 +#if DEBUG_RX
1127 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1128 + " netif_rx_reschedule succeeded\n",
1129 + dev->name);
1130 +#endif
1131 + qmgr_disable_irq(rxq);
1132 + continue;
1133 + }
1134 +#if DEBUG_RX
1135 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
1136 + dev->name);
1137 +#endif
1138 + return 0; /* all work done */
1139 + }
1140 +
1141 + desc = rx_desc_ptr(port, n);
1142 +#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
1143 + if (desc->error_count)
1144 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
1145 + " errors %u\n", dev->name, desc->status,
1146 + desc->error_count);
1147 +#endif
1148 + skb = NULL;
1149 + switch (desc->status) {
1150 + case 0:
1151 +#ifdef __ARMEB__
1152 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
1153 + phys = dma_map_single(&dev->dev, skb->data,
1154 + RX_SIZE,
1155 + DMA_FROM_DEVICE);
1156 + if (dma_mapping_error(phys)) {
1157 + dev_kfree_skb(skb);
1158 + skb = NULL;
1159 + }
1160 + }
1161 +#else
1162 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1163 +#endif
1164 + if (!skb)
1165 + stats->rx_dropped++;
1166 + break;
1167 + case ERR_HDLC_ALIGN:
1168 + case ERR_HDLC_ABORT:
1169 + stats->rx_frame_errors++;
1170 + stats->rx_errors++;
1171 + break;
1172 + case ERR_HDLC_FCS:
1173 + stats->rx_crc_errors++;
1174 + stats->rx_errors++;
1175 + break;
1176 + case ERR_HDLC_TOO_LONG:
1177 + stats->rx_length_errors++;
1178 + stats->rx_errors++;
1179 + break;
1180 + default: /* FIXME - remove printk */
1181 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
1182 + " errors %u\n", dev->name, desc->status,
1183 + desc->error_count);
1184 + stats->rx_errors++;
1185 + }
1186 +
1187 + if (!skb) {
1188 + /* put the desc back on RX-ready queue */
1189 + desc->buf_len = RX_SIZE;
1190 + desc->pkt_len = desc->status = 0;
1191 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1192 + continue;
1193 + }
1194 +
1195 + /* process received frame */
1196 +#ifdef __ARMEB__
1197 + temp = skb;
1198 + skb = port->rx_buff_tab[n];
1199 + dma_unmap_single(&dev->dev, desc->data,
1200 + RX_SIZE, DMA_FROM_DEVICE);
1201 +#else
1202 + dma_sync_single(&dev->dev, desc->data,
1203 + RX_SIZE, DMA_FROM_DEVICE);
1204 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1205 + ALIGN(desc->pkt_len, 4) / 4);
1206 +#endif
1207 + skb_put(skb, desc->pkt_len);
1208 +
1209 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
1210 +
1211 + skb->protocol = hdlc_type_trans(skb, dev);
1212 + dev->last_rx = jiffies;
1213 + stats->rx_packets++;
1214 + stats->rx_bytes += skb->len;
1215 + netif_receive_skb(skb);
1216 +
1217 + /* put the new buffer on RX-free queue */
1218 +#ifdef __ARMEB__
1219 + port->rx_buff_tab[n] = temp;
1220 + desc->data = phys;
1221 +#endif
1222 + desc->buf_len = RX_SIZE;
1223 + desc->pkt_len = 0;
1224 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1225 + received++;
1226 + }
1227 +#if DEBUG_RX
1228 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
1229 +#endif
1230 + return received; /* not all work done */
1231 +}
1232 +
1233 +
1234 +static void hss_hdlc_txdone_irq(void *pdev)
1235 +{
1236 + struct net_device *dev = pdev;
1237 + struct port *port = dev_to_port(dev);
1238 + struct net_device_stats *stats = hdlc_stats(dev);
1239 + int n_desc;
1240 +
1241 +#if DEBUG_TX
1242 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
1243 +#endif
1244 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
1245 + port, 1)) >= 0) {
1246 + struct desc *desc;
1247 + int start;
1248 +
1249 + desc = tx_desc_ptr(port, n_desc);
1250 +
1251 + stats->tx_packets++;
1252 + stats->tx_bytes += desc->pkt_len;
1253 +
1254 + dma_unmap_tx(port, desc);
1255 +#if DEBUG_TX
1256 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
1257 + dev->name, port->tx_buff_tab[n_desc]);
1258 +#endif
1259 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1260 + port->tx_buff_tab[n_desc] = NULL;
1261 +
1262 + start = qmgr_stat_empty(port->plat->txreadyq);
1263 + queue_put_desc(port->plat->txreadyq,
1264 + tx_desc_phys(port, n_desc), desc);
1265 + if (start) {
1266 +#if DEBUG_TX
1267 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
1268 + " ready\n", dev->name);
1269 +#endif
1270 + netif_wake_queue(dev);
1271 + }
1272 + }
1273 +}
1274 +
1275 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
1276 +{
1277 + struct port *port = dev_to_port(dev);
1278 + struct net_device_stats *stats = hdlc_stats(dev);
1279 + unsigned int txreadyq = port->plat->txreadyq;
1280 + int len, offset, bytes, n;
1281 + void *mem;
1282 + u32 phys;
1283 + struct desc *desc;
1284 +
1285 +#if DEBUG_TX
1286 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
1287 +#endif
1288 +
1289 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
1290 + dev_kfree_skb(skb);
1291 + stats->tx_errors++;
1292 + return NETDEV_TX_OK;
1293 + }
1294 +
1295 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
1296 +
1297 + len = skb->len;
1298 +#ifdef __ARMEB__
1299 + offset = 0; /* no need to keep alignment */
1300 + bytes = len;
1301 + mem = skb->data;
1302 +#else
1303 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
1304 + bytes = ALIGN(offset + len, 4);
1305 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1306 + dev_kfree_skb(skb);
1307 + stats->tx_dropped++;
1308 + return NETDEV_TX_OK;
1309 + }
1310 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1311 + dev_kfree_skb(skb);
1312 +#endif
1313 +
1314 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1315 + if (dma_mapping_error(phys)) {
1316 +#ifdef __ARMEB__
1317 + dev_kfree_skb(skb);
1318 +#else
1319 + kfree(mem);
1320 +#endif
1321 + stats->tx_dropped++;
1322 + return NETDEV_TX_OK;
1323 + }
1324 +
1325 + n = queue_get_desc(txreadyq, port, 1);
1326 + BUG_ON(n < 0);
1327 + desc = tx_desc_ptr(port, n);
1328 +
1329 +#ifdef __ARMEB__
1330 + port->tx_buff_tab[n] = skb;
1331 +#else
1332 + port->tx_buff_tab[n] = mem;
1333 +#endif
1334 + desc->data = phys + offset;
1335 + desc->buf_len = desc->pkt_len = len;
1336 +
1337 + wmb();
1338 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
1339 + dev->trans_start = jiffies;
1340 +
1341 + if (qmgr_stat_empty(txreadyq)) {
1342 +#if DEBUG_TX
1343 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
1344 +#endif
1345 + netif_stop_queue(dev);
1346 + /* we could miss TX ready interrupt */
1347 + if (!qmgr_stat_empty(txreadyq)) {
1348 +#if DEBUG_TX
1349 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
1350 + dev->name);
1351 +#endif
1352 + netif_wake_queue(dev);
1353 + }
1354 + }
1355 +
1356 +#if DEBUG_TX
1357 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
1358 +#endif
1359 + return NETDEV_TX_OK;
1360 +}
1361 +
1362 +
1363 +static int request_hdlc_queues(struct port *port)
1364 +{
1365 + int err;
1366 +
1367 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
1368 + if (err)
1369 + return err;
1370 +
1371 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
1372 + if (err)
1373 + goto rel_rxfree;
1374 +
1375 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
1376 + if (err)
1377 + goto rel_rx;
1378 +
1379 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1380 + if (err)
1381 + goto rel_tx;
1382 +
1383 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
1384 + if (err)
1385 + goto rel_txready;
1386 + return 0;
1387 +
1388 +rel_txready:
1389 + qmgr_release_queue(port->plat->txreadyq);
1390 +rel_tx:
1391 + qmgr_release_queue(queue_ids[port->id].tx);
1392 +rel_rx:
1393 + qmgr_release_queue(queue_ids[port->id].rx);
1394 +rel_rxfree:
1395 + qmgr_release_queue(queue_ids[port->id].rxfree);
1396 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1397 + port->netdev->name);
1398 + return err;
1399 +}
1400 +
1401 +static void release_hdlc_queues(struct port *port)
1402 +{
1403 + qmgr_release_queue(queue_ids[port->id].rxfree);
1404 + qmgr_release_queue(queue_ids[port->id].rx);
1405 + qmgr_release_queue(queue_ids[port->id].txdone);
1406 + qmgr_release_queue(queue_ids[port->id].tx);
1407 + qmgr_release_queue(port->plat->txreadyq);
1408 +}
1409 +
1410 +static int init_hdlc_queues(struct port *port)
1411 +{
1412 + int i;
1413 +
1414 + if (!ports_open)
1415 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
1416 + POOL_ALLOC_SIZE, 32, 0)))
1417 + return -ENOMEM;
1418 +
1419 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1420 + &port->desc_tab_phys)))
1421 + return -ENOMEM;
1422 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1423 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1424 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1425 +
1426 + /* Setup RX buffers */
1427 + for (i = 0; i < RX_DESCS; i++) {
1428 + struct desc *desc = rx_desc_ptr(port, i);
1429 + buffer_t *buff;
1430 + void *data;
1431 +#ifdef __ARMEB__
1432 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
1433 + return -ENOMEM;
1434 + data = buff->data;
1435 +#else
1436 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
1437 + return -ENOMEM;
1438 + data = buff;
1439 +#endif
1440 + desc->buf_len = RX_SIZE;
1441 + desc->data = dma_map_single(&port->netdev->dev, data,
1442 + RX_SIZE, DMA_FROM_DEVICE);
1443 + if (dma_mapping_error(desc->data)) {
1444 + free_buffer(buff);
1445 + return -EIO;
1446 + }
1447 + port->rx_buff_tab[i] = buff;
1448 + }
1449 +
1450 + return 0;
1451 +}
1452 +
1453 +static void destroy_hdlc_queues(struct port *port)
1454 +{
1455 + int i;
1456 +
1457 + if (port->desc_tab) {
1458 + for (i = 0; i < RX_DESCS; i++) {
1459 + struct desc *desc = rx_desc_ptr(port, i);
1460 + buffer_t *buff = port->rx_buff_tab[i];
1461 + if (buff) {
1462 + dma_unmap_single(&port->netdev->dev,
1463 + desc->data, RX_SIZE,
1464 + DMA_FROM_DEVICE);
1465 + free_buffer(buff);
1466 + }
1467 + }
1468 + for (i = 0; i < TX_DESCS; i++) {
1469 + struct desc *desc = tx_desc_ptr(port, i);
1470 + buffer_t *buff = port->tx_buff_tab[i];
1471 + if (buff) {
1472 + dma_unmap_tx(port, desc);
1473 + free_buffer(buff);
1474 + }
1475 + }
1476 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1477 + port->desc_tab = NULL;
1478 + }
1479 +
1480 + if (!ports_open && dma_pool) {
1481 + dma_pool_destroy(dma_pool);
1482 + dma_pool = NULL;
1483 + }
1484 +}
1485 +
1486 +static int hss_hdlc_open(struct net_device *dev)
1487 +{
1488 + struct port *port = dev_to_port(dev);
1489 + unsigned long flags;
1490 + int i, err = 0;
1491 +
1492 + if ((err = hdlc_open(dev)))
1493 + return err;
1494 +
1495 + if ((err = request_hdlc_queues(port)))
1496 + goto err_hdlc_close;
1497 +
1498 + if ((err = init_hdlc_queues(port)))
1499 + goto err_destroy_queues;
1500 +
1501 + spin_lock_irqsave(&npe_lock, flags);
1502 +
1503 + if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
1504 + err = -EBUSY; /* channel #0 is used for G.704 framing */
1505 + goto err_unlock;
1506 + }
1507 + if (port->mode != MODE_HDLC)
1508 + for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
1509 + if (port->channels[i] == CHANNEL_HDLC) {
1510 + err = -ECHRNG; /* frame too short */
1511 + goto err_unlock;
1512 + }
1513 +
1514 + if ((err = hss_config_load_firmware(port)))
1515 + goto err_unlock;
1516 +
1517 + if (!port->chan_open_count && port->plat->open)
1518 + if ((err = port->plat->open(port->id, dev,
1519 + hss_hdlc_set_carrier)))
1520 + goto err_unlock;
1521 +
1522 + if (port->mode == MODE_G704 && !port->chan_open_count)
1523 + if ((err = hss_prepare_chan(port)))
1524 + goto err_plat_close;
1525 +
1526 + spin_unlock_irqrestore(&npe_lock, flags);
1527 +
1528 + /* Populate queues with buffers, no failure after this point */
1529 + for (i = 0; i < TX_DESCS; i++)
1530 + queue_put_desc(port->plat->txreadyq,
1531 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
1532 +
1533 + for (i = 0; i < RX_DESCS; i++)
1534 + queue_put_desc(queue_ids[port->id].rxfree,
1535 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
1536 +
1537 + napi_enable(&port->napi);
1538 + netif_start_queue(dev);
1539 +
1540 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1541 + hss_hdlc_rx_irq, dev);
1542 +
1543 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1544 + hss_hdlc_txdone_irq, dev);
1545 + qmgr_enable_irq(queue_ids[port->id].txdone);
1546 +
1547 + ports_open++;
1548 + port->hdlc_open = 1;
1549 +
1550 + hss_config_set_hdlc_cfg(port);
1551 + hss_config_set_lut(port);
1552 + hss_config_load(port);
1553 +
1554 + if (port->mode == MODE_G704 && !port->chan_open_count)
1555 + hss_config_start_chan(port);
1556 +
1557 + hss_config_start_hdlc(port);
1558 +
1559 + /* we may already have RX data, enables IRQ */
1560 + netif_rx_schedule(dev, &port->napi);
1561 + return 0;
1562 +
1563 +err_plat_close:
1564 + if (!port->chan_open_count && port->plat->close)
1565 + port->plat->close(port->id, dev);
1566 +err_unlock:
1567 + spin_unlock_irqrestore(&npe_lock, flags);
1568 +err_destroy_queues:
1569 + destroy_hdlc_queues(port);
1570 + release_hdlc_queues(port);
1571 +err_hdlc_close:
1572 + hdlc_close(dev);
1573 + return err;
1574 +}
1575 +
1576 +static int hss_hdlc_close(struct net_device *dev)
1577 +{
1578 + struct port *port = dev_to_port(dev);
1579 + unsigned long flags;
1580 + int i, buffs = RX_DESCS; /* allocated RX buffers */
1581 +
1582 + spin_lock_irqsave(&npe_lock, flags);
1583 + ports_open--;
1584 + port->hdlc_open = 0;
1585 + qmgr_disable_irq(queue_ids[port->id].rx);
1586 + netif_stop_queue(dev);
1587 + napi_disable(&port->napi);
1588 +
1589 + hss_config_stop_hdlc(port);
1590 +
1591 + if (port->mode == MODE_G704 && !port->chan_open_count)
1592 + hss_chan_stop(port);
1593 +
1594 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1595 + buffs--;
1596 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1597 + buffs--;
1598 +
1599 + if (buffs)
1600 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1601 + " left in NPE\n", dev->name, buffs);
1602 +
1603 + buffs = TX_DESCS;
1604 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1605 + buffs--; /* cancel TX */
1606 +
1607 + i = 0;
1608 + do {
1609 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1610 + buffs--;
1611 + if (!buffs)
1612 + break;
1613 + } while (++i < MAX_CLOSE_WAIT);
1614 +
1615 + if (buffs)
1616 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1617 + "left in NPE\n", dev->name, buffs);
1618 +#if DEBUG_CLOSE
1619 + if (!buffs)
1620 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1621 +#endif
1622 + qmgr_disable_irq(queue_ids[port->id].txdone);
1623 +
1624 + if (!port->chan_open_count && port->plat->close)
1625 + port->plat->close(port->id, dev);
1626 + spin_unlock_irqrestore(&npe_lock, flags);
1627 +
1628 + destroy_hdlc_queues(port);
1629 + release_hdlc_queues(port);
1630 + hdlc_close(dev);
1631 + return 0;
1632 +}
1633 +
1634 +
1635 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1636 + unsigned short parity)
1637 +{
1638 + struct port *port = dev_to_port(dev);
1639 +
1640 + if (encoding != ENCODING_NRZ)
1641 + return -EINVAL;
1642 +
1643 + switch(parity) {
1644 + case PARITY_CRC16_PR1_CCITT:
1645 + port->hdlc_cfg = 0;
1646 + return 0;
1647 +
1648 + case PARITY_CRC32_PR1_CCITT:
1649 + port->hdlc_cfg = PKT_HDLC_CRC_32;
1650 + return 0;
1651 +
1652 + default:
1653 + return -EINVAL;
1654 + }
1655 +}
1656 +
1657 +
1658 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1659 +{
1660 + const size_t size = sizeof(sync_serial_settings);
1661 + sync_serial_settings new_line;
1662 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1663 + struct port *port = dev_to_port(dev);
1664 + unsigned long flags;
1665 + int i, clk;
1666 +
1667 + if (cmd != SIOCWANDEV)
1668 + return hdlc_ioctl(dev, ifr, cmd);
1669 +
1670 + switch(ifr->ifr_settings.type) {
1671 + case IF_GET_IFACE:
1672 + ifr->ifr_settings.type = IF_IFACE_V35;
1673 + if (ifr->ifr_settings.size < size) {
1674 + ifr->ifr_settings.size = size; /* data size wanted */
1675 + return -ENOBUFS;
1676 + }
1677 + memset(&new_line, 0, sizeof(new_line));
1678 + new_line.clock_type = port->clock_type;
1679 + new_line.clock_rate = port->clock_rate;
1680 + new_line.loopback = port->loopback;
1681 + if (copy_to_user(line, &new_line, size))
1682 + return -EFAULT;
1683 +
1684 + if (!port->chan_buf)
1685 + return 0;
1686 +
1687 + dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
1688 + chan_rx_buf_len(port), DMA_FROM_DEVICE);
1689 + printk(KERN_DEBUG "RX:\n");
1690 + for (i = 0; i < chan_rx_buf_len(port); i++) {
1691 + if (i % 32 == 0)
1692 + printk(KERN_DEBUG "%03X ", i);
1693 + printk("%02X%c", chan_rx_buf(port)[i],
1694 + (i + 1) % 32 ? ' ' : '\n');
1695 + }
1696 +
1697 +#if 0
1698 + printk(KERN_DEBUG "TX:\n");
1699 + for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
1700 + + chan_tx_lists_len(port); i++) {
1701 + if (i % 32 == 0)
1702 + printk(KERN_DEBUG "%03X ", i);
1703 + printk("%02X%c", chan_tx_buf(port)[i],
1704 + (i + 1) % 32 ? ' ' : '\n');
1705 + }
1706 +#endif
1707 + port->msg_count = 10;
1708 + return 0;
1709 +
1710 + case IF_IFACE_SYNC_SERIAL:
1711 + case IF_IFACE_V35:
1712 + if(!capable(CAP_NET_ADMIN))
1713 + return -EPERM;
1714 + if (copy_from_user(&new_line, line, size))
1715 + return -EFAULT;
1716 +
1717 + clk = new_line.clock_type;
1718 + if (port->plat->set_clock)
1719 + clk = port->plat->set_clock(port->id, clk);
1720 +
1721 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
1722 + return -EINVAL; /* No such clock setting */
1723 +
1724 + if (new_line.loopback != 0 && new_line.loopback != 1)
1725 + return -EINVAL;
1726 +
1727 + port->clock_type = clk; /* Update settings */
1728 + /* FIXME port->clock_rate = new_line.clock_rate */;
1729 + port->loopback = new_line.loopback;
1730 +
1731 + spin_lock_irqsave(&npe_lock, flags);
1732 +
1733 + if (port->chan_open_count || port->hdlc_open) {
1734 + hss_config_set_line(port);
1735 + hss_config_load(port);
1736 + }
1737 + if (port->loopback || port->carrier)
1738 + netif_carrier_on(port->netdev);
1739 + else
1740 + netif_carrier_off(port->netdev);
1741 + spin_unlock_irqrestore(&npe_lock, flags);
1742 +
1743 + return 0;
1744 +
1745 + default:
1746 + return hdlc_ioctl(dev, ifr, cmd);
1747 + }
1748 +}
1749 +
1750 +/*****************************************************************************
1751 + * channelized (G.704) operation
1752 + ****************************************************************************/
1753 +
1754 +static void g704_rx_framer(struct port *port, unsigned int offset)
1755 +{
1756 + u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
1757 + CHAN_RX_FRAMES);
1758 + unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
1759 + unsigned int is_first = port->just_set_offset;
1760 + u8 zeros_even, zeros_odd, ones_even, ones_odd;
1761 + enum alignment aligned;
1762 +
1763 + port->just_set_offset = 0;
1764 + dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
1765 + DMA_FROM_DEVICE);
1766 +
1767 + /* check if aligned first */
1768 + for (frame = 0; frame < CHAN_RX_TRIGGER &&
1769 + (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
1770 + bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
1771 + u8 ve = data[frame];
1772 + u8 vo = data[frame + 1];
1773 +
1774 + if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
1775 + bad_even++;
1776 +
1777 + if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
1778 + bad_odd++;
1779 + }
1780 +
1781 + if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
1782 + aligned = EVEN_FIRST;
1783 + else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
1784 + aligned = ODD_FIRST;
1785 + else
1786 + aligned = NOT_ALIGNED;
1787 +
1788 + if (aligned != NOT_ALIGNED) {
1789 + if (aligned == port->aligned)
1790 + return; /* no change */
1791 + if (printk_ratelimit())
1792 + printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
1793 + " first)\n", port->id, port->frame_sync_offset,
1794 + aligned == EVEN_FIRST ? "even" : "odd");
1795 + port->aligned = aligned;
1796 +
1797 + atomic_inc(&port->chan_tx_irq_number);
1798 + wake_up_interruptible(&port->chan_tx_waitq);
1799 + atomic_inc(&port->chan_rx_irq_number);
1800 + wake_up_interruptible(&port->chan_rx_waitq);
1801 + return;
1802 + }
1803 +
1804 + /* not aligned */
1805 + if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
1806 + printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
1807 + port->aligned = NOT_ALIGNED;
1808 +#if DEBUG_FRAMER
1809 + for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
1810 + printk("%c%02X%s", cnt == offset ? '>' : ' ',
1811 + chan_rx_buf(port)[cnt],
1812 + (cnt + 1) % 32 ? "" : "\n");
1813 +#endif
1814 +
1815 + for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
1816 + if (port->chan_devices[cnt]) {
1817 + set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
1818 + ->errors_bitmap);
1819 + set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
1820 + ->errors_bitmap);
1821 + }
1822 + atomic_inc(&port->chan_tx_irq_number);
1823 + wake_up_interruptible(&port->chan_tx_waitq);
1824 + atomic_inc(&port->chan_rx_irq_number);
1825 + wake_up_interruptible(&port->chan_rx_waitq);
1826 + }
1827 +
1828 + if (is_first)
1829 + return;
1830 +
1831 + zeros_even = zeros_odd = 0;
1832 + ones_even = ones_odd = 0xFF;
1833 + for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
1834 + zeros_even |= data[frame];
1835 + zeros_odd |= data[frame + 1];
1836 + ones_even &= data[frame];
1837 + ones_odd &= data[frame + 1];
1838 + }
1839 +
1840 + for (bit = 0; bit < 7; bit++) {
1841 + if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
1842 + (ones_odd & 0x40) == 0x40) {
1843 + aligned = EVEN_FIRST; /* maybe */
1844 + break;
1845 + }
1846 + if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
1847 + (ones_even & 0x40) == 0x40) {
1848 + aligned = ODD_FIRST; /* maybe */
1849 + break;
1850 + }
1851 + zeros_even <<= 1;
1852 + ones_even = ones_even << 1 | 1;
1853 + zeros_odd <<= 1;
1854 + ones_odd = ones_odd << 1 | 1;
1855 + }
1856 +
1857 + port->frame_sync_offset += port->frame_size - bit;
1858 + port->frame_sync_offset %= port->frame_size;
1859 + port->just_set_offset = 1;
1860 +
1861 +#if DEBUG_FRAMER
1862 + if (bit == 7)
1863 + printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
1864 + port->id, port->frame_sync_offset);
1865 + else
1866 + printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
1867 + " %u (%s frame first)\n", port->id,
1868 + port->frame_sync_offset,
1869 + aligned == EVEN_FIRST ? "even" : "odd");
1870 +#endif
1871 +
1872 + hss_config_set_rx_frame(port);
1873 + hss_config_load(port);
1874 +}
1875 +
1876 +static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
1877 +{
1878 + /* in bytes */
1879 + unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
1880 + unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
1881 + int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
1882 +
1883 + offset *= list_len;
1884 + eaten = sub_offset(offset, last_offset, buff_len);
1885 +
1886 + if (chan_dev->tx_count > eaten + 2 * list_len) {
1887 + /* two pages must be reserved for the transmitter */
1888 + chan_dev->tx_first += eaten;
1889 + chan_dev->tx_first %= buff_len;
1890 + chan_dev->tx_count -= eaten;
1891 + } else {
1892 + /* FIXME check
1893 + 0
1894 + 1 tx_first (may still be transmited)
1895 + 2 tx_offset (currently reported by the NPE)
1896 + 3 tx_first + 2 * list_len (free to write here)
1897 + 4
1898 + 5
1899 + */
1900 +
1901 + /* printk(KERN_DEBUG "TX buffer underflow\n"); */
1902 + chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
1903 + chan_dev->tx_count = 2 * list_len; /* reserve */
1904 + set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
1905 + }
1906 +}
1907 +
1908 +static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
1909 +{
1910 + /* in bytes */
1911 + unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
1912 + unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
1913 + int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
1914 +
1915 + offset *= chan_dev->chan_count;
1916 + chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
1917 + buff_len) + trig_len;
1918 + if (chan_dev->rx_count > buff_len - 2 * trig_len) {
1919 + /* two pages - offset[0] and offset[1] are lost - FIXME check */
1920 + /* printk(KERN_DEBUG "RX buffer overflow\n"); */
1921 + chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
1922 + chan_dev->rx_count = buff_len - 2 * trig_len;
1923 + set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
1924 + }
1925 +}
1926 +
1927 +static void hss_chan_irq(void *pdev)
1928 +{
1929 + struct port *port = pdev;
1930 + u32 v;
1931 +
1932 +#if DEBUG_RX
1933 + printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
1934 +#endif
1935 + spin_lock(&npe_lock);
1936 + while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
1937 + unsigned int first, errors, tx_list, rx_frame;
1938 + int i, bad;
1939 +
1940 + first = v >> 24;
1941 + errors = (v >> 16) & 0xFF;
1942 + tx_list = (v >> 8) & 0xFF;
1943 + rx_frame = v & 0xFF;
1944 +
1945 + if (port->msg_count) {
1946 + printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
1947 + " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
1948 + " 0x%02X\n", port->id, jiffies, first, errors,
1949 + tx_list, rx_frame);
1950 + port->msg_count--;
1951 + }
1952 +
1953 + BUG_ON(rx_frame % CHAN_RX_TRIGGER);
1954 + BUG_ON(rx_frame >= CHAN_RX_FRAMES);
1955 + BUG_ON(tx_list >= CHAN_TX_LISTS);
1956 +
1957 + bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
1958 + if (!bad && tx_list != port->chan_last_tx) {
1959 + if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
1960 + printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
1961 + " current %i\n", port->chan_last_tx,
1962 + tx_list);
1963 + for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1964 + if (!port->chan_devices[i] ||
1965 + !port->chan_devices[i]->open_count)
1966 + continue;
1967 + chan_process_tx_irq(port->chan_devices[i],
1968 + tx_list);
1969 + }
1970 + atomic_inc(&port->chan_tx_irq_number);
1971 +#if 0
1972 + printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
1973 + jiffies, errors);
1974 +#endif
1975 + wake_up_interruptible(&port->chan_tx_waitq);
1976 + }
1977 +
1978 + if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
1979 + CHAN_RX_FRAMES)
1980 + printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
1981 + " current %i\n", port->chan_last_rx, rx_frame);
1982 +
1983 + if (port->mode == MODE_G704)
1984 + g704_rx_framer(port, rx_frame);
1985 +
1986 + if (!bad &&
1987 + (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
1988 + for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1989 + if (!port->chan_devices[i] ||
1990 + !port->chan_devices[i]->open_count)
1991 + continue;
1992 + chan_process_rx_irq(port->chan_devices[i],
1993 + rx_frame);
1994 + }
1995 + atomic_inc(&port->chan_rx_irq_number);
1996 + wake_up_interruptible(&port->chan_rx_waitq);
1997 + }
1998 + port->chan_last_tx = tx_list;
1999 + port->chan_last_rx = rx_frame;
2000 + }
2001 + spin_unlock(&npe_lock);
2002 +}
2003 +
2004 +
2005 +static int hss_prepare_chan(struct port *port)
2006 +{
2007 + int err;
2008 +
2009 + if ((err = hss_config_load_firmware(port)))
2010 + return err;
2011 +
2012 + if ((err = qmgr_request_queue(queue_ids[port->id].chan,
2013 + CHAN_QUEUE_LEN, 0, 0)))
2014 + return err;
2015 +
2016 + if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
2017 + chan_tx_lists_len(port) +
2018 + chan_rx_buf_len(port), GFP_KERNEL))) {
2019 + goto release_queue;
2020 + err = -ENOBUFS;
2021 + }
2022 +
2023 + port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
2024 + chan_tx_buf_len(port) +
2025 + chan_tx_lists_len(port),
2026 + DMA_TO_DEVICE);
2027 + if (dma_mapping_error(port->chan_tx_buf_phys)) {
2028 + err = -EIO;
2029 + goto free;
2030 + }
2031 +
2032 + port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
2033 + chan_rx_buf_len(port),
2034 + DMA_FROM_DEVICE);
2035 + if (dma_mapping_error(port->chan_rx_buf_phys)) {
2036 + err = -EIO;
2037 + goto unmap_tx;
2038 + }
2039 +
2040 + qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
2041 + hss_chan_irq, port);
2042 + qmgr_enable_irq(queue_ids[port->id].chan);
2043 + hss_chan_irq(port);
2044 + return 0;
2045 +
2046 +unmap_tx:
2047 + dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2048 + chan_tx_buf_len(port) + chan_tx_lists_len(port),
2049 + DMA_TO_DEVICE);
2050 +free:
2051 + kfree(port->chan_buf);
2052 + port->chan_buf = NULL;
2053 +release_queue:
2054 + qmgr_release_queue(queue_ids[port->id].chan);
2055 + return err;
2056 +}
2057 +
2058 +void hss_chan_stop(struct port *port)
2059 +{
2060 + if (!port->chan_open_count && !port->hdlc_open)
2061 + qmgr_disable_irq(queue_ids[port->id].chan);
2062 +
2063 + hss_config_stop_chan(port);
2064 + hss_config_set_lut(port);
2065 + hss_config_load(port);
2066 +
2067 + if (!port->chan_open_count && !port->hdlc_open) {
2068 + dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2069 + chan_tx_buf_len(port) +
2070 + chan_tx_lists_len(port), DMA_TO_DEVICE);
2071 + dma_unmap_single(port->dev, port->chan_rx_buf_phys,
2072 + chan_rx_buf_len(port), DMA_FROM_DEVICE);
2073 + kfree(port->chan_buf);
2074 + port->chan_buf = NULL;
2075 + qmgr_release_queue(queue_ids[port->id].chan);
2076 + }
2077 +}
2078 +
2079 +static int hss_chan_open(struct inode *inode, struct file *file)
2080 +{
2081 + struct chan_device *chan_dev = inode_to_chan_dev(inode);
2082 + struct port *port = chan_dev->port;
2083 + unsigned long flags;
2084 + int i, err = 0;
2085 +
2086 + spin_lock_irqsave(&npe_lock, flags);
2087 +
2088 + if (chan_dev->open_count) {
2089 + if (chan_dev->excl_open || (file->f_flags & O_EXCL))
2090 + err = -EBUSY;
2091 + else
2092 + chan_dev->open_count++;
2093 + goto out;
2094 + }
2095 +
2096 + if (port->mode == MODE_HDLC) {
2097 + err = -ENOSYS;
2098 + goto out;
2099 + }
2100 +
2101 + if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
2102 + err = -EBUSY; /* channel #0 is used for G.704 signaling */
2103 + goto out;
2104 + }
2105 + for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
2106 + if (port->channels[i - 1] == chan_dev->id) {
2107 + err = -ECHRNG; /* frame too short */
2108 + goto out;
2109 + }
2110 +
2111 + chan_dev->rx_first = chan_dev->tx_first = 0;
2112 + chan_dev->rx_count = chan_dev->tx_count = 0;
2113 + clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
2114 + clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
2115 +
2116 + if (!port->chan_open_count && !port->hdlc_open) {
2117 + if (port->plat->open)
2118 + if ((err = port->plat->open(port->id, port->netdev,
2119 + hss_hdlc_set_carrier)))
2120 + goto out;
2121 + if ((err = hss_prepare_chan(port))) {
2122 + if (port->plat->close)
2123 + port->plat->close(port->id, port->netdev);
2124 + goto out;
2125 + }
2126 + }
2127 +
2128 + hss_config_stop_chan(port);
2129 + chan_dev->open_count++;
2130 + port->chan_open_count++;
2131 + chan_dev->excl_open = !!file->f_flags & O_EXCL;
2132 +
2133 + hss_config_set_lut(port);
2134 + hss_config_load(port);
2135 + hss_config_start_chan(port);
2136 +out:
2137 + spin_unlock_irqrestore(&npe_lock, flags);
2138 + return err;
2139 +}
2140 +
2141 +static int hss_chan_release(struct inode *inode, struct file *file)
2142 +{
2143 + struct chan_device *chan_dev = inode_to_chan_dev(inode);
2144 + struct port *port = chan_dev->port;
2145 + unsigned long flags;
2146 +
2147 + spin_lock_irqsave(&npe_lock, flags);
2148 +
2149 + if (!--chan_dev->open_count) {
2150 + if (!--port->chan_open_count && !port->hdlc_open) {
2151 + hss_chan_stop(port);
2152 + if (port->plat->close)
2153 + port->plat->close(port->id, port->netdev);
2154 + } else {
2155 + hss_config_stop_chan(port);
2156 + hss_config_set_lut(port);
2157 + hss_config_set_line(port); //
2158 + hss_config_start_chan(port);
2159 + }
2160 + }
2161 +
2162 + spin_unlock_irqrestore(&npe_lock, flags);
2163 + return 0;
2164 +}
2165 +
2166 +static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
2167 + loff_t *f_pos)
2168 +{
2169 + struct chan_device *chan_dev = inode_to_chan_dev
2170 + (file->f_path.dentry->d_inode);
2171 + struct port *port = chan_dev->port;
2172 + unsigned long flags;
2173 + u8 *rx_buf;
2174 + int res = 0, loops = 0;
2175 +
2176 + spin_lock_irqsave(&npe_lock, flags);
2177 +
2178 + while (1) {
2179 + int prev_irq = atomic_read(&port->chan_rx_irq_number);
2180 +#if 0
2181 + if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
2182 + || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2183 + res = -EIO;
2184 + goto out;
2185 + }
2186 +#endif
2187 + if (count == 0)
2188 + goto out; /* no need to wait */
2189 +
2190 + if (chan_dev->rx_count)
2191 + break;
2192 +
2193 + spin_unlock_irqrestore(&npe_lock, flags);
2194 + loops++;
2195 + if ((res = wait_event_interruptible
2196 + (port->chan_rx_waitq,
2197 + atomic_read(&port->chan_rx_irq_number) != prev_irq)))
2198 + goto out;
2199 + spin_lock_irqsave(&npe_lock, flags);
2200 + continue;
2201 + }
2202 +
2203 + dma_sync_single(port->dev, port->chan_rx_buf_phys,
2204 + chan_rx_buf_len(port), DMA_FROM_DEVICE);
2205 +
2206 +#if 0
2207 + if (loops > 1)
2208 + printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
2209 + " last_rx %u loops %i\n", chan_dev->rx_first,
2210 + chan_dev->rx_count, count, port->chan_last_rx, loops);
2211 +#endif
2212 + rx_buf = chan_rx_buf(port);
2213 + while (chan_dev->rx_count > 0 && res < count) {
2214 + unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
2215 + unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
2216 +
2217 + chan = chan_dev->log_channels[chan];
2218 + if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
2219 + res = -EFAULT;
2220 + goto out;
2221 + }
2222 + chan_dev->rx_first++;
2223 + chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
2224 + chan_dev->rx_count--;
2225 + res++;
2226 + }
2227 +out:
2228 +#if 0
2229 + printk(KERN_DEBUG "EXIT rx_first %u rx_count %u res %i\n",
2230 + chan_dev->rx_first, chan_dev->rx_count, res);
2231 +#endif
2232 + spin_unlock_irqrestore(&npe_lock, flags);
2233 + return res;
2234 +}
2235 +
2236 +static ssize_t hss_chan_write(struct file *file, const char __user *buf,
2237 + size_t count, loff_t *f_pos)
2238 +{
2239 + struct chan_device *chan_dev = inode_to_chan_dev
2240 + (file->f_path.dentry->d_inode);
2241 + struct port *port = chan_dev->port;
2242 + unsigned long flags;
2243 + u8 *tx_buf;
2244 + int res = 0, loops = 0;
2245 +
2246 + spin_lock_irqsave(&npe_lock, flags);
2247 + while (1) {
2248 + int prev_irq = atomic_read(&port->chan_tx_irq_number);
2249 +#if 0
2250 + if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
2251 + || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2252 + res = -EIO;
2253 + goto out;
2254 + }
2255 +#endif
2256 + if (count == 0)
2257 + goto out; /* no need to wait */
2258 +
2259 + if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2260 + break;
2261 +
2262 + spin_unlock_irqrestore(&npe_lock, flags);
2263 + loops++;
2264 + if ((res = wait_event_interruptible
2265 + (port->chan_tx_waitq,
2266 + atomic_read (&port->chan_tx_irq_number) != prev_irq)))
2267 + goto out;
2268 + spin_lock_irqsave(&npe_lock, flags);
2269 + continue;
2270 + }
2271 +
2272 +#if 0
2273 + if (loops > 1)
2274 + printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
2275 + " last_tx %u loops %i\n", chan_dev->tx_first,
2276 + chan_dev->tx_count, count, port->chan_last_tx, loops);
2277 +#endif
2278 + tx_buf = chan_tx_buf(port);
2279 + while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
2280 + res < count) {
2281 + unsigned int tail, chan, frame;
2282 +
2283 + tail = (chan_dev->tx_first + chan_dev->tx_count) %
2284 + (CHAN_TX_FRAMES * chan_dev->chan_count);
2285 + chan = tail % chan_dev->chan_count;
2286 + frame = tail / chan_dev->chan_count;
2287 + chan = chan_dev->log_channels[chan];
2288 +
2289 + if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
2290 + printk(KERN_DEBUG "BUG? TX %u %u %u\n",
2291 + tail, chan, frame);
2292 + res = -EFAULT;
2293 + goto out_sync;
2294 + }
2295 + chan_dev->tx_count++;
2296 + res++;
2297 + }
2298 +out_sync:
2299 + dma_sync_single(port->dev, port->chan_tx_buf_phys,
2300 + chan_tx_buf_len(port), DMA_TO_DEVICE);
2301 +out:
2302 +#if 0
2303 + printk(KERN_DEBUG "EXIT TX_first %u tx_count %u res %i\n",
2304 + chan_dev->tx_first, chan_dev->tx_count, res);
2305 +#endif
2306 + spin_unlock_irqrestore(&npe_lock, flags);
2307 + return res;
2308 +}
2309 +
2310 +
2311 +static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
2312 +{
2313 + struct chan_device *chan_dev = inode_to_chan_dev
2314 + (file->f_path.dentry->d_inode);
2315 + struct port *port = chan_dev->port;
2316 + unsigned long flags;
2317 + unsigned int mask = 0;
2318 +
2319 + spin_lock_irqsave(&npe_lock, flags);
2320 + poll_wait(file, &port->chan_tx_waitq, wait);
2321 + poll_wait(file, &port->chan_rx_waitq, wait);
2322 +
2323 + if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2324 + mask |= POLLOUT | POLLWRNORM;
2325 + if (chan_dev->rx_count)
2326 + mask |= POLLIN | POLLRDNORM;
2327 + spin_unlock_irqrestore(&npe_lock, flags);
2328 + return mask;
2329 +}
2330 +
2331 +/*****************************************************************************
2332 + * channelized device sysfs attributes
2333 + ****************************************************************************/
2334 +
2335 +static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
2336 + char *buf)
2337 +{
2338 + struct chan_device *chan_dev = dev_get_drvdata(dev);
2339 +
2340 + return print_channels(chan_dev->port, buf, chan_dev->id);
2341 +}
2342 +
2343 +static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
2344 + const char *buf, size_t len)
2345 +{
2346 + struct chan_device *chan_dev = dev_get_drvdata(dev);
2347 + struct port *port = chan_dev->port;
2348 + unsigned long flags;
2349 + unsigned int ch;
2350 + size_t orig_len = len;
2351 + int err;
2352 +
2353 + if (len && buf[len - 1] == '\n')
2354 + len--;
2355 +
2356 + if (len != 7 || memcmp(buf, "destroy", 7))
2357 + return -EINVAL;
2358 +
2359 + spin_lock_irqsave(&npe_lock, flags);
2360 + cdev_del(&chan_dev->cdev);
2361 +
2362 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2363 + if (port->channels[ch] == chan_dev->id)
2364 + port->channels[ch] = CHANNEL_UNUSED;
2365 + port->chan_devices[chan_dev->id] = NULL;
2366 + kfree(chan_dev);
2367 + spin_unlock_irqrestore(&npe_lock, flags);
2368 +
2369 + if ((err = device_schedule_callback(dev, device_unregister)))
2370 + return err;
2371 + return orig_len;
2372 +}
2373 +
2374 +static struct device_attribute chan_attr =
2375 + __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
2376 +
2377 +/*****************************************************************************
2378 + * main sysfs attributes
2379 + ****************************************************************************/
2380 +
2381 +static const struct file_operations chan_fops = {
2382 + .owner = THIS_MODULE,
2383 + .llseek = no_llseek,
2384 + .read = hss_chan_read,
2385 + .write = hss_chan_write,
2386 + .poll = hss_chan_poll,
2387 + .open = hss_chan_open,
2388 + .release = hss_chan_release,
2389 +};
2390 +
2391 +static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
2392 + const char *buf, size_t len)
2393 +{
2394 + struct port *port = dev_get_drvdata(dev);
2395 + struct chan_device *chan_dev;
2396 + u8 channels[MAX_CHANNELS];
2397 + size_t orig_len = len;
2398 + unsigned long flags;
2399 + unsigned int ch, id;
2400 + int minor, err;
2401 +
2402 + if ((err = parse_channels(&buf, &len, channels)) < 1)
2403 + return err;
2404 +
2405 + if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
2406 + return -ENOBUFS;
2407 +
2408 + spin_lock_irqsave(&npe_lock, flags);
2409 +
2410 + if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2411 + err = -EINVAL;
2412 + goto free;
2413 + }
2414 +
2415 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2416 + if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
2417 + printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2418 + err = -EBUSY;
2419 + goto free;
2420 + }
2421 +
2422 + for (id = 0; id < MAX_CHAN_DEVICES; id++)
2423 + if (port->chan_devices[id] == NULL)
2424 + break;
2425 +
2426 + if (id == MAX_CHAN_DEVICES) {
2427 + err = -EBUSY;
2428 + goto free;
2429 + }
2430 +
2431 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2432 + if (channels[ch])
2433 + break;
2434 +
2435 + minor = port->id * MAX_CHAN_DEVICES + ch;
2436 + chan_dev->id = id;
2437 + chan_dev->port = port;
2438 + chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
2439 + "hss%uch%u", port->id, ch);
2440 + if (IS_ERR(chan_dev->dev)) {
2441 + err = PTR_ERR(chan_dev->dev);
2442 + goto free;
2443 + }
2444 +
2445 + cdev_init(&chan_dev->cdev, &chan_fops);
2446 + chan_dev->cdev.owner = THIS_MODULE;
2447 + if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
2448 + goto destroy_device;
2449 +
2450 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2451 + if (channels[ch])
2452 + port->channels[ch] = id;
2453 + port->chan_devices[id] = chan_dev;
2454 + dev_set_drvdata(chan_dev->dev, chan_dev);
2455 + BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
2456 +
2457 + spin_unlock_irqrestore(&npe_lock, flags);
2458 + return orig_len;
2459 +
2460 +destroy_device:
2461 + device_unregister(chan_dev->dev);
2462 +free:
2463 + kfree(chan_dev);
2464 + spin_unlock_irqrestore(&npe_lock, flags);
2465 + return err;
2466 +}
2467 +
2468 +static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
2469 + char *buf)
2470 +{
2471 + return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
2472 +}
2473 +
2474 +static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
2475 + const char *buf, size_t len)
2476 +{
2477 + struct port *port = dev_get_drvdata(dev);
2478 + u8 channels[MAX_CHANNELS];
2479 + size_t orig_len = len;
2480 + unsigned long flags;
2481 + unsigned int ch;
2482 + int err;
2483 +
2484 + if ((err = parse_channels(&buf, &len, channels)) < 0)
2485 + return err;
2486 +
2487 + spin_lock_irqsave(&npe_lock, flags);
2488 +
2489 + if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2490 + err = -EINVAL;
2491 + goto err;
2492 + }
2493 +
2494 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2495 + if (channels[ch] &&
2496 + port->channels[ch] != CHANNEL_UNUSED &&
2497 + port->channels[ch] != CHANNEL_HDLC) {
2498 + printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2499 + err = -EBUSY;
2500 + goto err;
2501 + }
2502 +
2503 + for (ch = 0; ch < MAX_CHANNELS; ch++)
2504 + if (channels[ch])
2505 + port->channels[ch] = CHANNEL_HDLC;
2506 + else if (port->channels[ch] == CHANNEL_HDLC)
2507 + port->channels[ch] = CHANNEL_UNUSED;
2508 +
2509 + if (port->chan_open_count || port->hdlc_open) {
2510 + hss_config_set_lut(port);
2511 + hss_config_load(port);
2512 + }
2513 +
2514 + spin_unlock_irqrestore(&npe_lock, flags);
2515 + return orig_len;
2516 +
2517 +err:
2518 + spin_unlock_irqrestore(&npe_lock, flags);
2519 + return err;
2520 +}
2521 +
2522 +static ssize_t show_clock_type(struct device *dev,
2523 + struct device_attribute *attr, char *buf)
2524 +{
2525 + struct port *port = dev_get_drvdata(dev);
2526 +
2527 + strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
2528 + return 5;
2529 +}
2530 +
2531 +static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
2532 + const char *buf, size_t len)
2533 +{
2534 + struct port *port = dev_get_drvdata(dev);
2535 + size_t orig_len = len;
2536 + unsigned long flags;
2537 + unsigned int clk, err;
2538 +
2539 + if (len && buf[len - 1] == '\n')
2540 + len--;
2541 +
2542 + if (len != 3)
2543 + return -EINVAL;
2544 + if (!memcmp(buf, "ext", 3))
2545 + clk = CLOCK_EXT;
2546 + else if (!memcmp(buf, "int", 3))
2547 + clk = CLOCK_INT;
2548 + else
2549 + return -EINVAL;
2550 +
2551 + spin_lock_irqsave(&npe_lock, flags);
2552 + if (port->plat->set_clock)
2553 + clk = port->plat->set_clock(port->id, clk);
2554 + if (clk != CLOCK_EXT && clk != CLOCK_INT) {
2555 + err = -EINVAL; /* plat->set_clock shouldn't change the state */
2556 + goto err;
2557 + }
2558 + port->clock_type = clk;
2559 + if (port->chan_open_count || port->hdlc_open) {
2560 + hss_config_set_line(port);
2561 + hss_config_load(port);
2562 + }
2563 + spin_unlock_irqrestore(&npe_lock, flags);
2564 +
2565 + return orig_len;
2566 +err:
2567 + spin_unlock_irqrestore(&npe_lock, flags);
2568 + return err;
2569 +}
2570 +
2571 +static ssize_t show_clock_rate(struct device *dev,
2572 + struct device_attribute *attr, char *buf)
2573 +{
2574 + struct port *port = dev_get_drvdata(dev);
2575 +
2576 + sprintf(buf, "%u\n", port->clock_rate);
2577 + return strlen(buf) + 1;
2578 +}
2579 +
2580 +static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
2581 + const char *buf, size_t len)
2582 +{
2583 +#if 0
2584 + struct port *port = dev_get_drvdata(dev);
2585 + size_t orig_len = len;
2586 + unsigned long flags;
2587 + unsigned int rate;
2588 +
2589 + if (len && buf[len - 1] == '\n')
2590 + len--;
2591 +
2592 + if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
2593 + return -EINVAL;
2594 + if (len)
2595 + return -EINVAL;
2596 +
2597 + spin_lock_irqsave(&npe_lock, flags);
2598 + port->clock_rate = rate;
2599 + spin_unlock_irqrestore(&npe_lock, flags);
2600 + return orig_len;
2601 +#endif
2602 + return -EINVAL; /* FIXME not yet supported */
2603 +}
2604 +
2605 +static ssize_t show_frame_size(struct device *dev,
2606 + struct device_attribute *attr, char *buf)
2607 +{
2608 + struct port *port = dev_get_drvdata(dev);
2609 +
2610 + if (port->mode != MODE_RAW && port->mode != MODE_G704)
2611 + return -EINVAL;
2612 +
2613 + sprintf(buf, "%u\n", port->frame_size);
2614 + return strlen(buf) + 1;
2615 +}
2616 +
2617 +static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
2618 + const char *buf, size_t len)
2619 +{
2620 + struct port *port = dev_get_drvdata(dev);
2621 + size_t ret = len;
2622 + unsigned long flags;
2623 + unsigned int size;
2624 +
2625 + if (len && buf[len - 1] == '\n')
2626 + len--;
2627 +
2628 + if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
2629 + return -EINVAL;
2630 + if (len || size % 8 > 1)
2631 + return -EINVAL;
2632 +
2633 + spin_lock_irqsave(&npe_lock, flags);
2634 + if (port->mode != MODE_RAW && port->mode != MODE_G704)
2635 + ret = -EINVAL;
2636 + else if (!port->chan_open_count && !port->hdlc_open)
2637 + ret = -EBUSY;
2638 + else {
2639 + port->frame_size = size;
2640 + port->frame_sync_offset = 0;
2641 + }
2642 + spin_unlock_irqrestore(&npe_lock, flags);
2643 + return ret;
2644 +}
2645 +
2646 +static ssize_t show_frame_offset(struct device *dev,
2647 + struct device_attribute *attr, char *buf)
2648 +{
2649 + struct port *port = dev_get_drvdata(dev);
2650 +
2651 + sprintf(buf, "%u\n", port->frame_sync_offset);
2652 + return strlen(buf) + 1;
2653 +}
2654 +
2655 +static ssize_t set_frame_offset(struct device *dev,
2656 + struct device_attribute *attr,
2657 + const char *buf, size_t len)
2658 +{
2659 + struct port *port = dev_get_drvdata(dev);
2660 + size_t orig_len = len;
2661 + unsigned long flags;
2662 + unsigned int offset;
2663 +
2664 + if (len && buf[len - 1] == '\n')
2665 + len--;
2666 +
2667 + if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
2668 + return -EINVAL;
2669 + if (len)
2670 + return -EINVAL;
2671 +
2672 + spin_lock_irqsave(&npe_lock, flags);
2673 +
2674 + port->frame_sync_offset = offset;
2675 + if (port->chan_open_count || port->hdlc_open) {
2676 + hss_config_set_rx_frame(port);
2677 + hss_config_load(port);
2678 + }
2679 +
2680 + spin_unlock_irqrestore(&npe_lock, flags);
2681 + return orig_len;
2682 +}
2683 +
2684 +static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
2685 + char *buf)
2686 +{
2687 + struct port *port = dev_get_drvdata(dev);
2688 +
2689 + sprintf(buf, "%u\n", port->loopback);
2690 + return strlen(buf) + 1;
2691 +}
2692 +
2693 +static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
2694 + const char *buf, size_t len)
2695 +{
2696 + struct port *port = dev_get_drvdata(dev);
2697 + size_t orig_len = len;
2698 + unsigned long flags;
2699 + unsigned int lb;
2700 +
2701 + if (len && buf[len - 1] == '\n')
2702 + len--;
2703 +
2704 + if (get_number(&buf, &len, &lb, 0, 1))
2705 + return -EINVAL;
2706 + if (len)
2707 + return -EINVAL;
2708 +
2709 + spin_lock_irqsave(&npe_lock, flags);
2710 +
2711 + if (port->loopback != lb) {
2712 + port->loopback = lb;
2713 + if (port->chan_open_count || port->hdlc_open) {
2714 + hss_config_set_core(port);
2715 + hss_config_load(port);
2716 + }
2717 + if (port->loopback || port->carrier)
2718 + netif_carrier_on(port->netdev);
2719 + else
2720 + netif_carrier_off(port->netdev);
2721 + }
2722 +
2723 + spin_unlock_irqrestore(&npe_lock, flags);
2724 + return orig_len;
2725 +}
2726 +
2727 +static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
2728 + char *buf)
2729 +{
2730 + struct port *port = dev_get_drvdata(dev);
2731 +
2732 + switch(port->mode) {
2733 + case MODE_RAW:
2734 + strcpy(buf, "raw\n");
2735 + break;
2736 + case MODE_G704:
2737 + strcpy(buf, "g704\n");
2738 + break;
2739 + default:
2740 + strcpy(buf, "hdlc\n");
2741 + break;
2742 + }
2743 + return strlen(buf) + 1;
2744 +}
2745 +
2746 +static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
2747 + const char *buf, size_t len)
2748 +{
2749 + struct port *port = dev_get_drvdata(dev);
2750 + size_t ret = len;
2751 + unsigned long flags;
2752 +
2753 + if (len && buf[len - 1] == '\n')
2754 + len--;
2755 +
2756 + spin_lock_irqsave(&npe_lock, flags);
2757 +
2758 + if (port->chan_open_count || port->hdlc_open) {
2759 + ret = -EBUSY;
2760 + } else if (len == 4 && !memcmp(buf, "hdlc", 4))
2761 + port->mode = MODE_HDLC;
2762 + else if (len == 3 && !memcmp(buf, "raw", 3))
2763 + port->mode = MODE_RAW;
2764 + else if (len == 4 && !memcmp(buf, "g704", 4))
2765 + port->mode = MODE_G704;
2766 + else
2767 + ret = -EINVAL;
2768 +
2769 + spin_unlock_irqrestore(&npe_lock, flags);
2770 + return ret;
2771 +}
2772 +
2773 +static struct device_attribute hss_attrs[] = {
2774 + __ATTR(create_chan, 0200, NULL, create_chan),
2775 + __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
2776 + __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
2777 + __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
2778 + __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
2779 + __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
2780 + __ATTR(loopback, 0644, show_loopback, set_loopback),
2781 + __ATTR(mode, 0644, show_mode, set_mode),
2782 +};
2783 +
2784 +/*****************************************************************************
2785 + * initialization
2786 + ****************************************************************************/
2787 +
2788 +static int __devinit hss_init_one(struct platform_device *pdev)
2789 +{
2790 + struct port *port;
2791 + struct net_device *dev;
2792 + hdlc_device *hdlc;
2793 + int i, err;
2794 +
2795 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
2796 + return -ENOMEM;
2797 + platform_set_drvdata(pdev, port);
2798 + port->id = pdev->id;
2799 +
2800 + if ((port->npe = npe_request(0)) == NULL) {
2801 + err = -ENOSYS;
2802 + goto err_free;
2803 + }
2804 +
2805 + port->dev = &pdev->dev;
2806 + port->plat = pdev->dev.platform_data;
2807 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
2808 + err = -ENOMEM;
2809 + goto err_plat;
2810 + }
2811 +
2812 + SET_NETDEV_DEV(dev, &pdev->dev);
2813 + hdlc = dev_to_hdlc(dev);
2814 + hdlc->attach = hss_hdlc_attach;
2815 + hdlc->xmit = hss_hdlc_xmit;
2816 + dev->open = hss_hdlc_open;
2817 + dev->stop = hss_hdlc_close;
2818 + dev->do_ioctl = hss_hdlc_ioctl;
2819 + dev->tx_queue_len = 100;
2820 + port->clock_type = CLOCK_EXT;
2821 + port->clock_rate = 2048000;
2822 + port->frame_size = 256; /* E1 */
2823 + memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
2824 + init_waitqueue_head(&port->chan_tx_waitq);
2825 + init_waitqueue_head(&port->chan_rx_waitq);
2826 + netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
2827 +
2828 + if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
2829 + goto err_free_netdev;
2830 +
2831 + for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2832 + BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
2833 +
2834 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
2835 + return 0;
2836 +
2837 +err_free_netdev:
2838 + free_netdev(dev);
2839 +err_plat:
2840 + npe_release(port->npe);
2841 + platform_set_drvdata(pdev, NULL);
2842 +err_free:
2843 + kfree(port);
2844 + return err;
2845 +}
2846 +
2847 +static int __devexit hss_remove_one(struct platform_device *pdev)
2848 +{
2849 + struct port *port = platform_get_drvdata(pdev);
2850 + int i;
2851 +
2852 + for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2853 + device_remove_file(port->dev, &hss_attrs[i]);
2854 +
2855 + unregister_hdlc_device(port->netdev);
2856 + free_netdev(port->netdev);
2857 + npe_release(port->npe);
2858 + platform_set_drvdata(pdev, NULL);
2859 + kfree(port);
2860 + return 0;
2861 +}
2862 +
2863 +static struct platform_driver drv = {
2864 + .driver.name = DRV_NAME,
2865 + .probe = hss_init_one,
2866 + .remove = hss_remove_one,
2867 +};
2868 +
2869 +static int __init hss_init_module(void)
2870 +{
2871 + int err;
2872 + dev_t rdev;
2873 +
2874 + if ((ixp4xx_read_feature_bits() &
2875 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
2876 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
2877 + return -ENOSYS;
2878 +
2879 + if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
2880 + "hss")))
2881 + return err;
2882 +
2883 + spin_lock_init(&npe_lock);
2884 +
2885 + if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
2886 + printk(KERN_ERR "Can't register device class 'hss'\n");
2887 + err = PTR_ERR(hss_class);
2888 + goto free_chrdev;
2889 + }
2890 + if ((err = platform_driver_register(&drv)))
2891 + goto destroy_class;
2892 +
2893 + chan_major = MAJOR(rdev);
2894 + return 0;
2895 +
2896 +destroy_class:
2897 + class_destroy(hss_class);
2898 +free_chrdev:
2899 + unregister_chrdev_region(MKDEV(chan_major, 0),
2900 + HSS_COUNT * MAX_CHAN_DEVICES);
2901 + return err;
2902 +}
2903 +
2904 +static void __exit hss_cleanup_module(void)
2905 +{
2906 + platform_driver_unregister(&drv);
2907 + class_destroy(hss_class);
2908 + unregister_chrdev_region(MKDEV(chan_major, 0),
2909 + HSS_COUNT * MAX_CHAN_DEVICES);
2910 +}
2911 +
2912 +MODULE_AUTHOR("Krzysztof Halasa");
2913 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
2914 +MODULE_LICENSE("GPL v2");
2915 +MODULE_ALIAS("platform:ixp4xx_hss");
2916 +module_init(hss_init_module);
2917 +module_exit(hss_cleanup_module);
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