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add first batch of enrik's ar7 system code cleanups
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-10-21 16:43:16.316951500 +0200
3 +++ linux.dev/Makefile 2005-10-21 16:45:42.294074500 +0200
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
14 --- linux.old/arch/mips/Makefile 2005-10-21 16:43:16.316951500 +0200
15 +++ linux.dev/arch/mips/Makefile 2005-10-21 16:45:42.134064500 +0200
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o
25 +SUBDIRS += arch/mips/ar7
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
34 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
35 +++ linux.dev/arch/mips/ar7/Makefile 2005-10-21 17:02:14.507635750 +0200
36 @@ -0,0 +1,14 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
44 +O_TARGET := ar7.o
45 +
46 +obj-y := tnetd73xx_misc.o misc.o
47 +export-objs := misc.o irq.o init.o
48 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o psp_env.o memory.o printf.o cmdline.o time.o
49 +
50 +include $(TOPDIR)/Rules.make
51 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
52 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-10-21 16:45:42.090061750 +0200
54 @@ -0,0 +1,64 @@
55 +/*
56 + * Carsten Langgaard, carstenl@mips.com
57 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
58 + *
59 + * This program is free software; you can distribute it and/or modify it
60 + * under the terms of the GNU General Public License (Version 2) as
61 + * published by the Free Software Foundation.
62 + *
63 + * This program is distributed in the hope it will be useful, but WITHOUT
64 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
65 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
66 + * for more details.
67 + *
68 + * You should have received a copy of the GNU General Public License along
69 + * with this program; if not, write to the Free Software Foundation, Inc.,
70 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
71 + *
72 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
73 + */
74 +#include <linux/init.h>
75 +#include <linux/string.h>
76 +
77 +#include <asm/bootinfo.h>
78 +
79 +extern int prom_argc;
80 +extern int *_prom_argv;
81 +
82 +/*
83 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
84 + * This macro take care of sign extension.
85 + */
86 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
87 +
88 +char arcs_cmdline[CL_SIZE];
89 +
90 +char * __init prom_getcmdline(void)
91 +{
92 + return &(arcs_cmdline[0]);
93 +}
94 +
95 +
96 +void __init prom_init_cmdline(void)
97 +{
98 + char *cp;
99 + int actr;
100 +
101 + actr = 1; /* Always ignore argv[0] */
102 +
103 + cp = &(arcs_cmdline[0]);
104 +#ifdef CONFIG_CMDLINE_BOOL
105 + strcpy(cp, CONFIG_CMDLINE);
106 + cp += strlen(CONFIG_CMDLINE);
107 + *cp++ = ' ';
108 +#endif
109 + while(actr < prom_argc) {
110 + strcpy(cp, prom_argv(actr));
111 + cp += strlen(prom_argv(actr));
112 + *cp++ = ' ';
113 + actr++;
114 + }
115 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
116 + --cp;
117 + *cp = '\0';
118 +}
119 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
120 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
121 +++ linux.dev/arch/mips/ar7/init.c 2005-10-21 17:02:14.507635750 +0200
122 @@ -0,0 +1,199 @@
123 +/*
124 + * Carsten Langgaard, carstenl@mips.com
125 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
126 + *
127 + * This program is free software; you can distribute it and/or modify it
128 + * under the terms of the GNU General Public License (Version 2) as
129 + * published by the Free Software Foundation.
130 + *
131 + * This program is distributed in the hope it will be useful, but WITHOUT
132 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
133 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
134 + * for more details.
135 + *
136 + * You should have received a copy of the GNU General Public License along
137 + * with this program; if not, write to the Free Software Foundation, Inc.,
138 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
139 + *
140 + * PROM library initialisation code.
141 + */
142 +#include <linux/config.h>
143 +#include <linux/init.h>
144 +#include <linux/string.h>
145 +#include <linux/kernel.h>
146 +#include <linux/module.h>
147 +
148 +#include <asm/io.h>
149 +#include <asm/mips-boards/prom.h>
150 +#include <asm/mips-boards/generic.h>
151 +
152 +#include <asm/ar7/adam2_env.h>
153 +
154 +int prom_argc;
155 +int *_prom_argv, *_prom_envp;
156 +
157 +/* max # of Adam2 environment variables */
158 +#define MAX_ENV_ENTRY 80
159 +
160 +static t_env_var local_envp[MAX_ENV_ENTRY];
161 +static int env_type = 0;
162 +int init_debug = 0;
163 +
164 +unsigned int max_env_entry;
165 +
166 +extern char *prom_psp_getenv(char *envname);
167 +
168 +static inline char *prom_adam2_getenv(char *envname)
169 +{
170 + /*
171 + * Return a pointer to the given environment variable.
172 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
173 + * in the PROM structures are only 32-bit, so we need some
174 + * workarounds, if we are running in 64-bit mode.
175 + */
176 + int i;
177 + t_env_var *env = (t_env_var *) local_envp;
178 +
179 + if (strcmp("bootloader", envname) == 0)
180 + return "Adam2";
181 +
182 + i = strlen(envname);
183 + while (env->name) {
184 + if(strncmp(envname, env->name, i) == 0) {
185 + return(env->val);
186 + }
187 + env++;
188 + }
189 +
190 + return NULL;
191 +}
192 +
193 +/* XXX "bootloader" won't be returned.
194 + * Better make it an element of local_envp */
195 +static inline t_env_var *
196 +prom_adam2_iterenv(t_env_var *env) {
197 + if (!env)
198 + env = local_envp;
199 + else
200 + env++;
201 + if (env - local_envp > MAX_ENV_ENTRY || !env->name)
202 + return 0;
203 + return env;
204 +}
205 +
206 +char *prom_getenv(char *envname)
207 +{
208 + if (env_type == 1)
209 + return prom_psp_getenv(envname);
210 + else
211 + return prom_adam2_getenv(envname);
212 +}
213 +
214 +t_env_var *
215 +prom_iterenv(t_env_var *last)
216 +{
217 + if (env_type == 1)
218 + return 0; /* not yet implemented */
219 + return prom_adam2_iterenv(last);
220 +}
221 +
222 +static inline unsigned char str2hexnum(unsigned char c)
223 +{
224 + if (c >= '0' && c <= '9')
225 + return c - '0';
226 + if (c >= 'a' && c <= 'f')
227 + return c - 'a' + 10;
228 + return 0; /* foo */
229 +}
230 +
231 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
232 +{
233 + int i;
234 +
235 + for (i = 0; i < 6; i++) {
236 + unsigned char num;
237 +
238 + if((*str == '.') || (*str == ':'))
239 + str++;
240 + num = str2hexnum(*str++) << 4;
241 + num |= (str2hexnum(*str++));
242 + ea[i] = num;
243 + }
244 +}
245 +
246 +int get_ethernet_addr(char *ethernet_addr)
247 +{
248 + char *ethaddr_str;
249 +
250 + ethaddr_str = prom_getenv("ethaddr");
251 + if (!ethaddr_str) {
252 + printk("ethaddr not set in boot prom\n");
253 + return -1;
254 + }
255 + str2eaddr(ethernet_addr, ethaddr_str);
256 +
257 + if (init_debug > 1) {
258 + int i;
259 + printk("get_ethernet_addr: ");
260 + for (i=0; i<5; i++)
261 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
262 + printk("%02x\n", *(ethernet_addr+i));
263 + }
264 +
265 + return 0;
266 +}
267 +
268 +struct psbl_rec {
269 + unsigned int psbl_size;
270 + unsigned int env_base;
271 + unsigned int env_size;
272 + unsigned int ffs_base;
273 + unsigned int ffs_size;
274 +};
275 +
276 +static const char psp_env_version[] = "TIENV0.8";
277 +
278 +int __init prom_init(int argc, char **argv, char **envp)
279 +{
280 + int i;
281 +
282 + t_env_var *env = (t_env_var *) envp;
283 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
284 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
285 +
286 + prom_argc = argc;
287 + _prom_argv = (int *)argv;
288 + _prom_envp = (int *)envp;
289 +
290 + if(strcmp(psp_env, psp_env_version) == 0) {
291 + /* PSPBOOT */
292 +
293 + env_type = 1;
294 + _prom_envp = psp_env;
295 + max_env_entry = (psbl->env_size / 16) - 1;
296 + } else {
297 + /* Copy what we need locally so we are not dependent on
298 + * bootloader RAM. In Adam2, the environment parameters
299 + * are in flash but the table that references them is in
300 + * RAM
301 + */
302 +
303 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
304 + if (env->name) {
305 + local_envp[i].name = env->name;
306 + local_envp[i].val = env->val;
307 + } else {
308 + local_envp[i].name = NULL;
309 + local_envp[i].val = NULL;
310 + }
311 + }
312 + }
313 +
314 + set_io_port_base(0);
315 +
316 + prom_printf("\nLINUX started...\n");
317 + prom_init_cmdline();
318 + prom_meminit();
319 +
320 + return 0;
321 +}
322 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
323 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
324 +++ linux.dev/arch/mips/ar7/irq.c 2005-10-21 17:02:14.507635750 +0200
325 @@ -0,0 +1,925 @@
326 +/*
327 + * Nitin Dhingra, iamnd@ti.com
328 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
329 + *
330 + * ########################################################################
331 + *
332 + * This program is free software; you can distribute it and/or modify it
333 + * under the terms of the GNU General Public License (Version 2) as
334 + * published by the Free Software Foundation.
335 + *
336 + * This program is distributed in the hope it will be useful, but WITHOUT
337 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
338 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
339 + * for more details.
340 + *
341 + * You should have received a copy of the GNU General Public License along
342 + * with this program; if not, write to the Free Software Foundation, Inc.,
343 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
344 + *
345 + * ########################################################################
346 + *
347 + * Routines for generic manipulation of the interrupts found on the Texas
348 + * Instruments avalanche board
349 + *
350 + */
351 +
352 +#include <linux/config.h>
353 +#include <linux/init.h>
354 +#include <linux/sched.h>
355 +#include <linux/slab.h>
356 +#include <linux/interrupt.h>
357 +#include <linux/kernel_stat.h>
358 +#include <linux/proc_fs.h>
359 +#include <linux/module.h>
360 +#include <asm/irq.h>
361 +#include <asm/mips-boards/prom.h>
362 +#include <asm/ar7/ar7.h>
363 +#include <asm/ar7/avalanche_intc.h>
364 +#include <asm/gdb-stub.h>
365 +
366 +
367 +#define shutdown_avalanche_irq disable_avalanche_irq
368 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
369 +
370 +static unsigned int startup_avalanche_irq(unsigned int irq);
371 +static void end_avalanche_irq(unsigned int irq);
372 +void enable_avalanche_irq(unsigned int irq_nr);
373 +void disable_avalanche_irq(unsigned int irq_nr);
374 +
375 +static struct hw_interrupt_type avalanche_irq_type = {
376 + "TI AVALANCHE",
377 + startup_avalanche_irq,
378 + shutdown_avalanche_irq,
379 + enable_avalanche_irq,
380 + disable_avalanche_irq,
381 + mask_and_ack_avalanche_irq,
382 + end_avalanche_irq,
383 + NULL
384 +};
385 +
386 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
387 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
388 +
389 +
390 +unsigned long spurious_count = 0;
391 +
392 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
393 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
394 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
395 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
396 +
397 +extern asmlinkage void mipsIRQ(void);
398 +
399 +#ifdef CONFIG_AR7_VLYNQ
400 +#include <asm/ar7/vlynq.h>
401 +extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
402 +#endif
403 +
404 +/*
405 + * The avalanche/MIPS interrupt line numbers are used to represent the
406 + * interrupts within the irqaction arrays. The index notation is
407 + * is as follows:
408 + *
409 + * 0-7 MIPS CPU Exceptions (HW/SW)
410 + * 8-47 Primary Interrupts (Avalanche)
411 + * 48-79 Secondary Interrupts (Avalanche)
412 + *
413 + */
414 +
415 +
416 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
417 +{
418 + NULL, NULL, NULL, NULL,
419 + NULL, NULL, NULL, NULL,
420 + NULL, NULL, NULL, NULL,
421 + NULL, NULL, NULL, NULL,
422 + NULL, NULL, NULL, NULL,
423 + NULL, NULL, NULL, NULL,
424 + NULL, NULL, NULL, NULL,
425 + NULL, NULL, NULL, NULL,
426 + NULL, NULL, NULL, NULL,
427 + NULL, NULL, NULL, NULL
428 +};
429 +
430 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
431 +{
432 + NULL, NULL, NULL, NULL,
433 + NULL, NULL, NULL, NULL,
434 + NULL, NULL, NULL, NULL,
435 + NULL, NULL, NULL, NULL,
436 + NULL, NULL, NULL, NULL,
437 + NULL, NULL, NULL, NULL,
438 + NULL, NULL, NULL, NULL,
439 + NULL, NULL, NULL, NULL
440 +};
441 +
442 +/*
443 + This remaps interrupts to exist on other channels than the default
444 + channels. essentially we can use the line # as the index for this
445 + array
446 + */
447 +
448 +
449 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
450 +unsigned long uni_secondary_interrupt = 0;
451 +
452 +static struct irqaction r4ktimer_action = {
453 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
454 +};
455 +
456 +static struct irqaction *irq_action[8] = {
457 + NULL, /* SW int 0 */
458 + NULL, /* SW int 1 */
459 + NULL, /* HW int 0 */
460 + NULL,
461 + NULL,
462 + NULL, /* HW int 3 */
463 + NULL, /* HW int 4 */
464 + &r4ktimer_action /* HW int 5 */
465 +};
466 +
467 +static void end_avalanche_irq(unsigned int irq)
468 +{
469 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
470 + enable_avalanche_irq(irq);
471 +}
472 +
473 +void disable_avalanche_irq(unsigned int irq_nr)
474 +{
475 + unsigned long flags;
476 + unsigned long chan_nr=0;
477 + unsigned long int_bit=0;
478 +
479 + if(irq_nr >= AVALANCHE_INT_END)
480 + {
481 + printk(KERN_ERR "%s: whee, invalid irq_nr %d\n",
482 + __FUNCTION__, irq_nr);
483 + panic("IRQ, you lose...");
484 + }
485 +
486 + save_and_cli(flags);
487 +
488 +
489 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
490 + {
491 + /* disable mips exception */
492 +
493 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
494 + change_c0_status(ST0_IM,int_bit);
495 + restore_flags(flags);
496 + return;
497 + }
498 +
499 +#if defined (CONFIG_AR7_VLYNQ)
500 + /* Vlynq irq_nr are 72-145 in the system and are placed after
501 + * the interrupts managed by the interrupt controller.
502 + */
503 + if(irq_nr >= AVALANCHE_INTC_END)
504 + {
505 + if(irq_nr >= AVALANCHE_INT_END_LOW_VLYNQ)
506 + /* Vlynq interrupts 32-63 */
507 + vlynq_interrupt_disable(&vlynqDevice1,VLYNQ_REMOTE_DVC,
508 + irq_nr-AVALANCHE_INT_END_LOW_VLYNQ);
509 + else
510 + /* Vlynq interupts 0-31 */
511 + vlynq_interrupt_disable(&vlynqDevice0,VLYNQ_REMOTE_DVC,
512 + irq_nr-AVALANCHE_INTC_END);
513 +
514 + goto ret_from_disable_irq;
515 + }
516 +#endif
517 +
518 + /* irq_nr represents the line number for the interrupt. We must
519 + * disable the channel number associated with that line number.
520 + */
521 +
522 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
523 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
524 + else
525 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
526 +
527 + /* disable the interrupt channel bit */
528 +
529 + /* primary interrupt #'s 0-31 */
530 +
531 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
532 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
533 +
534 + /* primary interrupt #'s 32-39 */
535 +
536 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
537 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
538 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
539 +
540 + else /* secondary interrupt #'s 0-31 */
541 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
542 +
543 +#if defined (CONFIG_AR7_VLYNQ)
544 +ret_from_disable_irq:
545 +#endif
546 +
547 + restore_flags(flags);
548 +}
549 +
550 +void enable_avalanche_irq(unsigned int irq_nr)
551 +{
552 + unsigned long flags;
553 + unsigned long chan_nr=0;
554 + unsigned long int_bit=0;
555 +
556 + if(irq_nr > AVALANCHE_INT_END) {
557 + printk(KERN_ERR "%s: whee, invalid irq_nr %d\n",
558 + __FUNCTION__, irq_nr);
559 + panic("IRQ, you lose...");
560 + }
561 +
562 + save_and_cli(flags);
563 +
564 +
565 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
566 + {
567 + /* Enable MIPS exceptions */
568 + int_bit = read_c0_status();
569 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
570 + restore_flags(flags);
571 + return;
572 + }
573 +
574 +#if defined (CONFIG_AR7_VLYNQ)
575 + /* Vlynq irq_nr are 80-143 in the system and are placed after
576 + * the interrupts managed by the interrupt controller.
577 + */
578 + if(irq_nr >= AVALANCHE_INTC_END)
579 + {
580 + if(irq_nr >= AVALANCHE_INT_END_LOW_VLYNQ)
581 + /* Vlynq interrupts 32-63 */
582 + vlynq_interrupt_enable(&vlynqDevice1,VLYNQ_REMOTE_DVC,
583 + irq_nr-AVALANCHE_INT_END_LOW_VLYNQ);
584 + else
585 + /* Vlynq interupts 0-31 */
586 + vlynq_interrupt_enable(&vlynqDevice0,VLYNQ_REMOTE_DVC,
587 + irq_nr-AVALANCHE_INTC_END);
588 +
589 + goto ret_from_enable_irq;
590 + }
591 +#endif
592 +
593 + /* irq_nr represents the line number for the interrupt. We must
594 + * disable the channel number associated with that line number.
595 + */
596 +
597 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
598 + chan_nr = AVINTNUM(irq_nr);
599 + else
600 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
601 +
602 + /* enable the interrupt channel bit */
603 +
604 + /* primary interrupt #'s 0-31 */
605 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
606 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
607 +
608 + /* primary interrupt #'s 32 throuth 39 */
609 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
610 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
611 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
612 +
613 + else /* secondary interrupt #'s 0-31 */
614 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
615 +
616 +#if defined (CONFIG_AR7_VLYNQ)
617 +ret_from_enable_irq:
618 +#endif
619 +
620 + restore_flags(flags);
621 +}
622 +
623 +static unsigned int startup_avalanche_irq(unsigned int irq)
624 +{
625 + enable_avalanche_irq(irq);
626 + return 0; /* never anything pending */
627 +}
628 +
629 +
630 +int get_irq_list(char *buf)
631 +{
632 + int i, len = 0;
633 + int num = 0;
634 + struct irqaction *action;
635 +
636 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
637 + {
638 + action = irq_action[i];
639 + if (!action)
640 + continue;
641 + len += sprintf(buf+len, "%2d: %8d %c %s",
642 + num, kstat.irqs[0][num],
643 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
644 + action->name);
645 + for (action=action->next; action; action = action->next) {
646 + len += sprintf(buf+len, ",%s %s",
647 + (action->flags & SA_INTERRUPT) ? " +" : "",
648 + action->name);
649 + }
650 + len += sprintf(buf+len, " [MIPS interrupt]\n");
651 + }
652 +
653 +
654 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
655 + {
656 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
657 + action = hw0_irq_action_primary[i];
658 + else
659 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
660 + if (!action)
661 + continue;
662 + len += sprintf(buf+len, "%2d: %8d %c %s",
663 + num, kstat.irqs[0][ LNXINTNUM(i) ],
664 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
665 + action->name);
666 +
667 + for (action=action->next; action; action = action->next)
668 + {
669 + len += sprintf(buf+len, ",%s %s",
670 + (action->flags & SA_INTERRUPT) ? " +" : "",
671 + action->name);
672 + }
673 +
674 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
675 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
676 + else
677 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
678 +
679 + }
680 +
681 + return len;
682 +}
683 +
684 +int request_irq(unsigned int irq,
685 + void (*handler)(int, void *, struct pt_regs *),
686 + unsigned long irqflags,
687 + const char * devname,
688 + void *dev_id)
689 +{
690 + struct irqaction *action;
691 +
692 + if (irq > AVALANCHE_INT_END)
693 + return -EINVAL;
694 + if (!handler)
695 + return -EINVAL;
696 +
697 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
698 + if(!action)
699 + return -ENOMEM;
700 +
701 + action->handler = handler;
702 + action->flags = irqflags;
703 + action->mask = 0;
704 + action->name = devname;
705 + irq_desc_ti[irq].action = action;
706 + action->dev_id = dev_id;
707 +
708 + action->next = 0;
709 +
710 + if(irq < MIPS_EXCEPTION_OFFSET)
711 + {
712 + irq_action[irq] = action;
713 + enable_avalanche_irq(irq);
714 + return 0;
715 + }
716 +
717 + if(irq < AVALANCHE_INT_END_PRIMARY)
718 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
719 + else
720 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
721 +
722 + enable_avalanche_irq(irq);
723 +
724 + return 0;
725 +}
726 +
727 +void free_irq(unsigned int irq, void *dev_id)
728 +{
729 + struct irqaction *action;
730 +
731 + if (irq > AVALANCHE_INT_END) {
732 + printk(KERN_ERR "Trying to free IRQ%d\n",irq);
733 + return;
734 + }
735 +
736 + if(irq < MIPS_EXCEPTION_OFFSET)
737 + {
738 + action = irq_action[irq];
739 + irq_action[irq] = NULL;
740 + irq_desc_ti[irq].action = NULL;
741 + disable_avalanche_irq(irq);
742 + kfree(action);
743 + return;
744 + }
745 +
746 + if(irq < AVALANCHE_INT_END_PRIMARY) {
747 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
748 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
749 + irq_desc_ti[irq].action = NULL;
750 + }
751 + else {
752 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
753 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
754 + irq_desc_ti[irq].action = NULL;
755 + }
756 +
757 + disable_avalanche_irq(irq);
758 + kfree(action);
759 +}
760 +
761 +#ifdef CONFIG_KGDB
762 +extern void breakpoint(void);
763 +extern int remote_debug;
764 +#endif
765 +
766 +
767 +//void init_IRQ(void) __init;
768 +void __init init_IRQ(void)
769 +{
770 + int i;
771 +
772 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
773 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
774 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
775 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
776 +
777 + /* Disable interrupts and clear pending
778 + */
779 +
780 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
781 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
782 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
783 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
784 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
785 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
786 +
787 +
788 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
789 + /* hack for speeding up the pacing. */
790 + printk(KERN_INFO "the pacing pre-scalar has been set as 600.\n");
791 + avalanche_hw0_ipaceregs->ipacep = 600;
792 + /* Channel to line mapping, Line to Channel mapping */
793 +
794 + for(i = 0; i < 40; i++)
795 + avalanche_int_set(i,i);
796 +
797 + /* Now safe to set the exception vector. */
798 + set_except_vector(0, mipsIRQ);
799 +
800 + /* Setup the IRQ description array. These will be mapped
801 + * as flat interrupts numbers. The mapping is as follows
802 + *
803 + * 0-7 MIPS CPU Exceptions (HW/SW)
804 + * 8-46 Primary Interrupts (Avalanche)
805 + * 47-78 Secondary Interrupts (Avalanche)
806 + */
807 +
808 + for (i = 0; i <= AVALANCHE_INT_END; i++)
809 + {
810 + irq_desc_ti[i].status = IRQ_DISABLED;
811 + irq_desc_ti[i].action = 0;
812 + irq_desc_ti[i].depth = 1;
813 + irq_desc_ti[i].handler = &avalanche_irq_type;
814 + }
815 +
816 +#ifdef CONFIG_KGDB
817 + if (remote_debug)
818 + {
819 + set_debug_traps();
820 + breakpoint();
821 + }
822 +#endif
823 +}
824 +
825 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
826 +{
827 + struct irqaction *action;
828 + int irq, cpu = smp_processor_id();
829 + unsigned long int_line_number,status;
830 + int i,secondary = 0;
831 + int chan_nr=0;
832 +
833 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
834 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
835 +
836 +
837 + if(chan_nr < 32)
838 + {
839 + if( chan_nr != uni_secondary_interrupt)
840 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
841 +
842 + }
843 +
844 + if((chan_nr < 40) && (chan_nr > 31))
845 + {
846 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
847 + }
848 +
849 +
850 + /* If the Priority Interrupt Index Register returns 40 then no
851 + * interrupts are pending
852 + */
853 +
854 + if(chan_nr == 40)
855 + return;
856 +
857 + if(chan_nr == uni_secondary_interrupt)
858 + {
859 + status = avalanche_hw0_ecregs->exsr;
860 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
861 + {
862 + if (status & 1<<i)
863 + {
864 + /* clear secondary interrupt */
865 + avalanche_hw0_ecregs->excr = 1 << i;
866 + break;
867 + }
868 + }
869 + irq = i;
870 + secondary = 1;
871 +
872 + /* clear the universal secondary interrupt */
873 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
874 +
875 + }
876 + else
877 + irq = chan_nr;
878 +
879 + /* Suraj Add code to clear secondary interrupt */
880 +
881 + if(secondary)
882 + action = hw0_irq_action_secondary[irq];
883 + else
884 + action = hw0_irq_action_primary[irq];
885 +
886 + /* if action == NULL, then we don't have a handler for the irq */
887 +
888 + if ( action == NULL ) {
889 + printk(KERN_ERR "No handler for hw0 irq: %i\n", irq);
890 + return;
891 + }
892 +
893 + irq_enter(cpu,irq);
894 + if(secondary)
895 + {
896 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
897 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
898 + }
899 + else
900 + {
901 + kstat.irqs[0][irq + 8]++;
902 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
903 + }
904 +
905 + irq_exit(cpu,irq);
906 +
907 + if(softirq_pending(cpu))
908 + do_softirq();
909 +
910 + return;
911 +}
912 +
913 +void avalanche_int_set(int channel, int line)
914 +{
915 + switch(channel)
916 + {
917 + case(0):
918 + avalanche_hw0_chregs->cintnr0 = line;
919 + break;
920 + case(1):
921 + avalanche_hw0_chregs->cintnr1 = line;
922 + break;
923 + case(2):
924 + avalanche_hw0_chregs->cintnr2 = line;
925 + break;
926 + case(3):
927 + avalanche_hw0_chregs->cintnr3 = line;
928 + break;
929 + case(4):
930 + avalanche_hw0_chregs->cintnr4 = line;
931 + break;
932 + case(5):
933 + avalanche_hw0_chregs->cintnr5 = line;
934 + break;
935 + case(6):
936 + avalanche_hw0_chregs->cintnr6 = line;
937 + break;
938 + case(7):
939 + avalanche_hw0_chregs->cintnr7 = line;
940 + break;
941 + case(8):
942 + avalanche_hw0_chregs->cintnr8 = line;
943 + break;
944 + case(9):
945 + avalanche_hw0_chregs->cintnr9 = line;
946 + break;
947 + case(10):
948 + avalanche_hw0_chregs->cintnr10 = line;
949 + break;
950 + case(11):
951 + avalanche_hw0_chregs->cintnr11 = line;
952 + break;
953 + case(12):
954 + avalanche_hw0_chregs->cintnr12 = line;
955 + break;
956 + case(13):
957 + avalanche_hw0_chregs->cintnr13 = line;
958 + break;
959 + case(14):
960 + avalanche_hw0_chregs->cintnr14 = line;
961 + break;
962 + case(15):
963 + avalanche_hw0_chregs->cintnr15 = line;
964 + break;
965 + case(16):
966 + avalanche_hw0_chregs->cintnr16 = line;
967 + break;
968 + case(17):
969 + avalanche_hw0_chregs->cintnr17 = line;
970 + break;
971 + case(18):
972 + avalanche_hw0_chregs->cintnr18 = line;
973 + break;
974 + case(19):
975 + avalanche_hw0_chregs->cintnr19 = line;
976 + break;
977 + case(20):
978 + avalanche_hw0_chregs->cintnr20 = line;
979 + break;
980 + case(21):
981 + avalanche_hw0_chregs->cintnr21 = line;
982 + break;
983 + case(22):
984 + avalanche_hw0_chregs->cintnr22 = line;
985 + break;
986 + case(23):
987 + avalanche_hw0_chregs->cintnr23 = line;
988 + break;
989 + case(24):
990 + avalanche_hw0_chregs->cintnr24 = line;
991 + break;
992 + case(25):
993 + avalanche_hw0_chregs->cintnr25 = line;
994 + break;
995 + case(26):
996 + avalanche_hw0_chregs->cintnr26 = line;
997 + break;
998 + case(27):
999 + avalanche_hw0_chregs->cintnr27 = line;
1000 + break;
1001 + case(28):
1002 + avalanche_hw0_chregs->cintnr28 = line;
1003 + break;
1004 + case(29):
1005 + avalanche_hw0_chregs->cintnr29 = line;
1006 + break;
1007 + case(30):
1008 + avalanche_hw0_chregs->cintnr30 = line;
1009 + break;
1010 + case(31):
1011 + avalanche_hw0_chregs->cintnr31 = line;
1012 + break;
1013 + case(32):
1014 + avalanche_hw0_chregs->cintnr32 = line;
1015 + break;
1016 + case(33):
1017 + avalanche_hw0_chregs->cintnr33 = line;
1018 + break;
1019 + case(34):
1020 + avalanche_hw0_chregs->cintnr34 = line;
1021 + break;
1022 + case(35):
1023 + avalanche_hw0_chregs->cintnr35 = line;
1024 + break;
1025 + case(36):
1026 + avalanche_hw0_chregs->cintnr36 = line;
1027 + break;
1028 + case(37):
1029 + avalanche_hw0_chregs->cintnr37 = line;
1030 + break;
1031 + case(38):
1032 + avalanche_hw0_chregs->cintnr38 = line;
1033 + break;
1034 + case(39):
1035 + avalanche_hw0_chregs->cintnr39 = line;
1036 + break;
1037 + default:
1038 + printk(KERN_ERR "Error: Unknown Avalanche interrupt channel\n");
1039 + }
1040 +
1041 + line_to_channel[line] = channel; /* Suraj check */
1042 +
1043 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1044 + uni_secondary_interrupt = line;
1045 +
1046 +}
1047 +
1048 +
1049 +#define AVALANCHE_MAX_PACING_BLK 3
1050 +#define AVALANCHE_PACING_LOW_VAL 2
1051 +#define AVALANCHE_PACING_HIGH_VAL 63
1052 +
1053 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
1054 + unsigned int pace_value)
1055 +{
1056 + unsigned int blk_offset;
1057 + unsigned long flags;
1058 +
1059 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
1060 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
1061 + return (0);
1062 +
1063 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
1064 + return(-1);
1065 +
1066 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
1067 + pace_value < AVALANCHE_PACING_LOW_VAL)
1068 + return(-1);
1069 +
1070 + blk_offset = blk_num*8;
1071 +
1072 + save_and_cli(flags);
1073 +
1074 + /* disable the interrupt pacing, if enabled previously */
1075 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
1076 +
1077 + /* clear the pacing map */
1078 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
1079 +
1080 + /* setup the new values */
1081 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
1082 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
1083 +
1084 + restore_flags(flags);
1085 +
1086 + return(0);
1087 +}
1088 +
1089 +/* Sets the trigger type: edge or level */
1090 +int avalanche_intr_type_set(unsigned int irq_nr, unsigned long type_val)
1091 +{
1092 + unsigned long flags;
1093 + unsigned long chan_nr=0;
1094 +
1095 + printk(KERN_NOTICE "AVALANCHE_INT_END_PRIMARY %d\n",
1096 + AVALANCHE_INT_END_PRIMARY);
1097 + printk(KERN_NOTICE "AVALANCHE_INT_END_SECONDARY %d\n",
1098 + AVALANCHE_INT_END_SECONDARY);
1099 + printk(KERN_NOTICE "AVALANCHE_INT_END %d\n", AVALANCHE_INT_END);
1100 + printk(KERN_NOTICE "AVALANCHE_INTC_END %d\n", AVALANCHE_INTC_END);
1101 + if(irq_nr < MIPS_EXCEPTION_OFFSET ||
1102 + irq_nr >= AVALANCHE_INT_END)
1103 + {
1104 + printk(KERN_ERR "%s: whee, invalid irq_nr %d\n",
1105 + __FUNCTION__, irq_nr);
1106 + panic("IRQ, you lose...");
1107 + return(-1);
1108 + }
1109 +
1110 + if(type_val > 1)
1111 + {
1112 + printk(KERN_ERR "Not a valid polarity value.\n");
1113 + return(-1);
1114 + }
1115 +
1116 +#if defined (CONFIG_AR7_VLYNQ)
1117 + /* Vlynq irq_nr are 80-143 in the system and are placed after the interrupts
1118 + * managed by the interrupt controller.
1119 + */
1120 + if(irq_nr >= AVALANCHE_INTC_END)
1121 + {
1122 + /* Type values for VLYNQ are INTC are different. */
1123 + if(irq_nr >= AVALANCHE_INT_END_LOW_VLYNQ)
1124 + /* Vlynq interrupts 32-63 */
1125 + vlynq_interrupt_set_type(&vlynqDevice1, VLYNQ_REMOTE_DVC,
1126 + irq_nr - AVALANCHE_INT_END_LOW_VLYNQ, !type_val);
1127 + else
1128 + /* Vlynq interupts 0-31 */
1129 + vlynq_interrupt_set_type(&vlynqDevice0, VLYNQ_REMOTE_DVC,
1130 + irq_nr - AVALANCHE_INTC_END, !type_val);
1131 +
1132 + goto ret_from_set_type;
1133 + }
1134 +#endif
1135 +
1136 + irq_nr = AVINTNUM(irq_nr);
1137 +
1138 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
1139 +
1140 + save_and_cli(flags);
1141 +
1142 + /* primary interrupt #'s 0-31 */
1143 + if(chan_nr < AVALANCHE_INT_END_PRIMARY_REG1)
1144 + {
1145 + if(type_val)
1146 + avalanche_hw0_icregs->inttypr1 |= (1 << chan_nr);
1147 + else
1148 + avalanche_hw0_icregs->inttypr1 &= ~(1 << chan_nr);
1149 + }
1150 + /* primary interrupt #'s 32 throuth 39 */
1151 + else
1152 + {
1153 + if(type_val)
1154 + avalanche_hw0_icregs->inttypr2 |=
1155 + (1 << (chan_nr - AVALANCHE_INT_END_PRIMARY_REG1));
1156 + else
1157 + avalanche_hw0_icregs->inttypr2 &=
1158 + ~(1 << (chan_nr - AVALANCHE_INT_END_PRIMARY_REG1));
1159 + }
1160 +
1161 + restore_flags(flags);
1162 +
1163 +#if defined (CONFIG_AR7_VLYNQ)
1164 +ret_from_set_type:
1165 +#endif
1166 +
1167 + return(0);
1168 +}
1169 +
1170 +
1171 +int avalanche_intr_polarity_set(unsigned int irq_nr, unsigned long polarity_val)
1172 +{
1173 + unsigned long flags;
1174 + unsigned long chan_nr=0;
1175 +
1176 + if(irq_nr < MIPS_EXCEPTION_OFFSET ||
1177 + irq_nr >= AVALANCHE_INT_END)
1178 + {
1179 + printk(KERN_ERR "%s: whee, invalid irq_nr %d\n",
1180 + __FUNCTION__, irq_nr);
1181 +#if defined (CONFIG_AR7_VLYNQ)
1182 + printk(KERN_ERR "Not one of the primary or vlynq avalanche interrupts.\n");
1183 +#else
1184 + printk(KERN_ERR "Not one of the primary avalanche interrupts\n");
1185 +#endif
1186 + panic("IRQ, you lose...");
1187 + return(-1);
1188 + }
1189 +
1190 + if(polarity_val > 1)
1191 + {
1192 + printk(KERN_ERR "Not a valid polarity value.\n");
1193 + return(-1);
1194 + }
1195 +
1196 +
1197 +#if defined (CONFIG_AR7_VLYNQ)
1198 + /* Vlynq irq_nr are 80-143 in the system and are placed after the interrupts
1199 + * managed by the interrupt controller.
1200 + */
1201 + if(irq_nr >= AVALANCHE_INTC_END)
1202 + {
1203 + if(irq_nr >= AVALANCHE_INT_END_LOW_VLYNQ)
1204 + /* Vlynq interrupts 32-63 */
1205 + vlynq_interrupt_set_polarity(&vlynqDevice1, VLYNQ_REMOTE_DVC,
1206 + irq_nr - AVALANCHE_INT_END_LOW_VLYNQ, polarity_val);
1207 + else
1208 + /* Vlynq interupts 0-31 */
1209 + vlynq_interrupt_set_polarity(&vlynqDevice0, VLYNQ_REMOTE_DVC,
1210 + irq_nr - AVALANCHE_INTC_END, polarity_val);
1211 + goto ret_from_set_polarity;
1212 + }
1213 +#endif
1214 +
1215 + irq_nr = AVINTNUM(irq_nr);
1216 +
1217 + chan_nr = line_to_channel[irq_nr];
1218 +
1219 + save_and_cli(flags);
1220 +
1221 + /* primary interrupt #'s 0-31 */
1222 + if(chan_nr < AVALANCHE_INT_END_PRIMARY_REG1)
1223 + {
1224 + if(polarity_val)
1225 + avalanche_hw0_icregs->intpolr1 |= (1 << chan_nr);
1226 + else
1227 + avalanche_hw0_icregs->intpolr1 &= ~(1 << chan_nr);
1228 + }
1229 + /* primary interrupt #'s 32 throuth 39 */
1230 + else
1231 + {
1232 + if(polarity_val)
1233 + avalanche_hw0_icregs->intpolr2 |=
1234 + (1 << (chan_nr - AVALANCHE_INT_END_PRIMARY_REG1));
1235 + else
1236 + avalanche_hw0_icregs->intpolr2 &=
1237 + ~(1 << (chan_nr - AVALANCHE_INT_END_PRIMARY_REG1));
1238 + }
1239 +
1240 + restore_flags(flags);
1241 +
1242 +#if defined (CONFIG_AR7_VLYNQ)
1243 +ret_from_set_polarity:
1244 +#endif
1245 +
1246 + return(0);
1247 +}
1248 +
1249 +EXPORT_SYMBOL(avalanche_intr_polarity_set);
1250 +EXPORT_SYMBOL(avalanche_intr_type_set);
1251 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
1252 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1253 +++ linux.dev/arch/mips/ar7/memory.c 2005-10-21 16:45:42.090061750 +0200
1254 @@ -0,0 +1,131 @@
1255 +/*
1256 + * Carsten Langgaard, carstenl@mips.com
1257 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1258 + *
1259 + * ########################################################################
1260 + *
1261 + * This program is free software; you can distribute it and/or modify it
1262 + * under the terms of the GNU General Public License (Version 2) as
1263 + * published by the Free Software Foundation.
1264 + *
1265 + * This program is distributed in the hope it will be useful, but WITHOUT
1266 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1267 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1268 + * for more details.
1269 + *
1270 + * You should have received a copy of the GNU General Public License along
1271 + * with this program; if not, write to the Free Software Foundation, Inc.,
1272 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1273 + *
1274 + * ########################################################################
1275 + *
1276 + * PROM library functions for acquiring/using memory descriptors given to
1277 + * us from the YAMON.
1278 + *
1279 + */
1280 +#include <linux/config.h>
1281 +#include <linux/init.h>
1282 +#include <linux/mm.h>
1283 +#include <linux/bootmem.h>
1284 +
1285 +#include <asm/bootinfo.h>
1286 +#include <asm/page.h>
1287 +#include <asm/mips-boards/prom.h>
1288 +
1289 +enum yamon_memtypes {
1290 + yamon_dontuse,
1291 + yamon_prom,
1292 + yamon_free,
1293 +};
1294 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1295 +
1296 +/* References to section boundaries */
1297 +extern char _end;
1298 +
1299 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1300 +
1301 +
1302 +struct prom_pmemblock * __init prom_getmdesc(void)
1303 +{
1304 + char *memsize_str;
1305 + unsigned int memsize;
1306 +
1307 + memsize_str = prom_getenv("memsize");
1308 + if (!memsize_str) {
1309 + memsize = 0x02000000;
1310 + } else {
1311 + memsize = simple_strtol(memsize_str, NULL, 0);
1312 + }
1313 +
1314 + memset(mdesc, 0, sizeof(mdesc));
1315 +
1316 + mdesc[0].type = yamon_dontuse;
1317 + mdesc[0].base = 0x00000000;
1318 + mdesc[0].size = CONFIG_AR7_MEMORY;
1319 +
1320 + mdesc[1].type = yamon_prom;
1321 + mdesc[1].base = CONFIG_AR7_MEMORY;
1322 + mdesc[1].size = 0x00020000;
1323 +
1324 + mdesc[2].type = yamon_free;
1325 + mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1326 + mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1327 +
1328 + return &mdesc[0];
1329 +}
1330 +
1331 +static int __init prom_memtype_classify (unsigned int type)
1332 +{
1333 + switch (type) {
1334 + case yamon_free:
1335 + return BOOT_MEM_RAM;
1336 + case yamon_prom:
1337 + return BOOT_MEM_ROM_DATA;
1338 + default:
1339 + return BOOT_MEM_RESERVED;
1340 + }
1341 +}
1342 +
1343 +void __init prom_meminit(void)
1344 +{
1345 + struct prom_pmemblock *p;
1346 +
1347 + p = prom_getmdesc();
1348 +
1349 + while (p->size) {
1350 + long type;
1351 + unsigned long base, size;
1352 +
1353 + type = prom_memtype_classify (p->type);
1354 + base = p->base;
1355 + size = p->size;
1356 +
1357 + add_memory_region(base, size, type);
1358 + p++;
1359 + }
1360 +}
1361 +
1362 +void __init prom_free_prom_memory (void)
1363 +{
1364 +#if 0
1365 + int i;
1366 + unsigned long freed = 0;
1367 + unsigned long addr;
1368 +
1369 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1370 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1371 + continue;
1372 +
1373 + addr = boot_mem_map.map[i].addr;
1374 + while (addr < boot_mem_map.map[i].addr
1375 + + boot_mem_map.map[i].size) {
1376 + ClearPageReserved(virt_to_page(__va(addr)));
1377 + set_page_count(virt_to_page(__va(addr)), 1);
1378 + free_page((unsigned long)__va(addr));
1379 + addr += PAGE_SIZE;
1380 + freed += PAGE_SIZE;
1381 + }
1382 + }
1383 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1384 +#endif
1385 +}
1386 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1387 --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1388 +++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-10-21 16:45:42.118063500 +0200
1389 @@ -0,0 +1,120 @@
1390 +/*
1391 + * Carsten Langgaard, carstenl@mips.com
1392 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1393 + *
1394 + * ########################################################################
1395 + *
1396 + * This program is free software; you can distribute it and/or modify it
1397 + * under the terms of the GNU General Public License (Version 2) as
1398 + * published by the Free Software Foundation.
1399 + *
1400 + * This program is distributed in the hope it will be useful, but WITHOUT
1401 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1402 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1403 + * for more details.
1404 + *
1405 + * You should have received a copy of the GNU General Public License along
1406 + * with this program; if not, write to the Free Software Foundation, Inc.,
1407 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1408 + *
1409 + * ########################################################################
1410 + *
1411 + * Interrupt exception dispatch code.
1412 + *
1413 + */
1414 +#include <linux/config.h>
1415 +
1416 +#include <asm/asm.h>
1417 +#include <asm/mipsregs.h>
1418 +#include <asm/regdef.h>
1419 +#include <asm/stackframe.h>
1420 +
1421 +/* A lot of complication here is taken away because:
1422 + *
1423 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1424 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1425 + * common case is one pending IRQ so optimize in that direction.
1426 + *
1427 + * 2) We need not check against bits in the status register IRQ mask, that
1428 + * would make this routine slow as hell.
1429 + *
1430 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1431 + * between like BSD spl() brain-damage.
1432 + *
1433 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1434 + * IRQs which we don't use at all and all external interrupt sources are
1435 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1436 + *
1437 + * MIPS IRQ Source
1438 + * -------- ------
1439 + * 0 Software (ignored)
1440 + * 1 Software (ignored)
1441 + * 2 Combined hardware interrupt (hw0)
1442 + * 3 Hardware (ignored)
1443 + * 4 Hardware (ignored)
1444 + * 5 Hardware (ignored)
1445 + * 6 Hardware (ignored)
1446 + * 7 R4k timer (what we use)
1447 + *
1448 + * Note: On the SEAD board thing are a little bit different.
1449 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1450 + * wired to UART1.
1451 + *
1452 + * We handle the IRQ according to _our_ priority which is:
1453 + *
1454 + * Highest ---- R4k Timer
1455 + * Lowest ---- Combined hardware interrupt
1456 + *
1457 + * then we just return, if multiple IRQs are pending then we will just take
1458 + * another exception, big deal.
1459 + */
1460 +
1461 +.text
1462 +.set noreorder
1463 +.set noat
1464 + .align 5
1465 +NESTED(mipsIRQ, PT_SIZE, sp)
1466 + SAVE_ALL
1467 + CLI
1468 + .set at
1469 +
1470 + mfc0 s0, CP0_CAUSE # get irq bits
1471 +
1472 + /* First we check for r4k counter/timer IRQ. */
1473 + andi a0, s0, CAUSEF_IP7
1474 + beq a0, zero, 1f
1475 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1476 +
1477 + /* Wheee, a timer interrupt. */
1478 + move a0, sp
1479 + jal ar7_timer_interrupt
1480 + nop
1481 +
1482 + j ret_from_irq
1483 + nop
1484 +
1485 + 1:
1486 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1487 + nop
1488 +
1489 + /* Wheee, combined hardware level zero interrupt. */
1490 + jal avalanche_hw0_irqdispatch
1491 + move a0, sp # delay slot
1492 +
1493 + j ret_from_irq
1494 + nop # delay slot
1495 +
1496 + 1:
1497 + /*
1498 + * Here by mistake? This is possible, what can happen is that by the
1499 + * time we take the exception the IRQ pin goes low, so just leave if
1500 + * this is the case.
1501 + */
1502 + move a1,s0
1503 + PRINT("Got interrupt: c0_cause = %08x\n")
1504 + mfc0 a1, CP0_EPC
1505 + PRINT("c0_epc = %08x\n")
1506 +
1507 + j ret_from_irq
1508 + nop
1509 +END(mipsIRQ)
1510 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
1511 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
1512 +++ linux.dev/arch/mips/ar7/misc.c 2005-10-21 16:45:42.122063750 +0200
1513 @@ -0,0 +1,319 @@
1514 +#include <asm/ar7/sangam.h>
1515 +#include <asm/ar7/avalanche_misc.h>
1516 +#include <linux/module.h>
1517 +#include <linux/spinlock.h>
1518 +
1519 +#define TRUE 1
1520 +
1521 +static unsigned int avalanche_vbus_freq;
1522 +
1523 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
1524 +
1525 +/*****************************************************************************
1526 + * Reset Control Module.
1527 + *****************************************************************************/
1528 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
1529 + AVALANCHE_RESET_CTRL_T reset_ctrl)
1530 +{
1531 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1532 +
1533 + if(module_reset_bit >= 32 && module_reset_bit < 64)
1534 + return;
1535 +
1536 + if(module_reset_bit >= 64)
1537 + {
1538 + if(p_remote_vlynq_dev_reset_ctrl)
1539 + return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
1540 + else
1541 + return;
1542 + }
1543 +
1544 + if(reset_ctrl == OUT_OF_RESET)
1545 + *reset_reg |= 1 << module_reset_bit;
1546 + else
1547 + *reset_reg &= ~(1 << module_reset_bit);
1548 +}
1549 +
1550 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
1551 +{
1552 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1553 +
1554 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
1555 +}
1556 +
1557 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
1558 +{
1559 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
1560 + *sw_reset_reg = mode;
1561 +}
1562 +
1563 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
1564 +
1565 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
1566 +{
1567 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1568 +
1569 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1570 +}
1571 +
1572 +
1573 +/*****************************************************************************
1574 + * Power Control Module
1575 + *****************************************************************************/
1576 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1577 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1578 +
1579 +
1580 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1581 +{
1582 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1583 +
1584 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1585 + /* power down the module */
1586 + *power_reg |= (1 << module_power_bit);
1587 + else
1588 + /* power on the module */
1589 + *power_reg &= (~(1 << module_power_bit));
1590 +}
1591 +
1592 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1593 +{
1594 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1595 +
1596 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1597 +}
1598 +
1599 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1600 +{
1601 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1602 +
1603 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1604 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1605 +}
1606 +
1607 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1608 +{
1609 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1610 +
1611 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1612 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1613 +}
1614 +
1615 +/*****************************************************************************
1616 + * GPIO Control
1617 + *****************************************************************************/
1618 +
1619 +/****************************************************************************
1620 + * FUNCTION: avalanche_gpio_init
1621 + ***************************************************************************/
1622 +void avalanche_gpio_init(void)
1623 +{
1624 + spinlock_t closeLock;
1625 + unsigned int closeFlag;
1626 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1627 + spin_lock_irqsave(&closeLock, closeFlag);
1628 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1629 + spin_unlock_irqrestore(&closeLock, closeFlag);
1630 +}
1631 +
1632 +/****************************************************************************
1633 + * FUNCTION: avalanche_gpio_ctrl
1634 + ***************************************************************************/
1635 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1636 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1637 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1638 +{
1639 + spinlock_t closeLock;
1640 + unsigned int closeFlag;
1641 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1642 +
1643 + if(gpio_pin >= 32)
1644 + return(-1);
1645 +
1646 + spin_lock_irqsave(&closeLock, closeFlag);
1647 +
1648 + if(pin_mode == GPIO_PIN)
1649 + {
1650 + *gpio_ctrl |= (1 << gpio_pin);
1651 +
1652 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1653 +
1654 + if(pin_direction == GPIO_INPUT_PIN)
1655 + *gpio_ctrl |= (1 << gpio_pin);
1656 + else
1657 + *gpio_ctrl &= ~(1 << gpio_pin);
1658 + }
1659 + else /* FUNCTIONAL PIN */
1660 + {
1661 + *gpio_ctrl &= ~(1 << gpio_pin);
1662 + }
1663 +
1664 + spin_unlock_irqrestore(&closeLock, closeFlag);
1665 +
1666 + return (0);
1667 +}
1668 +
1669 +/****************************************************************************
1670 + * FUNCTION: avalanche_gpio_out
1671 + ***************************************************************************/
1672 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1673 +{
1674 + spinlock_t closeLock;
1675 + unsigned int closeFlag;
1676 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1677 +
1678 + if(gpio_pin >= 32)
1679 + return(-1);
1680 +
1681 + spin_lock_irqsave(&closeLock, closeFlag);
1682 + if(value == TRUE)
1683 + *gpio_out |= 1 << gpio_pin;
1684 + else
1685 + *gpio_out &= ~(1 << gpio_pin);
1686 + spin_unlock_irqrestore(&closeLock, closeFlag);
1687 +
1688 + return(0);
1689 +}
1690 +
1691 +/****************************************************************************
1692 + * FUNCTION: avalanche_gpio_in
1693 + ***************************************************************************/
1694 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1695 +{
1696 + spinlock_t closeLock;
1697 + unsigned int closeFlag;
1698 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1699 + int ret_val = 0;
1700 +
1701 + if(gpio_pin >= 32)
1702 + return(-1);
1703 +
1704 + spin_lock_irqsave(&closeLock, closeFlag);
1705 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1706 + spin_unlock_irqrestore(&closeLock, closeFlag);
1707 +
1708 + return (ret_val);
1709 +}
1710 +
1711 +/****************************************************************************
1712 + * FUNCTION: avalanche_gpio_out_val
1713 + ***************************************************************************/
1714 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1715 + unsigned int reg_index)
1716 +{
1717 + spinlock_t closeLock;
1718 + unsigned int closeFlag;
1719 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1720 +
1721 + if(reg_index > 0)
1722 + return(-1);
1723 +
1724 + spin_lock_irqsave(&closeLock, closeFlag);
1725 + *gpio_out &= ~out_mask;
1726 + *gpio_out |= out_val;
1727 + spin_unlock_irqrestore(&closeLock, closeFlag);
1728 +
1729 + return(0);
1730 +}
1731 +
1732 +/****************************************************************************
1733 + * FUNCTION: avalanche_gpio_in_value
1734 + ***************************************************************************/
1735 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1736 +{
1737 + spinlock_t closeLock;
1738 + unsigned int closeFlag;
1739 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1740 +
1741 + if(reg_index > 0)
1742 + return(-1);
1743 +
1744 + spin_lock_irqsave(&closeLock, closeFlag);
1745 + *in_val = *gpio_in;
1746 + spin_unlock_irqrestore(&closeLock, closeFlag);
1747 +
1748 + return (0);
1749 +}
1750 +
1751 +/***********************************************************************
1752 + *
1753 + * Wakeup Control Module for TNETV1050 Communication Processor
1754 + *
1755 + ***********************************************************************/
1756 +
1757 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1758 +
1759 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1760 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1761 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1762 +{
1763 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1764 +
1765 + /* enable/disable */
1766 + if (wakeup_ctrl == WAKEUP_ENABLED)
1767 + /* enable wakeup */
1768 + *wakeup_status_reg |= wakeup_int;
1769 + else
1770 + /* disable wakeup */
1771 + *wakeup_status_reg &= (~wakeup_int);
1772 +
1773 + /* set polarity */
1774 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1775 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1776 + else
1777 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1778 +}
1779 +
1780 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1781 +{
1782 + avalanche_vbus_freq = new_vbus_freq;
1783 +}
1784 +
1785 +unsigned int avalanche_get_vbus_freq()
1786 +{
1787 + return(avalanche_vbus_freq);
1788 +}
1789 +
1790 +unsigned int avalanche_get_chip_version_info()
1791 +{
1792 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1793 +}
1794 +
1795 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1796 +
1797 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1798 +{
1799 + if(p_set_mdix_on_chip_fn)
1800 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1801 + else
1802 + return(-1);
1803 +}
1804 +
1805 +unsigned int avalanche_is_mdix_on_chip(void)
1806 +{
1807 + return(p_set_mdix_on_chip_fn ? 1:0);
1808 +}
1809 +
1810 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1811 +EXPORT_SYMBOL(avalanche_get_reset_status);
1812 +EXPORT_SYMBOL(avalanche_sys_reset);
1813 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1814 +EXPORT_SYMBOL(avalanche_power_ctrl);
1815 +EXPORT_SYMBOL(avalanche_get_power_status);
1816 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1817 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1818 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1819 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1820 +
1821 +EXPORT_SYMBOL(avalanche_gpio_init);
1822 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1823 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1824 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1825 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1826 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1827 +
1828 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1829 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1830 +
1831 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1832 +
1833 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1834 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1835 +++ linux.dev/arch/mips/ar7/platform.h 2005-10-21 16:45:42.122063750 +0200
1836 @@ -0,0 +1,65 @@
1837 +#ifndef _PLATFORM_H_
1838 +#define _PLATFORM_H_
1839 +
1840 +#include <linux/config.h>
1841 +
1842 +
1843 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1844 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1845 + */
1846 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1847 +#define ENV_SPACE_SIZE (10 * 1024)
1848 +#endif
1849 +
1850 +#ifdef CONFIG_MIPS_TNETV1050SDB
1851 +#define TNETV1050SDB
1852 +#define DUAL_FLASH
1853 +#endif
1854 +
1855 +#ifdef CONFIG_MIPS_AR7DB
1856 +#define TNETD73XX_BOARD
1857 +#define AR7DB
1858 +#endif
1859 +
1860 +#ifdef CONFIG_MIPS_AR7RD
1861 +#define TNETD73XX_BOARD
1862 +#define AR7RD
1863 +#endif
1864 +
1865 +#ifdef CONFIG_AR7WRD
1866 +#define TNETD73XX_BOARD
1867 +#define AR7WRD
1868 +#endif
1869 +
1870 +#ifdef CONFIG_MIPS_AR7VWI
1871 +#define TNETD73XX_BOARD
1872 +#define AR7VWi
1873 +#endif
1874 +
1875 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1876 +#ifdef CONFIG_MIPS_AR7VW
1877 +#define TNETD73XX_BOARD
1878 +#define AR7WRD
1879 +#endif
1880 +
1881 +#ifdef CONFIG_MIPS_AR7WI
1882 +#define TNETD73XX_BOARD
1883 +#define AR7Wi
1884 +#endif
1885 +
1886 +#ifdef CONFIG_MIPS_AR7V
1887 +#define TNETD73XX_BOARD
1888 +#define AR7V
1889 +#endif
1890 +
1891 +#ifdef CONFIG_MIPS_AR7V
1892 +#define TNETD73XX_BOARD
1893 +#define AR7V
1894 +#endif
1895 +
1896 +#ifdef CONFIG_MIPS_WA1130
1897 +#define AVALANCHE
1898 +#define WLAN
1899 +#endif
1900 +
1901 +#endif
1902 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1903 --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1904 +++ linux.dev/arch/mips/ar7/printf.c 2005-10-21 16:45:42.122063750 +0200
1905 @@ -0,0 +1,53 @@
1906 +/*
1907 + * Carsten Langgaard, carstenl@mips.com
1908 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1909 + *
1910 + * This program is free software; you can distribute it and/or modify it
1911 + * under the terms of the GNU General Public License (Version 2) as
1912 + * published by the Free Software Foundation.
1913 + *
1914 + * This program is distributed in the hope it will be useful, but WITHOUT
1915 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1916 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1917 + * for more details.
1918 + *
1919 + * You should have received a copy of the GNU General Public License along
1920 + * with this program; if not, write to the Free Software Foundation, Inc.,
1921 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1922 + *
1923 + * Putting things on the screen/serial line using Adam2 facilities.
1924 + */
1925 +
1926 +#include <linux/config.h>
1927 +#include <linux/init.h>
1928 +#include <linux/kernel.h>
1929 +#include <linux/serial_reg.h>
1930 +#include <linux/spinlock.h>
1931 +#include <asm/io.h>
1932 +#include <asm/serial.h>
1933 +#include <asm/addrspace.h>
1934 +
1935 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1936 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)
1937 +
1938 +static char ppbuf[1024];
1939 +
1940 +void (*prom_print_str)(unsigned int out, char *s, int len);
1941 +
1942 +void prom_printf(char *fmt, ...) __init;
1943 +void prom_printf(char *fmt, ...)
1944 +{
1945 + va_list args;
1946 + int len;
1947 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1948 +
1949 + va_start(args, fmt);
1950 + vsprintf(ppbuf, fmt, args);
1951 + len = strlen(ppbuf);
1952 +
1953 + prom_print_str(1, ppbuf, len);
1954 +
1955 + va_end(args);
1956 + return;
1957 +
1958 +}
1959 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1960 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1961 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-10-21 16:45:42.122063750 +0200
1962 @@ -0,0 +1,350 @@
1963 +#include <linux/config.h>
1964 +#include <linux/init.h>
1965 +#include <linux/string.h>
1966 +#include <linux/kernel.h>
1967 +#include <linux/module.h>
1968 +#include <asm/io.h>
1969 +
1970 +#include "platform.h"
1971 +
1972 +#define ENV_CELL_SIZE 16
1973 +
1974 +/* control field decode */
1975 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1976 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1977 +
1978 +#define ENV_CTRL_MASK 0x03
1979 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1980 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1981 +
1982 +struct env_variable {
1983 + unsigned char varNum;
1984 + unsigned char ctrl;
1985 + unsigned short chksum;
1986 + unsigned char numCells;
1987 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1988 + * here, continues for
1989 + * numCells.
1990 + */
1991 +};
1992 +
1993 +extern unsigned int max_env_entry;
1994 +
1995 +/* Internal macros */
1996 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1997 +
1998 +typedef enum ENV_VARS {
1999 + env_vars_start = 0,
2000 + CPUFREQ,
2001 + MEMSZ,
2002 + FLASHSZ,
2003 + MODETTY0,
2004 + MODETTY1,
2005 + PROMPT,
2006 + BOOTCFG,
2007 + HWA_0,
2008 +#if !defined (AVALANCHE) || defined(TNETC401B)
2009 + HWA_1,
2010 +#endif
2011 +#if !defined(TNETV1020_BOARD)
2012 + HWA_RNDIS,
2013 +#endif
2014 +#if defined (TNETD73XX_BOARD)
2015 + HWA_3,
2016 +#endif
2017 + IPA,
2018 + IPA_SVR,
2019 + BLINE_MAC0,
2020 +#if !defined (AVALANCHE) || defined(TNETC401B)
2021 + BLINE_MAC1,
2022 +#endif
2023 +#if !defined(TNETV1020_BOARD)
2024 + BLINE_RNDIS,
2025 +#endif
2026 +#if defined (TNETD73XX_BOARD)
2027 + BLINE_ATM,
2028 +#endif
2029 +#if !defined(TNETV1020_BOARD)
2030 + USB_PID,
2031 + USB_VID,
2032 + USB_EPPOLLI,
2033 +#endif
2034 + IPA_GATEWAY,
2035 + SUBNET_MASK,
2036 +#if defined (TNETV1050_BOARD)
2037 + BLINE_ESWITCH,
2038 +#endif
2039 +#if !defined(TNETV1020_BOARD)
2040 + USB_SERIAL,
2041 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
2042 +#endif
2043 + REMOTE_USER,
2044 + REMOTE_PASS,
2045 + REMOTE_DIR,
2046 + SYSFREQ,
2047 + LINK_TIMEOUT,
2048 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
2049 + MAC_PORT,
2050 +#endif
2051 + PATH,
2052 + HOSTNAME,
2053 +#ifdef WLAN
2054 + HW_REV_MAJOR,
2055 + HW_REV_MINOR,
2056 + HW_PATCH,
2057 + SW_PATCH,
2058 + SERIAL_NUMBER,
2059 +#endif
2060 + TFTPCFG,
2061 +#if defined (TNETV1050_BOARD)
2062 + HWA_ESWITCH,
2063 +#endif
2064 + /*
2065 + * Add new env variables here.
2066 + * NOTE: New environment variables should always be placed at the end, ie
2067 + * just before env_vars_end.
2068 + */
2069 +
2070 + env_vars_end
2071 +} ENV_VARS;
2072 +
2073 +
2074 +struct env_description {
2075 + ENV_VARS idx;
2076 + char *nm;
2077 + char *alias;
2078 +};
2079 +
2080 +#define ENVSTR(x) #x
2081 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
2082 +
2083 +struct env_description env_ns[] = {
2084 + _ENV_ENTRY(env_vars_start), /* start. */
2085 + _ENV_ENTRY(CPUFREQ),
2086 + _ENV_ENTRY(MEMSZ),
2087 + _ENV_ENTRY(FLASHSZ),
2088 + _ENV_ENTRY(MODETTY0),
2089 + _ENV_ENTRY(MODETTY1),
2090 + _ENV_ENTRY(PROMPT),
2091 + _ENV_ENTRY(BOOTCFG),
2092 + _ENV_ENTRY(HWA_0),
2093 +#if !defined (AVALANCHE) || defined(TNETC401B)
2094 + _ENV_ENTRY(HWA_1),
2095 +#endif
2096 +#if !defined(TNETV1020_BOARD)
2097 + _ENV_ENTRY(HWA_RNDIS),
2098 +#endif
2099 +#if defined (TNETD73XX_BOARD)
2100 + _ENV_ENTRY(HWA_3),
2101 +#endif
2102 + _ENV_ENTRY(IPA),
2103 + _ENV_ENTRY(IPA_SVR),
2104 + _ENV_ENTRY(IPA_GATEWAY),
2105 + _ENV_ENTRY(SUBNET_MASK),
2106 + _ENV_ENTRY(BLINE_MAC0),
2107 +#if !defined (AVALANCHE) || defined(TNETC401B)
2108 + _ENV_ENTRY(BLINE_MAC1),
2109 +#endif
2110 +#if !defined(TNETV1020_BOARD)
2111 + _ENV_ENTRY(BLINE_RNDIS),
2112 +#endif
2113 +#if defined (TNETD73XX_BOARD)
2114 + _ENV_ENTRY(BLINE_ATM),
2115 +#endif
2116 +#if !defined(TNETV1020_BOARD)
2117 + _ENV_ENTRY(USB_PID),
2118 + _ENV_ENTRY(USB_VID),
2119 + _ENV_ENTRY(USB_EPPOLLI),
2120 +#endif
2121 +#if defined (TNETV1050_BOARD)
2122 + _ENV_ENTRY(BLINE_ESWITCH),
2123 +#endif
2124 +#if !defined(TNETV1020_BOARD)
2125 + _ENV_ENTRY(USB_SERIAL),
2126 + _ENV_ENTRY(HWA_HRNDIS),
2127 +#endif
2128 + _ENV_ENTRY(REMOTE_USER),
2129 + _ENV_ENTRY(REMOTE_PASS),
2130 + _ENV_ENTRY(REMOTE_DIR),
2131 + _ENV_ENTRY(SYSFREQ),
2132 + _ENV_ENTRY(LINK_TIMEOUT),
2133 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
2134 + _ENV_ENTRY(MAC_PORT),
2135 +#endif
2136 + _ENV_ENTRY(PATH),
2137 + _ENV_ENTRY(HOSTNAME),
2138 +#ifdef WLAN
2139 + _ENV_ENTRY(HW_REV_MAJOR),
2140 + _ENV_ENTRY(HW_REV_MINOR),
2141 + _ENV_ENTRY(HW_PATCH),
2142 + _ENV_ENTRY(SW_PATCH),
2143 + _ENV_ENTRY(SERIAL_NUMBER),
2144 +#endif
2145 + _ENV_ENTRY(TFTPCFG),
2146 +#if defined (TNETV1050_BOARD)
2147 + _ENV_ENTRY(HWA_ESWITCH),
2148 +#endif
2149 + /*
2150 + * Add new entries below this.
2151 + */
2152 + /* Adam2 environment name alias. */
2153 + { .idx = IPA, .nm = "my_ipaddress" },
2154 + { .idx = CPUFREQ, .nm = "cpufrequency" },
2155 + { .idx = SYSFREQ, .nm = "sysfrequency" },
2156 + { .idx = HWA_0, .nm = "maca" },
2157 +#ifndef AVALANCHE
2158 + { .idx = HWA_1, .nm = "macb" },
2159 +#endif
2160 + { .idx = MODETTY0, .nm = "modetty0" },
2161 + { .idx = MODETTY1, .nm = "modetty1" },
2162 + { .idx = MEMSZ, .nm = "memsize" },
2163 +
2164 + _ENV_ENTRY(env_vars_end) /* delimiter. */
2165 +};
2166 +
2167 +static inline int var_to_idx(const char* var)
2168 +{
2169 + int ii;
2170 +
2171 + /* go over the list of pre-defined environment variables */
2172 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
2173 + /* check if the env variable is listed */
2174 + if (strcmp(env_ns[ii].nm, var) == 0) {
2175 + return env_ns[ii].idx;
2176 + }
2177 +
2178 + /* if an alias is present, check if the alias matches
2179 + * the description
2180 + */
2181 + if (env_ns[ii].alias != NULL) {
2182 + if (strcmp(env_ns[ii].alias, var) == 0) {
2183 + return env_ns[ii].idx;
2184 + }
2185 + }
2186 + }
2187 + return 0;
2188 +}
2189 +
2190 +extern int *_prom_envp;
2191 +
2192 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
2193 + * the next read some seconds later is ok. It looks like something is hidding or
2194 + * overlay the flash address at 0xb0000000. Is this possible?
2195 + *
2196 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
2197 + */
2198 +
2199 +static inline struct env_variable* get_var_by_number(int index)
2200 +{
2201 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
2202 + volatile unsigned char nr;
2203 + int i;
2204 +
2205 + env_var++; /* skip signature */
2206 +
2207 + i = 0;
2208 + nr = readb(&(env_var->varNum));
2209 +
2210 + while (i < max_env_entry && nr != 0xFF) {
2211 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
2212 + if (nr == index) {
2213 + return env_var;
2214 + }
2215 + }
2216 + i++;
2217 + env_var = get_next_block(env_var);
2218 + nr = readb(&(env_var->varNum));
2219 + }
2220 +
2221 + return NULL;
2222 +}
2223 +
2224 +static inline struct env_variable* get_var_by_name(char *var)
2225 +{
2226 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
2227 + volatile unsigned char nr;
2228 + int i;
2229 +
2230 + env_var++; /* skip signature */
2231 +
2232 + nr = readb(&(env_var->varNum));
2233 + i = 0;
2234 +
2235 + while (i < max_env_entry && nr != 0xFF) {
2236 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
2237 + if (strcmp(var, env_var->data) == 0)
2238 + return env_var;
2239 + }
2240 + i++;
2241 + env_var = get_next_block(env_var);
2242 + nr = readb(&(env_var->varNum));
2243 + }
2244 + return NULL;
2245 +}
2246 +
2247 +static inline struct env_variable* get_var(char *var)
2248 +{
2249 + int index = var_to_idx(var);
2250 +
2251 + if (index)
2252 + return get_var_by_number(index);
2253 + else
2254 + return get_var_by_name(var);
2255 +
2256 + return NULL;
2257 +}
2258 +
2259 +static inline char *get_value(struct env_variable* env_var)
2260 +{
2261 + unsigned char *name;
2262 + unsigned char *value;
2263 + unsigned short chksum;
2264 + int i;
2265 +
2266 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
2267 +
2268 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
2269 + name = env_var->data;
2270 + value = env_var->data + strlen(name) + 1;
2271 +
2272 + for(i = 0; i < strlen(name); i++)
2273 + chksum += name[i];
2274 + } else
2275 + value = env_var->data;
2276 +
2277 + for (i = 0; i < strlen(value); i++)
2278 + chksum += value[i];
2279 +
2280 + chksum += env_var->chksum;
2281 + chksum = ~(chksum);
2282 +
2283 + if(chksum != 0) {
2284 + return NULL;
2285 + }
2286 +
2287 + return value;
2288 +}
2289 +
2290 +struct psbl_rec {
2291 + unsigned int psbl_size;
2292 + unsigned int env_base;
2293 + unsigned int env_size;
2294 + unsigned int ffs_base;
2295 + unsigned int ffs_size;
2296 +};
2297 +
2298 +char *prom_psp_getenv(char *envname)
2299 +{
2300 + struct env_variable* env_var;
2301 + char *value;
2302 +
2303 + if (strcmp("bootloader", envname) == 0)
2304 + return "PSPBoot";
2305 +
2306 + if (!(env_var = get_var(envname)))
2307 + return NULL;
2308 +
2309 + value = get_value(env_var);
2310 +
2311 + return value;
2312 +}
2313 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
2314 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
2315 +++ linux.dev/arch/mips/ar7/reset.c 2005-10-21 16:45:42.122063750 +0200
2316 @@ -0,0 +1,56 @@
2317 +/*
2318 + * Carsten Langgaard, carstenl@mips.com
2319 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2320 + *
2321 + * ########################################################################
2322 + *
2323 + * This program is free software; you can distribute it and/or modify it
2324 + * under the terms of the GNU General Public License (Version 2) as
2325 + * published by the Free Software Foundation.
2326 + *
2327 + * This program is distributed in the hope it will be useful, but WITHOUT
2328 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2329 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2330 + * for more details.
2331 + *
2332 + * You should have received a copy of the GNU General Public License along
2333 + * with this program; if not, write to the Free Software Foundation, Inc.,
2334 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2335 + *
2336 + * ########################################################################
2337 + *
2338 + * Reset the MIPS boards.
2339 + *
2340 + */
2341 +#include <linux/config.h>
2342 +
2343 +#include <asm/reboot.h>
2344 +#include <asm/mips-boards/generic.h>
2345 +
2346 +static void ar7_machine_restart(char *command);
2347 +static void ar7_machine_halt(void);
2348 +static void ar7_machine_power_off(void);
2349 +
2350 +static void ar7_machine_restart(char *command)
2351 +{
2352 + volatile unsigned int *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
2353 +
2354 + *softres_reg = 1;
2355 +}
2356 +
2357 +static void ar7_machine_halt(void)
2358 +{
2359 +
2360 +}
2361 +
2362 +static void ar7_machine_power_off(void)
2363 +{
2364 +
2365 +}
2366 +
2367 +void ar7_reboot_setup(void)
2368 +{
2369 + _machine_restart = ar7_machine_restart;
2370 + _machine_halt = ar7_machine_halt;
2371 + _machine_power_off = ar7_machine_power_off;
2372 +}
2373 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
2374 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
2375 +++ linux.dev/arch/mips/ar7/setup.c 2005-10-21 16:45:42.122063750 +0200
2376 @@ -0,0 +1,120 @@
2377 +/*
2378 + * Carsten Langgaard, carstenl@mips.com
2379 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
2380 + *
2381 + * This program is free software; you can distribute it and/or modify it
2382 + * under the terms of the GNU General Public License (Version 2) as
2383 + * published by the Free Software Foundation.
2384 + *
2385 + * This program is distributed in the hope it will be useful, but WITHOUT
2386 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2387 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2388 + * for more details.
2389 + *
2390 + * You should have received a copy of the GNU General Public License along
2391 + * with this program; if not, write to the Free Software Foundation, Inc.,
2392 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2393 + */
2394 +#include <linux/config.h>
2395 +#include <linux/init.h>
2396 +#include <linux/sched.h>
2397 +#include <linux/mc146818rtc.h>
2398 +#include <linux/ioport.h>
2399 +
2400 +#include <asm/cpu.h>
2401 +#include <asm/bootinfo.h>
2402 +#include <asm/irq.h>
2403 +#include <asm/mips-boards/generic.h>
2404 +#include <asm/mips-boards/prom.h>
2405 +
2406 +#include <asm/dma.h>
2407 +#include <asm/time.h>
2408 +#include <asm/traps.h>
2409 +
2410 +#ifdef CONFIG_KGDB
2411 +extern void rs_kgdb_hook(int);
2412 +int remote_debug = 0;
2413 +#endif
2414 +
2415 +extern struct rtc_ops no_rtc_ops;
2416 +
2417 +extern void ar7_reboot_setup(void);
2418 +
2419 +extern void ar7_time_init(void);
2420 +extern void ar7_timer_setup(struct irqaction *irq);
2421 +
2422 +const char *get_system_type(void)
2423 +{
2424 + return "Texas Instruments AR7";
2425 +}
2426 +
2427 +void __init ar7_setup(void)
2428 +{
2429 +#ifdef CONFIG_KGDB
2430 + int rs_putDebugChar(char);
2431 + char rs_getDebugChar(void);
2432 + extern int (*generic_putDebugChar)(char);
2433 + extern char (*generic_getDebugChar)(void);
2434 +#endif
2435 + char *argptr;
2436 +#ifdef CONFIG_SERIAL_CONSOLE
2437 + argptr = prom_getcmdline();
2438 + if ((argptr = strstr(argptr, "console=")) == NULL) {
2439 + char console[20];
2440 + char *s;
2441 + int i = 0;
2442 +
2443 + s = prom_getenv("modetty0");
2444 + strcpy(console, "38400");
2445 +
2446 + if (s != NULL) {
2447 + while (s[i] >= '0' && s[i] <= '9')
2448 + i++;
2449 +
2450 + if (i > 0) {
2451 + strncpy(console, s, i);
2452 + console[i] = 0;
2453 + }
2454 + }
2455 +
2456 + argptr = prom_getcmdline();
2457 + strcat(argptr, " console=ttyS0,");
2458 + strcat(argptr, console);
2459 + }
2460 +#endif
2461 +
2462 +#ifdef CONFIG_KGDB
2463 + argptr = prom_getcmdline();
2464 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2465 + int line;
2466 + argptr += strlen("kgdb=ttyS");
2467 + if (*argptr != '0' && *argptr != '1')
2468 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
2469 + "falling back to /dev/ttyS1\n", *argptr);
2470 + line = *argptr == '0' ? 0 : 1;
2471 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2472 + line ? 1 : 0);
2473 +
2474 + rs_kgdb_hook(line);
2475 + generic_putDebugChar = rs_putDebugChar;
2476 + generic_getDebugChar = rs_getDebugChar;
2477 +
2478 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2479 + "please connect your debugger\n", line ? 1 : 0);
2480 +
2481 + remote_debug = 1;
2482 + /* Breakpoints are in init_IRQ() */
2483 + }
2484 +#endif
2485 +
2486 + argptr = prom_getcmdline();
2487 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
2488 + cpu_data[0].options &= ~MIPS_CPU_FPU;
2489 +
2490 + rtc_ops = &no_rtc_ops;
2491 +
2492 + ar7_reboot_setup();
2493 +
2494 + board_time_init = ar7_time_init;
2495 + board_timer_setup = ar7_timer_setup;
2496 +}
2497 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
2498 --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
2499 +++ linux.dev/arch/mips/ar7/time.c 2005-10-21 16:45:42.126064000 +0200
2500 @@ -0,0 +1,124 @@
2501 +/*
2502 + * Carsten Langgaard, carstenl@mips.com
2503 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2504 + *
2505 + * ########################################################################
2506 + *
2507 + * This program is free software; you can distribute it and/or modify it
2508 + * under the terms of the GNU General Public License (Version 2) as
2509 + * published by the Free Software Foundation.
2510 + *
2511 + * This program is distributed in the hope it will be useful, but WITHOUT
2512 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2513 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2514 + * for more details.
2515 + *
2516 + * You should have received a copy of the GNU General Public License along
2517 + * with this program; if not, write to the Free Software Foundation, Inc.,
2518 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2519 + *
2520 + * ########################################################################
2521 + *
2522 + * Setting up the clock on the MIPS boards.
2523 + *
2524 + */
2525 +
2526 +#include <linux/types.h>
2527 +#include <linux/config.h>
2528 +#include <linux/init.h>
2529 +#include <linux/kernel_stat.h>
2530 +#include <linux/sched.h>
2531 +#include <linux/spinlock.h>
2532 +
2533 +#include <asm/mipsregs.h>
2534 +#include <asm/ptrace.h>
2535 +#include <asm/hardirq.h>
2536 +#include <asm/div64.h>
2537 +
2538 +#include <linux/interrupt.h>
2539 +#include <linux/mc146818rtc.h>
2540 +#include <linux/timex.h>
2541 +
2542 +#include <asm/mips-boards/generic.h>
2543 +#include <asm/mips-boards/prom.h>
2544 +
2545 +extern asmlinkage void mipsIRQ(void);
2546 +
2547 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2548 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
2549 +
2550 +#define MIPS_CPU_TIMER_IRQ 7
2551 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2552 +
2553 +static inline void ack_r4ktimer(unsigned long newval)
2554 +{
2555 + write_c0_compare(newval);
2556 +}
2557 +
2558 +void ar7_timer_interrupt(struct pt_regs *regs)
2559 +{
2560 + int cpu = smp_processor_id();
2561 +
2562 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2563 +
2564 + if (r4k_offset == 0)
2565 + goto null;
2566 +
2567 + do {
2568 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2569 + do_timer(regs);
2570 + r4k_cur += r4k_offset;
2571 + ack_r4ktimer(r4k_cur);
2572 +
2573 + } while (((unsigned long)read_c0_count()
2574 + - r4k_cur) < 0x7fffffff);
2575 +
2576 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2577 +
2578 + if (softirq_pending(cpu))
2579 + do_softirq();
2580 +
2581 + return;
2582 +
2583 +null:
2584 + ack_r4ktimer(0);
2585 +}
2586 +
2587 +/*
2588 + * Figure out the r4k offset, the amount to increment the compare
2589 + * register for each time tick.
2590 + */
2591 +static unsigned long __init cal_r4koff(void)
2592 +{
2593 + return ((CONFIG_AR7_CPU*500000)/HZ);
2594 +}
2595 +
2596 +void __init ar7_time_init(void)
2597 +{
2598 + unsigned long flags;
2599 + unsigned int est_freq;
2600 +
2601 + set_except_vector(0, mipsIRQ);
2602 + write_c0_count(0);
2603 +
2604 + printk("calculating r4koff... ");
2605 + r4k_offset = cal_r4koff();
2606 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2607 +
2608 + est_freq = 2*r4k_offset*HZ;
2609 + est_freq += 5000; /* round */
2610 + est_freq -= est_freq%10000;
2611 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2612 + (est_freq%1000000)*100/1000000);
2613 +}
2614 +
2615 +void __init ar7_timer_setup(struct irqaction *irq)
2616 +{
2617 + /* we are using the cpu counter for timer interrupts */
2618 + irq->handler = no_action; /* we use our own handler */
2619 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2620 +
2621 + r4k_cur = (read_c0_count() + r4k_offset);
2622 + write_c0_compare(r4k_cur);
2623 + set_c0_status(ALLINTS);
2624 +}
2625 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2626 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2627 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-10-21 16:45:42.126064000 +0200
2628 @@ -0,0 +1,924 @@
2629 +/******************************************************************************
2630 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2631 + ******************************************************************************
2632 + * FILE NAME: tnetd73xx_misc.c
2633 + *
2634 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2635 + * FSER Modules API
2636 + * As per TNETD73xx specifications
2637 + *
2638 + * REVISION HISTORY:
2639 + * 27 Nov 02 - Sharath Kumar PSP TII
2640 + * 14 Feb 03 - Anant Gole PSP TII
2641 + *
2642 + * (C) Copyright 2002, Texas Instruments, Inc
2643 + *******************************************************************************/
2644 +
2645 +#define LITTLE_ENDIAN
2646 +#define _LINK_KSEG0_
2647 +
2648 +#include <linux/types.h>
2649 +#include <asm/ar7/tnetd73xx.h>
2650 +#include <asm/ar7/tnetd73xx_misc.h>
2651 +
2652 +/* TNETD73XX Revision */
2653 +u32 tnetd73xx_get_revision(void)
2654 +{
2655 + /* Read Chip revision register - This register is from GPIO module */
2656 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2657 +}
2658 +
2659 +/*****************************************************************************
2660 + * Reset Control Module
2661 + *****************************************************************************/
2662 +
2663 +
2664 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2665 +{
2666 + u32 reset_status;
2667 +
2668 + /* read current reset register */
2669 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2670 +
2671 + if (reset_ctrl == OUT_OF_RESET)
2672 + {
2673 + /* bring module out of reset */
2674 + reset_status |= (1 << reset_module);
2675 + }
2676 + else
2677 + {
2678 + /* put module in reset */
2679 + reset_status &= (~(1 << reset_module));
2680 + }
2681 +
2682 + /* write to the reset register */
2683 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2684 +}
2685 +
2686 +
2687 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2688 +{
2689 + u32 reset_status;
2690 +
2691 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2692 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2693 +}
2694 +
2695 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2696 +{
2697 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2698 +}
2699 +
2700 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2701 +
2702 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2703 +{
2704 + u32 sys_reset_status;
2705 +
2706 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2707 +
2708 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2709 +}
2710 +
2711 +
2712 +/*****************************************************************************
2713 + * Power Control Module
2714 + *****************************************************************************/
2715 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2716 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2717 +
2718 +
2719 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2720 +{
2721 + u32 power_status;
2722 +
2723 + /* read current power down control register */
2724 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2725 +
2726 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2727 + {
2728 + /* power down the module */
2729 + power_status |= (1 << power_module);
2730 + }
2731 + else
2732 + {
2733 + /* power on the module */
2734 + power_status &= (~(1 << power_module));
2735 + }
2736 +
2737 + /* write to the reset register */
2738 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2739 +}
2740 +
2741 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2742 +{
2743 + u32 power_status;
2744 +
2745 + /* read current power down control register */
2746 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2747 +
2748 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2749 +}
2750 +
2751 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2752 +{
2753 + u32 power_status;
2754 +
2755 + /* read current power down control register */
2756 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2757 +
2758 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2759 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2760 +
2761 + /* write to power down control register */
2762 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2763 +}
2764 +
2765 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2766 +{
2767 + u32 power_status;
2768 +
2769 + /* read current power down control register */
2770 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2771 +
2772 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2773 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2774 +
2775 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2776 +}
2777 +
2778 +
2779 +/*****************************************************************************
2780 + * Wakeup Control
2781 + *****************************************************************************/
2782 +
2783 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2784 +
2785 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2786 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2787 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2788 +{
2789 + u32 wakeup_status;
2790 +
2791 + /* read the wakeup control register */
2792 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2793 +
2794 + /* enable/disable */
2795 + if (wakeup_ctrl == WAKEUP_ENABLED)
2796 + {
2797 + /* enable wakeup */
2798 + wakeup_status |= wakeup_int;
2799 + }
2800 + else
2801 + {
2802 + /* disable wakeup */
2803 + wakeup_status &= (~wakeup_int);
2804 + }
2805 +
2806 + /* set polarity */
2807 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2808 + {
2809 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2810 + }
2811 + else
2812 + {
2813 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2814 + }
2815 +
2816 + /* write the wakeup control register */
2817 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2818 +}
2819 +
2820 +
2821 +/*****************************************************************************
2822 + * FSER Control
2823 + *****************************************************************************/
2824 +
2825 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2826 +{
2827 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2828 +}
2829 +
2830 +/*****************************************************************************
2831 + * Clock Control
2832 + *****************************************************************************/
2833 +
2834 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2835 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2836 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2837 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2838 +
2839 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2840 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2841 +
2842 +#define CLKC_PRE_DIVIDER 0x0000001F
2843 +#define CLKC_POST_DIVIDER 0x001F0000
2844 +
2845 +#define CLKC_PLL_STATUS 0x1
2846 +#define CLKC_PLL_FACTOR 0x0000F000
2847 +
2848 +#define BOOTCR_PLL_BYPASS (1 << 5)
2849 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2850 +
2851 +#define MIPS_PLL_SELECT 0x00030000
2852 +#define SYSTEM_PLL_SELECT 0x0000C000
2853 +#define USB_PLL_SELECT 0x000C0000
2854 +#define ADSLSS_PLL_SELECT 0x00C00000
2855 +
2856 +#define MIPS_AFECLKI_SELECT 0x00000000
2857 +#define MIPS_REFCLKI_SELECT 0x00010000
2858 +#define MIPS_XTAL3IN_SELECT 0x00020000
2859 +
2860 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2861 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2862 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2863 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2864 +
2865 +#define USB_SYSPLL_SELECT 0x00000000
2866 +#define USB_REFCLKI_SELECT 0x00040000
2867 +#define USB_XTAL3IN_SELECT 0x00080000
2868 +#define USB_MIPSPLL_SELECT 0x000C0000
2869 +
2870 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2871 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2872 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2873 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2874 +
2875 +#define SYS_MAX CLK_MHZ(150)
2876 +#define SYS_MIN CLK_MHZ(1)
2877 +
2878 +#define MIPS_SYNC_MAX SYS_MAX
2879 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2880 +#define MIPS_MIN CLK_MHZ(1)
2881 +
2882 +#define USB_MAX CLK_MHZ(100)
2883 +#define USB_MIN CLK_MHZ(1)
2884 +
2885 +#define ADSL_MAX CLK_MHZ(180)
2886 +#define ADSL_MIN CLK_MHZ(1)
2887 +
2888 +#define PLL_MUL_MAXFACTOR 15
2889 +#define MAX_DIV_VALUE 32
2890 +#define MIN_DIV_VALUE 1
2891 +
2892 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2893 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2894 +
2895 +#define DIVIDER_LOCK_TIME 10100
2896 +#define PLL_LOCK_TIME 10100 * 75
2897 +
2898 +
2899 +
2900 + /****************************************************************************
2901 + * DATA PURPOSE: PRIVATE Variables
2902 + **************************************************************************/
2903 + static u32 *clk_src[4];
2904 + static u32 mips_pll_out;
2905 + static u32 sys_pll_out;
2906 + static u32 afeclk_inp;
2907 + static u32 refclk_inp;
2908 + static u32 xtal_inp;
2909 + static u32 present_min;
2910 + static u32 present_max;
2911 +
2912 + /* Forward References */
2913 + static u32 find_gcd(u32 min, u32 max);
2914 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2915 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2916 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2917 + static void find_approx(u32 *,u32 *,u32);
2918 +
2919 + /****************************************************************************
2920 + * FUNCTION: tnetd73xx_clkc_init
2921 + ****************************************************************************
2922 + * Description: The routine initializes the internal variables depending on
2923 + * on the sources selected for different clocks.
2924 + ***************************************************************************/
2925 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2926 +{
2927 +
2928 + u32 choice;
2929 +
2930 + afeclk_inp = afeclk;
2931 + refclk_inp = refclk;
2932 + xtal_inp = xtal3in;
2933 +
2934 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2935 + switch(choice)
2936 + {
2937 + case MIPS_AFECLKI_SELECT:
2938 + clk_src[CLKC_MIPS] = &afeclk_inp;
2939 + break;
2940 +
2941 + case MIPS_REFCLKI_SELECT:
2942 + clk_src[CLKC_MIPS] = &refclk_inp;
2943 + break;
2944 +
2945 + case MIPS_XTAL3IN_SELECT:
2946 + clk_src[CLKC_MIPS] = &xtal_inp;
2947 + break;
2948 +
2949 + default :
2950 + clk_src[CLKC_MIPS] = 0;
2951 +
2952 + }
2953 +
2954 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2955 + switch(choice)
2956 + {
2957 + case SYSTEM_AFECLKI_SELECT:
2958 + clk_src[CLKC_SYS] = &afeclk_inp;
2959 + break;
2960 +
2961 + case SYSTEM_REFCLKI_SELECT:
2962 + clk_src[CLKC_SYS] = &refclk_inp;
2963 + break;
2964 +
2965 + case SYSTEM_XTAL3IN_SELECT:
2966 + clk_src[CLKC_SYS] = &xtal_inp;
2967 + break;
2968 +
2969 + case SYSTEM_MIPSPLL_SELECT:
2970 + clk_src[CLKC_SYS] = &mips_pll_out;
2971 + break;
2972 +
2973 + default :
2974 + clk_src[CLKC_SYS] = 0;
2975 +
2976 + }
2977 +
2978 +
2979 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2980 + switch(choice)
2981 + {
2982 + case ADSLSS_AFECLKI_SELECT:
2983 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2984 + break;
2985 +
2986 + case ADSLSS_REFCLKI_SELECT:
2987 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2988 + break;
2989 +
2990 + case ADSLSS_XTAL3IN_SELECT:
2991 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2992 + break;
2993 +
2994 + case ADSLSS_MIPSPLL_SELECT:
2995 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2996 + break;
2997 +
2998 + default :
2999 + clk_src[CLKC_ADSLSS] = 0;
3000 +
3001 + }
3002 +
3003 +
3004 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
3005 + switch(choice)
3006 + {
3007 + case USB_SYSPLL_SELECT:
3008 + clk_src[CLKC_USB] = &sys_pll_out ;
3009 + break;
3010 +
3011 + case USB_REFCLKI_SELECT:
3012 + clk_src[CLKC_USB] = &refclk_inp;
3013 + break;
3014 +
3015 + case USB_XTAL3IN_SELECT:
3016 + clk_src[CLKC_USB] = &xtal_inp;
3017 + break;
3018 +
3019 + case USB_MIPSPLL_SELECT:
3020 + clk_src[CLKC_USB] = &mips_pll_out;
3021 + break;
3022 +
3023 + default :
3024 + clk_src[CLKC_USB] = 0;
3025 +
3026 + }
3027 +}
3028 +
3029 +
3030 +
3031 +/****************************************************************************
3032 + * FUNCTION: tnetd73xx_clkc_set_freq
3033 + ****************************************************************************
3034 + * Description: The above routine is called to set the output_frequency of the
3035 + * selected clock(using clk_id) to the required value given
3036 + * by the variable output_freq.
3037 + ***************************************************************************/
3038 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
3039 +(
3040 + TNETD73XX_CLKC_ID_T clk_id,
3041 + u32 output_freq
3042 + )
3043 +{
3044 + u32 base_freq;
3045 + u32 multiplier;
3046 + u32 divider;
3047 + u32 min_prediv;
3048 + u32 max_prediv;
3049 + u32 prediv;
3050 + u32 postdiv;
3051 + u32 temp;
3052 +
3053 + /* check if PLLs are bypassed*/
3054 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
3055 + {
3056 + return TNETD73XX_ERR_ERROR;
3057 + }
3058 +
3059 + /*check if the requested output_frequency is in valid range*/
3060 + switch( clk_id )
3061 + {
3062 + case CLKC_SYS:
3063 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
3064 + {
3065 + return TNETD73XX_ERR_ERROR;
3066 + }
3067 + present_min = SYS_MIN;
3068 + present_max = SYS_MAX;
3069 + break;
3070 +
3071 + case CLKC_MIPS:
3072 + if((output_freq < MIPS_MIN) ||
3073 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
3074 + {
3075 + return TNETD73XX_ERR_ERROR;
3076 + }
3077 + present_min = MIPS_MIN;
3078 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
3079 + break;
3080 +
3081 + case CLKC_USB:
3082 + if( output_freq < USB_MIN || output_freq > USB_MAX)
3083 + {
3084 + return TNETD73XX_ERR_ERROR;
3085 + }
3086 + present_min = USB_MIN;
3087 + present_max = USB_MAX;
3088 + break;
3089 +
3090 + case CLKC_ADSLSS:
3091 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
3092 + {
3093 + return TNETD73XX_ERR_ERROR;
3094 + }
3095 + present_min = ADSL_MIN;
3096 + present_max = ADSL_MAX;
3097 + break;
3098 + }
3099 +
3100 +
3101 + base_freq = get_base_frequency(clk_id);
3102 +
3103 +
3104 + /* check for minimum base frequency value */
3105 + if( base_freq < MIN_PLL_INP_FREQ)
3106 + {
3107 + return TNETD73XX_ERR_ERROR;
3108 + }
3109 +
3110 + get_val(output_freq, base_freq, &multiplier, &divider);
3111 +
3112 + /* check multiplier range */
3113 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
3114 + {
3115 + return TNETD73XX_ERR_ERROR;
3116 + }
3117 +
3118 + /* check divider value */
3119 + if( divider == 0 )
3120 + {
3121 + return TNETD73XX_ERR_ERROR;
3122 + }
3123 +
3124 + /*compute minimum and maximum predivider values */
3125 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
3126 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
3127 +
3128 + /*adjust the value of divider so that it not less than minimum predivider value*/
3129 + if (divider < min_prediv)
3130 + {
3131 + temp = CEIL(min_prediv, divider);
3132 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
3133 + {
3134 + return TNETD73XX_ERR_ERROR ;
3135 + }
3136 + else
3137 + {
3138 + multiplier = temp * multiplier;
3139 + divider = min_prediv;
3140 + }
3141 +
3142 + }
3143 +
3144 + /* compute predivider and postdivider values */
3145 + prediv = compute_prediv (divider, min_prediv, max_prediv);
3146 + postdiv = CEIL(divider,prediv);
3147 +
3148 + /*return fail if postdivider value falls out of range */
3149 + if(postdiv > MAX_DIV_VALUE)
3150 + {
3151 + return TNETD73XX_ERR_ERROR;
3152 + }
3153 +
3154 +
3155 + /*write predivider and postdivider values*/
3156 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
3157 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
3158 +
3159 + /*wait for divider output to stabilise*/
3160 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
3161 +
3162 + /*write to PLL clock register*/
3163 +
3164 + if(clk_id == CLKC_SYS)
3165 + {
3166 + /* but before writing put DRAM to hold mode */
3167 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
3168 + }
3169 + /*Bring PLL into div mode */
3170 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
3171 +
3172 + /*compute the word to be written to PLLCR
3173 + *corresponding to multiplier value
3174 + */
3175 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
3176 +
3177 + /* wait till PLL enters div mode */
3178 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
3179 + /*nothing*/;
3180 +
3181 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
3182 +
3183 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
3184 + /*nothing*/;
3185 +
3186 +
3187 + /*wait for External pll to lock*/
3188 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
3189 +
3190 + if(clk_id == CLKC_SYS)
3191 + {
3192 + /* Bring DRAM out of hold */
3193 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
3194 + }
3195 +
3196 + return TNETD73XX_ERR_OK ;
3197 +}
3198 +
3199 +/****************************************************************************
3200 + * FUNCTION: tnetd73xx_clkc_get_freq
3201 + ****************************************************************************
3202 + * Description: The above routine is called to get the output_frequency of the
3203 + * selected clock( clk_id)
3204 + ***************************************************************************/
3205 +u32 tnetd73xx_clkc_get_freq
3206 +(
3207 + TNETD73XX_CLKC_ID_T clk_id
3208 + )
3209 +{
3210 +
3211 + u32 clk_ctrl_register;
3212 + u32 clk_pll_setting;
3213 + u32 clk_predivider;
3214 + u32 clk_postdivider;
3215 + u16 pll_factor;
3216 + u32 base_freq;
3217 + u32 divider;
3218 +
3219 + base_freq = get_base_frequency(clk_id);
3220 +
3221 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
3222 +
3223 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
3224 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
3225 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
3226 +
3227 + divider = clk_predivider * clk_postdivider;
3228 +
3229 +
3230 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
3231 + {
3232 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
3233 + }
3234 +
3235 +
3236 + else
3237 + {
3238 + /* return the current clock speed based upon the PLL setting */
3239 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
3240 +
3241 + /* Get the PLL multiplication factor */
3242 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
3243 +
3244 + /* Check if we're in divide mode or multiply mode */
3245 + if((clk_pll_setting & 0x1) == 0)
3246 + {
3247 + /* We're in divide mode */
3248 + if(pll_factor < 0x10)
3249 + return (CEIL(base_freq >> 1, divider));
3250 + else
3251 + return (CEIL(base_freq >> 2, divider));
3252 + }
3253 +
3254 + else /* We're in PLL mode */
3255 + {
3256 + /* See if PLLNDIV & PLLDIV are set */
3257 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
3258 + {
3259 + if(clk_pll_setting & 0x1000)
3260 + {
3261 + /* clk = base_freq * k/2 */
3262 + return(CEIL((base_freq * pll_factor) >> 1, divider));
3263 + }
3264 + else
3265 + {
3266 + /* clk = base_freq * (k-1) / 4)*/
3267 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
3268 + }
3269 + }
3270 + else
3271 + {
3272 + if(pll_factor < 0x10)
3273 + {
3274 + /* clk = base_freq * k */
3275 + return(CEIL(base_freq * pll_factor, divider));
3276 + }
3277 +
3278 + else
3279 + {
3280 + /* clk = base_freq */
3281 + return(CEIL(base_freq, divider));
3282 + }
3283 + }
3284 + }
3285 + return(0); /* Should never reach here */
3286 +
3287 + }
3288 +
3289 +}
3290 +
3291 +
3292 +/* local helper functions */
3293 +
3294 +/****************************************************************************
3295 + * FUNCTION: get_base_frequency
3296 + ****************************************************************************
3297 + * Description: The above routine is called to get base frequency of the clocks.
3298 + ***************************************************************************/
3299 +
3300 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
3301 +{
3302 + /* update the current MIPs PLL output value, if the required
3303 + * source is MIPS PLL
3304 + */
3305 + if ( clk_src[clk_id] == &mips_pll_out)
3306 + {
3307 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3308 + }
3309 +
3310 +
3311 + /* update the current System PLL output value, if the required
3312 + * source is system PLL
3313 + */
3314 + if ( clk_src[clk_id] == &sys_pll_out)
3315 + {
3316 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
3317 + }
3318 +
3319 + return (*clk_src[clk_id]);
3320 +
3321 +}
3322 +
3323 +
3324 +
3325 +/****************************************************************************
3326 + * FUNCTION: find_gcd
3327 + ****************************************************************************
3328 + * Description: The above routine is called to find gcd of 2 numbers.
3329 + ***************************************************************************/
3330 +static u32 find_gcd
3331 +(
3332 + u32 min,
3333 + u32 max
3334 + )
3335 +{
3336 + if (max % min == 0)
3337 + {
3338 + return min;
3339 + }
3340 + else
3341 + {
3342 + return find_gcd(max % min, min);
3343 + }
3344 +}
3345 +
3346 +/****************************************************************************
3347 + * FUNCTION: compute_prediv
3348 + ****************************************************************************
3349 + * Description: The above routine is called to compute predivider value
3350 + ***************************************************************************/
3351 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
3352 +{
3353 + u16 prediv;
3354 +
3355 + /* return the divider itself it it falls within the range of predivider*/
3356 + if (min <= divider && divider <= max)
3357 + {
3358 + return divider;
3359 + }
3360 +
3361 + /* find a value for prediv such that it is a factor of divider */
3362 + for (prediv = max; prediv >= min ; prediv--)
3363 + {
3364 + if ( (divider % prediv) == 0 )
3365 + {
3366 + return prediv;
3367 + }
3368 + }
3369 +
3370 + /* No such factor exists, return min as prediv */
3371 + return min;
3372 +}
3373 +
3374 +/****************************************************************************
3375 + * FUNCTION: get_val
3376 + ****************************************************************************
3377 + * Description: This routine is called to get values of divider and multiplier.
3378 + ***************************************************************************/
3379 +
3380 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
3381 +{
3382 + u32 temp_mul;
3383 + u32 temp_div;
3384 + u32 gcd;
3385 + u32 min_freq;
3386 + u32 max_freq;
3387 +
3388 + /* find gcd of base_freq, output_freq */
3389 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
3390 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
3391 + gcd = find_gcd(min_freq , max_freq);
3392 +
3393 + if(gcd == 0)
3394 + return; /* ERROR */
3395 +
3396 + /* compute values of multiplier and divider */
3397 + temp_mul = output_freq / gcd;
3398 + temp_div = base_freq / gcd;
3399 +
3400 +
3401 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
3402 + if( temp_mul > PLL_MUL_MAXFACTOR )
3403 + {
3404 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
3405 + return;
3406 +
3407 + find_approx(&temp_mul,&temp_div,base_freq);
3408 + }
3409 +
3410 + *multiplier = temp_mul;
3411 + *divider = temp_div;
3412 +}
3413 +
3414 +/****************************************************************************
3415 + * FUNCTION: find_approx
3416 + ****************************************************************************
3417 + * Description: This function gets the approx value of num/denom.
3418 + ***************************************************************************/
3419 +
3420 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
3421 +{
3422 + u32 num1;
3423 + u32 denom1;
3424 + u32 num2;
3425 + u32 denom2;
3426 + int32_t closest;
3427 + int32_t prev_closest;
3428 + u32 temp_num;
3429 + u32 temp_denom;
3430 + u32 normalize;
3431 + u32 gcd;
3432 + u32 output_freq;
3433 +
3434 + num1 = *num;
3435 + denom1 = *denom;
3436 +
3437 + prev_closest = 0x7fffffff; /* maximum possible value */
3438 + num2 = num1;
3439 + denom2 = denom1;
3440 +
3441 + /* start with max */
3442 + for(temp_num = 15; temp_num >=1; temp_num--)
3443 + {
3444 +
3445 + temp_denom = CEIL(temp_num * denom1, num1);
3446 + output_freq = (temp_num * base_freq) / temp_denom;
3447 +
3448 + if(temp_denom < 1)
3449 + {
3450 + break;
3451 + }
3452 + else
3453 + {
3454 + normalize = CEIL(num1,temp_num);
3455 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
3456 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
3457 + {
3458 + prev_closest = closest;
3459 + num2 = temp_num;
3460 + denom2 = temp_denom;
3461 + }
3462 +
3463 + }
3464 +
3465 + }
3466 +
3467 + gcd = find_gcd(num2,denom2);
3468 + num2 = num2 / gcd;
3469 + denom2 = denom2 /gcd;
3470 +
3471 + *num = num2;
3472 + *denom = denom2;
3473 +}
3474 +
3475 +
3476 +/*****************************************************************************
3477 + * GPIO Control
3478 + *****************************************************************************/
3479 +
3480 +/****************************************************************************
3481 + * FUNCTION: tnetd73xx_gpio_init
3482 + ***************************************************************************/
3483 +void tnetd73xx_gpio_init()
3484 +{
3485 + /* Bring module out of reset */
3486 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
3487 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
3488 +}
3489 +
3490 +/****************************************************************************
3491 + * FUNCTION: tnetd73xx_gpio_ctrl
3492 + ***************************************************************************/
3493 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
3494 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
3495 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
3496 +{
3497 + u32 pin_status;
3498 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
3499 + if (pin_mode == GPIO_PIN)
3500 + {
3501 + pin_status |= (1 << gpio_pin);
3502 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3503 +
3504 + /* Set pin direction */
3505 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
3506 + if (pin_direction == GPIO_INPUT_PIN)
3507 + {
3508 + pin_status |= (1 << gpio_pin);
3509 + }
3510 + else /* GPIO_OUTPUT_PIN */
3511 + {
3512 + pin_status &= (~(1 << gpio_pin));
3513 + }
3514 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
3515 + }
3516 + else /* FUNCTIONAL PIN */
3517 + {
3518 + pin_status &= (~(1 << gpio_pin));
3519 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3520 + }
3521 +
3522 +}
3523 +
3524 +/****************************************************************************
3525 + * FUNCTION: tnetd73xx_gpio_out
3526 + ***************************************************************************/
3527 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
3528 +{
3529 + u32 pin_value;
3530 +
3531 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
3532 + if (value == 1)
3533 + {
3534 + pin_value |= (1 << gpio_pin);
3535 + }
3536 + else
3537 + {
3538 + pin_value &= (~(1 << gpio_pin));
3539 + }
3540 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
3541 +}
3542 +
3543 +/****************************************************************************
3544 + * FUNCTION: tnetd73xx_gpio_in
3545 + ***************************************************************************/
3546 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
3547 +{
3548 + u32 pin_value;
3549 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
3550 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
3551 +}
3552 +
3553 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
3554 --- linux.old/arch/mips/config-shared.in 2005-10-21 16:43:18.917114000 +0200
3555 +++ linux.dev/arch/mips/config-shared.in 2005-10-21 16:45:42.126064000 +0200
3556 @@ -20,6 +20,16 @@
3557 mainmenu_option next_comment
3558 comment 'Machine selection'
3559 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3560 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3561 +if [ "$CONFIG_AR7" = "y" ]; then
3562 + choice 'Texas Instruments Reference Platform' \
3563 + "AR7DB CONFIG_AR7DB \
3564 + AR7RD CONFIG_AR7RD \
3565 + AR7WRD CONFIG_AR7WRD" AR7DB
3566 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
3567 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
3568 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3569 +fi
3570 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3571 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3572 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3573 @@ -239,6 +249,10 @@
3574 define_bool CONFIG_NONCOHERENT_IO y
3575 define_bool CONFIG_PC_KEYB y
3576 fi
3577 +if [ "$CONFIG_AR7" = "y" ]; then
3578 + define_bool CONFIG_NONCOHERENT_IO y
3579 + define_bool CONFIG_SWAP_IO_SPACE y
3580 +fi
3581 if [ "$CONFIG_CASIO_E55" = "y" ]; then
3582 define_bool CONFIG_IRQ_CPU y
3583 define_bool CONFIG_NONCOHERENT_IO y
3584 @@ -736,6 +750,7 @@
3585 mainmenu_option next_comment
3586 comment 'General setup'
3587 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3588 + "$CONFIG_AR7" = "y" -o \
3589 "$CONFIG_CASIO_E55" = "y" -o \
3590 "$CONFIG_DDB5074" = "y" -o \
3591 "$CONFIG_DDB5476" = "y" -o \
3592 @@ -797,6 +812,7 @@
3593 bool 'Networking support' CONFIG_NET
3594
3595 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3596 + "$CONFIG_AR7" = "y" -o \
3597 "$CONFIG_CASIO_E55" = "y" -o \
3598 "$CONFIG_DECSTATION" = "y" -o \
3599 "$CONFIG_IBM_WORKPAD" = "y" -o \
3600 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
3601 --- linux.old/arch/mips/kernel/head.S 2005-10-21 16:43:16.396956500 +0200
3602 +++ linux.dev/arch/mips/kernel/head.S 2005-10-21 16:45:42.126064000 +0200
3603 @@ -75,11 +75,11 @@
3604 * size!
3605 */
3606 NESTED(except_vec4, 0, sp)
3607 - .set push
3608 - .set noreorder
3609 -1: j 1b /* Dummy, will be replaced */
3610 - nop
3611 - .set pop
3612 + .set mips2
3613 + lui k0, 0x9400
3614 + ori k0, 0x200
3615 + jr k0
3616 + nop
3617 END(except_vec4)
3618
3619 /*
3620 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
3621 --- linux.old/arch/mips/kernel/irq.c 2004-02-18 14:36:30.000000000 +0100
3622 +++ linux.dev/arch/mips/kernel/irq.c 2005-10-21 16:45:42.130064250 +0200
3623 @@ -76,6 +76,7 @@
3624 * Generic, controller-independent functions:
3625 */
3626
3627 +#ifndef CONFIG_AR7
3628 int get_irq_list(char *buf)
3629 {
3630 int i, j;
3631 @@ -110,6 +111,7 @@
3632 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3633 return p - buf;
3634 }
3635 +#endif
3636
3637 #ifdef CONFIG_SMP
3638 int global_irq_holder = NO_PROC_ID;
3639 @@ -525,6 +527,7 @@
3640 *
3641 */
3642
3643 +#ifndef CONFIG_AR7
3644 int request_irq(unsigned int irq,
3645 void (*handler)(int, void *, struct pt_regs *),
3646 unsigned long irqflags,
3647 @@ -569,6 +572,7 @@
3648 kfree(action);
3649 return retval;
3650 }
3651 +#endif
3652
3653 /**
3654 * free_irq - free an interrupt
3655 @@ -588,6 +592,7 @@
3656 * the machine.
3657 */
3658
3659 +#ifndef CONFIG_AR7
3660 void free_irq(unsigned int irq, void *dev_id)
3661 {
3662 irq_desc_t *desc;
3663 @@ -629,6 +634,7 @@
3664 return;
3665 }
3666 }
3667 +#endif
3668
3669 /*
3670 * IRQ autodetection code..
3671 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
3672 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
3673 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-10-21 17:02:14.507635750 +0200
3674 @@ -40,6 +40,12 @@
3675 extern long __strnlen_user_nocheck_asm(const char *s);
3676 extern long __strnlen_user_asm(const char *s);
3677
3678 +#ifdef CONFIG_AR7
3679 +#include <asm/ar7/adam2_env.h>
3680 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3681 +#endif
3682 +
3683 +
3684 EXPORT_SYMBOL(mips_machtype);
3685 #ifdef CONFIG_EISA
3686 EXPORT_SYMBOL(EISA_bus);
3687 @@ -103,3 +109,10 @@
3688 #endif
3689
3690 EXPORT_SYMBOL(get_wchan);
3691 +
3692 +#ifdef CONFIG_AR7
3693 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3694 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3695 +EXPORT_SYMBOL_NOVERS(prom_iterenv);
3696 +#endif
3697 +
3698 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3699 --- linux.old/arch/mips/kernel/setup.c 2005-10-21 16:43:16.396956500 +0200
3700 +++ linux.dev/arch/mips/kernel/setup.c 2005-10-21 16:45:42.130064250 +0200
3701 @@ -235,7 +235,11 @@
3702 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3703 #define PFN_PHYS(x) ((x) << PAGE_SHIFT)
3704
3705 +#ifdef CONFIG_AR7
3706 +#define MAXMEM HIGHMEM_START + CONFIG_AR7_MEMORY
3707 +#else
3708 #define MAXMEM HIGHMEM_START
3709 +#endif
3710 #define MAXMEM_PFN PFN_DOWN(MAXMEM)
3711
3712 static inline void bootmem_init(void)
3713 @@ -320,7 +324,12 @@
3714 #endif
3715
3716 /* Initialize the boot-time allocator with low memory only. */
3717 +#ifdef CONFIG_AR7
3718 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
3719 + CONFIG_AR7_MEMORY >> PAGE_SHIFT, max_low_pfn);
3720 +#else
3721 bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3722 +#endif
3723
3724 /*
3725 * Register fully available low RAM pages with the bootmem allocator.
3726 @@ -494,6 +503,7 @@
3727 void hp_setup(void);
3728 void au1x00_setup(void);
3729 void frame_info_init(void);
3730 + void ar7_setup(void);
3731
3732 frame_info_init();
3733 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3734 @@ -691,6 +701,11 @@
3735 pmc_yosemite_setup();
3736 break;
3737 #endif
3738 +#ifdef CONFIG_AR7
3739 + case MACH_GROUP_UNKNOWN:
3740 + ar7_setup();
3741 + break;
3742 +#endif
3743 default:
3744 panic("Unsupported architecture");
3745 }
3746 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3747 --- linux.old/arch/mips/kernel/traps.c 2005-10-21 16:43:16.400956750 +0200
3748 +++ linux.dev/arch/mips/kernel/traps.c 2005-10-21 16:45:42.130064250 +0200
3749 @@ -869,9 +869,15 @@
3750
3751 exception_handlers[n] = handler;
3752 if (n == 0 && cpu_has_divec) {
3753 +#ifdef CONFIG_AR7
3754 + *(volatile u32 *)(KSEG0+0x200+CONFIG_AR7_MEMORY) = 0x08000000 |
3755 + (0x03ffffff & (handler >> 2));
3756 + flush_icache_range(KSEG0+0x200+CONFIG_AR7_MEMORY, KSEG0 + 0x204 + CONFIG_AR7_MEMORY);
3757 +#else
3758 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3759 (0x03ffffff & (handler >> 2));
3760 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3761 +#endif
3762 }
3763 return (void *)old_handler;
3764 }
3765 @@ -1022,6 +1028,12 @@
3766
3767 if (board_nmi_handler_setup)
3768 board_nmi_handler_setup();
3769 +#ifdef CONFIG_AR7
3770 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x80), &except_vec1_generic, 0x80);
3771 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x180), &except_vec3_generic, 0x80);
3772 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x200), &except_vec4, 8);
3773 + flush_icache_range(KSEG0 + CONFIG_AR7_MEMORY, KSEG0 + CONFIG_AR7_MEMORY + 0x208);
3774 +#endif
3775
3776 flush_icache_range(KSEG0, KSEG0 + 0x400);
3777
3778 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3779 --- linux.old/arch/mips/lib/promlib.c 2003-08-25 13:44:40.000000000 +0200
3780 +++ linux.dev/arch/mips/lib/promlib.c 2005-10-21 16:45:42.130064250 +0200
3781 @@ -1,6 +1,8 @@
3782 #include <stdarg.h>
3783 #include <linux/kernel.h>
3784 +#include <linux/config.h>
3785
3786 +#ifndef CONFIG_AR7
3787 extern void prom_putchar(char);
3788
3789 void prom_printf(char *fmt, ...)
3790 @@ -22,3 +24,4 @@
3791 }
3792 va_end(args);
3793 }
3794 +#endif
3795 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3796 --- linux.old/arch/mips/mm/init.c 2004-02-18 14:36:30.000000000 +0100
3797 +++ linux.dev/arch/mips/mm/init.c 2005-10-21 16:45:42.134064500 +0200
3798 @@ -248,6 +248,9 @@
3799
3800 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3801 low = max_low_pfn;
3802 +#ifdef CONFIG_AR7
3803 + low = NODE_DATA(0)->bdata->node_low_pfn - (CONFIG_AR7_MEMORY >> PAGE_SHIFT);
3804 +#endif
3805 high = highend_pfn;
3806
3807 #ifdef CONFIG_ISA
3808 @@ -270,7 +273,11 @@
3809 zones_size[ZONE_HIGHMEM] = high - low;
3810 #endif
3811
3812 +#ifdef CONFIG_AR7
3813 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, CONFIG_AR7_MEMORY, 0);
3814 +#else
3815 free_area_init(zones_size);
3816 +#endif
3817 }
3818
3819 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3820 @@ -298,6 +305,10 @@
3821 return 0;
3822 }
3823
3824 +#ifdef CONFIG_AR7
3825 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3826 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3827 +#endif
3828 void __init mem_init(void)
3829 {
3830 unsigned long codesize, reservedpages, datasize, initsize;
3831 @@ -315,9 +326,21 @@
3832 #else
3833 max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3834 #endif
3835 +
3836 +#ifdef CONFIG_AR7
3837 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3838 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3839 +
3840 +#if 0
3841 + /* WTF? */
3842 + free_bootmem_node(NODE_DATA(0), (CONFIG_AR7_MEMORY+PAGE_SIZE), (__pa(&_ftext))-(CONFIG_AR7_MEMORY+PAGE_SIZE));
3843 +#endif
3844 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3845 +#else
3846 high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3847 -
3848 totalram_pages += free_all_bootmem();
3849 +#endif
3850 +
3851 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3852
3853 reservedpages = ram = 0;
3854 diff -urN linux.old/drivers/char/Config.in linux.dev/drivers/char/Config.in
3855 --- linux.old/drivers/char/Config.in 2005-10-21 16:43:16.440959250 +0200
3856 +++ linux.dev/drivers/char/Config.in 2005-10-21 17:02:20.199991500 +0200
3857 @@ -188,6 +188,14 @@
3858 tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
3859 fi
3860
3861 +if [ "$CONFIG_AR7" = "y" ]; then
3862 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
3863 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
3864 +
3865 + define_int CONFIG_AR7_VLYNQ_PORTS 2
3866 + tristate 'ADAM2 environment support (read-only)' CONFIG_AR7_ADAM2
3867 +fi
3868 +
3869 source drivers/i2c/Config.in
3870
3871 mainmenu_option next_comment
3872 diff -urN linux.old/drivers/char/Config.in.orig linux.dev/drivers/char/Config.in.orig
3873 --- linux.old/drivers/char/Config.in.orig 1970-01-01 01:00:00.000000000 +0100
3874 +++ linux.dev/drivers/char/Config.in.orig 2005-10-21 16:45:47.854422000 +0200
3875 @@ -0,0 +1,414 @@
3876 +#
3877 +# Character device configuration
3878 +#
3879 +mainmenu_option next_comment
3880 +comment 'Character devices'
3881 +
3882 +bool 'Virtual terminal' CONFIG_VT
3883 +if [ "$CONFIG_VT" = "y" ]; then
3884 + bool ' Support for console on virtual terminal' CONFIG_VT_CONSOLE
3885 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3886 + bool ' Support for Lasi/Dino PS2 port' CONFIG_GSC_PS2
3887 + fi
3888 +fi
3889 +tristate 'Standard/generic (8250/16550 and compatible UARTs) serial support' CONFIG_SERIAL
3890 +if [ "$CONFIG_SERIAL" = "y" ]; then
3891 + bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
3892 + if [ "$CONFIG_GSC_LASI" = "y" ]; then
3893 + bool ' serial port on GSC support' CONFIG_SERIAL_GSC
3894 + fi
3895 + if [ "$CONFIG_IA64" = "y" ]; then
3896 + bool ' Support for serial port described by EFI HCDP table' CONFIG_SERIAL_HCDP
3897 + fi
3898 + if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
3899 + tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
3900 + tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
3901 + fi
3902 +fi
3903 +dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
3904 +if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
3905 + bool ' Support more than 4 serial ports' CONFIG_SERIAL_MANY_PORTS
3906 + bool ' Support for sharing serial interrupts' CONFIG_SERIAL_SHARE_IRQ
3907 + bool ' Autodetect IRQ on standard ports (unsafe)' CONFIG_SERIAL_DETECT_IRQ
3908 + bool ' Support special multiport boards' CONFIG_SERIAL_MULTIPORT
3909 + bool ' Support the Bell Technologies HUB6 card' CONFIG_HUB6
3910 +fi
3911 +bool 'Non-standard serial port support' CONFIG_SERIAL_NONSTANDARD
3912 +if [ "$CONFIG_SERIAL_NONSTANDARD" = "y" ]; then
3913 + tristate ' Computone IntelliPort Plus serial support' CONFIG_COMPUTONE
3914 + tristate ' Comtrol Rocketport support' CONFIG_ROCKETPORT
3915 + tristate ' Cyclades async mux support' CONFIG_CYCLADES
3916 + if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_CYCLADES" != "n" ]; then
3917 + bool ' Cyclades-Z interrupt mode operation (EXPERIMENTAL)' CONFIG_CYZ_INTR
3918 + fi
3919 + if [ "$CONFIG_X86_64" != "y" ]; then
3920 + tristate ' Digiboard Intelligent Async Support' CONFIG_DIGIEPCA
3921 + if [ "$CONFIG_DIGIEPCA" = "n" ]; then
3922 + tristate ' Digiboard PC/Xx Support' CONFIG_DIGI
3923 + fi
3924 + fi
3925 + dep_tristate ' Hayes ESP serial port support' CONFIG_ESPSERIAL $CONFIG_ISA
3926 + tristate ' Moxa Intellio support' CONFIG_MOXA_INTELLIO
3927 + tristate ' Moxa SmartIO support' CONFIG_MOXA_SMARTIO
3928 + if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
3929 + dep_tristate ' Multi-Tech multiport card support (EXPERIMENTAL)' CONFIG_ISI m
3930 + fi
3931 + tristate ' Microgate SyncLink card support' CONFIG_SYNCLINK
3932 + tristate ' SyncLink Multiport support' CONFIG_SYNCLINKMP
3933 + tristate ' HDLC line discipline support' CONFIG_N_HDLC
3934 + tristate ' SDL RISCom/8 card support' CONFIG_RISCOM8
3935 + if [ "$CONFIG_X86_64" != "y" ]; then
3936 + tristate ' Specialix IO8+ card support' CONFIG_SPECIALIX
3937 + if [ "$CONFIG_SPECIALIX" != "n" ]; then
3938 + bool ' Specialix DTR/RTS pin is RTS' CONFIG_SPECIALIX_RTSCTS
3939 + fi
3940 + tristate ' Specialix SX (and SI) card support' CONFIG_SX
3941 + tristate ' Specialix RIO system support' CONFIG_RIO
3942 + if [ "$CONFIG_RIO" != "n" ]; then
3943 + bool ' Support really old RIO/PCI cards' CONFIG_RIO_OLDPCI
3944 + fi
3945 + fi
3946 + bool ' Stallion multiport serial support' CONFIG_STALDRV
3947 + if [ "$CONFIG_STALDRV" = "y" ]; then
3948 + tristate ' Stallion EasyIO or EC8/32 support' CONFIG_STALLION
3949 + tristate ' Stallion EC8/64, ONboard, Brumby support' CONFIG_ISTALLION
3950 + fi
3951 + if [ "$CONFIG_PARISC" = "y" ]; then
3952 + if [ "$CONFIG_PDC_CONSOLE" != "y" ]; then
3953 + bool ' Serial MUX support' CONFIG_SERIAL_MUX CONFIG_SERIAL_NONSTANDARD
3954 + fi
3955 + if [ "$CONFIG_SERIAL_MUX" != "y" ]; then
3956 + bool ' PDC software console support' CONFIG_PDC_CONSOLE CONFIG_SERIAL_NONSTANDARD
3957 + fi
3958 + fi
3959 + if [ "$CONFIG_MIPS" = "y" ]; then
3960 + bool ' TX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
3961 + dep_bool ' Console on TX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
3962 + bool ' TMPTX39XX/49XX serial port support' CONFIG_SERIAL_TXX9
3963 + dep_bool ' Console on TMPTX39XX/49XX serial port' CONFIG_SERIAL_TXX9_CONSOLE $CONFIG_SERIAL_TXX9
3964 + if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
3965 + bool ' Enable Au1x00 UART Support' CONFIG_AU1X00_UART
3966 + if [ "$CONFIG_AU1X00_UART" = "y" ]; then
3967 + bool ' Enable Au1x00 serial console' CONFIG_AU1X00_SERIAL_CONSOLE
3968 + fi
3969 + dep_tristate ' Au1x00 USB TTY Device support' CONFIG_AU1X00_USB_TTY $CONFIG_SOC_AU1X00
3970 + if [ "$CONFIG_AU1000_USB_TTY" != "y" ]; then
3971 + dep_tristate ' Au1x00 USB Raw Device support' CONFIG_AU1X00_USB_RAW $CONFIG_SOC_AU1X00
3972 + fi
3973 + if [ "$CONFIG_AU1X00_USB_TTY" != "n" -o \
3974 + "$CONFIG_AU1X00_USB_RAW" != "n" ]; then
3975 + define_bool CONFIG_AU1X00_USB_DEVICE y
3976 + fi
3977 + fi
3978 + bool ' TXx927 SIO support' CONFIG_TXX927_SERIAL
3979 + if [ "$CONFIG_TXX927_SERIAL" = "y" ]; then
3980 + bool ' TXx927 SIO Console support' CONFIG_TXX927_SERIAL_CONSOLE
3981 + fi
3982 + if [ "$CONFIG_SIBYTE_SB1xxx_SOC" = "y" ]; then
3983 + bool ' Support for BCM1xxx onchip DUART' CONFIG_SIBYTE_SB1250_DUART
3984 + if [ "$CONFIG_SIBYTE_SB1250_DUART" = "y" ]; then
3985 + bool ' Console on BCM1xxx DUART' CONFIG_SIBYTE_SB1250_DUART_CONSOLE
3986 + if [ "$CONFIG_SIBYTE_SB1250_DUART_CONSOLE" = "y" ]; then
3987 + define_bool CONFIG_SERIAL_CONSOLE y
3988 + fi
3989 + fi
3990 + fi
3991 + fi
3992 + if [ "$CONFIG_DECSTATION" = "y" ]; then
3993 + bool ' DECstation serial support' CONFIG_SERIAL_DEC
3994 + dep_bool ' Support for console on a DECstation serial port' CONFIG_SERIAL_DEC_CONSOLE $CONFIG_SERIAL_DEC
3995 + dep_bool ' DZ11 serial support' CONFIG_DZ $CONFIG_SERIAL_DEC $CONFIG_MIPS32
3996 + dep_bool ' Z85C30 serial support' CONFIG_ZS $CONFIG_SERIAL_DEC $CONFIG_TC
3997 + fi
3998 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
3999 + bool ' SGI Zilog85C30 serial support' CONFIG_IP22_SERIAL
4000 + fi
4001 + if [ "$CONFIG_IA64" = "y" ]; then
4002 + bool ' SGI SN2 l1 serial port support' CONFIG_SGI_L1_SERIAL
4003 + if [ "$CONFIG_SGI_L1_SERIAL" = "y" ]; then
4004 + bool ' SGI SN2 l1 Console support' CONFIG_SGI_L1_SERIAL_CONSOLE
4005 + fi
4006 + if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then
4007 + bool ' SGI SN2 IOC4 serial port support' CONFIG_SGI_IOC4_SERIAL
4008 + fi
4009 + fi
4010 +fi
4011 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
4012 + tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
4013 +fi
4014 +if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
4015 + bool 'DC21285 serial port support' CONFIG_SERIAL_21285
4016 + if [ "$CONFIG_SERIAL_21285" = "y" ]; then
4017 + if [ "$CONFIG_OBSOLETE" = "y" ]; then
4018 + bool ' Use /dev/ttyS0 device (OBSOLETE)' CONFIG_SERIAL_21285_OLD
4019 + fi
4020 + bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
4021 + fi
4022 + if [ "$CONFIG_PARISC" = "y" ]; then
4023 + bool ' PDC software console support' CONFIG_PDC_CONSOLE
4024 + fi
4025 +fi
4026 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
4027 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
4028 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
4029 + define_bool CONFIG_IT8172_CIR y
4030 + else
4031 + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
4032 + fi
4033 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
4034 + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
4035 +fi
4036 +if [ "$CONFIG_MIPS_IVR" = "y" ]; then
4037 + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
4038 + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
4039 + define_bool CONFIG_IT8172_CIR y
4040 + fi
4041 + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
4042 +fi
4043 +if [ "$CONFIG_CPU_VR41XX" = "y" ]; then
4044 + bool 'NEC VR4100 series Keyboard Interface Unit Support ' CONFIG_VR41XX_KIU
4045 +fi
4046 +bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
4047 +if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
4048 + int 'Maximum number of Unix98 PTYs in use (0-2048)' CONFIG_UNIX98_PTY_COUNT 256
4049 +fi
4050 +if [ "$CONFIG_PARPORT" != "n" ]; then
4051 + dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
4052 + if [ "$CONFIG_PRINTER" != "n" ]; then
4053 + bool ' Support for console on line printer' CONFIG_LP_CONSOLE
4054 + fi
4055 + dep_tristate 'Support for user-space parallel port device drivers' CONFIG_PPDEV $CONFIG_PARPORT
4056 + dep_tristate 'Texas Instruments parallel link cable support' CONFIG_TIPAR $CONFIG_PARPORT
4057 +fi
4058 +
4059 +if [ "$CONFIG_PPC64" = "y" ] ; then
4060 + bool 'pSeries Hypervisor Virtual Console support' CONFIG_HVC_CONSOLE
4061 +fi
4062 +if [ "$CONFIG_ALL_PPC" = "y" ]; then
4063 + tristate 'Total Impact briQ front panel driver' CONFIG_BRIQ_PANEL
4064 +fi
4065 +
4066 +if [ "$CONFIG_AR7" = "y" ]; then
4067 + bool 'VLYNQ support for the TI SOC' CONFIG_AR7_VLYNQ
4068 + dep_bool 'VLYNQ clock source Internal' CONFIG_VLYNQ_CLK_LOCAL $CONFIG_AR7_VLYNQ
4069 +
4070 + define_int CONFIG_AR7_VLYNQ_PORTS 2
4071 +fi
4072 +
4073 +source drivers/i2c/Config.in
4074 +
4075 +mainmenu_option next_comment
4076 +comment 'Mice'
4077 +tristate 'Bus Mouse Support' CONFIG_BUSMOUSE
4078 +if [ "$CONFIG_BUSMOUSE" != "n" ]; then
4079 + dep_tristate ' ATIXL busmouse support' CONFIG_ATIXL_BUSMOUSE $CONFIG_BUSMOUSE
4080 + dep_tristate ' Logitech busmouse support' CONFIG_LOGIBUSMOUSE $CONFIG_BUSMOUSE
4081 + dep_tristate ' Microsoft busmouse support' CONFIG_MS_BUSMOUSE $CONFIG_BUSMOUSE
4082 + if [ "$CONFIG_ADB" = "y" -a "$CONFIG_ADB_KEYBOARD" = "y" ]; then
4083 + dep_tristate ' Apple Desktop Bus mouse support (old driver)' CONFIG_ADBMOUSE $CONFIG_BUSMOUSE
4084 + fi
4085 +# if [ "$CONFIG_DECSTATION" = "y" ]; then
4086 +# dep_bool ' MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE $CONFIG_ACCESSBUS
4087 +# fi
4088 +fi
4089 +
4090 +tristate 'Mouse Support (not serial and bus mice)' CONFIG_MOUSE
4091 +if [ "$CONFIG_MOUSE" != "n" ]; then
4092 + bool ' PS/2 mouse (aka "auxiliary device") support' CONFIG_PSMOUSE
4093 + tristate ' C&T 82C710 mouse port support (as on TI Travelmate)' CONFIG_82C710_MOUSE
4094 + tristate ' PC110 digitizer pad support' CONFIG_PC110_PAD
4095 + tristate ' MK712 touch screen support' CONFIG_MK712_MOUSE
4096 +fi
4097 +endmenu
4098 +
4099 +source drivers/char/joystick/Config.in
4100 +
4101 +tristate 'QIC-02 tape support' CONFIG_QIC02_TAPE
4102 +if [ "$CONFIG_QIC02_TAPE" != "n" ]; then
4103 + bool ' Do you want runtime configuration for QIC-02' CONFIG_QIC02_DYNCONF
4104 + if [ "$CONFIG_QIC02_DYNCONF" != "y" ]; then
4105 + comment ' Edit configuration parameters in ./include/linux/tpqic02.h!'
4106 + else
4107 + comment ' Setting runtime QIC-02 configuration is done with qic02conf'
4108 + comment ' from the tpqic02-support package. It is available at'
4109 + comment ' metalab.unc.edu or ftp://titus.cfw.com/pub/Linux/util/'
4110 + fi
4111 +fi
4112 +
4113 +tristate 'IPMI top-level message handler' CONFIG_IPMI_HANDLER
4114 +dep_mbool ' Generate a panic event to all BMCs on a panic' CONFIG_IPMI_PANIC_EVENT $CONFIG_IPMI_HANDLER
4115 +dep_tristate ' Device interface for IPMI' CONFIG_IPMI_DEVICE_INTERFACE $CONFIG_IPMI_HANDLER
4116 +dep_tristate ' IPMI KCS handler' CONFIG_IPMI_KCS $CONFIG_IPMI_HANDLER
4117 +dep_tristate ' IPMI Watchdog Timer' CONFIG_IPMI_WATCHDOG $CONFIG_IPMI_HANDLER
4118 +
4119 +mainmenu_option next_comment
4120 +comment 'Watchdog Cards'
4121 +bool 'Watchdog Timer Support' CONFIG_WATCHDOG
4122 +if [ "$CONFIG_WATCHDOG" != "n" ]; then
4123 + bool ' Disable watchdog shutdown on close' CONFIG_WATCHDOG_NOWAYOUT
4124 + tristate ' Acquire SBC Watchdog Timer' CONFIG_ACQUIRE_WDT
4125 + tristate ' Advantech SBC Watchdog Timer' CONFIG_ADVANTECH_WDT
4126 + tristate ' ALi M7101 PMU on ALi 1535D+ Watchdog Timer' CONFIG_ALIM1535_WDT
4127 + tristate ' ALi M7101 PMU Watchdog Timer' CONFIG_ALIM7101_WDT
4128 + tristate ' AMD "Elan" SC520 Watchdog Timer' CONFIG_SC520_WDT
4129 + tristate ' Berkshire Products PC Watchdog' CONFIG_PCWATCHDOG
4130 + if [ "$CONFIG_FOOTBRIDGE" = "y" ]; then
4131 + tristate ' DC21285 watchdog' CONFIG_21285_WATCHDOG
4132 + if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
4133 + tristate ' NetWinder WB83C977 watchdog' CONFIG_977_WATCHDOG
4134 + fi
4135 + fi
4136 + tristate ' Eurotech CPU-1220/1410 Watchdog Timer' CONFIG_EUROTECH_WDT
4137 + tristate ' IB700 SBC Watchdog Timer' CONFIG_IB700_WDT
4138 + tristate ' ICP ELectronics Wafer 5823 Watchdog' CONFIG_WAFER_WDT
4139 + tristate ' Intel i810 TCO timer / Watchdog' CONFIG_I810_TCO
4140 + tristate ' Mixcom Watchdog' CONFIG_MIXCOMWD
4141 + tristate ' SBC-60XX Watchdog Timer' CONFIG_60XX_WDT
4142 + dep_tristate ' SC1200 Watchdog Timer (EXPERIMENTAL)' CONFIG_SC1200_WDT $CONFIG_EXPERIMENTAL
4143 + tristate ' NatSemi SCx200 Watchdog' CONFIG_SCx200_WDT
4144 + tristate ' Software Watchdog' CONFIG_SOFT_WATCHDOG
4145 + tristate ' W83877F (EMACS) Watchdog Timer' CONFIG_W83877F_WDT
4146 + tristate ' WDT Watchdog timer' CONFIG_WDT
4147 + tristate ' WDT PCI Watchdog timer' CONFIG_WDTPCI
4148 + if [ "$CONFIG_WDT" != "n" ]; then
4149 + bool ' WDT501 features' CONFIG_WDT_501
4150 + if [ "$CONFIG_WDT_501" = "y" ]; then
4151 + bool ' Fan Tachometer' CONFIG_WDT_501_FAN
4152 + fi
4153 + fi
4154 + tristate ' ZF MachZ Watchdog' CONFIG_MACHZ_WDT
4155 + if [ "$CONFIG_SGI_IP22" = "y" ]; then
4156 + dep_tristate ' Indy/I2 Hardware Watchdog' CONFIG_INDYDOG $CONFIG_SGI_IP22
4157 + fi
4158 + if [ "$CONFIG_8xx" = "y" ]; then
4159 + tristate ' MPC8xx Watchdog Timer' CONFIG_8xx_WDT
4160 + fi
4161 +fi
4162 +endmenu
4163 +
4164 +if [ "$CONFIG_ARCH_NETWINDER" = "y" ]; then
4165 + tristate 'NetWinder thermometer support' CONFIG_DS1620
4166 + tristate 'NetWinder Button' CONFIG_NWBUTTON
4167 + if [ "$CONFIG_NWBUTTON" != "n" ]; then
4168 + bool ' Reboot Using Button' CONFIG_NWBUTTON_REBOOT
4169 + fi
4170 + tristate 'NetWinder flash support' CONFIG_NWFLASH
4171 +fi
4172 +tristate 'NatSemi SCx200 Support' CONFIG_SCx200
4173 +dep_tristate ' NatSemi SCx200 GPIO Support' CONFIG_SCx200_GPIO $CONFIG_SCx200
4174 +
4175 +if [ "$CONFIG_IA64_GENERIC" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
4176 + bool 'SGI SN2 fetchop support' CONFIG_FETCHOP
4177 +fi
4178 +
4179 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_X86_64" = "y" ]; then
4180 + dep_tristate 'AMD 768/8111 Random Number Generator support' CONFIG_AMD_RNG $CONFIG_PCI
4181 +fi
4182 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
4183 + dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
4184 +fi
4185 +if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" -o \
4186 + "$CONFIG_X86_64" = "y" ]; then
4187 + dep_tristate 'Intel/AMD/VIA HW Random Number Generator support' CONFIG_HW_RANDOM $CONFIG_PCI
4188 +fi
4189 +dep_tristate 'AMD 76x native power management (Experimental)' CONFIG_AMD_PM768 $CONFIG_PCI
4190 +tristate '/dev/nvram support' CONFIG_NVRAM
4191 +tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
4192 +if [ "$CONFIG_IA64" = "y" ]; then
4193 + bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
4194 +fi
4195 +if [ "$CONFIG_OBSOLETE" = "y" -a "$CONFIG_ALPHA_BOOK1" = "y" ]; then
4196 + bool 'Tadpole ANA H8 Support (OBSOLETE)' CONFIG_H8
4197 +fi
4198 +if [ "$CONFIG_SGI_IP22" = "y" ]; then
4199 + tristate 'Dallas DS1286 RTC support' CONFIG_DS1286
4200 +fi
4201 +if [ "$CONFIG_SGI_IP27" = "y" ]; then
4202 + tristate 'SGI M48T35 RTC support' CONFIG_SGI_IP27_RTC
4203 +fi
4204 +if [ "$CONFIG_TOSHIBA_RBTX4927" = "y" -o "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
4205 + tristate 'Dallas DS1742 RTC support' CONFIG_DS1742
4206 +fi
4207 +
4208 +tristate 'Double Talk PC internal speech card support' CONFIG_DTLK
4209 +tristate 'Siemens R3964 line discipline' CONFIG_R3964
4210 +tristate 'Applicom intelligent fieldbus card support' CONFIG_APPLICOM
4211 +if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_X86" = "y" -a "$CONFIG_X86_64" != "y" ]; then
4212 + dep_tristate 'Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)' CONFIG_SONYPI $CONFIG_PCI
4213 +fi
4214 +
4215 +mainmenu_option next_comment
4216 +comment 'Ftape, the floppy tape device driver'
4217 +tristate 'Ftape (QIC-80/Travan) support' CONFIG_FTAPE
4218 +if [ "$CONFIG_FTAPE" != "n" ]; then
4219 + source drivers/char/ftape/Config.in
4220 +fi
4221 +
4222 +endmenu
4223 +
4224 +if [ "$CONFIG_GART_IOMMU" = "y" ]; then
4225 + bool '/dev/agpgart (AGP Support)' CONFIG_AGP
4226 + define_bool CONFIG_AGP_AMD_K8 y
4227 +else
4228 + tristate '/dev/agpgart (AGP Support)' CONFIG_AGP
4229 +fi
4230 +if [ "$CONFIG_AGP" != "n" ]; then
4231 + bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
4232 + bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
4233 + bool ' VIA chipset support' CONFIG_AGP_VIA
4234 + bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
4235 + if [ "$CONFIG_GART_IOMMU" != "y" ]; then
4236 + bool ' AMD Opteron/Athlon64 on-CPU GART support' CONFIG_AGP_AMD_K8
4237 + fi
4238 + bool ' Generic SiS support' CONFIG_AGP_SIS
4239 + bool ' ALI chipset support' CONFIG_AGP_ALI
4240 + bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
4241 + if [ "$CONFIG_X86" = "y" ]; then
4242 + bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
4243 + fi
4244 + if [ "$CONFIG_IA64" = "y" ]; then
4245 + bool ' Intel 460GX support' CONFIG_AGP_I460
4246 + bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
4247 + fi
4248 + bool ' ATI IGP chipset support' CONFIG_AGP_ATI
4249 +fi
4250 +
4251 +mainmenu_option next_comment
4252 +comment 'Direct Rendering Manager (XFree86 DRI support)'
4253 +bool 'Direct Rendering Manager (XFree86 DRI support)' CONFIG_DRM
4254 +if [ "$CONFIG_DRM" = "y" ]; then
4255 + bool ' Build drivers for old (XFree 4.0) DRM' CONFIG_DRM_OLD
4256 + if [ "$CONFIG_DRM_OLD" = "y" ]; then
4257 + comment 'DRM 4.0 drivers'
4258 + source drivers/char/drm-4.0/Config.in
4259 + else
4260 + comment 'DRM 4.1 drivers'
4261 + define_bool CONFIG_DRM_NEW y
4262 + source drivers/char/drm/Config.in
4263 + fi
4264 +fi
4265 +
4266 +if [ "$CONFIG_X86" = "y" ]; then
4267 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
4268 +fi
4269 +
4270 +endmenu
4271 +
4272 +if [ "$CONFIG_HOTPLUG" = "y" -a "$CONFIG_PCMCIA" != "n" ]; then
4273 + source drivers/char/pcmcia/Config.in
4274 +fi
4275 +if [ "$CONFIG_SOC_AU1X00" = "y" ]; then
4276 + tristate ' Alchemy Au1x00 GPIO device support' CONFIG_AU1X00_GPIO
4277 + tristate ' Au1000/ADS7846 touchscreen support' CONFIG_TS_AU1X00_ADS7846
4278 + #tristate ' Alchemy Au1550 PSC SPI support' CONFIG_AU1550_PSC_SPI
4279 +fi
4280 +if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
4281 + tristate ' ITE GPIO' CONFIG_ITE_GPIO
4282 +fi
4283 +
4284 +if [ "$CONFIG_X86" = "y" ]; then
4285 + tristate 'ACP Modem (Mwave) support' CONFIG_MWAVE
4286 + dep_tristate 'HP OB600 C/CT Pop-up mouse support' CONFIG_OBMOUSE $CONFIG_INPUT_MOUSEDEV
4287 +fi
4288 +
4289 +endmenu
4290 diff -urN linux.old/drivers/char/Makefile linux.dev/drivers/char/Makefile
4291 --- linux.old/drivers/char/Makefile 2005-10-21 16:43:16.460960500 +0200
4292 +++ linux.dev/drivers/char/Makefile 2005-10-21 17:02:20.199991500 +0200
4293 @@ -240,6 +240,13 @@
4294 obj-y += joystick/js.o
4295 endif
4296
4297 +#
4298 +# Texas Intruments VLYNQ driver
4299 +#
4300 +
4301 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
4302 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
4303 +
4304 obj-$(CONFIG_FETCHOP) += fetchop.o
4305 obj-$(CONFIG_BUSMOUSE) += busmouse.o
4306 obj-$(CONFIG_DTLK) += dtlk.o
4307 @@ -340,6 +347,11 @@
4308 obj-y += ipmi/ipmi.o
4309 endif
4310
4311 +subdir-$(CONFIG_AR7_ADAM2) += ticfg
4312 +ifeq ($(CONFIG_AR7_ADAM2),y)
4313 + obj-y += ticfg/ticfg.o
4314 +endif
4315 +
4316 include $(TOPDIR)/Rules.make
4317
4318 fastdep:
4319 diff -urN linux.old/drivers/char/Makefile.orig linux.dev/drivers/char/Makefile.orig
4320 --- linux.old/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100
4321 +++ linux.dev/drivers/char/Makefile.orig 2005-10-21 16:54:20.566016250 +0200
4322 @@ -0,0 +1,374 @@
4323 +#
4324 +# Makefile for the kernel character device drivers.
4325 +#
4326 +# Note! Dependencies are done automagically by 'make dep', which also
4327 +# removes any old dependencies. DON'T put your own dependencies here
4328 +# unless it's something special (ie not a .c file).
4329 +#
4330 +# Note 2! The CFLAGS definitions are now inherited from the
4331 +# parent makes..
4332 +#
4333 +
4334 +#
4335 +# This file contains the font map for the default (hardware) font
4336 +#
4337 +FONTMAPFILE = cp437.uni
4338 +
4339 +O_TARGET := char.o
4340 +
4341 +obj-y += mem.o tty_io.o n_tty.o tty_ioctl.o raw.o pty.o misc.o random.o
4342 +
4343 +# All of the (potential) objects that export symbols.
4344 +# This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
4345 +
4346 +export-objs := busmouse.o console.o keyboard.o sysrq.o \
4347 + misc.o pty.o random.o selection.o serial.o \
4348 + sonypi.o tty_io.o tty_ioctl.o generic_serial.o \
4349 + au1000_gpio.o vac-serial.o hp_psaux.o nvram.o \
4350 + scx200.o fetchop.o
4351 +
4352 +mod-subdirs := joystick ftape drm drm-4.0 pcmcia
4353 +
4354 +list-multi :=
4355 +
4356 +KEYMAP =defkeymap.o
4357 +KEYBD =pc_keyb.o
4358 +CONSOLE =console.o
4359 +SERIAL =serial.o
4360 +
4361 +ifeq ($(ARCH),s390)
4362 + KEYMAP =
4363 + KEYBD =
4364 + CONSOLE =
4365 + SERIAL =
4366 +endif
4367 +
4368 +ifeq ($(ARCH),mips)
4369 + ifneq ($(CONFIG_PC_KEYB),y)
4370 + KEYBD =
4371 + endif
4372 + ifeq ($(CONFIG_VR41XX_KIU),y)
4373 + ifeq ($(CONFIG_IBM_WORKPAD),y)
4374 + KEYMAP = ibm_workpad_keymap.o
4375 + endif
4376 + ifeq ($(CONFIG_VICTOR_MPC30X),y)
4377 + KEYMAP = victor_mpc30x_keymap.o
4378 + endif
4379 + KEYBD = vr41xx_keyb.o
4380 + endif
4381 +endif
4382 +
4383 +ifeq ($(ARCH),s390x)
4384 + KEYMAP =
4385 + KEYBD =
4386 + CONSOLE =
4387 + SERIAL =
4388 +endif
4389 +
4390 +ifeq ($(ARCH),m68k)
4391 + ifdef CONFIG_AMIGA
4392 + KEYBD = amikeyb.o
4393 + else
4394 + ifndef CONFIG_MAC
4395 + KEYBD =
4396 + endif
4397 + endif
4398 + SERIAL =
4399 +endif
4400 +
4401 +ifeq ($(ARCH),parisc)
4402 + ifdef CONFIG_GSC_PS2
4403 + KEYBD = hp_psaux.o hp_keyb.o
4404 + else
4405 + KEYBD =
4406 + endif
4407 + ifdef CONFIG_SERIAL_MUX
4408 + CONSOLE += mux.o
4409 + endif
4410 + ifdef CONFIG_PDC_CONSOLE
4411 + CONSOLE += pdc_console.o
4412 + endif
4413 +endif
4414 +
4415 +ifdef CONFIG_Q40
4416 + KEYBD += q40_keyb.o
4417 + SERIAL = serial.o
4418 +endif
4419 +
4420 +ifdef CONFIG_APOLLO
4421 + KEYBD += dn_keyb.o
4422 +endif
4423 +
4424 +ifeq ($(ARCH),parisc)
4425 + ifdef CONFIG_GSC_PS2
4426 + KEYBD = hp_psaux.o hp_keyb.o
4427 + else
4428 + KEYBD =
4429 + endif
4430 + ifdef CONFIG_PDC_CONSOLE
4431 + CONSOLE += pdc_console.o
4432 + endif
4433 +endif
4434 +
4435 +ifeq ($(ARCH),arm)
4436 + ifneq ($(CONFIG_PC_KEYMAP),y)
4437 + KEYMAP =
4438 + endif
4439 + ifneq ($(CONFIG_PC_KEYB),y)
4440 + KEYBD =
4441 + endif
4442 +endif
4443 +
4444 +ifeq ($(ARCH),sh)
4445 + KEYMAP =
4446 + KEYBD =
4447 + CONSOLE =
4448 + ifeq ($(CONFIG_SH_HP600),y)
4449 + KEYMAP = defkeymap.o
4450 + KEYBD = scan_keyb.o hp600_keyb.o
4451 + CONSOLE = console.o
4452 + endif
4453 + ifeq ($(CONFIG_SH_DMIDA),y)
4454 + # DMIDA does not connect the HD64465 PS/2 keyboard port
4455 + # but we allow for USB keyboards to be plugged in.
4456 + KEYMAP = defkeymap.o
4457 + KEYBD = # hd64465_keyb.o pc_keyb.o
4458 + CONSOLE = console.o
4459 + endif
4460 + ifeq ($(CONFIG_SH_EC3104),y)
4461 + KEYMAP = defkeymap.o
4462 + KEYBD = ec3104_keyb.o
4463 + CONSOLE = console.o
4464 + endif
4465 + ifeq ($(CONFIG_SH_DREAMCAST),y)
4466 + KEYMAP = defkeymap.o
4467 + KEYBD =
4468 + CONSOLE = console.o
4469 + endif
4470 +endif
4471 +
4472 +ifeq ($(CONFIG_DECSTATION),y)
4473 + KEYMAP =
4474 + KEYBD =
4475 +endif
4476 +
4477 +ifeq ($(CONFIG_BAGET_MIPS),y)
4478 + KEYBD =
4479 + SERIAL = vac-serial.o
4480 +endif
4481 +
4482 +ifeq ($(CONFIG_NINO),y)
4483 + SERIAL =
4484 +endif
4485 +
4486 +ifneq ($(CONFIG_SUN_SERIAL),)
4487 + SERIAL =
4488 +endif
4489 +
4490 +ifeq ($(CONFIG_QTRONIX_KEYBOARD),y)
4491 + KEYBD = qtronix.o
4492 + KEYMAP = qtronixmap.o
4493 +endif
4494 +
4495 +ifeq ($(CONFIG_DUMMY_KEYB),y)
4496 + KEYBD = dummy_keyb.o
4497 +endif
4498 +
4499 +obj-$(CONFIG_VT) += vt.o vc_screen.o consolemap.o consolemap_deftbl.o $(CONSOLE) selection.o
4500 +obj-$(CONFIG_SERIAL) += $(SERIAL)
4501 +obj-$(CONFIG_PARPORT_SERIAL) += parport_serial.o
4502 +obj-$(CONFIG_SERIAL_HCDP) += hcdp_serial.o
4503 +obj-$(CONFIG_SERIAL_21285) += serial_21285.o
4504 +obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
4505 +obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
4506 +obj-$(CONFIG_TS_AU1X00_ADS7846) += au1000_ts.o
4507 +obj-$(CONFIG_SERIAL_DEC) += decserial.o
4508 +
4509 +ifndef CONFIG_SUN_KEYBOARD
4510 + obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)
4511 +else
4512 + obj-$(CONFIG_PCI) += keyboard.o $(KEYMAP)
4513 +endif
4514 +
4515 +obj-$(CONFIG_HIL) += hp_keyb.o
4516 +obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
4517 +obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
4518 +obj-$(CONFIG_ROCKETPORT) += rocket.o
4519 +obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
4520 +obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
4521 +obj-$(CONFIG_DIGI) += pcxx.o
4522 +obj-$(CONFIG_DIGIEPCA) += epca.o
4523 +obj-$(CONFIG_CYCLADES) += cyclades.o
4524 +obj-$(CONFIG_STALLION) += stallion.o
4525 +obj-$(CONFIG_ISTALLION) += istallion.o
4526 +obj-$(CONFIG_SIBYTE_SB1250_DUART) += sb1250_duart.o
4527 +obj-$(CONFIG_COMPUTONE) += ip2.o ip2main.o
4528 +obj-$(CONFIG_RISCOM8) += riscom8.o
4529 +obj-$(CONFIG_ISI) += isicom.o
4530 +obj-$(CONFIG_ESPSERIAL) += esp.o
4531 +obj-$(CONFIG_SYNCLINK) += synclink.o
4532 +obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o
4533 +obj-$(CONFIG_N_HDLC) += n_hdlc.o
4534 +obj-$(CONFIG_SPECIALIX) += specialix.o
4535 +obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o
4536 +obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
4537 +obj-$(CONFIG_SX) += sx.o generic_serial.o
4538 +obj-$(CONFIG_RIO) += rio/rio.o generic_serial.o
4539 +obj-$(CONFIG_SH_SCI) += sh-sci.o generic_serial.o
4540 +obj-$(CONFIG_SERIAL167) += serial167.o
4541 +obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o
4542 +obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o
4543 +obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o
4544 +obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o
4545 +obj-$(CONFIG_SERIAL_TX3912) += generic_serial.o serial_tx3912.o
4546 +obj-$(CONFIG_TXX927_SERIAL) += serial_txx927.o
4547 +obj-$(CONFIG_SERIAL_TXX9) += generic_serial.o serial_txx9.o
4548 +obj-$(CONFIG_IP22_SERIAL) += sgiserial.o
4549 +obj-$(CONFIG_AU1X00_UART) += au1x00-serial.o
4550 +obj-$(CONFIG_SGI_L1_SERIAL) += sn_serial.o
4551 +
4552 +subdir-$(CONFIG_RIO) += rio
4553 +subdir-$(CONFIG_INPUT) += joystick
4554 +
4555 +obj-$(CONFIG_ATIXL_BUSMOUSE) += atixlmouse.o
4556 +obj-$(CONFIG_LOGIBUSMOUSE) += logibusmouse.o
4557 +obj-$(CONFIG_PRINTER) += lp.o
4558 +obj-$(CONFIG_TIPAR) += tipar.o
4559 +obj-$(CONFIG_OBMOUSE) += obmouse.o
4560 +
4561 +ifeq ($(CONFIG_INPUT),y)
4562 +obj-y += joystick/js.o
4563 +endif
4564 +
4565 +#
4566 +# Texas Intruments VLYNQ driver
4567 +#
4568 +
4569 +subdir-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq
4570 +obj-$(CONFIG_AR7_VLYNQ) += avalanche_vlynq/avalanche_vlynq.o
4571 +
4572 +obj-$(CONFIG_FETCHOP) += fetchop.o
4573 +obj-$(CONFIG_BUSMOUSE) += busmouse.o
4574 +obj-$(CONFIG_DTLK) += dtlk.o
4575 +obj-$(CONFIG_R3964) += n_r3964.o
4576 +obj-$(CONFIG_APPLICOM) += applicom.o
4577 +obj-$(CONFIG_SONYPI) += sonypi.o
4578 +obj-$(CONFIG_MS_BUSMOUSE) += msbusmouse.o
4579 +obj-$(CONFIG_82C710_MOUSE) += qpmouse.o
4580 +obj-$(CONFIG_AMIGAMOUSE) += amigamouse.o
4581 +obj-$(CONFIG_ATARIMOUSE) += atarimouse.o
4582 +obj-$(CONFIG_ADBMOUSE) += adbmouse.o
4583 +obj-$(CONFIG_PC110_PAD) += pc110pad.o
4584 +obj-$(CONFIG_MK712_MOUSE) += mk712.o
4585 +obj-$(CONFIG_RTC) += rtc.o
4586 +obj-$(CONFIG_GEN_RTC) += genrtc.o
4587 +obj-$(CONFIG_EFI_RTC) += efirtc.o
4588 +obj-$(CONFIG_MIPS_RTC) += mips_rtc.o
4589 +obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
4590 +ifeq ($(CONFIG_PPC),)
4591 + obj-$(CONFIG_NVRAM) += nvram.o
4592 +endif
4593 +obj-$(CONFIG_TOSHIBA) += toshiba.o
4594 +obj-$(CONFIG_I8K) += i8k.o
4595 +obj-$(CONFIG_DS1286) += ds1286.o
4596 +obj-$(CONFIG_DS1620) += ds1620.o
4597 +obj-$(CONFIG_DS1742) += ds1742.o
4598 +obj-$(CONFIG_INTEL_RNG) += i810_rng.o
4599 +obj-$(CONFIG_AMD_RNG) += amd768_rng.o
4600 +obj-$(CONFIG_HW_RANDOM) += hw_random.o
4601 +obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
4602 +obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o
4603 +
4604 +obj-$(CONFIG_ITE_GPIO) += ite_gpio.o
4605 +obj-$(CONFIG_AU1X00_GPIO) += au1000_gpio.o
4606 +obj-$(CONFIG_AU1550_PSC_SPI) += au1550_psc_spi.o
4607 +obj-$(CONFIG_AU1X00_USB_TTY) += au1000_usbtty.o
4608 +obj-$(CONFIG_AU1X00_USB_RAW) += au1000_usbraw.o
4609 +obj-$(CONFIG_COBALT_LCD) += lcd.o
4610 +
4611 +obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
4612 +
4613 +subdir-$(CONFIG_FTAPE) += ftape
4614 +subdir-$(CONFIG_DRM_OLD) += drm-4.0
4615 +subdir-$(CONFIG_DRM_NEW) += drm
4616 +subdir-$(CONFIG_PCMCIA) += pcmcia
4617 +subdir-$(CONFIG_AGP) += agp
4618 +
4619 +ifeq ($(CONFIG_FTAPE),y)
4620 +obj-y += ftape/ftape.o
4621 +endif
4622 +
4623 +obj-$(CONFIG_H8) += h8.o
4624 +obj-$(CONFIG_PPDEV) += ppdev.o
4625 +obj-$(CONFIG_DZ) += dz.o
4626 +obj-$(CONFIG_NWBUTTON) += nwbutton.o
4627 +obj-$(CONFIG_NWFLASH) += nwflash.o
4628 +obj-$(CONFIG_SCx200) += scx200.o
4629 +obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
4630 +
4631 +# Only one watchdog can succeed. We probe the hardware watchdog
4632 +# drivers first, then the softdog driver. This means if your hardware
4633 +# watchdog dies or is 'borrowed' for some reason the software watchdog
4634 +# still gives you some cover.
4635 +
4636 +obj-$(CONFIG_PCWATCHDOG) += pcwd.o
4637 +obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
4638 +obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o
4639 +obj-$(CONFIG_IB700_WDT) += ib700wdt.o
4640 +obj-$(CONFIG_MIXCOMWD) += mixcomwd.o
4641 +obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o
4642 +obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o
4643 +obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
4644 +obj-$(CONFIG_WDT) += wdt.o
4645 +obj-$(CONFIG_WDTPCI) += wdt_pci.o
4646 +obj-$(CONFIG_21285_WATCHDOG) += wdt285.o
4647 +obj-$(CONFIG_977_WATCHDOG) += wdt977.o
4648 +obj-$(CONFIG_I810_TCO) += i810-tco.o
4649 +obj-$(CONFIG_MACHZ_WDT) += machzwd.o
4650 +obj-$(CONFIG_SH_WDT) += shwdt.o
4651 +obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o
4652 +obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
4653 +obj-$(CONFIG_ALIM1535_WDT) += alim1535d_wdt.o
4654 +obj-$(CONFIG_INDYDOG) += indydog.o
4655 +obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
4656 +obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
4657 +obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
4658 +obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o
4659 +obj-$(CONFIG_INDYDOG) += indydog.o
4660 +obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
4661 +
4662 +subdir-$(CONFIG_MWAVE) += mwave
4663 +ifeq ($(CONFIG_MWAVE),y)
4664 + obj-y += mwave/mwave.o
4665 +endif
4666 +
4667 +subdir-$(CONFIG_IPMI_HANDLER) += ipmi
4668 +ifeq ($(CONFIG_IPMI_HANDLER),y)
4669 + obj-y += ipmi/ipmi.o
4670 +endif
4671 +
4672 +include $(TOPDIR)/Rules.make
4673 +
4674 +fastdep:
4675 +
4676 +conmakehash: conmakehash.c
4677 + $(HOSTCC) $(HOSTCFLAGS) -o conmakehash conmakehash.c
4678 +
4679 +consolemap_deftbl.c: $(FONTMAPFILE) conmakehash
4680 + ./conmakehash $(FONTMAPFILE) > consolemap_deftbl.c
4681 +
4682 +consolemap_deftbl.o: consolemap_deftbl.c $(TOPDIR)/include/linux/types.h
4683 +
4684 +.DELETE_ON_ERROR:
4685 +
4686 +defkeymap.c: defkeymap.map
4687 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4688 +
4689 +qtronixmap.c: qtronixmap.map
4690 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4691 +
4692 +ibm_workpad_keymap.c: ibm_workpad_keymap.map
4693 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4694 +
4695 +victor_mpc30x_keymap.c: victor_mpc30x_keymap.map
4696 + set -e ; loadkeys --mktable $< | sed -e 's/^static *//' > $@
4697 diff -urN linux.old/drivers/char/avalanche_vlynq/Makefile linux.dev/drivers/char/avalanche_vlynq/Makefile
4698 --- linux.old/drivers/char/avalanche_vlynq/Makefile 1970-01-01 01:00:00.000000000 +0100
4699 +++ linux.dev/drivers/char/avalanche_vlynq/Makefile 2005-10-21 17:02:20.195991250 +0200
4700 @@ -0,0 +1,16 @@
4701 +#
4702 +# Makefile for the linux kernel.
4703 +#
4704 +# Note! Dependencies are done automagically by 'make dep', which also
4705 +# removes any old dependencies. DON'T put your own dependencies here
4706 +# unless it's something special (ie not a .c file).
4707 +#
4708 +# Note 2! The CFLAGS definitions are now in the main makefile...
4709 +
4710 +O_TARGET := avalanche_vlynq.o
4711 +
4712 +export-objs := vlynq_board.o
4713 +
4714 +obj-y += vlynq_drv.o vlynq_hal.o vlynq_board.o
4715 +
4716 +include $(TOPDIR)/Rules.make
4717 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_board.c linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c
4718 --- linux.old/drivers/char/avalanche_vlynq/vlynq_board.c 1970-01-01 01:00:00.000000000 +0100
4719 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_board.c 2005-10-21 17:02:20.195991250 +0200
4720 @@ -0,0 +1,184 @@
4721 +/*
4722 + * Jeff Harrell, jharrell@ti.com
4723 + * Copyright (C) 2001 Texas Instruments, Inc. All rights reserved.
4724 + *
4725 + * This program is free software; you can distribute it and/or modify it
4726 + * under the terms of the GNU General Public License (Version 2) as
4727 + * published by the Free Software Foundation.
4728 + *
4729 + * This program is distributed in the hope it will be useful, but WITHOUT
4730 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4731 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4732 + * for more details.
4733 + *
4734 + * You should have received a copy of the GNU General Public License along
4735 + * with this program; if not, write to the Free Software Foundation, Inc.,
4736 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4737 + *
4738 + * Texas Instruments Sangam specific setup.
4739 + */
4740 +#include <linux/config.h>
4741 +#include <linux/module.h>
4742 +#include <asm/ar7/sangam.h>
4743 +#include <asm/ar7/avalanche_misc.h>
4744 +#include <asm/ar7/vlynq.h>
4745 +
4746 +#define SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR 30 /* MSB - 1 bit */
4747 +#define SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR 31 /* MSB bit */
4748 +#define SYS_VLYNQ_OPTIONS 0x7F; /* all options*/
4749 +
4750 +/* These defines are board specific */
4751 +
4752 +
4753 +#define VLYNQ0_REMOTE_WINDOW1_OFFSET (0x0C000000)
4754 +#define VLYNQ0_REMOTE_WINDOW1_SIZE (0x500)
4755 +
4756 +
4757 +#define VLYNQ1_REMOTE_WINDOW1_OFFSET (0x0C000000)
4758 +#define VLYNQ1_REMOTE_WINDOW1_SIZE (0x500)
4759 +
4760 +
4761 +extern VLYNQ_DEV vlynqDevice0, vlynqDevice1;
4762 +int vlynq_init_status[2] = {0, 0};
4763 +EXPORT_SYMBOL(vlynq_init_status);
4764 +static int reset_hack = 1;
4765 +
4766 +void vlynq_ar7wrd_dev_init()
4767 +{
4768 + *(unsigned long*) AVALANCHE_GPIO_ENBL |= (1<<18);
4769 + vlynq_delay(20000);
4770 + *(unsigned long*) AVALANCHE_GPIO_DIR &= ~(1<<18);
4771 + vlynq_delay(20000);
4772 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT&= ~(1<<18);
4773 + vlynq_delay(50000);
4774 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT|= (1<<18);
4775 + vlynq_delay(50000);
4776 +
4777 + /* Initialize the MIPS host vlynq driver for a given vlynq interface */
4778 + vlynqDevice0.dev_idx = 0; /* first vlynq module - this parameter is for reference only */
4779 + vlynqDevice0.module_base = AVALANCHE_LOW_VLYNQ_CONTROL_BASE; /* vlynq0 module base address */
4780 +
4781 +#if defined(CONFIG_VLYNQ_CLK_LOCAL)
4782 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_LOCAL;
4783 +#else
4784 + vlynqDevice0.clk_source = VLYNQ_CLK_SOURCE_REMOTE;
4785 +#endif
4786 + vlynqDevice0.clk_div = 0x01; /* board/hardware specific */
4787 + vlynqDevice0.state = VLYNQ_DRV_STATE_UNINIT; /* uninitialized module */
4788 +
4789 + /* Populate vlynqDevice0.local_mem & Vlynq0.remote_mem based on system configuration */
4790 + /*Local memory configuration */
4791 +
4792 + /* Demiurg : not good !*/
4793 +#if 0
4794 + vlynqDevice0.local_mem.Txmap= AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE & ~(0xc0000000) ; /* physical address */
4795 + vlynqDevice0.remote_mem.RxOffset[0]= VLYNQ0_REMOTE_WINDOW1_OFFSET; /* This is specific to the board on the other end */
4796 + vlynqDevice0.remote_mem.RxSize[0]=VLYNQ0_REMOTE_WINDOW1_SIZE;
4797 +#endif
4798 +
4799 + /* Demiurg : This is how it should be ! */
4800 + vlynqDevice0.local_mem.Txmap = PHYSADDR(AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE);
4801 +#define VLYNQ_ACX111_MEM_OFFSET 0xC0000000 /* Physical address of ACX111 memory */
4802 +#define VLYNQ_ACX111_MEM_SIZE 0x00040000 /* Total size of the ACX111 memory */
4803 +#define VLYNQ_ACX111_REG_OFFSET 0xF0000000 /* PHYS_ADDR of ACX111 control registers */
4804 +#define VLYNQ_ACX111_REG_SIZE 0x00022000 /* Size of ACX111 registers area, MAC+PHY */
4805 +#define ACX111_VL1_REMOTE_SIZE 0x1000000
4806 + vlynqDevice0.remote_mem.RxOffset[0] = VLYNQ_ACX111_MEM_OFFSET;
4807 + vlynqDevice0.remote_mem.RxSize[0] = VLYNQ_ACX111_MEM_SIZE ;
4808 + vlynqDevice0.remote_mem.RxOffset[1] = VLYNQ_ACX111_REG_OFFSET;
4809 + vlynqDevice0.remote_mem.RxSize[1] = VLYNQ_ACX111_REG_SIZE ;
4810 + vlynqDevice0.remote_mem.Txmap = 0;
4811 + vlynqDevice0.local_mem.RxOffset[0] = AVALANCHE_SDRAM_BASE;
4812 + vlynqDevice0.local_mem.RxSize[0] = ACX111_VL1_REMOTE_SIZE;
4813 +
4814 +
4815 + /* Local interrupt configuration */
4816 + vlynqDevice0.local_irq.intLocal = VLYNQ_INT_LOCAL; /* Host handles vlynq interrupts*/
4817 + vlynqDevice0.local_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* vlynq root isr used */
4818 + vlynqDevice0.local_irq.map_vector = SYS_VLYNQ_LOCAL_INTERRUPT_VECTOR;
4819 + vlynqDevice0.local_irq.intr_ptr = 0; /* Since remote interrupts part of vlynq root isr this is unused */
4820 +
4821 + /* Remote interrupt configuration */
4822 + vlynqDevice0.remote_irq.intLocal = VLYNQ_INT_REMOTE; /* MIPS handles interrupts */
4823 + vlynqDevice0.remote_irq.intRemote = VLYNQ_INT_ROOT_ISR; /* Not significant since MIPS handles interrupts */
4824 + vlynqDevice0.remote_irq.map_vector = SYS_VLYNQ_REMOTE_INTERRUPT_VECTOR;
4825 + vlynqDevice0. remote_irq.intr_ptr = AVALANCHE_INTC_BASE; /* Not significant since MIPS handles interrupts */
4826 +
4827 + if(reset_hack != 1)
4828 + printk("About to re-init the VLYNQ.\n");
4829 +
4830 + if(vlynq_init(&vlynqDevice0,VLYNQ_INIT_PERFORM_ALL)== 0)
4831 + {
4832 + /* Suraj added the following to keep the 1130 going. */
4833 + vlynq_interrupt_vector_set(&vlynqDevice0, 0 /* intr vector line running into 1130 vlynq */,
4834 + 0 /* intr mapped onto the interrupt register on remote vlynq and this vlynq */,
4835 + VLYNQ_REMOTE_DVC, 0 /* polarity active high */, 0 /* interrupt Level triggered */);
4836 +
4837 + /* System wide interrupt is 80 for 1130, please note. */
4838 + vlynq_init_status[0] = 1;
4839 + reset_hack = 2;
4840 + }
4841 + else
4842 + {
4843 + if(reset_hack == 1)
4844 + printk("VLYNQ INIT FAILED: Please try cold reboot. \n");
4845 + else
4846 + printk("Failed to initialize the VLYNQ interface at insmod.\n");
4847 +
4848 + }
4849 +}
4850 +
4851 +void vlynq_dev_init(void)
4852 +{
4853 + volatile unsigned int *reset_base = (unsigned int *) AVALANCHE_RESET_CONTROL_BASE;
4854 +
4855 + *reset_base &= ~((1 << AVALANCHE_LOW_VLYNQ_RESET_BIT)); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT)); */
4856 +
4857 + vlynq_delay(20000);
4858 +
4859 + /* Bring vlynq out of reset if not already done */
4860 + *reset_base |= (1 << AVALANCHE_LOW_VLYNQ_RESET_BIT); /* | (1 << AVALANCHE_HIGH_VLYNQ_RESET_BIT); */
4861 + vlynq_delay(20000); /* Allowing sufficient time to VLYNQ to settle down.*/
4862 +
4863 + vlynq_ar7wrd_dev_init( );
4864 +
4865 +}
4866 +
4867 +/* This function is board specific and should be ported for each board. */
4868 +void remote_vlynq_dev_reset_ctrl(unsigned int module_reset_bit,
4869 + AVALANCHE_RESET_CTRL_T reset_ctrl)
4870 +{
4871 + if(module_reset_bit >= 32)
4872 + return;
4873 +
4874 + switch(module_reset_bit)
4875 + {
4876 + case 0:
4877 + if(OUT_OF_RESET == reset_ctrl)
4878 + {
4879 + if(reset_hack) return;
4880 +
4881 + vlynq_delay(20000);
4882 + printk("Un-resetting the remote device.\n");
4883 + vlynq_dev_init();
4884 + printk("Re-initialized the VLYNQ.\n");
4885 + reset_hack = 2;
4886 + }
4887 + else if(IN_RESET == reset_ctrl)
4888 + {
4889 + *(unsigned long*) AVALANCHE_GPIO_DATA_OUT &= ~(1<<18);
4890 +
4891 + vlynq_delay(20000);
4892 + printk("Resetting the remote device.\n");
4893 + reset_hack = 0;
4894 + }
4895 + else
4896 + ;
4897 + break;
4898 +
4899 + default:
4900 + break;
4901 +
4902 + }
4903 +}
4904 +
4905 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c
4906 --- linux.old/drivers/char/avalanche_vlynq/vlynq_drv.c 1970-01-01 01:00:00.000000000 +0100
4907 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_drv.c 2005-10-21 17:02:20.199991500 +0200
4908 @@ -0,0 +1,243 @@
4909 +/******************************************************************************
4910 + * FILE PURPOSE: Vlynq Linux Device Driver Source
4911 + ******************************************************************************
4912 + * FILE NAME: vlynq_drv.c
4913 + *
4914 + * DESCRIPTION: Vlynq Linux Device Driver Source
4915 + *
4916 + * REVISION HISTORY:
4917 + *
4918 + * Date Description Author
4919 + *-----------------------------------------------------------------------------
4920 + * 17 July 2003 Initial Creation Anant Gole
4921 + * 17 Dec 2003 Updates Sharath Kumar
4922 + *
4923 + * (C) Copyright 2003, Texas Instruments, Inc
4924 + *******************************************************************************/
4925 +
4926 +#include <linux/config.h>
4927 +#include <linux/init.h>
4928 +#include <linux/module.h>
4929 +#include <linux/sched.h>
4930 +#include <linux/miscdevice.h>
4931 +#include <linux/smp_lock.h>
4932 +#include <linux/delay.h>
4933 +#include <linux/proc_fs.h>
4934 +#include <linux/capability.h>
4935 +#include <asm/ar7/avalanche_intc.h>
4936 +#include <asm/ar7/sangam.h>
4937 +#include <asm/ar7/vlynq.h>
4938 +
4939 +
4940 +#define TI_VLYNQ_VERSION "0.2"
4941 +
4942 +/* debug on ? */
4943 +#define VLYNQ_DEBUG
4944 +
4945 +/* Macro for debug and error printf's */
4946 +#ifdef VLYNQ_DEBUG
4947 +#define DBGPRINT printk
4948 +#else
4949 +#define DBGPRINT(x)
4950 +#endif
4951 +
4952 +#define ERRPRINT printk
4953 +
4954 +/* Define the max vlynq ports this driver will support.
4955 + Device name strings are statically added here */
4956 +#define MAX_VLYNQ_PORTS 2
4957 +
4958 +
4959 +/* Type define for VLYNQ private structure */
4960 +typedef struct vlynqPriv{
4961 + int irq;
4962 + VLYNQ_DEV *vlynqDevice;
4963 +}VLYNQ_PRIV;
4964 +
4965 +extern int vlynq_init_status[2];
4966 +
4967 +/* Extern Global variable for vlynq devices used in initialization of the vlynq device
4968 + * These variables need to be populated/initialized by the system as part of initialization
4969 + * process. The vlynq enumerator can run at initialization and populate these globals
4970 + */
4971 +
4972 +VLYNQ_DEV vlynqDevice0;
4973 +VLYNQ_DEV vlynqDevice1;
4974 +
4975 +/* Defining dummy macro AVALANCHE_HIGH_VLYNQ_INT to take
4976 + * care of compilation in case of single vlynq device
4977 + */
4978 +
4979 +#ifndef AVALANCHE_HIGH_VLYNQ_INT
4980 +#define AVALANCHE_HIGH_VLYNQ_INT 0
4981 +#endif
4982 +
4983 +
4984 +
4985 +/* vlynq private object */
4986 +VLYNQ_PRIV vlynq_priv[CONFIG_AR7_VLYNQ_PORTS] = {
4987 + { LNXINTNUM(AVALANCHE_LOW_VLYNQ_INT),&vlynqDevice0},
4988 + { LNXINTNUM(AVALANCHE_HIGH_VLYNQ_INT),&vlynqDevice1},
4989 +};
4990 +
4991 +extern void vlynq_dev_init(void);
4992 +
4993 +
4994 +/* =================================== all the operations */
4995 +
4996 +static int
4997 +vlynq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4998 +{
4999 + return 0;
5000 +}
5001 +
5002 +static struct file_operations vlynq_fops = {
5003 + owner: THIS_MODULE,
5004 + ioctl: vlynq_ioctl,
5005 +};
5006 +
5007 +/* Vlynq device object */
5008 +static struct miscdevice vlynq_dev [MAX_VLYNQ_PORTS] = {
5009 + { MISC_DYNAMIC_MINOR , "vlynq0", &vlynq_fops },
5010 + { MISC_DYNAMIC_MINOR , "vlynq1", &vlynq_fops },
5011 +};
5012 +
5013 +
5014 +/* Proc read function */
5015 +static int
5016 +vlynq_read_link_proc(char *buf, char **start, off_t offset, int count, int *eof, void *unused)
5017 +{
5018 + int instance;
5019 + int len = 0;
5020 +
5021 + len += sprintf(buf +len,"VLYNQ Devices : %d\n",CONFIG_AR7_VLYNQ_PORTS);
5022 +
5023 + for(instance =0;instance < CONFIG_AR7_VLYNQ_PORTS;instance++)
5024 + {
5025 + int link_state;
5026 + char *link_msg[] = {" DOWN "," UP "};
5027 +
5028 + if(vlynq_init_status[instance] == 0)
5029 + link_state = 0;
5030 +
5031 + else if (vlynq_link_check(vlynq_priv[instance].vlynqDevice))
5032 + link_state = 1;
5033 +
5034 + else
5035 + link_state = 0;
5036 +
5037 + len += sprintf(buf + len, "VLYNQ %d: Link state: %s\n",instance,link_msg[link_state]);
5038 +
5039 + }
5040 + /* Print info about vlynq device 1 */
5041 +
5042 + return len;
5043 +}
5044 +
5045 +
5046 +/* Proc function to display driver version */
5047 +static int
5048 +vlynq_read_ver_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data)
5049 +{
5050 + int instance;
5051 + int len=0;
5052 +
5053 + len += sprintf(buf +len,"\nTI Linux VLYNQ Driver Version %s\n",TI_VLYNQ_VERSION);
5054 + return len;
5055 +}
5056 +
5057 +
5058 +
5059 +
5060 +/* Wrapper for vlynq ISR */
5061 +static void lnx_vlynq_root_isr(int irq, void * arg, struct pt_regs *regs)
5062 +{
5063 + vlynq_root_isr(arg);
5064 +}
5065 +
5066 +/* =================================== init and cleanup */
5067 +
5068 +int vlynq_init_module(void)
5069 +{
5070 + int ret;
5071 + int unit = 0;
5072 + int instance_count = CONFIG_AR7_VLYNQ_PORTS;
5073 + volatile int *ptr;
5074 +
5075 + vlynq_dev_init();
5076 +
5077 + DBGPRINT("Vlynq CONFIG_AR7_VLYNQ_PORTS=%d\n", CONFIG_AR7_VLYNQ_PORTS);
5078 + /* If num of configured vlynq ports > supported by driver return error */
5079 + if (instance_count > MAX_VLYNQ_PORTS)
5080 + {
5081 + ERRPRINT("ERROR: vlynq_init_module(): Max %d supported\n", MAX_VLYNQ_PORTS);
5082 + return (-1);
5083 + }
5084 +
5085 + /* register the misc device */
5086 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
5087 + {
5088 + ret = misc_register(&vlynq_dev[unit]);
5089 +
5090 + if(ret < 0)
5091 + {
5092 + ERRPRINT("ERROR:Could not register vlynq device:%d\n",unit);
5093 + continue;
5094 + }
5095 + else
5096 + DBGPRINT("Vlynq Device %s registered with minor no %d as misc device. Result=%d\n",
5097 + vlynq_dev[unit].name, vlynq_dev[unit].minor, ret);
5098 +#if 0
5099 +
5100 + DBGPRINT("Calling vlynq init\n");
5101 +
5102 + /* Read the global variable for VLYNQ device structure and initialize vlynq driver */
5103 + ret = vlynq_init(vlynq_priv[unit].vlynqDevice,VLYNQ_INIT_PERFORM_ALL );
5104 +#endif
5105 +
5106 + if(vlynq_init_status[unit] == 0)
5107 + {
5108 + printk("VLYNQ %d : init failed\n",unit);
5109 + continue;
5110 + }
5111 +
5112 + /* Check link before proceeding */
5113 + if (!vlynq_link_check(vlynq_priv[unit].vlynqDevice))
5114 + {
5115 + DBGPRINT("\nError: Vlynq link not available.trying once before Exiting");
5116 + }
5117 + else
5118 + {
5119 + DBGPRINT("Vlynq instance:%d Link UP\n",unit);
5120 +
5121 + /* Install the vlynq local root ISR */
5122 + request_irq(vlynq_priv[unit].irq,lnx_vlynq_root_isr,0,vlynq_dev[unit].name,vlynq_priv[unit].vlynqDevice);
5123 + }
5124 + }
5125 +
5126 + proc_mkdir("avalanche", NULL);
5127 + /* Creating proc entry for the devices */
5128 + create_proc_read_entry("avalanche/vlynq_link", 0, NULL, vlynq_read_link_proc, NULL);
5129 + create_proc_read_entry("avalanche/vlynq_ver", 0, NULL, vlynq_read_ver_proc, NULL);
5130 +
5131 + return 0;
5132 +}
5133 +
5134 +void vlynq_cleanup_module(void)
5135 +{
5136 + int unit = 0;
5137 +
5138 + for (unit = 0; unit < CONFIG_AR7_VLYNQ_PORTS; unit++)
5139 + {
5140 + DBGPRINT("vlynq_cleanup_module(): Unregistring misc device %s\n",vlynq_dev[unit].name);
5141 + misc_deregister(&vlynq_dev[unit]);
5142 + }
5143 +
5144 + remove_proc_entry("avalanche/vlynq_link", NULL);
5145 + remove_proc_entry("avalanche/vlynq_ver", NULL);
5146 +}
5147 +
5148 +
5149 +module_init(vlynq_init_module);
5150 +module_exit(vlynq_cleanup_module);
5151 +
5152 diff -urN linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c
5153 --- linux.old/drivers/char/avalanche_vlynq/vlynq_hal.c 1970-01-01 01:00:00.000000000 +0100
5154 +++ linux.dev/drivers/char/avalanche_vlynq/vlynq_hal.c 2005-10-21 16:45:47.838421000 +0200
5155 @@ -0,0 +1,1214 @@
5156 +/***************************************************************************
5157 +**+----------------------------------------------------------------------+**
5158 +**| **** |**
5159 +**| **** |**
5160 +**| ******o*** |**
5161 +**| ********_///_**** |**
5162 +**| ***** /_//_/ **** |**
5163 +**| ** ** (__/ **** |**
5164 +**| ********* |**
5165 +**| **** |**
5166 +**| *** |**
5167 +**| |**
5168 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
5169 +**| ALL RIGHTS RESERVED |**
5170 +**| |**
5171 +**| Permission is hereby granted to licensees of Texas Instruments |**
5172 +**| Incorporated (TI) products to use this computer program for the sole |**
5173 +**| purpose of implementing a licensee product based on TI products. |**
5174 +**| No other rights to reproduce, use, or disseminate this computer |**
5175 +**| program, whether in part or in whole, are granted. |**
5176 +**| |**
5177 +**| TI makes no representation or warranties with respect to the |**
5178 +**| performance of this computer program, and specifically disclaims |**
5179 +**| any responsibility for any damages, special or consequential, |**
5180 +**| connected with the use of this program. |**
5181 +**| |**
5182 +**+----------------------------------------------------------------------+**
5183 +***************************************************************************/
5184 +
5185 +/***************************************************************************
5186 + * ------------------------------------------------------------------------------
5187 + * Module : vlynq_hal.c
5188 + * Description : This file implements VLYNQ HAL API.
5189 + * ------------------------------------------------------------------------------
5190 + ***************************************************************************/
5191 +
5192 +#include <linux/stddef.h>
5193 +#include <linux/types.h>
5194 +#include <asm/ar7/vlynq.h>
5195 +
5196 +/**** Local Function prototypes *******/
5197 +static int vlynqInterruptInit(VLYNQ_DEV *pdev);
5198 +static void vlynq_configClock(VLYNQ_DEV *pdev);
5199 +
5200 +/*** Second argument must be explicitly type casted to
5201 + * (VLYNQ_DEV*) inside the following functions */
5202 +static void vlynq_local_module_isr(void *arg1, void *arg2, void *arg3);
5203 +static void vlynq_remote_module_isr(void *arg1, void *arg2, void *arg3);
5204 +
5205 +
5206 +volatile int vlynq_delay_value = 0;
5207 +
5208 +/* Code adopted from original vlynq driver */
5209 +void vlynq_delay(unsigned int clktime)
5210 +{
5211 + int i = 0;
5212 + volatile int *ptr = &vlynq_delay_value;
5213 + *ptr = 0;
5214 +
5215 + /* We are assuming that the each cycle takes about
5216 + * 23 assembly instructions. */
5217 + for(i = 0; i < (clktime + 23)/23; i++)
5218 + {
5219 + *ptr = *ptr + 1;
5220 + }
5221 +}
5222 +
5223 +
5224 +/* ----------------------------------------------------------------------------
5225 + * Function : vlynq_configClock()
5226 + * Description: Configures clock settings based on input parameters
5227 + * Adapted from original vlyna driver from Cable
5228 + */
5229 +static void vlynq_configClock(VLYNQ_DEV * pdev)
5230 +{
5231 + unsigned int tmp;
5232 +
5233 + switch( pdev->clk_source)
5234 + {
5235 + case VLYNQ_CLK_SOURCE_LOCAL: /* we output the clock, clk_div in range [1..8]. */
5236 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
5237 + VLYNQ_CTRL_REG = tmp;
5238 + VLYNQ_R_CTRL_REG = 0ul;
5239 + break;
5240 + case VLYNQ_CLK_SOURCE_REMOTE: /* we need to set the clock pin as input */
5241 + VLYNQ_CTRL_REG = 0ul;
5242 + tmp = ((pdev->clk_div - 1) << 16) | VLYNQ_CTL_CLKDIR_MASK ;
5243 + VLYNQ_R_CTRL_REG = tmp;
5244 + break;
5245 + default: /* do nothing about the clock, but clear other bits. */
5246 + tmp = ~(VLYNQ_CTL_CLKDIR_MASK | VLYNQ_CTL_CLKDIV_MASK);
5247 + VLYNQ_CTRL_REG &= tmp;
5248 + break;
5249 + }
5250 +}
5251 +
5252 + /* ----------------------------------------------------------------------------
5253 + * Function : vlynq_link_check()
5254 + * Description: This function checks the current VLYNQ for a link.
5255 + * An arbitrary amount of time is allowed for the link to come up .
5256 + * Returns 0 for "no link / failure " and 1 for "link available".
5257 + * -----------------------------------------------------------------------------
5258 + */
5259 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev)
5260 +{
5261 + /*sleep for 64 cycles, allow link to come up*/
5262 + vlynq_delay(64);
5263 +
5264 + /* check status register return OK if link is found. */
5265 + if (VLYNQ_STATUS_REG & VLYNQ_STS_LINK_MASK)
5266 + {
5267 + return 1; /* Link Available */
5268 + }
5269 + else
5270 + {
5271 + return 0; /* Link Failure */
5272 + }
5273 +}
5274 +
5275 +/* ----------------------------------------------------------------------------
5276 + * Function : vlynq_init()
5277 + * Description: Initialization function accepting paramaters for VLYNQ module
5278 + * initialization. The Options bitmap decides what operations are performed
5279 + * as a part of initialization. The Input parameters are obtained through the
5280 + * sub fields of VLYNQ_DEV structure.
5281 + */
5282 +
5283 +int vlynq_init(VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options)
5284 +{
5285 + unsigned int map;
5286 + unsigned int val=0,cnt,tmp;
5287 + unsigned int counter=0;
5288 + VLYNQ_INTERRUPT_CNTRL *intSetting=NULL;
5289 +
5290 + /* validate arguments */
5291 + if( VLYNQ_OUTRANGE(pdev->clk_source, VLYNQ_CLK_SOURCE_REMOTE, VLYNQ_CLK_SOURCE_NONE) ||
5292 + VLYNQ_OUTRANGE(pdev->clk_div, 8, 1) )
5293 + {
5294 + return VLYNQ_INVALID_ARG;
5295 + }
5296 +
5297 + /** perform all sanity checks first **/
5298 + if(pdev->state != VLYNQ_DRV_STATE_UNINIT)
5299 + return VLYNQ_INVALID_DRV_STATE;
5300 +
5301 + /** Initialize local and remote register set addresses- additional
5302 + * provision to access the registers directly if need be */
5303 + pdev->local = (VLYNQ_REG_SET*)pdev->module_base;
5304 + pdev->remote = (VLYNQ_REG_SET*) (pdev->module_base + VLYNQ_REMOTE_REGS_OFFSET);
5305 +
5306 + /* Detect faulty int configuration that might induce int pkt looping */
5307 + if ( (options & VLYNQ_INIT_LOCAL_INTERRUPTS) && (options & VLYNQ_INIT_REMOTE_INTERRUPTS) )
5308 + {
5309 + /* case when both local and remote are configured */
5310 + if((pdev->local_irq.intLocal== VLYNQ_INT_REMOTE ) /* interrupts transfered to remote from local */
5311 + && (pdev->remote_irq.intLocal== VLYNQ_INT_REMOTE) /* interrupts transfered from remote to local */
5312 + && ((pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) || (pdev->remote_irq.intRemote == VLYNQ_INT_ROOT_ISR)) )
5313 + {
5314 + return (VLYNQ_INT_CONFIG_ERR);
5315 + }
5316 + }
5317 +
5318 + pdev->state = VLYNQ_DRV_STATE_ININIT;
5319 + pdev->intCount = 0;
5320 + pdev->isrCount = 0;
5321 +
5322 + /*** Its assumed that the vlynq module has been brought out of reset
5323 + * before invocation of vlynq_init. Since, this operation is board specific
5324 + * it must be handled outside this generic driver */
5325 +
5326 + /* Assert reset the remote device, call reset_cb,
5327 + * reset CB holds Reset according to the device needs. */
5328 + VLYNQ_RESETCB(VLYNQ_RESET_ASSERT);
5329 +
5330 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
5331 + * usually input for all the devices. */
5332 + if (options & VLYNQ_INIT_CONFIG_CLOCK)
5333 + {
5334 + vlynq_configClock(pdev);
5335 + }
5336 +
5337 + /* Call reset_cb again. It will release the remote device
5338 + * from reset, and wait for a while. */
5339 + VLYNQ_RESETCB(VLYNQ_RESET_DEASSERT);
5340 +
5341 + if(options & VLYNQ_INIT_CHECK_LINK )
5342 + {
5343 + /* Check for link up during initialization*/
5344 + while( counter < 25 )
5345 + {
5346 + /* loop around giving a chance for link status to settle down */
5347 + counter++;
5348 + if(vlynq_link_check(pdev))
5349 + {
5350 + /* Link is up exit loop*/
5351 + break;
5352 + }
5353 +
5354 + vlynq_delay(4000);
5355 + }/*end of while counter loop */
5356 +
5357 + if(!vlynq_link_check(pdev))
5358 + {
5359 + /* Handle this case as abort */
5360 + pdev->state = VLYNQ_DRV_STATE_ERROR;
5361 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
5362 + return VLYNQ_LINK_DOWN;
5363 + }/* end of if not vlynq_link_check conditional block */
5364 +
5365 + }/*end of if options & VLYNQ_INIT_CHECK_LINK conditional block */
5366 +
5367 +
5368 + if (options & VLYNQ_INIT_LOCAL_MEM_REGIONS)
5369 + {
5370 + /* Initialise local memory regions . This initialization lets
5371 + * the local host access remote device memory regions*/
5372 + int i;
5373 +
5374 + /* configure the VLYNQ portal window to a PHYSICAL
5375 + * address of the local CPU */
5376 + VLYNQ_ALIGN4(pdev->local_mem.Txmap);
5377 + VLYNQ_TXMAP_REG = (pdev->local_mem.Txmap);
5378 +
5379 + /*This code assumes input parameter is itself a physical address */
5380 + for(i=0; i < VLYNQ_MAX_MEMORY_REGIONS ; i++)
5381 + {
5382 + /* Physical address on the remote */
5383 + map = i+1;
5384 + VLYNQ_R_RXMAP_SIZE_REG(map) = 0;
5385 + if( pdev->remote_mem.RxSize[i])
5386 + {
5387 + VLYNQ_ALIGN4(pdev->remote_mem.RxOffset[i]);
5388 + VLYNQ_ALIGN4(pdev->remote_mem.RxSize[i]);
5389 + VLYNQ_R_RXMAP_OFFSET_REG(map) = pdev->remote_mem.RxOffset[i];
5390 + VLYNQ_R_RXMAP_SIZE_REG(map) = pdev->remote_mem.RxSize[i];
5391 + }
5392 + }
5393 + }
5394 +
5395 + if(options & VLYNQ_INIT_REMOTE_MEM_REGIONS )
5396 + {
5397 + int i;
5398 +
5399 + /* Initialise remote memory regions. This initialization lets remote
5400 + * device access local host memory regions. It configures the VLYNQ portal
5401 + * window to a PHYSICAL address of the remote */
5402 + VLYNQ_ALIGN4(pdev->remote_mem.Txmap);
5403 + VLYNQ_R_TXMAP_REG = pdev->remote_mem.Txmap;
5404 +
5405 + for( i=0; i<VLYNQ_MAX_MEMORY_REGIONS; i++)
5406 + {
5407 + /* Physical address on the local */
5408 + map = i+1;
5409 + VLYNQ_RXMAP_SIZE_REG(map) = 0;
5410 + if( pdev->local_mem.RxSize[i])
5411 + {
5412 + VLYNQ_ALIGN4(pdev->local_mem.RxOffset[i]);
5413 + VLYNQ_ALIGN4(pdev->local_mem.RxSize[i]);
5414 + VLYNQ_RXMAP_OFFSET_REG(map) = (pdev->local_mem.RxOffset[i]);
5415 + VLYNQ_RXMAP_SIZE_REG(map) = (pdev->local_mem.RxSize[i]);
5416 + }
5417 + }
5418 + }
5419 +
5420 + /* Adapted from original vlynq driver from cable - Calculate VLYNQ bus width */
5421 + pdev->width = 3 + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_STATUS_REG)
5422 + + VLYNQ_STATUS_FLD_WIDTH(VLYNQ_R_STATUS_REG);
5423 +
5424 + /* chance to initialize the device, e.g. to boost VLYNQ
5425 + * clock by modifying pdev->clk_div or and verify the width. */
5426 + VLYNQ_RESETCB(VLYNQ_RESET_LINKESTABLISH);
5427 +
5428 + /* Handle VLYNQ clock, HW default (Sense On Reset) is
5429 + * usually input for all the devices. */
5430 + if(options & VLYNQ_INIT_CONFIG_CLOCK )
5431 + {
5432 + vlynq_configClock(pdev);
5433 + }
5434 +
5435 + /* last check for link*/
5436 + if(options & VLYNQ_INIT_CHECK_LINK )
5437 + {
5438 + /* Final Check for link during initialization*/
5439 + while( counter < 25 )
5440 + {
5441 + /* loop around giving a chance for link status to settle down */
5442 + counter++;
5443 + if(vlynq_link_check(pdev))
5444 + {
5445 + /* Link is up exit loop*/
5446 + break;
5447 + }
5448 +
5449 + vlynq_delay(4000);
5450 + }/*end of while counter loop */
5451 +
5452 + if(!vlynq_link_check(pdev))
5453 + {
5454 + /* Handle this case as abort */
5455 + pdev->state = VLYNQ_DRV_STATE_ERROR;
5456 + VLYNQ_RESETCB( VLYNQ_RESET_INITFAIL);
5457 + return VLYNQ_LINK_DOWN;
5458 + }/* end of if not vlynq_link_check conditional block */
5459 +
5460 + } /* end of if options & VLYNQ_INIT_CHECK_LINK */
5461 +
5462 + if(options & VLYNQ_INIT_LOCAL_INTERRUPTS )
5463 + {
5464 + /* Configure local interrupt settings */
5465 + intSetting = &(pdev->local_irq);
5466 +
5467 + /* Map local module status interrupts to interrupt vector*/
5468 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
5469 +
5470 + /* enable local module status interrupts */
5471 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
5472 +
5473 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
5474 + {
5475 + /*set the intLocal bit*/
5476 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
5477 + }
5478 +
5479 + /* Irrespective of whether interrupts are handled locally, program
5480 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
5481 + * i.e remote packets are set intPending register->which will result in
5482 + * same packet being sent out) has been done already
5483 + */
5484 +
5485 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
5486 + {
5487 + /* Set the int2Cfg register, so that remote interrupt
5488 + * packets are written to intPending register */
5489 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
5490 +
5491 + /* Set intPtr register to point to intPending register */
5492 + VLYNQ_INT_PTR_REG = VLYNQ_INT_PENDING_REG_PTR ;
5493 + }
5494 + else
5495 + {
5496 + /*set the interrupt pointer register*/
5497 + VLYNQ_INT_PTR_REG = intSetting->intr_ptr;
5498 + /* Dont bother to modify int2Cfg as it would be zero */
5499 + }
5500 +
5501 + /** Clear bits related to INT settings in control register **/
5502 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
5503 +
5504 + /** Or the bits to be set with Control register **/
5505 + VLYNQ_CTRL_REG = VLYNQ_CTRL_REG | val;
5506 +
5507 + /* initialise local ICB */
5508 + if(vlynqInterruptInit(pdev)==VLYNQ_MEMALLOC_FAIL)
5509 + return VLYNQ_MEMALLOC_FAIL;
5510 +
5511 + /* Install handler for local module status interrupts. By default when
5512 + * local interrupt setting is initialised, the local module status are
5513 + * enabled and handler hooked up */
5514 + if(vlynq_install_isr(pdev, intSetting->map_vector, vlynq_local_module_isr,
5515 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
5516 + return VLYNQ_INVALID_ARG;
5517 + } /* end of init local interrupts */
5518 +
5519 + if(options & VLYNQ_INIT_REMOTE_INTERRUPTS )
5520 + {
5521 + /* Configure remote interrupt settings from configuration */
5522 + intSetting = &(pdev->remote_irq);
5523 +
5524 + /* Map remote module status interrupts to remote interrupt vector*/
5525 + val = intSetting->map_vector << VLYNQ_CTL_INTVEC_SHIFT ;
5526 + /* enable remote module status interrupts */
5527 + val |= 0x01 << VLYNQ_CTL_INTEN_SHIFT;
5528 +
5529 + if ( intSetting->intLocal == VLYNQ_INT_LOCAL )
5530 + {
5531 + /*set the intLocal bit*/
5532 + val |= 0x01 << VLYNQ_CTL_INTLOCAL_SHIFT;
5533 + }
5534 +
5535 + /* Irrespective of whether interrupts are handled locally, program
5536 + * int2Cfg. Error checking for accidental loop(when intLocal=0 and int2Cfg=1
5537 + * i.e remote packets are set intPending register->which will result in
5538 + * same packet being sent out) has been done already
5539 + */
5540 +
5541 + if (intSetting->intRemote == VLYNQ_INT_ROOT_ISR)
5542 + {
5543 + /* Set the int2Cfg register, so that remote interrupt
5544 + * packets are written to intPending register */
5545 + val |= 0x01 << VLYNQ_CTL_INT2CFG_SHIFT;
5546 + /* Set intPtr register to point to intPending register */
5547 + VLYNQ_R_INT_PTR_REG = VLYNQ_R_INT_PENDING_REG_PTR ;
5548 + }
5549 + else
5550 + {
5551 + /*set the interrupt pointer register*/
5552 + VLYNQ_R_INT_PTR_REG = intSetting->intr_ptr;
5553 + /* Dont bother to modify int2Cfg as it would be zero */
5554 + }
5555 +
5556 + if( (intSetting->intLocal == VLYNQ_INT_REMOTE) &&
5557 + (options & VLYNQ_INIT_LOCAL_INTERRUPTS) &&
5558 + (pdev->local_irq.intRemote == VLYNQ_INT_ROOT_ISR) )
5559 + {
5560 + /* Install handler for remote module status interrupts. By default when
5561 + * remote interrupts are forwarded to local root_isr then remote_module_isr is
5562 + * enabled and handler hooked up */
5563 + if(vlynq_install_isr(pdev,intSetting->map_vector,vlynq_remote_module_isr,
5564 + pdev, NULL, NULL) == VLYNQ_INVALID_ARG)
5565 + return VLYNQ_INVALID_ARG;
5566 + }
5567 +
5568 +
5569 + /** Clear bits related to INT settings in control register **/
5570 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG & (~VLYNQ_CTL_INTFIELDS_CLEAR_MASK);
5571 +
5572 + /** Or the bits to be set with the remote Control register **/
5573 + VLYNQ_R_CTRL_REG = VLYNQ_R_CTRL_REG | val;
5574 +
5575 + } /* init remote interrupt settings*/
5576 +
5577 + if(options & VLYNQ_INIT_CLEAR_ERRORS )
5578 + {
5579 + /* Clear errors during initialization */
5580 + tmp = VLYNQ_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
5581 + VLYNQ_STATUS_REG = tmp;
5582 + tmp = VLYNQ_R_STATUS_REG & (VLYNQ_STS_RERROR_MASK | VLYNQ_STS_LERROR_MASK);
5583 + VLYNQ_R_STATUS_REG = tmp;
5584 + }
5585 +
5586 + /* clear int status */
5587 + val = VLYNQ_INT_STAT_REG;
5588 + VLYNQ_INT_STAT_REG = val;
5589 +
5590 + /* finish initialization */
5591 + pdev->state = VLYNQ_DRV_STATE_RUN;
5592 + VLYNQ_RESETCB( VLYNQ_RESET_INITOK);
5593 + return VLYNQ_SUCCESS;
5594 +
5595 +}
5596 +
5597 +
5598 +/* ----------------------------------------------------------------------------
5599 + * Function : vlynqInterruptInit()
5600 + * Description: This local function is used to set up the ICB table for the
5601 + * VLYNQ_STATUS_REG vlynq module. The input parameter "pdev" points the vlynq
5602 + * device instance whose ICB is allocated.
5603 + * Return : returns VLYNQ_SUCCESS or vlynq error for failure
5604 + * -----------------------------------------------------------------------------
5605 + */
5606 +static int vlynqInterruptInit(VLYNQ_DEV *pdev)
5607 +{
5608 + int i, numslots;
5609 +
5610 + /* Memory allocated statically.
5611 + * Initialise ICB,free list.Indicate primary slot empty.
5612 + * Intialise intVector <==> map_vector translation table*/
5613 + for(i=0; i < VLYNQ_NUM_INT_BITS; i++)
5614 + {
5615 + pdev->pIntrCB[i].isr = NULL;
5616 + pdev->pIntrCB[i].next = NULL; /*nothing chained */
5617 + pdev->vector_map[i] = -1; /* indicates unmapped */
5618 + }
5619 +
5620 + /* In the ICB slots, [VLYNQ_NUM_INT_BITS i.e 32 to ICB array size) are expansion slots
5621 + * required only when interrupt chaining/sharing is supported. In case
5622 + * of chained interrupts the list starts from primary slot and the
5623 + * additional slots are obtained from the common free area */
5624 +
5625 + /* Initialise freelist */
5626 +
5627 + numslots = VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS;
5628 +
5629 + if (numslots > VLYNQ_NUM_INT_BITS)
5630 + {
5631 + pdev->freelist = &(pdev->pIntrCB[VLYNQ_NUM_INT_BITS]);
5632 +
5633 + for(i = VLYNQ_NUM_INT_BITS; i < (numslots-1) ; i++)
5634 + {
5635 + pdev->pIntrCB[i].next = &(pdev->pIntrCB[i+1]);
5636 + pdev->pIntrCB[i].isr = NULL;
5637 + }
5638 + pdev->pIntrCB[i].next=NULL; /* Indicate end of freelist*/
5639 + pdev->pIntrCB[i].isr=NULL;
5640 + }
5641 + else
5642 + {
5643 + pdev->freelist = NULL;
5644 + }
5645 +
5646 + /** Reset mapping for IV 0-7 **/
5647 + VLYNQ_IVR_03TO00_REG = 0;
5648 + VLYNQ_IVR_07TO04_REG = 0;
5649 +
5650 + return VLYNQ_SUCCESS;
5651 +}
5652 +
5653 +/** remember that hooking up of root ISR handler with the interrupt controller
5654 + * is not done as a part of this driver. Typically, it must be done after
5655 + * invoking vlynq_init*/
5656 +
5657 +
5658 + /* ----------------------------------------------------------------------------
5659 + * ISR with the SOC interrupt controller. This ISR typically scans
5660 + * the Int PENDING/SET register in the VLYNQ module and calls the
5661 + * appropriate ISR associated with the correponding vector number.
5662 + * -----------------------------------------------------------------------------
5663 + */
5664 +void vlynq_root_isr(void *arg)
5665 +{
5666 + int source; /* Bit position of pending interrupt, start from 0 */
5667 + unsigned int interrupts, clrInterrupts;
5668 + VLYNQ_DEV * pdev;
5669 + VLYNQ_INTR_CNTRL_ICB *entry;
5670 +
5671 + pdev=(VLYNQ_DEV*)(arg); /*obtain the vlynq device pointer*/
5672 +
5673 + interrupts = VLYNQ_INT_STAT_REG; /* Get the list of pending interrupts */
5674 + VLYNQ_INT_STAT_REG = interrupts; /* clear the int CR register */
5675 + clrInterrupts = interrupts; /* save them for further analysis */
5676 +
5677 + debugPrint("vlynq_root_isr: dev %u. INTCR = 0x%08lx\n", pdev->dev_idx, clrInterrupts,0,0,0,0);
5678 +
5679 + /* Scan interrupt bits */
5680 + source =0;
5681 + while( clrInterrupts != 0)
5682 + {
5683 + /* test if bit is set? */
5684 + if( 0x1ul & clrInterrupts)
5685 + {
5686 + entry = &(pdev->pIntrCB[source]); /* Get the ISR entry */
5687 + pdev->intCount++; /* update interrupt count */
5688 + if(entry->isr != NULL)
5689 + {
5690 + do
5691 + {
5692 + pdev->isrCount++; /* update isr invocation count */
5693 + /* Call the user ISR and update the count for ISR */
5694 + entry->isrCount++;
5695 + entry->isr(entry->arg1, entry->arg2, entry->arg3);
5696 + if (entry->next == NULL) break;
5697 + entry = entry->next;
5698 +
5699 + } while (entry->isr != NULL);
5700 + }
5701 + else
5702 + {
5703 + debugPrint(" ISR not installed for vlynq vector:%d\n",source,0,0,0,0,0);
5704 + }
5705 + }
5706 + clrInterrupts >>= 1; /* Next source bit */
5707 + ++source;
5708 + } /* endWhile clrInterrupts != 0 */
5709 +}
5710 +
5711 +
5712 + /* ----------------------------------------------------------------------------
5713 + * Function : vlynq_local__module_isr()
5714 + * Description: This ISR is attached to the local VLYNQ interrupt vector
5715 + * by the Vlynq Driver when local interrupts are being handled. i.e.
5716 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5717 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5718 + * is invoked.
5719 + * VLYNQ_DEV is passed as arg1. arg2 and arg3 are unused.
5720 + * -----------------------------------------------------------------------------
5721 + */
5722 +static void vlynq_local_module_isr(void *arg1,void *arg2, void *arg3)
5723 +{
5724 + VLYNQ_REPORT_CB func;
5725 + unsigned int dwStatRegVal;
5726 + VLYNQ_DEV * pdev;
5727 +
5728 + pdev = (VLYNQ_DEV*) arg1;
5729 + /* Callback function is read from the device pointer that is passed as an argument */
5730 + func = pdev->report_cb;
5731 +
5732 + /* read local status register */
5733 + dwStatRegVal = VLYNQ_STATUS_REG;
5734 +
5735 + /* clear pending events */
5736 + VLYNQ_STATUS_REG = dwStatRegVal;
5737 +
5738 + /* invoke user callback */
5739 + if( func != NULL)
5740 + func( pdev, VLYNQ_LOCAL_DVC, dwStatRegVal);
5741 +
5742 +}
5743 +
5744 + /* ----------------------------------------------------------------------------
5745 + * Function : vlynq_remote_module_isr()
5746 + * Description: This ISR is attached to the remote VLYNQ interrupt vector
5747 + * by the Vlynq Driver when remote interrupts are being handled locally. i.e.
5748 + * intLocal=1. This ISR handles local Vlynq module status interrupts only
5749 + * AS a part of this ISR, user callback in VLYNQ_DEV structure
5750 + * is invoked.
5751 + * The parameters irq,regs ar unused.
5752 + * -----------------------------------------------------------------------------
5753 + */
5754 +static void vlynq_remote_module_isr(void *arg1,void *arg2, void *arg3)
5755 +{
5756 + VLYNQ_REPORT_CB func;
5757 + unsigned int dwStatRegVal;
5758 + VLYNQ_DEV * pdev;
5759 +
5760 +
5761 + pdev = (VLYNQ_DEV*) arg1;
5762 +
5763 + /* Callback function is read from the device pointer that is passed as an argument */
5764 + func = pdev->report_cb;
5765 +
5766 + /* read local status register */
5767 + dwStatRegVal = VLYNQ_R_STATUS_REG;
5768 +
5769 + /* clear pending events */
5770 + VLYNQ_R_STATUS_REG = dwStatRegVal;
5771 +
5772 + /* invoke user callback */
5773 + if( func != NULL)
5774 + func( pdev, VLYNQ_REMOTE_DVC, dwStatRegVal);
5775 +
5776 +}
5777 +
5778 +/* ----------------------------------------------------------------------------
5779 + * Function : vlynq_interrupt_get_count()
5780 + * Description: This function returns the number of times a particular intr
5781 + * has been invoked.
5782 + *
5783 + * It returns 0, if erroneous map_vector is specified or if the corres isr
5784 + * has not been registered with VLYNQ.
5785 + */
5786 +unsigned int vlynq_interrupt_get_count(VLYNQ_DEV *pdev,
5787 + unsigned int map_vector)
5788 +{
5789 + VLYNQ_INTR_CNTRL_ICB *entry;
5790 + unsigned int count = 0;
5791 +
5792 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5793 + return count;
5794 +
5795 + entry = &(pdev->pIntrCB[map_vector]);
5796 +
5797 + if (entry)
5798 + count = entry->isrCount;
5799 +
5800 + return (count);
5801 +}
5802 +
5803 +
5804 +/* ----------------------------------------------------------------------------
5805 + * Function : vlynq_install_isr()
5806 + * Description: This function installs ISR for Vlynq interrupt vector
5807 + * bits(in IntPending register). This function should be used only when
5808 + * Vlynq interrupts are being handled locally(remote may be programmed to send
5809 + * interrupt packets).Also, the int2cfg should be 1 and the least significant
5810 + * 8 bits of the Interrupt Pointer Register must point to Interrupt
5811 + * Pending/Set Register).
5812 + * If host int2cfg=0 and the Interrupt Pointer register contains
5813 + * the address of the interrupt set register in the interrupt controller
5814 + * module of the local device , then the ISR for the remote interrupt must be
5815 + * directly registered with the Interrupt controller and must not use this API
5816 + * Note: this function simply installs the ISR in ICB It doesnt modify
5817 + * any register settings
5818 + */
5819 +int
5820 +vlynq_install_isr(VLYNQ_DEV *pdev,
5821 + unsigned int map_vector,
5822 + VLYNQ_INTR_CNTRL_ISR isr,
5823 + void *arg1, void *arg2, void *arg3)
5824 +{
5825 + VLYNQ_INTR_CNTRL_ICB *entry;
5826 +
5827 + if ( (map_vector > (VLYNQ_NUM_INT_BITS-1)) || (isr == NULL) )
5828 + return VLYNQ_INVALID_ARG;
5829 +
5830 + entry = &(pdev->pIntrCB[map_vector]);
5831 +
5832 + if(entry->isr == NULL)
5833 + {
5834 + entry->isr = isr;
5835 + entry->arg1 = arg1;
5836 + entry->arg2 = arg2;
5837 + entry->arg3 = arg3;
5838 + entry->next = NULL;
5839 + }
5840 + else
5841 + {
5842 + /** No more empty slots,return error */
5843 + if(pdev->freelist == NULL)
5844 + return VLYNQ_MEMALLOC_FAIL;
5845 +
5846 + while(entry->next != NULL)
5847 + {
5848 + entry = entry->next;
5849 + }
5850 +
5851 + /* Append new node to the chain */
5852 + entry->next = pdev->freelist;
5853 + /* Remove the appended node from freelist */
5854 + pdev->freelist = pdev->freelist->next;
5855 + entry= entry->next;
5856 +
5857 + /*** Set the ICB fields ***/
5858 + entry->isr = isr;
5859 + entry->arg1 = arg1;
5860 + entry->arg2 = arg2;
5861 + entry->arg3 = arg3;
5862 + entry->next = NULL;
5863 + }
5864 +
5865 + return VLYNQ_SUCCESS;
5866 +}
5867 +
5868 +
5869 +
5870 +/* ----------------------------------------------------------------------------
5871 + * Function : vlynq_uninstall_isr
5872 + * Description: This function is used to uninstall a previously
5873 + * registered ISR. In case of shared/chained interrupts, the
5874 + * void * arg parameter must uniquely identify the ISR to be
5875 + * uninstalled.
5876 + * Note: this function simply uninstalls the ISR in ICB
5877 + * It doesnt modify any register settings
5878 + */
5879 +int
5880 +vlynq_uninstall_isr(VLYNQ_DEV *pdev,
5881 + unsigned int map_vector,
5882 + void *arg1, void *arg2, void *arg3)
5883 +{
5884 + VLYNQ_INTR_CNTRL_ICB *entry,*temp;
5885 +
5886 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
5887 + return VLYNQ_INVALID_ARG;
5888 +
5889 + entry = &(pdev->pIntrCB[map_vector]);
5890 +
5891 + if(entry->isr == NULL )
5892 + return VLYNQ_ISR_NON_EXISTENT;
5893 +
5894 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5895 + {
5896 + if(entry->next == NULL)
5897 + {
5898 + entry->isr=NULL;
5899 + return VLYNQ_SUCCESS;
5900 + }
5901 + else
5902 + {
5903 + temp = entry->next;
5904 + /* Copy next node in the chain to prim.slot */
5905 + entry->isr = temp->isr;
5906 + entry->arg1 = temp->arg1;
5907 + entry->arg2 = temp->arg2;
5908 + entry->arg3 = temp->arg3;
5909 + entry->next = temp->next;
5910 + /* Free the just copied node */
5911 + temp->isr = NULL;
5912 + temp->arg1 = NULL;
5913 + temp->arg2 = NULL;
5914 + temp->arg3 = NULL;
5915 + temp->next = pdev->freelist;
5916 + pdev->freelist = temp;
5917 + return VLYNQ_SUCCESS;
5918 + }
5919 + }
5920 + else
5921 + {
5922 + temp = entry;
5923 + while ( (entry = temp->next) != NULL)
5924 + {
5925 + if ( (entry->arg1 == arg1) && (entry->arg2 == arg2) && (entry->arg3 == arg3) )
5926 + {
5927 + /* remove node from chain */
5928 + temp->next = entry->next;
5929 + /* Add the removed node to freelist */
5930 + entry->isr = NULL;
5931 + entry->arg1 = NULL;
5932 + entry->arg2 = NULL;
5933 + entry->arg3 = NULL;
5934 + entry->next = pdev->freelist;
5935 + entry->isrCount = 0;
5936 + pdev->freelist = entry;
5937 + return VLYNQ_SUCCESS;
5938 + }
5939 + temp = entry;
5940 + }
5941 +
5942 + return VLYNQ_ISR_NON_EXISTENT;
5943 + }
5944 +}
5945 +
5946 +
5947 +
5948 +
5949 +/* ----------------------------------------------------------------------------
5950 + * function : vlynq_interrupt_vector_set()
5951 + * description:configures interrupt vector mapping,interrupt type
5952 + * polarity -all in one go.
5953 + */
5954 +int
5955 +vlynq_interrupt_vector_set(VLYNQ_DEV *pdev, /* vlynq device */
5956 + unsigned int int_vector, /* int vector on vlynq device */
5957 + unsigned int map_vector, /* bit for this interrupt */
5958 + VLYNQ_DEV_TYPE dev_type, /* local or remote device */
5959 + VLYNQ_INTR_POLARITY pol, /* polarity of interrupt */
5960 + VLYNQ_INTR_TYPE type) /* pulsed/level interrupt */
5961 +{
5962 + volatile unsigned int * vecreg;
5963 + unsigned int val=0;
5964 + unsigned int bytemask=0XFF;
5965 +
5966 + /* use the lower 8 bits of val to set the value , shift it to
5967 + * appropriate byte position in the ivr and write it to the
5968 + * corresponding register */
5969 +
5970 + /* validate the number of interrupts supported */
5971 + if (int_vector >= VLYNQ_IVR_MAXIVR)
5972 + return VLYNQ_INVALID_ARG;
5973 +
5974 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
5975 + return VLYNQ_INVALID_ARG;
5976 +
5977 + if (dev_type == VLYNQ_LOCAL_DVC)
5978 + {
5979 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
5980 + }
5981 + else
5982 + {
5983 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
5984 + }
5985 +
5986 + /* Update the intVector<==> bit position translation table */
5987 + pdev->vector_map[map_vector] = int_vector;
5988 +
5989 + /* val has been initialised to zero. we only have to turn on appropriate bits*/
5990 + if(type == VLYNQ_INTR_PULSED)
5991 + val |= VLYNQ_IVR_INTTYPE_MASK;
5992 +
5993 + if(pol == VLYNQ_INTR_ACTIVE_LOW)
5994 + val |= VLYNQ_IVR_INTPOL_MASK;
5995 +
5996 + val |= map_vector;
5997 +
5998 + /** clear the correct byte position and then or val **/
5999 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6000 +
6001 + /** write to correct byte position in vecreg*/
6002 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
6003 +
6004 + /* Setting a interrupt vector, leaves the interrupt disabled
6005 + * which must be enabled subsequently */
6006 +
6007 + return VLYNQ_SUCCESS;
6008 +}
6009 +
6010 +
6011 +/* ----------------------------------------------------------------------------
6012 + * Function : vlynq_interrupt_vector_cntl()
6013 + * Description:enables/disable interrupt
6014 + */
6015 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
6016 + unsigned int int_vector,
6017 + VLYNQ_DEV_TYPE dev_type,
6018 + unsigned int enable)
6019 +{
6020 + volatile unsigned int *vecReg;
6021 + unsigned int val=0;
6022 + unsigned int intenMask=0x80;
6023 +
6024 + /* validate the number of interrupts supported */
6025 + if (int_vector >= VLYNQ_IVR_MAXIVR)
6026 + return VLYNQ_INVALID_ARG;
6027 +
6028 + if (dev_type == VLYNQ_LOCAL_DVC)
6029 + {
6030 + vecReg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6031 + }
6032 + else
6033 + {
6034 + vecReg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6035 + }
6036 +
6037 + /** Clear the correct byte position and then or val **/
6038 + *vecReg = (*vecReg) & ( ~(intenMask << ( (int_vector %4)*8) ) );
6039 +
6040 + if(enable)
6041 + {
6042 + val |= VLYNQ_IVR_INTEN_MASK;
6043 + /** Write to correct byte position in vecReg*/
6044 + *vecReg = (*vecReg) | (val << ( (int_vector % 4)*8) ) ;
6045 + }
6046 +
6047 + return VLYNQ_SUCCESS;
6048 +
6049 +}/* end of function vlynq_interrupt_vector_cntl */
6050 +
6051 +
6052 +
6053 +/* ----------------------------------------------------------------------------
6054 + * Function : vlynq_interrupt_vector_map()
6055 + * Description:Configures interrupt vector mapping alone
6056 + */
6057 +int
6058 +vlynq_interrupt_vector_map( VLYNQ_DEV *pdev,
6059 + VLYNQ_DEV_TYPE dev_type,
6060 + unsigned int int_vector,
6061 + unsigned int map_vector)
6062 +{
6063 + volatile unsigned int * vecreg;
6064 + unsigned int val=0;
6065 + unsigned int bytemask=0x1f; /* mask to turn off bits corresponding to int vector */
6066 +
6067 + /* use the lower 8 bits of val to set the value , shift it to
6068 + * appropriate byte position in the ivr and write it to the
6069 + * corresponding register */
6070 +
6071 + /* validate the number of interrupts supported */
6072 + if (int_vector >= VLYNQ_IVR_MAXIVR)
6073 + return VLYNQ_INVALID_ARG;
6074 +
6075 + if(map_vector > (VLYNQ_NUM_INT_BITS - 1) )
6076 + return VLYNQ_INVALID_ARG;
6077 +
6078 + if (dev_type == VLYNQ_LOCAL_DVC)
6079 + {
6080 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6081 + }
6082 + else
6083 + {
6084 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6085 + }
6086 +
6087 + /* Update the intVector<==> bit position translation table */
6088 + pdev->vector_map[map_vector] = int_vector;
6089 +
6090 + /** val has been initialised to zero. we only have to turn on
6091 + * appropriate bits*/
6092 + val |= map_vector;
6093 +
6094 + /** clear the correct byte position and then or val **/
6095 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6096 +
6097 + /** write to correct byte position in vecreg*/
6098 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
6099 +
6100 + return VLYNQ_SUCCESS;
6101 +}
6102 +
6103 +
6104 +/* ----------------------------------------------------------------------------
6105 + * function : vlynq_interrupt_set_polarity()
6106 + * description:configures interrupt polarity .
6107 + */
6108 +int
6109 +vlynq_interrupt_set_polarity( VLYNQ_DEV *pdev ,
6110 + VLYNQ_DEV_TYPE dev_type,
6111 + unsigned int map_vector,
6112 + VLYNQ_INTR_POLARITY pol)
6113 +{
6114 + volatile unsigned int * vecreg;
6115 + int int_vector;
6116 + unsigned int val=0;
6117 + unsigned int bytemask=0x20; /** mask to turn off bits corresponding to int polarity */
6118 +
6119 + /* get the int_vector from map_vector */
6120 + int_vector = pdev->vector_map[map_vector];
6121 +
6122 + if(int_vector == -1)
6123 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6124 +
6125 + /* use the lower 8 bits of val to set the value , shift it to
6126 + * appropriate byte position in the ivr and write it to the
6127 + * corresponding register */
6128 +
6129 + if (dev_type == VLYNQ_LOCAL_DVC)
6130 + {
6131 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6132 + }
6133 + else
6134 + {
6135 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6136 + }
6137 +
6138 + /* val has been initialised to zero. we only have to turn on
6139 + * appropriate bits, if need be*/
6140 +
6141 + /** clear the correct byte position and then or val **/
6142 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6143 +
6144 + if( pol == VLYNQ_INTR_ACTIVE_LOW)
6145 + {
6146 + val |= VLYNQ_IVR_INTPOL_MASK;
6147 + /** write to correct byte position in vecreg*/
6148 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
6149 + }
6150 +
6151 + return VLYNQ_SUCCESS;
6152 +}
6153 +
6154 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
6155 + VLYNQ_DEV_TYPE dev_type,
6156 + unsigned int map_vector)
6157 +{
6158 + volatile unsigned int * vecreg;
6159 + int int_vector;
6160 + unsigned int val=0;
6161 +
6162 + /* get the int_vector from map_vector */
6163 + int_vector = pdev->vector_map[map_vector];
6164 +
6165 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
6166 + return(-1);
6167 +
6168 + if(int_vector == -1)
6169 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6170 +
6171 + /* use the lower 8 bits of val to set the value , shift it to
6172 + * appropriate byte position in the ivr and write it to the
6173 + * corresponding register */
6174 +
6175 + if (dev_type == VLYNQ_LOCAL_DVC)
6176 + {
6177 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6178 + }
6179 + else
6180 + {
6181 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6182 + }
6183 +
6184 + /** read the information into val **/
6185 + val = (*vecreg) & ((VLYNQ_IVR_INTPOL_MASK << ( (int_vector %4)*8) ) );
6186 +
6187 + return (val ? (VLYNQ_INTR_ACTIVE_LOW) : (VLYNQ_INTR_ACTIVE_HIGH));
6188 +}
6189 +
6190 +
6191 +/* ----------------------------------------------------------------------------
6192 + * function : vlynq_interrupt_set_type()
6193 + * description:configures interrupt type .
6194 + */
6195 +int vlynq_interrupt_set_type( VLYNQ_DEV *pdev,
6196 + VLYNQ_DEV_TYPE dev_type,
6197 + unsigned int map_vector,
6198 + VLYNQ_INTR_TYPE type)
6199 +{
6200 + volatile unsigned int * vecreg;
6201 + unsigned int val=0;
6202 + int int_vector;
6203 +
6204 + /** mask to turn off bits corresponding to interrupt type */
6205 + unsigned int bytemask=0x40;
6206 +
6207 + /* get the int_vector from map_vector */
6208 + int_vector = pdev->vector_map[map_vector];
6209 + if(int_vector == -1)
6210 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6211 +
6212 + /* use the lower 8 bits of val to set the value , shift it to
6213 + * appropriate byte position in the ivr and write it to the
6214 + * corresponding register */
6215 + if (dev_type == VLYNQ_LOCAL_DVC)
6216 + {
6217 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6218 + }
6219 + else
6220 + {
6221 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6222 + }
6223 +
6224 + /** val has been initialised to zero. we only have to turn on
6225 + * appropriate bits if need be*/
6226 +
6227 + /** clear the correct byte position and then or val **/
6228 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6229 +
6230 + if( type == VLYNQ_INTR_PULSED)
6231 + {
6232 + val |= VLYNQ_IVR_INTTYPE_MASK;
6233 + /** write to correct byte position in vecreg*/
6234 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
6235 + }
6236 +
6237 + return VLYNQ_SUCCESS;
6238 +}
6239 +
6240 +/* ----------------------------------------------------------------------------
6241 + * function : vlynq_interrupt_get_type()
6242 + * description:returns interrupt type .
6243 + */
6244 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev, VLYNQ_DEV_TYPE dev_type,
6245 + unsigned int map_vector)
6246 +{
6247 + volatile unsigned int * vecreg;
6248 + unsigned int val=0;
6249 + int int_vector;
6250 +
6251 + if (map_vector > (VLYNQ_NUM_INT_BITS-1))
6252 + return(-1);
6253 +
6254 + /* get the int_vector from map_vector */
6255 + int_vector = pdev->vector_map[map_vector];
6256 + if(int_vector == -1)
6257 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6258 +
6259 + /* use the lower 8 bits of val to set the value , shift it to
6260 + * appropriate byte position in the ivr and write it to the
6261 + * corresponding register */
6262 + if (dev_type == VLYNQ_LOCAL_DVC)
6263 + {
6264 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6265 + }
6266 + else
6267 + {
6268 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6269 + }
6270 +
6271 + /** Read the correct bit position into val **/
6272 + val = (*vecreg) & ((VLYNQ_IVR_INTTYPE_MASK << ( (int_vector %4)*8) ) );
6273 +
6274 + return (val ? (VLYNQ_INTR_PULSED) : (VLYNQ_INTR_LEVEL));
6275 +}
6276 +
6277 +/* ----------------------------------------------------------------------------
6278 + * function : vlynq_interrupt_enable()
6279 + * description:Enable interrupt by writing to IVR register.
6280 + */
6281 +int vlynq_interrupt_enable( VLYNQ_DEV *pdev,
6282 + VLYNQ_DEV_TYPE dev_type,
6283 + unsigned int map_vector)
6284 +{
6285 + volatile unsigned int * vecreg;
6286 + unsigned int val=0;
6287 + int int_vector;
6288 +
6289 + /** mask to turn off bits corresponding to interrupt enable */
6290 + unsigned int bytemask=0x80;
6291 +
6292 + /* get the int_vector from map_vector */
6293 + int_vector = pdev->vector_map[map_vector];
6294 + if(int_vector == -1)
6295 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6296 +
6297 + /* use the lower 8 bits of val to set the value , shift it to
6298 + * appropriate byte position in the ivr and write it to the
6299 + * corresponding register */
6300 +
6301 + if (dev_type == VLYNQ_LOCAL_DVC)
6302 + {
6303 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6304 + }
6305 + else
6306 + {
6307 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6308 + }
6309 +
6310 + /** val has been initialised to zero. we only have to turn on
6311 + * bit corresponding to interrupt enable*/
6312 + val |= VLYNQ_IVR_INTEN_MASK;
6313 +
6314 + /** clear the correct byte position and then or val **/
6315 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6316 +
6317 + /** write to correct byte position in vecreg*/
6318 + *vecreg = (*vecreg) | (val << ( (int_vector % 4)*8) ) ;
6319 +
6320 + return VLYNQ_SUCCESS;
6321 +}
6322 +
6323 +
6324 +/* ----------------------------------------------------------------------------
6325 + * function : vlynq_interrupt_disable()
6326 + * description:Disable interrupt by writing to IVR register.
6327 + */
6328 +int
6329 +vlynq_interrupt_disable( VLYNQ_DEV *pdev,
6330 + VLYNQ_DEV_TYPE dev_type,
6331 + unsigned int map_vector)
6332 +{
6333 + volatile unsigned int * vecreg;
6334 + int int_vector;
6335 +
6336 + /** mask to turn off bits corresponding to interrupt enable */
6337 + unsigned int bytemask=0x80;
6338 +
6339 + /* get the int_vector from map_vector */
6340 + int_vector = pdev->vector_map[map_vector];
6341 + if(int_vector == -1)
6342 + return VLYNQ_INTVEC_MAP_NOT_FOUND;
6343 +
6344 + /* use the lower 8 bits of val to set the value , shift it to
6345 + * appropriate byte position in the ivr and write it to the
6346 + * corresponding register */
6347 + if (dev_type == VLYNQ_LOCAL_DVC)
6348 + {
6349 + vecreg = (volatile unsigned int *) (VLYNQ_IVR_OFFSET(int_vector));
6350 + }
6351 + else
6352 + {
6353 + vecreg = (volatile unsigned int *) (VLYNQ_R_IVR_OFFSET(int_vector));
6354 + }
6355 +
6356 + /* We disable the interrupt by simply turning off the bit
6357 + * corresponding to Interrupt enable.
6358 + * Clear the interrupt enable bit in the correct byte position **/
6359 + *vecreg = (*vecreg) & ( ~(bytemask << ( (int_vector %4)*8) ) );
6360 +
6361 + /* Dont have to set any bit positions */
6362 +
6363 + return VLYNQ_SUCCESS;
6364 +
6365 +}
6366 +
6367 +
6368 +
6369 +
6370 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
6371 --- linux.old/drivers/char/serial.c 2005-10-21 16:43:20.709226000 +0200
6372 +++ linux.dev/drivers/char/serial.c 2005-10-21 16:45:42.166066500 +0200
6373 @@ -419,7 +419,40 @@
6374 return 0;
6375 }
6376
6377 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
6378 +#if defined(CONFIG_AR7)
6379 +
6380 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6381 +{
6382 + return (inb(info->port + (offset * 4)) & 0xff);
6383 +}
6384 +
6385 +
6386 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
6387 +{
6388 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
6389 + return (inb(info->port + (offset * 4)) & 0xff);
6390 +#else
6391 + return (inb_p(info->port + (offset * 4)) & 0xff);
6392 +#endif
6393 +}
6394 +
6395 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
6396 +{
6397 + outb(value, info->port + (offset * 4));
6398 +}
6399 +
6400 +
6401 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
6402 + int value)
6403 +{
6404 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
6405 + outb(value, info->port + (offset * 4));
6406 +#else
6407 + outb_p(value, info->port + (offset * 4));
6408 +#endif
6409 +}
6410 +
6411 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
6412
6413 #include <asm/mips-boards/atlas.h>
6414
6415 @@ -478,8 +511,10 @@
6416 * needed for certain old 386 machines, I've left these #define's
6417 * in....
6418 */
6419 +#ifndef CONFIG_AR7
6420 #define serial_inp(info, offset) serial_in(info, offset)
6421 #define serial_outp(info, offset, value) serial_out(info, offset, value)
6422 +#endif
6423
6424
6425 /*
6426 @@ -1728,7 +1763,15 @@
6427 /* Special case since 134 is really 134.5 */
6428 quot = (2*baud_base / 269);
6429 else if (baud)
6430 +#ifdef CONFIG_AR7
6431 + quot = (CONFIG_AR7_SYS*500000) / baud;
6432 +
6433 + if ((quot%16)>7)
6434 + quot += 8;
6435 + quot /=16;
6436 +#else
6437 quot = baud_base / baud;
6438 +#endif
6439 }
6440 /* If the quotient is zero refuse the change */
6441 if (!quot && old_termios) {
6442 @@ -5540,8 +5583,10 @@
6443 state->irq = irq_cannonicalize(state->irq);
6444 if (state->hub6)
6445 state->io_type = SERIAL_IO_HUB6;
6446 +#ifndef CONFIG_AR7
6447 if (state->port && check_region(state->port,8))
6448 continue;
6449 +#endif
6450 #ifdef CONFIG_MCA
6451 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
6452 continue;
6453 @@ -5997,7 +6042,15 @@
6454 info->io_type = state->io_type;
6455 info->iomem_base = state->iomem_base;
6456 info->iomem_reg_shift = state->iomem_reg_shift;
6457 +#ifdef CONFIG_AR7
6458 + quot = (CONFIG_AR7_SYS*500000) / baud;
6459 +
6460 + if ((quot%16)>7)
6461 + quot += 8;
6462 + quot /=16;
6463 +#else
6464 quot = state->baud_base / baud;
6465 +#endif
6466 cval = cflag & (CSIZE | CSTOPB);
6467 #if defined(__powerpc__) || defined(__alpha__)
6468 cval >>= 8;
6469 diff -urN linux.old/drivers/char/serial.c.orig linux.dev/drivers/char/serial.c.orig
6470 --- linux.old/drivers/char/serial.c.orig 1970-01-01 01:00:00.000000000 +0100
6471 +++ linux.dev/drivers/char/serial.c.orig 2005-10-21 16:43:20.709226000 +0200
6472 @@ -0,0 +1,6054 @@
6473 +/*
6474 + * linux/drivers/char/serial.c
6475 + *
6476 + * Copyright (C) 1991, 1992 Linus Torvalds
6477 + * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997,
6478 + * 1998, 1999 Theodore Ts'o
6479 + *
6480 + * Extensively rewritten by Theodore Ts'o, 8/16/92 -- 9/14/92. Now
6481 + * much more extensible to support other serial cards based on the
6482 + * 16450/16550A UART's. Added support for the AST FourPort and the
6483 + * Accent Async board.
6484 + *
6485 + * set_serial_info fixed to set the flags, custom divisor, and uart
6486 + * type fields. Fix suggested by Michael K. Johnson 12/12/92.
6487 + *
6488 + * 11/95: TIOCMIWAIT, TIOCGICOUNT by Angelo Haritsis <ah@doc.ic.ac.uk>
6489 + *
6490 + * 03/96: Modularised by Angelo Haritsis <ah@doc.ic.ac.uk>
6491 + *
6492 + * rs_set_termios fixed to look also for changes of the input
6493 + * flags INPCK, BRKINT, PARMRK, IGNPAR and IGNBRK.
6494 + * Bernd Anhäupl 05/17/96.
6495 + *
6496 + * 1/97: Extended dumb serial ports are a config option now.
6497 + * Saves 4k. Michael A. Griffith <grif@acm.org>
6498 + *
6499 + * 8/97: Fix bug in rs_set_termios with RTS
6500 + * Stanislav V. Voronyi <stas@uanet.kharkov.ua>
6501 + *
6502 + * 3/98: Change the IRQ detection, use of probe_irq_o*(),
6503 + * suppress TIOCSERGWILD and TIOCSERSWILD
6504 + * Etienne Lorrain <etienne.lorrain@ibm.net>
6505 + *
6506 + * 4/98: Added changes to support the ARM architecture proposed by
6507 + * Russell King
6508 + *
6509 + * 5/99: Updated to include support for the XR16C850 and ST16C654
6510 + * uarts. Stuart MacDonald <stuartm@connecttech.com>
6511 + *
6512 + * 8/99: Generalized PCI support added. Theodore Ts'o
6513 + *
6514 + * 3/00: Rid circular buffer of redundant xmit_cnt. Fix a
6515 + * few races on freeing buffers too.
6516 + * Alan Modra <alan@linuxcare.com>
6517 + *
6518 + * 5/00: Support for the RSA-DV II/S card added.
6519 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
6520 + *
6521 + * 6/00: Remove old-style timer, use timer_list
6522 + * Andrew Morton <andrewm@uow.edu.au>
6523 + *
6524 + * 7/00: Support Timedia/Sunix/Exsys PCI cards
6525 + *
6526 + * 7/00: fix some returns on failure not using MOD_DEC_USE_COUNT.
6527 + * Arnaldo Carvalho de Melo <acme@conectiva.com.br>
6528 + *
6529 + * 10/00: add in optional software flow control for serial console.
6530 + * Kanoj Sarcar <kanoj@sgi.com> (Modified by Theodore Ts'o)
6531 + *
6532 + * 02/02: Fix for AMD Elan bug in transmit irq routine, by
6533 + * Christer Weinigel <wingel@hog.ctrl-c.liu.se>,
6534 + * Robert Schwebel <robert@schwebel.de>,
6535 + * Juergen Beisert <jbeisert@eurodsn.de>,
6536 + * Theodore Ts'o <tytso@mit.edu>
6537 + *
6538 + * 10/00: Added suport for MIPS Atlas board.
6539 + * 11/00: Hooks for serial kernel debug port support added.
6540 + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard,
6541 + * carstenl@mips.com
6542 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6543 + */
6544 +
6545 +static char *serial_version = "5.05c";
6546 +static char *serial_revdate = "2001-07-08";
6547 +
6548 +/*
6549 + * Serial driver configuration section. Here are the various options:
6550 + *
6551 + * CONFIG_HUB6
6552 + * Enables support for the venerable Bell Technologies
6553 + * HUB6 card.
6554 + *
6555 + * CONFIG_SERIAL_MANY_PORTS
6556 + * Enables support for ports beyond the standard, stupid
6557 + * COM 1/2/3/4.
6558 + *
6559 + * CONFIG_SERIAL_MULTIPORT
6560 + * Enables support for special multiport board support.
6561 + *
6562 + * CONFIG_SERIAL_SHARE_IRQ
6563 + * Enables support for multiple serial ports on one IRQ
6564 + *
6565 + * CONFIG_SERIAL_DETECT_IRQ
6566 + * Enable the autodetection of IRQ on standart ports
6567 + *
6568 + * SERIAL_PARANOIA_CHECK
6569 + * Check the magic number for the async_structure where
6570 + * ever possible.
6571 + *
6572 + * CONFIG_SERIAL_ACPI
6573 + * Enable support for serial console port and serial
6574 + * debug port as defined by the SPCR and DBGP tables in
6575 + * ACPI 2.0.
6576 + */
6577 +
6578 +#include <linux/config.h>
6579 +#include <linux/version.h>
6580 +
6581 +#undef SERIAL_PARANOIA_CHECK
6582 +#define CONFIG_SERIAL_NOPAUSE_IO
6583 +#define SERIAL_DO_RESTART
6584 +
6585 +#if 0
6586 +/* These defines are normally controlled by the autoconf.h */
6587 +#define CONFIG_SERIAL_MANY_PORTS
6588 +#define CONFIG_SERIAL_SHARE_IRQ
6589 +#define CONFIG_SERIAL_DETECT_IRQ
6590 +#define CONFIG_SERIAL_MULTIPORT
6591 +#define CONFIG_HUB6
6592 +#endif
6593 +
6594 +#ifdef CONFIG_PCI
6595 +#define ENABLE_SERIAL_PCI
6596 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6597 +#define CONFIG_SERIAL_SHARE_IRQ
6598 +#endif
6599 +#ifndef CONFIG_SERIAL_MANY_PORTS
6600 +#define CONFIG_SERIAL_MANY_PORTS
6601 +#endif
6602 +#endif
6603 +
6604 +#ifdef CONFIG_SERIAL_ACPI
6605 +#define ENABLE_SERIAL_ACPI
6606 +#endif
6607 +
6608 +#if defined(CONFIG_ISAPNP)|| (defined(CONFIG_ISAPNP_MODULE) && defined(MODULE))
6609 +#ifndef ENABLE_SERIAL_PNP
6610 +#define ENABLE_SERIAL_PNP
6611 +#endif
6612 +#endif
6613 +
6614 +/* Set of debugging defines */
6615 +
6616 +#undef SERIAL_DEBUG_INTR
6617 +#undef SERIAL_DEBUG_OPEN
6618 +#undef SERIAL_DEBUG_FLOW
6619 +#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
6620 +#undef SERIAL_DEBUG_PCI
6621 +#undef SERIAL_DEBUG_AUTOCONF
6622 +
6623 +/* Sanity checks */
6624 +
6625 +#ifdef CONFIG_SERIAL_MULTIPORT
6626 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6627 +#define CONFIG_SERIAL_SHARE_IRQ
6628 +#endif
6629 +#endif
6630 +
6631 +#ifdef CONFIG_HUB6
6632 +#ifndef CONFIG_SERIAL_MANY_PORTS
6633 +#define CONFIG_SERIAL_MANY_PORTS
6634 +#endif
6635 +#ifndef CONFIG_SERIAL_SHARE_IRQ
6636 +#define CONFIG_SERIAL_SHARE_IRQ
6637 +#endif
6638 +#endif
6639 +
6640 +#ifdef MODULE
6641 +#undef CONFIG_SERIAL_CONSOLE
6642 +#endif
6643 +
6644 +#define CONFIG_SERIAL_RSA
6645 +
6646 +#define RS_STROBE_TIME (10*HZ)
6647 +#define RS_ISR_PASS_LIMIT 256
6648 +
6649 +#if defined(__i386__) && (defined(CONFIG_M386) || defined(CONFIG_M486))
6650 +#define SERIAL_INLINE
6651 +#endif
6652 +
6653 +/*
6654 + * End of serial driver configuration section.
6655 + */
6656 +
6657 +#include <linux/module.h>
6658 +
6659 +#include <linux/types.h>
6660 +#ifdef LOCAL_HEADERS
6661 +#include "serial_local.h"
6662 +#else
6663 +#include <linux/serial.h>
6664 +#include <linux/serialP.h>
6665 +#include <linux/serial_reg.h>
6666 +#include <asm/serial.h>
6667 +#define LOCAL_VERSTRING ""
6668 +#endif
6669 +
6670 +#include <linux/errno.h>
6671 +#include <linux/signal.h>
6672 +#include <linux/sched.h>
6673 +#include <linux/timer.h>
6674 +#include <linux/interrupt.h>
6675 +#include <linux/tty.h>
6676 +#include <linux/tty_flip.h>
6677 +#include <linux/major.h>
6678 +#include <linux/string.h>
6679 +#include <linux/fcntl.h>
6680 +#include <linux/ptrace.h>
6681 +#include <linux/ioport.h>
6682 +#include <linux/mm.h>
6683 +#include <linux/slab.h>
6684 +#if (LINUX_VERSION_CODE >= 131343)
6685 +#include <linux/init.h>
6686 +#endif
6687 +#if (LINUX_VERSION_CODE >= 131336)
6688 +#include <asm/uaccess.h>
6689 +#endif
6690 +#include <linux/delay.h>
6691 +#ifdef CONFIG_SERIAL_CONSOLE
6692 +#include <linux/console.h>
6693 +#endif
6694 +#ifdef ENABLE_SERIAL_PCI
6695 +#include <linux/pci.h>
6696 +#endif
6697 +#ifdef ENABLE_SERIAL_PNP
6698 +#include <linux/isapnp.h>
6699 +#endif
6700 +#ifdef CONFIG_MAGIC_SYSRQ
6701 +#include <linux/sysrq.h>
6702 +#endif
6703 +
6704 +/*
6705 + * All of the compatibilty code so we can compile serial.c against
6706 + * older kernels is hidden in serial_compat.h
6707 + */
6708 +#if defined(LOCAL_HEADERS) || (LINUX_VERSION_CODE < 0x020317) /* 2.3.23 */
6709 +#include "serial_compat.h"
6710 +#endif
6711 +
6712 +#include <asm/system.h>
6713 +#include <asm/io.h>
6714 +#include <asm/irq.h>
6715 +#include <asm/bitops.h>
6716 +
6717 +#if defined(CONFIG_MAC_SERIAL)
6718 +#define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2)
6719 +#else
6720 +#define SERIAL_DEV_OFFSET 0
6721 +#endif
6722 +
6723 +#ifdef SERIAL_INLINE
6724 +#define _INLINE_ inline
6725 +#else
6726 +#define _INLINE_
6727 +#endif
6728 +
6729 +static char *serial_name = "Serial driver";
6730 +
6731 +static DECLARE_TASK_QUEUE(tq_serial);
6732 +
6733 +static struct tty_driver serial_driver, callout_driver;
6734 +static int serial_refcount;
6735 +
6736 +static struct timer_list serial_timer;
6737 +
6738 +/* serial subtype definitions */
6739 +#ifndef SERIAL_TYPE_NORMAL
6740 +#define SERIAL_TYPE_NORMAL 1
6741 +#define SERIAL_TYPE_CALLOUT 2
6742 +#endif
6743 +
6744 +/* number of characters left in xmit buffer before we ask for more */
6745 +#define WAKEUP_CHARS 256
6746 +
6747 +/*
6748 + * IRQ_timeout - How long the timeout should be for each IRQ
6749 + * should be after the IRQ has been active.
6750 + */
6751 +
6752 +static struct async_struct *IRQ_ports[NR_IRQS];
6753 +#ifdef CONFIG_SERIAL_MULTIPORT
6754 +static struct rs_multiport_struct rs_multiport[NR_IRQS];
6755 +#endif
6756 +static int IRQ_timeout[NR_IRQS];
6757 +#ifdef CONFIG_SERIAL_CONSOLE
6758 +static struct console sercons;
6759 +static int lsr_break_flag;
6760 +#endif
6761 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6762 +static unsigned long break_pressed; /* break, really ... */
6763 +#endif
6764 +
6765 +static unsigned detect_uart_irq (struct serial_state * state);
6766 +static void autoconfig(struct serial_state * state);
6767 +static void change_speed(struct async_struct *info, struct termios *old);
6768 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
6769 +
6770 +/*
6771 + * Here we define the default xmit fifo size used for each type of
6772 + * UART
6773 + */
6774 +static struct serial_uart_config uart_config[] = {
6775 + { "unknown", 1, 0 },
6776 + { "8250", 1, 0 },
6777 + { "16450", 1, 0 },
6778 + { "16550", 1, 0 },
6779 + { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
6780 + { "cirrus", 1, 0 }, /* usurped by cyclades.c */
6781 + { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
6782 + { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO |
6783 + UART_STARTECH },
6784 + { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO},
6785 + { "Startech", 1, 0}, /* usurped by cyclades.c */
6786 + { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO},
6787 + { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO |
6788 + UART_STARTECH },
6789 + { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO |
6790 + UART_STARTECH },
6791 + { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO },
6792 + { 0, 0}
6793 +};
6794 +
6795 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
6796 +
6797 +#define PORT_RSA_MAX 4
6798 +static int probe_rsa[PORT_RSA_MAX];
6799 +static int force_rsa[PORT_RSA_MAX];
6800 +
6801 +MODULE_PARM(probe_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6802 +MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
6803 +MODULE_PARM(force_rsa, "1-" __MODULE_STRING(PORT_RSA_MAX) "i");
6804 +MODULE_PARM_DESC(force_rsa, "Force I/O ports for RSA");
6805 +#endif /* CONFIG_SERIAL_RSA */
6806 +
6807 +struct serial_state rs_table[RS_TABLE_SIZE] = {
6808 + SERIAL_PORT_DFNS /* Defined in serial.h */
6809 +};
6810 +
6811 +#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state))
6812 +int serial_nr_ports = NR_PORTS;
6813 +
6814 +#if (defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP))
6815 +#define NR_PCI_BOARDS 8
6816 +
6817 +static struct pci_board_inst serial_pci_board[NR_PCI_BOARDS];
6818 +
6819 +#ifndef IS_PCI_REGION_IOPORT
6820 +#define IS_PCI_REGION_IOPORT(dev, r) (pci_resource_flags((dev), (r)) & \
6821 + IORESOURCE_IO)
6822 +#endif
6823 +#ifndef IS_PCI_REGION_IOMEM
6824 +#define IS_PCI_REGION_IOMEM(dev, r) (pci_resource_flags((dev), (r)) & \
6825 + IORESOURCE_MEM)
6826 +#endif
6827 +#ifndef PCI_IRQ_RESOURCE
6828 +#define PCI_IRQ_RESOURCE(dev, r) ((dev)->irq_resource[r].start)
6829 +#endif
6830 +#ifndef pci_get_subvendor
6831 +#define pci_get_subvendor(dev) ((dev)->subsystem_vendor)
6832 +#define pci_get_subdevice(dev) ((dev)->subsystem_device)
6833 +#endif
6834 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
6835 +
6836 +#ifndef PREPARE_FUNC
6837 +#define PREPARE_FUNC(dev) (dev->prepare)
6838 +#define ACTIVATE_FUNC(dev) (dev->activate)
6839 +#define DEACTIVATE_FUNC(dev) (dev->deactivate)
6840 +#endif
6841 +
6842 +#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
6843 +
6844 +static struct tty_struct *serial_table[NR_PORTS];
6845 +static struct termios *serial_termios[NR_PORTS];
6846 +static struct termios *serial_termios_locked[NR_PORTS];
6847 +
6848 +
6849 +#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT)
6850 +#define DBG_CNT(s) printk("(%s): [%x] refc=%d, serc=%d, ttyc=%d -> %s\n", \
6851 + kdevname(tty->device), (info->flags), serial_refcount,info->count,tty->count,s)
6852 +#else
6853 +#define DBG_CNT(s)
6854 +#endif
6855 +
6856 +/*
6857 + * tmp_buf is used as a temporary buffer by serial_write. We need to
6858 + * lock it in case the copy_from_user blocks while swapping in a page,
6859 + * and some other program tries to do a serial write at the same time.
6860 + * Since the lock will only come under contention when the system is
6861 + * swapping and available memory is low, it makes sense to share one
6862 + * buffer across all the serial ports, since it significantly saves
6863 + * memory if large numbers of serial ports are open.
6864 + */
6865 +static unsigned char *tmp_buf;
6866 +#ifdef DECLARE_MUTEX
6867 +static DECLARE_MUTEX(tmp_buf_sem);
6868 +#else
6869 +static struct semaphore tmp_buf_sem = MUTEX;
6870 +#endif
6871 +
6872 +
6873 +static inline int serial_paranoia_check(struct async_struct *info,
6874 + kdev_t device, const char *routine)
6875 +{
6876 +#ifdef SERIAL_PARANOIA_CHECK
6877 + static const char *badmagic =
6878 + "Warning: bad magic number for serial struct (%s) in %s\n";
6879 + static const char *badinfo =
6880 + "Warning: null async_struct for (%s) in %s\n";
6881 +
6882 + if (!info) {
6883 + printk(badinfo, kdevname(device), routine);
6884 + return 1;
6885 + }
6886 + if (info->magic != SERIAL_MAGIC) {
6887 + printk(badmagic, kdevname(device), routine);
6888 + return 1;
6889 + }
6890 +#endif
6891 + return 0;
6892 +}
6893 +
6894 +#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
6895 +
6896 +#include <asm/mips-boards/atlas.h>
6897 +
6898 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6899 +{
6900 + return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff);
6901 +}
6902 +
6903 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
6904 +{
6905 + *(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value;
6906 +}
6907 +
6908 +#else
6909 +
6910 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
6911 +{
6912 + switch (info->io_type) {
6913 +#ifdef CONFIG_HUB6
6914 + case SERIAL_IO_HUB6:
6915 + outb(info->hub6 - 1 + offset, info->port);
6916 + return inb(info->port+1);
6917 +#endif
6918 + case SERIAL_IO_MEM:
6919 + return readb((unsigned long) info->iomem_base +
6920 + (offset<<info->iomem_reg_shift));
6921 + default:
6922 + return inb(info->port + offset);
6923 + }
6924 +}
6925 +
6926 +static _INLINE_ void serial_out(struct async_struct *info, int offset,
6927 + int value)
6928 +{
6929 + switch (info->io_type) {
6930 +#ifdef CONFIG_HUB6
6931 + case SERIAL_IO_HUB6:
6932 + outb(info->hub6 - 1 + offset, info->port);
6933 + outb(value, info->port+1);
6934 + break;
6935 +#endif
6936 + case SERIAL_IO_MEM:
6937 + writeb(value, (unsigned long) info->iomem_base +
6938 + (offset<<info->iomem_reg_shift));
6939 + break;
6940 + default:
6941 + outb(value, info->port+offset);
6942 + }
6943 +}
6944 +#endif
6945 +
6946 +
6947 +/*
6948 + * We used to support using pause I/O for certain machines. We
6949 + * haven't supported this for a while, but just in case it's badly
6950 + * needed for certain old 386 machines, I've left these #define's
6951 + * in....
6952 + */
6953 +#define serial_inp(info, offset) serial_in(info, offset)
6954 +#define serial_outp(info, offset, value) serial_out(info, offset, value)
6955 +
6956 +
6957 +/*
6958 + * For the 16C950
6959 + */
6960 +void serial_icr_write(struct async_struct *info, int offset, int value)
6961 +{
6962 + serial_out(info, UART_SCR, offset);
6963 + serial_out(info, UART_ICR, value);
6964 +}
6965 +
6966 +unsigned int serial_icr_read(struct async_struct *info, int offset)
6967 +{
6968 + int value;
6969 +
6970 + serial_icr_write(info, UART_ACR, info->ACR | UART_ACR_ICRRD);
6971 + serial_out(info, UART_SCR, offset);
6972 + value = serial_in(info, UART_ICR);
6973 + serial_icr_write(info, UART_ACR, info->ACR);
6974 + return value;
6975 +}
6976 +
6977 +/*
6978 + * ------------------------------------------------------------
6979 + * rs_stop() and rs_start()
6980 + *
6981 + * This routines are called before setting or resetting tty->stopped.
6982 + * They enable or disable transmitter interrupts, as necessary.
6983 + * ------------------------------------------------------------
6984 + */
6985 +static void rs_stop(struct tty_struct *tty)
6986 +{
6987 + struct async_struct *info = (struct async_struct *)tty->driver_data;
6988 + unsigned long flags;
6989 +
6990 + if (serial_paranoia_check(info, tty->device, "rs_stop"))
6991 + return;
6992 +
6993 + save_flags(flags); cli();
6994 + if (info->IER & UART_IER_THRI) {
6995 + info->IER &= ~UART_IER_THRI;
6996 + serial_out(info, UART_IER, info->IER);
6997 + }
6998 + if (info->state->type == PORT_16C950) {
6999 + info->ACR |= UART_ACR_TXDIS;
7000 + serial_icr_write(info, UART_ACR, info->ACR);
7001 + }
7002 + restore_flags(flags);
7003 +}
7004 +
7005 +static void rs_start(struct tty_struct *tty)
7006 +{
7007 + struct async_struct *info = (struct async_struct *)tty->driver_data;
7008 + unsigned long flags;
7009 +
7010 + if (serial_paranoia_check(info, tty->device, "rs_start"))
7011 + return;
7012 +
7013 + save_flags(flags); cli();
7014 + if (info->xmit.head != info->xmit.tail
7015 + && info->xmit.buf
7016 + && !(info->IER & UART_IER_THRI)) {
7017 + info->IER |= UART_IER_THRI;
7018 + serial_out(info, UART_IER, info->IER);
7019 + }
7020 + if (info->state->type == PORT_16C950) {
7021 + info->ACR &= ~UART_ACR_TXDIS;
7022 + serial_icr_write(info, UART_ACR, info->ACR);
7023 + }
7024 + restore_flags(flags);
7025 +}
7026 +
7027 +/*
7028 + * ----------------------------------------------------------------------
7029 + *
7030 + * Here starts the interrupt handling routines. All of the following
7031 + * subroutines are declared as inline and are folded into
7032 + * rs_interrupt(). They were separated out for readability's sake.
7033 + *
7034 + * Note: rs_interrupt() is a "fast" interrupt, which means that it
7035 + * runs with interrupts turned off. People who may want to modify
7036 + * rs_interrupt() should try to keep the interrupt handler as fast as
7037 + * possible. After you are done making modifications, it is not a bad
7038 + * idea to do:
7039 + *
7040 + * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
7041 + *
7042 + * and look at the resulting assemble code in serial.s.
7043 + *
7044 + * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
7045 + * -----------------------------------------------------------------------
7046 + */
7047 +
7048 +/*
7049 + * This routine is used by the interrupt handler to schedule
7050 + * processing in the software interrupt portion of the driver.
7051 + */
7052 +static _INLINE_ void rs_sched_event(struct async_struct *info,
7053 + int event)
7054 +{
7055 + info->event |= 1 << event;
7056 + queue_task(&info->tqueue, &tq_serial);
7057 + mark_bh(SERIAL_BH);
7058 +}
7059 +
7060 +static _INLINE_ void receive_chars(struct async_struct *info,
7061 + int *status, struct pt_regs * regs)
7062 +{
7063 + struct tty_struct *tty = info->tty;
7064 + unsigned char ch;
7065 + struct async_icount *icount;
7066 + int max_count = 256;
7067 +
7068 + icount = &info->state->icount;
7069 + do {
7070 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
7071 + tty->flip.tqueue.routine((void *) tty);
7072 + if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
7073 + /* no room in flip buffer, discard rx FIFO contents to clear IRQ
7074 + * *FIXME* Hardware with auto flow control
7075 + * would benefit from leaving the data in the FIFO and
7076 + * disabling the rx IRQ until space becomes available.
7077 + */
7078 + do {
7079 + serial_inp(info, UART_RX);
7080 + icount->overrun++;
7081 + *status = serial_inp(info, UART_LSR);
7082 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
7083 + return; // if TTY_DONT_FLIP is set
7084 + }
7085 + }
7086 + ch = serial_inp(info, UART_RX);
7087 + *tty->flip.char_buf_ptr = ch;
7088 + icount->rx++;
7089 +
7090 +#ifdef SERIAL_DEBUG_INTR
7091 + printk("DR%02x:%02x...", ch, *status);
7092 +#endif
7093 + *tty->flip.flag_buf_ptr = 0;
7094 + if (*status & (UART_LSR_BI | UART_LSR_PE |
7095 + UART_LSR_FE | UART_LSR_OE)) {
7096 + /*
7097 + * For statistics only
7098 + */
7099 + if (*status & UART_LSR_BI) {
7100 + *status &= ~(UART_LSR_FE | UART_LSR_PE);
7101 + icount->brk++;
7102 + /*
7103 + * We do the SysRQ and SAK checking
7104 + * here because otherwise the break
7105 + * may get masked by ignore_status_mask
7106 + * or read_status_mask.
7107 + */
7108 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7109 + if (info->line == sercons.index) {
7110 + if (!break_pressed) {
7111 + break_pressed = jiffies;
7112 + goto ignore_char;
7113 + }
7114 + break_pressed = 0;
7115 + }
7116 +#endif
7117 + if (info->flags & ASYNC_SAK)
7118 + do_SAK(tty);
7119 + } else if (*status & UART_LSR_PE)
7120 + icount->parity++;
7121 + else if (*status & UART_LSR_FE)
7122 + icount->frame++;
7123 + if (*status & UART_LSR_OE)
7124 + icount->overrun++;
7125 +
7126 + /*
7127 + * Mask off conditions which should be ignored.
7128 + */
7129 + *status &= info->read_status_mask;
7130 +
7131 +#ifdef CONFIG_SERIAL_CONSOLE
7132 + if (info->line == sercons.index) {
7133 + /* Recover the break flag from console xmit */
7134 + *status |= lsr_break_flag;
7135 + lsr_break_flag = 0;
7136 + }
7137 +#endif
7138 + if (*status & (UART_LSR_BI)) {
7139 +#ifdef SERIAL_DEBUG_INTR
7140 + printk("handling break....");
7141 +#endif
7142 + *tty->flip.flag_buf_ptr = TTY_BREAK;
7143 + } else if (*status & UART_LSR_PE)
7144 + *tty->flip.flag_buf_ptr = TTY_PARITY;
7145 + else if (*status & UART_LSR_FE)
7146 + *tty->flip.flag_buf_ptr = TTY_FRAME;
7147 + }
7148 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7149 + if (break_pressed && info->line == sercons.index) {
7150 + if (ch != 0 &&
7151 + time_before(jiffies, break_pressed + HZ*5)) {
7152 + handle_sysrq(ch, regs, NULL, NULL);
7153 + break_pressed = 0;
7154 + goto ignore_char;
7155 + }
7156 + break_pressed = 0;
7157 + }
7158 +#endif
7159 + if ((*status & info->ignore_status_mask) == 0) {
7160 + tty->flip.flag_buf_ptr++;
7161 + tty->flip.char_buf_ptr++;
7162 + tty->flip.count++;
7163 + }
7164 + if ((*status & UART_LSR_OE) &&
7165 + (tty->flip.count < TTY_FLIPBUF_SIZE)) {
7166 + /*
7167 + * Overrun is special, since it's reported
7168 + * immediately, and doesn't affect the current
7169 + * character
7170 + */
7171 + *tty->flip.flag_buf_ptr = TTY_OVERRUN;
7172 + tty->flip.count++;
7173 + tty->flip.flag_buf_ptr++;
7174 + tty->flip.char_buf_ptr++;
7175 + }
7176 +#if defined(CONFIG_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
7177 + ignore_char:
7178 +#endif
7179 + *status = serial_inp(info, UART_LSR);
7180 + } while ((*status & UART_LSR_DR) && (max_count-- > 0));
7181 +#if (LINUX_VERSION_CODE > 131394) /* 2.1.66 */
7182 + tty_flip_buffer_push(tty);
7183 +#else
7184 + queue_task_irq_off(&tty->flip.tqueue, &tq_timer);
7185 +#endif
7186 +}
7187 +
7188 +static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done)
7189 +{
7190 + int count;
7191 +
7192 + if (info->x_char) {
7193 + serial_outp(info, UART_TX, info->x_char);
7194 + info->state->icount.tx++;
7195 + info->x_char = 0;
7196 + if (intr_done)
7197 + *intr_done = 0;
7198 + return;
7199 + }
7200 + if (info->xmit.head == info->xmit.tail
7201 + || info->tty->stopped
7202 + || info->tty->hw_stopped) {
7203 + info->IER &= ~UART_IER_THRI;
7204 + serial_out(info, UART_IER, info->IER);
7205 + return;
7206 + }
7207 +
7208 + count = info->xmit_fifo_size;
7209 + do {
7210 + serial_out(info, UART_TX, info->xmit.buf[info->xmit.tail]);
7211 + info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
7212 + info->state->icount.tx++;
7213 + if (info->xmit.head == info->xmit.tail)
7214 + break;
7215 + } while (--count > 0);
7216 +
7217 + if (CIRC_CNT(info->xmit.head,
7218 + info->xmit.tail,
7219 + SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
7220 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
7221 +
7222 +#ifdef SERIAL_DEBUG_INTR
7223 + printk("THRE...");
7224 +#endif
7225 + if (intr_done)
7226 + *intr_done = 0;
7227 +
7228 + if (info->xmit.head == info->xmit.tail) {
7229 + info->IER &= ~UART_IER_THRI;
7230 + serial_out(info, UART_IER, info->IER);
7231 + }
7232 +}
7233 +
7234 +static _INLINE_ void check_modem_status(struct async_struct *info)
7235 +{
7236 + int status;
7237 + struct async_icount *icount;
7238 +
7239 + status = serial_in(info, UART_MSR);
7240 +
7241 + if (status & UART_MSR_ANY_DELTA) {
7242 + icount = &info->state->icount;
7243 + /* update input line counters */
7244 + if (status & UART_MSR_TERI)
7245 + icount->rng++;
7246 + if (status & UART_MSR_DDSR)
7247 + icount->dsr++;
7248 + if (status & UART_MSR_DDCD) {
7249 + icount->dcd++;
7250 +#ifdef CONFIG_HARD_PPS
7251 + if ((info->flags & ASYNC_HARDPPS_CD) &&
7252 + (status & UART_MSR_DCD))
7253 + hardpps();
7254 +#endif
7255 + }
7256 + if (status & UART_MSR_DCTS)
7257 + icount->cts++;
7258 + wake_up_interruptible(&info->delta_msr_wait);
7259 + }
7260 +
7261 + if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
7262 +#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
7263 + printk("ttys%d CD now %s...", info->line,
7264 + (status & UART_MSR_DCD) ? "on" : "off");
7265 +#endif
7266 + if (status & UART_MSR_DCD)
7267 + wake_up_interruptible(&info->open_wait);
7268 + else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
7269 + (info->flags & ASYNC_CALLOUT_NOHUP))) {
7270 +#ifdef SERIAL_DEBUG_OPEN
7271 + printk("doing serial hangup...");
7272 +#endif
7273 + if (info->tty)
7274 + tty_hangup(info->tty);
7275 + }
7276 + }
7277 + if (info->flags & ASYNC_CTS_FLOW) {
7278 + if (info->tty->hw_stopped) {
7279 + if (status & UART_MSR_CTS) {
7280 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
7281 + printk("CTS tx start...");
7282 +#endif
7283 + info->tty->hw_stopped = 0;
7284 + info->IER |= UART_IER_THRI;
7285 + serial_out(info, UART_IER, info->IER);
7286 + rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
7287 + return;
7288 + }
7289 + } else {
7290 + if (!(status & UART_MSR_CTS)) {
7291 +#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
7292 + printk("CTS tx stop...");
7293 +#endif
7294 + info->tty->hw_stopped = 1;
7295 + info->IER &= ~UART_IER_THRI;
7296 + serial_out(info, UART_IER, info->IER);
7297 + }
7298 + }
7299 + }
7300 +}
7301 +
7302 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7303 +/*
7304 + * This is the serial driver's generic interrupt routine
7305 + */
7306 +static void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs)
7307 +{
7308 + int status, iir;
7309 + struct async_struct * info;
7310 + int pass_counter = 0;
7311 + struct async_struct *end_mark = 0;
7312 +#ifdef CONFIG_SERIAL_MULTIPORT
7313 + int first_multi = 0;
7314 + struct rs_multiport_struct *multi;
7315 +#endif
7316 +
7317 +#ifdef SERIAL_DEBUG_INTR
7318 + printk("rs_interrupt(%d)...", irq);
7319 +#endif
7320 +
7321 + info = IRQ_ports[irq];
7322 + if (!info)
7323 + return;
7324 +
7325 +#ifdef CONFIG_SERIAL_MULTIPORT
7326 + multi = &rs_multiport[irq];
7327 + if (multi->port_monitor)
7328 + first_multi = inb(multi->port_monitor);
7329 +#endif
7330 +
7331 + do {
7332 + if (!info->tty ||
7333 + ((iir=serial_in(info, UART_IIR)) & UART_IIR_NO_INT)) {
7334 + if (!end_mark)
7335 + end_mark = info;
7336 + goto next;
7337 + }
7338 +#ifdef SERIAL_DEBUG_INTR
7339 + printk("IIR = %x...", serial_in(info, UART_IIR));
7340 +#endif
7341 + end_mark = 0;
7342 +
7343 + info->last_active = jiffies;
7344 +
7345 + status = serial_inp(info, UART_LSR);
7346 +#ifdef SERIAL_DEBUG_INTR
7347 + printk("status = %x...", status);
7348 +#endif
7349 + if (status & UART_LSR_DR)
7350 + receive_chars(info, &status, regs);
7351 + check_modem_status(info);
7352 +#ifdef CONFIG_MELAN
7353 + if ((status & UART_LSR_THRE) ||
7354 + /* for buggy ELAN processors */
7355 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
7356 + transmit_chars(info, 0);
7357 +#else
7358 + if (status & UART_LSR_THRE)
7359 + transmit_chars(info, 0);
7360 +#endif
7361 +
7362 + next:
7363 + info = info->next_port;
7364 + if (!info) {
7365 + info = IRQ_ports[irq];
7366 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
7367 +#if 0
7368 + printk("rs loop break\n");
7369 +#endif
7370 + break; /* Prevent infinite loops */
7371 + }
7372 + continue;
7373 + }
7374 + } while (end_mark != info);
7375 +#ifdef CONFIG_SERIAL_MULTIPORT
7376 + if (multi->port_monitor)
7377 + printk("rs port monitor (normal) irq %d: 0x%x, 0x%x\n",
7378 + info->state->irq, first_multi,
7379 + inb(multi->port_monitor));
7380 +#endif
7381 +#ifdef SERIAL_DEBUG_INTR
7382 + printk("end.\n");
7383 +#endif
7384 +}
7385 +#endif /* #ifdef CONFIG_SERIAL_SHARE_IRQ */
7386 +
7387 +
7388 +/*
7389 + * This is the serial driver's interrupt routine for a single port
7390 + */
7391 +static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs)
7392 +{
7393 + int status, iir;
7394 + int pass_counter = 0;
7395 + struct async_struct * info;
7396 +#ifdef CONFIG_SERIAL_MULTIPORT
7397 + int first_multi = 0;
7398 + struct rs_multiport_struct *multi;
7399 +#endif
7400 +
7401 +#ifdef SERIAL_DEBUG_INTR
7402 + printk("rs_interrupt_single(%d)...", irq);
7403 +#endif
7404 +
7405 + info = IRQ_ports[irq];
7406 + if (!info || !info->tty)
7407 + return;
7408 +
7409 +#ifdef CONFIG_SERIAL_MULTIPORT
7410 + multi = &rs_multiport[irq];
7411 + if (multi->port_monitor)
7412 + first_multi = inb(multi->port_monitor);
7413 +#endif
7414 +
7415 + iir = serial_in(info, UART_IIR);
7416 + do {
7417 + status = serial_inp(info, UART_LSR);
7418 +#ifdef SERIAL_DEBUG_INTR
7419 + printk("status = %x...", status);
7420 +#endif
7421 + if (status & UART_LSR_DR)
7422 + receive_chars(info, &status, regs);
7423 + check_modem_status(info);
7424 +#ifdef CONFIG_MELAN
7425 + if ((status & UART_LSR_THRE) ||
7426 + /* For buggy ELAN processors */
7427 + ((iir & UART_IIR_ID) == UART_IIR_THRI))
7428 + transmit_chars(info, 0);
7429 +#else
7430 + if (status & UART_LSR_THRE)
7431 + transmit_chars(info, 0);
7432 +#endif
7433 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
7434 +#if SERIAL_DEBUG_INTR
7435 + printk("rs_single loop break.\n");
7436 +#endif
7437 + break;
7438 + }
7439 + iir = serial_in(info, UART_IIR);
7440 +#ifdef SERIAL_DEBUG_INTR
7441 + printk("IIR = %x...", iir);
7442 +#endif
7443 + } while ((iir & UART_IIR_NO_INT) == 0);
7444 + info->last_active = jiffies;
7445 +#ifdef CONFIG_SERIAL_MULTIPORT
7446 + if (multi->port_monitor)
7447 + printk("rs port monitor (single) irq %d: 0x%x, 0x%x\n",
7448 + info->state->irq, first_multi,
7449 + inb(multi->port_monitor));
7450 +#endif
7451 +#ifdef SERIAL_DEBUG_INTR
7452 + printk("end.\n");
7453 +#endif
7454 +}
7455 +
7456 +#ifdef CONFIG_SERIAL_MULTIPORT
7457 +/*
7458 + * This is the serial driver's for multiport boards
7459 + */
7460 +static void rs_interrupt_multi(int irq, void *dev_id, struct pt_regs * regs)
7461 +{
7462 + int status;
7463 + struct async_struct * info;
7464 + int pass_counter = 0;
7465 + int first_multi= 0;
7466 + struct rs_multiport_struct *multi;
7467 +
7468 +#ifdef SERIAL_DEBUG_INTR
7469 + printk("rs_interrupt_multi(%d)...", irq);
7470 +#endif
7471 +
7472 + info = IRQ_ports[irq];
7473 + if (!info)
7474 + return;
7475 + multi = &rs_multiport[irq];
7476 + if (!multi->port1) {
7477 + /* Should never happen */
7478 + printk("rs_interrupt_multi: NULL port1!\n");
7479 + return;
7480 + }
7481 + if (multi->port_monitor)
7482 + first_multi = inb(multi->port_monitor);
7483 +
7484 + while (1) {
7485 + if (!info->tty ||
7486 + (serial_in(info, UART_IIR) & UART_IIR_NO_INT))
7487 + goto next;
7488 +
7489 + info->last_active = jiffies;
7490 +
7491 + status = serial_inp(info, UART_LSR);
7492 +#ifdef SERIAL_DEBUG_INTR
7493 + printk("status = %x...", status);
7494 +#endif
7495 + if (status & UART_LSR_DR)
7496 + receive_chars(info, &status, regs);
7497 + check_modem_status(info);
7498 + if (status & UART_LSR_THRE)
7499 + transmit_chars(info, 0);
7500 +
7501 + next:
7502 + info = info->next_port;
7503 + if (info)
7504 + continue;
7505 +
7506 + info = IRQ_ports[irq];
7507 + /*
7508 + * The user was a bonehead, and misconfigured their
7509 + * multiport info. Rather than lock up the kernel
7510 + * in an infinite loop, if we loop too many times,
7511 + * print a message and break out of the loop.
7512 + */
7513 + if (pass_counter++ > RS_ISR_PASS_LIMIT) {
7514 + printk("Misconfigured multiport serial info "
7515 + "for irq %d. Breaking out irq loop\n", irq);
7516 + break;
7517 + }
7518 + if (multi->port_monitor)
7519 + printk("rs port monitor irq %d: 0x%x, 0x%x\n",
7520 + info->state->irq, first_multi,
7521 + inb(multi->port_monitor));
7522 + if ((inb(multi->port1) & multi->mask1) != multi->match1)
7523 + continue;
7524 + if (!multi->port2)
7525 + break;
7526 + if ((inb(multi->port2) & multi->mask2) != multi->match2)
7527 + continue;
7528 + if (!multi->port3)
7529 + break;
7530 + if ((inb(multi->port3) & multi->mask3) != multi->match3)
7531 + continue;
7532 + if (!multi->port4)
7533 + break;
7534 + if ((inb(multi->port4) & multi->mask4) != multi->match4)
7535 + continue;
7536 + break;
7537 + }
7538 +#ifdef SERIAL_DEBUG_INTR
7539 + printk("end.\n");
7540 +#endif
7541 +}
7542 +#endif
7543 +
7544 +/*
7545 + * -------------------------------------------------------------------
7546 + * Here ends the serial interrupt routines.
7547 + * -------------------------------------------------------------------
7548 + */
7549 +
7550 +/*
7551 + * This routine is used to handle the "bottom half" processing for the
7552 + * serial driver, known also the "software interrupt" processing.
7553 + * This processing is done at the kernel interrupt level, after the
7554 + * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
7555 + * is where time-consuming activities which can not be done in the
7556 + * interrupt driver proper are done; the interrupt driver schedules
7557 + * them using rs_sched_event(), and they get done here.
7558 + */
7559 +static void do_serial_bh(void)
7560 +{
7561 + run_task_queue(&tq_serial);
7562 +}
7563 +
7564 +static void do_softint(void *private_)
7565 +{
7566 + struct async_struct *info = (struct async_struct *) private_;
7567 + struct tty_struct *tty;
7568 +
7569 + tty = info->tty;
7570 + if (!tty)
7571 + return;
7572 +
7573 + if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) {
7574 + tty_wakeup(tty);
7575 +
7576 +#ifdef SERIAL_HAVE_POLL_WAIT
7577 + wake_up_interruptible(&tty->poll_wait);
7578 +#endif
7579 + }
7580 +}
7581 +
7582 +/*
7583 + * This subroutine is called when the RS_TIMER goes off. It is used
7584 + * by the serial driver to handle ports that do not have an interrupt
7585 + * (irq=0). This doesn't work very well for 16450's, but gives barely
7586 + * passable results for a 16550A. (Although at the expense of much
7587 + * CPU overhead).
7588 + */
7589 +static void rs_timer(unsigned long dummy)
7590 +{
7591 + static unsigned long last_strobe;
7592 + struct async_struct *info;
7593 + unsigned int i;
7594 + unsigned long flags;
7595 +
7596 + if ((jiffies - last_strobe) >= RS_STROBE_TIME) {
7597 + for (i=0; i < NR_IRQS; i++) {
7598 + info = IRQ_ports[i];
7599 + if (!info)
7600 + continue;
7601 + save_flags(flags); cli();
7602 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7603 + if (info->next_port) {
7604 + do {
7605 + serial_out(info, UART_IER, 0);
7606 + info->IER |= UART_IER_THRI;
7607 + serial_out(info, UART_IER, info->IER);
7608 + info = info->next_port;
7609 + } while (info);
7610 +#ifdef CONFIG_SERIAL_MULTIPORT
7611 + if (rs_multiport[i].port1)
7612 + rs_interrupt_multi(i, NULL, NULL);
7613 + else
7614 +#endif
7615 + rs_interrupt(i, NULL, NULL);
7616 + } else
7617 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
7618 + rs_interrupt_single(i, NULL, NULL);
7619 + restore_flags(flags);
7620 + }
7621 + }
7622 + last_strobe = jiffies;
7623 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
7624 +
7625 + if (IRQ_ports[0]) {
7626 + save_flags(flags); cli();
7627 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7628 + rs_interrupt(0, NULL, NULL);
7629 +#else
7630 + rs_interrupt_single(0, NULL, NULL);
7631 +#endif
7632 + restore_flags(flags);
7633 +
7634 + mod_timer(&serial_timer, jiffies + IRQ_timeout[0]);
7635 + }
7636 +}
7637 +
7638 +/*
7639 + * ---------------------------------------------------------------
7640 + * Low level utility subroutines for the serial driver: routines to
7641 + * figure out the appropriate timeout for an interrupt chain, routines
7642 + * to initialize and startup a serial port, and routines to shutdown a
7643 + * serial port. Useful stuff like that.
7644 + * ---------------------------------------------------------------
7645 + */
7646 +
7647 +/*
7648 + * This routine figures out the correct timeout for a particular IRQ.
7649 + * It uses the smallest timeout of all of the serial ports in a
7650 + * particular interrupt chain. Now only used for IRQ 0....
7651 + */
7652 +static void figure_IRQ_timeout(int irq)
7653 +{
7654 + struct async_struct *info;
7655 + int timeout = 60*HZ; /* 60 seconds === a long time :-) */
7656 +
7657 + info = IRQ_ports[irq];
7658 + if (!info) {
7659 + IRQ_timeout[irq] = 60*HZ;
7660 + return;
7661 + }
7662 + while (info) {
7663 + if (info->timeout < timeout)
7664 + timeout = info->timeout;
7665 + info = info->next_port;
7666 + }
7667 + if (!irq)
7668 + timeout = timeout / 2;
7669 + IRQ_timeout[irq] = (timeout > 3) ? timeout-2 : 1;
7670 +}
7671 +
7672 +#ifdef CONFIG_SERIAL_RSA
7673 +/* Attempts to turn on the RSA FIFO. Returns zero on failure */
7674 +static int enable_rsa(struct async_struct *info)
7675 +{
7676 + unsigned char mode;
7677 + int result;
7678 + unsigned long flags;
7679 +
7680 + save_flags(flags); cli();
7681 + mode = serial_inp(info, UART_RSA_MSR);
7682 + result = mode & UART_RSA_MSR_FIFO;
7683 +
7684 + if (!result) {
7685 + serial_outp(info, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
7686 + mode = serial_inp(info, UART_RSA_MSR);
7687 + result = mode & UART_RSA_MSR_FIFO;
7688 + }
7689 +
7690 + restore_flags(flags);
7691 + return result;
7692 +}
7693 +
7694 +/* Attempts to turn off the RSA FIFO. Returns zero on failure */
7695 +static int disable_rsa(struct async_struct *info)
7696 +{
7697 + unsigned char mode;
7698 + int result;
7699 + unsigned long flags;
7700 +
7701 + save_flags(flags); cli();
7702 + mode = serial_inp(info, UART_RSA_MSR);
7703 + result = !(mode & UART_RSA_MSR_FIFO);
7704 +
7705 + if (!result) {
7706 + serial_outp(info, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
7707 + mode = serial_inp(info, UART_RSA_MSR);
7708 + result = !(mode & UART_RSA_MSR_FIFO);
7709 + }
7710 +
7711 + restore_flags(flags);
7712 + return result;
7713 +}
7714 +#endif /* CONFIG_SERIAL_RSA */
7715 +
7716 +static int startup(struct async_struct * info)
7717 +{
7718 + unsigned long flags;
7719 + int retval=0;
7720 + void (*handler)(int, void *, struct pt_regs *);
7721 + struct serial_state *state= info->state;
7722 + unsigned long page;
7723 +#ifdef CONFIG_SERIAL_MANY_PORTS
7724 + unsigned short ICP;
7725 +#endif
7726 +
7727 + page = get_zeroed_page(GFP_KERNEL);
7728 + if (!page)
7729 + return -ENOMEM;
7730 +
7731 + save_flags(flags); cli();
7732 +
7733 + if (info->flags & ASYNC_INITIALIZED) {
7734 + free_page(page);
7735 + goto errout;
7736 + }
7737 +
7738 + if (!CONFIGURED_SERIAL_PORT(state) || !state->type) {
7739 + if (info->tty)
7740 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7741 + free_page(page);
7742 + goto errout;
7743 + }
7744 + if (info->xmit.buf)
7745 + free_page(page);
7746 + else
7747 + info->xmit.buf = (unsigned char *) page;
7748 +
7749 +#ifdef SERIAL_DEBUG_OPEN
7750 + printk("starting up ttys%d (irq %d)...", info->line, state->irq);
7751 +#endif
7752 +
7753 + if (uart_config[state->type].flags & UART_STARTECH) {
7754 + /* Wake up UART */
7755 + serial_outp(info, UART_LCR, 0xBF);
7756 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7757 + /*
7758 + * Turn off LCR == 0xBF so we actually set the IER
7759 + * register on the XR16C850
7760 + */
7761 + serial_outp(info, UART_LCR, 0);
7762 + serial_outp(info, UART_IER, 0);
7763 + /*
7764 + * Now reset LCR so we can turn off the ECB bit
7765 + */
7766 + serial_outp(info, UART_LCR, 0xBF);
7767 + serial_outp(info, UART_EFR, 0);
7768 + /*
7769 + * For a XR16C850, we need to set the trigger levels
7770 + */
7771 + if (state->type == PORT_16850) {
7772 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7773 + UART_FCTR_RX);
7774 + serial_outp(info, UART_TRG, UART_TRG_96);
7775 + serial_outp(info, UART_FCTR, UART_FCTR_TRGD |
7776 + UART_FCTR_TX);
7777 + serial_outp(info, UART_TRG, UART_TRG_96);
7778 + }
7779 + serial_outp(info, UART_LCR, 0);
7780 + }
7781 +
7782 + if (state->type == PORT_16750) {
7783 + /* Wake up UART */
7784 + serial_outp(info, UART_IER, 0);
7785 + }
7786 +
7787 + if (state->type == PORT_16C950) {
7788 + /* Wake up and initialize UART */
7789 + info->ACR = 0;
7790 + serial_outp(info, UART_LCR, 0xBF);
7791 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7792 + serial_outp(info, UART_IER, 0);
7793 + serial_outp(info, UART_LCR, 0);
7794 + serial_icr_write(info, UART_CSR, 0); /* Reset the UART */
7795 + serial_outp(info, UART_LCR, 0xBF);
7796 + serial_outp(info, UART_EFR, UART_EFR_ECB);
7797 + serial_outp(info, UART_LCR, 0);
7798 + }
7799 +
7800 +#ifdef CONFIG_SERIAL_RSA
7801 + /*
7802 + * If this is an RSA port, see if we can kick it up to the
7803 + * higher speed clock.
7804 + */
7805 + if (state->type == PORT_RSA) {
7806 + if (state->baud_base != SERIAL_RSA_BAUD_BASE &&
7807 + enable_rsa(info))
7808 + state->baud_base = SERIAL_RSA_BAUD_BASE;
7809 + if (state->baud_base == SERIAL_RSA_BAUD_BASE)
7810 + serial_outp(info, UART_RSA_FRR, 0);
7811 + }
7812 +#endif
7813 +
7814 + /*
7815 + * Clear the FIFO buffers and disable them
7816 + * (they will be reenabled in change_speed())
7817 + */
7818 + if (uart_config[state->type].flags & UART_CLEAR_FIFO) {
7819 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
7820 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
7821 + UART_FCR_CLEAR_RCVR |
7822 + UART_FCR_CLEAR_XMIT));
7823 + serial_outp(info, UART_FCR, 0);
7824 + }
7825 +
7826 + /*
7827 + * Clear the interrupt registers.
7828 + */
7829 + (void) serial_inp(info, UART_LSR);
7830 + (void) serial_inp(info, UART_RX);
7831 + (void) serial_inp(info, UART_IIR);
7832 + (void) serial_inp(info, UART_MSR);
7833 +
7834 + /*
7835 + * At this point there's no way the LSR could still be 0xFF;
7836 + * if it is, then bail out, because there's likely no UART
7837 + * here.
7838 + */
7839 + if (!(info->flags & ASYNC_BUGGY_UART) &&
7840 + (serial_inp(info, UART_LSR) == 0xff)) {
7841 + printk("ttyS%d: LSR safety check engaged!\n", state->line);
7842 + if (capable(CAP_SYS_ADMIN)) {
7843 + if (info->tty)
7844 + set_bit(TTY_IO_ERROR, &info->tty->flags);
7845 + } else
7846 + retval = -ENODEV;
7847 + goto errout;
7848 + }
7849 +
7850 + /*
7851 + * Allocate the IRQ if necessary
7852 + */
7853 + if (state->irq && (!IRQ_ports[state->irq] ||
7854 + !IRQ_ports[state->irq]->next_port)) {
7855 + if (IRQ_ports[state->irq]) {
7856 +#ifdef CONFIG_SERIAL_SHARE_IRQ
7857 + free_irq(state->irq, &IRQ_ports[state->irq]);
7858 +#ifdef CONFIG_SERIAL_MULTIPORT
7859 + if (rs_multiport[state->irq].port1)
7860 + handler = rs_interrupt_multi;
7861 + else
7862 +#endif
7863 + handler = rs_interrupt;
7864 +#else
7865 + retval = -EBUSY;
7866 + goto errout;
7867 +#endif /* CONFIG_SERIAL_SHARE_IRQ */
7868 + } else
7869 + handler = rs_interrupt_single;
7870 +
7871 + retval = request_irq(state->irq, handler, SA_SHIRQ,
7872 + "serial", &IRQ_ports[state->irq]);
7873 + if (retval) {
7874 + if (capable(CAP_SYS_ADMIN)) {
7875 + if (info->tty)
7876 + set_bit(TTY_IO_ERROR,
7877 + &info->tty->flags);
7878 + retval = 0;
7879 + }
7880 + goto errout;
7881 + }
7882 + }
7883 +
7884 + /*
7885 + * Insert serial port into IRQ chain.
7886 + */
7887 + info->prev_port = 0;
7888 + info->next_port = IRQ_ports[state->irq];
7889 + if (info->next_port)
7890 + info->next_port->prev_port = info;
7891 + IRQ_ports[state->irq] = info;
7892 + figure_IRQ_timeout(state->irq);
7893 +
7894 + /*
7895 + * Now, initialize the UART
7896 + */
7897 + serial_outp(info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
7898 +
7899 + info->MCR = 0;
7900 + if (info->tty->termios->c_cflag & CBAUD)
7901 + info->MCR = UART_MCR_DTR | UART_MCR_RTS;
7902 +#ifdef CONFIG_SERIAL_MANY_PORTS
7903 + if (info->flags & ASYNC_FOURPORT) {
7904 + if (state->irq == 0)
7905 + info->MCR |= UART_MCR_OUT1;
7906 + } else
7907 +#endif
7908 + {
7909 + if (state->irq != 0)
7910 + info->MCR |= UART_MCR_OUT2;
7911 + }
7912 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
7913 + serial_outp(info, UART_MCR, info->MCR);
7914 +
7915 + /*
7916 + * Finally, enable interrupts
7917 + */
7918 + info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
7919 + serial_outp(info, UART_IER, info->IER); /* enable interrupts */
7920 +
7921 +#ifdef CONFIG_SERIAL_MANY_PORTS
7922 + if (info->flags & ASYNC_FOURPORT) {
7923 + /* Enable interrupts on the AST Fourport board */
7924 + ICP = (info->port & 0xFE0) | 0x01F;
7925 + outb_p(0x80, ICP);
7926 + (void) inb_p(ICP);
7927 + }
7928 +#endif
7929 +
7930 + /*
7931 + * And clear the interrupt registers again for luck.
7932 + */
7933 + (void)serial_inp(info, UART_LSR);
7934 + (void)serial_inp(info, UART_RX);
7935 + (void)serial_inp(info, UART_IIR);
7936 + (void)serial_inp(info, UART_MSR);
7937 +
7938 + if (info->tty)
7939 + clear_bit(TTY_IO_ERROR, &info->tty->flags);
7940 + info->xmit.head = info->xmit.tail = 0;
7941 +
7942 + /*
7943 + * Set up serial timers...
7944 + */
7945 + mod_timer(&serial_timer, jiffies + 2*HZ/100);
7946 +
7947 + /*
7948 + * Set up the tty->alt_speed kludge
7949 + */
7950 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
7951 + if (info->tty) {
7952 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
7953 + info->tty->alt_speed = 57600;
7954 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
7955 + info->tty->alt_speed = 115200;
7956 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
7957 + info->tty->alt_speed = 230400;
7958 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
7959 + info->tty->alt_speed = 460800;
7960 + }
7961 +#endif
7962 +
7963 + /*
7964 + * and set the speed of the serial port
7965 + */
7966 + change_speed(info, 0);
7967 +
7968 + info->flags |= ASYNC_INITIALIZED;
7969 + restore_flags(flags);
7970 + return 0;
7971 +
7972 +errout:
7973 + restore_flags(flags);
7974 + return retval;
7975 +}
7976 +
7977 +/*
7978 + * This routine will shutdown a serial port; interrupts are disabled, and
7979 + * DTR is dropped if the hangup on close termio flag is on.
7980 + */
7981 +static void shutdown(struct async_struct * info)
7982 +{
7983 + unsigned long flags;
7984 + struct serial_state *state;
7985 + int retval;
7986 +
7987 + if (!(info->flags & ASYNC_INITIALIZED))
7988 + return;
7989 +
7990 + state = info->state;
7991 +
7992 +#ifdef SERIAL_DEBUG_OPEN
7993 + printk("Shutting down serial port %d (irq %d)....", info->line,
7994 + state->irq);
7995 +#endif
7996 +
7997 + save_flags(flags); cli(); /* Disable interrupts */
7998 +
7999 + /*
8000 + * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
8001 + * here so the queue might never be waken up
8002 + */
8003 + wake_up_interruptible(&info->delta_msr_wait);
8004 +
8005 + /*
8006 + * First unlink the serial port from the IRQ chain...
8007 + */
8008 + if (info->next_port)
8009 + info->next_port->prev_port = info->prev_port;
8010 + if (info->prev_port)
8011 + info->prev_port->next_port = info->next_port;
8012 + else
8013 + IRQ_ports[state->irq] = info->next_port;
8014 + figure_IRQ_timeout(state->irq);
8015 +
8016 + /*
8017 + * Free the IRQ, if necessary
8018 + */
8019 + if (state->irq && (!IRQ_ports[state->irq] ||
8020 + !IRQ_ports[state->irq]->next_port)) {
8021 + if (IRQ_ports[state->irq]) {
8022 + free_irq(state->irq, &IRQ_ports[state->irq]);
8023 + retval = request_irq(state->irq, rs_interrupt_single,
8024 + SA_SHIRQ, "serial",
8025 + &IRQ_ports[state->irq]);
8026 +
8027 + if (retval)
8028 + printk("serial shutdown: request_irq: error %d"
8029 + " Couldn't reacquire IRQ.\n", retval);
8030 + } else
8031 + free_irq(state->irq, &IRQ_ports[state->irq]);
8032 + }
8033 +
8034 + if (info->xmit.buf) {
8035 + unsigned long pg = (unsigned long) info->xmit.buf;
8036 + info->xmit.buf = 0;
8037 + free_page(pg);
8038 + }
8039 +
8040 + info->IER = 0;
8041 + serial_outp(info, UART_IER, 0x00); /* disable all intrs */
8042 +#ifdef CONFIG_SERIAL_MANY_PORTS
8043 + if (info->flags & ASYNC_FOURPORT) {
8044 + /* reset interrupts on the AST Fourport board */
8045 + (void) inb((info->port & 0xFE0) | 0x01F);
8046 + info->MCR |= UART_MCR_OUT1;
8047 + } else
8048 +#endif
8049 + info->MCR &= ~UART_MCR_OUT2;
8050 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
8051 +
8052 + /* disable break condition */
8053 + serial_out(info, UART_LCR, serial_inp(info, UART_LCR) & ~UART_LCR_SBC);
8054 +
8055 + if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
8056 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
8057 + serial_outp(info, UART_MCR, info->MCR);
8058 +
8059 + /* disable FIFO's */
8060 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
8061 + UART_FCR_CLEAR_RCVR |
8062 + UART_FCR_CLEAR_XMIT));
8063 + serial_outp(info, UART_FCR, 0);
8064 +
8065 +#ifdef CONFIG_SERIAL_RSA
8066 + /*
8067 + * Reset the RSA board back to 115kbps compat mode.
8068 + */
8069 + if ((state->type == PORT_RSA) &&
8070 + (state->baud_base == SERIAL_RSA_BAUD_BASE &&
8071 + disable_rsa(info)))
8072 + state->baud_base = SERIAL_RSA_BAUD_BASE_LO;
8073 +#endif
8074 +
8075 +
8076 + (void)serial_in(info, UART_RX); /* read data port to reset things */
8077 +
8078 + if (info->tty)
8079 + set_bit(TTY_IO_ERROR, &info->tty->flags);
8080 +
8081 + if (uart_config[info->state->type].flags & UART_STARTECH) {
8082 + /* Arrange to enter sleep mode */
8083 + serial_outp(info, UART_LCR, 0xBF);
8084 + serial_outp(info, UART_EFR, UART_EFR_ECB);
8085 + serial_outp(info, UART_LCR, 0);
8086 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
8087 + serial_outp(info, UART_LCR, 0xBF);
8088 + serial_outp(info, UART_EFR, 0);
8089 + serial_outp(info, UART_LCR, 0);
8090 + }
8091 + if (info->state->type == PORT_16750) {
8092 + /* Arrange to enter sleep mode */
8093 + serial_outp(info, UART_IER, UART_IERX_SLEEP);
8094 + }
8095 + info->flags &= ~ASYNC_INITIALIZED;
8096 + restore_flags(flags);
8097 +}
8098 +
8099 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8100 +static int baud_table[] = {
8101 + 0, 50, 75, 110, 134, 150, 200, 300,
8102 + 600, 1200, 1800, 2400, 4800, 9600, 19200,
8103 + 38400, 57600, 115200, 230400, 460800, 0 };
8104 +
8105 +static int tty_get_baud_rate(struct tty_struct *tty)
8106 +{
8107 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8108 + unsigned int cflag, i;
8109 +
8110 + cflag = tty->termios->c_cflag;
8111 +
8112 + i = cflag & CBAUD;
8113 + if (i & CBAUDEX) {
8114 + i &= ~CBAUDEX;
8115 + if (i < 1 || i > 2)
8116 + tty->termios->c_cflag &= ~CBAUDEX;
8117 + else
8118 + i += 15;
8119 + }
8120 + if (i == 15) {
8121 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
8122 + i += 1;
8123 + if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
8124 + i += 2;
8125 + }
8126 + return baud_table[i];
8127 +}
8128 +#endif
8129 +
8130 +/*
8131 + * This routine is called to set the UART divisor registers to match
8132 + * the specified baud rate for a serial port.
8133 + */
8134 +static void change_speed(struct async_struct *info,
8135 + struct termios *old_termios)
8136 +{
8137 + int quot = 0, baud_base, baud;
8138 + unsigned cflag, cval, fcr = 0;
8139 + int bits;
8140 + unsigned long flags;
8141 +
8142 + if (!info->tty || !info->tty->termios)
8143 + return;
8144 + cflag = info->tty->termios->c_cflag;
8145 + if (!CONFIGURED_SERIAL_PORT(info))
8146 + return;
8147 +
8148 + /* byte size and parity */
8149 + switch (cflag & CSIZE) {
8150 + case CS5: cval = 0x00; bits = 7; break;
8151 + case CS6: cval = 0x01; bits = 8; break;
8152 + case CS7: cval = 0x02; bits = 9; break;
8153 + case CS8: cval = 0x03; bits = 10; break;
8154 + /* Never happens, but GCC is too dumb to figure it out */
8155 + default: cval = 0x00; bits = 7; break;
8156 + }
8157 + if (cflag & CSTOPB) {
8158 + cval |= 0x04;
8159 + bits++;
8160 + }
8161 + if (cflag & PARENB) {
8162 + cval |= UART_LCR_PARITY;
8163 + bits++;
8164 + }
8165 + if (!(cflag & PARODD))
8166 + cval |= UART_LCR_EPAR;
8167 +#ifdef CMSPAR
8168 + if (cflag & CMSPAR)
8169 + cval |= UART_LCR_SPAR;
8170 +#endif
8171 +
8172 + /* Determine divisor based on baud rate */
8173 + baud = tty_get_baud_rate(info->tty);
8174 + if (!baud)
8175 + baud = 9600; /* B0 transition handled in rs_set_termios */
8176 +#ifdef CONFIG_SERIAL_RSA
8177 + if ((info->state->type == PORT_RSA) &&
8178 + (info->state->baud_base != SERIAL_RSA_BAUD_BASE) &&
8179 + enable_rsa(info))
8180 + info->state->baud_base = SERIAL_RSA_BAUD_BASE;
8181 +#endif
8182 + baud_base = info->state->baud_base;
8183 + if (info->state->type == PORT_16C950) {
8184 + if (baud <= baud_base)
8185 + serial_icr_write(info, UART_TCR, 0);
8186 + else if (baud <= 2*baud_base) {
8187 + serial_icr_write(info, UART_TCR, 0x8);
8188 + baud_base = baud_base * 2;
8189 + } else if (baud <= 4*baud_base) {
8190 + serial_icr_write(info, UART_TCR, 0x4);
8191 + baud_base = baud_base * 4;
8192 + } else
8193 + serial_icr_write(info, UART_TCR, 0);
8194 + }
8195 + if (baud == 38400 &&
8196 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
8197 + quot = info->state->custom_divisor;
8198 + else {
8199 + if (baud == 134)
8200 + /* Special case since 134 is really 134.5 */
8201 + quot = (2*baud_base / 269);
8202 + else if (baud)
8203 + quot = baud_base / baud;
8204 + }
8205 + /* If the quotient is zero refuse the change */
8206 + if (!quot && old_termios) {
8207 + info->tty->termios->c_cflag &= ~CBAUD;
8208 + info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD);
8209 + baud = tty_get_baud_rate(info->tty);
8210 + if (!baud)
8211 + baud = 9600;
8212 + if (baud == 38400 &&
8213 + ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST))
8214 + quot = info->state->custom_divisor;
8215 + else {
8216 + if (baud == 134)
8217 + /* Special case since 134 is really 134.5 */
8218 + quot = (2*baud_base / 269);
8219 + else if (baud)
8220 + quot = baud_base / baud;
8221 + }
8222 + }
8223 + /* As a last resort, if the quotient is zero, default to 9600 bps */
8224 + if (!quot)
8225 + quot = baud_base / 9600;
8226 + /*
8227 + * Work around a bug in the Oxford Semiconductor 952 rev B
8228 + * chip which causes it to seriously miscalculate baud rates
8229 + * when DLL is 0.
8230 + */
8231 + if (((quot & 0xFF) == 0) && (info->state->type == PORT_16C950) &&
8232 + (info->state->revision == 0x5201))
8233 + quot++;
8234 +
8235 + info->quot = quot;
8236 + info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base);
8237 + info->timeout += HZ/50; /* Add .02 seconds of slop */
8238 +
8239 + /* Set up FIFO's */
8240 + if (uart_config[info->state->type].flags & UART_USE_FIFO) {
8241 + if ((info->state->baud_base / quot) < 2400)
8242 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
8243 +#ifdef CONFIG_SERIAL_RSA
8244 + else if (info->state->type == PORT_RSA)
8245 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
8246 +#endif
8247 + else
8248 + fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
8249 + }
8250 + if (info->state->type == PORT_16750)
8251 + fcr |= UART_FCR7_64BYTE;
8252 +
8253 + /* CTS flow control flag and modem status interrupts */
8254 + info->IER &= ~UART_IER_MSI;
8255 + if (info->flags & ASYNC_HARDPPS_CD)
8256 + info->IER |= UART_IER_MSI;
8257 + if (cflag & CRTSCTS) {
8258 + info->flags |= ASYNC_CTS_FLOW;
8259 + info->IER |= UART_IER_MSI;
8260 + } else
8261 + info->flags &= ~ASYNC_CTS_FLOW;
8262 + if (cflag & CLOCAL)
8263 + info->flags &= ~ASYNC_CHECK_CD;
8264 + else {
8265 + info->flags |= ASYNC_CHECK_CD;
8266 + info->IER |= UART_IER_MSI;
8267 + }
8268 + serial_out(info, UART_IER, info->IER);
8269 +
8270 + /*
8271 + * Set up parity check flag
8272 + */
8273 +#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
8274 +
8275 + info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
8276 + if (I_INPCK(info->tty))
8277 + info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
8278 + if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
8279 + info->read_status_mask |= UART_LSR_BI;
8280 +
8281 + /*
8282 + * Characters to ignore
8283 + */
8284 + info->ignore_status_mask = 0;
8285 + if (I_IGNPAR(info->tty))
8286 + info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
8287 + if (I_IGNBRK(info->tty)) {
8288 + info->ignore_status_mask |= UART_LSR_BI;
8289 + /*
8290 + * If we're ignore parity and break indicators, ignore
8291 + * overruns too. (For real raw support).
8292 + */
8293 + if (I_IGNPAR(info->tty))
8294 + info->ignore_status_mask |= UART_LSR_OE;
8295 + }
8296 + /*
8297 + * !!! ignore all characters if CREAD is not set
8298 + */
8299 + if ((cflag & CREAD) == 0)
8300 + info->ignore_status_mask |= UART_LSR_DR;
8301 + save_flags(flags); cli();
8302 + if (uart_config[info->state->type].flags & UART_STARTECH) {
8303 + serial_outp(info, UART_LCR, 0xBF);
8304 + serial_outp(info, UART_EFR,
8305 + (cflag & CRTSCTS) ? UART_EFR_CTS : 0);
8306 + }
8307 + serial_outp(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
8308 + serial_outp(info, UART_DLL, quot & 0xff); /* LS of divisor */
8309 + serial_outp(info, UART_DLM, quot >> 8); /* MS of divisor */
8310 + if (info->state->type == PORT_16750)
8311 + serial_outp(info, UART_FCR, fcr); /* set fcr */
8312 + serial_outp(info, UART_LCR, cval); /* reset DLAB */
8313 + info->LCR = cval; /* Save LCR */
8314 + if (info->state->type != PORT_16750) {
8315 + if (fcr & UART_FCR_ENABLE_FIFO) {
8316 + /* emulated UARTs (Lucent Venus 167x) need two steps */
8317 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
8318 + }
8319 + serial_outp(info, UART_FCR, fcr); /* set fcr */
8320 + }
8321 + restore_flags(flags);
8322 +}
8323 +
8324 +static void rs_put_char(struct tty_struct *tty, unsigned char ch)
8325 +{
8326 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8327 + unsigned long flags;
8328 +
8329 + if (serial_paranoia_check(info, tty->device, "rs_put_char"))
8330 + return;
8331 +
8332 + if (!tty || !info->xmit.buf)
8333 + return;
8334 +
8335 + save_flags(flags); cli();
8336 + if (CIRC_SPACE(info->xmit.head,
8337 + info->xmit.tail,
8338 + SERIAL_XMIT_SIZE) == 0) {
8339 + restore_flags(flags);
8340 + return;
8341 + }
8342 +
8343 + info->xmit.buf[info->xmit.head] = ch;
8344 + info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
8345 + restore_flags(flags);
8346 +}
8347 +
8348 +static void rs_flush_chars(struct tty_struct *tty)
8349 +{
8350 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8351 + unsigned long flags;
8352 +
8353 + if (serial_paranoia_check(info, tty->device, "rs_flush_chars"))
8354 + return;
8355 +
8356 + if (info->xmit.head == info->xmit.tail
8357 + || tty->stopped
8358 + || tty->hw_stopped
8359 + || !info->xmit.buf)
8360 + return;
8361 +
8362 + save_flags(flags); cli();
8363 + info->IER |= UART_IER_THRI;
8364 + serial_out(info, UART_IER, info->IER);
8365 + restore_flags(flags);
8366 +}
8367 +
8368 +static int rs_write(struct tty_struct * tty, int from_user,
8369 + const unsigned char *buf, int count)
8370 +{
8371 + int c, ret = 0;
8372 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8373 + unsigned long flags;
8374 +
8375 + if (serial_paranoia_check(info, tty->device, "rs_write"))
8376 + return 0;
8377 +
8378 + if (!tty || !info->xmit.buf || !tmp_buf)
8379 + return 0;
8380 +
8381 + save_flags(flags);
8382 + if (from_user) {
8383 + down(&tmp_buf_sem);
8384 + while (1) {
8385 + int c1;
8386 + c = CIRC_SPACE_TO_END(info->xmit.head,
8387 + info->xmit.tail,
8388 + SERIAL_XMIT_SIZE);
8389 + if (count < c)
8390 + c = count;
8391 + if (c <= 0)
8392 + break;
8393 +
8394 + c -= copy_from_user(tmp_buf, buf, c);
8395 + if (!c) {
8396 + if (!ret)
8397 + ret = -EFAULT;
8398 + break;
8399 + }
8400 + cli();
8401 + c1 = CIRC_SPACE_TO_END(info->xmit.head,
8402 + info->xmit.tail,
8403 + SERIAL_XMIT_SIZE);
8404 + if (c1 < c)
8405 + c = c1;
8406 + memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c);
8407 + info->xmit.head = ((info->xmit.head + c) &
8408 + (SERIAL_XMIT_SIZE-1));
8409 + restore_flags(flags);
8410 + buf += c;
8411 + count -= c;
8412 + ret += c;
8413 + }
8414 + up(&tmp_buf_sem);
8415 + } else {
8416 + cli();
8417 + while (1) {
8418 + c = CIRC_SPACE_TO_END(info->xmit.head,
8419 + info->xmit.tail,
8420 + SERIAL_XMIT_SIZE);
8421 + if (count < c)
8422 + c = count;
8423 + if (c <= 0) {
8424 + break;
8425 + }
8426 + memcpy(info->xmit.buf + info->xmit.head, buf, c);
8427 + info->xmit.head = ((info->xmit.head + c) &
8428 + (SERIAL_XMIT_SIZE-1));
8429 + buf += c;
8430 + count -= c;
8431 + ret += c;
8432 + }
8433 + restore_flags(flags);
8434 + }
8435 + if (info->xmit.head != info->xmit.tail
8436 + && !tty->stopped
8437 + && !tty->hw_stopped
8438 + && !(info->IER & UART_IER_THRI)) {
8439 + info->IER |= UART_IER_THRI;
8440 + serial_out(info, UART_IER, info->IER);
8441 + }
8442 + return ret;
8443 +}
8444 +
8445 +static int rs_write_room(struct tty_struct *tty)
8446 +{
8447 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8448 +
8449 + if (serial_paranoia_check(info, tty->device, "rs_write_room"))
8450 + return 0;
8451 + return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
8452 +}
8453 +
8454 +static int rs_chars_in_buffer(struct tty_struct *tty)
8455 +{
8456 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8457 +
8458 + if (serial_paranoia_check(info, tty->device, "rs_chars_in_buffer"))
8459 + return 0;
8460 + return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
8461 +}
8462 +
8463 +static void rs_flush_buffer(struct tty_struct *tty)
8464 +{
8465 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8466 + unsigned long flags;
8467 +
8468 + if (serial_paranoia_check(info, tty->device, "rs_flush_buffer"))
8469 + return;
8470 + save_flags(flags); cli();
8471 + info->xmit.head = info->xmit.tail = 0;
8472 + restore_flags(flags);
8473 +#ifdef SERIAL_HAVE_POLL_WAIT
8474 + wake_up_interruptible(&tty->poll_wait);
8475 +#endif
8476 + tty_wakeup(tty);
8477 +}
8478 +
8479 +/*
8480 + * This function is used to send a high-priority XON/XOFF character to
8481 + * the device
8482 + */
8483 +static void rs_send_xchar(struct tty_struct *tty, char ch)
8484 +{
8485 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8486 +
8487 + if (serial_paranoia_check(info, tty->device, "rs_send_char"))
8488 + return;
8489 +
8490 + info->x_char = ch;
8491 + if (ch) {
8492 + /* Make sure transmit interrupts are on */
8493 + info->IER |= UART_IER_THRI;
8494 + serial_out(info, UART_IER, info->IER);
8495 + }
8496 +}
8497 +
8498 +/*
8499 + * ------------------------------------------------------------
8500 + * rs_throttle()
8501 + *
8502 + * This routine is called by the upper-layer tty layer to signal that
8503 + * incoming characters should be throttled.
8504 + * ------------------------------------------------------------
8505 + */
8506 +static void rs_throttle(struct tty_struct * tty)
8507 +{
8508 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8509 + unsigned long flags;
8510 +#ifdef SERIAL_DEBUG_THROTTLE
8511 + char buf[64];
8512 +
8513 + printk("throttle %s: %d....\n", tty_name(tty, buf),
8514 + tty->ldisc.chars_in_buffer(tty));
8515 +#endif
8516 +
8517 + if (serial_paranoia_check(info, tty->device, "rs_throttle"))
8518 + return;
8519 +
8520 + if (I_IXOFF(tty))
8521 + rs_send_xchar(tty, STOP_CHAR(tty));
8522 +
8523 + if (tty->termios->c_cflag & CRTSCTS)
8524 + info->MCR &= ~UART_MCR_RTS;
8525 +
8526 + save_flags(flags); cli();
8527 + serial_out(info, UART_MCR, info->MCR);
8528 + restore_flags(flags);
8529 +}
8530 +
8531 +static void rs_unthrottle(struct tty_struct * tty)
8532 +{
8533 + struct async_struct *info = (struct async_struct *)tty->driver_data;
8534 + unsigned long flags;
8535 +#ifdef SERIAL_DEBUG_THROTTLE
8536 + char buf[64];
8537 +
8538 + printk("unthrottle %s: %d....\n", tty_name(tty, buf),
8539 + tty->ldisc.chars_in_buffer(tty));
8540 +#endif
8541 +
8542 + if (serial_paranoia_check(info, tty->device, "rs_unthrottle"))
8543 + return;
8544 +
8545 + if (I_IXOFF(tty)) {
8546 + if (info->x_char)
8547 + info->x_char = 0;
8548 + else
8549 + rs_send_xchar(tty, START_CHAR(tty));
8550 + }
8551 + if (tty->termios->c_cflag & CRTSCTS)
8552 + info->MCR |= UART_MCR_RTS;
8553 + save_flags(flags); cli();
8554 + serial_out(info, UART_MCR, info->MCR);
8555 + restore_flags(flags);
8556 +}
8557 +
8558 +/*
8559 + * ------------------------------------------------------------
8560 + * rs_ioctl() and friends
8561 + * ------------------------------------------------------------
8562 + */
8563 +
8564 +static int get_serial_info(struct async_struct * info,
8565 + struct serial_struct * retinfo)
8566 +{
8567 + struct serial_struct tmp;
8568 + struct serial_state *state = info->state;
8569 +
8570 + if (!retinfo)
8571 + return -EFAULT;
8572 + memset(&tmp, 0, sizeof(tmp));
8573 + tmp.type = state->type;
8574 + tmp.line = state->line;
8575 + tmp.port = state->port;
8576 + if (HIGH_BITS_OFFSET)
8577 + tmp.port_high = state->port >> HIGH_BITS_OFFSET;
8578 + else
8579 + tmp.port_high = 0;
8580 + tmp.irq = state->irq;
8581 + tmp.flags = state->flags;
8582 + tmp.xmit_fifo_size = state->xmit_fifo_size;
8583 + tmp.baud_base = state->baud_base;
8584 + tmp.close_delay = state->close_delay;
8585 + tmp.closing_wait = state->closing_wait;
8586 + tmp.custom_divisor = state->custom_divisor;
8587 + tmp.hub6 = state->hub6;
8588 + tmp.io_type = state->io_type;
8589 + if (copy_to_user(retinfo,&tmp,sizeof(*retinfo)))
8590 + return -EFAULT;
8591 + return 0;
8592 +}
8593 +
8594 +static int set_serial_info(struct async_struct * info,
8595 + struct serial_struct * new_info)
8596 +{
8597 + struct serial_struct new_serial;
8598 + struct serial_state old_state, *state;
8599 + unsigned int i,change_irq,change_port;
8600 + int retval = 0;
8601 + unsigned long new_port;
8602 +
8603 + if (copy_from_user(&new_serial,new_info,sizeof(new_serial)))
8604 + return -EFAULT;
8605 + state = info->state;
8606 + old_state = *state;
8607 +
8608 + new_port = new_serial.port;
8609 + if (HIGH_BITS_OFFSET)
8610 + new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET;
8611 +
8612 + change_irq = new_serial.irq != state->irq;
8613 + change_port = (new_port != ((int) state->port)) ||
8614 + (new_serial.hub6 != state->hub6);
8615 +
8616 + if (!capable(CAP_SYS_ADMIN)) {
8617 + if (change_irq || change_port ||
8618 + (new_serial.baud_base != state->baud_base) ||
8619 + (new_serial.type != state->type) ||
8620 + (new_serial.close_delay != state->close_delay) ||
8621 + (new_serial.xmit_fifo_size != state->xmit_fifo_size) ||
8622 + ((new_serial.flags & ~ASYNC_USR_MASK) !=
8623 + (state->flags & ~ASYNC_USR_MASK)))
8624 + return -EPERM;
8625 + state->flags = ((state->flags & ~ASYNC_USR_MASK) |
8626 + (new_serial.flags & ASYNC_USR_MASK));
8627 + info->flags = ((info->flags & ~ASYNC_USR_MASK) |
8628 + (new_serial.flags & ASYNC_USR_MASK));
8629 + state->custom_divisor = new_serial.custom_divisor;
8630 + goto check_and_exit;
8631 + }
8632 +
8633 + new_serial.irq = irq_cannonicalize(new_serial.irq);
8634 +
8635 + if ((new_serial.irq >= NR_IRQS) || (new_serial.irq < 0) ||
8636 + (new_serial.baud_base < 9600)|| (new_serial.type < PORT_UNKNOWN) ||
8637 + (new_serial.type > PORT_MAX) || (new_serial.type == PORT_CIRRUS) ||
8638 + (new_serial.type == PORT_STARTECH)) {
8639 + return -EINVAL;
8640 + }
8641 +
8642 + if ((new_serial.type != state->type) ||
8643 + (new_serial.xmit_fifo_size <= 0))
8644 + new_serial.xmit_fifo_size =
8645 + uart_config[new_serial.type].dfl_xmit_fifo_size;
8646 +
8647 + /* Make sure address is not already in use */
8648 + if (new_serial.type) {
8649 + for (i = 0 ; i < NR_PORTS; i++)
8650 + if ((state != &rs_table[i]) &&
8651 + (rs_table[i].io_type == SERIAL_IO_PORT) &&
8652 + (rs_table[i].port == new_port) &&
8653 + rs_table[i].type)
8654 + return -EADDRINUSE;
8655 + }
8656 +
8657 + if ((change_port || change_irq) && (state->count > 1))
8658 + return -EBUSY;
8659 +
8660 + /*
8661 + * OK, past this point, all the error checking has been done.
8662 + * At this point, we start making changes.....
8663 + */
8664 +
8665 + state->baud_base = new_serial.baud_base;
8666 + state->flags = ((state->flags & ~ASYNC_FLAGS) |
8667 + (new_serial.flags & ASYNC_FLAGS));
8668 + info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) |
8669 + (info->flags & ASYNC_INTERNAL_FLAGS));
8670 + state->custom_divisor = new_serial.custom_divisor;
8671 + state->close_delay = new_serial.close_delay * HZ/100;
8672 + state->closing_wait = new_serial.closing_wait * HZ/100;
8673 +#if (LINUX_VERSION_CODE > 0x20100)
8674 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
8675 +#endif
8676 + info->xmit_fifo_size = state->xmit_fifo_size =
8677 + new_serial.xmit_fifo_size;
8678 +
8679 + if ((state->type != PORT_UNKNOWN) && state->port) {
8680 +#ifdef CONFIG_SERIAL_RSA
8681 + if (old_state.type == PORT_RSA)
8682 + release_region(state->port + UART_RSA_BASE, 16);
8683 + else
8684 +#endif
8685 + release_region(state->port,8);
8686 + }
8687 + state->type = new_serial.type;
8688 + if (change_port || change_irq) {
8689 + /*
8690 + * We need to shutdown the serial port at the old
8691 + * port/irq combination.
8692 + */
8693 + shutdown(info);
8694 + state->irq = new_serial.irq;
8695 + info->port = state->port = new_port;
8696 + info->hub6 = state->hub6 = new_serial.hub6;
8697 + if (info->hub6)
8698 + info->io_type = state->io_type = SERIAL_IO_HUB6;
8699 + else if (info->io_type == SERIAL_IO_HUB6)
8700 + info->io_type = state->io_type = SERIAL_IO_PORT;
8701 + }
8702 + if ((state->type != PORT_UNKNOWN) && state->port) {
8703 +#ifdef CONFIG_SERIAL_RSA
8704 + if (state->type == PORT_RSA)
8705 + request_region(state->port + UART_RSA_BASE,
8706 + 16, "serial_rsa(set)");
8707 + else
8708 +#endif
8709 + request_region(state->port,8,"serial(set)");
8710 + }
8711 +
8712 +
8713 +check_and_exit:
8714 + if ((!state->port && !state->iomem_base) || !state->type)
8715 + return 0;
8716 + if (info->flags & ASYNC_INITIALIZED) {
8717 + if (((old_state.flags & ASYNC_SPD_MASK) !=
8718 + (state->flags & ASYNC_SPD_MASK)) ||
8719 + (old_state.custom_divisor != state->custom_divisor)) {
8720 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
8721 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
8722 + info->tty->alt_speed = 57600;
8723 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
8724 + info->tty->alt_speed = 115200;
8725 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
8726 + info->tty->alt_speed = 230400;
8727 + if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
8728 + info->tty->alt_speed = 460800;
8729 +#endif
8730 + change_speed(info, 0);
8731 + }
8732 + } else
8733 + retval = startup(info);
8734 + return retval;
8735 +}
8736 +
8737 +
8738 +/*
8739 + * get_lsr_info - get line status register info
8740 + *
8741 + * Purpose: Let user call ioctl() to get info when the UART physically
8742 + * is emptied. On bus types like RS485, the transmitter must
8743 + * release the bus after transmitting. This must be done when
8744 + * the transmit shift register is empty, not be done when the
8745 + * transmit holding register is empty. This functionality
8746 + * allows an RS485 driver to be written in user space.
8747 + */
8748 +static int get_lsr_info(struct async_struct * info, unsigned int *value)
8749 +{
8750 + unsigned char status;
8751 + unsigned int result;
8752 + unsigned long flags;
8753 +
8754 + save_flags(flags); cli();
8755 + status = serial_in(info, UART_LSR);
8756 + restore_flags(flags);
8757 + result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
8758 +
8759 + /*
8760 + * If we're about to load something into the transmit
8761 + * register, we'll pretend the transmitter isn't empty to
8762 + * avoid a race condition (depending on when the transmit
8763 + * interrupt happens).
8764 + */
8765 + if (info->x_char ||
8766 + ((CIRC_CNT(info->xmit.head, info->xmit.tail,
8767 + SERIAL_XMIT_SIZE) > 0) &&
8768 + !info->tty->stopped && !info->tty->hw_stopped))
8769 + result &= ~TIOCSER_TEMT;
8770 +
8771 + if (copy_to_user(value, &result, sizeof(int)))
8772 + return -EFAULT;
8773 + return 0;
8774 +}
8775 +
8776 +
8777 +static int get_modem_info(struct async_struct * info, unsigned int *value)
8778 +{
8779 + unsigned char control, status;
8780 + unsigned int result;
8781 + unsigned long flags;
8782 +
8783 + control = info->MCR;
8784 + save_flags(flags); cli();
8785 + status = serial_in(info, UART_MSR);
8786 + restore_flags(flags);
8787 + result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
8788 + | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
8789 +#ifdef TIOCM_OUT1
8790 + | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
8791 + | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
8792 +#endif
8793 + | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0)
8794 + | ((status & UART_MSR_RI) ? TIOCM_RNG : 0)
8795 + | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0)
8796 + | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
8797 +
8798 + if (copy_to_user(value, &result, sizeof(int)))
8799 + return -EFAULT;
8800 + return 0;
8801 +}
8802 +
8803 +static int set_modem_info(struct async_struct * info, unsigned int cmd,
8804 + unsigned int *value)
8805 +{
8806 + unsigned int arg;
8807 + unsigned long flags;
8808 +
8809 + if (copy_from_user(&arg, value, sizeof(int)))
8810 + return -EFAULT;
8811 +
8812 + switch (cmd) {
8813 + case TIOCMBIS:
8814 + if (arg & TIOCM_RTS)
8815 + info->MCR |= UART_MCR_RTS;
8816 + if (arg & TIOCM_DTR)
8817 + info->MCR |= UART_MCR_DTR;
8818 +#ifdef TIOCM_OUT1
8819 + if (arg & TIOCM_OUT1)
8820 + info->MCR |= UART_MCR_OUT1;
8821 + if (arg & TIOCM_OUT2)
8822 + info->MCR |= UART_MCR_OUT2;
8823 +#endif
8824 + if (arg & TIOCM_LOOP)
8825 + info->MCR |= UART_MCR_LOOP;
8826 + break;
8827 + case TIOCMBIC:
8828 + if (arg & TIOCM_RTS)
8829 + info->MCR &= ~UART_MCR_RTS;
8830 + if (arg & TIOCM_DTR)
8831 + info->MCR &= ~UART_MCR_DTR;
8832 +#ifdef TIOCM_OUT1
8833 + if (arg & TIOCM_OUT1)
8834 + info->MCR &= ~UART_MCR_OUT1;
8835 + if (arg & TIOCM_OUT2)
8836 + info->MCR &= ~UART_MCR_OUT2;
8837 +#endif
8838 + if (arg & TIOCM_LOOP)
8839 + info->MCR &= ~UART_MCR_LOOP;
8840 + break;
8841 + case TIOCMSET:
8842 + info->MCR = ((info->MCR & ~(UART_MCR_RTS |
8843 +#ifdef TIOCM_OUT1
8844 + UART_MCR_OUT1 |
8845 + UART_MCR_OUT2 |
8846 +#endif
8847 + UART_MCR_LOOP |
8848 + UART_MCR_DTR))
8849 + | ((arg & TIOCM_RTS) ? UART_MCR_RTS : 0)
8850 +#ifdef TIOCM_OUT1
8851 + | ((arg & TIOCM_OUT1) ? UART_MCR_OUT1 : 0)
8852 + | ((arg & TIOCM_OUT2) ? UART_MCR_OUT2 : 0)
8853 +#endif
8854 + | ((arg & TIOCM_LOOP) ? UART_MCR_LOOP : 0)
8855 + | ((arg & TIOCM_DTR) ? UART_MCR_DTR : 0));
8856 + break;
8857 + default:
8858 + return -EINVAL;
8859 + }
8860 + save_flags(flags); cli();
8861 + info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */
8862 + serial_out(info, UART_MCR, info->MCR);
8863 + restore_flags(flags);
8864 + return 0;
8865 +}
8866 +
8867 +static int do_autoconfig(struct async_struct * info)
8868 +{
8869 + int irq, retval;
8870 +
8871 + if (!capable(CAP_SYS_ADMIN))
8872 + return -EPERM;
8873 +
8874 + if (info->state->count > 1)
8875 + return -EBUSY;
8876 +
8877 + shutdown(info);
8878 +
8879 + autoconfig(info->state);
8880 + if ((info->state->flags & ASYNC_AUTO_IRQ) &&
8881 + (info->state->port != 0 || info->state->iomem_base != 0) &&
8882 + (info->state->type != PORT_UNKNOWN)) {
8883 + irq = detect_uart_irq(info->state);
8884 + if (irq > 0)
8885 + info->state->irq = irq;
8886 + }
8887 +
8888 + retval = startup(info);
8889 + if (retval)
8890 + return retval;
8891 + return 0;
8892 +}
8893 +
8894 +/*
8895 + * rs_break() --- routine which turns the break handling on or off
8896 + */
8897 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
8898 +static void send_break( struct async_struct * info, int duration)
8899 +{
8900 + if (!CONFIGURED_SERIAL_PORT(info))
8901 + return;
8902 + current->state = TASK_INTERRUPTIBLE;
8903 + current->timeout = jiffies + duration;
8904 + cli();
8905 + info->LCR |= UART_LCR_SBC;
8906 + serial_out(info, UART_LCR, info->LCR);
8907 + schedule();
8908 + info->LCR &= ~UART_LCR_SBC;
8909 + serial_out(info, UART_LCR, info->LCR);
8910 + sti();
8911 +}
8912 +#else
8913 +static void rs_break(struct tty_struct *tty, int break_state)
8914 +{
8915 + struct async_struct * info = (struct async_struct *)tty->driver_data;
8916 + unsigned long flags;
8917 +
8918 + if (serial_paranoia_check(info, tty->device, "rs_break"))
8919 + return;
8920 +
8921 + if (!CONFIGURED_SERIAL_PORT(info))
8922 + return;
8923 + save_flags(flags); cli();
8924 + if (break_state == -1)
8925 + info->LCR |= UART_LCR_SBC;
8926 + else
8927 + info->LCR &= ~UART_LCR_SBC;
8928 + serial_out(info, UART_LCR, info->LCR);
8929 + restore_flags(flags);
8930 +}
8931 +#endif
8932 +
8933 +#ifdef CONFIG_SERIAL_MULTIPORT
8934 +static int get_multiport_struct(struct async_struct * info,
8935 + struct serial_multiport_struct *retinfo)
8936 +{
8937 + struct serial_multiport_struct ret;
8938 + struct rs_multiport_struct *multi;
8939 +
8940 + multi = &rs_multiport[info->state->irq];
8941 +
8942 + ret.port_monitor = multi->port_monitor;
8943 +
8944 + ret.port1 = multi->port1;
8945 + ret.mask1 = multi->mask1;
8946 + ret.match1 = multi->match1;
8947 +
8948 + ret.port2 = multi->port2;
8949 + ret.mask2 = multi->mask2;
8950 + ret.match2 = multi->match2;
8951 +
8952 + ret.port3 = multi->port3;
8953 + ret.mask3 = multi->mask3;
8954 + ret.match3 = multi->match3;
8955 +
8956 + ret.port4 = multi->port4;
8957 + ret.mask4 = multi->mask4;
8958 + ret.match4 = multi->match4;
8959 +
8960 + ret.irq = info->state->irq;
8961 +
8962 + if (copy_to_user(retinfo,&ret,sizeof(*retinfo)))
8963 + return -EFAULT;
8964 + return 0;
8965 +}
8966 +
8967 +static int set_multiport_struct(struct async_struct * info,
8968 + struct serial_multiport_struct *in_multi)
8969 +{
8970 + struct serial_multiport_struct new_multi;
8971 + struct rs_multiport_struct *multi;
8972 + struct serial_state *state;
8973 + int was_multi, now_multi;
8974 + int retval;
8975 + void (*handler)(int, void *, struct pt_regs *);
8976 +
8977 + if (!capable(CAP_SYS_ADMIN))
8978 + return -EPERM;
8979 + state = info->state;
8980 +
8981 + if (copy_from_user(&new_multi, in_multi,
8982 + sizeof(struct serial_multiport_struct)))
8983 + return -EFAULT;
8984 +
8985 + if (new_multi.irq != state->irq || state->irq == 0 ||
8986 + !IRQ_ports[state->irq])
8987 + return -EINVAL;
8988 +
8989 + multi = &rs_multiport[state->irq];
8990 + was_multi = (multi->port1 != 0);
8991 +
8992 + multi->port_monitor = new_multi.port_monitor;
8993 +
8994 + if (multi->port1)
8995 + release_region(multi->port1,1);
8996 + multi->port1 = new_multi.port1;
8997 + multi->mask1 = new_multi.mask1;
8998 + multi->match1 = new_multi.match1;
8999 + if (multi->port1)
9000 + request_region(multi->port1,1,"serial(multiport1)");
9001 +
9002 + if (multi->port2)
9003 + release_region(multi->port2,1);
9004 + multi->port2 = new_multi.port2;
9005 + multi->mask2 = new_multi.mask2;
9006 + multi->match2 = new_multi.match2;
9007 + if (multi->port2)
9008 + request_region(multi->port2,1,"serial(multiport2)");
9009 +
9010 + if (multi->port3)
9011 + release_region(multi->port3,1);
9012 + multi->port3 = new_multi.port3;
9013 + multi->mask3 = new_multi.mask3;
9014 + multi->match3 = new_multi.match3;
9015 + if (multi->port3)
9016 + request_region(multi->port3,1,"serial(multiport3)");
9017 +
9018 + if (multi->port4)
9019 + release_region(multi->port4,1);
9020 + multi->port4 = new_multi.port4;
9021 + multi->mask4 = new_multi.mask4;
9022 + multi->match4 = new_multi.match4;
9023 + if (multi->port4)
9024 + request_region(multi->port4,1,"serial(multiport4)");
9025 +
9026 + now_multi = (multi->port1 != 0);
9027 +
9028 + if (IRQ_ports[state->irq]->next_port &&
9029 + (was_multi != now_multi)) {
9030 + free_irq(state->irq, &IRQ_ports[state->irq]);
9031 + if (now_multi)
9032 + handler = rs_interrupt_multi;
9033 + else
9034 + handler = rs_interrupt;
9035 +
9036 + retval = request_irq(state->irq, handler, SA_SHIRQ,
9037 + "serial", &IRQ_ports[state->irq]);
9038 + if (retval) {
9039 + printk("Couldn't reallocate serial interrupt "
9040 + "driver!!\n");
9041 + }
9042 + }
9043 + return 0;
9044 +}
9045 +#endif
9046 +
9047 +static int rs_ioctl(struct tty_struct *tty, struct file * file,
9048 + unsigned int cmd, unsigned long arg)
9049 +{
9050 + struct async_struct * info = (struct async_struct *)tty->driver_data;
9051 + struct async_icount cprev, cnow; /* kernel counter temps */
9052 + struct serial_icounter_struct icount;
9053 + unsigned long flags;
9054 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
9055 + int retval, tmp;
9056 +#endif
9057 +
9058 + if (serial_paranoia_check(info, tty->device, "rs_ioctl"))
9059 + return -ENODEV;
9060 +
9061 + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
9062 + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) &&
9063 + (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
9064 + if (tty->flags & (1 << TTY_IO_ERROR))
9065 + return -EIO;
9066 + }
9067 +
9068 + switch (cmd) {
9069 +#if (LINUX_VERSION_CODE < 131394) /* Linux 2.1.66 */
9070 + case TCSBRK: /* SVID version: non-zero arg --> no break */
9071 + retval = tty_check_change(tty);
9072 + if (retval)
9073 + return retval;
9074 + tty_wait_until_sent(tty, 0);
9075 + if (signal_pending(current))
9076 + return -EINTR;
9077 + if (!arg) {
9078 + send_break(info, HZ/4); /* 1/4 second */
9079 + if (signal_pending(current))
9080 + return -EINTR;
9081 + }
9082 + return 0;
9083 + case TCSBRKP: /* support for POSIX tcsendbreak() */
9084 + retval = tty_check_change(tty);
9085 + if (retval)
9086 + return retval;
9087 + tty_wait_until_sent(tty, 0);
9088 + if (signal_pending(current))
9089 + return -EINTR;
9090 + send_break(info, arg ? arg*(HZ/10) : HZ/4);
9091 + if (signal_pending(current))
9092 + return -EINTR;
9093 + return 0;
9094 + case TIOCGSOFTCAR:
9095 + tmp = C_CLOCAL(tty) ? 1 : 0;
9096 + if (copy_to_user((void *)arg, &tmp, sizeof(int)))
9097 + return -EFAULT;
9098 + return 0;
9099 + case TIOCSSOFTCAR:
9100 + if (copy_from_user(&tmp, (void *)arg, sizeof(int)))
9101 + return -EFAULT;
9102 +
9103 + tty->termios->c_cflag =
9104 + ((tty->termios->c_cflag & ~CLOCAL) |
9105 + (tmp ? CLOCAL : 0));
9106 + return 0;
9107 +#endif
9108 + case TIOCMGET:
9109 + return get_modem_info(info, (unsigned int *) arg);
9110 + case TIOCMBIS:
9111 + case TIOCMBIC:
9112 + case TIOCMSET:
9113 + return set_modem_info(info, cmd, (unsigned int *) arg);
9114 + case TIOCGSERIAL:
9115 + return get_serial_info(info,
9116 + (struct serial_struct *) arg);
9117 + case TIOCSSERIAL:
9118 + return set_serial_info(info,
9119 + (struct serial_struct *) arg);
9120 + case TIOCSERCONFIG:
9121 + return do_autoconfig(info);
9122 +
9123 + case TIOCSERGETLSR: /* Get line status register */
9124 + return get_lsr_info(info, (unsigned int *) arg);
9125 +
9126 + case TIOCSERGSTRUCT:
9127 + if (copy_to_user((struct async_struct *) arg,
9128 + info, sizeof(struct async_struct)))
9129 + return -EFAULT;
9130 + return 0;
9131 +
9132 +#ifdef CONFIG_SERIAL_MULTIPORT
9133 + case TIOCSERGETMULTI:
9134 + return get_multiport_struct(info,
9135 + (struct serial_multiport_struct *) arg);
9136 + case TIOCSERSETMULTI:
9137 + return set_multiport_struct(info,
9138 + (struct serial_multiport_struct *) arg);
9139 +#endif
9140 +
9141 + /*
9142 + * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
9143 + * - mask passed in arg for lines of interest
9144 + * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
9145 + * Caller should use TIOCGICOUNT to see which one it was
9146 + */
9147 + case TIOCMIWAIT:
9148 + save_flags(flags); cli();
9149 + /* note the counters on entry */
9150 + cprev = info->state->icount;
9151 + restore_flags(flags);
9152 + /* Force modem status interrupts on */
9153 + info->IER |= UART_IER_MSI;
9154 + serial_out(info, UART_IER, info->IER);
9155 + while (1) {
9156 + interruptible_sleep_on(&info->delta_msr_wait);
9157 + /* see if a signal did it */
9158 + if (signal_pending(current))
9159 + return -ERESTARTSYS;
9160 + save_flags(flags); cli();
9161 + cnow = info->state->icount; /* atomic copy */
9162 + restore_flags(flags);
9163 + if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
9164 + cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
9165 + return -EIO; /* no change => error */
9166 + if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
9167 + ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
9168 + ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
9169 + ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
9170 + return 0;
9171 + }
9172 + cprev = cnow;
9173 + }
9174 + /* NOTREACHED */
9175 +
9176 + /*
9177 + * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
9178 + * Return: write counters to the user passed counter struct
9179 + * NB: both 1->0 and 0->1 transitions are counted except for
9180 + * RI where only 0->1 is counted.
9181 + */
9182 + case TIOCGICOUNT:
9183 + save_flags(flags); cli();
9184 + cnow = info->state->icount;
9185 + restore_flags(flags);
9186 + icount.cts = cnow.cts;
9187 + icount.dsr = cnow.dsr;
9188 + icount.rng = cnow.rng;
9189 + icount.dcd = cnow.dcd;
9190 + icount.rx = cnow.rx;
9191 + icount.tx = cnow.tx;
9192 + icount.frame = cnow.frame;
9193 + icount.overrun = cnow.overrun;
9194 + icount.parity = cnow.parity;
9195 + icount.brk = cnow.brk;
9196 + icount.buf_overrun = cnow.buf_overrun;
9197 +
9198 + if (copy_to_user((void *)arg, &icount, sizeof(icount)))
9199 + return -EFAULT;
9200 + return 0;
9201 + case TIOCSERGWILD:
9202 + case TIOCSERSWILD:
9203 + /* "setserial -W" is called in Debian boot */
9204 + printk ("TIOCSER?WILD ioctl obsolete, ignored.\n");
9205 + return 0;
9206 +
9207 + default:
9208 + return -ENOIOCTLCMD;
9209 + }
9210 + return 0;
9211 +}
9212 +
9213 +static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios)
9214 +{
9215 + struct async_struct *info = (struct async_struct *)tty->driver_data;
9216 + unsigned long flags;
9217 + unsigned int cflag = tty->termios->c_cflag;
9218 +
9219 + if ( (cflag == old_termios->c_cflag)
9220 + && ( RELEVANT_IFLAG(tty->termios->c_iflag)
9221 + == RELEVANT_IFLAG(old_termios->c_iflag)))
9222 + return;
9223 +
9224 + change_speed(info, old_termios);
9225 +
9226 + /* Handle transition to B0 status */
9227 + if ((old_termios->c_cflag & CBAUD) &&
9228 + !(cflag & CBAUD)) {
9229 + info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
9230 + save_flags(flags); cli();
9231 + serial_out(info, UART_MCR, info->MCR);
9232 + restore_flags(flags);
9233 + }
9234 +
9235 + /* Handle transition away from B0 status */
9236 + if (!(old_termios->c_cflag & CBAUD) &&
9237 + (cflag & CBAUD)) {
9238 + info->MCR |= UART_MCR_DTR;
9239 + if (!(tty->termios->c_cflag & CRTSCTS) ||
9240 + !test_bit(TTY_THROTTLED, &tty->flags)) {
9241 + info->MCR |= UART_MCR_RTS;
9242 + }
9243 + save_flags(flags); cli();
9244 + serial_out(info, UART_MCR, info->MCR);
9245 + restore_flags(flags);
9246 + }
9247 +
9248 + /* Handle turning off CRTSCTS */
9249 + if ((old_termios->c_cflag & CRTSCTS) &&
9250 + !(tty->termios->c_cflag & CRTSCTS)) {
9251 + tty->hw_stopped = 0;
9252 + rs_start(tty);
9253 + }
9254 +
9255 +#if 0
9256 + /*
9257 + * No need to wake up processes in open wait, since they
9258 + * sample the CLOCAL flag once, and don't recheck it.
9259 + * XXX It's not clear whether the current behavior is correct
9260 + * or not. Hence, this may change.....
9261 + */
9262 + if (!(old_termios->c_cflag & CLOCAL) &&
9263 + (tty->termios->c_cflag & CLOCAL))
9264 + wake_up_interruptible(&info->open_wait);
9265 +#endif
9266 +}
9267 +
9268 +/*
9269 + * ------------------------------------------------------------
9270 + * rs_close()
9271 + *
9272 + * This routine is called when the serial port gets closed. First, we
9273 + * wait for the last remaining data to be sent. Then, we unlink its
9274 + * async structure from the interrupt chain if necessary, and we free
9275 + * that IRQ if nothing is left in the chain.
9276 + * ------------------------------------------------------------
9277 + */
9278 +static void rs_close(struct tty_struct *tty, struct file * filp)
9279 +{
9280 + struct async_struct * info = (struct async_struct *)tty->driver_data;
9281 + struct serial_state *state;
9282 + unsigned long flags;
9283 +
9284 + if (!info || serial_paranoia_check(info, tty->device, "rs_close"))
9285 + return;
9286 +
9287 + state = info->state;
9288 +
9289 + save_flags(flags); cli();
9290 +
9291 + if (tty_hung_up_p(filp)) {
9292 + DBG_CNT("before DEC-hung");
9293 + MOD_DEC_USE_COUNT;
9294 + restore_flags(flags);
9295 + return;
9296 + }
9297 +
9298 +#ifdef SERIAL_DEBUG_OPEN
9299 + printk("rs_close ttys%d, count = %d\n", info->line, state->count);
9300 +#endif
9301 + if ((tty->count == 1) && (state->count != 1)) {
9302 + /*
9303 + * Uh, oh. tty->count is 1, which means that the tty
9304 + * structure will be freed. state->count should always
9305 + * be one in these conditions. If it's greater than
9306 + * one, we've got real problems, since it means the
9307 + * serial port won't be shutdown.
9308 + */
9309 + printk("rs_close: bad serial port count; tty->count is 1, "
9310 + "state->count is %d\n", state->count);
9311 + state->count = 1;
9312 + }
9313 + if (--state->count < 0) {
9314 + printk("rs_close: bad serial port count for ttys%d: %d\n",
9315 + info->line, state->count);
9316 + state->count = 0;
9317 + }
9318 + if (state->count) {
9319 + DBG_CNT("before DEC-2");
9320 + MOD_DEC_USE_COUNT;
9321 + restore_flags(flags);
9322 + return;
9323 + }
9324 + info->flags |= ASYNC_CLOSING;
9325 + restore_flags(flags);
9326 + /*
9327 + * Save the termios structure, since this port may have
9328 + * separate termios for callout and dialin.
9329 + */
9330 + if (info->flags & ASYNC_NORMAL_ACTIVE)
9331 + info->state->normal_termios = *tty->termios;
9332 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
9333 + info->state->callout_termios = *tty->termios;
9334 + /*
9335 + * Now we wait for the transmit buffer to clear; and we notify
9336 + * the line discipline to only process XON/XOFF characters.
9337 + */
9338 + tty->closing = 1;
9339 + if (state->closing_wait != ASYNC_CLOSING_WAIT_NONE)
9340 + tty_wait_until_sent(tty, state->closing_wait);
9341 + /*
9342 + * At this point we stop accepting input. To do this, we
9343 + * disable the receive line status interrupts, and tell the
9344 + * interrupt driver to stop checking the data ready bit in the
9345 + * line status register.
9346 + */
9347 + info->IER &= ~UART_IER_RLSI;
9348 + info->read_status_mask &= ~UART_LSR_DR;
9349 + if (info->flags & ASYNC_INITIALIZED) {
9350 + serial_out(info, UART_IER, info->IER);
9351 + /*
9352 + * Before we drop DTR, make sure the UART transmitter
9353 + * has completely drained; this is especially
9354 + * important if there is a transmit FIFO!
9355 + */
9356 + rs_wait_until_sent(tty, info->timeout);
9357 + }
9358 + shutdown(info);
9359 + if (tty->driver.flush_buffer)
9360 + tty->driver.flush_buffer(tty);
9361 + tty_ldisc_flush(tty);
9362 + tty->closing = 0;
9363 + info->event = 0;
9364 + info->tty = 0;
9365 + if (info->blocked_open) {
9366 + if (state->close_delay) {
9367 + set_current_state(TASK_INTERRUPTIBLE);
9368 + schedule_timeout(state->close_delay);
9369 + }
9370 + wake_up_interruptible(&info->open_wait);
9371 + }
9372 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
9373 + ASYNC_CLOSING);
9374 + wake_up_interruptible(&info->close_wait);
9375 + MOD_DEC_USE_COUNT;
9376 +}
9377 +
9378 +/*
9379 + * rs_wait_until_sent() --- wait until the transmitter is empty
9380 + */
9381 +static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
9382 +{
9383 + struct async_struct * info = (struct async_struct *)tty->driver_data;
9384 + unsigned long orig_jiffies, char_time;
9385 + int lsr;
9386 +
9387 + if (serial_paranoia_check(info, tty->device, "rs_wait_until_sent"))
9388 + return;
9389 +
9390 + if (info->state->type == PORT_UNKNOWN)
9391 + return;
9392 +
9393 + if (info->xmit_fifo_size == 0)
9394 + return; /* Just in case.... */
9395 +
9396 + orig_jiffies = jiffies;
9397 + /*
9398 + * Set the check interval to be 1/5 of the estimated time to
9399 + * send a single character, and make it at least 1. The check
9400 + * interval should also be less than the timeout.
9401 + *
9402 + * Note: we have to use pretty tight timings here to satisfy
9403 + * the NIST-PCTS.
9404 + */
9405 + char_time = (info->timeout - HZ/50) / info->xmit_fifo_size;
9406 + char_time = char_time / 5;
9407 + if (char_time == 0)
9408 + char_time = 1;
9409 + if (timeout && timeout < char_time)
9410 + char_time = timeout;
9411 + /*
9412 + * If the transmitter hasn't cleared in twice the approximate
9413 + * amount of time to send the entire FIFO, it probably won't
9414 + * ever clear. This assumes the UART isn't doing flow
9415 + * control, which is currently the case. Hence, if it ever
9416 + * takes longer than info->timeout, this is probably due to a
9417 + * UART bug of some kind. So, we clamp the timeout parameter at
9418 + * 2*info->timeout.
9419 + */
9420 + if (!timeout || timeout > 2*info->timeout)
9421 + timeout = 2*info->timeout;
9422 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
9423 + printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
9424 + printk("jiff=%lu...", jiffies);
9425 +#endif
9426 + while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) {
9427 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
9428 + printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
9429 +#endif
9430 + set_current_state(TASK_INTERRUPTIBLE);
9431 + schedule_timeout(char_time);
9432 + if (signal_pending(current))
9433 + break;
9434 + if (timeout && time_after(jiffies, orig_jiffies + timeout))
9435 + break;
9436 + }
9437 +#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
9438 + printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
9439 +#endif
9440 +}
9441 +
9442 +/*
9443 + * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
9444 + */
9445 +static void rs_hangup(struct tty_struct *tty)
9446 +{
9447 + struct async_struct * info = (struct async_struct *)tty->driver_data;
9448 + struct serial_state *state = info->state;
9449 +
9450 + if (serial_paranoia_check(info, tty->device, "rs_hangup"))
9451 + return;
9452 +
9453 + state = info->state;
9454 +
9455 + rs_flush_buffer(tty);
9456 + if (info->flags & ASYNC_CLOSING)
9457 + return;
9458 + shutdown(info);
9459 + info->event = 0;
9460 + state->count = 0;
9461 + info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
9462 + info->tty = 0;
9463 + wake_up_interruptible(&info->open_wait);
9464 +}
9465 +
9466 +/*
9467 + * ------------------------------------------------------------
9468 + * rs_open() and friends
9469 + * ------------------------------------------------------------
9470 + */
9471 +static int block_til_ready(struct tty_struct *tty, struct file * filp,
9472 + struct async_struct *info)
9473 +{
9474 + DECLARE_WAITQUEUE(wait, current);
9475 + struct serial_state *state = info->state;
9476 + int retval;
9477 + int do_clocal = 0, extra_count = 0;
9478 + unsigned long flags;
9479 +
9480 + /*
9481 + * If the device is in the middle of being closed, then block
9482 + * until it's done, and then try again.
9483 + */
9484 + if (tty_hung_up_p(filp) ||
9485 + (info->flags & ASYNC_CLOSING)) {
9486 + if (info->flags & ASYNC_CLOSING)
9487 + interruptible_sleep_on(&info->close_wait);
9488 +#ifdef SERIAL_DO_RESTART
9489 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
9490 + -EAGAIN : -ERESTARTSYS);
9491 +#else
9492 + return -EAGAIN;
9493 +#endif
9494 + }
9495 +
9496 + /*
9497 + * If this is a callout device, then just make sure the normal
9498 + * device isn't being used.
9499 + */
9500 + if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
9501 + if (info->flags & ASYNC_NORMAL_ACTIVE)
9502 + return -EBUSY;
9503 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
9504 + (info->flags & ASYNC_SESSION_LOCKOUT) &&
9505 + (info->session != current->session))
9506 + return -EBUSY;
9507 + if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
9508 + (info->flags & ASYNC_PGRP_LOCKOUT) &&
9509 + (info->pgrp != current->pgrp))
9510 + return -EBUSY;
9511 + info->flags |= ASYNC_CALLOUT_ACTIVE;
9512 + return 0;
9513 + }
9514 +
9515 + /*
9516 + * If non-blocking mode is set, or the port is not enabled,
9517 + * then make the check up front and then exit.
9518 + */
9519 + if ((filp->f_flags & O_NONBLOCK) ||
9520 + (tty->flags & (1 << TTY_IO_ERROR))) {
9521 + if (info->flags & ASYNC_CALLOUT_ACTIVE)
9522 + return -EBUSY;
9523 + info->flags |= ASYNC_NORMAL_ACTIVE;
9524 + return 0;
9525 + }
9526 +
9527 + if (info->flags & ASYNC_CALLOUT_ACTIVE) {
9528 + if (state->normal_termios.c_cflag & CLOCAL)
9529 + do_clocal = 1;
9530 + } else {
9531 + if (tty->termios->c_cflag & CLOCAL)
9532 + do_clocal = 1;
9533 + }
9534 +
9535 + /*
9536 + * Block waiting for the carrier detect and the line to become
9537 + * free (i.e., not in use by the callout). While we are in
9538 + * this loop, state->count is dropped by one, so that
9539 + * rs_close() knows when to free things. We restore it upon
9540 + * exit, either normal or abnormal.
9541 + */
9542 + retval = 0;
9543 + add_wait_queue(&info->open_wait, &wait);
9544 +#ifdef SERIAL_DEBUG_OPEN
9545 + printk("block_til_ready before block: ttys%d, count = %d\n",
9546 + state->line, state->count);
9547 +#endif
9548 + save_flags(flags); cli();
9549 + if (!tty_hung_up_p(filp)) {
9550 + extra_count = 1;
9551 + state->count--;
9552 + }
9553 + restore_flags(flags);
9554 + info->blocked_open++;
9555 + while (1) {
9556 + save_flags(flags); cli();
9557 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
9558 + (tty->termios->c_cflag & CBAUD))
9559 + serial_out(info, UART_MCR,
9560 + serial_inp(info, UART_MCR) |
9561 + (UART_MCR_DTR | UART_MCR_RTS));
9562 + restore_flags(flags);
9563 + set_current_state(TASK_INTERRUPTIBLE);
9564 + if (tty_hung_up_p(filp) ||
9565 + !(info->flags & ASYNC_INITIALIZED)) {
9566 +#ifdef SERIAL_DO_RESTART
9567 + if (info->flags & ASYNC_HUP_NOTIFY)
9568 + retval = -EAGAIN;
9569 + else
9570 + retval = -ERESTARTSYS;
9571 +#else
9572 + retval = -EAGAIN;
9573 +#endif
9574 + break;
9575 + }
9576 + if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
9577 + !(info->flags & ASYNC_CLOSING) &&
9578 + (do_clocal || (serial_in(info, UART_MSR) &
9579 + UART_MSR_DCD)))
9580 + break;
9581 + if (signal_pending(current)) {
9582 + retval = -ERESTARTSYS;
9583 + break;
9584 + }
9585 +#ifdef SERIAL_DEBUG_OPEN
9586 + printk("block_til_ready blocking: ttys%d, count = %d\n",
9587 + info->line, state->count);
9588 +#endif
9589 + schedule();
9590 + }
9591 + set_current_state(TASK_RUNNING);
9592 + remove_wait_queue(&info->open_wait, &wait);
9593 + if (extra_count)
9594 + state->count++;
9595 + info->blocked_open--;
9596 +#ifdef SERIAL_DEBUG_OPEN
9597 + printk("block_til_ready after blocking: ttys%d, count = %d\n",
9598 + info->line, state->count);
9599 +#endif
9600 + if (retval)
9601 + return retval;
9602 + info->flags |= ASYNC_NORMAL_ACTIVE;
9603 + return 0;
9604 +}
9605 +
9606 +static int get_async_struct(int line, struct async_struct **ret_info)
9607 +{
9608 + struct async_struct *info;
9609 + struct serial_state *sstate;
9610 +
9611 + sstate = rs_table + line;
9612 + sstate->count++;
9613 + if (sstate->info) {
9614 + *ret_info = sstate->info;
9615 + return 0;
9616 + }
9617 + info = kmalloc(sizeof(struct async_struct), GFP_KERNEL);
9618 + if (!info) {
9619 + sstate->count--;
9620 + return -ENOMEM;
9621 + }
9622 + memset(info, 0, sizeof(struct async_struct));
9623 + init_waitqueue_head(&info->open_wait);
9624 + init_waitqueue_head(&info->close_wait);
9625 + init_waitqueue_head(&info->delta_msr_wait);
9626 + info->magic = SERIAL_MAGIC;
9627 + info->port = sstate->port;
9628 + info->flags = sstate->flags;
9629 + info->io_type = sstate->io_type;
9630 + info->iomem_base = sstate->iomem_base;
9631 + info->iomem_reg_shift = sstate->iomem_reg_shift;
9632 + info->xmit_fifo_size = sstate->xmit_fifo_size;
9633 + info->line = line;
9634 + info->tqueue.routine = do_softint;
9635 + info->tqueue.data = info;
9636 + info->state = sstate;
9637 + if (sstate->info) {
9638 + kfree(info);
9639 + *ret_info = sstate->info;
9640 + return 0;
9641 + }
9642 + *ret_info = sstate->info = info;
9643 + return 0;
9644 +}
9645 +
9646 +/*
9647 + * This routine is called whenever a serial port is opened. It
9648 + * enables interrupts for a serial port, linking in its async structure into
9649 + * the IRQ chain. It also performs the serial-specific
9650 + * initialization for the tty structure.
9651 + *
9652 + * Note that on failure, we don't decrement the module use count - the tty
9653 + * later will call rs_close, which will decrement it for us as long as
9654 + * tty->driver_data is set non-NULL. --rmk
9655 + */
9656 +static int rs_open(struct tty_struct *tty, struct file * filp)
9657 +{
9658 + struct async_struct *info;
9659 + int retval, line;
9660 + unsigned long page;
9661 +
9662 + MOD_INC_USE_COUNT;
9663 + line = MINOR(tty->device) - tty->driver.minor_start;
9664 + if ((line < 0) || (line >= NR_PORTS)) {
9665 + MOD_DEC_USE_COUNT;
9666 + return -ENODEV;
9667 + }
9668 + retval = get_async_struct(line, &info);
9669 + if (retval) {
9670 + MOD_DEC_USE_COUNT;
9671 + return retval;
9672 + }
9673 + tty->driver_data = info;
9674 + info->tty = tty;
9675 + if (serial_paranoia_check(info, tty->device, "rs_open"))
9676 + return -ENODEV;
9677 +
9678 +#ifdef SERIAL_DEBUG_OPEN
9679 + printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line,
9680 + info->state->count);
9681 +#endif
9682 +#if (LINUX_VERSION_CODE > 0x20100)
9683 + info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
9684 +#endif
9685 +
9686 + /*
9687 + * This relies on lock_kernel() stuff so wants tidying for 2.5
9688 + */
9689 + if (!tmp_buf) {
9690 + page = get_zeroed_page(GFP_KERNEL);
9691 + if (!page)
9692 + return -ENOMEM;
9693 + if (tmp_buf)
9694 + free_page(page);
9695 + else
9696 + tmp_buf = (unsigned char *) page;
9697 + }
9698 +
9699 + /*
9700 + * If the port is the middle of closing, bail out now
9701 + */
9702 + if (tty_hung_up_p(filp) ||
9703 + (info->flags & ASYNC_CLOSING)) {
9704 + if (info->flags & ASYNC_CLOSING)
9705 + interruptible_sleep_on(&info->close_wait);
9706 +#ifdef SERIAL_DO_RESTART
9707 + return ((info->flags & ASYNC_HUP_NOTIFY) ?
9708 + -EAGAIN : -ERESTARTSYS);
9709 +#else
9710 + return -EAGAIN;
9711 +#endif
9712 + }
9713 +
9714 + /*
9715 + * Start up serial port
9716 + */
9717 + retval = startup(info);
9718 + if (retval)
9719 + return retval;
9720 +
9721 + retval = block_til_ready(tty, filp, info);
9722 + if (retval) {
9723 +#ifdef SERIAL_DEBUG_OPEN
9724 + printk("rs_open returning after block_til_ready with %d\n",
9725 + retval);
9726 +#endif
9727 + return retval;
9728 + }
9729 +
9730 + if ((info->state->count == 1) &&
9731 + (info->flags & ASYNC_SPLIT_TERMIOS)) {
9732 + if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
9733 + *tty->termios = info->state->normal_termios;
9734 + else
9735 + *tty->termios = info->state->callout_termios;
9736 + change_speed(info, 0);
9737 + }
9738 +#ifdef CONFIG_SERIAL_CONSOLE
9739 + if (sercons.cflag && sercons.index == line) {
9740 + tty->termios->c_cflag = sercons.cflag;
9741 + sercons.cflag = 0;
9742 + change_speed(info, 0);
9743 + }
9744 +#endif
9745 + info->session = current->session;
9746 + info->pgrp = current->pgrp;
9747 +
9748 +#ifdef SERIAL_DEBUG_OPEN
9749 + printk("rs_open ttys%d successful...", info->line);
9750 +#endif
9751 + return 0;
9752 +}
9753 +
9754 +/*
9755 + * /proc fs routines....
9756 + */
9757 +
9758 +static inline int line_info(char *buf, struct serial_state *state)
9759 +{
9760 + struct async_struct *info = state->info, scr_info;
9761 + char stat_buf[30], control, status;
9762 + int ret;
9763 + unsigned long flags;
9764 +
9765 + /*
9766 + * Return zero characters for ports not claimed by driver.
9767 + */
9768 + if (state->type == PORT_UNKNOWN) {
9769 + return 0; /* ignore unused ports */
9770 + }
9771 +
9772 + ret = sprintf(buf, "%d: uart:%s port:%lX irq:%d",
9773 + state->line, uart_config[state->type].name,
9774 + (state->port ? state->port : (long)state->iomem_base),
9775 + state->irq);
9776 +
9777 + /*
9778 + * Figure out the current RS-232 lines
9779 + */
9780 + if (!info) {
9781 + info = &scr_info; /* This is just for serial_{in,out} */
9782 +
9783 + info->magic = SERIAL_MAGIC;
9784 + info->port = state->port;
9785 + info->flags = state->flags;
9786 + info->hub6 = state->hub6;
9787 + info->io_type = state->io_type;
9788 + info->iomem_base = state->iomem_base;
9789 + info->iomem_reg_shift = state->iomem_reg_shift;
9790 + info->quot = 0;
9791 + info->tty = 0;
9792 + }
9793 + save_flags(flags); cli();
9794 + status = serial_in(info, UART_MSR);
9795 + control = info != &scr_info ? info->MCR : serial_in(info, UART_MCR);
9796 + restore_flags(flags);
9797 +
9798 + stat_buf[0] = 0;
9799 + stat_buf[1] = 0;
9800 + if (control & UART_MCR_RTS)
9801 + strcat(stat_buf, "|RTS");
9802 + if (status & UART_MSR_CTS)
9803 + strcat(stat_buf, "|CTS");
9804 + if (control & UART_MCR_DTR)
9805 + strcat(stat_buf, "|DTR");
9806 + if (status & UART_MSR_DSR)
9807 + strcat(stat_buf, "|DSR");
9808 + if (status & UART_MSR_DCD)
9809 + strcat(stat_buf, "|CD");
9810 + if (status & UART_MSR_RI)
9811 + strcat(stat_buf, "|RI");
9812 +
9813 + if (info->quot) {
9814 + ret += sprintf(buf+ret, " baud:%d",
9815 + state->baud_base / info->quot);
9816 + }
9817 +
9818 + ret += sprintf(buf+ret, " tx:%d rx:%d",
9819 + state->icount.tx, state->icount.rx);
9820 +
9821 + if (state->icount.frame)
9822 + ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
9823 +
9824 + if (state->icount.parity)
9825 + ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
9826 +
9827 + if (state->icount.brk)
9828 + ret += sprintf(buf+ret, " brk:%d", state->icount.brk);
9829 +
9830 + if (state->icount.overrun)
9831 + ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
9832 +
9833 + /*
9834 + * Last thing is the RS-232 status lines
9835 + */
9836 + ret += sprintf(buf+ret, " %s\n", stat_buf+1);
9837 + return ret;
9838 +}
9839 +
9840 +static int rs_read_proc(char *page, char **start, off_t off, int count,
9841 + int *eof, void *data)
9842 +{
9843 + int i, len = 0, l;
9844 + off_t begin = 0;
9845 +
9846 + len += sprintf(page, "serinfo:1.0 driver:%s%s revision:%s\n",
9847 + serial_version, LOCAL_VERSTRING, serial_revdate);
9848 + for (i = 0; i < NR_PORTS && len < 4000; i++) {
9849 + l = line_info(page + len, &rs_table[i]);
9850 + len += l;
9851 + if (len+begin > off+count)
9852 + goto done;
9853 + if (len+begin < off) {
9854 + begin += len;
9855 + len = 0;
9856 + }
9857 + }
9858 + *eof = 1;
9859 +done:
9860 + if (off >= len+begin)
9861 + return 0;
9862 + *start = page + (off-begin);
9863 + return ((count < begin+len-off) ? count : begin+len-off);
9864 +}
9865 +
9866 +/*
9867 + * ---------------------------------------------------------------------
9868 + * rs_init() and friends
9869 + *
9870 + * rs_init() is called at boot-time to initialize the serial driver.
9871 + * ---------------------------------------------------------------------
9872 + */
9873 +
9874 +/*
9875 + * This routine prints out the appropriate serial driver version
9876 + * number, and identifies which options were configured into this
9877 + * driver.
9878 + */
9879 +static char serial_options[] __initdata =
9880 +#ifdef CONFIG_HUB6
9881 + " HUB-6"
9882 +#define SERIAL_OPT
9883 +#endif
9884 +#ifdef CONFIG_SERIAL_MANY_PORTS
9885 + " MANY_PORTS"
9886 +#define SERIAL_OPT
9887 +#endif
9888 +#ifdef CONFIG_SERIAL_MULTIPORT
9889 + " MULTIPORT"
9890 +#define SERIAL_OPT
9891 +#endif
9892 +#ifdef CONFIG_SERIAL_SHARE_IRQ
9893 + " SHARE_IRQ"
9894 +#define SERIAL_OPT
9895 +#endif
9896 +#ifdef CONFIG_SERIAL_DETECT_IRQ
9897 + " DETECT_IRQ"
9898 +#define SERIAL_OPT
9899 +#endif
9900 +#ifdef ENABLE_SERIAL_PCI
9901 + " SERIAL_PCI"
9902 +#define SERIAL_OPT
9903 +#endif
9904 +#ifdef ENABLE_SERIAL_PNP
9905 + " ISAPNP"
9906 +#define SERIAL_OPT
9907 +#endif
9908 +#ifdef ENABLE_SERIAL_ACPI
9909 + " SERIAL_ACPI"
9910 +#define SERIAL_OPT
9911 +#endif
9912 +#ifdef SERIAL_OPT
9913 + " enabled\n";
9914 +#else
9915 + " no serial options enabled\n";
9916 +#endif
9917 +#undef SERIAL_OPT
9918 +
9919 +static _INLINE_ void show_serial_version(void)
9920 +{
9921 + printk(KERN_INFO "%s version %s%s (%s) with%s", serial_name,
9922 + serial_version, LOCAL_VERSTRING, serial_revdate,
9923 + serial_options);
9924 +}
9925 +
9926 +/*
9927 + * This routine detect the IRQ of a serial port by clearing OUT2 when
9928 + * no UART interrupt are requested (IER = 0) (*GPL*). This seems to work at
9929 + * each time, as long as no other device permanently request the IRQ.
9930 + * If no IRQ is detected, or multiple IRQ appear, this function returns 0.
9931 + * The variable "state" and the field "state->port" should not be null.
9932 + */
9933 +static unsigned detect_uart_irq (struct serial_state * state)
9934 +{
9935 + int irq;
9936 + unsigned long irqs;
9937 + unsigned char save_mcr, save_ier;
9938 + struct async_struct scr_info; /* serial_{in,out} because HUB6 */
9939 +
9940 +#ifdef CONFIG_SERIAL_MANY_PORTS
9941 + unsigned char save_ICP=0; /* no warning */
9942 + unsigned short ICP=0;
9943 +
9944 + if (state->flags & ASYNC_FOURPORT) {
9945 + ICP = (state->port & 0xFE0) | 0x01F;
9946 + save_ICP = inb_p(ICP);
9947 + outb_p(0x80, ICP);
9948 + (void) inb_p(ICP);
9949 + }
9950 +#endif
9951 + scr_info.magic = SERIAL_MAGIC;
9952 + scr_info.state = state;
9953 + scr_info.port = state->port;
9954 + scr_info.flags = state->flags;
9955 +#ifdef CONFIG_HUB6
9956 + scr_info.hub6 = state->hub6;
9957 +#endif
9958 + scr_info.io_type = state->io_type;
9959 + scr_info.iomem_base = state->iomem_base;
9960 + scr_info.iomem_reg_shift = state->iomem_reg_shift;
9961 +
9962 + /* forget possible initially masked and pending IRQ */
9963 + probe_irq_off(probe_irq_on());
9964 + save_mcr = serial_inp(&scr_info, UART_MCR);
9965 + save_ier = serial_inp(&scr_info, UART_IER);
9966 + serial_outp(&scr_info, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
9967 +
9968 + irqs = probe_irq_on();
9969 + serial_outp(&scr_info, UART_MCR, 0);
9970 + udelay (10);
9971 + if (state->flags & ASYNC_FOURPORT) {
9972 + serial_outp(&scr_info, UART_MCR,
9973 + UART_MCR_DTR | UART_MCR_RTS);
9974 + } else {
9975 + serial_outp(&scr_info, UART_MCR,
9976 + UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
9977 + }
9978 + serial_outp(&scr_info, UART_IER, 0x0f); /* enable all intrs */
9979 + (void)serial_inp(&scr_info, UART_LSR);
9980 + (void)serial_inp(&scr_info, UART_RX);
9981 + (void)serial_inp(&scr_info, UART_IIR);
9982 + (void)serial_inp(&scr_info, UART_MSR);
9983 + serial_outp(&scr_info, UART_TX, 0xFF);
9984 + udelay (20);
9985 + irq = probe_irq_off(irqs);
9986 +
9987 + serial_outp(&scr_info, UART_MCR, save_mcr);
9988 + serial_outp(&scr_info, UART_IER, save_ier);
9989 +#ifdef CONFIG_SERIAL_MANY_PORTS
9990 + if (state->flags & ASYNC_FOURPORT)
9991 + outb_p(save_ICP, ICP);
9992 +#endif
9993 + return (irq > 0)? irq : 0;
9994 +}
9995 +
9996 +/*
9997 + * This is a quickie test to see how big the FIFO is.
9998 + * It doesn't work at all the time, more's the pity.
9999 + */
10000 +static int size_fifo(struct async_struct *info)
10001 +{
10002 + unsigned char old_fcr, old_mcr, old_dll, old_dlm;
10003 + int count;
10004 +
10005 + old_fcr = serial_inp(info, UART_FCR);
10006 + old_mcr = serial_inp(info, UART_MCR);
10007 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO |
10008 + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
10009 + serial_outp(info, UART_MCR, UART_MCR_LOOP);
10010 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
10011 + old_dll = serial_inp(info, UART_DLL);
10012 + old_dlm = serial_inp(info, UART_DLM);
10013 + serial_outp(info, UART_DLL, 0x01);
10014 + serial_outp(info, UART_DLM, 0x00);
10015 + serial_outp(info, UART_LCR, 0x03);
10016 + for (count = 0; count < 256; count++)
10017 + serial_outp(info, UART_TX, count);
10018 + mdelay(20);
10019 + for (count = 0; (serial_inp(info, UART_LSR) & UART_LSR_DR) &&
10020 + (count < 256); count++)
10021 + serial_inp(info, UART_RX);
10022 + serial_outp(info, UART_FCR, old_fcr);
10023 + serial_outp(info, UART_MCR, old_mcr);
10024 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
10025 + serial_outp(info, UART_DLL, old_dll);
10026 + serial_outp(info, UART_DLM, old_dlm);
10027 +
10028 + return count;
10029 +}
10030 +
10031 +/*
10032 + * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
10033 + * When this function is called we know it is at least a StarTech
10034 + * 16650 V2, but it might be one of several StarTech UARTs, or one of
10035 + * its clones. (We treat the broken original StarTech 16650 V1 as a
10036 + * 16550, and why not? Startech doesn't seem to even acknowledge its
10037 + * existence.)
10038 + *
10039 + * What evil have men's minds wrought...
10040 + */
10041 +static void autoconfig_startech_uarts(struct async_struct *info,
10042 + struct serial_state *state,
10043 + unsigned long flags)
10044 +{
10045 + unsigned char scratch, scratch2, scratch3, scratch4;
10046 +
10047 + /*
10048 + * First we check to see if it's an Oxford Semiconductor UART.
10049 + *
10050 + * If we have to do this here because some non-National
10051 + * Semiconductor clone chips lock up if you try writing to the
10052 + * LSR register (which serial_icr_read does)
10053 + */
10054 + if (state->type == PORT_16550A) {
10055 + /*
10056 + * EFR [4] must be set else this test fails
10057 + *
10058 + * This shouldn't be necessary, but Mike Hudson
10059 + * (Exoray@isys.ca) claims that it's needed for 952
10060 + * dual UART's (which are not recommended for new designs).
10061 + */
10062 + info->ACR = 0;
10063 + serial_out(info, UART_LCR, 0xBF);
10064 + serial_out(info, UART_EFR, 0x10);
10065 + serial_out(info, UART_LCR, 0x00);
10066 + /* Check for Oxford Semiconductor 16C950 */
10067 + scratch = serial_icr_read(info, UART_ID1);
10068 + scratch2 = serial_icr_read(info, UART_ID2);
10069 + scratch3 = serial_icr_read(info, UART_ID3);
10070 +
10071 + if (scratch == 0x16 && scratch2 == 0xC9 &&
10072 + (scratch3 == 0x50 || scratch3 == 0x52 ||
10073 + scratch3 == 0x54)) {
10074 + state->type = PORT_16C950;
10075 + state->revision = serial_icr_read(info, UART_REV) |
10076 + (scratch3 << 8);
10077 + return;
10078 + }
10079 + }
10080 +
10081 + /*
10082 + * We check for a XR16C850 by setting DLL and DLM to 0, and
10083 + * then reading back DLL and DLM. If DLM reads back 0x10,
10084 + * then the UART is a XR16C850 and the DLL contains the chip
10085 + * revision. If DLM reads back 0x14, then the UART is a
10086 + * XR16C854.
10087 + *
10088 + */
10089 +
10090 + /* Save the DLL and DLM */
10091 +
10092 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
10093 + scratch3 = serial_inp(info, UART_DLL);
10094 + scratch4 = serial_inp(info, UART_DLM);
10095 +
10096 + serial_outp(info, UART_DLL, 0);
10097 + serial_outp(info, UART_DLM, 0);
10098 + scratch2 = serial_inp(info, UART_DLL);
10099 + scratch = serial_inp(info, UART_DLM);
10100 + serial_outp(info, UART_LCR, 0);
10101 +
10102 + if (scratch == 0x10 || scratch == 0x14) {
10103 + if (scratch == 0x10)
10104 + state->revision = scratch2;
10105 + state->type = PORT_16850;
10106 + return;
10107 + }
10108 +
10109 + /* Restore the DLL and DLM */
10110 +
10111 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
10112 + serial_outp(info, UART_DLL, scratch3);
10113 + serial_outp(info, UART_DLM, scratch4);
10114 + serial_outp(info, UART_LCR, 0);
10115 + /*
10116 + * We distinguish between the '654 and the '650 by counting
10117 + * how many bytes are in the FIFO. I'm using this for now,
10118 + * since that's the technique that was sent to me in the
10119 + * serial driver update, but I'm not convinced this works.
10120 + * I've had problems doing this in the past. -TYT
10121 + */
10122 + if (size_fifo(info) == 64)
10123 + state->type = PORT_16654;
10124 + else
10125 + state->type = PORT_16650V2;
10126 +}
10127 +
10128 +/*
10129 + * This routine is called by rs_init() to initialize a specific serial
10130 + * port. It determines what type of UART chip this serial port is
10131 + * using: 8250, 16450, 16550, 16550A. The important question is
10132 + * whether or not this UART is a 16550A or not, since this will
10133 + * determine whether or not we can use its FIFO features or not.
10134 + */
10135 +static void autoconfig(struct serial_state * state)
10136 +{
10137 + unsigned char status1, status2, scratch, scratch2, scratch3;
10138 + unsigned char save_lcr, save_mcr;
10139 + struct async_struct *info, scr_info;
10140 + unsigned long flags;
10141 +
10142 + state->type = PORT_UNKNOWN;
10143 +
10144 +#ifdef SERIAL_DEBUG_AUTOCONF
10145 + printk("Testing ttyS%d (0x%04lx, 0x%04x)...\n", state->line,
10146 + state->port, (unsigned) state->iomem_base);
10147 +#endif
10148 +
10149 + if (!CONFIGURED_SERIAL_PORT(state))
10150 + return;
10151 +
10152 + info = &scr_info; /* This is just for serial_{in,out} */
10153 +
10154 + info->magic = SERIAL_MAGIC;
10155 + info->state = state;
10156 + info->port = state->port;
10157 + info->flags = state->flags;
10158 +#ifdef CONFIG_HUB6
10159 + info->hub6 = state->hub6;
10160 +#endif
10161 + info->io_type = state->io_type;
10162 + info->iomem_base = state->iomem_base;
10163 + info->iomem_reg_shift = state->iomem_reg_shift;
10164 +
10165 + save_flags(flags); cli();
10166 +
10167 + if (!(state->flags & ASYNC_BUGGY_UART) &&
10168 + !state->iomem_base) {
10169 + /*
10170 + * Do a simple existence test first; if we fail this,
10171 + * there's no point trying anything else.
10172 + *
10173 + * 0x80 is used as a nonsense port to prevent against
10174 + * false positives due to ISA bus float. The
10175 + * assumption is that 0x80 is a non-existent port;
10176 + * which should be safe since include/asm/io.h also
10177 + * makes this assumption.
10178 + */
10179 + scratch = serial_inp(info, UART_IER);
10180 + serial_outp(info, UART_IER, 0);
10181 +#ifdef __i386__
10182 + outb(0xff, 0x080);
10183 +#endif
10184 + scratch2 = serial_inp(info, UART_IER);
10185 + serial_outp(info, UART_IER, 0x0F);
10186 +#ifdef __i386__
10187 + outb(0, 0x080);
10188 +#endif
10189 + scratch3 = serial_inp(info, UART_IER);
10190 + serial_outp(info, UART_IER, scratch);
10191 + if (scratch2 || scratch3 != 0x0F) {
10192 +#ifdef SERIAL_DEBUG_AUTOCONF
10193 + printk("serial: ttyS%d: simple autoconfig failed "
10194 + "(%02x, %02x)\n", state->line,
10195 + scratch2, scratch3);
10196 +#endif
10197 + restore_flags(flags);
10198 + return; /* We failed; there's nothing here */
10199 + }
10200 + }
10201 +
10202 + save_mcr = serial_in(info, UART_MCR);
10203 + save_lcr = serial_in(info, UART_LCR);
10204 +
10205 + /*
10206 + * Check to see if a UART is really there. Certain broken
10207 + * internal modems based on the Rockwell chipset fail this
10208 + * test, because they apparently don't implement the loopback
10209 + * test mode. So this test is skipped on the COM 1 through
10210 + * COM 4 ports. This *should* be safe, since no board
10211 + * manufacturer would be stupid enough to design a board
10212 + * that conflicts with COM 1-4 --- we hope!
10213 + */
10214 + if (!(state->flags & ASYNC_SKIP_TEST)) {
10215 + serial_outp(info, UART_MCR, UART_MCR_LOOP | 0x0A);
10216 + status1 = serial_inp(info, UART_MSR) & 0xF0;
10217 + serial_outp(info, UART_MCR, save_mcr);
10218 + if (status1 != 0x90) {
10219 +#ifdef SERIAL_DEBUG_AUTOCONF
10220 + printk("serial: ttyS%d: no UART loopback failed\n",
10221 + state->line);
10222 +#endif
10223 + restore_flags(flags);
10224 + return;
10225 + }
10226 + }
10227 + serial_outp(info, UART_LCR, 0xBF); /* set up for StarTech test */
10228 + serial_outp(info, UART_EFR, 0); /* EFR is the same as FCR */
10229 + serial_outp(info, UART_LCR, 0);
10230 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
10231 + scratch = serial_in(info, UART_IIR) >> 6;
10232 + switch (scratch) {
10233 + case 0:
10234 + state->type = PORT_16450;
10235 + break;
10236 + case 1:
10237 + state->type = PORT_UNKNOWN;
10238 + break;
10239 + case 2:
10240 + state->type = PORT_16550;
10241 + break;
10242 + case 3:
10243 + state->type = PORT_16550A;
10244 + break;
10245 + }
10246 + if (state->type == PORT_16550A) {
10247 + /* Check for Startech UART's */
10248 + serial_outp(info, UART_LCR, UART_LCR_DLAB);
10249 + if (serial_in(info, UART_EFR) == 0) {
10250 + serial_outp(info, UART_EFR, 0xA8);
10251 + if (serial_in(info, UART_EFR) == 0) {
10252 + /* We are a NS16552D/Motorola
10253 + * 8xxx DUART, stop. */
10254 + goto out;
10255 + }
10256 + state->type = PORT_16650;
10257 + serial_outp(info, UART_EFR, 0);
10258 + } else {
10259 + serial_outp(info, UART_LCR, 0xBF);
10260 + if (serial_in(info, UART_EFR) == 0)
10261 + autoconfig_startech_uarts(info, state, flags);
10262 + }
10263 + }
10264 + if (state->type == PORT_16550A) {
10265 + /* Check for TI 16750 */
10266 + serial_outp(info, UART_LCR, save_lcr | UART_LCR_DLAB);
10267 + serial_outp(info, UART_FCR,
10268 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
10269 + scratch = serial_in(info, UART_IIR) >> 5;
10270 + if (scratch == 7) {
10271 + /*
10272 + * If this is a 16750, and not a cheap UART
10273 + * clone, then it should only go into 64 byte
10274 + * mode if the UART_FCR7_64BYTE bit was set
10275 + * while UART_LCR_DLAB was latched.
10276 + */
10277 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
10278 + serial_outp(info, UART_LCR, 0);
10279 + serial_outp(info, UART_FCR,
10280 + UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
10281 + scratch = serial_in(info, UART_IIR) >> 5;
10282 + if (scratch == 6)
10283 + state->type = PORT_16750;
10284 + }
10285 + serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO);
10286 + }
10287 +#if defined(CONFIG_SERIAL_RSA) && defined(MODULE)
10288 + if (state->type == PORT_16550A) {
10289 + int i;
10290 +
10291 + for (i = 0 ; i < PORT_RSA_MAX ; ++i) {
10292 + if (!probe_rsa[i] && !force_rsa[i])
10293 + break;
10294 + if (((probe_rsa[i] != state->port) ||
10295 + check_region(state->port + UART_RSA_BASE, 16)) &&
10296 + (force_rsa[i] != state->port))
10297 + continue;
10298 + if (!enable_rsa(info))
10299 + continue;
10300 + state->type = PORT_RSA;
10301 + state->baud_base = SERIAL_RSA_BAUD_BASE;
10302 + break;
10303 + }
10304 + }
10305 +#endif
10306 +out:
10307 + serial_outp(info, UART_LCR, save_lcr);
10308 + if (state->type == PORT_16450) {
10309 + scratch = serial_in(info, UART_SCR);
10310 + serial_outp(info, UART_SCR, 0xa5);
10311 + status1 = serial_in(info, UART_SCR);
10312 + serial_outp(info, UART_SCR, 0x5a);
10313 + status2 = serial_in(info, UART_SCR);
10314 + serial_outp(info, UART_SCR, scratch);
10315 +
10316 + if ((status1 != 0xa5) || (status2 != 0x5a))
10317 + state->type = PORT_8250;
10318 + }
10319 + state->xmit_fifo_size = uart_config[state->type].dfl_xmit_fifo_size;
10320 +
10321 + if (state->type == PORT_UNKNOWN) {
10322 + restore_flags(flags);
10323 + return;
10324 + }
10325 +
10326 + if (info->port) {
10327 +#ifdef CONFIG_SERIAL_RSA
10328 + if (state->type == PORT_RSA)
10329 + request_region(info->port + UART_RSA_BASE, 16,
10330 + "serial_rsa(auto)");
10331 + else
10332 +#endif
10333 + request_region(info->port,8,"serial(auto)");
10334 + }
10335 +
10336 + /*
10337 + * Reset the UART.
10338 + */
10339 +#ifdef CONFIG_SERIAL_RSA
10340 + if (state->type == PORT_RSA)
10341 + serial_outp(info, UART_RSA_FRR, 0);
10342 +#endif
10343 + serial_outp(info, UART_MCR, save_mcr);
10344 + serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO |
10345 + UART_FCR_CLEAR_RCVR |
10346 + UART_FCR_CLEAR_XMIT));
10347 + serial_outp(info, UART_FCR, 0);
10348 + (void)serial_in(info, UART_RX);
10349 + serial_outp(info, UART_IER, 0);
10350 +
10351 + restore_flags(flags);
10352 +}
10353 +
10354 +int register_serial(struct serial_struct *req);
10355 +void unregister_serial(int line);
10356 +
10357 +#if (LINUX_VERSION_CODE > 0x20100)
10358 +EXPORT_SYMBOL(register_serial);
10359 +EXPORT_SYMBOL(unregister_serial);
10360 +#else
10361 +static struct symbol_table serial_syms = {
10362 +#include <linux/symtab_begin.h>
10363 + X(register_serial),
10364 + X(unregister_serial),
10365 +#include <linux/symtab_end.h>
10366 +};
10367 +#endif
10368 +
10369 +
10370 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
10371 +
10372 +static void __devinit printk_pnp_dev_id(unsigned short vendor,
10373 + unsigned short device)
10374 +{
10375 + printk("%c%c%c%x%x%x%x",
10376 + 'A' + ((vendor >> 2) & 0x3f) - 1,
10377 + 'A' + (((vendor & 3) << 3) | ((vendor >> 13) & 7)) - 1,
10378 + 'A' + ((vendor >> 8) & 0x1f) - 1,
10379 + (device >> 4) & 0x0f,
10380 + device & 0x0f,
10381 + (device >> 12) & 0x0f,
10382 + (device >> 8) & 0x0f);
10383 +}
10384 +
10385 +static _INLINE_ int get_pci_port(struct pci_dev *dev,
10386 + struct pci_board *board,
10387 + struct serial_struct *req,
10388 + int idx)
10389 +{
10390 + unsigned long port;
10391 + int base_idx;
10392 + int max_port;
10393 + int offset;
10394 +
10395 + base_idx = SPCI_FL_GET_BASE(board->flags);
10396 + if (board->flags & SPCI_FL_BASE_TABLE)
10397 + base_idx += idx;
10398 +
10399 + if (board->flags & SPCI_FL_REGION_SZ_CAP) {
10400 + max_port = pci_resource_len(dev, base_idx) / 8;
10401 + if (idx >= max_port)
10402 + return 1;
10403 + }
10404 +
10405 + offset = board->first_uart_offset;
10406 +
10407 + /* Timedia/SUNIX uses a mixture of BARs and offsets */
10408 + /* Ugh, this is ugly as all hell --- TYT */
10409 + if(dev->vendor == PCI_VENDOR_ID_TIMEDIA ) /* 0x1409 */
10410 + switch(idx) {
10411 + case 0: base_idx=0;
10412 + break;
10413 + case 1: base_idx=0; offset=8;
10414 + break;
10415 + case 2: base_idx=1;
10416 + break;
10417 + case 3: base_idx=1; offset=8;
10418 + break;
10419 + case 4: /* BAR 2*/
10420 + case 5: /* BAR 3 */
10421 + case 6: /* BAR 4*/
10422 + case 7: base_idx=idx-2; /* BAR 5*/
10423 + }
10424 +
10425 + /* Some Titan cards are also a little weird */
10426 + if (dev->vendor == PCI_VENDOR_ID_TITAN &&
10427 + (dev->device == PCI_DEVICE_ID_TITAN_400L ||
10428 + dev->device == PCI_DEVICE_ID_TITAN_800L)) {
10429 + switch (idx) {
10430 + case 0: base_idx = 1;
10431 + break;
10432 + case 1: base_idx = 2;
10433 + break;
10434 + default:
10435 + base_idx = 4;
10436 + offset = 8 * (idx - 2);
10437 + }
10438 +
10439 + }
10440 +
10441 + /* HP's Diva chip puts the 4th/5th serial port further out, and
10442 + * some serial ports are supposed to be hidden on certain models.
10443 + */
10444 + if (dev->vendor == PCI_VENDOR_ID_HP &&
10445 + dev->device == PCI_DEVICE_ID_HP_SAS) {
10446 + switch (dev->subsystem_device) {
10447 + case 0x104B: /* Maestro */
10448 + if (idx == 3) idx++;
10449 + break;
10450 + case 0x1282: /* Everest / Longs Peak */
10451 + if (idx > 0) idx++;
10452 + if (idx > 2) idx++;
10453 + break;
10454 + }
10455 + if (idx > 2) {
10456 + offset = 0x18;
10457 + }
10458 + }
10459 +
10460 + port = pci_resource_start(dev, base_idx) + offset;
10461 +
10462 + if ((board->flags & SPCI_FL_BASE_TABLE) == 0)
10463 + port += idx * (board->uart_offset ? board->uart_offset : 8);
10464 +
10465 + if (IS_PCI_REGION_IOPORT(dev, base_idx)) {
10466 + req->port = port;
10467 + if (HIGH_BITS_OFFSET)
10468 + req->port_high = port >> HIGH_BITS_OFFSET;
10469 + else
10470 + req->port_high = 0;
10471 + return 0;
10472 + }
10473 + req->io_type = SERIAL_IO_MEM;
10474 + req->iomem_base = ioremap(port, board->uart_offset);
10475 + req->iomem_reg_shift = board->reg_shift;
10476 + req->port = 0;
10477 + return 0;
10478 +}
10479 +
10480 +static _INLINE_ int get_pci_irq(struct pci_dev *dev,
10481 + struct pci_board *board,
10482 + int idx)
10483 +{
10484 + int base_idx;
10485 +
10486 + if ((board->flags & SPCI_FL_IRQRESOURCE) == 0)
10487 + return dev->irq;
10488 +
10489 + base_idx = SPCI_FL_GET_IRQBASE(board->flags);
10490 + if (board->flags & SPCI_FL_IRQ_TABLE)
10491 + base_idx += idx;
10492 +
10493 + return PCI_IRQ_RESOURCE(dev, base_idx);
10494 +}
10495 +
10496 +/*
10497 + * Common enabler code shared by both PCI and ISAPNP probes
10498 + */
10499 +static void __devinit start_pci_pnp_board(struct pci_dev *dev,
10500 + struct pci_board *board)
10501 +{
10502 + int k, line;
10503 + struct serial_struct serial_req;
10504 + int base_baud;
10505 +
10506 + if (PREPARE_FUNC(dev) && (PREPARE_FUNC(dev))(dev) < 0) {
10507 + printk("serial: PNP device '");
10508 + printk_pnp_dev_id(dev->vendor, dev->device);
10509 + printk("' prepare failed\n");
10510 + return;
10511 + }
10512 +
10513 + if (ACTIVATE_FUNC(dev) && (ACTIVATE_FUNC(dev))(dev) < 0) {
10514 + printk("serial: PNP device '");
10515 + printk_pnp_dev_id(dev->vendor, dev->device);
10516 + printk("' activate failed\n");
10517 + return;
10518 + }
10519 +
10520 + /*
10521 + * Run the initialization function, if any
10522 + */
10523 + if (board->init_fn && ((board->init_fn)(dev, board, 1) != 0))
10524 + return;
10525 +
10526 + /*
10527 + * Register the serial board in the array if we need to
10528 + * shutdown the board on a module unload or card removal
10529 + */
10530 + if (DEACTIVATE_FUNC(dev) || board->init_fn) {
10531 + for (k=0; k < NR_PCI_BOARDS; k++)
10532 + if (serial_pci_board[k].dev == 0)
10533 + break;
10534 + if (k >= NR_PCI_BOARDS)
10535 + return;
10536 + serial_pci_board[k].board = *board;
10537 + serial_pci_board[k].dev = dev;
10538 + }
10539 +
10540 + base_baud = board->base_baud;
10541 + if (!base_baud)
10542 + base_baud = BASE_BAUD;
10543 + memset(&serial_req, 0, sizeof(serial_req));
10544 +
10545 + for (k=0; k < board->num_ports; k++) {
10546 + serial_req.irq = get_pci_irq(dev, board, k);
10547 + if (get_pci_port(dev, board, &serial_req, k))
10548 + break;
10549 + serial_req.flags = ASYNC_SKIP_TEST | ASYNC_AUTOPROBE;
10550 +#ifdef SERIAL_DEBUG_PCI
10551 + printk("Setup PCI/PNP port: port %x, irq %d, type %d\n",
10552 + serial_req.port, serial_req.irq, serial_req.io_type);
10553 +#endif
10554 + line = register_serial(&serial_req);
10555 + if (line < 0)
10556 + break;
10557 + rs_table[line].baud_base = base_baud;
10558 + rs_table[line].dev = dev;
10559 + }
10560 +}
10561 +#endif /* ENABLE_SERIAL_PCI || ENABLE_SERIAL_PNP */
10562 +
10563 +#ifdef ENABLE_SERIAL_PCI
10564 +/*
10565 + * Some PCI serial cards using the PLX 9050 PCI interface chip require
10566 + * that the card interrupt be explicitly enabled or disabled. This
10567 + * seems to be mainly needed on card using the PLX which also use I/O
10568 + * mapped memory.
10569 + */
10570 +static int __devinit
10571 +pci_plx9050_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10572 +{
10573 + u8 data, *p, irq_config;
10574 + int pci_config;
10575 +
10576 + irq_config = 0x41;
10577 + pci_config = PCI_COMMAND_MEMORY;
10578 + if (dev->vendor == PCI_VENDOR_ID_PANACOM)
10579 + irq_config = 0x43;
10580 + if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
10581 + (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
10582 + /*
10583 + * As the megawolf cards have the int pins active
10584 + * high, and have 2 UART chips, both ints must be
10585 + * enabled on the 9050. Also, the UARTS are set in
10586 + * 16450 mode by default, so we have to enable the
10587 + * 16C950 'enhanced' mode so that we can use the deep
10588 + * FIFOs
10589 + */
10590 + irq_config = 0x5b;
10591 + pci_config = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
10592 + }
10593 +
10594 + pci_read_config_byte(dev, PCI_COMMAND, &data);
10595 +
10596 + if (enable)
10597 + pci_write_config_byte(dev, PCI_COMMAND,
10598 + data | pci_config);
10599 +
10600 + /* enable/disable interrupts */
10601 + p = ioremap(pci_resource_start(dev, 0), 0x80);
10602 + writel(enable ? irq_config : 0x00, (unsigned long)p + 0x4c);
10603 + iounmap(p);
10604 +
10605 + if (!enable)
10606 + pci_write_config_byte(dev, PCI_COMMAND,
10607 + data & ~pci_config);
10608 + return 0;
10609 +}
10610 +
10611 +
10612 +/*
10613 + * SIIG serial cards have an PCI interface chip which also controls
10614 + * the UART clocking frequency. Each UART can be clocked independently
10615 + * (except cards equiped with 4 UARTs) and initial clocking settings
10616 + * are stored in the EEPROM chip. It can cause problems because this
10617 + * version of serial driver doesn't support differently clocked UART's
10618 + * on single PCI card. To prevent this, initialization functions set
10619 + * high frequency clocking for all UART's on given card. It is safe (I
10620 + * hope) because it doesn't touch EEPROM settings to prevent conflicts
10621 + * with other OSes (like M$ DOS).
10622 + *
10623 + * SIIG support added by Andrey Panin <pazke@mail.tp.ru>, 10/1999
10624 + *
10625 + * There is two family of SIIG serial cards with different PCI
10626 + * interface chip and different configuration methods:
10627 + * - 10x cards have control registers in IO and/or memory space;
10628 + * - 20x cards have control registers in standard PCI configuration space.
10629 + *
10630 + * SIIG initialization functions exported for use by parport_serial.c module.
10631 + */
10632 +
10633 +#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
10634 +#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
10635 +
10636 +int __devinit
10637 +pci_siig10x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10638 +{
10639 + u16 data, *p;
10640 +
10641 + if (!enable) return 0;
10642 +
10643 + p = ioremap(pci_resource_start(dev, 0), 0x80);
10644 +
10645 + switch (dev->device & 0xfff8) {
10646 + case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
10647 + data = 0xffdf;
10648 + break;
10649 + case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
10650 + data = 0xf7ff;
10651 + break;
10652 + default: /* 1S1P, 4S */
10653 + data = 0xfffb;
10654 + break;
10655 + }
10656 +
10657 + writew(readw((unsigned long) p + 0x28) & data, (unsigned long) p + 0x28);
10658 + iounmap(p);
10659 + return 0;
10660 +}
10661 +EXPORT_SYMBOL(pci_siig10x_fn);
10662 +
10663 +#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
10664 +#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
10665 +
10666 +int __devinit
10667 +pci_siig20x_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10668 +{
10669 + u8 data;
10670 +
10671 + if (!enable) return 0;
10672 +
10673 + /* Change clock frequency for the first UART. */
10674 + pci_read_config_byte(dev, 0x6f, &data);
10675 + pci_write_config_byte(dev, 0x6f, data & 0xef);
10676 +
10677 + /* If this card has 2 UART, we have to do the same with second UART. */
10678 + if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
10679 + ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
10680 + pci_read_config_byte(dev, 0x73, &data);
10681 + pci_write_config_byte(dev, 0x73, data & 0xef);
10682 + }
10683 + return 0;
10684 +}
10685 +EXPORT_SYMBOL(pci_siig20x_fn);
10686 +
10687 +/* Added for EKF Intel i960 serial boards */
10688 +static int __devinit
10689 +pci_inteli960ni_fn(struct pci_dev *dev,
10690 + struct pci_board *board,
10691 + int enable)
10692 +{
10693 + unsigned long oldval;
10694 +
10695 + if (!(pci_get_subdevice(dev) & 0x1000))
10696 + return(-1);
10697 +
10698 + if (!enable) /* is there something to deinit? */
10699 + return(0);
10700 +
10701 +#ifdef SERIAL_DEBUG_PCI
10702 + printk(KERN_DEBUG " Subsystem ID %lx (intel 960)\n",
10703 + (unsigned long) board->subdevice);
10704 +#endif
10705 + /* is firmware started? */
10706 + pci_read_config_dword(dev, 0x44, (void*) &oldval);
10707 + if (oldval == 0x00001000L) { /* RESET value */
10708 + printk(KERN_DEBUG "Local i960 firmware missing");
10709 + return(-1);
10710 + }
10711 + return(0);
10712 +}
10713 +
10714 +/*
10715 + * Timedia has an explosion of boards, and to avoid the PCI table from
10716 + * growing *huge*, we use this function to collapse some 70 entries
10717 + * in the PCI table into one, for sanity's and compactness's sake.
10718 + */
10719 +static unsigned short timedia_single_port[] = {
10720 + 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 };
10721 +static unsigned short timedia_dual_port[] = {
10722 + 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
10723 + 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
10724 + 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
10725 + 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
10726 + 0xD079, 0 };
10727 +static unsigned short timedia_quad_port[] = {
10728 + 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
10729 + 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
10730 + 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
10731 + 0xB157, 0 };
10732 +static unsigned short timedia_eight_port[] = {
10733 + 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
10734 + 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 };
10735 +static struct timedia_struct {
10736 + int num;
10737 + unsigned short *ids;
10738 +} timedia_data[] = {
10739 + { 1, timedia_single_port },
10740 + { 2, timedia_dual_port },
10741 + { 4, timedia_quad_port },
10742 + { 8, timedia_eight_port },
10743 + { 0, 0 }
10744 +};
10745 +
10746 +static int __devinit
10747 +pci_timedia_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10748 +{
10749 + int i, j;
10750 + unsigned short *ids;
10751 +
10752 + if (!enable)
10753 + return 0;
10754 +
10755 + for (i=0; timedia_data[i].num; i++) {
10756 + ids = timedia_data[i].ids;
10757 + for (j=0; ids[j]; j++) {
10758 + if (pci_get_subdevice(dev) == ids[j]) {
10759 + board->num_ports = timedia_data[i].num;
10760 + return 0;
10761 + }
10762 + }
10763 + }
10764 + return 0;
10765 +}
10766 +
10767 +/*
10768 + * HP's Remote Management Console. The Diva chip came in several
10769 + * different versions. N-class, L2000 and A500 have two Diva chips, each
10770 + * with 3 UARTs (the third UART on the second chip is unused). Superdome
10771 + * and Keystone have one Diva chip with 3 UARTs. Some later machines have
10772 + * one Diva chip, but it has been expanded to 5 UARTs.
10773 + */
10774 +static int __devinit
10775 +pci_hp_diva(struct pci_dev *dev, struct pci_board *board, int enable)
10776 +{
10777 + if (!enable)
10778 + return 0;
10779 +
10780 + switch (dev->subsystem_device) {
10781 + case 0x1049: /* Prelude Diva 1 */
10782 + case 0x1223: /* Superdome */
10783 + case 0x1226: /* Keystone */
10784 + case 0x1282: /* Everest / Longs Peak */
10785 + board->num_ports = 3;
10786 + break;
10787 + case 0x104A: /* Prelude Diva 2 */
10788 + board->num_ports = 2;
10789 + break;
10790 + case 0x104B: /* Maestro */
10791 + board->num_ports = 4;
10792 + break;
10793 + case 0x1227: /* Powerbar */
10794 + board->num_ports = 1;
10795 + break;
10796 + }
10797 +
10798 + return 0;
10799 +}
10800 +
10801 +static int __devinit
10802 +pci_xircom_fn(struct pci_dev *dev, struct pci_board *board, int enable)
10803 +{
10804 + __set_current_state(TASK_UNINTERRUPTIBLE);
10805 + schedule_timeout(HZ/10);
10806 + return 0;
10807 +}
10808 +
10809 +/*
10810 + * This is the configuration table for all of the PCI serial boards
10811 + * which we support. It is directly indexed by the pci_board_num_t enum
10812 + * value, which is encoded in the pci_device_id PCI probe table's
10813 + * driver_data member.
10814 + */
10815 +enum pci_board_num_t {
10816 + pbn_b0_1_115200,
10817 + pbn_default = 0,
10818 +
10819 + pbn_b0_2_115200,
10820 + pbn_b0_4_115200,
10821 +
10822 + pbn_b0_1_921600,
10823 + pbn_b0_2_921600,
10824 + pbn_b0_4_921600,
10825 +
10826 + pbn_b0_bt_1_115200,
10827 + pbn_b0_bt_2_115200,
10828 + pbn_b0_bt_1_460800,
10829 + pbn_b0_bt_2_460800,
10830 + pbn_b0_bt_2_921600,
10831 +
10832 + pbn_b1_1_115200,
10833 + pbn_b1_2_115200,
10834 + pbn_b1_4_115200,
10835 + pbn_b1_8_115200,
10836 +
10837 + pbn_b1_2_921600,
10838 + pbn_b1_4_921600,
10839 + pbn_b1_8_921600,
10840 +
10841 + pbn_b1_2_1382400,
10842 + pbn_b1_4_1382400,
10843 + pbn_b1_8_1382400,
10844 +
10845 + pbn_b2_1_115200,
10846 + pbn_b2_8_115200,
10847 + pbn_b2_4_460800,
10848 + pbn_b2_8_460800,
10849 + pbn_b2_16_460800,
10850 + pbn_b2_4_921600,
10851 + pbn_b2_8_921600,
10852 +
10853 + pbn_b2_bt_1_115200,
10854 + pbn_b2_bt_2_115200,
10855 + pbn_b2_bt_4_115200,
10856 + pbn_b2_bt_2_921600,
10857 +
10858 + pbn_panacom,
10859 + pbn_panacom2,
10860 + pbn_panacom4,
10861 + pbn_plx_romulus,
10862 + pbn_oxsemi,
10863 + pbn_timedia,
10864 + pbn_intel_i960,
10865 + pbn_sgi_ioc3,
10866 + pbn_hp_diva,
10867 +#ifdef CONFIG_DDB5074
10868 + pbn_nec_nile4,
10869 +#endif
10870 +
10871 + pbn_dci_pccom4,
10872 + pbn_dci_pccom8,
10873 +
10874 + pbn_xircom_combo,
10875 +
10876 + pbn_siig10x_0,
10877 + pbn_siig10x_1,
10878 + pbn_siig10x_2,
10879 + pbn_siig10x_4,
10880 + pbn_siig20x_0,
10881 + pbn_siig20x_2,
10882 + pbn_siig20x_4,
10883 +
10884 + pbn_computone_4,
10885 + pbn_computone_6,
10886 + pbn_computone_8,
10887 +};
10888 +
10889 +static struct pci_board pci_boards[] __devinitdata = {
10890 + /*
10891 + * PCI Flags, Number of Ports, Base (Maximum) Baud Rate,
10892 + * Offset to get to next UART's registers,
10893 + * Register shift to use for memory-mapped I/O,
10894 + * Initialization function, first UART offset
10895 + */
10896 +
10897 + /* Generic serial board, pbn_b0_1_115200, pbn_default */
10898 + { SPCI_FL_BASE0, 1, 115200 }, /* pbn_b0_1_115200,
10899 + pbn_default */
10900 +
10901 + { SPCI_FL_BASE0, 2, 115200 }, /* pbn_b0_2_115200 */
10902 + { SPCI_FL_BASE0, 4, 115200 }, /* pbn_b0_4_115200 */
10903 +
10904 + { SPCI_FL_BASE0, 1, 921600 }, /* pbn_b0_1_921600 */
10905 + { SPCI_FL_BASE0, 2, 921600 }, /* pbn_b0_2_921600 */
10906 + { SPCI_FL_BASE0, 4, 921600 }, /* pbn_b0_4_921600 */
10907 +
10908 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b0_bt_1_115200 */
10909 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b0_bt_2_115200 */
10910 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 1, 460800 }, /* pbn_b0_bt_1_460800 */
10911 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 460800 }, /* pbn_b0_bt_2_460800 */
10912 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b0_bt_2_921600 */
10913 +
10914 + { SPCI_FL_BASE1, 1, 115200 }, /* pbn_b1_1_115200 */
10915 + { SPCI_FL_BASE1, 2, 115200 }, /* pbn_b1_2_115200 */
10916 + { SPCI_FL_BASE1, 4, 115200 }, /* pbn_b1_4_115200 */
10917 + { SPCI_FL_BASE1, 8, 115200 }, /* pbn_b1_8_115200 */
10918 +
10919 + { SPCI_FL_BASE1, 2, 921600 }, /* pbn_b1_2_921600 */
10920 + { SPCI_FL_BASE1, 4, 921600 }, /* pbn_b1_4_921600 */
10921 + { SPCI_FL_BASE1, 8, 921600 }, /* pbn_b1_8_921600 */
10922 +
10923 + { SPCI_FL_BASE1, 2, 1382400 }, /* pbn_b1_2_1382400 */
10924 + { SPCI_FL_BASE1, 4, 1382400 }, /* pbn_b1_4_1382400 */
10925 + { SPCI_FL_BASE1, 8, 1382400 }, /* pbn_b1_8_1382400 */
10926 +
10927 + { SPCI_FL_BASE2, 1, 115200 }, /* pbn_b2_1_115200 */
10928 + { SPCI_FL_BASE2, 8, 115200 }, /* pbn_b2_8_115200 */
10929 + { SPCI_FL_BASE2, 4, 460800 }, /* pbn_b2_4_460800 */
10930 + { SPCI_FL_BASE2, 8, 460800 }, /* pbn_b2_8_460800 */
10931 + { SPCI_FL_BASE2, 16, 460800 }, /* pbn_b2_16_460800 */
10932 + { SPCI_FL_BASE2, 4, 921600 }, /* pbn_b2_4_921600 */
10933 + { SPCI_FL_BASE2, 8, 921600 }, /* pbn_b2_8_921600 */
10934 +
10935 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 1, 115200 }, /* pbn_b2_bt_1_115200 */
10936 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 115200 }, /* pbn_b2_bt_2_115200 */
10937 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 115200 }, /* pbn_b2_bt_4_115200 */
10938 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600 }, /* pbn_b2_bt_2_921600 */
10939 +
10940 + { SPCI_FL_BASE2, 2, 921600, /* IOMEM */ /* pbn_panacom */
10941 + 0x400, 7, pci_plx9050_fn },
10942 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_panacom2 */
10943 + 0x400, 7, pci_plx9050_fn },
10944 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_panacom4 */
10945 + 0x400, 7, pci_plx9050_fn },
10946 + { SPCI_FL_BASE2, 4, 921600, /* pbn_plx_romulus */
10947 + 0x20, 2, pci_plx9050_fn, 0x03 },
10948 + /* This board uses the size of PCI Base region 0 to
10949 + * signal now many ports are available */
10950 + { SPCI_FL_BASE0 | SPCI_FL_REGION_SZ_CAP, 32, 115200 }, /* pbn_oxsemi */
10951 + { SPCI_FL_BASE_TABLE, 1, 921600, /* pbn_timedia */
10952 + 0, 0, pci_timedia_fn },
10953 + /* EKF addition for i960 Boards form EKF with serial port */
10954 + { SPCI_FL_BASE0, 32, 921600, /* max 256 ports */ /* pbn_intel_i960 */
10955 + 8<<2, 2, pci_inteli960ni_fn, 0x10000},
10956 + { SPCI_FL_BASE0 | SPCI_FL_IRQRESOURCE, /* pbn_sgi_ioc3 */
10957 + 1, 458333, 0, 0, 0, 0x20178 },
10958 + { SPCI_FL_BASE0, 5, 115200, 8, 0, pci_hp_diva, 0}, /* pbn_hp_diva */
10959 +#ifdef CONFIG_DDB5074
10960 + /*
10961 + * NEC Vrc-5074 (Nile 4) builtin UART.
10962 + * Conditionally compiled in since this is a motherboard device.
10963 + */
10964 + { SPCI_FL_BASE0, 1, 520833, /* pbn_nec_nile4 */
10965 + 64, 3, NULL, 0x300 },
10966 +#endif
10967 +
10968 + {SPCI_FL_BASE3, 4, 115200, 8}, /* pbn_dci_pccom4 */
10969 + {SPCI_FL_BASE3, 8, 115200, 8}, /* pbn_dci_pccom8 */
10970 +
10971 + { SPCI_FL_BASE0, 1, 115200, /* pbn_xircom_combo */
10972 + 0, 0, pci_xircom_fn },
10973 +
10974 + { SPCI_FL_BASE2, 1, 460800, /* pbn_siig10x_0 */
10975 + 0, 0, pci_siig10x_fn },
10976 + { SPCI_FL_BASE2, 1, 921600, /* pbn_siig10x_1 */
10977 + 0, 0, pci_siig10x_fn },
10978 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siig10x_2 */
10979 + 0, 0, pci_siig10x_fn },
10980 + { SPCI_FL_BASE2 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siig10x_4 */
10981 + 0, 0, pci_siig10x_fn },
10982 + { SPCI_FL_BASE0, 1, 921600, /* pbn_siix20x_0 */
10983 + 0, 0, pci_siig20x_fn },
10984 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 2, 921600, /* pbn_siix20x_2 */
10985 + 0, 0, pci_siig20x_fn },
10986 + { SPCI_FL_BASE0 | SPCI_FL_BASE_TABLE, 4, 921600, /* pbn_siix20x_4 */
10987 + 0, 0, pci_siig20x_fn },
10988 +
10989 + { SPCI_FL_BASE0, 4, 921600, /* IOMEM */ /* pbn_computone_4 */
10990 + 0x40, 2, NULL, 0x200 },
10991 + { SPCI_FL_BASE0, 6, 921600, /* IOMEM */ /* pbn_computone_6 */
10992 + 0x40, 2, NULL, 0x200 },
10993 + { SPCI_FL_BASE0, 8, 921600, /* IOMEM */ /* pbn_computone_8 */
10994 + 0x40, 2, NULL, 0x200 },
10995 +};
10996 +
10997 +/*
10998 + * Given a complete unknown PCI device, try to use some heuristics to
10999 + * guess what the configuration might be, based on the pitiful PCI
11000 + * serial specs. Returns 0 on success, 1 on failure.
11001 + */
11002 +static int __devinit serial_pci_guess_board(struct pci_dev *dev,
11003 + struct pci_board *board)
11004 +{
11005 + int num_iomem = 0, num_port = 0, first_port = -1;
11006 + int i;
11007 +
11008 + /*
11009 + * If it is not a communications device or the programming
11010 + * interface is greater than 6, give up.
11011 + *
11012 + * (Should we try to make guesses for multiport serial devices
11013 + * later?)
11014 + */
11015 + if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
11016 + ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
11017 + (dev->class & 0xff) > 6)
11018 + return 1;
11019 +
11020 + for (i=0; i < 6; i++) {
11021 + if (IS_PCI_REGION_IOPORT(dev, i)) {
11022 + num_port++;
11023 + if (first_port == -1)
11024 + first_port = i;
11025 + }
11026 + if (IS_PCI_REGION_IOMEM(dev, i))
11027 + num_iomem++;
11028 + }
11029 +
11030 + /*
11031 + * If there is 1 or 0 iomem regions, and exactly one port, use
11032 + * it.
11033 + */
11034 + if (num_iomem <= 1 && num_port == 1) {
11035 + board->flags = first_port;
11036 + return 0;
11037 + }
11038 + return 1;
11039 +}
11040 +
11041 +static int __devinit serial_init_one(struct pci_dev *dev,
11042 + const struct pci_device_id *ent)
11043 +{
11044 + struct pci_board *board, tmp;
11045 + int rc;
11046 +
11047 + board = &pci_boards[ent->driver_data];
11048 +
11049 + rc = pci_enable_device(dev);
11050 + if (rc) return rc;
11051 +
11052 + if (ent->driver_data == pbn_default &&
11053 + serial_pci_guess_board(dev, board))
11054 + return -ENODEV;
11055 + else if (serial_pci_guess_board(dev, &tmp) == 0) {
11056 + printk(KERN_INFO "Redundant entry in serial pci_table. "
11057 + "Please send the output of\n"
11058 + "lspci -vv, this message (%04x,%04x,%04x,%04x)\n"
11059 + "and the manufacturer and name of "
11060 + "serial board or modem board\n"
11061 + "to serial-pci-info@lists.sourceforge.net.\n",
11062 + dev->vendor, dev->device,
11063 + pci_get_subvendor(dev), pci_get_subdevice(dev));
11064 + }
11065 +
11066 + start_pci_pnp_board(dev, board);
11067 +
11068 + return 0;
11069 +}
11070 +
11071 +static void __devexit serial_remove_one(struct pci_dev *dev)
11072 +{
11073 + int i;
11074 +
11075 + /*
11076 + * Iterate through all of the ports finding those that belong
11077 + * to this PCI device.
11078 + */
11079 + for(i = 0; i < NR_PORTS; i++) {
11080 + if (rs_table[i].dev != dev)
11081 + continue;
11082 + unregister_serial(i);
11083 + rs_table[i].dev = 0;
11084 + }
11085 + /*
11086 + * Now execute any board-specific shutdown procedure
11087 + */
11088 + for (i=0; i < NR_PCI_BOARDS; i++) {
11089 + struct pci_board_inst *brd = &serial_pci_board[i];
11090 +
11091 + if (serial_pci_board[i].dev != dev)
11092 + continue;
11093 + if (brd->board.init_fn)
11094 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
11095 + if (DEACTIVATE_FUNC(brd->dev))
11096 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
11097 + serial_pci_board[i].dev = 0;
11098 + }
11099 +}
11100 +
11101 +
11102 +static struct pci_device_id serial_pci_tbl[] __devinitdata = {
11103 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
11104 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11105 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
11106 + pbn_b1_8_1382400 },
11107 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
11108 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11109 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
11110 + pbn_b1_4_1382400 },
11111 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
11112 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11113 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
11114 + pbn_b1_2_1382400 },
11115 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11116 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11117 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
11118 + pbn_b1_8_1382400 },
11119 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11120 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11121 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
11122 + pbn_b1_4_1382400 },
11123 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11124 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11125 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
11126 + pbn_b1_2_1382400 },
11127 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11128 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11129 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
11130 + pbn_b1_8_921600 },
11131 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11132 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11133 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
11134 + pbn_b1_8_921600 },
11135 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11136 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11137 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
11138 + pbn_b1_4_921600 },
11139 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11140 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11141 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
11142 + pbn_b1_4_921600 },
11143 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11144 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11145 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
11146 + pbn_b1_2_921600 },
11147 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11148 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11149 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
11150 + pbn_b1_8_921600 },
11151 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11152 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11153 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
11154 + pbn_b1_8_921600 },
11155 + { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
11156 + PCI_SUBVENDOR_ID_CONNECT_TECH,
11157 + PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
11158 + pbn_b1_4_921600 },
11159 +
11160 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
11161 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11162 + pbn_b2_bt_1_115200 },
11163 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
11164 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11165 + pbn_b2_bt_2_115200 },
11166 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
11167 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11168 + pbn_b2_bt_4_115200 },
11169 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
11170 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11171 + pbn_b2_bt_2_115200 },
11172 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
11173 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11174 + pbn_b2_bt_4_115200 },
11175 + { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
11176 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11177 + pbn_b2_8_115200 },
11178 +
11179 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
11180 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11181 + pbn_b2_bt_2_115200 },
11182 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
11183 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11184 + pbn_b2_bt_2_921600 },
11185 + /* VScom SPCOM800, from sl@s.pl */
11186 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
11187 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11188 + pbn_b2_8_921600 },
11189 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
11190 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11191 + pbn_b2_4_921600 },
11192 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11193 + PCI_SUBVENDOR_ID_KEYSPAN,
11194 + PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
11195 + pbn_panacom },
11196 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
11197 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11198 + pbn_panacom4 },
11199 + { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
11200 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11201 + pbn_panacom2 },
11202 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11203 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
11204 + PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
11205 + pbn_b2_4_460800 },
11206 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11207 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
11208 + PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
11209 + pbn_b2_8_460800 },
11210 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11211 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
11212 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
11213 + pbn_b2_16_460800 },
11214 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11215 + PCI_SUBVENDOR_ID_CHASE_PCIFAST,
11216 + PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
11217 + pbn_b2_16_460800 },
11218 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11219 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
11220 + PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
11221 + pbn_b2_4_460800 },
11222 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
11223 + PCI_SUBVENDOR_ID_CHASE_PCIRAS,
11224 + PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
11225 + pbn_b2_8_460800 },
11226 + /* Megawolf Romulus PCI Serial Card, from Mike Hudson */
11227 + /* (Exoray@isys.ca) */
11228 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
11229 + 0x10b5, 0x106a, 0, 0,
11230 + pbn_plx_romulus },
11231 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
11232 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11233 + pbn_b1_4_115200 },
11234 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
11235 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11236 + pbn_b1_2_115200 },
11237 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
11238 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11239 + pbn_b1_8_115200 },
11240 + { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
11241 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11242 + pbn_b1_8_115200 },
11243 + { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
11244 + PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
11245 + pbn_b0_4_921600 },
11246 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
11247 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11248 + pbn_b0_4_115200 },
11249 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
11250 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11251 + pbn_b0_bt_2_921600 },
11252 +
11253 + /* Digitan DS560-558, from jimd@esoft.com */
11254 + { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
11255 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11256 + pbn_b1_1_115200 },
11257 +
11258 + /* 3Com US Robotics 56k Voice Internal PCI model 5610 */
11259 + { PCI_VENDOR_ID_USR, 0x1008,
11260 + PCI_ANY_ID, PCI_ANY_ID, },
11261 +
11262 + /* Titan Electronic cards */
11263 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
11264 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11265 + pbn_b0_1_921600 },
11266 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
11267 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11268 + pbn_b0_2_921600 },
11269 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
11270 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11271 + pbn_b0_4_921600 },
11272 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
11273 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11274 + pbn_b0_4_921600 },
11275 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
11276 + PCI_ANY_ID, PCI_ANY_ID,
11277 + SPCI_FL_BASE1, 1, 921600 },
11278 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
11279 + PCI_ANY_ID, PCI_ANY_ID,
11280 + SPCI_FL_BASE1 | SPCI_FL_BASE_TABLE, 2, 921600 },
11281 + /* The 400L and 800L have a custom hack in get_pci_port */
11282 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
11283 + PCI_ANY_ID, PCI_ANY_ID,
11284 + SPCI_FL_BASE_TABLE, 4, 921600 },
11285 + { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
11286 + PCI_ANY_ID, PCI_ANY_ID,
11287 + SPCI_FL_BASE_TABLE, 8, 921600 },
11288 +
11289 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
11290 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11291 + pbn_siig10x_0 },
11292 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
11293 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11294 + pbn_siig10x_0 },
11295 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
11296 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11297 + pbn_siig10x_0 },
11298 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
11299 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11300 + pbn_siig10x_2 },
11301 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
11302 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11303 + pbn_siig10x_2 },
11304 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
11305 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11306 + pbn_siig10x_2 },
11307 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
11308 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11309 + pbn_siig10x_4 },
11310 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
11311 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11312 + pbn_siig10x_4 },
11313 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
11314 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11315 + pbn_siig10x_4 },
11316 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
11317 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11318 + pbn_siig20x_0 },
11319 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
11320 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11321 + pbn_siig20x_0 },
11322 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
11323 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11324 + pbn_siig20x_0 },
11325 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
11326 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11327 + pbn_siig20x_2 },
11328 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
11329 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11330 + pbn_siig20x_2 },
11331 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
11332 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11333 + pbn_siig20x_2 },
11334 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
11335 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11336 + pbn_siig20x_4 },
11337 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
11338 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11339 + pbn_siig20x_4 },
11340 + { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
11341 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11342 + pbn_siig20x_4 },
11343 +
11344 + /* Computone devices submitted by Doug McNash dmcnash@computone.com */
11345 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
11346 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
11347 + 0, 0, pbn_computone_4 },
11348 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
11349 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
11350 + 0, 0, pbn_computone_8 },
11351 + { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
11352 + PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
11353 + 0, 0, pbn_computone_6 },
11354 +
11355 + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
11356 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_oxsemi },
11357 + { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
11358 + PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, pbn_timedia },
11359 +
11360 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
11361 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11362 + pbn_b0_bt_2_115200 },
11363 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
11364 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11365 + pbn_b0_bt_2_115200 },
11366 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
11367 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11368 + pbn_b0_bt_2_115200 },
11369 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
11370 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11371 + pbn_b0_bt_2_460800 },
11372 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
11373 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11374 + pbn_b0_bt_2_460800 },
11375 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
11376 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11377 + pbn_b0_bt_2_460800 },
11378 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
11379 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11380 + pbn_b0_bt_1_115200 },
11381 + { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
11382 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11383 + pbn_b0_bt_1_460800 },
11384 +
11385 + /* RAStel 2 port modem, gerg@moreton.com.au */
11386 + { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
11387 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11388 + pbn_b2_bt_2_115200 },
11389 +
11390 + /* EKF addition for i960 Boards form EKF with serial port */
11391 + { PCI_VENDOR_ID_INTEL, 0x1960,
11392 + 0xE4BF, PCI_ANY_ID, 0, 0,
11393 + pbn_intel_i960 },
11394 +
11395 + /* Xircom Cardbus/Ethernet combos */
11396 + { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
11397 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11398 + pbn_xircom_combo },
11399 +
11400 + /*
11401 + * Untested PCI modems, sent in from various folks...
11402 + */
11403 +
11404 + /* Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> */
11405 + { PCI_VENDOR_ID_ROCKWELL, 0x1004,
11406 + 0x1048, 0x1500, 0, 0,
11407 + pbn_b1_1_115200 },
11408 +
11409 + { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
11410 + 0xFF00, 0, 0, 0,
11411 + pbn_sgi_ioc3 },
11412 +
11413 + /* HP Diva card */
11414 + { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_SAS,
11415 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11416 + pbn_hp_diva },
11417 + { PCI_VENDOR_ID_HP, 0x1290,
11418 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11419 + pbn_b2_1_115200 },
11420 +
11421 +#ifdef CONFIG_DDB5074
11422 + /*
11423 + * NEC Vrc-5074 (Nile 4) builtin UART.
11424 + * Conditionally compiled in since this is a motherboard device.
11425 + */
11426 + { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
11427 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11428 + pbn_nec_nile4 },
11429 +#endif
11430 +
11431 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
11432 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11433 + pbn_dci_pccom4 },
11434 + { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
11435 + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
11436 + pbn_dci_pccom8 },
11437 +
11438 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
11439 + PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, },
11440 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
11441 + PCI_CLASS_COMMUNICATION_MODEM << 8, 0xffff00, },
11442 + { 0, }
11443 +};
11444 +
11445 +MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
11446 +
11447 +static struct pci_driver serial_pci_driver = {
11448 + name: "serial",
11449 + probe: serial_init_one,
11450 + remove: __devexit_p(serial_remove_one),
11451 + id_table: serial_pci_tbl,
11452 +};
11453 +
11454 +
11455 +/*
11456 + * Query PCI space for known serial boards
11457 + * If found, add them to the PCI device space in rs_table[]
11458 + *
11459 + * Accept a maximum of eight boards
11460 + *
11461 + */
11462 +static void __devinit probe_serial_pci(void)
11463 +{
11464 +#ifdef SERIAL_DEBUG_PCI
11465 + printk(KERN_DEBUG "Entered probe_serial_pci()\n");
11466 +#endif
11467 +
11468 + /* Register call PCI serial devices. Null out
11469 + * the driver name upon failure, as a signal
11470 + * not to attempt to unregister the driver later
11471 + */
11472 + if (pci_module_init (&serial_pci_driver) != 0)
11473 + serial_pci_driver.name = "";
11474 +
11475 +#ifdef SERIAL_DEBUG_PCI
11476 + printk(KERN_DEBUG "Leaving probe_serial_pci() (probe finished)\n");
11477 +#endif
11478 + return;
11479 +}
11480 +
11481 +#endif /* ENABLE_SERIAL_PCI */
11482 +
11483 +#ifdef ENABLE_SERIAL_PNP
11484 +
11485 +struct pnp_board {
11486 + unsigned short vendor;
11487 + unsigned short device;
11488 +};
11489 +
11490 +static struct pnp_board pnp_devices[] __devinitdata = {
11491 + /* Archtek America Corp. */
11492 + /* Archtek SmartLink Modem 3334BT Plug & Play */
11493 + { ISAPNP_VENDOR('A', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
11494 + /* Anchor Datacomm BV */
11495 + /* SXPro 144 External Data Fax Modem Plug & Play */
11496 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0001) },
11497 + /* SXPro 288 External Data Fax Modem Plug & Play */
11498 + { ISAPNP_VENDOR('A', 'D', 'C'), ISAPNP_DEVICE(0x0002) },
11499 + /* Rockwell 56K ACF II Fax+Data+Voice Modem */
11500 + { ISAPNP_VENDOR('A', 'K', 'Y'), ISAPNP_DEVICE(0x1021) },
11501 + /* AZT3005 PnP SOUND DEVICE */
11502 + { ISAPNP_VENDOR('A', 'Z', 'T'), ISAPNP_DEVICE(0x4001) },
11503 + /* Best Data Products Inc. Smart One 336F PnP Modem */
11504 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
11505 + /* Boca Research */
11506 + /* Boca Complete Ofc Communicator 14.4 Data-FAX */
11507 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
11508 + /* Boca Research 33,600 ACF Modem */
11509 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x1400) },
11510 + /* Boca 33.6 Kbps Internal FD34FSVD */
11511 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x3400) },
11512 + /* Boca 33.6 Kbps Internal FD34FSVD */
11513 + { ISAPNP_VENDOR('B', 'R', 'I'), ISAPNP_DEVICE(0x0A49) },
11514 + /* Best Data Products Inc. Smart One 336F PnP Modem */
11515 + { ISAPNP_VENDOR('B', 'D', 'P'), ISAPNP_DEVICE(0x3336) },
11516 + /* Computer Peripherals Inc */
11517 + /* EuroViVa CommCenter-33.6 SP PnP */
11518 + { ISAPNP_VENDOR('C', 'P', 'I'), ISAPNP_DEVICE(0x4050) },
11519 + /* Creative Labs */
11520 + /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
11521 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3001) },
11522 + /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
11523 + { ISAPNP_VENDOR('C', 'T', 'L'), ISAPNP_DEVICE(0x3011) },
11524 + /* Creative */
11525 + /* Creative Modem Blaster Flash56 DI5601-1 */
11526 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x1032) },
11527 + /* Creative Modem Blaster V.90 DI5660 */
11528 + { ISAPNP_VENDOR('D', 'M', 'B'), ISAPNP_DEVICE(0x2001) },
11529 + /* FUJITSU */
11530 + /* Fujitsu 33600 PnP-I2 R Plug & Play */
11531 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0202) },
11532 + /* Fujitsu FMV-FX431 Plug & Play */
11533 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0205) },
11534 + /* Fujitsu 33600 PnP-I4 R Plug & Play */
11535 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0206) },
11536 + /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
11537 + { ISAPNP_VENDOR('F', 'U', 'J'), ISAPNP_DEVICE(0x0209) },
11538 + /* Archtek America Corp. */
11539 + /* Archtek SmartLink Modem 3334BT Plug & Play */
11540 + { ISAPNP_VENDOR('G', 'V', 'C'), ISAPNP_DEVICE(0x000F) },
11541 + /* Hayes */
11542 + /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
11543 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x0001) },
11544 + /* Hayes Optima 336 V.34 + FAX + Voice PnP */
11545 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000C) },
11546 + /* Hayes Optima 336B V.34 + FAX + Voice PnP */
11547 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x000D) },
11548 + /* Hayes Accura 56K Ext Fax Modem PnP */
11549 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5670) },
11550 + /* Hayes Accura 56K Ext Fax Modem PnP */
11551 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5674) },
11552 + /* Hayes Accura 56K Fax Modem PnP */
11553 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0x5675) },
11554 + /* Hayes 288, V.34 + FAX */
11555 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF000) },
11556 + /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
11557 + { ISAPNP_VENDOR('H', 'A', 'Y'), ISAPNP_DEVICE(0xF001) },
11558 + /* IBM */
11559 + /* IBM Thinkpad 701 Internal Modem Voice */
11560 + { ISAPNP_VENDOR('I', 'B', 'M'), ISAPNP_DEVICE(0x0033) },
11561 + /* Intertex */
11562 + /* Intertex 28k8 33k6 Voice EXT PnP */
11563 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC801) },
11564 + /* Intertex 33k6 56k Voice EXT PnP */
11565 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xC901) },
11566 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
11567 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD801) },
11568 + /* Intertex 33k6 56k Voice SP EXT PnP */
11569 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xD901) },
11570 + /* Intertex 28k8 33k6 Voice SP INT PnP */
11571 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF401) },
11572 + /* Intertex 28k8 33k6 Voice SP EXT PnP */
11573 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF801) },
11574 + /* Intertex 33k6 56k Voice SP EXT PnP */
11575 + { ISAPNP_VENDOR('I', 'X', 'D'), ISAPNP_DEVICE(0xF901) },
11576 + /* Kortex International */
11577 + /* KORTEX 28800 Externe PnP */
11578 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0x4522) },
11579 + /* KXPro 33.6 Vocal ASVD PnP */
11580 + { ISAPNP_VENDOR('K', 'O', 'R'), ISAPNP_DEVICE(0xF661) },
11581 + /* Lasat */
11582 + /* LASAT Internet 33600 PnP */
11583 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4040) },
11584 + /* Lasat Safire 560 PnP */
11585 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x4540) },
11586 + /* Lasat Safire 336 PnP */
11587 + { ISAPNP_VENDOR('L', 'A', 'S'), ISAPNP_DEVICE(0x5440) },
11588 + /* Microcom, Inc. */
11589 + /* Microcom TravelPorte FAST V.34 Plug & Play */
11590 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x281) },
11591 + /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
11592 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0336) },
11593 + /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
11594 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0339) },
11595 + /* Microcom DeskPorte 28.8P Plug & Play */
11596 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0342) },
11597 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
11598 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
11599 + /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
11600 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
11601 + /* Microcom DeskPorte 28.8S Internal Plug & Play */
11602 + { ISAPNP_VENDOR('M', 'N', 'P'), ISAPNP_DEVICE(0x0502) },
11603 + /* Motorola */
11604 + /* Motorola BitSURFR Plug & Play */
11605 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1105) },
11606 + /* Motorola TA210 Plug & Play */
11607 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1111) },
11608 + /* Motorola HMTA 200 (ISDN) Plug & Play */
11609 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1114) },
11610 + /* Motorola BitSURFR Plug & Play */
11611 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1115) },
11612 + /* Motorola Lifestyle 28.8 Internal */
11613 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1190) },
11614 + /* Motorola V.3400 Plug & Play */
11615 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1501) },
11616 + /* Motorola Lifestyle 28.8 V.34 Plug & Play */
11617 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1502) },
11618 + /* Motorola Power 28.8 V.34 Plug & Play */
11619 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1505) },
11620 + /* Motorola ModemSURFR External 28.8 Plug & Play */
11621 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1509) },
11622 + /* Motorola Premier 33.6 Desktop Plug & Play */
11623 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150A) },
11624 + /* Motorola VoiceSURFR 56K External PnP */
11625 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x150F) },
11626 + /* Motorola ModemSURFR 56K External PnP */
11627 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1510) },
11628 + /* Motorola ModemSURFR 56K Internal PnP */
11629 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1550) },
11630 + /* Motorola ModemSURFR Internal 28.8 Plug & Play */
11631 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1560) },
11632 + /* Motorola Premier 33.6 Internal Plug & Play */
11633 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x1580) },
11634 + /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
11635 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15B0) },
11636 + /* Motorola VoiceSURFR 56K Internal PnP */
11637 + { ISAPNP_VENDOR('M', 'O', 'T'), ISAPNP_DEVICE(0x15F0) },
11638 + /* Com 1 */
11639 + /* Deskline K56 Phone System PnP */
11640 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00A1) },
11641 + /* PC Rider K56 Phone System PnP */
11642 + { ISAPNP_VENDOR('M', 'V', 'X'), ISAPNP_DEVICE(0x00F2) },
11643 + /* Pace 56 Voice Internal Plug & Play Modem */
11644 + { ISAPNP_VENDOR('P', 'M', 'C'), ISAPNP_DEVICE(0x2430) },
11645 + /* Generic */
11646 + /* Generic standard PC COM port */
11647 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0500) },
11648 + /* Generic 16550A-compatible COM port */
11649 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x0501) },
11650 + /* Compaq 14400 Modem */
11651 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC000) },
11652 + /* Compaq 2400/9600 Modem */
11653 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC001) },
11654 + /* Dial-Up Networking Serial Cable between 2 PCs */
11655 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC031) },
11656 + /* Dial-Up Networking Parallel Cable between 2 PCs */
11657 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC032) },
11658 + /* Standard 9600 bps Modem */
11659 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC100) },
11660 + /* Standard 14400 bps Modem */
11661 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC101) },
11662 + /* Standard 28800 bps Modem*/
11663 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC102) },
11664 + /* Standard Modem*/
11665 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC103) },
11666 + /* Standard 9600 bps Modem*/
11667 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC104) },
11668 + /* Standard 14400 bps Modem*/
11669 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC105) },
11670 + /* Standard 28800 bps Modem*/
11671 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC106) },
11672 + /* Standard Modem */
11673 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC107) },
11674 + /* Standard 9600 bps Modem */
11675 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC108) },
11676 + /* Standard 14400 bps Modem */
11677 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC109) },
11678 + /* Standard 28800 bps Modem */
11679 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10A) },
11680 + /* Standard Modem */
11681 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10B) },
11682 + /* Standard 9600 bps Modem */
11683 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10C) },
11684 + /* Standard 14400 bps Modem */
11685 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10D) },
11686 + /* Standard 28800 bps Modem */
11687 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10E) },
11688 + /* Standard Modem */
11689 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0xC10F) },
11690 + /* Standard PCMCIA Card Modem */
11691 + { ISAPNP_VENDOR('P', 'N', 'P'), ISAPNP_DEVICE(0x2000) },
11692 + /* Rockwell */
11693 + /* Modular Technology */
11694 + /* Rockwell 33.6 DPF Internal PnP */
11695 + /* Modular Technology 33.6 Internal PnP */
11696 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0030) },
11697 + /* Kortex International */
11698 + /* KORTEX 14400 Externe PnP */
11699 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x0100) },
11700 + /* Viking Components, Inc */
11701 + /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
11702 + { ISAPNP_VENDOR('R', 'O', 'K'), ISAPNP_DEVICE(0x4920) },
11703 + /* Rockwell */
11704 + /* British Telecom */
11705 + /* Modular Technology */
11706 + /* Rockwell 33.6 DPF External PnP */
11707 + /* BT Prologue 33.6 External PnP */
11708 + /* Modular Technology 33.6 External PnP */
11709 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x00A0) },
11710 + /* Viking 56K FAX INT */
11711 + { ISAPNP_VENDOR('R', 'S', 'S'), ISAPNP_DEVICE(0x0262) },
11712 + /* SupraExpress 28.8 Data/Fax PnP modem */
11713 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1310) },
11714 + /* SupraExpress 33.6 Data/Fax PnP modem */
11715 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1421) },
11716 + /* SupraExpress 33.6 Data/Fax PnP modem */
11717 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1590) },
11718 + /* SupraExpress 33.6 Data/Fax PnP modem */
11719 + { ISAPNP_VENDOR('S', 'U', 'P'), ISAPNP_DEVICE(0x1760) },
11720 + /* Phoebe Micro */
11721 + /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
11722 + { ISAPNP_VENDOR('T', 'E', 'X'), ISAPNP_DEVICE(0x0011) },
11723 + /* Archtek America Corp. */
11724 + /* Archtek SmartLink Modem 3334BT Plug & Play */
11725 + { ISAPNP_VENDOR('U', 'A', 'C'), ISAPNP_DEVICE(0x000F) },
11726 + /* 3Com Corp. */
11727 + /* Gateway Telepath IIvi 33.6 */
11728 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0000) },
11729 + /* Sportster Vi 14.4 PnP FAX Voicemail */
11730 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0004) },
11731 + /* U.S. Robotics 33.6K Voice INT PnP */
11732 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0006) },
11733 + /* U.S. Robotics 33.6K Voice EXT PnP */
11734 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x0007) },
11735 + /* U.S. Robotics 33.6K Voice INT PnP */
11736 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2002) },
11737 + /* U.S. Robotics 56K Voice INT PnP */
11738 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2070) },
11739 + /* U.S. Robotics 56K Voice EXT PnP */
11740 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x2080) },
11741 + /* U.S. Robotics 56K FAX INT */
11742 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3031) },
11743 + /* U.S. Robotics 56K Voice INT PnP */
11744 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3070) },
11745 + /* U.S. Robotics 56K Voice EXT PnP */
11746 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3080) },
11747 + /* U.S. Robotics 56K Voice INT PnP */
11748 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x3090) },
11749 + /* U.S. Robotics 56K Message */
11750 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9100) },
11751 + /* U.S. Robotics 56K FAX EXT PnP*/
11752 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9160) },
11753 + /* U.S. Robotics 56K FAX INT PnP*/
11754 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9170) },
11755 + /* U.S. Robotics 56K Voice EXT PnP*/
11756 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9180) },
11757 + /* U.S. Robotics 56K Voice INT PnP*/
11758 + { ISAPNP_VENDOR('U', 'S', 'R'), ISAPNP_DEVICE(0x9190) },
11759 + { 0, }
11760 +};
11761 +
11762 +static inline void avoid_irq_share(struct pci_dev *dev)
11763 +{
11764 + int i, map = 0x1FF8;
11765 + struct serial_state *state = rs_table;
11766 + struct isapnp_irq *irq;
11767 + struct isapnp_resources *res = dev->sysdata;
11768 +
11769 + for (i = 0; i < NR_PORTS; i++) {
11770 + if (state->type != PORT_UNKNOWN)
11771 + clear_bit(state->irq, &map);
11772 + state++;
11773 + }
11774 +
11775 + for ( ; res; res = res->alt)
11776 + for(irq = res->irq; irq; irq = irq->next)
11777 + irq->map = map;
11778 +}
11779 +
11780 +static char *modem_names[] __devinitdata = {
11781 + "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
11782 + "56K", "56k", "K56", "33.6", "28.8", "14.4",
11783 + "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
11784 + "33600", "28800", "14400", "V.90", "V.34", "V.32", 0
11785 +};
11786 +
11787 +static int __devinit check_name(char *name)
11788 +{
11789 + char **tmp = modem_names;
11790 +
11791 + while (*tmp) {
11792 + if (strstr(name, *tmp))
11793 + return 1;
11794 + tmp++;
11795 + }
11796 + return 0;
11797 +}
11798 +
11799 +static inline int check_compatible_id(struct pci_dev *dev)
11800 +{
11801 + int i;
11802 + for (i = 0; i < DEVICE_COUNT_COMPATIBLE; i++)
11803 + if ((dev->vendor_compatible[i] ==
11804 + ISAPNP_VENDOR('P', 'N', 'P')) &&
11805 + (swab16(dev->device_compatible[i]) >= 0xc000) &&
11806 + (swab16(dev->device_compatible[i]) <= 0xdfff))
11807 + return 0;
11808 + return 1;
11809 +}
11810 +
11811 +/*
11812 + * Given a complete unknown ISA PnP device, try to use some heuristics to
11813 + * detect modems. Currently use such heuristic set:
11814 + * - dev->name or dev->bus->name must contain "modem" substring;
11815 + * - device must have only one IO region (8 byte long) with base adress
11816 + * 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
11817 + *
11818 + * Such detection looks very ugly, but can detect at least some of numerous
11819 + * ISA PnP modems, alternatively we must hardcode all modems in pnp_devices[]
11820 + * table.
11821 + */
11822 +static int _INLINE_ serial_pnp_guess_board(struct pci_dev *dev,
11823 + struct pci_board *board)
11824 +{
11825 + struct isapnp_resources *res = (struct isapnp_resources *)dev->sysdata;
11826 + struct isapnp_resources *resa;
11827 +
11828 + if (!(check_name(dev->name) || check_name(dev->bus->name)) &&
11829 + !(check_compatible_id(dev)))
11830 + return 1;
11831 +
11832 + if (!res || res->next)
11833 + return 1;
11834 +
11835 + for (resa = res->alt; resa; resa = resa->alt) {
11836 + struct isapnp_port *port;
11837 + for (port = res->port; port; port = port->next)
11838 + if ((port->size == 8) &&
11839 + ((port->min == 0x2f8) ||
11840 + (port->min == 0x3f8) ||
11841 + (port->min == 0x2e8) ||
11842 + (port->min == 0x3e8)))
11843 + return 0;
11844 + }
11845 +
11846 + return 1;
11847 +}
11848 +
11849 +static void __devinit probe_serial_pnp(void)
11850 +{
11851 + struct pci_dev *dev = NULL;
11852 + struct pnp_board *pnp_board;
11853 + struct pci_board board;
11854 +
11855 +#ifdef SERIAL_DEBUG_PNP
11856 + printk("Entered probe_serial_pnp()\n");
11857 +#endif
11858 + if (!isapnp_present()) {
11859 +#ifdef SERIAL_DEBUG_PNP
11860 + printk("Leaving probe_serial_pnp() (no isapnp)\n");
11861 +#endif
11862 + return;
11863 + }
11864 +
11865 + isapnp_for_each_dev(dev) {
11866 + if (dev->active)
11867 + continue;
11868 +
11869 + memset(&board, 0, sizeof(board));
11870 + board.flags = SPCI_FL_BASE0 | SPCI_FL_PNPDEFAULT;
11871 + board.num_ports = 1;
11872 + board.base_baud = 115200;
11873 +
11874 + for (pnp_board = pnp_devices; pnp_board->vendor; pnp_board++)
11875 + if ((dev->vendor == pnp_board->vendor) &&
11876 + (dev->device == pnp_board->device))
11877 + break;
11878 +
11879 + if (pnp_board->vendor) {
11880 + /* Special case that's more efficient to hardcode */
11881 + if ((pnp_board->vendor == ISAPNP_VENDOR('A', 'K', 'Y') &&
11882 + pnp_board->device == ISAPNP_DEVICE(0x1021)))
11883 + board.flags |= SPCI_FL_NO_SHIRQ;
11884 + } else {
11885 + if (serial_pnp_guess_board(dev, &board))
11886 + continue;
11887 + }
11888 +
11889 + if (board.flags & SPCI_FL_NO_SHIRQ)
11890 + avoid_irq_share(dev);
11891 + start_pci_pnp_board(dev, &board);
11892 + }
11893 +
11894 +#ifdef SERIAL_DEBUG_PNP
11895 + printk("Leaving probe_serial_pnp() (probe finished)\n");
11896 +#endif
11897 + return;
11898 +}
11899 +
11900 +#endif /* ENABLE_SERIAL_PNP */
11901 +
11902 +/*
11903 + * The serial driver boot-time initialization code!
11904 + */
11905 +static int __init rs_init(void)
11906 +{
11907 + int i;
11908 + struct serial_state * state;
11909 +
11910 + init_bh(SERIAL_BH, do_serial_bh);
11911 + init_timer(&serial_timer);
11912 + serial_timer.function = rs_timer;
11913 + mod_timer(&serial_timer, jiffies + RS_STROBE_TIME);
11914 +
11915 + for (i = 0; i < NR_IRQS; i++) {
11916 + IRQ_ports[i] = 0;
11917 + IRQ_timeout[i] = 0;
11918 +#ifdef CONFIG_SERIAL_MULTIPORT
11919 + memset(&rs_multiport[i], 0,
11920 + sizeof(struct rs_multiport_struct));
11921 +#endif
11922 + }
11923 + show_serial_version();
11924 +
11925 + /* Initialize the tty_driver structure */
11926 +
11927 + memset(&serial_driver, 0, sizeof(struct tty_driver));
11928 + serial_driver.magic = TTY_DRIVER_MAGIC;
11929 +#if (LINUX_VERSION_CODE > 0x20100)
11930 + serial_driver.driver_name = "serial";
11931 +#endif
11932 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11933 + serial_driver.name = "tts/%d";
11934 +#else
11935 + serial_driver.name = "ttyS";
11936 +#endif
11937 + serial_driver.major = TTY_MAJOR;
11938 + serial_driver.minor_start = 64 + SERIAL_DEV_OFFSET;
11939 + serial_driver.name_base = SERIAL_DEV_OFFSET;
11940 + serial_driver.num = NR_PORTS;
11941 + serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
11942 + serial_driver.subtype = SERIAL_TYPE_NORMAL;
11943 + serial_driver.init_termios = tty_std_termios;
11944 + serial_driver.init_termios.c_cflag =
11945 + B9600 | CS8 | CREAD | HUPCL | CLOCAL;
11946 + serial_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
11947 + serial_driver.refcount = &serial_refcount;
11948 + serial_driver.table = serial_table;
11949 + serial_driver.termios = serial_termios;
11950 + serial_driver.termios_locked = serial_termios_locked;
11951 +
11952 + serial_driver.open = rs_open;
11953 + serial_driver.close = rs_close;
11954 + serial_driver.write = rs_write;
11955 + serial_driver.put_char = rs_put_char;
11956 + serial_driver.flush_chars = rs_flush_chars;
11957 + serial_driver.write_room = rs_write_room;
11958 + serial_driver.chars_in_buffer = rs_chars_in_buffer;
11959 + serial_driver.flush_buffer = rs_flush_buffer;
11960 + serial_driver.ioctl = rs_ioctl;
11961 + serial_driver.throttle = rs_throttle;
11962 + serial_driver.unthrottle = rs_unthrottle;
11963 + serial_driver.set_termios = rs_set_termios;
11964 + serial_driver.stop = rs_stop;
11965 + serial_driver.start = rs_start;
11966 + serial_driver.hangup = rs_hangup;
11967 +#if (LINUX_VERSION_CODE >= 131394) /* Linux 2.1.66 */
11968 + serial_driver.break_ctl = rs_break;
11969 +#endif
11970 +#if (LINUX_VERSION_CODE >= 131343)
11971 + serial_driver.send_xchar = rs_send_xchar;
11972 + serial_driver.wait_until_sent = rs_wait_until_sent;
11973 + serial_driver.read_proc = rs_read_proc;
11974 +#endif
11975 +
11976 + /*
11977 + * The callout device is just like normal device except for
11978 + * major number and the subtype code.
11979 + */
11980 + callout_driver = serial_driver;
11981 +#if (LINUX_VERSION_CODE > 0x2032D && defined(CONFIG_DEVFS_FS))
11982 + callout_driver.name = "cua/%d";
11983 +#else
11984 + callout_driver.name = "cua";
11985 +#endif
11986 + callout_driver.major = TTYAUX_MAJOR;
11987 + callout_driver.subtype = SERIAL_TYPE_CALLOUT;
11988 +#if (LINUX_VERSION_CODE >= 131343)
11989 + callout_driver.read_proc = 0;
11990 + callout_driver.proc_entry = 0;
11991 +#endif
11992 +
11993 + if (tty_register_driver(&serial_driver))
11994 + panic("Couldn't register serial driver\n");
11995 + if (tty_register_driver(&callout_driver))
11996 + panic("Couldn't register callout driver\n");
11997 +
11998 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
11999 + state->magic = SSTATE_MAGIC;
12000 + state->line = i;
12001 + state->type = PORT_UNKNOWN;
12002 + state->custom_divisor = 0;
12003 + state->close_delay = 5*HZ/10;
12004 + state->closing_wait = 30*HZ;
12005 + state->callout_termios = callout_driver.init_termios;
12006 + state->normal_termios = serial_driver.init_termios;
12007 + state->icount.cts = state->icount.dsr =
12008 + state->icount.rng = state->icount.dcd = 0;
12009 + state->icount.rx = state->icount.tx = 0;
12010 + state->icount.frame = state->icount.parity = 0;
12011 + state->icount.overrun = state->icount.brk = 0;
12012 + state->irq = irq_cannonicalize(state->irq);
12013 + if (state->hub6)
12014 + state->io_type = SERIAL_IO_HUB6;
12015 + if (state->port && check_region(state->port,8))
12016 + continue;
12017 +#ifdef CONFIG_MCA
12018 + if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
12019 + continue;
12020 +#endif
12021 + if (state->flags & ASYNC_BOOT_AUTOCONF)
12022 + autoconfig(state);
12023 + }
12024 + for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
12025 + if (state->type == PORT_UNKNOWN)
12026 + continue;
12027 + if ( (state->flags & ASYNC_BOOT_AUTOCONF)
12028 + && (state->flags & ASYNC_AUTO_IRQ)
12029 + && (state->port != 0 || state->iomem_base != 0))
12030 + state->irq = detect_uart_irq(state);
12031 + if (state->io_type == SERIAL_IO_MEM) {
12032 + printk(KERN_INFO"ttyS%02d%s at 0x%p (irq = %d) is a %s\n",
12033 + state->line + SERIAL_DEV_OFFSET,
12034 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
12035 + state->iomem_base, state->irq,
12036 + uart_config[state->type].name);
12037 + }
12038 + else {
12039 + printk(KERN_INFO "ttyS%02d%s at 0x%04lx (irq = %d) is a %s\n",
12040 + state->line + SERIAL_DEV_OFFSET,
12041 + (state->flags & ASYNC_FOURPORT) ? " FourPort" : "",
12042 + state->port, state->irq,
12043 + uart_config[state->type].name);
12044 + }
12045 + tty_register_devfs(&serial_driver, 0,
12046 + serial_driver.minor_start + state->line);
12047 + tty_register_devfs(&callout_driver, 0,
12048 + callout_driver.minor_start + state->line);
12049 + }
12050 +#ifdef ENABLE_SERIAL_PCI
12051 + probe_serial_pci();
12052 +#endif
12053 +#ifdef ENABLE_SERIAL_PNP
12054 + probe_serial_pnp();
12055 +#endif
12056 + return 0;
12057 +}
12058 +
12059 +/*
12060 + * This is for use by architectures that know their serial console
12061 + * attributes only at run time. Not to be invoked after rs_init().
12062 + */
12063 +int __init early_serial_setup(struct serial_struct *req)
12064 +{
12065 + int i = req->line;
12066 +
12067 + if (i >= NR_IRQS)
12068 + return(-ENOENT);
12069 + rs_table[i].magic = 0;
12070 + rs_table[i].baud_base = req->baud_base;
12071 + rs_table[i].port = req->port;
12072 + if (HIGH_BITS_OFFSET)
12073 + rs_table[i].port += (unsigned long) req->port_high <<
12074 + HIGH_BITS_OFFSET;
12075 + rs_table[i].irq = req->irq;
12076 + rs_table[i].flags = req->flags;
12077 + rs_table[i].close_delay = req->close_delay;
12078 + rs_table[i].io_type = req->io_type;
12079 + rs_table[i].hub6 = req->hub6;
12080 + rs_table[i].iomem_base = req->iomem_base;
12081 + rs_table[i].iomem_reg_shift = req->iomem_reg_shift;
12082 + rs_table[i].type = req->type;
12083 + rs_table[i].xmit_fifo_size = req->xmit_fifo_size;
12084 + rs_table[i].custom_divisor = req->custom_divisor;
12085 + rs_table[i].closing_wait = req->closing_wait;
12086 + return(0);
12087 +}
12088 +
12089 +/*
12090 + * register_serial and unregister_serial allows for 16x50 serial ports to be
12091 + * configured at run-time, to support PCMCIA modems.
12092 + */
12093 +
12094 +/**
12095 + * register_serial - configure a 16x50 serial port at runtime
12096 + * @req: request structure
12097 + *
12098 + * Configure the serial port specified by the request. If the
12099 + * port exists and is in use an error is returned. If the port
12100 + * is not currently in the table it is added.
12101 + *
12102 + * The port is then probed and if neccessary the IRQ is autodetected
12103 + * If this fails an error is returned.
12104 + *
12105 + * On success the port is ready to use and the line number is returned.
12106 + */
12107 +
12108 +int register_serial(struct serial_struct *req)
12109 +{
12110 + int i;
12111 + unsigned long flags;
12112 + struct serial_state *state;
12113 + struct async_struct *info;
12114 + unsigned long port;
12115 +
12116 + port = req->port;
12117 + if (HIGH_BITS_OFFSET)
12118 + port += (unsigned long) req->port_high << HIGH_BITS_OFFSET;
12119 +
12120 + save_flags(flags); cli();
12121 + for (i = 0; i < NR_PORTS; i++) {
12122 + if ((rs_table[i].port == port) &&
12123 + (rs_table[i].iomem_base == req->iomem_base))
12124 + break;
12125 + }
12126 +#ifdef __i386__
12127 + if (i == NR_PORTS) {
12128 + for (i = 4; i < NR_PORTS; i++)
12129 + if ((rs_table[i].type == PORT_UNKNOWN) &&
12130 + (rs_table[i].count == 0))
12131 + break;
12132 + }
12133 +#endif
12134 + if (i == NR_PORTS) {
12135 + for (i = 0; i < NR_PORTS; i++)
12136 + if ((rs_table[i].type == PORT_UNKNOWN) &&
12137 + (rs_table[i].count == 0))
12138 + break;
12139 + }
12140 + if (i == NR_PORTS) {
12141 + restore_flags(flags);
12142 + return -1;
12143 + }
12144 + state = &rs_table[i];
12145 + if (rs_table[i].count) {
12146 + restore_flags(flags);
12147 + printk("Couldn't configure serial #%d (port=%ld,irq=%d): "
12148 + "device already open\n", i, port, req->irq);
12149 + return -1;
12150 + }
12151 + state->irq = req->irq;
12152 + state->port = port;
12153 + state->flags = req->flags;
12154 + state->io_type = req->io_type;
12155 + state->iomem_base = req->iomem_base;
12156 + state->iomem_reg_shift = req->iomem_reg_shift;
12157 + if (req->baud_base)
12158 + state->baud_base = req->baud_base;
12159 + if ((info = state->info) != NULL) {
12160 + info->port = port;
12161 + info->flags = req->flags;
12162 + info->io_type = req->io_type;
12163 + info->iomem_base = req->iomem_base;
12164 + info->iomem_reg_shift = req->iomem_reg_shift;
12165 + }
12166 + autoconfig(state);
12167 + if (state->type == PORT_UNKNOWN) {
12168 + restore_flags(flags);
12169 + printk("register_serial(): autoconfig failed\n");
12170 + return -1;
12171 + }
12172 + restore_flags(flags);
12173 +
12174 + if ((state->flags & ASYNC_AUTO_IRQ) && CONFIGURED_SERIAL_PORT(state))
12175 + state->irq = detect_uart_irq(state);
12176 +
12177 + printk(KERN_INFO "ttyS%02d at %s 0x%04lx (irq = %d) is a %s\n",
12178 + state->line + SERIAL_DEV_OFFSET,
12179 + state->iomem_base ? "iomem" : "port",
12180 + state->iomem_base ? (unsigned long)state->iomem_base :
12181 + state->port, state->irq, uart_config[state->type].name);
12182 + tty_register_devfs(&serial_driver, 0,
12183 + serial_driver.minor_start + state->line);
12184 + tty_register_devfs(&callout_driver, 0,
12185 + callout_driver.minor_start + state->line);
12186 + return state->line + SERIAL_DEV_OFFSET;
12187 +}
12188 +
12189 +/**
12190 + * unregister_serial - deconfigure a 16x50 serial port
12191 + * @line: line to deconfigure
12192 + *
12193 + * The port specified is deconfigured and its resources are freed. Any
12194 + * user of the port is disconnected as if carrier was dropped. Line is
12195 + * the port number returned by register_serial().
12196 + */
12197 +
12198 +void unregister_serial(int line)
12199 +{
12200 + unsigned long flags;
12201 + struct serial_state *state = &rs_table[line];
12202 +
12203 + save_flags(flags); cli();
12204 + if (state->info && state->info->tty)
12205 + tty_hangup(state->info->tty);
12206 + state->type = PORT_UNKNOWN;
12207 + printk(KERN_INFO "ttyS%02d unloaded\n", state->line);
12208 + /* These will be hidden, because they are devices that will no longer
12209 + * be available to the system. (ie, PCMCIA modems, once ejected)
12210 + */
12211 + tty_unregister_devfs(&serial_driver,
12212 + serial_driver.minor_start + state->line);
12213 + tty_unregister_devfs(&callout_driver,
12214 + callout_driver.minor_start + state->line);
12215 + restore_flags(flags);
12216 +}
12217 +
12218 +static void __exit rs_fini(void)
12219 +{
12220 + unsigned long flags;
12221 + int e1, e2;
12222 + int i;
12223 + struct async_struct *info;
12224 +
12225 + /* printk("Unloading %s: version %s\n", serial_name, serial_version); */
12226 + del_timer_sync(&serial_timer);
12227 + save_flags(flags); cli();
12228 + remove_bh(SERIAL_BH);
12229 + if ((e1 = tty_unregister_driver(&serial_driver)))
12230 + printk("serial: failed to unregister serial driver (%d)\n",
12231 + e1);
12232 + if ((e2 = tty_unregister_driver(&callout_driver)))
12233 + printk("serial: failed to unregister callout driver (%d)\n",
12234 + e2);
12235 + restore_flags(flags);
12236 +
12237 + for (i = 0; i < NR_PORTS; i++) {
12238 + if ((info = rs_table[i].info)) {
12239 + rs_table[i].info = NULL;
12240 + kfree(info);
12241 + }
12242 + if ((rs_table[i].type != PORT_UNKNOWN) && rs_table[i].port) {
12243 +#ifdef CONFIG_SERIAL_RSA
12244 + if (rs_table[i].type == PORT_RSA)
12245 + release_region(rs_table[i].port +
12246 + UART_RSA_BASE, 16);
12247 + else
12248 +#endif
12249 + release_region(rs_table[i].port, 8);
12250 + }
12251 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
12252 + if (rs_table[i].iomem_base)
12253 + iounmap(rs_table[i].iomem_base);
12254 +#endif
12255 + }
12256 +#if defined(ENABLE_SERIAL_PCI) || defined(ENABLE_SERIAL_PNP)
12257 + for (i=0; i < NR_PCI_BOARDS; i++) {
12258 + struct pci_board_inst *brd = &serial_pci_board[i];
12259 +
12260 + if (serial_pci_board[i].dev == 0)
12261 + continue;
12262 + if (brd->board.init_fn)
12263 + (brd->board.init_fn)(brd->dev, &brd->board, 0);
12264 + if (DEACTIVATE_FUNC(brd->dev))
12265 + (DEACTIVATE_FUNC(brd->dev))(brd->dev);
12266 + }
12267 +#endif
12268 + if (tmp_buf) {
12269 + unsigned long pg = (unsigned long) tmp_buf;
12270 + tmp_buf = NULL;
12271 + free_page(pg);
12272 + }
12273 +
12274 +#ifdef ENABLE_SERIAL_PCI
12275 + if (serial_pci_driver.name[0])
12276 + pci_unregister_driver (&serial_pci_driver);
12277 +#endif
12278 +}
12279 +
12280 +module_init(rs_init);
12281 +module_exit(rs_fini);
12282 +MODULE_DESCRIPTION("Standard/generic (dumb) serial driver");
12283 +MODULE_AUTHOR("Theodore Ts'o <tytso@mit.edu>");
12284 +MODULE_LICENSE("GPL");
12285 +
12286 +
12287 +/*
12288 + * ------------------------------------------------------------
12289 + * Serial console driver
12290 + * ------------------------------------------------------------
12291 + */
12292 +#ifdef CONFIG_SERIAL_CONSOLE
12293 +
12294 +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
12295 +
12296 +static struct async_struct async_sercons;
12297 +
12298 +/*
12299 + * Wait for transmitter & holding register to empty
12300 + */
12301 +static inline void wait_for_xmitr(struct async_struct *info)
12302 +{
12303 + unsigned int status, tmout = 1000000;
12304 +
12305 + do {
12306 + status = serial_in(info, UART_LSR);
12307 +
12308 + if (status & UART_LSR_BI)
12309 + lsr_break_flag = UART_LSR_BI;
12310 +
12311 + if (--tmout == 0)
12312 + break;
12313 + } while((status & BOTH_EMPTY) != BOTH_EMPTY);
12314 +
12315 + /* Wait for flow control if necessary */
12316 + if (info->flags & ASYNC_CONS_FLOW) {
12317 + tmout = 1000000;
12318 + while (--tmout &&
12319 + ((serial_in(info, UART_MSR) & UART_MSR_CTS) == 0));
12320 + }
12321 +}
12322 +
12323 +
12324 +/*
12325 + * Print a string to the serial port trying not to disturb
12326 + * any possible real use of the port...
12327 + *
12328 + * The console must be locked when we get here.
12329 + */
12330 +static void serial_console_write(struct console *co, const char *s,
12331 + unsigned count)
12332 +{
12333 + static struct async_struct *info = &async_sercons;
12334 + int ier;
12335 + unsigned i;
12336 +
12337 + /*
12338 + * First save the IER then disable the interrupts
12339 + */
12340 + ier = serial_in(info, UART_IER);
12341 + serial_out(info, UART_IER, 0x00);
12342 +
12343 + /*
12344 + * Now, do each character
12345 + */
12346 + for (i = 0; i < count; i++, s++) {
12347 + wait_for_xmitr(info);
12348 +
12349 + /*
12350 + * Send the character out.
12351 + * If a LF, also do CR...
12352 + */
12353 + serial_out(info, UART_TX, *s);
12354 + if (*s == 10) {
12355 + wait_for_xmitr(info);
12356 + serial_out(info, UART_TX, 13);
12357 + }
12358 + }
12359 +
12360 + /*
12361 + * Finally, Wait for transmitter & holding register to empty
12362 + * and restore the IER
12363 + */
12364 + wait_for_xmitr(info);
12365 + serial_out(info, UART_IER, ier);
12366 +}
12367 +
12368 +static kdev_t serial_console_device(struct console *c)
12369 +{
12370 + return MKDEV(TTY_MAJOR, 64 + c->index);
12371 +}
12372 +
12373 +/*
12374 + * Setup initial baud/bits/parity/flow control. We do two things here:
12375 + * - construct a cflag setting for the first rs_open()
12376 + * - initialize the serial port
12377 + * Return non-zero if we didn't find a serial port.
12378 + */
12379 +static int __init serial_console_setup(struct console *co, char *options)
12380 +{
12381 + static struct async_struct *info;
12382 + struct serial_state *state;
12383 + unsigned cval;
12384 + int baud = 9600;
12385 + int bits = 8;
12386 + int parity = 'n';
12387 + int doflow = 0;
12388 + int cflag = CREAD | HUPCL | CLOCAL;
12389 + int quot = 0;
12390 + char *s;
12391 +
12392 + if (options) {
12393 + baud = simple_strtoul(options, NULL, 10);
12394 + s = options;
12395 + while(*s >= '0' && *s <= '9')
12396 + s++;
12397 + if (*s) parity = *s++;
12398 + if (*s) bits = *s++ - '0';
12399 + if (*s) doflow = (*s++ == 'r');
12400 + }
12401 +
12402 + /*
12403 + * Now construct a cflag setting.
12404 + */
12405 + switch(baud) {
12406 + case 1200:
12407 + cflag |= B1200;
12408 + break;
12409 + case 2400:
12410 + cflag |= B2400;
12411 + break;
12412 + case 4800:
12413 + cflag |= B4800;
12414 + break;
12415 + case 19200:
12416 + cflag |= B19200;
12417 + break;
12418 + case 38400:
12419 + cflag |= B38400;
12420 + break;
12421 + case 57600:
12422 + cflag |= B57600;
12423 + break;
12424 + case 115200:
12425 + cflag |= B115200;
12426 + break;
12427 + case 9600:
12428 + default:
12429 + cflag |= B9600;
12430 + /*
12431 + * Set this to a sane value to prevent a divide error
12432 + */
12433 + baud = 9600;
12434 + break;
12435 + }
12436 + switch(bits) {
12437 + case 7:
12438 + cflag |= CS7;
12439 + break;
12440 + default:
12441 + case 8:
12442 + cflag |= CS8;
12443 + break;
12444 + }
12445 + switch(parity) {
12446 + case 'o': case 'O':
12447 + cflag |= PARODD;
12448 + break;
12449 + case 'e': case 'E':
12450 + cflag |= PARENB;
12451 + break;
12452 + }
12453 + co->cflag = cflag;
12454 +
12455 + /*
12456 + * Divisor, bytesize and parity
12457 + */
12458 + state = rs_table + co->index;
12459 + if (doflow)
12460 + state->flags |= ASYNC_CONS_FLOW;
12461 + info = &async_sercons;
12462 + info->magic = SERIAL_MAGIC;
12463 + info->state = state;
12464 + info->port = state->port;
12465 + info->flags = state->flags;
12466 +#ifdef CONFIG_HUB6
12467 + info->hub6 = state->hub6;
12468 +#endif
12469 + info->io_type = state->io_type;
12470 + info->iomem_base = state->iomem_base;
12471 + info->iomem_reg_shift = state->iomem_reg_shift;
12472 + quot = state->baud_base / baud;
12473 + cval = cflag & (CSIZE | CSTOPB);
12474 +#if defined(__powerpc__) || defined(__alpha__)
12475 + cval >>= 8;
12476 +#else /* !__powerpc__ && !__alpha__ */
12477 + cval >>= 4;
12478 +#endif /* !__powerpc__ && !__alpha__ */
12479 + if (cflag & PARENB)
12480 + cval |= UART_LCR_PARITY;
12481 + if (!(cflag & PARODD))
12482 + cval |= UART_LCR_EPAR;
12483 +
12484 + /*
12485 + * Disable UART interrupts, set DTR and RTS high
12486 + * and set speed.
12487 + */
12488 + serial_out(info, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
12489 + serial_out(info, UART_DLL, quot & 0xff); /* LS of divisor */
12490 + serial_out(info, UART_DLM, quot >> 8); /* MS of divisor */
12491 + serial_out(info, UART_LCR, cval); /* reset DLAB */
12492 + serial_out(info, UART_IER, 0);
12493 + serial_out(info, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
12494 +
12495 + /*
12496 + * If we read 0xff from the LSR, there is no UART here.
12497 + */
12498 + if (serial_in(info, UART_LSR) == 0xff)
12499 + return -1;
12500 +
12501 + return 0;
12502 +}
12503 +
12504 +static struct console sercons = {
12505 + name: "ttyS",
12506 + write: serial_console_write,
12507 + device: serial_console_device,
12508 + setup: serial_console_setup,
12509 + flags: CON_PRINTBUFFER,
12510 + index: -1,
12511 +};
12512 +
12513 +/*
12514 + * Register console.
12515 + */
12516 +void __init serial_console_init(void)
12517 +{
12518 + register_console(&sercons);
12519 +}
12520 +#endif
12521 +
12522 +/*
12523 + Local variables:
12524 + compile-command: "gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing -pipe -fno-strength-reduce -march=i586 -DMODULE -DMODVERSIONS -include ../../include/linux/modversions.h -DEXPORT_SYMTAB -c serial.c"
12525 + End:
12526 +*/
12527 diff -urN linux.old/drivers/char/ticfg/Makefile linux.dev/drivers/char/ticfg/Makefile
12528 --- linux.old/drivers/char/ticfg/Makefile 1970-01-01 01:00:00.000000000 +0100
12529 +++ linux.dev/drivers/char/ticfg/Makefile 2005-10-21 17:02:20.199991500 +0200
12530 @@ -0,0 +1,6 @@
12531 +
12532 +O_TARGET := ticfg.o
12533 +
12534 +obj-$(CONFIG_AR7_ADAM2) := adam2_env.o
12535 +
12536 +include $(TOPDIR)/Rules.make
12537 diff -urN linux.old/drivers/char/ticfg/adam2_env.c linux.dev/drivers/char/ticfg/adam2_env.c
12538 --- linux.old/drivers/char/ticfg/adam2_env.c 1970-01-01 01:00:00.000000000 +0100
12539 +++ linux.dev/drivers/char/ticfg/adam2_env.c 2005-10-21 17:02:20.199991500 +0200
12540 @@ -0,0 +1,85 @@
12541 +#include <linux/types.h>
12542 +#include <linux/errno.h>
12543 +#include <linux/module.h>
12544 +#include <linux/kernel.h>
12545 +#include <linux/proc_fs.h>
12546 +#include <linux/fcntl.h>
12547 +#include <linux/init.h>
12548 +
12549 +#include <asm/ar7/adam2_env.h>
12550 +
12551 +#undef ADAM2_ENV_DEBUG
12552 +
12553 +#ifdef ADAM2_ENV_DEBUG
12554 +#define DPRINTK(args...) do { printk(args); } while(0);
12555 +#else
12556 +#define DPRINTK(args...) do { } while(0);
12557 +#endif
12558 +
12559 +#define ADAM2_ENV_DIR "ticfg"
12560 +#define ADAM2_ENV_NAME "env"
12561 +
12562 +static struct proc_dir_entry *adam2_env_proc_dir;
12563 +static struct proc_dir_entry *adam2_env_proc_ent;
12564 +
12565 +static int
12566 +adam2_proc_read_env(char *page, char **start, off_t pos, int count,
12567 + int *eof, void *data)
12568 +{
12569 + int len;
12570 + t_env_var *env;
12571 +
12572 + if (pos > 0)
12573 + return 0;
12574 +
12575 + len=0;
12576 + for (env = prom_iterenv(0); env; env = prom_iterenv(env)) {
12577 + if (env->val) {
12578 + /* XXX check for page len */
12579 + len += sprintf(page + len, "%s\t%s\n",
12580 + env->name, env->val);
12581 + }
12582 + }
12583 +
12584 + *eof=1;
12585 + return len;
12586 +}
12587 +
12588 +static int __init
12589 +adam2_env_init(void)
12590 +{
12591 +
12592 + DPRINTK("%s\n", __FUNCTION__);
12593 +
12594 + adam2_env_proc_dir = proc_mkdir(ADAM2_ENV_DIR, NULL);
12595 + if (!adam2_env_proc_dir) {
12596 + printk(KERN_ERR "%s: Unable to create /proc/%s entry\n",
12597 + __FUNCTION__, ADAM2_ENV_DIR);
12598 + return -ENOMEM;
12599 + }
12600 +
12601 + adam2_env_proc_ent =
12602 + create_proc_entry(ADAM2_ENV_NAME, 0444, adam2_env_proc_dir);
12603 + if (!adam2_env_proc_ent) {
12604 + printk(KERN_ERR "%s: Unable to create /proc/%s/%s entry\n",
12605 + __FUNCTION__, ADAM2_ENV_DIR, ADAM2_ENV_NAME);
12606 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
12607 + return -ENOMEM;
12608 + }
12609 + adam2_env_proc_ent->read_proc = adam2_proc_read_env;
12610 +
12611 + return 0;
12612 +}
12613 +
12614 +static
12615 +void __exit
12616 +adam2_env_cleanup(void)
12617 +{
12618 + remove_proc_entry(ADAM2_ENV_NAME, adam2_env_proc_dir);
12619 + remove_proc_entry(ADAM2_ENV_DIR, NULL);
12620 +}
12621 +
12622 +module_init(adam2_env_init);
12623 +module_exit(adam2_env_cleanup);
12624 +
12625 +MODULE_LICENSE("GPL");
12626 diff -urN linux.old/include/asm-mips/ar7/adam2_env.h linux.dev/include/asm-mips/ar7/adam2_env.h
12627 --- linux.old/include/asm-mips/ar7/adam2_env.h 1970-01-01 01:00:00.000000000 +0100
12628 +++ linux.dev/include/asm-mips/ar7/adam2_env.h 2005-10-21 17:02:25.564326750 +0200
12629 @@ -0,0 +1,13 @@
12630 +#ifndef _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12631 +#define _INCLUDE_ASM_AR7_ADAM2_ENV_H_
12632 +
12633 +/* Environment variable */
12634 +typedef struct {
12635 + char *name;
12636 + char *val;
12637 +} t_env_var;
12638 +
12639 +char *prom_getenv(char *);
12640 +t_env_var *prom_iterenv(t_env_var *);
12641 +
12642 +#endif /* _INCLUDE_ASM_AR7_ADAM2_ENV_H_ */
12643 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
12644 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
12645 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-10-21 16:45:42.178067250 +0200
12646 @@ -0,0 +1,33 @@
12647 +/*
12648 + * $Id$
12649 + * Copyright (C) $Date$ $Author$
12650 + *
12651 + * This program is free software; you can redistribute it and/or modify
12652 + * it under the terms of the GNU General Public License as published by
12653 + * the Free Software Foundation; either version 2 of the License, or
12654 + * (at your option) any later version.
12655 + *
12656 + * This program is distributed in the hope that it will be useful,
12657 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12658 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12659 + * GNU General Public License for more details.
12660 + *
12661 + * You should have received a copy of the GNU General Public License
12662 + * along with this program; if not, write to the Free Software
12663 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
12664 + *
12665 + */
12666 +
12667 +#ifndef _AR7_H
12668 +#define _AR7_H
12669 +
12670 +#include <asm/addrspace.h>
12671 +#include <linux/config.h>
12672 +
12673 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
12674 +
12675 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
12676 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
12677 +#define AR7_BASE_BAUD ( 3686400 / 16 )
12678 +
12679 +#endif
12680 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
12681 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
12682 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-10-21 17:02:25.568327000 +0200
12683 @@ -0,0 +1,292 @@
12684 + /*
12685 + * Nitin Dhingra, iamnd@ti.com
12686 + * Copyright (C) 2000 Texas Instruments Inc.
12687 + *
12688 + *
12689 + * ########################################################################
12690 + *
12691 + * This program is free software; you can distribute it and/or modify it
12692 + * under the terms of the GNU General Public License (Version 2) as
12693 + * published by the Free Software Foundation.
12694 + *
12695 + * This program is distributed in the hope it will be useful, but WITHOUT
12696 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12697 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12698 + * for more details.
12699 + *
12700 + * You should have received a copy of the GNU General Public License along
12701 + * with this program; if not, write to the Free Software Foundation, Inc.,
12702 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
12703 + *
12704 + * ########################################################################
12705 + *
12706 + * Defines of the Sead board specific address-MAP, registers, etc.
12707 + *
12708 + */
12709 +#ifndef _AVALANCHE_INTC_H
12710 +#define _AVALANCHE_INTC_H
12711 +
12712 +#include <linux/config.h>
12713 +
12714 +/* ----- */
12715 +
12716 +#define KSEG1_BASE 0xA0000000
12717 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
12718 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
12719 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
12720 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
12721 +
12722 +/* ----- */
12723 +
12724 +#define MIPS_EXCEPTION_OFFSET 8
12725 +
12726 +/******************************************************************************
12727 + Avalanche Interrupt number
12728 +******************************************************************************/
12729 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
12730 +
12731 +/*******************************************************************************
12732 +*Linux Interrupt number
12733 +*******************************************************************************/
12734 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
12735 +
12736 +
12737 +
12738 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
12739 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
12740 +
12741 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
12742 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
12743 +
12744 +#define AVALANCHE_INTC_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
12745 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) + \
12746 + MIPS_EXCEPTION_OFFSET)
12747 +
12748 +#if defined(CONFIG_AR7_VLYNQ)
12749 +#define AVALANCHE_INT_END_LOW_VLYNQ (AVALANCHE_INTC_END + 32)
12750 +#define AVALANCHE_INT_END_VLYNQ (AVALANCHE_INTC_END + 32 * CONFIG_AR7_VLYNQ_PORTS)
12751 +#define AVALANCHE_INT_END AVALANCHE_INT_END_VLYNQ
12752 +#else
12753 +#define AVALANCHE_INT_END AVALANCHE_INTC_END
12754 +#endif
12755 +
12756 +
12757 +/*
12758 + * Avalanche interrupt controller register base (primary)
12759 + */
12760 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
12761 +
12762 +/******************************************************************************
12763 + * Avalanche exception controller register base (secondary)
12764 + ******************************************************************************/
12765 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
12766 +
12767 +
12768 +/******************************************************************************
12769 + * Avalanche Interrupt pacing register base (secondary)
12770 + ******************************************************************************/
12771 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
12772 +
12773 +
12774 +
12775 +/******************************************************************************
12776 + * Avalanche Interrupt Channel Control register base
12777 + *****************************************************************************/
12778 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
12779 +
12780 +
12781 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
12782 +{
12783 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
12784 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
12785 + volatile unsigned long unused1; /*0x08 */
12786 + volatile unsigned long unused2; /*0x0C */
12787 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
12788 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
12789 + volatile unsigned long unused3; /*0x18 */
12790 + volatile unsigned long unused4; /*0x1C */
12791 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
12792 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
12793 + volatile unsigned long unused5; /*0x28 */
12794 + volatile unsigned long unused6; /*0x2C */
12795 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
12796 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
12797 + volatile unsigned long unused7; /* 0x38 */
12798 + volatile unsigned long unused8; /* 0x3c */
12799 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
12800 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
12801 + volatile unsigned long unused9; /* 0x48 */
12802 + volatile unsigned long unused10; /* 0x4C */
12803 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
12804 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
12805 + volatile unsigned long unused11; /* 0x58 */
12806 + volatile unsigned long unused12; /*0x5C */
12807 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
12808 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
12809 +};
12810 +
12811 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
12812 +{
12813 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
12814 + volatile unsigned long reserved; /*0x84 */
12815 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
12816 + volatile unsigned long reserved1; /*0x8c */
12817 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
12818 + volatile unsigned long reserved2; /*0x94 */
12819 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
12820 +};
12821 +struct avalanche_ipace_regs
12822 +{
12823 +
12824 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
12825 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
12826 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
12827 +};
12828 +struct avalanche_channel_int_number
12829 +{
12830 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
12831 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
12832 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
12833 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
12834 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
12835 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
12836 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
12837 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
12838 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
12839 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
12840 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
12841 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
12842 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
12843 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
12844 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
12845 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
12846 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
12847 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
12848 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
12849 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
12850 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
12851 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
12852 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
12853 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
12854 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
12855 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
12856 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
12857 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
12858 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
12859 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
12860 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
12861 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
12862 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
12863 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
12864 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
12865 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
12866 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
12867 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
12868 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
12869 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
12870 +};
12871 +
12872 +struct avalanche_interrupt_line_to_channel
12873 +{
12874 + unsigned long int_line0; /* Start of primary interrupts */
12875 + unsigned long int_line1;
12876 + unsigned long int_line2;
12877 + unsigned long int_line3;
12878 + unsigned long int_line4;
12879 + unsigned long int_line5;
12880 + unsigned long int_line6;
12881 + unsigned long int_line7;
12882 + unsigned long int_line8;
12883 + unsigned long int_line9;
12884 + unsigned long int_line10;
12885 + unsigned long int_line11;
12886 + unsigned long int_line12;
12887 + unsigned long int_line13;
12888 + unsigned long int_line14;
12889 + unsigned long int_line15;
12890 + unsigned long int_line16;
12891 + unsigned long int_line17;
12892 + unsigned long int_line18;
12893 + unsigned long int_line19;
12894 + unsigned long int_line20;
12895 + unsigned long int_line21;
12896 + unsigned long int_line22;
12897 + unsigned long int_line23;
12898 + unsigned long int_line24;
12899 + unsigned long int_line25;
12900 + unsigned long int_line26;
12901 + unsigned long int_line27;
12902 + unsigned long int_line28;
12903 + unsigned long int_line29;
12904 + unsigned long int_line30;
12905 + unsigned long int_line31;
12906 + unsigned long int_line32;
12907 + unsigned long int_line33;
12908 + unsigned long int_line34;
12909 + unsigned long int_line35;
12910 + unsigned long int_line36;
12911 + unsigned long int_line37;
12912 + unsigned long int_line38;
12913 + unsigned long int_line39;
12914 +};
12915 +
12916 +
12917 +/* Interrupt Line #'s (Sangam peripherals) */
12918 +
12919 +/*------------------------------*/
12920 +/* Sangam primary interrupts */
12921 +/*------------------------------*/
12922 +
12923 +#define UNIFIED_SECONDARY_INTERRUPT 0
12924 +#define AVALANCHE_EXT_INT_0 1
12925 +#define AVALANCHE_EXT_INT_1 2
12926 +/* Line #3 Reserved */
12927 +/* Line #4 Reserved */
12928 +#define AVALANCHE_TIMER_0_INT 5
12929 +#define AVALANCHE_TIMER_1_INT 6
12930 +#define AVALANCHE_UART0_INT 7
12931 +#define AVALANCHE_UART1_INT 8
12932 +#define AVALANCHE_PDMA_INT0 9
12933 +#define AVALANCHE_PDMA_INT1 10
12934 +/* Line #11 Reserved */
12935 +/* Line #12 Reserved */
12936 +/* Line #13 Reserved */
12937 +/* Line #14 Reserved */
12938 +#define AVALANCHE_ATM_SAR_INT 15
12939 +/* Line #16 Reserved */
12940 +/* Line #17 Reserved */
12941 +/* Line #18 Reserved */
12942 +#define AVALANCHE_MAC0_INT 19
12943 +/* Line #20 Reserved */
12944 +#define AVALANCHE_VLYNQ0_INT 21
12945 +#define AVALANCHE_CODEC_WAKE_INT 22
12946 +/* Line #23 Reserved */
12947 +#define AVALANCHE_USB_INT 24
12948 +#define AVALANCHE_VLYNQ1_INT 25
12949 +/* Line #26 Reserved */
12950 +/* Line #27 Reserved */
12951 +#define AVALANCHE_MAC1_INT 28
12952 +#define AVALANCHE_I2CM_INT 29
12953 +#define AVALANCHE_PDMA_INT2 30
12954 +#define AVALANCHE_PDMA_INT3 31
12955 +/* Line #32 Reserved */
12956 +/* Line #33 Reserved */
12957 +/* Line #34 Reserved */
12958 +/* Line #35 Reserved */
12959 +/* Line #36 Reserved */
12960 +#define AVALANCHE_VDMA_VT_RX_INT 37
12961 +#define AVALANCHE_VDMA_VT_TX_INT 38
12962 +#define AVALANCHE_ADSLSS_INT 39
12963 +
12964 +/*-----------------------------------*/
12965 +/* Sangam Secondary Interrupts */
12966 +/*-----------------------------------*/
12967 +#define PRIMARY_INTS 40
12968 +
12969 +#define EMIF_INT (7 + PRIMARY_INTS)
12970 +
12971 +
12972 +extern void avalanche_int_set(int channel, int line);
12973 +
12974 +
12975 +#endif /* _AVALANCHE_INTC_H */
12976 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
12977 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
12978 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-10-21 16:45:42.178067250 +0200
12979 @@ -0,0 +1,174 @@
12980 +#ifndef _AVALANCHE_MISC_H_
12981 +#define _AVALANCHE_MISC_H_
12982 +
12983 +typedef enum AVALANCHE_ERR_t
12984 +{
12985 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
12986 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
12987 +
12988 + /* Pointers and args */
12989 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
12990 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
12991 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
12992 +
12993 + /* Memory issues */
12994 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
12995 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
12996 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
12997 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
12998 +
12999 + /* Device issues */
13000 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
13001 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
13002 +
13003 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
13004 +
13005 +} AVALANCHE_ERR;
13006 +
13007 +/*****************************************************************************
13008 + * Reset Control Module
13009 + *****************************************************************************/
13010 +
13011 +typedef enum AVALANCHE_RESET_MODULE_tag
13012 +{
13013 + RESET_MODULE_UART0 = 0,
13014 + RESET_MODULE_UART1 = 1,
13015 + RESET_MODULE_I2C = 2,
13016 + RESET_MODULE_TIMER0 = 3,
13017 + RESET_MODULE_TIMER1 = 4,
13018 + RESET_MODULE_GPIO = 6,
13019 + RESET_MODULE_ADSLSS = 7,
13020 + RESET_MODULE_USBS = 8,
13021 + RESET_MODULE_SAR = 9,
13022 + RESET_MODULE_VDMA_VT = 11,
13023 + RESET_MODULE_FSER = 12,
13024 + RESET_MODULE_VLYNQ1 = 16,
13025 + RESET_MODULE_EMAC0 = 17,
13026 + RESET_MODULE_DMA = 18,
13027 + RESET_MODULE_BIST = 19,
13028 + RESET_MODULE_VLYNQ0 = 20,
13029 + RESET_MODULE_EMAC1 = 21,
13030 + RESET_MODULE_MDIO = 22,
13031 + RESET_MODULE_ADSLSS_DSP = 23,
13032 + RESET_MODULE_EPHY = 26
13033 +} AVALANCHE_RESET_MODULE_T;
13034 +
13035 +typedef enum AVALANCHE_RESET_CTRL_tag
13036 +{
13037 + IN_RESET = 0,
13038 + OUT_OF_RESET
13039 +} AVALANCHE_RESET_CTRL_T;
13040 +
13041 +typedef enum AVALANCHE_SYS_RST_MODE_tag
13042 +{
13043 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
13044 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
13045 +} AVALANCHE_SYS_RST_MODE_T;
13046 +
13047 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
13048 +{
13049 + HARDWARE_RESET = 0,
13050 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
13051 + WATCHDOG_RESET,
13052 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
13053 +} AVALANCHE_SYS_RESET_STATUS_T;
13054 +
13055 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
13056 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
13057 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
13058 +
13059 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
13060 +
13061 +/*****************************************************************************
13062 + * Power Control Module
13063 + *****************************************************************************/
13064 +
13065 +typedef enum AVALANCHE_POWER_CTRL_tag
13066 +{
13067 + POWER_CTRL_POWER_UP = 0,
13068 + POWER_CTRL_POWER_DOWN
13069 +} AVALANCHE_POWER_CTRL_T;
13070 +
13071 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
13072 +{
13073 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
13074 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
13075 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
13076 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
13077 +} AVALANCHE_SYS_POWER_MODE_T;
13078 +
13079 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
13080 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
13081 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
13082 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
13083 +
13084 +/*****************************************************************************
13085 + * Wakeup Control
13086 + *****************************************************************************/
13087 +
13088 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
13089 +{
13090 + WAKEUP_INT0 = 1,
13091 + WAKEUP_INT1 = 2,
13092 + WAKEUP_INT2 = 4,
13093 + WAKEUP_INT3 = 8
13094 +} AVALANCHE_WAKEUP_INTERRUPT_T;
13095 +
13096 +typedef enum TNETV1050_WAKEUP_CTRL_tag
13097 +{
13098 + WAKEUP_DISABLED = 0,
13099 + WAKEUP_ENABLED
13100 +} AVALANCHE_WAKEUP_CTRL_T;
13101 +
13102 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
13103 +{
13104 + WAKEUP_ACTIVE_HIGH = 0,
13105 + WAKEUP_ACTIVE_LOW
13106 +} AVALANCHE_WAKEUP_POLARITY_T;
13107 +
13108 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
13109 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
13110 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
13111 +
13112 +/*****************************************************************************
13113 + * GPIO Control
13114 + *****************************************************************************/
13115 +
13116 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
13117 +{
13118 + FUNCTIONAL_PIN = 0,
13119 + GPIO_PIN = 1
13120 +} AVALANCHE_GPIO_PIN_MODE_T;
13121 +
13122 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
13123 +{
13124 + GPIO_OUTPUT_PIN = 0,
13125 + GPIO_INPUT_PIN = 1
13126 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
13127 +
13128 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
13129 +
13130 +void avalanche_gpio_init(void);
13131 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
13132 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
13133 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
13134 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
13135 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
13136 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
13137 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
13138 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
13139 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
13140 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
13141 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
13142 +
13143 +unsigned int avalanche_get_chip_version_info(void);
13144 +
13145 +unsigned int avalanche_get_vbus_freq(void);
13146 +void avalanche_set_vbus_freq(unsigned int);
13147 +
13148 +
13149 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
13150 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
13151 +unsigned int avalanche_is_mdix_on_chip(void);
13152 +
13153 +#endif
13154 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
13155 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
13156 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-10-21 16:45:42.182067500 +0200
13157 @@ -0,0 +1,567 @@
13158 +/*
13159 + * $Id$
13160 + * Avalanche Register Descriptions
13161 + *
13162 + * Jeff Harrell, jharrell@ti.com
13163 + * 2000 (c) Texas Instruments Inc.
13164 + */
13165 +
13166 +#ifndef __AVALANCHE_REGS_H
13167 +#define __AVALANCHE_REGS_H
13168 +
13169 +#include <asm/addrspace.h>
13170 +#include <linux/config.h>
13171 +
13172 +/*----------------------------------------*/
13173 +/* Base offsets within the Avalanche ASIC */
13174 +/*----------------------------------------*/
13175 +
13176 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
13177 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
13178 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
13179 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
13180 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
13181 +#define DES_BASE (KSEG1ADDR(0x08600000))
13182 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
13183 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
13184 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
13185 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
13186 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
13187 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
13188 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
13189 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
13190 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
13191 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
13192 +#define I2C_BASE (KSEG1ADDR(0x08611000))
13193 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
13194 +#define USB_BASE (KSEG1ADDR(0x08611200))
13195 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
13196 +#define DMA_BASE (KSEG1ADDR(0x08611400))
13197 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
13198 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
13199 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
13200 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
13201 +
13202 +/*---------------------------------*/
13203 +/* Device ID, chip version number */
13204 +/*---------------------------------*/
13205 +
13206 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
13207 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
13208 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
13209 +
13210 +/*----------------------------------*/
13211 +/* Reset Control VW changed to ptrs */
13212 +/*----------------------------------*/
13213 +
13214 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
13215 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
13216 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
13217 +
13218 +/* reset control bits */
13219 +
13220 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
13221 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
13222 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
13223 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
13224 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
13225 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
13226 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
13227 +/*
13228 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
13229 + If you reset the GPIO interface all of the directions (i/o) of the UART B
13230 + interface pins are inputs and must be reconfigured so as not to lose the
13231 + serial console interface
13232 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
13233 +*/
13234 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
13235 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
13236 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
13237 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
13238 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
13239 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
13240 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
13241 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
13242 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
13243 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
13244 +
13245 +/*----------------------*/
13246 +/* Physical interfaces */
13247 +/*----------------------*/
13248 +
13249 +/* Phy loopback */
13250 +#define PHY_LOOPBACK 1
13251 +
13252 +
13253 +/* Phy 0 */
13254 +#define PHY0BASE (PHY_BASE)
13255 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
13256 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
13257 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
13258 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
13259 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
13260 +
13261 +
13262 +/* Phy 1 */
13263 +
13264 +#define PHY1BASE (PHY_BASE + 0x100000)
13265 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
13266 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
13267 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
13268 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
13269 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
13270 +
13271 +/* Phy 2 */
13272 +
13273 +#define PHY2BASE (PHY_BASE + 0x200000)
13274 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
13275 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
13276 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
13277 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
13278 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
13279 +
13280 +/*-------------------*/
13281 +/* Avalanche ATM SAR */
13282 +/*-------------------*/
13283 +
13284 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
13285 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
13286 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
13287 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
13288 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
13289 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
13290 +
13291 +/* Transmit completion ring registers */
13292 +
13293 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
13294 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
13295 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
13296 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
13297 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
13298 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
13299 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
13300 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
13301 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
13302 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
13303 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
13304 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
13305 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
13306 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
13307 +
13308 +/* Transmit Queue Packet registers */
13309 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
13310 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
13311 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
13312 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
13313 +/* Receive completion ring registers */
13314 +
13315 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
13316 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
13317 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
13318 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
13319 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
13320 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
13321 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
13322 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
13323 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
13324 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
13325 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
13326 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
13327 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
13328 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
13329 +
13330 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
13331 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
13332 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
13333 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
13334 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
13335 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
13336 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
13337 +
13338 +
13339 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
13340 +
13341 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
13342 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
13343 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
13344 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
13345 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
13346 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
13347 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
13348 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
13349 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
13350 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
13351 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
13352 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
13353 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
13354 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
13355 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
13356 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
13357 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
13358 +
13359 +
13360 +/*
13361 +
13362 +#define OAM_CPID_ADD 0xa30104e0
13363 +
13364 +#define OAM_LLID_ADD 0xa30104f0
13365 +
13366 +#define OAM_LLID_VAL 0xffffffff
13367 +
13368 +#define OAM_CORR_TAG 0xa3010500
13369 +
13370 +#define OAM_FAR_COUNT_ADD 0xa3010520
13371 +
13372 +#define OAM_NEAR_COUNT_ADD 0xa3010540
13373 +
13374 +#define OAM_CONFIG_REG_ADD 0xa3000018
13375 +*/
13376 +
13377 +
13378 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
13379 +
13380 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
13381 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
13382 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
13383 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
13384 +
13385 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
13386 +
13387 +
13388 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
13389 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
13390 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
13391 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
13392 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
13393 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
13394 +
13395 +/*------------------------------------------*/
13396 +/* DSL Interface */
13397 +/*------------------------------------------*/
13398 +
13399 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
13400 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
13401 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
13402 +
13403 +/* Fast */
13404 +
13405 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
13406 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
13407 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
13408 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
13409 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
13410 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
13411 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
13412 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
13413 +
13414 +/* Interleaved */
13415 +
13416 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
13417 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
13418 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
13419 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
13420 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
13421 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
13422 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
13423 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
13424 +
13425 +/*------------------------------------------*/
13426 +/* Broadband I/F */
13427 +/*------------------------------------------*/
13428 +
13429 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
13430 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
13431 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
13432 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
13433 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
13434 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
13435 +
13436 +#define AVBBIF_DISABLED 0x0
13437 +#define AVBBIF_LBT4040_INT 0x1
13438 +#define AVBBIF_XBUS 0x2
13439 +#define AVBBIF_LBT4040_EXT 0x4
13440 +
13441 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
13442 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
13443 +#define AVBBIF_TRANS_MASK 0xff000000
13444 +/*------------------------------------------*/
13445 +/* GPIO I/F */
13446 +/*------------------------------------------*/
13447 +
13448 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
13449 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
13450 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
13451 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
13452 +
13453 +#define GPIO_0 (1<<21)
13454 +#define GPIO_1 (1<<22)
13455 +#define GPIO_2 (1<<23)
13456 +#define GPIO_3 (1<<24)
13457 +#define EINT_1 (1<<18)
13458 +
13459 +/*
13460 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
13461 + If you reset the GPIO interface all of the directions (i/o) of the UART B
13462 + interface pins are inputs and must be reconfigured so as not to lose the
13463 + serial console interface
13464 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
13465 +*/
13466 +
13467 +/*------------------------------------------*/
13468 +/* CLK_CTRL */
13469 +/*------------------------------------------*/
13470 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
13471 +
13472 +#define PCLK_0_HALF_VBUS (0<<16)
13473 +#define PCLK_EQ_INPUT (1<<16)
13474 +#define BBIF_CLK_HALF_VBUS (0<<17)
13475 +#define BBIF_CLK_EQ_VBUS (1<<17)
13476 +#define BBIF_CLK_EQ_BBCLK (3<<17)
13477 +#define DSP_MODCLK_DSPCLKI (0<<20)
13478 +#define DSP_MODCLK_REFCLKI (1<<20)
13479 +#define USB_CLK_EQ_USBCLKI (0<<21)
13480 +#define USB_CLK_EQ_REFCLKI (1<<21)
13481 +
13482 +/*------------------------------------------*/
13483 +/* PCI Control Registers */
13484 +/*------------------------------------------*/
13485 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
13486 +#define PCIC_CONTROL_CFG_DONE (1<<0)
13487 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
13488 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
13489 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
13490 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
13491 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
13492 +#define PCIC_CONTROL_MEM_MASK (1<<6)
13493 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
13494 +#define PCIC_CONTROL_IO_MASK (1<<8)
13495 +/* PCIC_CONTROL_RESERVED (1<<9) */
13496 +#define PCIC_CONTROL_BASE0_EN (1<<10)
13497 +#define PCIC_CONTROL_BASE1_EN (1<<11)
13498 +#define PCIC_CONTROL_BASE2_EN (1<<12)
13499 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
13500 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
13501 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
13502 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
13503 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
13504 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
13505 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
13506 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
13507 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
13508 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
13509 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
13510 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
13511 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
13512 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
13513 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
13514 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
13515 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
13516 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
13517 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
13518 +#define PCIC_INT_CLEAR_PM (1<<0)
13519 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
13520 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
13521 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
13522 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
13523 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
13524 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
13525 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
13526 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
13527 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
13528 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
13529 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
13530 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
13531 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
13532 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
13533 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
13534 +#define PCIC_INT_EN_AVAL_PM (1<<0)
13535 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
13536 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
13537 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
13538 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
13539 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
13540 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
13541 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
13542 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
13543 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
13544 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
13545 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
13546 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
13547 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
13548 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
13549 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
13550 +#define PCIC_INT_EN_PCI_PM (1<<0)
13551 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
13552 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
13553 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
13554 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
13555 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
13556 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
13557 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
13558 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
13559 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
13560 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
13561 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
13562 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
13563 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
13564 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
13565 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
13566 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
13567 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
13568 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
13569 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
13570 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
13571 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
13572 +/* PCIC_PM_CTL_RESERVED (1<<2) */
13573 +/* PCIC_PM_CTL_RESERVED (1<<3) */
13574 +/* PCIC_PM_CTL_RESERVED (1<<4) */
13575 +/* PCIC_PM_CTL_RESERVED (1<<5) */
13576 +/* PCIC_PM_CTL_RESERVED (1<<6) */
13577 +/* PCIC_PM_CTL_RESERVED (1<<7) */
13578 +/* PCIC_PM_CTL_RESERVED (1<<8) */
13579 +/* PCIC_PM_CTL_RESERVED (1<<9) */
13580 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
13581 +#define PCIC_PM_CTL_PMEIN (1<<11)
13582 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
13583 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
13584 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
13585 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
13586 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
13587 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
13588 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
13589 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
13590 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
13591 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
13592 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
13593 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
13594 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
13595 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
13596 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
13597 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
13598 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
13599 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
13600 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
13601 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
13602 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
13603 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
13604 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
13605 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
13606 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
13607 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
13608 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
13609 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
13610 +
13611 +/*------------------------------------------*/
13612 +/* IIC_INTERFACE */
13613 +/*------------------------------------------*/
13614 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
13615 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
13616 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
13617 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
13618 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
13619 +
13620 +#define I2CWRITE 0x200
13621 +#define I2CREAD 0x300
13622 +#define I2C_END_BURST 0x400
13623 +
13624 +/* read bits */
13625 +#define I2C_READ_ERROR 0x8000
13626 +#define I2C_READ_COMPLETE 0x4000
13627 +#define I2C_READ_BUSY 0x2000
13628 +
13629 +/* device types */
13630 +#define I2C_IO_EXPANDER 0x2
13631 +#define I2C_RTC 0xd
13632 +
13633 +/* device Addresses on I2C bus (EVM3) */
13634 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
13635 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
13636 +#define EVM3_RTC_I2C_ADDR 0x0
13637 +
13638 +/*------------------------------------------*/
13639 +/* Ethernet MAC register offset definitions */
13640 +/*------------------------------------------*/
13641 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
13642 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
13643 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
13644 +
13645 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13646 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
13647 +
13648 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
13649 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
13650 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
13651 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
13652 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
13653 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
13654 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
13655 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
13656 +
13657 +
13658 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
13659 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
13660 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
13661 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
13662 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
13663 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
13664 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
13665 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
13666 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
13667 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
13668 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
13669 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
13670 +
13671 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
13672 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
13673 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
13674 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
13675 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
13676 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
13677 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
13678 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
13679 +
13680 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
13681 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
13682 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
13683 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
13684 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
13685 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
13686 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
13687 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
13688 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
13689 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
13690 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
13691 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
13692 +
13693 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
13694 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
13695 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
13696 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
13697 +
13698 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
13699 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
13700 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
13701 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
13702 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
13703 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
13704 +
13705 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
13706 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
13707 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
13708 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
13709 +
13710 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
13711 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
13712 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
13713 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
13714 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
13715 +
13716 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
13717 +
13718 +#endif __AVALANCHE_REGS_H
13719 +
13720 +
13721 +
13722 +
13723 +
13724 +
13725 diff -urN linux.old/include/asm-mips/ar7/avalanche_types.h linux.dev/include/asm-mips/ar7/avalanche_types.h
13726 --- linux.old/include/asm-mips/ar7/avalanche_types.h 1970-01-01 01:00:00.000000000 +0100
13727 +++ linux.dev/include/asm-mips/ar7/avalanche_types.h 2005-10-21 17:02:25.568327000 +0200
13728 @@ -0,0 +1,126 @@
13729 +/*------------------------------------------------------------------------------------------*\
13730 +\*------------------------------------------------------------------------------------------*/
13731 +#ifndef _avalanche_types_h_
13732 +#define _avalanche_types_h_
13733 +
13734 +/*--- #include <asm/avalanche/generic/hal_modules/haltypes.h> ---*/
13735 +#ifndef TRUE
13736 +#define TRUE 1
13737 +#endif
13738 +#ifndef FALSE
13739 +#define FALSE 0
13740 +#endif
13741 +#ifndef NULL
13742 +#define NULL (void *)0
13743 +#endif
13744 +
13745 +/*------------------------------------------------------------------------------------------*\
13746 + * Typen für Texas GPL Module
13747 +\*------------------------------------------------------------------------------------------*/
13748 +#ifndef __UINT8_T__
13749 +typedef unsigned char UINT8;
13750 +#define __UINT8_T__
13751 +#endif
13752 +
13753 +#ifndef __UCHAR_T__
13754 +typedef unsigned char UCHAR;
13755 +#define __UCHAR_T__
13756 +#endif
13757 +
13758 +#ifndef __INT8_T__
13759 +typedef signed char INT8;
13760 +#define __INT8_T__
13761 +#endif
13762 +
13763 +#ifndef __UINT16_T__
13764 +typedef unsigned short UINT16;
13765 +#define __UINT16_T__
13766 +#endif
13767 +
13768 +#ifndef __USHORT_T__
13769 +typedef unsigned short USHORT;
13770 +#define __USHORT_T__
13771 +#endif
13772 +
13773 +#ifndef __INT16_T__
13774 +typedef signed short INT16;
13775 +#define __INT16_T__
13776 +#endif
13777 +
13778 +#ifndef __UINT32_T__
13779 +typedef unsigned int UINT32;
13780 +#define __UINT32_T__
13781 +#endif
13782 +
13783 +#ifndef __UINT_T__
13784 +typedef unsigned int UINT;
13785 +#define __UINT_T__
13786 +#endif
13787 +
13788 +#ifndef __INT32_T__
13789 +typedef signed int INT32;
13790 +#define __INT32_T__
13791 +#endif
13792 +
13793 +#ifndef __ULONG_T__
13794 +typedef unsigned long ULONG;
13795 +#define __ULONG_T__
13796 +#endif
13797 +
13798 +#ifndef __BOOL_T__
13799 +typedef int BOOL;
13800 +#define __BOOL_T__
13801 +#endif
13802 +
13803 +#ifndef __STATUS_T__
13804 +typedef int STATUS;
13805 +#define __STATUS_T__
13806 +#endif
13807 +
13808 +/*------------------------------------------------------------------------------------------*\
13809 +\*------------------------------------------------------------------------------------------*/
13810 +typedef void (*p_vlynq_intr_cntrl_isr_t)(void *,void *,void *);
13811 +typedef INT32 (*p_vlynq_interrupt_vector_set_t)(void *, UINT32, UINT32, INT32, INT32, INT32);
13812 +typedef INT32 (*p_vlynq_interrupt_vector_cntl_t)(void *, UINT32, INT32, UINT32);
13813 +typedef UINT32 (*p_vlynq_interrupt_get_count_t)(void *, UINT32);
13814 +typedef INT32 (*p_vlynq_install_isr_t)(void *, UINT32, p_vlynq_intr_cntrl_isr_t, void *, void *, void *);
13815 +typedef INT32 (*p_vlynq_uninstall_isr_t)(void *, UINT32, void *, void *, void *);
13816 +typedef void (*p_vlynq_root_isr_t)(void *);
13817 +typedef void (*p_vlynq_delay_t)(UINT32);
13818 +typedef INT32 (*p_vlynq_interrupt_vector_map_t)(void *, INT32, UINT32, UINT32);
13819 +typedef INT32 (*p_vlynq_interrupt_set_polarity_t)(void *, INT32, UINT32, INT32);
13820 +typedef INT32 (*p_vlynq_interrupt_get_polarity_t)(void *, INT32, UINT32);
13821 +typedef INT32 (*p_vlynq_interrupt_set_type_t)(void *, INT32, UINT32, INT32);
13822 +typedef INT32 (*p_vlynq_interrupt_get_type_t)(void *, INT32, UINT32);
13823 +typedef INT32 (*p_vlynq_interrupt_enable_t)(void *, INT32, UINT32);
13824 +typedef INT32 (*p_vlynq_interrupt_disable_t)(void *, INT32, UINT32);
13825 +
13826 +/*------------------------------------------------------------------------------------------*\
13827 +\*------------------------------------------------------------------------------------------*/
13828 +extern p_vlynq_interrupt_vector_set_t p_vlynq_interrupt_vector_set;
13829 +extern p_vlynq_interrupt_vector_cntl_t p_vlynq_interrupt_vector_cntl;
13830 +extern p_vlynq_interrupt_get_count_t p_vlynq_interrupt_get_count;
13831 +extern p_vlynq_install_isr_t p_vlynq_install_isr;
13832 +extern p_vlynq_uninstall_isr_t p_vlynq_uninstall_isr;
13833 +extern p_vlynq_root_isr_t p_vlynq_root_isr;
13834 +extern p_vlynq_delay_t p_vlynq_delay;
13835 +extern p_vlynq_interrupt_vector_map_t p_vlynq_interrupt_vector_map;
13836 +extern p_vlynq_interrupt_set_polarity_t p_vlynq_interrupt_set_polarity;
13837 +extern p_vlynq_interrupt_get_polarity_t p_vlynq_interrupt_get_polarity;
13838 +extern p_vlynq_interrupt_set_type_t p_vlynq_interrupt_set_type;
13839 +extern p_vlynq_interrupt_get_type_t p_vlynq_interrupt_get_type;
13840 +extern p_vlynq_interrupt_enable_t p_vlynq_interrupt_enable;
13841 +extern p_vlynq_interrupt_disable_t p_vlynq_interrupt_disable;
13842 +extern void *p_vlynqDevice0;
13843 +extern void *p_vlynqDevice1;
13844 +
13845 +/*------------------------------------------------------------------------------------------*\
13846 +\*------------------------------------------------------------------------------------------*/
13847 +enum _avalanche_need_ {
13848 + avalanche_need_vlynq,
13849 + avalanche_need_auto_mdix
13850 +};
13851 +
13852 +int avalanche_need(enum _avalanche_need_);
13853 +
13854 +#endif /*--- #ifndef _avalanche_types_h_ ---*/
13855 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
13856 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
13857 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-10-21 16:45:42.182067500 +0200
13858 @@ -0,0 +1,26 @@
13859 +/*******************************************************************************
13860 + * FILE PURPOSE: Interface port id Header file
13861 + *******************************************************************************
13862 + * FILE NAME: if_port.h
13863 + *
13864 + * DESCRIPTION: Header file carrying information about port ids of interfaces
13865 + *
13866 + *
13867 + * (C) Copyright 2003, Texas Instruments, Inc
13868 + ******************************************************************************/
13869 +#ifndef _IF_PORT_H_
13870 +#define _IF_PORT_H_
13871 +
13872 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
13873 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
13874 +#define AVALANCHE_USB_PORT_ID 2
13875 +#define AVALANCHE_WLAN_PORT_ID 3
13876 +
13877 +
13878 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
13879 +
13880 +/* The marvell ports occupy port ids from 4 to 8 */
13881 +/* so the next port id number should start at 9 */
13882 +
13883 +
13884 +#endif /* _IF_PORT_H_ */
13885 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
13886 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
13887 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-10-21 16:45:42.222070000 +0200
13888 @@ -0,0 +1,180 @@
13889 +#ifndef _SANGAM_H_
13890 +#define _SANGAM_H_
13891 +
13892 +#include <linux/config.h>
13893 +#include <asm/addrspace.h>
13894 +
13895 +/*----------------------------------------------------
13896 + * Sangam's Module Base Addresses
13897 + *--------------------------------------------------*/
13898 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
13899 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
13900 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
13901 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
13902 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
13903 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
13904 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
13905 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
13906 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
13907 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
13908 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
13909 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
13910 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
13911 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
13912 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
13913 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
13914 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
13915 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
13916 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
13917 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
13918 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
13919 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
13920 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
13921 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
13922 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
13923 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
13924 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
13925 +
13926 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
13927 +
13928 +
13929 +/*----------------------------------------------------
13930 + * Sangam Interrupt Map (Primary Interrupts)
13931 + *--------------------------------------------------*/
13932 +
13933 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
13934 +#define AVALANCHE_EXT_INT_0 1
13935 +#define AVALANCHE_EXT_INT_1 2
13936 +/* Line# 3 to 4 are reserved */
13937 +#define AVALANCHE_TIMER_0_INT 5
13938 +#define AVALANCHE_TIMER_1_INT 6
13939 +#define AVALANCHE_UART0_INT 7
13940 +#define AVALANCHE_UART1_INT 8
13941 +#define AVALANCHE_DMA_INT0 9
13942 +#define AVALANCHE_DMA_INT1 10
13943 +/* Line# 11 to 14 are reserved */
13944 +#define AVALANCHE_ATM_SAR_INT 15
13945 +/* Line# 16 to 18 are reserved */
13946 +#define AVALANCHE_LOW_CPMAC_INT 19
13947 +/* Line# 20 is reserved */
13948 +#define AVALANCHE_LOW_VLYNQ_INT 21
13949 +#define AVALANCHE_CODEC_WAKEUP_INT 22
13950 +/* Line# 23 is reserved */
13951 +#define AVALANCHE_USB_SLAVE_INT 24
13952 +#define AVALANCHE_HIGH_VLYNQ_INT 25
13953 +/* Line# 26 to 27 are reserved */
13954 +#define AVALANCHE_UNIFIED_PHY_INT 28
13955 +#define AVALANCHE_I2C_INT 29
13956 +#define AVALANCHE_DMA_INT2 30
13957 +#define AVALANCHE_DMA_INT3 31
13958 +/* Line# 32 is reserved */
13959 +#define AVALANCHE_HIGH_CPMAC_INT 33
13960 +/* Line# 34 to 36 is reserved */
13961 +#define AVALANCHE_VDMA_VT_RX_INT 37
13962 +#define AVALANCHE_VDMA_VT_TX_INT 38
13963 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
13964 +
13965 +
13966 +#define AVALANCHE_EMIF_INT 47
13967 +
13968 +
13969 +
13970 +/*-----------------------------------------------------------
13971 + * Sangam's Reset Bits
13972 + *---------------------------------------------------------*/
13973 +
13974 +#define AVALANCHE_UART0_RESET_BIT 0
13975 +#define AVALANCHE_UART1_RESET_BIT 1
13976 +#define AVALANCHE_I2C_RESET_BIT 2
13977 +#define AVALANCHE_TIMER0_RESET_BIT 3
13978 +#define AVALANCHE_TIMER1_RESET_BIT 4
13979 +/* Reset bit 5 is reserved. */
13980 +#define AVALANCHE_GPIO_RESET_BIT 6
13981 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
13982 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
13983 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
13984 +/* Reset bit 10 is reserved. */
13985 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
13986 +#define AVALANCHE_FSER_RESET_BIT 12
13987 +/* Reset bit 13 to 15 are reserved */
13988 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
13989 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
13990 +#define AVALANCHE_MCDMA_RESET_BIT 18
13991 +#define AVALANCHE_BIST_RESET_BIT 19
13992 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
13993 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
13994 +#define AVALANCHE_MDIO_RESET_BIT 22
13995 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
13996 +/* Reset bit 24 to 25 are reserved */
13997 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
13998 +/* Reset bit 27 to 31 are reserved */
13999 +
14000 +
14001 +#define AVALANCHE_POWER_MODULE_USBSP 0
14002 +#define AVALANCHE_POWER_MODULE_WDTP 1
14003 +#define AVALANCHE_POWER_MODULE_UT0P 2
14004 +#define AVALANCHE_POWER_MODULE_UT1P 3
14005 +#define AVALANCHE_POWER_MODULE_IICP 4
14006 +#define AVALANCHE_POWER_MODULE_VDMAP 5
14007 +#define AVALANCHE_POWER_MODULE_GPIOP 6
14008 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
14009 +#define AVALANCHE_POWER_MODULE_SARP 8
14010 +#define AVALANCHE_POWER_MODULE_ADSLP 9
14011 +#define AVALANCHE_POWER_MODULE_EMIFP 10
14012 +#define AVALANCHE_POWER_MODULE_ADSPP 12
14013 +#define AVALANCHE_POWER_MODULE_RAMP 13
14014 +#define AVALANCHE_POWER_MODULE_ROMP 14
14015 +#define AVALANCHE_POWER_MODULE_DMAP 15
14016 +#define AVALANCHE_POWER_MODULE_BISTP 16
14017 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
14018 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
14019 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
14020 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
14021 +#define AVALANCHE_POWER_MODULE_EPHYP 24
14022 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
14023 +
14024 +
14025 +
14026 +
14027 +
14028 +/*
14029 + * Sangam board vectors
14030 + */
14031 +
14032 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
14033 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
14034 +
14035 +/*-----------------------------------------------------------------------------
14036 + * Sangam's system register.
14037 + *
14038 + *---------------------------------------------------------------------------*/
14039 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
14040 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
14041 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
14042 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
14043 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
14044 +
14045 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
14046 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
14047 +
14048 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
14049 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
14050 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
14051 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
14052 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
14053 +
14054 +/*
14055 + * Yamon Prom print address.
14056 + */
14057 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
14058 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
14059 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
14060 +
14061 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
14062 +
14063 +#define AVALANCHE_GPIO_PIN_COUNT 32
14064 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
14065 +
14066 +#include "sangam_boards.h"
14067 +
14068 +#endif /*_SANGAM_H_ */
14069 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
14070 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
14071 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-10-21 16:45:42.182067500 +0200
14072 @@ -0,0 +1,77 @@
14073 +#ifndef _SANGAM_BOARDS_H
14074 +#define _SANGAM_BOARDS_H
14075 +
14076 +// Let us define board specific information here.
14077 +
14078 +
14079 +#if defined(CONFIG_AR7DB)
14080 +
14081 +#define AFECLK_FREQ 35328000
14082 +#define REFCLK_FREQ 25000000
14083 +#define OSC3_FREQ 24000000
14084 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14085 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
14086 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14087 +
14088 +#endif
14089 +
14090 +
14091 +#if defined(CONFIG_AR7RD)
14092 +#define AFECLK_FREQ 35328000
14093 +#define REFCLK_FREQ 25000000
14094 +#define OSC3_FREQ 24000000
14095 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14096 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
14097 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14098 +#endif
14099 +
14100 +
14101 +#if defined(CONFIG_AR7WI)
14102 +#define AFECLK_FREQ 35328000
14103 +#define REFCLK_FREQ 25000000
14104 +#define OSC3_FREQ 24000000
14105 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14106 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
14107 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14108 +#endif
14109 +
14110 +
14111 +#if defined(CONFIG_AR7V)
14112 +#define AFECLK_FREQ 35328000
14113 +#define REFCLK_FREQ 25000000
14114 +#define OSC3_FREQ 24000000
14115 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14116 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
14117 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14118 +#endif
14119 +
14120 +
14121 +#if defined(CONFIG_AR7WRD)
14122 +#define AFECLK_FREQ 35328000
14123 +#define REFCLK_FREQ 25000000
14124 +#define OSC3_FREQ 24000000
14125 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14126 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
14127 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14128 +#endif
14129 +
14130 +
14131 +#if defined(CONFIG_AR7VWI)
14132 +#define AFECLK_FREQ 35328000
14133 +#define REFCLK_FREQ 25000000
14134 +#define OSC3_FREQ 24000000
14135 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
14136 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
14137 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
14138 +#endif
14139 +
14140 +
14141 +#if defined CONFIG_SEAD2
14142 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
14143 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
14144 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
14145 +#include <asm/mips-boards/sead.h>
14146 +#endif
14147 +
14148 +
14149 +#endif
14150 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
14151 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
14152 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-10-21 16:45:42.222070000 +0200
14153 @@ -0,0 +1,338 @@
14154 +/******************************************************************************
14155 + * FILE PURPOSE: TNETD73xx Common Header File
14156 + ******************************************************************************
14157 + * FILE NAME: tnetd73xx.h
14158 + *
14159 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
14160 + *
14161 + * REVISION HISTORY:
14162 + * 27 Nov 02 - PSP TII
14163 + *
14164 + * (C) Copyright 2002, Texas Instruments, Inc
14165 + *******************************************************************************/
14166 +
14167 +/*
14168 + *
14169 + *
14170 + * These are const, typedef, and api definitions for tnetd73xx.
14171 + *
14172 + * NOTES:
14173 + * 1. This file may be included into both C and Assembly files.
14174 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
14175 + * avoid C data types (typedefs) below;
14176 + * - for .c files, you don't have to do anything special.
14177 + *
14178 + * 2. This file has a number of sections for each SOC subsystem. When adding
14179 + * a new constant, find the subsystem you are working on and follow the
14180 + * name pattern. If you are adding another typedef for your interface, please,
14181 + * place it with other typedefs and function prototypes.
14182 + *
14183 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
14184 + * cluttering. Include such items directly into the module's .c file or have a
14185 + * local .h file to pass data between smaller modules. This file defines only
14186 + * shared items.
14187 + */
14188 +
14189 +#ifndef __TNETD73XX_H__
14190 +#define __TNETD73XX_H__
14191 +
14192 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
14193 +
14194 +extern unsigned int tnetd73xx_mips_freq;
14195 +extern unsigned int tnetd73xx_vbus_freq;
14196 +
14197 +#include "tnetd73xx_err.h"
14198 +
14199 +#endif /* _ASMLANGUAGE */
14200 +
14201 +
14202 +/*******************************************************************************************
14203 +* Emerald core specific
14204 +******************************************************************************************** */
14205 +
14206 +#ifdef BIG_ENDIAN
14207 +#elif defined(LITTLE_ENDIAN)
14208 +#else
14209 +#error Need to define endianism
14210 +#endif
14211 +
14212 +#ifndef KSEG_MSK
14213 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
14214 +#endif
14215 +
14216 +#ifndef KSEG_INV_MASK
14217 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
14218 +#endif
14219 +
14220 +#ifndef KSEG0_BASE
14221 +#define KSEG0_BASE 0x80000000
14222 +#endif
14223 +
14224 +#ifndef KSEG1_BASE
14225 +#define KSEG1_BASE 0xA0000000
14226 +#endif
14227 +
14228 +#ifndef KSEG0
14229 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
14230 +#endif
14231 +
14232 +#ifndef KSEG1
14233 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
14234 +#endif
14235 +
14236 +#ifndef KUSEG
14237 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
14238 +#endif
14239 +
14240 +#ifndef PHYS_ADDR
14241 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
14242 +#endif
14243 +
14244 +#ifndef PHYS_TO_K0
14245 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
14246 +#endif
14247 +
14248 +#ifndef PHYS_TO_K1
14249 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
14250 +#endif
14251 +
14252 +#ifndef REG8_ADDR
14253 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
14254 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
14255 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
14256 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
14257 +#endif
14258 +
14259 +#ifndef REG16_ADDR
14260 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
14261 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
14262 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
14263 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
14264 +#endif
14265 +
14266 +#ifndef REG32_ADDR
14267 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
14268 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
14269 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
14270 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
14271 +#endif
14272 +
14273 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
14274 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
14275 +#endif
14276 +
14277 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
14278 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
14279 +#endif
14280 +
14281 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
14282 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
14283 +#endif
14284 +
14285 +/* TNETD73XX chip definations */
14286 +
14287 +#define FREQ_1MHZ 1000000
14288 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
14289 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
14290 +
14291 +#ifdef AR7SEAD2
14292 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
14293 +#else
14294 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
14295 +#endif
14296 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
14297 +
14298 +
14299 +
14300 +/* Module base addresses */
14301 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
14302 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
14303 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
14304 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
14305 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
14306 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
14307 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
14308 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
14309 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
14310 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
14311 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
14312 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
14313 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
14314 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
14315 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
14316 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
14317 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
14318 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
14319 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
14320 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
14321 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
14322 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
14323 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
14324 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
14325 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
14326 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
14327 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
14328 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
14329 +
14330 +/* BBIF Registers */
14331 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
14332 +
14333 +/* Device Configuration Latch Registers */
14334 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
14335 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
14336 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
14337 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
14338 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
14339 +
14340 +/* GPIO Control */
14341 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
14342 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
14343 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
14344 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
14345 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
14346 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
14347 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
14348 +
14349 +/* Reset Control */
14350 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
14351 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
14352 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
14353 +
14354 +/* Power Control */
14355 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
14356 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
14357 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
14358 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
14359 +
14360 +/* Clock Control */
14361 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
14362 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
14363 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
14364 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
14365 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
14366 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
14367 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
14368 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
14369 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
14370 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
14371 +
14372 +/* EMIF control */
14373 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
14374 +
14375 +/* UART */
14376 +#ifdef AR7SEAD2
14377 +#define TNETD73XX_UART_FREQ 3686400
14378 +#else
14379 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
14380 +#endif
14381 +
14382 +/* Interrupt Controller */
14383 +
14384 +/* Primary interrupts */
14385 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
14386 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
14387 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
14388 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
14389 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
14390 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
14391 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
14392 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
14393 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
14394 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
14395 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
14396 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
14397 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
14398 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
14399 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
14400 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
14401 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
14402 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
14403 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
14404 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
14405 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
14406 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
14407 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
14408 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
14409 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
14410 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
14411 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
14412 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
14413 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
14414 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
14415 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
14416 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
14417 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
14418 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
14419 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
14420 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
14421 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
14422 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
14423 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
14424 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
14425 +
14426 +/* Secondary interrupts */
14427 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
14428 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
14429 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
14430 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
14431 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
14432 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
14433 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
14434 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
14435 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
14436 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
14437 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
14438 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
14439 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
14440 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
14441 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
14442 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
14443 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
14444 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
14445 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
14446 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
14447 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
14448 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
14449 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
14450 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
14451 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
14452 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
14453 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
14454 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
14455 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
14456 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
14457 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
14458 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
14459 +
14460 +/* These ugly macros are to access the -1 registers, like config1 */
14461 +#define MFC0_SEL1_OPCODE(dst, src)\
14462 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
14463 + nop; \
14464 + nop; \
14465 + nop
14466 +
14467 +#define MTC0_SEL1_OPCODE(dst, src)\
14468 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
14469 + nop; \
14470 + nop; \
14471 + nop
14472 +
14473 +
14474 +/* Below are Jade core specific */
14475 +#define CFG0_4K_IL_MASK 0x00380000
14476 +#define CFG0_4K_IL_SHIFT 19
14477 +#define CFG0_4K_IA_MASK 0x00070000
14478 +#define CFG0_4K_IA_SHIFT 16
14479 +#define CFG0_4K_IS_MASK 0x01c00000
14480 +#define CFG0_4K_IS_SHIFT 22
14481 +
14482 +#define CFG0_4K_DL_MASK 0x00001c00
14483 +#define CFG0_4K_DL_SHIFT 10
14484 +#define CFG0_4K_DA_MASK 0x00000380
14485 +#define CFG0_4K_DA_SHIFT 7
14486 +#define CFG0_4K_DS_MASK 0x0000E000
14487 +#define CFG0_4K_DS_SHIFT 13
14488 +
14489 +
14490 +
14491 +#endif /* __TNETD73XX_H_ */
14492 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
14493 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
14494 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-10-21 16:45:42.222070000 +0200
14495 @@ -0,0 +1,42 @@
14496 +/******************************************************************************
14497 + * FILE PURPOSE: TNETD73xx Error Definations Header File
14498 + ******************************************************************************
14499 + * FILE NAME: tnetd73xx_err.h
14500 + *
14501 + * DESCRIPTION: Error definations for TNETD73XX
14502 + *
14503 + * REVISION HISTORY:
14504 + * 27 Nov 02 - PSP TII
14505 + *
14506 + * (C) Copyright 2002, Texas Instruments, Inc
14507 + *******************************************************************************/
14508 +
14509 +
14510 +#ifndef __TNETD73XX_ERR_H__
14511 +#define __TNETD73XX_ERR_H__
14512 +
14513 +typedef enum TNETD73XX_ERR_t
14514 +{
14515 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
14516 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
14517 +
14518 + /* Pointers and args */
14519 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
14520 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
14521 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
14522 +
14523 + /* Memory issues */
14524 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
14525 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
14526 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
14527 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
14528 +
14529 + /* Device issues */
14530 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
14531 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
14532 +
14533 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
14534 +
14535 +} TNETD73XX_ERR;
14536 +
14537 +#endif /* __TNETD73XX_ERR_H__ */
14538 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
14539 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
14540 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-10-21 16:45:42.222070000 +0200
14541 @@ -0,0 +1,239 @@
14542 +/******************************************************************************
14543 + * FILE PURPOSE: TNETD73xx Misc modules API Header
14544 + ******************************************************************************
14545 + * FILE NAME: tnetd73xx_misc.h
14546 + *
14547 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
14548 + * FSER Modules API
14549 + * As per TNETD73xx specifications
14550 + *
14551 + * REVISION HISTORY:
14552 + * 27 Nov 02 - Sharath Kumar PSP TII
14553 + * 14 Feb 03 - Anant Gole PSP TII
14554 + *
14555 + * (C) Copyright 2002, Texas Instruments, Inc
14556 + *******************************************************************************/
14557 +
14558 +#ifndef __TNETD73XX_MISC_H__
14559 +#define __TNETD73XX_MISC_H__
14560 +
14561 +/*****************************************************************************
14562 + * Reset Control Module
14563 + *****************************************************************************/
14564 +
14565 +typedef enum TNETD73XX_RESET_MODULE_tag
14566 +{
14567 + RESET_MODULE_UART0 = 0,
14568 + RESET_MODULE_UART1 = 1,
14569 + RESET_MODULE_I2C = 2,
14570 + RESET_MODULE_TIMER0 = 3,
14571 + RESET_MODULE_TIMER1 = 4,
14572 + RESET_MODULE_GPIO = 6,
14573 + RESET_MODULE_ADSLSS = 7,
14574 + RESET_MODULE_USBS = 8,
14575 + RESET_MODULE_SAR = 9,
14576 + RESET_MODULE_VDMA_VT = 11,
14577 + RESET_MODULE_FSER = 12,
14578 + RESET_MODULE_VLYNQ1 = 16,
14579 + RESET_MODULE_EMAC0 = 17,
14580 + RESET_MODULE_DMA = 18,
14581 + RESET_MODULE_BIST = 19,
14582 + RESET_MODULE_VLYNQ0 = 20,
14583 + RESET_MODULE_EMAC1 = 21,
14584 + RESET_MODULE_MDIO = 22,
14585 + RESET_MODULE_ADSLSS_DSP = 23,
14586 + RESET_MODULE_EPHY = 26
14587 +} TNETD73XX_RESET_MODULE_T;
14588 +
14589 +typedef enum TNETD73XX_RESET_CTRL_tag
14590 +{
14591 + IN_RESET = 0,
14592 + OUT_OF_RESET
14593 +} TNETD73XX_RESET_CTRL_T;
14594 +
14595 +typedef enum TNETD73XX_SYS_RST_MODE_tag
14596 +{
14597 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
14598 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
14599 +} TNETD73XX_SYS_RST_MODE_T;
14600 +
14601 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
14602 +{
14603 + HARDWARE_RESET = 0,
14604 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
14605 + WATCHDOG_RESET,
14606 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
14607 +} TNETD73XX_SYS_RESET_STATUS_T;
14608 +
14609 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
14610 + TNETD73XX_RESET_CTRL_T reset_ctrl);
14611 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
14612 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
14613 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
14614 +
14615 +/*****************************************************************************
14616 + * Power Control Module
14617 + *****************************************************************************/
14618 +
14619 +typedef enum TNETD73XX_POWER_MODULE_tag
14620 +{
14621 + POWER_MODULE_USBSP = 0,
14622 + POWER_MODULE_WDTP = 1,
14623 + POWER_MODULE_UT0P = 2,
14624 + POWER_MODULE_UT1P = 3,
14625 + POWER_MODULE_IICP = 4,
14626 + POWER_MODULE_VDMAP = 5,
14627 + POWER_MODULE_GPIOP = 6,
14628 + POWER_MODULE_VLYNQ1P = 7,
14629 + POWER_MODULE_SARP = 8,
14630 + POWER_MODULE_ADSLP = 9,
14631 + POWER_MODULE_EMIFP = 10,
14632 + POWER_MODULE_ADSPP = 12,
14633 + POWER_MODULE_RAMP = 13,
14634 + POWER_MODULE_ROMP = 14,
14635 + POWER_MODULE_DMAP = 15,
14636 + POWER_MODULE_BISTP = 16,
14637 + POWER_MODULE_TIMER0P = 18,
14638 + POWER_MODULE_TIMER1P = 19,
14639 + POWER_MODULE_EMAC0P = 20,
14640 + POWER_MODULE_EMAC1P = 22,
14641 + POWER_MODULE_EPHYP = 24,
14642 + POWER_MODULE_VLYNQ0P = 27,
14643 +} TNETD73XX_POWER_MODULE_T;
14644 +
14645 +typedef enum TNETD73XX_POWER_CTRL_tag
14646 +{
14647 + POWER_CTRL_POWER_UP = 0,
14648 + POWER_CTRL_POWER_DOWN
14649 +} TNETD73XX_POWER_CTRL_T;
14650 +
14651 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
14652 +{
14653 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
14654 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
14655 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
14656 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
14657 +} TNETD73XX_SYS_POWER_MODE_T;
14658 +
14659 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
14660 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
14661 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
14662 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
14663 +
14664 +/*****************************************************************************
14665 + * Wakeup Control
14666 + *****************************************************************************/
14667 +
14668 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
14669 +{
14670 + WAKEUP_INT0 = 1,
14671 + WAKEUP_INT1 = 2,
14672 + WAKEUP_INT2 = 4,
14673 + WAKEUP_INT3 = 8
14674 +} TNETD73XX_WAKEUP_INTERRUPT_T;
14675 +
14676 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
14677 +{
14678 + WAKEUP_DISABLED = 0,
14679 + WAKEUP_ENABLED
14680 +} TNETD73XX_WAKEUP_CTRL_T;
14681 +
14682 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
14683 +{
14684 + WAKEUP_ACTIVE_HIGH = 0,
14685 + WAKEUP_ACTIVE_LOW
14686 +} TNETD73XX_WAKEUP_POLARITY_T;
14687 +
14688 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
14689 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
14690 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
14691 +
14692 +/*****************************************************************************
14693 + * FSER Control
14694 + *****************************************************************************/
14695 +
14696 +typedef enum TNETD73XX_FSER_MODE_tag
14697 +{
14698 + FSER_I2C = 0,
14699 + FSER_UART = 1
14700 +} TNETD73XX_FSER_MODE_T;
14701 +
14702 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
14703 +
14704 +/*****************************************************************************
14705 + * Clock Control
14706 + *****************************************************************************/
14707 +
14708 +#define CLK_MHZ(x) ( (x) * 1000000 )
14709 +
14710 +typedef enum TNETD73XX_CLKC_ID_tag
14711 +{
14712 + CLKC_SYS = 0,
14713 + CLKC_MIPS,
14714 + CLKC_USB,
14715 + CLKC_ADSLSS
14716 +} TNETD73XX_CLKC_ID_T;
14717 +
14718 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
14719 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
14720 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
14721 +
14722 +/*****************************************************************************
14723 + * GPIO Control
14724 + *****************************************************************************/
14725 +
14726 +typedef enum TNETD73XX_GPIO_PIN_tag
14727 +{
14728 + GPIO_UART0_RD = 0,
14729 + GPIO_UART0_TD = 1,
14730 + GPIO_UART0_RTS = 2,
14731 + GPIO_UART0_CTS = 3,
14732 + GPIO_FSER_CLK = 4,
14733 + GPIO_FSER_D = 5,
14734 + GPIO_EXT_AFE_SCLK = 6,
14735 + GPIO_EXT_AFE_TX_FS = 7,
14736 + GPIO_EXT_AFE_TXD = 8,
14737 + GPIO_EXT_AFE_RS_FS = 9,
14738 + GPIO_EXT_AFE_RXD1 = 10,
14739 + GPIO_EXT_AFE_RXD0 = 11,
14740 + GPIO_EXT_AFE_CDIN = 12,
14741 + GPIO_EXT_AFE_CDOUT = 13,
14742 + GPIO_EPHY_SPEED100 = 14,
14743 + GPIO_EPHY_LINKON = 15,
14744 + GPIO_EPHY_ACTIVITY = 16,
14745 + GPIO_EPHY_FDUPLEX = 17,
14746 + GPIO_EINT0 = 18,
14747 + GPIO_EINT1 = 19,
14748 + GPIO_MBSP0_TCLK = 20,
14749 + GPIO_MBSP0_RCLK = 21,
14750 + GPIO_MBSP0_RD = 22,
14751 + GPIO_MBSP0_TD = 23,
14752 + GPIO_MBSP0_RFS = 24,
14753 + GPIO_MBSP0_TFS = 25,
14754 + GPIO_MII_DIO = 26,
14755 + GPIO_MII_DCLK = 27,
14756 +} TNETD73XX_GPIO_PIN_T;
14757 +
14758 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
14759 +{
14760 + FUNCTIONAL_PIN = 0,
14761 + GPIO_PIN = 1
14762 +} TNETD73XX_GPIO_PIN_MODE_T;
14763 +
14764 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
14765 +{
14766 + GPIO_OUTPUT_PIN = 0,
14767 + GPIO_INPUT_PIN = 1
14768 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
14769 +
14770 +void tnetd73xx_gpio_init(void);
14771 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
14772 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
14773 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
14774 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
14775 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
14776 +
14777 +/* TNETD73XX Revision */
14778 +__u32 tnetd73xx_get_revision(void);
14779 +
14780 +#endif /* __TNETD73XX_MISC_H__ */
14781 diff -urN linux.old/include/asm-mips/ar7/vlynq.h linux.dev/include/asm-mips/ar7/vlynq.h
14782 --- linux.old/include/asm-mips/ar7/vlynq.h 1970-01-01 01:00:00.000000000 +0100
14783 +++ linux.dev/include/asm-mips/ar7/vlynq.h 2005-10-21 16:45:47.858422250 +0200
14784 @@ -0,0 +1,610 @@
14785 +/***************************************************************************
14786 +**+----------------------------------------------------------------------+**
14787 +**| **** |**
14788 +**| **** |**
14789 +**| ******o*** |**
14790 +**| ********_///_**** |**
14791 +**| ***** /_//_/ **** |**
14792 +**| ** ** (__/ **** |**
14793 +**| ********* |**
14794 +**| **** |**
14795 +**| *** |**
14796 +**| |**
14797 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
14798 +**| ALL RIGHTS RESERVED |**
14799 +**| |**
14800 +**| Permission is hereby granted to licensees of Texas Instruments |**
14801 +**| Incorporated (TI) products to use this computer program for the sole |**
14802 +**| purpose of implementing a licensee product based on TI products. |**
14803 +**| No other rights to reproduce, use, or disseminate this computer |**
14804 +**| program, whether in part or in whole, are granted. |**
14805 +**| |**
14806 +**| TI makes no representation or warranties with respect to the |**
14807 +**| performance of this computer program, and specifically disclaims |**
14808 +**| any responsibility for any damages, special or consequential, |**
14809 +**| connected with the use of this program. |**
14810 +**| |**
14811 +**+----------------------------------------------------------------------+**
14812 +***************************************************************************/
14813 +
14814 +/*********************************************************************************
14815 + * ------------------------------------------------------------------------------
14816 + * Module : vlynq_hal.h
14817 + * Description :
14818 + * This header file provides the set of functions exported by the
14819 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
14820 + * ------------------------------------------------------------------------------
14821 + *********************************************************************************/
14822 +
14823 +#ifndef _VLYNQ_HAL_H_
14824 +#define _VLYNQ_HAL_H_
14825 +
14826 +/* Enable/Disable debug feature */
14827 +#undef VLYNQ_DEBUG
14828 +
14829 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
14830 +#define debugPrint(format,args...)
14831 +#else
14832 +#define debugPrint(format,args...)
14833 +#endif
14834 +
14835 + /* number of VLYNQ memory regions supported */
14836 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
14837 +
14838 + /* Max.number of external interrupt inputs supported by VLYNQ module */
14839 +#define VLYNQ_IVR_MAXIVR 0x08
14840 +
14841 +#define VLYNQ_CLK_DIV_MAX 0x08
14842 +#define VLYNQ_CLK_DIV_MIN 0x01
14843 +
14844 +
14845 +/*** the total number of entries allocated for ICB would be
14846 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
14847 +#define VLYNQ_IVR_CHAIN_SLOTS 10
14848 +
14849 +
14850 +/* Error defines */
14851 +#define VLYNQ_SUCCESS 0
14852 +
14853 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
14854 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
14855 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
14856 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
14857 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
14858 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
14859 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
14860 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
14861 +
14862 +/* Vlynq Defines and Macros */
14863 +
14864 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
14865 +
14866 +/* Base address of module */
14867 +#define VLYNQ_BASE (pdev->module_base)
14868 +
14869 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
14870 +
14871 +#define VLYNQ_REV_OFFSET 0x0000
14872 +#define VLYNQ_CTRL_OFFSET 0x0004
14873 +#define VLYNQ_STATUS_OFFSET 0x0008
14874 +#define VLYNQ_INT_STAT_OFFSET 0x0010
14875 +#define VLYNQ_INT_PEND_OFFSET 0x0014
14876 +#define VLYNQ_INT_PTR_OFFSET 0x0018
14877 +#define VLYNQ_TXMAP_OFFSET 0x001c
14878 +
14879 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
14880 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
14881 +
14882 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
14883 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
14884 +
14885 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
14886 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
14887 +
14888 +#define VLYNQ_REV_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
14889 +#define VLYNQ_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
14890 +#define VLYNQ_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
14891 +#define VLYNQ_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
14892 +#define VLYNQ_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
14893 +#define VLYNQ_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
14894 +#define VLYNQ_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
14895 +
14896 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14897 +#define VLYNQ_RXMAP_SIZE_REG(map) \
14898 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
14899 +
14900 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14901 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
14902 + *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
14903 +
14904 +#define VLYNQ_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
14905 +
14906 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
14907 +#define VLYNQ_IVR_OFFSET(ivr) \
14908 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
14909 +
14910 +#define VLYNQ_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(0)) )
14911 +#define VLYNQ_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_IVR_OFFSET(4)) )
14912 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14913 +
14914 +#define VLYNQ_IVR_INTEN(ivr) (((unsigned int)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
14915 +#define VLYNQ_IVR_INTTYPE(ivr) (((unsigned int)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
14916 +#define VLYNQ_IVR_INTPOL(ivr) (((unsigned int)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
14917 +#define VLYNQ_IVR_INTVEC(ivr) (((unsigned int)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
14918 +#define VLYNQ_IVR_INTALL(ivr) (((unsigned int)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
14919 +
14920 +
14921 +
14922 +/*********************************
14923 + * Remote VLYNQ register set *
14924 + *********************************/
14925 +
14926 +#define VLYNQ_R_REV_OFFSET 0x0080
14927 +#define VLYNQ_R_CTRL_OFFSET 0x0084
14928 +#define VLYNQ_R_STATUS_OFFSET 0x0088
14929 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
14930 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
14931 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
14932 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
14933 +
14934 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
14935 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
14936 +
14937 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
14938 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
14939 +
14940 +#define VLYNQ_R_REV_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
14941 +#define VLYNQ_R_CTRL_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
14942 +#define VLYNQ_R_STATUS_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
14943 +#define VLYNQ_R_INT_STAT_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
14944 +#define VLYNQ_R_INT_PEND_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
14945 +#define VLYNQ_R_INT_PTR_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
14946 +#define VLYNQ_R_TXMAP_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
14947 +
14948 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14949 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
14950 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
14951 +
14952 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
14953 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
14954 + *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
14955 +
14956 +#define VLYNQ_R_CHIP_VER_REG *((volatile unsigned int *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
14957 +
14958 +#define VLYNQ_R_IVR_OFFSET(ivr) \
14959 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
14960 +
14961 +
14962 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
14963 +#define VLYNQ_R_IVR_03TO00_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(0)) )
14964 +#define VLYNQ_R_IVR_07TO04_REG *((volatile unsigned int*) (VLYNQ_R_IVR_OFFSET(4)) )
14965 +
14966 +
14967 +/****End of remote register set definition******/
14968 +
14969 +
14970 +/*** Masks for individual register fields ***/
14971 +
14972 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
14973 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
14974 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
14975 +
14976 +
14977 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
14978 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
14979 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
14980 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
14981 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
14982 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
14983 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
14984 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
14985 +
14986 +
14987 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
14988 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
14989 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
14990 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
14991 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
14992 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
14993 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
14994 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
14995 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
14996 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
14997 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
14998 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
14999 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
15000 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
15001 +
15002 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
15003 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
15004 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
15005 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
15006 +
15007 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
15008 +
15009 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
15010 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
15011 +
15012 +#define VLYNQ_IVR_INTEN_MASK 0x80
15013 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
15014 +#define VLYNQ_IVR_INTPOL_MASK 0x20
15015 +
15016 +
15017 +/**** Helper macros ****/
15018 +
15019 +#define VLYNQ_RESETCB(arg) \
15020 + if( pdev->reset_cb != NULL) \
15021 + { \
15022 + (pdev->reset_cb)(pdev, (arg)); \
15023 + }
15024 +
15025 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
15026 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
15027 +
15028 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
15029 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
15030 +
15031 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
15032 +
15033 +
15034 +/*************************************
15035 + * Enums *
15036 + *************************************/
15037 +
15038 +/* Initialization options define what operations are
15039 + * undertaken during vlynq module initialization */
15040 +typedef enum
15041 +{
15042 + /* Init host local memory regions.This allows
15043 + * local host access remote memory regions */
15044 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
15045 + /* Init host remote memory regions.This allows
15046 + * remote device access local memory regions */
15047 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
15048 + /* Init local interrupt config*/
15049 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
15050 + /* Init remote interrupt config*/
15051 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
15052 + /* Check link during initialization*/
15053 + VLYNQ_INIT_CHECK_LINK =0x10,
15054 + /* configure clock during init */
15055 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
15056 + /* Clear errors during init */
15057 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
15058 + /* All options */
15059 + VLYNQ_INIT_PERFORM_ALL =0x7F
15060 +}VLYNQ_INIT_OPTIONS;
15061 +
15062 +
15063 +/* VLYNQ_DEV_TYPE identifies local or remote device */
15064 +typedef enum
15065 +{
15066 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
15067 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
15068 +}VLYNQ_DEV_TYPE;
15069 +
15070 +
15071 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
15072 +typedef enum
15073 +{
15074 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
15075 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
15076 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
15077 +}VLYNQ_CLK_SOURCE;
15078 +
15079 +
15080 +/* VLYNQ_DRV_STATE indicates the current driver state */
15081 +typedef enum
15082 +{
15083 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
15084 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
15085 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
15086 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
15087 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
15088 +}VLYNQ_DRV_STATE;
15089 +
15090 +
15091 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
15092 +typedef enum
15093 +{
15094 + VLYNQ_BUS_WIDTH_3 = 3,
15095 + VLYNQ_BUS_WIDTH_5 = 5,
15096 + VLYNQ_BUS_WIDTH_7 = 7,
15097 + VLYNQ_BUS_WIDTH_9 = 9
15098 +}VLYNQ_BUS_WIDTH;
15099 +
15100 +
15101 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
15102 + * interrupts are processed by the host or passed on to the
15103 + * remote device.
15104 + */
15105 +typedef enum
15106 +{
15107 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
15108 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
15109 +}VLYNQ_LOCAL_INT_CONFIG;
15110 +
15111 +
15112 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
15113 + * interrupts are to be handled by the SOC system ISR
15114 + * or via the vlynq root ISR
15115 + */
15116 +typedef enum
15117 +{
15118 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
15119 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
15120 +}VLYNQ_REMOTE_INT_CONFIG;
15121 +
15122 +
15123 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
15124 +typedef enum
15125 +{
15126 + VLYNQ_INTR_ACTIVE_HIGH = 0,
15127 + VLYNQ_INTR_ACTIVE_LOW = 1
15128 +}VLYNQ_INTR_POLARITY;
15129 +
15130 +
15131 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
15132 +typedef enum
15133 +{
15134 + VLYNQ_INTR_LEVEL = 0,
15135 + VLYNQ_INTR_PULSED = 1
15136 +}VLYNQ_INTR_TYPE;
15137 +
15138 +
15139 +/* VLYNQ_RESET_MODE - vlynq reset mode */
15140 +typedef enum
15141 +{
15142 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
15143 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
15144 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
15145 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
15146 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
15147 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
15148 +}VLYNQ_RESET_MODE;
15149 +
15150 +
15151 +
15152 +/*************************************
15153 + * Typedefs *
15154 + *************************************/
15155 +
15156 +struct VLYNQ_DEV_t; /*forward declaration*/
15157 +
15158 +/*--------Function Pointers defintions -----------*/
15159 +
15160 +/* prototype for interrupt handler definition */
15161 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
15162 +
15163 +typedef void
15164 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
15165 +
15166 +typedef void
15167 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
15168 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
15169 + unsigned int dwStatRegVal); /* Value of the relevant status register */
15170 +
15171 +
15172 +/*-------Structure Definitions------------*/
15173 +
15174 +typedef struct VLYNQ_MEMORY_MAP_t
15175 +{
15176 + unsigned int Txmap;
15177 + unsigned int RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
15178 + unsigned int RxSize[VLYNQ_MAX_MEMORY_REGIONS];
15179 +}VLYNQ_MEMORY_MAP;
15180 +
15181 +
15182 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
15183 + * settings in vlynq Control register */
15184 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
15185 +{
15186 + /* vlynq interrupts handled by host or remote - maps to
15187 + * intLocal bit in vlynq control register */
15188 + VLYNQ_LOCAL_INT_CONFIG intLocal;
15189 +
15190 + /* remote interrupts handled by vlynq isr or host system
15191 + * interrupt controller - maps to the int2Cfg in vlynq
15192 + * control register */
15193 + VLYNQ_REMOTE_INT_CONFIG intRemote;
15194 +
15195 + /* bit in pending/set register used for module interrupts*/
15196 + unsigned int map_vector;
15197 +
15198 + /* used only if remote interrupts are to be handled by system ISR*/
15199 + unsigned int intr_ptr;
15200 +
15201 +}VLYNQ_INTERRUPT_CNTRL;
15202 +
15203 +
15204 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
15205 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
15206 + * table to identify the ISR to be invoked
15207 + */
15208 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
15209 +{
15210 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
15211 + void *arg1 ; /* Arg 1 for the ISR */
15212 + void *arg2 ; /* Arg 2 for the ISR */
15213 + void *arg3 ; /* Arg 3 for the ISR */
15214 + unsigned int isrCount; /* number of ISR invocations so far */
15215 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
15216 +}VLYNQ_INTR_CNTRL_ICB;
15217 +
15218 +/* overlay of vlynq register set */
15219 +typedef struct VLYNQ_REG_SET_t
15220 +{
15221 + unsigned int revision; /*offset : 0x00 */
15222 + unsigned int control; /* 0x04*/
15223 + unsigned int status; /* 0x08*/
15224 + unsigned int pad1; /* 0x0c*/
15225 + unsigned int intStatus; /*0x10*/
15226 + unsigned int intPending; /*0x14*/
15227 + unsigned int intPtr; /*0x18*/
15228 + unsigned int txMap; /*0x1C*/
15229 + unsigned int rxSize1; /*0x20*/
15230 + unsigned int rxOffset1; /*0x24*/
15231 + unsigned int rxSize2; /*0x28*/
15232 + unsigned int rxOffset2; /*0x2C*/
15233 + unsigned int rxSize3; /*0x30*/
15234 + unsigned int rxOffset3; /*0x34*/
15235 + unsigned int rxSize4; /*0x38*/
15236 + unsigned int rxOffset4; /*0x3C*/
15237 + unsigned int chipVersion; /*0x40*/
15238 + unsigned int pad2[8];
15239 + unsigned int ivr30; /*0x60*/
15240 + unsigned int ivr74; /*0x64*/
15241 + unsigned int pad3[7];
15242 +}VLYNQ_REG_SET;
15243 +
15244 +
15245 +typedef struct VLYNQ_DEV_t
15246 +{
15247 + /** module index:1,2,3... used for debugging purposes */
15248 + unsigned int dev_idx;
15249 +
15250 + /*VLYNQ module base address */
15251 + unsigned int module_base;
15252 +
15253 + /* clock source selection */
15254 + VLYNQ_CLK_SOURCE clk_source;
15255 +
15256 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
15257 + unsigned int clk_div;
15258 +
15259 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
15260 + VLYNQ_DRV_STATE state;
15261 +
15262 + /* Valid VLYNQ bus width, filled by driver */
15263 + VLYNQ_BUS_WIDTH width;
15264 +
15265 + /* local memory mapping */
15266 + VLYNQ_MEMORY_MAP local_mem;
15267 +
15268 + /* remote memory mapping */
15269 + VLYNQ_MEMORY_MAP remote_mem;
15270 +
15271 + /* Local module interrupt params */
15272 + VLYNQ_INTERRUPT_CNTRL local_irq;
15273 +
15274 + /* remote module interrupt params */
15275 + VLYNQ_INTERRUPT_CNTRL remote_irq;
15276 +
15277 + /*** ICB related fields **/
15278 +
15279 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
15280 + * expansion slots for shared interrupts*/
15281 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
15282 + VLYNQ_INTR_CNTRL_ICB *freelist;
15283 +
15284 + /* table holding mapping between intVector and the bit position the interrupt
15285 + * is mapped to(mapVector)*/
15286 + char vector_map[32];
15287 +
15288 + /* user callback for vlynq events, NULL if unused */
15289 + VLYNQ_REPORT_CB report_cb;
15290 +
15291 + /* user callback for resetting/realeasing remote device */
15292 + VLYNQ_RESET_REMOTE reset_cb;
15293 +
15294 + /*** Handles provided for direct access to register set if need be
15295 + * Must be intialized to point to appropriate address during
15296 + * vlynq_init */
15297 + volatile VLYNQ_REG_SET * local;
15298 + volatile VLYNQ_REG_SET * remote;
15299 +
15300 + unsigned int intCount; /* number of interrupts generated so far */
15301 + unsigned int isrCount; /* number of ISR invocations so far */
15302 +}VLYNQ_DEV;
15303 +
15304 +
15305 +typedef struct VLYNQ_ISR_ARGS_t
15306 +{
15307 + int irq;
15308 + void * arg;
15309 + void * regset;
15310 +}VLYNQ_ISR_ARGS;
15311 +
15312 +
15313 +/****************************************
15314 + * Function Prototypes *
15315 + * API exported by generic vlynq driver *
15316 + ****************************************/
15317 +/* Initialization function */
15318 +int vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
15319 +
15320 +/* Check vlynq link */
15321 +unsigned int vlynq_link_check( VLYNQ_DEV * pdev);
15322 +
15323 +/* Set interrupt vector in local or remote device */
15324 +int vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
15325 + unsigned int int_vector,
15326 + unsigned int map_vector,
15327 + VLYNQ_DEV_TYPE dev,
15328 + VLYNQ_INTR_POLARITY pol,
15329 + VLYNQ_INTR_TYPE type);
15330 +
15331 +
15332 +int vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
15333 + unsigned int int_vector,
15334 + VLYNQ_DEV_TYPE dev,
15335 + unsigned int enable);
15336 +
15337 +unsigned int vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
15338 + unsigned int map_vector);
15339 +
15340 +int vlynq_install_isr( VLYNQ_DEV *pdev,
15341 + unsigned int map_vector,
15342 + VLYNQ_INTR_CNTRL_ISR isr,
15343 + void *arg1, void *arg2, void *arg3);
15344 +
15345 +int vlynq_uninstall_isr( VLYNQ_DEV *pdev,
15346 + unsigned int map_vector,
15347 + void *arg1, void *arg2, void *arg3);
15348 +
15349 +
15350 +void vlynq_root_isr(void *arg);
15351 +
15352 +void vlynq_delay(unsigned int clktime);
15353 +
15354 +/* The following functions, provide better granularity in setting
15355 + * interrupt parameters. (for better support of linux INT Controller)
15356 + * Note: The interrupt source is identified by "map_vector"- the bit
15357 + * position in interrupt status register*/
15358 +
15359 +int vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
15360 + VLYNQ_DEV_TYPE dev,
15361 + unsigned int int_vector,
15362 + unsigned int map_vector);
15363 +
15364 +int vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
15365 + VLYNQ_DEV_TYPE dev,
15366 + unsigned int map_vector,
15367 + VLYNQ_INTR_POLARITY pol);
15368 +
15369 +int vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
15370 + VLYNQ_DEV_TYPE dev_type,
15371 + unsigned int map_vector);
15372 +
15373 +int vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
15374 + VLYNQ_DEV_TYPE dev,
15375 + unsigned int map_vector,
15376 + VLYNQ_INTR_TYPE type);
15377 +
15378 +int vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
15379 + VLYNQ_DEV_TYPE dev_type,
15380 + unsigned int map_vector);
15381 +
15382 +int vlynq_interrupt_enable(VLYNQ_DEV* pdev,
15383 + VLYNQ_DEV_TYPE dev,
15384 + unsigned int map_vector);
15385 +
15386 +int vlynq_interrupt_disable(VLYNQ_DEV * pdev,
15387 + VLYNQ_DEV_TYPE dev,
15388 + unsigned int map_vector);
15389 +
15390 +
15391 +
15392 +
15393 +
15394 +#endif /* _VLYNQ_HAL_H_ */
15395 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal.h linux.dev/include/asm-mips/ar7/vlynq_hal.h
15396 --- linux.old/include/asm-mips/ar7/vlynq_hal.h 1970-01-01 01:00:00.000000000 +0100
15397 +++ linux.dev/include/asm-mips/ar7/vlynq_hal.h 2005-10-21 17:02:25.568327000 +0200
15398 @@ -0,0 +1,606 @@
15399 +/***************************************************************************
15400 +**+----------------------------------------------------------------------+**
15401 +**| **** |**
15402 +**| **** |**
15403 +**| ******o*** |**
15404 +**| ********_///_**** |**
15405 +**| ***** /_//_/ **** |**
15406 +**| ** ** (__/ **** |**
15407 +**| ********* |**
15408 +**| **** |**
15409 +**| *** |**
15410 +**| |**
15411 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
15412 +**| ALL RIGHTS RESERVED |**
15413 +**| |**
15414 +**| Permission is hereby granted to licensees of Texas Instruments |**
15415 +**| Incorporated (TI) products to use this computer program for the sole |**
15416 +**| purpose of implementing a licensee product based on TI products. |**
15417 +**| No other rights to reproduce, use, or disseminate this computer |**
15418 +**| program, whether in part or in whole, are granted. |**
15419 +**| |**
15420 +**| TI makes no representation or warranties with respect to the |**
15421 +**| performance of this computer program, and specifically disclaims |**
15422 +**| any responsibility for any damages, special or consequential, |**
15423 +**| connected with the use of this program. |**
15424 +**| |**
15425 +**+----------------------------------------------------------------------+**
15426 +***************************************************************************/
15427 +
15428 +/*********************************************************************************
15429 + * ------------------------------------------------------------------------------
15430 + * Module : vlynq_hal.h
15431 + * Description :
15432 + * This header file provides the set of functions exported by the
15433 + * VLYNQ HAL. This file is included from the SOC specific VLYNQ driver wrapper.
15434 + * ------------------------------------------------------------------------------
15435 + *********************************************************************************/
15436 +
15437 +#ifndef _VLYNQ_HAL_H_
15438 +#define _VLYNQ_HAL_H_
15439 +
15440 +#include <asm/ar7/avalanche_types.h>
15441 +#include <asm/ar7/vlynq_hal_params.h>
15442 +
15443 +#ifndef PRIVATE
15444 +#define PRIVATE static
15445 +#endif
15446 +
15447 +#ifndef GLOBAL
15448 +#define GLOBAL
15449 +#endif
15450 +
15451 +/* Enable/Disable debug feature */
15452 +#undef VLYNQ_DEBUG
15453 +
15454 +#ifdef VLYNQ_DEBUG /* This needs to be OS abstracted - for testing use vxworks/linux calls */
15455 +#define debugPrint(format,args...)
15456 +#else
15457 +#define debugPrint(format,args...)
15458 +#endif
15459 +
15460 +/* Error defines */
15461 +#define VLYNQ_SUCCESS 0
15462 +
15463 +#define VLYNQ_ERRCODE_BASE 0 /* Chosen by system */
15464 +#define VLYNQ_INVALID_ARG -(VLYNQ_ERRCODE_BASE+1)
15465 +#define VLYNQ_INVALID_DRV_STATE -(VLYNQ_ERRCODE_BASE+2)
15466 +#define VLYNQ_INT_CONFIG_ERR -(VLYNQ_ERRCODE_BASE+3)
15467 +#define VLYNQ_LINK_DOWN -(VLYNQ_ERRCODE_BASE+4)
15468 +#define VLYNQ_MEMALLOC_FAIL -(VLYNQ_ERRCODE_BASE+5)
15469 +#define VLYNQ_ISR_NON_EXISTENT -(VLYNQ_ERRCODE_BASE+6)
15470 +#define VLYNQ_INTVEC_MAP_NOT_FOUND -(VLYNQ_ERRCODE_BASE+7)
15471 +
15472 +/* Vlynq Defines and Macros */
15473 +
15474 +#define VLYNQ_NUM_INT_BITS 32 /* 32 bit interrupt staus register */
15475 +
15476 +/* Base address of module */
15477 +#define VLYNQ_BASE (pdev->module_base)
15478 +
15479 +#define VLYNQ_REMOTE_REGS_OFFSET 0x0080
15480 +
15481 +#define VLYNQ_REV_OFFSET 0x0000
15482 +#define VLYNQ_CTRL_OFFSET 0x0004
15483 +#define VLYNQ_STATUS_OFFSET 0x0008
15484 +#define VLYNQ_INT_STAT_OFFSET 0x0010
15485 +#define VLYNQ_INT_PEND_OFFSET 0x0014
15486 +#define VLYNQ_INT_PTR_OFFSET 0x0018
15487 +#define VLYNQ_TXMAP_OFFSET 0x001c
15488 +
15489 +#define VLYNQ_RX0MAP_SIZE_REG_OFFSET 0x0020
15490 +#define VLYNQ_RX0MAP_OFFSET_REG_OFFSET 0x0024
15491 +
15492 +#define VLYNQ_CHIP_VER_OFFSET 0x0040
15493 +#define VLYNQ_IVR_REGS_OFFSET 0x0060
15494 +
15495 +#define VLYNQ_INT_PENDING_REG_PTR 0x14
15496 +#define VLYNQ_R_INT_PENDING_REG_PTR VLYNQ_REMOTE_REGS_OFFSET + 0x14
15497 +
15498 +#define VLYNQ_REV_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_REV_OFFSET))
15499 +#define VLYNQ_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CTRL_OFFSET))
15500 +#define VLYNQ_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_STATUS_OFFSET))
15501 +#define VLYNQ_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_STAT_OFFSET))
15502 +#define VLYNQ_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PEND_OFFSET))
15503 +#define VLYNQ_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_INT_PTR_OFFSET))
15504 +#define VLYNQ_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_TXMAP_OFFSET))
15505 +
15506 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
15507 +#define VLYNQ_RXMAP_SIZE_REG(map) \
15508 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_SIZE_REG_OFFSET+( (map-1)<<3)))
15509 +
15510 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
15511 +#define VLYNQ_RXMAP_OFFSET_REG(map) \
15512 + *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_RX0MAP_OFFSET_REG_OFFSET+( (map-1)<<3)))
15513 +
15514 +#define VLYNQ_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE+VLYNQ_CHIP_VER_OFFSET))
15515 +
15516 +/* 0 =< ivr <= 31; currently ivr < VLYNQ_IVR_MAXIVR=8) */
15517 +#define VLYNQ_IVR_OFFSET(ivr) \
15518 + (VLYNQ_BASE + VLYNQ_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3) )
15519 +
15520 +#define VLYNQ_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(0)) )
15521 +#define VLYNQ_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_IVR_OFFSET(4)) )
15522 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
15523 +
15524 +#define VLYNQ_IVR_INTEN(ivr) (((UINT32)(0x80)) << ((((unsigned)(ivr)) % 4) * 8))
15525 +#define VLYNQ_IVR_INTTYPE(ivr) (((UINT32)(0x40)) << ((((unsigned)(ivr)) % 4) * 8))
15526 +#define VLYNQ_IVR_INTPOL(ivr) (((UINT32)(0x20)) << ((((unsigned)(ivr)) % 4) * 8))
15527 +#define VLYNQ_IVR_INTVEC(ivr) (((UINT32)(0x1F)) << ((((unsigned)(ivr)) % 4) * 8))
15528 +#define VLYNQ_IVR_INTALL(ivr) (((UINT32)(0xFF)) << ((((unsigned)(ivr)) % 4) * 8))
15529 +
15530 +
15531 +
15532 +/*********************************
15533 + * Remote VLYNQ register set *
15534 + *********************************/
15535 +
15536 +#define VLYNQ_R_REV_OFFSET 0x0080
15537 +#define VLYNQ_R_CTRL_OFFSET 0x0084
15538 +#define VLYNQ_R_STATUS_OFFSET 0x0088
15539 +#define VLYNQ_R_INT_STAT_OFFSET 0x0090
15540 +#define VLYNQ_R_INT_PEND_OFFSET 0x0094
15541 +#define VLYNQ_R_INT_PTR_OFFSET 0x0098
15542 +#define VLYNQ_R_TXMAP_OFFSET 0x009c
15543 +
15544 +#define VLYNQ_R_RX0MAP_SIZE_REG_OFFSET 0x00A0
15545 +#define VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET 0x00A4
15546 +
15547 +#define VLYNQ_R_CHIP_VER_OFFSET 0x00C0
15548 +#define VLYNQ_R_IVR_REGS_OFFSET 0x00E0
15549 +
15550 +#define VLYNQ_R_REV_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_REV_OFFSET))
15551 +#define VLYNQ_R_CTRL_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CTRL_OFFSET))
15552 +#define VLYNQ_R_STATUS_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_STATUS_OFFSET))
15553 +#define VLYNQ_R_INT_STAT_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_STAT_OFFSET))
15554 +#define VLYNQ_R_INT_PEND_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PEND_OFFSET))
15555 +#define VLYNQ_R_INT_PTR_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_INT_PTR_OFFSET))
15556 +#define VLYNQ_R_TXMAP_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_TXMAP_OFFSET))
15557 +
15558 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
15559 +#define VLYNQ_R_RXMAP_SIZE_REG(map) \
15560 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_SIZE_REG_OFFSET + ((map-1)<<3)))
15561 +
15562 +/** map takes on values between 1 to VLYNQ_MAX_MEMORY_REGIONS **/
15563 +#define VLYNQ_R_RXMAP_OFFSET_REG(map) \
15564 + *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_RX0MAP_OFFSET_REG_OFFSET + ((map-1)<<3)))
15565 +
15566 +#define VLYNQ_R_CHIP_VER_REG *((volatile UINT32 *)(VLYNQ_BASE + VLYNQ_R_CHIP_VER_OFFSET)
15567 +
15568 +#define VLYNQ_R_IVR_OFFSET(ivr) \
15569 + (VLYNQ_BASE + VLYNQ_R_IVR_REGS_OFFSET +((((unsigned)(ivr)) & 31) & ~3))
15570 +
15571 +
15572 +/*** Can be extended for 11TO08...31TO28 when all 31 are supported**/
15573 +#define VLYNQ_R_IVR_03TO00_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(0)) )
15574 +#define VLYNQ_R_IVR_07TO04_REG *((volatile UINT32*) (VLYNQ_R_IVR_OFFSET(4)) )
15575 +
15576 +
15577 +/****End of remote register set definition******/
15578 +
15579 +
15580 +/*** Masks for individual register fields ***/
15581 +
15582 +#define VLYNQ_MODULE_ID_MASK 0xffff0000
15583 +#define VLYNQ_MAJOR_REV_MASK 0x0000ff00
15584 +#define VLYNQ_MINOR_REV_MASK 0x000000ff
15585 +
15586 +
15587 +#define VLYNQ_CTL_ILOOP_MASK 0x00000002
15588 +#define VLYNQ_CTL_INT2CFG_MASK 0x00000080
15589 +#define VLYNQ_CTL_INTVEC_MASK 0x00001f00
15590 +#define VLYNQ_CTL_INTEN_MASK 0x00002000
15591 +#define VLYNQ_CTL_INTLOCAL_MASK 0x00004000
15592 +#define VLYNQ_CTL_CLKDIR_MASK 0x00008000
15593 +#define VLYNQ_CTL_CLKDIV_MASK 0x00070000
15594 +#define VLYNQ_CTL_MODE_MASK 0x00e00000
15595 +
15596 +
15597 +#define VLYNQ_STS_LINK_MASK 0x00000001 /* Link is active */
15598 +#define VLYNQ_STS_MPEND_MASK 0x00000002 /* Pending master requests */
15599 +#define VLYNQ_STS_SPEND_MASK 0x00000004 /* Pending slave requests */
15600 +#define VLYNQ_STS_NFEMPTY0_MASK 0x00000008 /* Master data FIFO not empty */
15601 +#define VLYNQ_STS_NFEMPTY1_MASK 0x00000010 /* Master command FIFO not empty */
15602 +#define VLYNQ_STS_NFEMPTY2_MASK 0x00000020 /* Slave data FIFO not empty */
15603 +#define VLYNQ_STS_NFEMPTY3_MASK 0x00000040 /* Slave command FIFO not empty */
15604 +#define VLYNQ_STS_LERROR_MASK 0x00000080 /* Local error, w/c */
15605 +#define VLYNQ_STS_RERROR_MASK 0x00000100 /* remote error w/c */
15606 +#define VLYNQ_STS_OFLOW_MASK 0x00000200
15607 +#define VLYNQ_STS_IFLOW_MASK 0x00000400
15608 +#define VLYNQ_STS_MODESUP_MASK 0x00E00000 /* Highest mode supported */
15609 +#define VLYNQ_STS_SWIDTH_MASK 0x07000000 /* Used for reading the width of VLYNQ bus */
15610 +#define VLYNQ_STS_DEBUG_MASK 0xE0000000
15611 +
15612 +#define VLYNQ_CTL_INTVEC_SHIFT 0x08
15613 +#define VLYNQ_CTL_INTEN_SHIFT 0x0D
15614 +#define VLYNQ_CTL_INT2CFG_SHIFT 0x07
15615 +#define VLYNQ_CTL_INTLOCAL_SHIFT 0x0E
15616 +
15617 +#define VLYNQ_CTL_INTFIELDS_CLEAR_MASK 0x7F80
15618 +
15619 +#define VLYNQ_CHIPVER_DEVREV_MASK 0xffff0000
15620 +#define VLYNQ_CHIPVER_DEVID_MASK 0x0000ffff
15621 +
15622 +#define VLYNQ_IVR_INTEN_MASK 0x80
15623 +#define VLYNQ_IVR_INTTYPE_MASK 0x40
15624 +#define VLYNQ_IVR_INTPOL_MASK 0x20
15625 +
15626 +
15627 +/**** Helper macros ****/
15628 +
15629 +#define VLYNQ_RESETCB(arg) \
15630 + if( pdev->reset_cb != NULL) \
15631 + { \
15632 + (pdev->reset_cb)(pdev, (arg)); \
15633 + }
15634 +
15635 +#define VLYNQ_STATUS_FLD_WIDTH(sts) (((sts) & VLYNQ_STS_SWIDTH_MASK) >> 24 )
15636 +#define VLYNQ_CTL_INTVEC(x) (((x) & 31) << 8 )
15637 +
15638 +#define VLYNQ_INRANGE(x,hi,lo) (((x) <= (hi)) && ((x) >= (lo)))
15639 +#define VLYNQ_OUTRANGE(x,hi,lo) (((x) > (hi)) || ((x) < (lo)))
15640 +
15641 +#define VLYNQ_ALIGN4(x) (x)=(x)&(~3)
15642 +
15643 +
15644 +/*************************************
15645 + * Enums *
15646 + *************************************/
15647 +
15648 +/* Initialization options define what operations are
15649 + * undertaken during vlynq module initialization */
15650 +typedef enum
15651 +{
15652 + /* Init host local memory regions.This allows
15653 + * local host access remote memory regions */
15654 + VLYNQ_INIT_LOCAL_MEM_REGIONS = 0x01,
15655 + /* Init host remote memory regions.This allows
15656 + * remote device access local memory regions */
15657 + VLYNQ_INIT_REMOTE_MEM_REGIONS =0x02,
15658 + /* Init local interrupt config*/
15659 + VLYNQ_INIT_LOCAL_INTERRUPTS =0x04,
15660 + /* Init remote interrupt config*/
15661 + VLYNQ_INIT_REMOTE_INTERRUPTS =0x08,
15662 + /* Check link during initialization*/
15663 + VLYNQ_INIT_CHECK_LINK =0x10,
15664 + /* configure clock during init */
15665 + VLYNQ_INIT_CONFIG_CLOCK =0x20,
15666 + /* Clear errors during init */
15667 + VLYNQ_INIT_CLEAR_ERRORS =0x40,
15668 + /* All options */
15669 + VLYNQ_INIT_PERFORM_ALL =0x7F
15670 +}VLYNQ_INIT_OPTIONS;
15671 +
15672 +
15673 +/* VLYNQ_DEV_TYPE identifies local or remote device */
15674 +typedef enum
15675 +{
15676 + VLYNQ_LOCAL_DVC = 0, /* vlynq local device (SOC's vlynq module) */
15677 + VLYNQ_REMOTE_DVC = 1 /* vlynq remote device (remote vlynq module) */
15678 +}VLYNQ_DEV_TYPE;
15679 +
15680 +
15681 +/* VLYNQ_CLK_SOURCE identifies the vlynq module clock source */
15682 +typedef enum
15683 +{
15684 + VLYNQ_CLK_SOURCE_NONE = 0, /* do not initialize clock generator*/
15685 + VLYNQ_CLK_SOURCE_LOCAL = 1, /* clock is generated by local machine */
15686 + VLYNQ_CLK_SOURCE_REMOTE = 2 /* clock is generated by remote machine */
15687 +}VLYNQ_CLK_SOURCE;
15688 +
15689 +
15690 +/* VLYNQ_DRV_STATE indicates the current driver state */
15691 +typedef enum
15692 +{
15693 + VLYNQ_DRV_STATE_UNINIT = 0, /* driver is uninitialized */
15694 + VLYNQ_DRV_STATE_ININIT = 1, /* VLYNQ is being initialized */
15695 + VLYNQ_DRV_STATE_RUN = 2, /* VLYNQ is running properly */
15696 + VLYNQ_DRV_STATE_HOLD = 3, /* driver stopped temporarily */
15697 + VLYNQ_DRV_STATE_ERROR = 4 /* driver stopped on unrecoverable error */
15698 +}VLYNQ_DRV_STATE;
15699 +
15700 +
15701 +/* VLYNQ_BUS_WIDTH identifies the vlynq module bus width */
15702 +typedef enum
15703 +{
15704 + VLYNQ_BUS_WIDTH_3 = 3,
15705 + VLYNQ_BUS_WIDTH_5 = 5,
15706 + VLYNQ_BUS_WIDTH_7 = 7,
15707 + VLYNQ_BUS_WIDTH_9 = 9
15708 +}VLYNQ_BUS_WIDTH;
15709 +
15710 +
15711 +/* VLYNQ_LOCAL_INT_CONFIG indicates whether the local vlynq
15712 + * interrupts are processed by the host or passed on to the
15713 + * remote device.
15714 + */
15715 +typedef enum
15716 +{
15717 + VLYNQ_INT_REMOTE = 0, /* Interrupt packets sent to remote, intlocal=0 */
15718 + VLYNQ_INT_LOCAL = 1 /* Interrupts are handled locally, intlocal=1 */
15719 +}VLYNQ_LOCAL_INT_CONFIG;
15720 +
15721 +
15722 +/* VLYNQ_REMOTE_INT_CONFIG indicates whether the remote
15723 + * interrupts are to be handled by the SOC system ISR
15724 + * or via the vlynq root ISR
15725 + */
15726 +typedef enum
15727 +{
15728 + VLYNQ_INT_ROOT_ISR = 0, /* remote ints handled via vlynq root ISR */
15729 + VLYNQ_INT_SYSTEM_ISR = 1 /* remote ints handled via system ISR */
15730 +}VLYNQ_REMOTE_INT_CONFIG;
15731 +
15732 +
15733 +/* VLYNQ_INTR_POLARITY - vlynq interrupt polarity setting */
15734 +typedef enum
15735 +{
15736 + VLYNQ_INTR_ACTIVE_HIGH = 0,
15737 + VLYNQ_INTR_ACTIVE_LOW = 1
15738 +}VLYNQ_INTR_POLARITY;
15739 +
15740 +
15741 +/* VLYNQ_INTR_TYPE - vlynq interrupt type */
15742 +typedef enum
15743 +{
15744 + VLYNQ_INTR_LEVEL = 0,
15745 + VLYNQ_INTR_PULSED = 1
15746 +}VLYNQ_INTR_TYPE;
15747 +
15748 +
15749 +/* VLYNQ_RESET_MODE - vlynq reset mode */
15750 +typedef enum
15751 +{
15752 + VLYNQ_RESET_ASSERT, /* hold device in reset state */
15753 + VLYNQ_RESET_DEASSERT, /* release device from reset state */
15754 + VLYNQ_RESET_INITFAIL, /* handle the device in case driver initialization fails */
15755 + VLYNQ_RESET_LINKESTABLISH, /* handle the device in case driver established link */
15756 + VLYNQ_RESET_INITFAIL2, /* Driver initialization failed but VLYNQ link exist. */
15757 + VLYNQ_RESET_INITOK /* Driver initialization finished OK. */
15758 +}VLYNQ_RESET_MODE;
15759 +
15760 +
15761 +
15762 +/*************************************
15763 + * Typedefs *
15764 + *************************************/
15765 +
15766 +struct VLYNQ_DEV_t; /*forward declaration*/
15767 +
15768 +/*--------Function Pointers defintions -----------*/
15769 +
15770 +/* prototype for interrupt handler definition */
15771 +typedef void (*VLYNQ_INTR_CNTRL_ISR)(void *arg1,void *arg2,void *arg3);
15772 +
15773 +typedef void
15774 +(*VLYNQ_RESET_REMOTE)(struct VLYNQ_DEV_t *pDev, VLYNQ_RESET_MODE mode);
15775 +
15776 +typedef void
15777 +(*VLYNQ_REPORT_CB)( struct VLYNQ_DEV_t *pDev, /* This VLYNQ */
15778 + VLYNQ_DEV_TYPE aSrcDvc, /* Event Cause -local/remote? */
15779 + UINT32 dwStatRegVal); /* Value of the relevant status register */
15780 +
15781 +
15782 +/*-------Structure Definitions------------*/
15783 +
15784 +typedef struct VLYNQ_MEMORY_MAP_t
15785 +{
15786 + UINT32 Txmap;
15787 + UINT32 RxOffset[VLYNQ_MAX_MEMORY_REGIONS];
15788 + UINT32 RxSize[VLYNQ_MAX_MEMORY_REGIONS];
15789 +}VLYNQ_MEMORY_MAP;
15790 +
15791 +
15792 +/**VLYNQ_INTERRUPT_CNTRL - defines the vlynq module interrupt
15793 + * settings in vlynq Control register */
15794 +typedef struct VLYNQ_INTERRUPT_CNTRL_t
15795 +{
15796 + /* vlynq interrupts handled by host or remote - maps to
15797 + * intLocal bit in vlynq control register */
15798 + VLYNQ_LOCAL_INT_CONFIG intLocal;
15799 +
15800 + /* remote interrupts handled by vlynq isr or host system
15801 + * interrupt controller - maps to the int2Cfg in vlynq
15802 + * control register */
15803 + VLYNQ_REMOTE_INT_CONFIG intRemote;
15804 +
15805 + /* bit in pending/set register used for module interrupts*/
15806 + UINT32 map_vector;
15807 +
15808 + /* used only if remote interrupts are to be handled by system ISR*/
15809 + UINT32 intr_ptr;
15810 +
15811 +}VLYNQ_INTERRUPT_CNTRL;
15812 +
15813 +
15814 +/* VLYNQ_INTR_CNTRL_ICB - defines the Interrupt control block which hold
15815 + * the interrupt dispatch table. The vlynq_root_isr() indexes into this
15816 + * table to identify the ISR to be invoked
15817 + */
15818 +typedef struct VLYNQ_INTR_CNTRL_ICB_t
15819 +{
15820 + VLYNQ_INTR_CNTRL_ISR isr; /* Clear errors during initialization */
15821 + void *arg1 ; /* Arg 1 for the ISR */
15822 + void *arg2 ; /* Arg 2 for the ISR */
15823 + void *arg3 ; /* Arg 3 for the ISR */
15824 + UINT32 isrCount; /* number of ISR invocations so far */
15825 + struct VLYNQ_INTR_CNTRL_ICB_t *next;
15826 +}VLYNQ_INTR_CNTRL_ICB;
15827 +
15828 +/* overlay of vlynq register set */
15829 +typedef struct VLYNQ_REG_SET_t
15830 +{
15831 + UINT32 revision; /*offset : 0x00 */
15832 + UINT32 control; /* 0x04*/
15833 + UINT32 status; /* 0x08*/
15834 + UINT32 pad1; /* 0x0c*/
15835 + UINT32 intStatus; /*0x10*/
15836 + UINT32 intPending; /*0x14*/
15837 + UINT32 intPtr; /*0x18*/
15838 + UINT32 txMap; /*0x1C*/
15839 + UINT32 rxSize1; /*0x20*/
15840 + UINT32 rxOffset1; /*0x24*/
15841 + UINT32 rxSize2; /*0x28*/
15842 + UINT32 rxOffset2; /*0x2C*/
15843 + UINT32 rxSize3; /*0x30*/
15844 + UINT32 rxOffset3; /*0x34*/
15845 + UINT32 rxSize4; /*0x38*/
15846 + UINT32 rxOffset4; /*0x3C*/
15847 + UINT32 chipVersion; /*0x40*/
15848 + UINT32 pad2[8];
15849 + UINT32 ivr30; /*0x60*/
15850 + UINT32 ivr74; /*0x64*/
15851 + UINT32 pad3[7];
15852 +}VLYNQ_REG_SET;
15853 +
15854 +
15855 +typedef struct VLYNQ_DEV_t
15856 +{
15857 + /** module index:1,2,3... used for debugging purposes */
15858 + UINT32 dev_idx;
15859 +
15860 + /*VLYNQ module base address */
15861 + UINT32 module_base;
15862 +
15863 + /* clock source selection */
15864 + VLYNQ_CLK_SOURCE clk_source;
15865 +
15866 + /* Clock Divider.Val=1 to 8. VLYNQ_clk = VBUSCLK/clk_div */
15867 + UINT32 clk_div;
15868 +
15869 + /* State of the VLYNQ driver, set to VLYNQ_DRV_STATE_UNINIT, when initializing */
15870 + VLYNQ_DRV_STATE state;
15871 +
15872 + /* Valid VLYNQ bus width, filled by driver */
15873 + VLYNQ_BUS_WIDTH width;
15874 +
15875 + /* local memory mapping */
15876 + VLYNQ_MEMORY_MAP local_mem;
15877 +
15878 + /* remote memory mapping */
15879 + VLYNQ_MEMORY_MAP remote_mem;
15880 +
15881 + /* Local module interrupt params */
15882 + VLYNQ_INTERRUPT_CNTRL local_irq;
15883 +
15884 + /* remote module interrupt params */
15885 + VLYNQ_INTERRUPT_CNTRL remote_irq;
15886 +
15887 + /*** ICB related fields **/
15888 +
15889 + /* Sizeof of ICB = VLYNQ_NUM_INT_BITS(for 32 bits in IntPending) +
15890 + * expansion slots for shared interrupts*/
15891 + VLYNQ_INTR_CNTRL_ICB pIntrCB[VLYNQ_NUM_INT_BITS + VLYNQ_IVR_CHAIN_SLOTS];
15892 + VLYNQ_INTR_CNTRL_ICB *freelist;
15893 +
15894 + /* table holding mapping between intVector and the bit position the interrupt
15895 + * is mapped to(mapVector)*/
15896 + INT8 vector_map[32];
15897 +
15898 + /* user callback for vlynq events, NULL if unused */
15899 + VLYNQ_REPORT_CB report_cb;
15900 +
15901 + /* user callback for resetting/realeasing remote device */
15902 + VLYNQ_RESET_REMOTE reset_cb;
15903 +
15904 + /*** Handles provided for direct access to register set if need be
15905 + * Must be intialized to point to appropriate address during
15906 + * vlynq_init */
15907 + volatile VLYNQ_REG_SET * local;
15908 + volatile VLYNQ_REG_SET * remote;
15909 +
15910 + UINT32 intCount; /* number of interrupts generated so far */
15911 + UINT32 isrCount; /* number of ISR invocations so far */
15912 +}VLYNQ_DEV;
15913 +
15914 +
15915 +typedef struct VLYNQ_ISR_ARGS_t
15916 +{
15917 + int irq;
15918 + void * arg;
15919 + void * regset;
15920 +}VLYNQ_ISR_ARGS;
15921 +
15922 +
15923 +/****************************************
15924 + * Function Prototypes *
15925 + * API exported by generic vlynq driver *
15926 + ****************************************/
15927 +/* Initialization function */
15928 +GLOBAL INT32 vlynq_init( VLYNQ_DEV *pdev, VLYNQ_INIT_OPTIONS options);
15929 +
15930 +/* Check vlynq link */
15931 +GLOBAL UINT32 vlynq_link_check( VLYNQ_DEV * pdev);
15932 +
15933 +/* Set interrupt vector in local or remote device */
15934 +GLOBAL INT32 vlynq_interrupt_vector_set( VLYNQ_DEV *pdev,
15935 + UINT32 int_vector,
15936 + UINT32 map_vector,
15937 + VLYNQ_DEV_TYPE dev,
15938 + VLYNQ_INTR_POLARITY pol,
15939 + VLYNQ_INTR_TYPE type);
15940 +
15941 +
15942 +GLOBAL INT32 vlynq_interrupt_vector_cntl( VLYNQ_DEV *pdev,
15943 + UINT32 int_vector,
15944 + VLYNQ_DEV_TYPE dev,
15945 + UINT32 enable);
15946 +
15947 +GLOBAL UINT32 vlynq_interrupt_get_count( VLYNQ_DEV *pdev,
15948 + UINT32 map_vector);
15949 +
15950 +GLOBAL INT32 vlynq_install_isr( VLYNQ_DEV *pdev,
15951 + UINT32 map_vector,
15952 + VLYNQ_INTR_CNTRL_ISR isr,
15953 + void *arg1, void *arg2, void *arg3);
15954 +
15955 +GLOBAL INT32 vlynq_uninstall_isr( VLYNQ_DEV *pdev,
15956 + UINT32 map_vector,
15957 + void *arg1, void *arg2, void *arg3);
15958 +
15959 +
15960 +GLOBAL void vlynq_root_isr(void *arg);
15961 +
15962 +GLOBAL void vlynq_delay(UINT32 clktime);
15963 +
15964 +/* The following functions, provide better granularity in setting
15965 + * interrupt parameters. (for better support of linux INT Controller)
15966 + * Note: The interrupt source is identified by "map_vector"- the bit
15967 + * position in interrupt status register*/
15968 +
15969 +GLOBAL INT32 vlynq_interrupt_vector_map(VLYNQ_DEV * pdev,
15970 + VLYNQ_DEV_TYPE dev,
15971 + UINT32 int_vector,
15972 + UINT32 map_vector);
15973 +
15974 +GLOBAL INT32 vlynq_interrupt_set_polarity(VLYNQ_DEV * pdev,
15975 + VLYNQ_DEV_TYPE dev,
15976 + UINT32 map_vector,
15977 + VLYNQ_INTR_POLARITY pol);
15978 +
15979 +GLOBAL INT32 vlynq_interrupt_get_polarity( VLYNQ_DEV *pdev ,
15980 + VLYNQ_DEV_TYPE dev_type,
15981 + UINT32 map_vector);
15982 +
15983 +GLOBAL INT32 vlynq_interrupt_set_type(VLYNQ_DEV * pdev,
15984 + VLYNQ_DEV_TYPE dev,
15985 + UINT32 map_vector,
15986 + VLYNQ_INTR_TYPE type);
15987 +
15988 +GLOBAL INT32 vlynq_interrupt_get_type( VLYNQ_DEV *pdev,
15989 + VLYNQ_DEV_TYPE dev_type,
15990 + UINT32 map_vector);
15991 +
15992 +GLOBAL INT32 vlynq_interrupt_enable(VLYNQ_DEV* pdev,
15993 + VLYNQ_DEV_TYPE dev,
15994 + UINT32 map_vector);
15995 +
15996 +GLOBAL INT32 vlynq_interrupt_disable(VLYNQ_DEV * pdev,
15997 + VLYNQ_DEV_TYPE dev,
15998 + UINT32 map_vector);
15999 +
16000 +
16001 +
16002 +
16003 +
16004 +#endif /* _VLYNQ_HAL_H_ */
16005 diff -urN linux.old/include/asm-mips/ar7/vlynq_hal_params.h linux.dev/include/asm-mips/ar7/vlynq_hal_params.h
16006 --- linux.old/include/asm-mips/ar7/vlynq_hal_params.h 1970-01-01 01:00:00.000000000 +0100
16007 +++ linux.dev/include/asm-mips/ar7/vlynq_hal_params.h 2005-10-21 17:02:25.568327000 +0200
16008 @@ -0,0 +1,50 @@
16009 +/***************************************************************************
16010 +**+----------------------------------------------------------------------+**
16011 +**| **** |**
16012 +**| **** |**
16013 +**| ******o*** |**
16014 +**| ********_///_**** |**
16015 +**| ***** /_//_/ **** |**
16016 +**| ** ** (__/ **** |**
16017 +**| ********* |**
16018 +**| **** |**
16019 +**| *** |**
16020 +**| |**
16021 +**| Copyright (c) 2003 Texas Instruments Incorporated |**
16022 +**| ALL RIGHTS RESERVED |**
16023 +**| |**
16024 +**| Permission is hereby granted to licensees of Texas Instruments |**
16025 +**| Incorporated (TI) products to use this computer program for the sole |**
16026 +**| purpose of implementing a licensee product based on TI products. |**
16027 +**| No other rights to reproduce, use, or disseminate this computer |**
16028 +**| program, whether in part or in whole, are granted. |**
16029 +**| |**
16030 +**| TI makes no representation or warranties with respect to the |**
16031 +**| performance of this computer program, and specifically disclaims |**
16032 +**| any responsibility for any damages, special or consequential, |**
16033 +**| connected with the use of this program. |**
16034 +**| |**
16035 +**+----------------------------------------------------------------------+**
16036 +***************************************************************************/
16037 +
16038 +/* This file defines Vlynq module parameters*/
16039 +
16040 +#ifndef _VLYNQ_HAL_PARAMS_H
16041 +#define _VLYNQ_HAL_PARAMS_H
16042 +
16043 + /* number of VLYNQ memory regions supported */
16044 +#define VLYNQ_MAX_MEMORY_REGIONS 0x04
16045 +
16046 + /* Max.number of external interrupt inputs supported by VLYNQ module */
16047 +#define VLYNQ_IVR_MAXIVR 0x08
16048 +
16049 +#define VLYNQ_CLK_DIV_MAX 0x08
16050 +#define VLYNQ_CLK_DIV_MIN 0x01
16051 +
16052 +
16053 +/*** the total number of entries allocated for ICB would be
16054 + * 32(for 32 bits in IntPending register) + VLYNQ_IVR_CHAIN_SLOTS*/
16055 +#define VLYNQ_IVR_CHAIN_SLOTS 10
16056 +
16057 +
16058 +#endif /* _VLYNQ_HAL_PARAMS_H */
16059 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
16060 --- linux.old/include/asm-mips/io.h 2003-08-25 13:44:43.000000000 +0200
16061 +++ linux.dev/include/asm-mips/io.h 2005-10-21 16:45:42.250071750 +0200
16062 @@ -63,8 +63,12 @@
16063 #ifdef CONFIG_64BIT_PHYS_ADDR
16064 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
16065 #else
16066 +#ifdef CONFIG_AR7
16067 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
16068 +#else
16069 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
16070 #endif
16071 +#endif
16072
16073 #define IO_SPACE_LIMIT 0xffff
16074
16075 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
16076 --- linux.old/include/asm-mips/irq.h 2003-08-25 13:44:43.000000000 +0200
16077 +++ linux.dev/include/asm-mips/irq.h 2005-10-21 16:45:42.278073500 +0200
16078 @@ -14,7 +14,12 @@
16079 #include <linux/config.h>
16080 #include <linux/linkage.h>
16081
16082 +#ifdef CONFIG_AR7
16083 +#include <asm/ar7/avalanche_intc.h>
16084 +#define NR_IRQS AVALANCHE_INT_END + 1
16085 +#else
16086 #define NR_IRQS 128 /* Largest number of ints of all machines. */
16087 +#endif
16088
16089 #ifdef CONFIG_I8259
16090 static inline int irq_cannonicalize(int irq)
16091 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
16092 --- linux.old/include/asm-mips/page.h 2004-02-18 14:36:32.000000000 +0100
16093 +++ linux.dev/include/asm-mips/page.h 2005-10-21 16:45:42.282073750 +0200
16094 @@ -129,7 +129,11 @@
16095
16096 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
16097 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
16098 +#ifdef CONFIG_AR7
16099 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
16100 +#else
16101 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
16102 +#endif
16103 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
16104
16105 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
16106 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
16107 --- linux.old/include/asm-mips/pgtable-32.h 2004-02-18 14:36:32.000000000 +0100
16108 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-10-21 16:45:42.286074000 +0200
16109 @@ -108,7 +108,18 @@
16110 * and a page entry and page directory to the page they refer to.
16111 */
16112
16113 -#ifdef CONFIG_CPU_VR41XX
16114 +#if defined(CONFIG_AR7)
16115 +#define mk_pte(page, pgprot) \
16116 +({ \
16117 + pte_t __pte; \
16118 + \
16119 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
16120 + CONFIG_AR7_MEMORY) | \
16121 + pgprot_val(pgprot); \
16122 + \
16123 + __pte; \
16124 +})
16125 +#elif defined(CONFIG_CPU_VR41XX)
16126 #define mk_pte(page, pgprot) \
16127 ({ \
16128 pte_t __pte; \
16129 @@ -130,6 +141,7 @@
16130 })
16131 #endif
16132
16133 +
16134 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
16135 {
16136 #ifdef CONFIG_CPU_VR41XX
16137 @@ -175,7 +187,10 @@
16138 set_pte(ptep, __pte(0));
16139 }
16140
16141 -#ifdef CONFIG_CPU_VR41XX
16142 +#if defined(CONFIG_AR7)
16143 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
16144 +#define pte_page(x) phys_to_page(pte_val(x))
16145 +#elif defined(CONFIG_CPU_VR41XX)
16146 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
16147 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
16148 #else
16149 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16150 --- linux.old/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
16151 +++ linux.dev/include/asm-mips/serial.h 2005-10-21 16:45:42.294074500 +0200
16152 @@ -65,6 +65,15 @@
16153
16154 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
16155
16156 +#ifdef CONFIG_AR7
16157 +#include <asm/ar7/ar7.h>
16158 +#define AR7_SERIAL_PORT_DEFNS \
16159 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
16160 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
16161 +#else
16162 +#define AR7_SERIAL_PORT_DEFNS
16163 +#endif
16164 +
16165 #ifdef CONFIG_MIPS_JAZZ
16166 #define _JAZZ_SERIAL_INIT(int, base) \
16167 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
16168 @@ -468,6 +477,7 @@
16169 #endif
16170
16171 #define SERIAL_PORT_DFNS \
16172 + AR7_SERIAL_PORT_DEFNS \
16173 ATLAS_SERIAL_PORT_DEFNS \
16174 AU1000_SERIAL_PORT_DEFNS \
16175 COBALT_SERIAL_PORT_DEFNS \
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