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name sercomm-based ar7 images (dg834/compatible) .img instead of .bin, because the...
[openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -Nur linux-2.4.32/arch/mips/bcm947xx/cfe_env.c linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c
2 --- linux-2.4.32/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/cfe_env.c 2005-12-19 01:56:35.104829500 +0100
4 @@ -0,0 +1,234 @@
5 +/*
6 + * NVRAM variable manipulation (Linux kernel half)
7 + *
8 + * Copyright 2001-2003, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + *
16 + * $Id$
17 + */
18 +
19 +#include <linux/config.h>
20 +#include <linux/init.h>
21 +#include <linux/module.h>
22 +#include <linux/kernel.h>
23 +#include <linux/string.h>
24 +#include <asm/io.h>
25 +#include <asm/uaccess.h>
26 +
27 +#include <typedefs.h>
28 +#include <osl.h>
29 +#include <bcmendian.h>
30 +#include <bcmutils.h>
31 +
32 +#define NVRAM_SIZE (0x1ff0)
33 +static char _nvdata[NVRAM_SIZE] __initdata;
34 +static char _valuestr[256] __initdata;
35 +
36 +/*
37 + * TLV types. These codes are used in the "type-length-value"
38 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
39 + *
40 + * The layout of the flash/nvram is as follows:
41 + *
42 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
43 + *
44 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
45 + * The "length" field marks the length of the data section, not
46 + * including the type and length fields.
47 + *
48 + * Environment variables are stored as follows:
49 + *
50 + * <type_env> <length> <flags> <name> = <value>
51 + *
52 + * If bit 0 (low bit) is set, the length is an 8-bit value.
53 + * If bit 0 (low bit) is clear, the length is a 16-bit value
54 + *
55 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
56 + * indicates the size of the length field.
57 + *
58 + * Flags are from the constants below:
59 + *
60 + */
61 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
62 +#define ENV_LENGTH_8BITS 0x01
63 +
64 +#define ENV_TYPE_USER 0x80
65 +
66 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
67 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
68 +
69 +/*
70 + * The actual TLV types we support
71 + */
72 +
73 +#define ENV_TLV_TYPE_END 0x00
74 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
75 +
76 +/*
77 + * Environment variable flags
78 + */
79 +
80 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
81 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
82 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
83 +
84 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
85 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
86 +
87 +
88 +/* *********************************************************************
89 + * _nvram_read(buffer,offset,length)
90 + *
91 + * Read data from the NVRAM device
92 + *
93 + * Input parameters:
94 + * buffer - destination buffer
95 + * offset - offset of data to read
96 + * length - number of bytes to read
97 + *
98 + * Return value:
99 + * number of bytes read, or <0 if error occured
100 + ********************************************************************* */
101 +static int
102 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
103 +{
104 + int i;
105 + if (offset > NVRAM_SIZE)
106 + return -1;
107 +
108 + for ( i = 0; i < length; i++) {
109 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
110 + }
111 + return length;
112 +}
113 +
114 +
115 +static char*
116 +_strnchr(const char *dest,int c,size_t cnt)
117 +{
118 + while (*dest && (cnt > 0)) {
119 + if (*dest == c) return (char *) dest;
120 + dest++;
121 + cnt--;
122 + }
123 + return NULL;
124 +}
125 +
126 +
127 +
128 +/*
129 + * Core support API: Externally visible.
130 + */
131 +
132 +/*
133 + * Get the value of an NVRAM variable
134 + * @param name name of variable to get
135 + * @return value of variable or NULL if undefined
136 + */
137 +
138 +char*
139 +cfe_env_get(unsigned char *nv_buf, char* name)
140 +{
141 + int size;
142 + unsigned char *buffer;
143 + unsigned char *ptr;
144 + unsigned char *envval;
145 + unsigned int reclen;
146 + unsigned int rectype;
147 + int offset;
148 + int flg;
149 +
150 + size = NVRAM_SIZE;
151 + buffer = &_nvdata[0];
152 +
153 + ptr = buffer;
154 + offset = 0;
155 +
156 + /* Read the record type and length */
157 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
158 + goto error;
159 + }
160 +
161 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
162 +
163 + /* Adjust pointer for TLV type */
164 + rectype = *(ptr);
165 + offset++;
166 + size--;
167 +
168 + /*
169 + * Read the length. It can be either 1 or 2 bytes
170 + * depending on the code
171 + */
172 + if (rectype & ENV_LENGTH_8BITS) {
173 + /* Read the record type and length - 8 bits */
174 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
175 + goto error;
176 + }
177 + reclen = *(ptr);
178 + size--;
179 + offset++;
180 + }
181 + else {
182 + /* Read the record type and length - 16 bits, MSB first */
183 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
184 + goto error;
185 + }
186 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
187 + size -= 2;
188 + offset += 2;
189 + }
190 +
191 + if (reclen > size)
192 + break; /* should not happen, bad NVRAM */
193 +
194 + switch (rectype) {
195 + case ENV_TLV_TYPE_ENV:
196 + /* Read the TLV data */
197 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
198 + goto error;
199 + flg = *ptr++;
200 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
201 + if (envval) {
202 + *envval++ = '\0';
203 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
204 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
205 +#if 0
206 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
207 +#endif
208 + if(!strcmp(ptr, name)){
209 + return _valuestr;
210 + }
211 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
212 + return _valuestr;
213 + }
214 + break;
215 +
216 + default:
217 + /* Unknown TLV type, skip it. */
218 + break;
219 + }
220 +
221 + /*
222 + * Advance to next TLV
223 + */
224 +
225 + size -= (int)reclen;
226 + offset += reclen;
227 +
228 + /* Read the next record type */
229 + ptr = buffer;
230 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
231 + goto error;
232 + }
233 +
234 +error:
235 + return NULL;
236 +
237 +}
238 +
239 diff -Nur linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile
240 --- linux-2.4.32/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
241 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/compressed/Makefile 2005-12-16 23:39:10.668819500 +0100
242 @@ -0,0 +1,33 @@
243 +#
244 +# Makefile for Broadcom BCM947XX boards
245 +#
246 +# Copyright 2001-2003, Broadcom Corporation
247 +# All Rights Reserved.
248 +#
249 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
250 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
251 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
252 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
253 +#
254 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
255 +#
256 +
257 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
258 +SYSTEM ?= $(TOPDIR)/vmlinux
259 +
260 +all: vmlinuz
261 +
262 +# Don't build dependencies, this may die if $(CC) isn't gcc
263 +dep:
264 +
265 +# Create a gzipped version named vmlinuz for compatibility
266 +vmlinuz: piggy
267 + gzip -c9 $< > $@
268 +
269 +piggy: $(SYSTEM)
270 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
271 +
272 +mrproper: clean
273 +
274 +clean:
275 + rm -f vmlinuz piggy
276 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S
277 --- linux-2.4.32/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
278 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/int-handler.S 2005-12-16 23:39:10.668819500 +0100
279 @@ -0,0 +1,51 @@
280 +/*
281 + * Generic interrupt handler for Broadcom MIPS boards
282 + *
283 + * Copyright 2004, Broadcom Corporation
284 + * All Rights Reserved.
285 + *
286 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
287 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
288 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
289 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
290 + *
291 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
292 + */
293 +
294 +#include <linux/config.h>
295 +
296 +#include <asm/asm.h>
297 +#include <asm/mipsregs.h>
298 +#include <asm/regdef.h>
299 +#include <asm/stackframe.h>
300 +
301 +/*
302 + * MIPS IRQ Source
303 + * -------- ------
304 + * 0 Software (ignored)
305 + * 1 Software (ignored)
306 + * 2 Combined hardware interrupt (hw0)
307 + * 3 Hardware
308 + * 4 Hardware
309 + * 5 Hardware
310 + * 6 Hardware
311 + * 7 R4k timer
312 + */
313 +
314 + .text
315 + .set noreorder
316 + .set noat
317 + .align 5
318 + NESTED(brcmIRQ, PT_SIZE, sp)
319 + SAVE_ALL
320 + CLI
321 + .set at
322 + .set noreorder
323 +
324 + jal brcm_irq_dispatch
325 + move a0, sp
326 +
327 + j ret_from_irq
328 + nop
329 +
330 + END(brcmIRQ)
331 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/irq.c linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c
332 --- linux-2.4.32/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
333 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/irq.c 2005-12-16 23:39:10.668819500 +0100
334 @@ -0,0 +1,130 @@
335 +/*
336 + * Generic interrupt control functions for Broadcom MIPS boards
337 + *
338 + * Copyright 2004, Broadcom Corporation
339 + * All Rights Reserved.
340 + *
341 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
342 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
343 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
344 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
345 + *
346 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
347 + */
348 +
349 +#include <linux/config.h>
350 +#include <linux/init.h>
351 +#include <linux/kernel.h>
352 +#include <linux/types.h>
353 +#include <linux/interrupt.h>
354 +#include <linux/irq.h>
355 +
356 +#include <asm/irq.h>
357 +#include <asm/mipsregs.h>
358 +#include <asm/gdb-stub.h>
359 +
360 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
361 +
362 +extern asmlinkage void brcmIRQ(void);
363 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
364 +
365 +void
366 +brcm_irq_dispatch(struct pt_regs *regs)
367 +{
368 + u32 cause;
369 +
370 + cause = read_c0_cause() &
371 + read_c0_status() &
372 + CAUSEF_IP;
373 +
374 +#ifdef CONFIG_KERNPROF
375 + change_c0_status(cause | 1, 1);
376 +#else
377 + clear_c0_status(cause);
378 +#endif
379 +
380 + if (cause & CAUSEF_IP7)
381 + do_IRQ(7, regs);
382 + if (cause & CAUSEF_IP2)
383 + do_IRQ(2, regs);
384 + if (cause & CAUSEF_IP3)
385 + do_IRQ(3, regs);
386 + if (cause & CAUSEF_IP4)
387 + do_IRQ(4, regs);
388 + if (cause & CAUSEF_IP5)
389 + do_IRQ(5, regs);
390 + if (cause & CAUSEF_IP6)
391 + do_IRQ(6, regs);
392 +}
393 +
394 +static void
395 +enable_brcm_irq(unsigned int irq)
396 +{
397 + if (irq < 8)
398 + set_c0_status(1 << (irq + 8));
399 + else
400 + set_c0_status(IE_IRQ0);
401 +}
402 +
403 +static void
404 +disable_brcm_irq(unsigned int irq)
405 +{
406 + if (irq < 8)
407 + clear_c0_status(1 << (irq + 8));
408 + else
409 + clear_c0_status(IE_IRQ0);
410 +}
411 +
412 +static void
413 +ack_brcm_irq(unsigned int irq)
414 +{
415 + /* Already done in brcm_irq_dispatch */
416 +}
417 +
418 +static unsigned int
419 +startup_brcm_irq(unsigned int irq)
420 +{
421 + enable_brcm_irq(irq);
422 +
423 + return 0; /* never anything pending */
424 +}
425 +
426 +static void
427 +end_brcm_irq(unsigned int irq)
428 +{
429 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
430 + enable_brcm_irq(irq);
431 +}
432 +
433 +static struct hw_interrupt_type brcm_irq_type = {
434 + typename: "MIPS",
435 + startup: startup_brcm_irq,
436 + shutdown: disable_brcm_irq,
437 + enable: enable_brcm_irq,
438 + disable: disable_brcm_irq,
439 + ack: ack_brcm_irq,
440 + end: end_brcm_irq,
441 + NULL
442 +};
443 +
444 +void __init
445 +init_IRQ(void)
446 +{
447 + int i;
448 +
449 + for (i = 0; i < NR_IRQS; i++) {
450 + irq_desc[i].status = IRQ_DISABLED;
451 + irq_desc[i].action = 0;
452 + irq_desc[i].depth = 1;
453 + irq_desc[i].handler = &brcm_irq_type;
454 + }
455 +
456 + set_except_vector(0, brcmIRQ);
457 + change_c0_status(ST0_IM, ALLINTS);
458 +
459 +#ifdef CONFIG_REMOTE_DEBUG
460 + printk("Breaking into debugger...\n");
461 + set_debug_traps();
462 + breakpoint();
463 +#endif
464 +}
465 diff -Nur linux-2.4.32/arch/mips/bcm947xx/generic/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile
466 --- linux-2.4.32/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
467 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/generic/Makefile 2005-12-16 23:39:10.668819500 +0100
468 @@ -0,0 +1,15 @@
469 +#
470 +# Makefile for the BCM947xx specific kernel interface routines
471 +# under Linux.
472 +#
473 +
474 +.S.s:
475 + $(CPP) $(AFLAGS) $< -o $*.s
476 +.S.o:
477 + $(CC) $(AFLAGS) -c $< -o $*.o
478 +
479 +O_TARGET := brcm.o
480 +
481 +obj-y := int-handler.o irq.o
482 +
483 +include $(TOPDIR)/Rules.make
484 diff -Nur linux-2.4.32/arch/mips/bcm947xx/gpio.c linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c
485 --- linux-2.4.32/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
486 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/gpio.c 2005-12-16 23:39:10.668819500 +0100
487 @@ -0,0 +1,158 @@
488 +/*
489 + * GPIO char driver
490 + *
491 + * Copyright 2005, Broadcom Corporation
492 + * All Rights Reserved.
493 + *
494 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
495 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
496 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
497 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
498 + *
499 + * $Id$
500 + */
501 +
502 +#include <linux/module.h>
503 +#include <linux/init.h>
504 +#include <linux/fs.h>
505 +#include <linux/miscdevice.h>
506 +#include <asm/uaccess.h>
507 +
508 +#include <typedefs.h>
509 +#include <bcmutils.h>
510 +#include <sbutils.h>
511 +#include <bcmdevs.h>
512 +
513 +static sb_t *gpio_sbh;
514 +static int gpio_major;
515 +static devfs_handle_t gpio_dir;
516 +static struct {
517 + char *name;
518 + devfs_handle_t handle;
519 +} gpio_file[] = {
520 + { "in", NULL },
521 + { "out", NULL },
522 + { "outen", NULL },
523 + { "control", NULL }
524 +};
525 +
526 +static int
527 +gpio_open(struct inode *inode, struct file * file)
528 +{
529 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
530 + return -ENODEV;
531 +
532 + MOD_INC_USE_COUNT;
533 + return 0;
534 +}
535 +
536 +static int
537 +gpio_release(struct inode *inode, struct file * file)
538 +{
539 + MOD_DEC_USE_COUNT;
540 + return 0;
541 +}
542 +
543 +static ssize_t
544 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
545 +{
546 + u32 val;
547 +
548 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
549 + case 0:
550 + val = sb_gpioin(gpio_sbh);
551 + break;
552 + case 1:
553 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
554 + break;
555 + case 2:
556 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
557 + break;
558 + case 3:
559 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
560 + break;
561 + default:
562 + return -ENODEV;
563 + }
564 +
565 + if (put_user(val, (u32 *) buf))
566 + return -EFAULT;
567 +
568 + return sizeof(val);
569 +}
570 +
571 +static ssize_t
572 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
573 +{
574 + u32 val;
575 +
576 + if (get_user(val, (u32 *) buf))
577 + return -EFAULT;
578 +
579 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
580 + case 0:
581 + return -EACCES;
582 + case 1:
583 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
584 + break;
585 + case 2:
586 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
587 + break;
588 + case 3:
589 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
590 + break;
591 + default:
592 + return -ENODEV;
593 + }
594 +
595 + return sizeof(val);
596 +}
597 +
598 +static struct file_operations gpio_fops = {
599 + owner: THIS_MODULE,
600 + open: gpio_open,
601 + release: gpio_release,
602 + read: gpio_read,
603 + write: gpio_write,
604 +};
605 +
606 +static int __init
607 +gpio_init(void)
608 +{
609 + int i;
610 +
611 + if (!(gpio_sbh = sb_kattach()))
612 + return -ENODEV;
613 +
614 + sb_gpiosetcore(gpio_sbh);
615 +
616 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
617 + return gpio_major;
618 +
619 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
620 +
621 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
622 + gpio_file[i].handle = devfs_register(gpio_dir,
623 + gpio_file[i].name,
624 + DEVFS_FL_DEFAULT, gpio_major, i,
625 + S_IFCHR | S_IRUGO | S_IWUGO,
626 + &gpio_fops, NULL);
627 + }
628 +
629 + return 0;
630 +}
631 +
632 +static void __exit
633 +gpio_exit(void)
634 +{
635 + int i;
636 +
637 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
638 + devfs_unregister(gpio_file[i].handle);
639 + devfs_unregister(gpio_dir);
640 + devfs_unregister_chrdev(gpio_major, "gpio");
641 + sb_detach(gpio_sbh);
642 +}
643 +
644 +module_init(gpio_init);
645 +module_exit(gpio_exit);
646 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h
647 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
648 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-16 23:39:10.672819750 +0100
649 @@ -0,0 +1,391 @@
650 +/*
651 + * Broadcom device-specific manifest constants.
652 + *
653 + * Copyright 2005, Broadcom Corporation
654 + * All Rights Reserved.
655 + *
656 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
657 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
658 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
659 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
660 + * $Id$
661 + */
662 +
663 +#ifndef _BCMDEVS_H
664 +#define _BCMDEVS_H
665 +
666 +
667 +/* Known PCI vendor Id's */
668 +#define VENDOR_EPIGRAM 0xfeda
669 +#define VENDOR_BROADCOM 0x14e4
670 +#define VENDOR_3COM 0x10b7
671 +#define VENDOR_NETGEAR 0x1385
672 +#define VENDOR_DIAMOND 0x1092
673 +#define VENDOR_DELL 0x1028
674 +#define VENDOR_HP 0x0e11
675 +#define VENDOR_APPLE 0x106b
676 +
677 +/* PCI Device Id's */
678 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
679 +#define BCM4211_DEVICE_ID 0x4211
680 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
681 +#define BCM4231_DEVICE_ID 0x4231
682 +
683 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
684 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
685 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
686 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
687 +
688 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
689 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
690 +
691 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
692 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
693 +
694 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
695 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
696 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
697 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
698 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
699 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
700 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
701 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
702 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
703 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
704 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
705 +
706 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
707 +
708 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
709 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
710 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
711 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
712 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
713 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
714 +
715 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
716 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
717 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
718 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
719 +
720 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
721 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
722 +
723 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
724 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
725 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
726 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
727 +
728 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
729 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
730 +#define BCM4306_D11G_ID2 0x4325
731 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
732 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
733 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
734 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
735 +
736 +#define BCM4309_PKG_ID 1 /* 4309 package id */
737 +
738 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
739 +#define BCM4303_PKG_ID 2 /* 4303 package id */
740 +
741 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
742 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
743 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
744 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
745 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
746 +
747 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
748 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
749 +
750 +
751 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
752 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
753 +
754 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
755 +
756 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
757 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
758 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
759 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
760 +
761 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
762 +
763 +/* Address map */
764 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
765 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
766 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
767 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
768 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
769 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
770 +
771 +/* Core register space */
772 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
773 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
774 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
775 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
776 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
777 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
778 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
779 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
780 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
781 +
782 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
783 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
784 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
785 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
786 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
787 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
788 +
789 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
790 +
791 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
792 +
793 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
794 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
795 +
796 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
797 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
798 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
799 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
800 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
801 +
802 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
803 +
804 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
805 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
806 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
807 +
808 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
809 +
810 +/* PCMCIA vendor Id's */
811 +
812 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
813 +
814 +/* SDIO vendor Id's */
815 +#define VENDOR_BROADCOM_SDIO 0x00BF
816 +
817 +
818 +/* boardflags */
819 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
820 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
821 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
822 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
823 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
824 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
825 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
826 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
827 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
828 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
829 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
830 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
831 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
832 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
833 +
834 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
835 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
836 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
837 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
838 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
839 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
840 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
841 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
842 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
843 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
844 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
845 +
846 +/* Bus types */
847 +#define SB_BUS 0 /* Silicon Backplane */
848 +#define PCI_BUS 1 /* PCI target */
849 +#define PCMCIA_BUS 2 /* PCMCIA target */
850 +#define SDIO_BUS 3 /* SDIO target */
851 +#define JTAG_BUS 4 /* JTAG */
852 +
853 +/* Allows optimization for single-bus support */
854 +#ifdef BCMBUSTYPE
855 +#define BUSTYPE(bus) (BCMBUSTYPE)
856 +#else
857 +#define BUSTYPE(bus) (bus)
858 +#endif
859 +
860 +/* power control defines */
861 +#define PLL_DELAY 150 /* us pll on delay */
862 +#define FREF_DELAY 200 /* us fref change delay */
863 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
864 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
865 +
866 +/* Reference Board Types */
867 +
868 +#define BU4710_BOARD 0x0400
869 +#define VSIM4710_BOARD 0x0401
870 +#define QT4710_BOARD 0x0402
871 +
872 +#define BU4610_BOARD 0x0403
873 +#define VSIM4610_BOARD 0x0404
874 +
875 +#define BU4307_BOARD 0x0405
876 +#define BCM94301CB_BOARD 0x0406
877 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
878 +#define BCM94301MP_BOARD 0x0407
879 +#define BCM94307MP_BOARD 0x0408
880 +#define BCMAP4307_BOARD 0x0409
881 +
882 +#define BU4309_BOARD 0x040a
883 +#define BCM94309CB_BOARD 0x040b
884 +#define BCM94309MP_BOARD 0x040c
885 +#define BCM4309AP_BOARD 0x040d
886 +
887 +#define BCM94302MP_BOARD 0x040e
888 +
889 +#define VSIM4310_BOARD 0x040f
890 +#define BU4711_BOARD 0x0410
891 +#define BCM94310U_BOARD 0x0411
892 +#define BCM94310AP_BOARD 0x0412
893 +#define BCM94310MP_BOARD 0x0414
894 +
895 +#define BU4306_BOARD 0x0416
896 +#define BCM94306CB_BOARD 0x0417
897 +#define BCM94306MP_BOARD 0x0418
898 +
899 +#define BCM94710D_BOARD 0x041a
900 +#define BCM94710R1_BOARD 0x041b
901 +#define BCM94710R4_BOARD 0x041c
902 +#define BCM94710AP_BOARD 0x041d
903 +
904 +
905 +#define BU2050_BOARD 0x041f
906 +
907 +
908 +#define BCM94309G_BOARD 0x0421
909 +
910 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
911 +
912 +#define BU4704_BOARD 0x0423
913 +#define BU4702_BOARD 0x0424
914 +
915 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
916 +
917 +#define BU4317_BOARD 0x0426
918 +
919 +
920 +#define BCM94702MN_BOARD 0x0428
921 +
922 +/* BCM4702 1U CompactPCI Board */
923 +#define BCM94702CPCI_BOARD 0x0429
924 +
925 +/* BCM4702 with BCM95380 VLAN Router */
926 +#define BCM95380RR_BOARD 0x042a
927 +
928 +/* cb4306 with SiGe PA */
929 +#define BCM94306CBSG_BOARD 0x042b
930 +
931 +/* mp4301 with 2050 radio */
932 +#define BCM94301MPL_BOARD 0x042c
933 +
934 +/* cb4306 with SiGe PA */
935 +#define PCSG94306_BOARD 0x042d
936 +
937 +/* bu4704 with sdram */
938 +#define BU4704SD_BOARD 0x042e
939 +
940 +/* Dual 11a/11g Router */
941 +#define BCM94704AGR_BOARD 0x042f
942 +
943 +/* 11a-only minipci */
944 +#define BCM94308MP_BOARD 0x0430
945 +
946 +
947 +
948 +/* BCM94317 boards */
949 +#define BCM94317CB_BOARD 0x0440
950 +#define BCM94317MP_BOARD 0x0441
951 +#define BCM94317PCMCIA_BOARD 0x0442
952 +#define BCM94317SDIO_BOARD 0x0443
953 +
954 +#define BU4712_BOARD 0x0444
955 +#define BU4712SD_BOARD 0x045d
956 +#define BU4712L_BOARD 0x045f
957 +
958 +/* BCM4712 boards */
959 +#define BCM94712AP_BOARD 0x0445
960 +#define BCM94712P_BOARD 0x0446
961 +
962 +/* BCM4318 boards */
963 +#define BU4318_BOARD 0x0447
964 +#define CB4318_BOARD 0x0448
965 +#define MPG4318_BOARD 0x0449
966 +#define MP4318_BOARD 0x044a
967 +#define SD4318_BOARD 0x044b
968 +
969 +/* BCM63XX boards */
970 +#define BCM96338_BOARD 0x6338
971 +#define BCM96345_BOARD 0x6345
972 +#define BCM96348_BOARD 0x6348
973 +
974 +/* Another mp4306 with SiGe */
975 +#define BCM94306P_BOARD 0x044c
976 +
977 +/* CF-like 4317 modules */
978 +#define BCM94317CF_BOARD 0x044d
979 +
980 +/* mp4303 */
981 +#define BCM94303MP_BOARD 0x044e
982 +
983 +/* mpsgh4306 */
984 +#define BCM94306MPSGH_BOARD 0x044f
985 +
986 +/* BRCM 4306 w/ Front End Modules */
987 +#define BCM94306MPM 0x0450
988 +#define BCM94306MPL 0x0453
989 +
990 +/* 4712agr */
991 +#define BCM94712AGR_BOARD 0x0451
992 +
993 +/* The real CF 4317 board */
994 +#define CFI4317_BOARD 0x0452
995 +
996 +/* pcmcia 4303 */
997 +#define PC4303_BOARD 0x0454
998 +
999 +/* 5350K */
1000 +#define BCM95350K_BOARD 0x0455
1001 +
1002 +/* 5350R */
1003 +#define BCM95350R_BOARD 0x0456
1004 +
1005 +/* 4306mplna */
1006 +#define BCM94306MPLNA_BOARD 0x0457
1007 +
1008 +/* 4320 boards */
1009 +#define BU4320_BOARD 0x0458
1010 +#define BU4320S_BOARD 0x0459
1011 +#define BCM94320PH_BOARD 0x045a
1012 +
1013 +/* 4306mph */
1014 +#define BCM94306MPH_BOARD 0x045b
1015 +
1016 +/* 4306pciv */
1017 +#define BCM94306PCIV_BOARD 0x045c
1018 +
1019 +#define BU4712SD_BOARD 0x045d
1020 +
1021 +#define BCM94320PFLSH_BOARD 0x045e
1022 +
1023 +#define BU4712L_BOARD 0x045f
1024 +#define BCM94712LGR_BOARD 0x0460
1025 +#define BCM94320R_BOARD 0x0461
1026 +
1027 +#define BU5352_BOARD 0x0462
1028 +
1029 +#define BCM94318MPGH_BOARD 0x0463
1030 +
1031 +
1032 +#define BCM95352GR_BOARD 0x0467
1033 +
1034 +/* bcm95351agr */
1035 +#define BCM95351AGR_BOARD 0x0470
1036 +
1037 +/* # of GPIO pins */
1038 +#define GPIO_NUMPINS 16
1039 +
1040 +#endif /* _BCMDEVS_H */
1041 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h
1042 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
1043 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmendian.h 2005-12-16 23:39:10.672819750 +0100
1044 @@ -0,0 +1,152 @@
1045 +/*
1046 + * local version of endian.h - byte order defines
1047 + *
1048 + * Copyright 2005, Broadcom Corporation
1049 + * All Rights Reserved.
1050 + *
1051 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1052 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1053 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1054 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1055 + *
1056 + * $Id$
1057 +*/
1058 +
1059 +#ifndef _BCMENDIAN_H_
1060 +#define _BCMENDIAN_H_
1061 +
1062 +#include <typedefs.h>
1063 +
1064 +/* Byte swap a 16 bit value */
1065 +#define BCMSWAP16(val) \
1066 + ((uint16)( \
1067 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
1068 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
1069 +
1070 +/* Byte swap a 32 bit value */
1071 +#define BCMSWAP32(val) \
1072 + ((uint32)( \
1073 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
1074 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
1075 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
1076 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1077 +
1078 +/* 2 Byte swap a 32 bit value */
1079 +#define BCMSWAP32BY16(val) \
1080 + ((uint32)( \
1081 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1082 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1083 +
1084 +
1085 +static INLINE uint16
1086 +bcmswap16(uint16 val)
1087 +{
1088 + return BCMSWAP16(val);
1089 +}
1090 +
1091 +static INLINE uint32
1092 +bcmswap32(uint32 val)
1093 +{
1094 + return BCMSWAP32(val);
1095 +}
1096 +
1097 +static INLINE uint32
1098 +bcmswap32by16(uint32 val)
1099 +{
1100 + return BCMSWAP32BY16(val);
1101 +}
1102 +
1103 +/* buf - start of buffer of shorts to swap */
1104 +/* len - byte length of buffer */
1105 +static INLINE void
1106 +bcmswap16_buf(uint16 *buf, uint len)
1107 +{
1108 + len = len/2;
1109 +
1110 + while(len--){
1111 + *buf = bcmswap16(*buf);
1112 + buf++;
1113 + }
1114 +}
1115 +
1116 +#ifndef hton16
1117 +#ifndef IL_BIGENDIAN
1118 +#define HTON16(i) BCMSWAP16(i)
1119 +#define hton16(i) bcmswap16(i)
1120 +#define hton32(i) bcmswap32(i)
1121 +#define ntoh16(i) bcmswap16(i)
1122 +#define ntoh32(i) bcmswap32(i)
1123 +#define ltoh16(i) (i)
1124 +#define ltoh32(i) (i)
1125 +#define htol16(i) (i)
1126 +#define htol32(i) (i)
1127 +#else
1128 +#define HTON16(i) (i)
1129 +#define hton16(i) (i)
1130 +#define hton32(i) (i)
1131 +#define ntoh16(i) (i)
1132 +#define ntoh32(i) (i)
1133 +#define ltoh16(i) bcmswap16(i)
1134 +#define ltoh32(i) bcmswap32(i)
1135 +#define htol16(i) bcmswap16(i)
1136 +#define htol32(i) bcmswap32(i)
1137 +#endif
1138 +#endif
1139 +
1140 +#ifndef IL_BIGENDIAN
1141 +#define ltoh16_buf(buf, i)
1142 +#define htol16_buf(buf, i)
1143 +#else
1144 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1145 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1146 +#endif
1147 +
1148 +/*
1149 +* load 16-bit value from unaligned little endian byte array.
1150 +*/
1151 +static INLINE uint16
1152 +ltoh16_ua(uint8 *bytes)
1153 +{
1154 + return (bytes[1]<<8)+bytes[0];
1155 +}
1156 +
1157 +/*
1158 +* load 32-bit value from unaligned little endian byte array.
1159 +*/
1160 +static INLINE uint32
1161 +ltoh32_ua(uint8 *bytes)
1162 +{
1163 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1164 +}
1165 +
1166 +/*
1167 +* load 16-bit value from unaligned big(network) endian byte array.
1168 +*/
1169 +static INLINE uint16
1170 +ntoh16_ua(uint8 *bytes)
1171 +{
1172 + return (bytes[0]<<8)+bytes[1];
1173 +}
1174 +
1175 +/*
1176 +* load 32-bit value from unaligned big(network) endian byte array.
1177 +*/
1178 +static INLINE uint32
1179 +ntoh32_ua(uint8 *bytes)
1180 +{
1181 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1182 +}
1183 +
1184 +#define ltoh_ua(ptr) ( \
1185 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1186 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1187 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1188 +)
1189 +
1190 +#define ntoh_ua(ptr) ( \
1191 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1192 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1193 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1194 +)
1195 +
1196 +#endif /* _BCMENDIAN_H_ */
1197 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h
1198 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1199 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-12-16 23:39:10.700821500 +0100
1200 @@ -0,0 +1,229 @@
1201 +/*
1202 + * Hardware-specific definitions for
1203 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1204 + *
1205 + * Copyright 2005, Broadcom Corporation
1206 + * All Rights Reserved.
1207 + *
1208 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1209 + * the contents of this file may not be disclosed to third parties, copied
1210 + * or duplicated in any form, in whole or in part, without the prior
1211 + * written permission of Broadcom Corporation.
1212 + * $Id$
1213 + */
1214 +
1215 +#ifndef _bcmenet_47xx_h_
1216 +#define _bcmenet_47xx_h_
1217 +
1218 +#include <bcmenetmib.h>
1219 +#include <bcmenetrxh.h>
1220 +#include <bcmenetphy.h>
1221 +
1222 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1223 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1224 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1225 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1226 +
1227 +/* power management event wakeup pattern constants */
1228 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1229 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1230 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1231 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1232 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1233 +
1234 +/* cpp contortions to concatenate w/arg prescan */
1235 +#ifndef PAD
1236 +#define _PADLINE(line) pad ## line
1237 +#define _XSTR(line) _PADLINE(line)
1238 +#define PAD _XSTR(__LINE__)
1239 +#endif /* PAD */
1240 +
1241 +/*
1242 + * Host Interface Registers
1243 + */
1244 +typedef volatile struct _bcmenettregs {
1245 + /* Device and Power Control */
1246 + uint32 devcontrol;
1247 + uint32 PAD[2];
1248 + uint32 biststatus;
1249 + uint32 wakeuplength;
1250 + uint32 PAD[3];
1251 +
1252 + /* Interrupt Control */
1253 + uint32 intstatus;
1254 + uint32 intmask;
1255 + uint32 gptimer;
1256 + uint32 PAD[23];
1257 +
1258 + /* Ethernet MAC Address Filtering Control */
1259 + uint32 PAD[2];
1260 + uint32 enetftaddr;
1261 + uint32 enetftdata;
1262 + uint32 PAD[2];
1263 +
1264 + /* Ethernet MAC Control */
1265 + uint32 emactxmaxburstlen;
1266 + uint32 emacrxmaxburstlen;
1267 + uint32 emaccontrol;
1268 + uint32 emacflowcontrol;
1269 +
1270 + uint32 PAD[20];
1271 +
1272 + /* DMA Lazy Interrupt Control */
1273 + uint32 intrecvlazy;
1274 + uint32 PAD[63];
1275 +
1276 + /* DMA engine */
1277 + dma32regp_t dmaregs;
1278 + dma32diag_t dmafifo;
1279 + uint32 PAD[116];
1280 +
1281 + /* EMAC Registers */
1282 + uint32 rxconfig;
1283 + uint32 rxmaxlength;
1284 + uint32 txmaxlength;
1285 + uint32 PAD;
1286 + uint32 mdiocontrol;
1287 + uint32 mdiodata;
1288 + uint32 emacintmask;
1289 + uint32 emacintstatus;
1290 + uint32 camdatalo;
1291 + uint32 camdatahi;
1292 + uint32 camcontrol;
1293 + uint32 enetcontrol;
1294 + uint32 txcontrol;
1295 + uint32 txwatermark;
1296 + uint32 mibcontrol;
1297 + uint32 PAD[49];
1298 +
1299 + /* EMAC MIB counters */
1300 + bcmenetmib_t mib;
1301 +
1302 + uint32 PAD[585];
1303 +
1304 + /* Sonics SiliconBackplane config registers */
1305 + sbconfig_t sbconfig;
1306 +} bcmenetregs_t;
1307 +
1308 +/* device control */
1309 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1310 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1311 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1312 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1313 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1314 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1315 +#define DC_PA_SHIFT 18
1316 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1317 +#define DC_FS_SHIFT 23
1318 +#define DC_FS_4K 0 /* 4Kbytes */
1319 +#define DC_FS_512 1 /* 512bytes */
1320 +
1321 +/* wakeup length */
1322 +#define WL_P0_MASK 0x7f /* pattern 0 */
1323 +#define WL_D0 ((uint32)1 << 7)
1324 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1325 +#define WL_P1_SHIFT 8
1326 +#define WL_D1 ((uint32)1 << 15)
1327 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1328 +#define WL_P2_SHIFT 16
1329 +#define WL_D2 ((uint32)1 << 23)
1330 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1331 +#define WL_P3_SHIFT 24
1332 +#define WL_D3 ((uint32)1 << 31)
1333 +
1334 +/* intstatus and intmask */
1335 +#define I_PME ((uint32)1 << 6) /* power management event */
1336 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1337 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1338 +#define I_PD ((uint32)1 << 11) /* data error */
1339 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1340 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1341 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1342 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1343 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1344 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1345 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1346 +#define I_MW ((uint32)1 << 27) /* mii write */
1347 +#define I_MR ((uint32)1 << 28) /* mii read */
1348 +
1349 +/* emaccontrol */
1350 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1351 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1352 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1353 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1354 +#define EMC_LC_SHIFT 5
1355 +
1356 +/* emacflowcontrol */
1357 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1358 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1359 +
1360 +/* interrupt receive lazy */
1361 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1362 +#define IRL_FC_MASK 0xff000000 /* frame count */
1363 +#define IRL_FC_SHIFT 24 /* frame count */
1364 +
1365 +/* emac receive config */
1366 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1367 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1368 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1369 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1370 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1371 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1372 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1373 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1374 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1375 +
1376 +/* emac mdio control */
1377 +#define MC_MF_MASK 0x7f /* mdc frequency */
1378 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1379 +
1380 +/* emac mdio data */
1381 +#define MD_DATA_MASK 0xffff /* r/w data */
1382 +#define MD_TA_MASK 0x30000 /* turnaround value */
1383 +#define MD_TA_SHIFT 16
1384 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1385 +#define MD_RA_MASK 0x7c0000 /* register address */
1386 +#define MD_RA_SHIFT 18
1387 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1388 +#define MD_PMD_SHIFT 23
1389 +#define MD_OP_MASK 0x30000000 /* opcode */
1390 +#define MD_OP_SHIFT 28
1391 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1392 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1393 +#define MD_SB_MASK 0xc0000000 /* start bits */
1394 +#define MD_SB_SHIFT 30
1395 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1396 +
1397 +/* emac intstatus and intmask */
1398 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1399 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1400 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1401 +
1402 +/* emac cam data high */
1403 +#define CD_V ((uint32)1 << 16) /* valid bit */
1404 +
1405 +/* emac cam control */
1406 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1407 +#define CC_MS ((uint32)1 << 1) /* mask select */
1408 +#define CC_RD ((uint32)1 << 2) /* read */
1409 +#define CC_WR ((uint32)1 << 3) /* write */
1410 +#define CC_INDEX_MASK 0x3f0000 /* index */
1411 +#define CC_INDEX_SHIFT 16
1412 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1413 +
1414 +/* emac ethernet control */
1415 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1416 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1417 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1418 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1419 +
1420 +/* emac transmit control */
1421 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1422 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1423 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1424 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1425 +
1426 +/* emac mib control */
1427 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1428 +
1429 +#endif /* _bcmenet_47xx_h_ */
1430 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h
1431 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1432 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetmib.h 2005-12-16 23:39:10.700821500 +0100
1433 @@ -0,0 +1,81 @@
1434 +/*
1435 + * Hardware-specific MIB definition for
1436 + * Broadcom Home Networking Division
1437 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1438 + *
1439 + * Copyright 2005, Broadcom Corporation
1440 + * All Rights Reserved.
1441 + *
1442 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1443 + * the contents of this file may not be disclosed to third parties, copied
1444 + * or duplicated in any form, in whole or in part, without the prior
1445 + * written permission of Broadcom Corporation.
1446 + * $Id$
1447 + */
1448 +
1449 +#ifndef _bcmenetmib_h_
1450 +#define _bcmenetmib_h_
1451 +
1452 +/* cpp contortions to concatenate w/arg prescan */
1453 +#ifndef PAD
1454 +#define _PADLINE(line) pad ## line
1455 +#define _XSTR(line) _PADLINE(line)
1456 +#define PAD _XSTR(__LINE__)
1457 +#endif /* PAD */
1458 +
1459 +/*
1460 + * EMAC MIB Registers
1461 + */
1462 +typedef volatile struct {
1463 + uint32 tx_good_octets;
1464 + uint32 tx_good_pkts;
1465 + uint32 tx_octets;
1466 + uint32 tx_pkts;
1467 + uint32 tx_broadcast_pkts;
1468 + uint32 tx_multicast_pkts;
1469 + uint32 tx_len_64;
1470 + uint32 tx_len_65_to_127;
1471 + uint32 tx_len_128_to_255;
1472 + uint32 tx_len_256_to_511;
1473 + uint32 tx_len_512_to_1023;
1474 + uint32 tx_len_1024_to_max;
1475 + uint32 tx_jabber_pkts;
1476 + uint32 tx_oversize_pkts;
1477 + uint32 tx_fragment_pkts;
1478 + uint32 tx_underruns;
1479 + uint32 tx_total_cols;
1480 + uint32 tx_single_cols;
1481 + uint32 tx_multiple_cols;
1482 + uint32 tx_excessive_cols;
1483 + uint32 tx_late_cols;
1484 + uint32 tx_defered;
1485 + uint32 tx_carrier_lost;
1486 + uint32 tx_pause_pkts;
1487 + uint32 PAD[8];
1488 +
1489 + uint32 rx_good_octets;
1490 + uint32 rx_good_pkts;
1491 + uint32 rx_octets;
1492 + uint32 rx_pkts;
1493 + uint32 rx_broadcast_pkts;
1494 + uint32 rx_multicast_pkts;
1495 + uint32 rx_len_64;
1496 + uint32 rx_len_65_to_127;
1497 + uint32 rx_len_128_to_255;
1498 + uint32 rx_len_256_to_511;
1499 + uint32 rx_len_512_to_1023;
1500 + uint32 rx_len_1024_to_max;
1501 + uint32 rx_jabber_pkts;
1502 + uint32 rx_oversize_pkts;
1503 + uint32 rx_fragment_pkts;
1504 + uint32 rx_missed_pkts;
1505 + uint32 rx_crc_align_errs;
1506 + uint32 rx_undersize;
1507 + uint32 rx_crc_errs;
1508 + uint32 rx_align_errs;
1509 + uint32 rx_symbol_errs;
1510 + uint32 rx_pause_pkts;
1511 + uint32 rx_nonpause_pkts;
1512 +} bcmenetmib_t;
1513 +
1514 +#endif /* _bcmenetmib_h_ */
1515 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h
1516 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1517 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetphy.h 2005-12-16 23:39:10.700821500 +0100
1518 @@ -0,0 +1,58 @@
1519 +/*
1520 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1521 + *
1522 + * Copyright 2005, Broadcom Corporation
1523 + * All Rights Reserved.
1524 + *
1525 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1526 + * the contents of this file may not be disclosed to third parties, copied
1527 + * or duplicated in any form, in whole or in part, without the prior
1528 + * written permission of Broadcom Corporation.
1529 + * $Id$
1530 + */
1531 +
1532 +#ifndef _bcmenetphy_h_
1533 +#define _bcmenetphy_h_
1534 +
1535 +/* phy address */
1536 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1537 +#define EPHY_MASK 0x1f
1538 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1539 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1540 +
1541 +/* just a few phy registers */
1542 +#define CTL_RESET (1 << 15) /* reset */
1543 +#define CTL_LOOP (1 << 14) /* loopback */
1544 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1545 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1546 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1547 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1548 +
1549 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1550 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1551 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1552 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1553 +
1554 +/* link partner ability register */
1555 +#define LPA_SLCT 0x001f /* same as advertise selector */
1556 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1557 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1558 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1559 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1560 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1561 +#define LPA_RESV 0x1c00 /* unused */
1562 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1563 +#define LPA_LPACK 0x4000 /* link partner acked us */
1564 +#define LPA_NPAGE 0x8000 /* next page bit */
1565 +
1566 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1567 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1568 +
1569 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1570 +#define STAT_LINK (1 << 2) /* link status */
1571 +#define STAT_JAB (1 << 1) /* jabber detected */
1572 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1573 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1574 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1575 +
1576 +#endif /* _bcmenetphy_h_ */
1577 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h
1578 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1579 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-12-16 23:39:10.700821500 +0100
1580 @@ -0,0 +1,43 @@
1581 +/*
1582 + * Hardware-specific Receive Data Header for the
1583 + * Broadcom Home Networking Division
1584 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1585 + *
1586 + * Copyright 2005, Broadcom Corporation
1587 + * All Rights Reserved.
1588 + *
1589 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1590 + * the contents of this file may not be disclosed to third parties, copied
1591 + * or duplicated in any form, in whole or in part, without the prior
1592 + * written permission of Broadcom Corporation.
1593 + * $Id$
1594 + */
1595 +
1596 +#ifndef _bcmenetrxh_h_
1597 +#define _bcmenetrxh_h_
1598 +
1599 +/*
1600 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1601 + * with every frame consisting of
1602 + * 16bits of frame length, followed by
1603 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1604 + */
1605 +typedef volatile struct {
1606 + uint16 len;
1607 + uint16 flags;
1608 + uint16 pad[12];
1609 +} bcmenetrxh_t;
1610 +
1611 +#define RXHDR_LEN 28
1612 +
1613 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1614 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1615 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1616 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1617 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1618 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1619 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1620 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1621 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1622 +
1623 +#endif /* _bcmenetrxh_h_ */
1624 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h
1625 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1626 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-16 23:39:10.700821500 +0100
1627 @@ -0,0 +1,141 @@
1628 +/*
1629 + * NVRAM variable manipulation
1630 + *
1631 + * Copyright 2005, Broadcom Corporation
1632 + * All Rights Reserved.
1633 + *
1634 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1635 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1636 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1637 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1638 + *
1639 + * $Id$
1640 + */
1641 +
1642 +#ifndef _bcmnvram_h_
1643 +#define _bcmnvram_h_
1644 +
1645 +#ifndef _LANGUAGE_ASSEMBLY
1646 +
1647 +#include <typedefs.h>
1648 +
1649 +struct nvram_header {
1650 + uint32 magic;
1651 + uint32 len;
1652 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1653 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1654 + uint32 config_ncdl; /* ncdl values for memc */
1655 +};
1656 +
1657 +struct nvram_tuple {
1658 + char *name;
1659 + char *value;
1660 + struct nvram_tuple *next;
1661 +};
1662 +
1663 +/*
1664 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1665 + * platforms.
1666 + */
1667 +extern int BCMINIT(nvram_init)(void *sbh);
1668 +
1669 +/*
1670 + * Disable NVRAM access. May be unnecessary or undefined on certain
1671 + * platforms.
1672 + */
1673 +extern void BCMINIT(nvram_exit)(void *sbh);
1674 +
1675 +/*
1676 + * Get the value of an NVRAM variable. The pointer returned may be
1677 + * invalid after a set.
1678 + * @param name name of variable to get
1679 + * @return value of variable or NULL if undefined
1680 + */
1681 +extern char * BCMINIT(nvram_get)(const char *name);
1682 +
1683 +/*
1684 + * Read the reset GPIO value from the nvram and set the GPIO
1685 + * as input
1686 + */
1687 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1688 +
1689 +/*
1690 + * Get the value of an NVRAM variable.
1691 + * @param name name of variable to get
1692 + * @return value of variable or NUL if undefined
1693 + */
1694 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1695 +
1696 +/*
1697 + * Match an NVRAM variable.
1698 + * @param name name of variable to match
1699 + * @param match value to compare against value of variable
1700 + * @return TRUE if variable is defined and its value is string equal
1701 + * to match or FALSE otherwise
1702 + */
1703 +static INLINE int
1704 +nvram_match(char *name, char *match) {
1705 + const char *value = BCMINIT(nvram_get)(name);
1706 + return (value && !strcmp(value, match));
1707 +}
1708 +
1709 +/*
1710 + * Inversely match an NVRAM variable.
1711 + * @param name name of variable to match
1712 + * @param match value to compare against value of variable
1713 + * @return TRUE if variable is defined and its value is not string
1714 + * equal to invmatch or FALSE otherwise
1715 + */
1716 +static INLINE int
1717 +nvram_invmatch(char *name, char *invmatch) {
1718 + const char *value = BCMINIT(nvram_get)(name);
1719 + return (value && strcmp(value, invmatch));
1720 +}
1721 +
1722 +/*
1723 + * Set the value of an NVRAM variable. The name and value strings are
1724 + * copied into private storage. Pointers to previously set values
1725 + * may become invalid. The new value may be immediately
1726 + * retrieved but will not be permanently stored until a commit.
1727 + * @param name name of variable to set
1728 + * @param value value of variable
1729 + * @return 0 on success and errno on failure
1730 + */
1731 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1732 +
1733 +/*
1734 + * Unset an NVRAM variable. Pointers to previously set values
1735 + * remain valid until a set.
1736 + * @param name name of variable to unset
1737 + * @return 0 on success and errno on failure
1738 + * NOTE: use nvram_commit to commit this change to flash.
1739 + */
1740 +extern int BCMINIT(nvram_unset)(const char *name);
1741 +
1742 +/*
1743 + * Commit NVRAM variables to permanent storage. All pointers to values
1744 + * may be invalid after a commit.
1745 + * NVRAM values are undefined after a commit.
1746 + * @return 0 on success and errno on failure
1747 + */
1748 +extern int BCMINIT(nvram_commit)(void);
1749 +
1750 +/*
1751 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1752 + * @param buf buffer to store variables
1753 + * @param count size of buffer in bytes
1754 + * @return 0 on success and errno on failure
1755 + */
1756 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1757 +
1758 +#endif /* _LANGUAGE_ASSEMBLY */
1759 +
1760 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1761 +#define NVRAM_VERSION 1
1762 +#define NVRAM_HEADER_SIZE 20
1763 +#define NVRAM_SPACE 0x8000
1764 +
1765 +#define NVRAM_MAX_VALUE_LEN 255
1766 +#define NVRAM_MAX_PARAM_LEN 64
1767 +
1768 +#endif /* _bcmnvram_h_ */
1769 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h
1770 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1771 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmparams.h 2005-12-16 23:39:10.700821500 +0100
1772 @@ -0,0 +1,25 @@
1773 +/*
1774 + * Misc system wide parameters.
1775 + *
1776 + * Copyright 2005, Broadcom Corporation
1777 + * All Rights Reserved.
1778 + *
1779 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1780 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1781 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1782 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1783 + * $Id$
1784 + */
1785 +
1786 +#ifndef _bcmparams_h_
1787 +#define _bcmparams_h_
1788 +
1789 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1790 +
1791 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1792 +
1793 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1794 +
1795 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1796 +
1797 +#endif
1798 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h
1799 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1800 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-16 23:39:10.704821750 +0100
1801 @@ -0,0 +1,23 @@
1802 +/*
1803 + * Misc useful routines to access NIC local SROM/OTP .
1804 + *
1805 + * Copyright 2005, Broadcom Corporation
1806 + * All Rights Reserved.
1807 + *
1808 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1809 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1810 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1811 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1812 + *
1813 + * $Id$
1814 + */
1815 +
1816 +#ifndef _bcmsrom_h_
1817 +#define _bcmsrom_h_
1818 +
1819 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1820 +
1821 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1822 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1823 +
1824 +#endif /* _bcmsrom_h_ */
1825 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h
1826 --- linux-2.4.32/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1827 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bcmutils.h 2005-12-16 23:39:10.704821750 +0100
1828 @@ -0,0 +1,313 @@
1829 +/*
1830 + * Misc useful os-independent macros and functions.
1831 + *
1832 + * Copyright 2005, Broadcom Corporation
1833 + * All Rights Reserved.
1834 + *
1835 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1836 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1837 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1838 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1839 + * $Id$
1840 + */
1841 +
1842 +#ifndef _bcmutils_h_
1843 +#define _bcmutils_h_
1844 +
1845 +/*** driver-only section ***/
1846 +#ifdef BCMDRIVER
1847 +#include <osl.h>
1848 +
1849 +#define _BCM_U 0x01 /* upper */
1850 +#define _BCM_L 0x02 /* lower */
1851 +#define _BCM_D 0x04 /* digit */
1852 +#define _BCM_C 0x08 /* cntrl */
1853 +#define _BCM_P 0x10 /* punct */
1854 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1855 +#define _BCM_X 0x40 /* hex digit */
1856 +#define _BCM_SP 0x80 /* hard space (0x20) */
1857 +
1858 +#define GPIO_PIN_NOTDEFINED 0x20
1859 +
1860 +extern unsigned char bcm_ctype[];
1861 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1862 +
1863 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1864 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1865 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1866 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1867 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1868 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1869 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1870 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1871 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1872 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1873 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1874 +
1875 +/*
1876 + * Spin at most 'us' microseconds while 'exp' is true.
1877 + * Caller should explicitly test 'exp' when this completes
1878 + * and take appropriate error action if 'exp' is still true.
1879 + */
1880 +#define SPINWAIT(exp, us) { \
1881 + uint countdown = (us) + 9; \
1882 + while ((exp) && (countdown >= 10)) {\
1883 + OSL_DELAY(10); \
1884 + countdown -= 10; \
1885 + } \
1886 +}
1887 +
1888 +/* generic osl packet queue */
1889 +struct pktq {
1890 + void *head; /* first packet to dequeue */
1891 + void *tail; /* last packet to dequeue */
1892 + uint len; /* number of queued packets */
1893 + uint maxlen; /* maximum number of queued packets */
1894 + bool priority; /* enqueue by packet priority */
1895 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1896 +};
1897 +#define DEFAULT_QLEN 128
1898 +
1899 +#define pktq_len(q) ((q)->len)
1900 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1901 +#define pktq_head(q) ((q)->head)
1902 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1903 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1904 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1905 +
1906 +/* externs */
1907 +/* packet */
1908 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1909 +extern uint pkttotlen(osl_t *osh, void *);
1910 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1911 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1912 +extern void *pktdeq(struct pktq *q);
1913 +extern void *pktdeqtail(struct pktq *q);
1914 +/* string */
1915 +extern uint bcm_atoi(char *s);
1916 +extern uchar bcm_toupper(uchar c);
1917 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1918 +extern char *bcmstrstr(char *haystack, char *needle);
1919 +extern char *bcmstrcat(char *dest, const char *src);
1920 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1921 +/* ethernet address */
1922 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1923 +extern int bcm_ether_atoe(char *p, char *ea);
1924 +/* delay */
1925 +extern void bcm_mdelay(uint ms);
1926 +/* variable access */
1927 +extern char *getvar(char *vars, char *name);
1928 +extern int getintvar(char *vars, char *name);
1929 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1930 +#define bcmlog(fmt, a1, a2)
1931 +#define bcmdumplog(buf, size) *buf = '\0'
1932 +#define bcmdumplogent(buf, idx) -1
1933 +
1934 +#endif /* #ifdef BCMDRIVER */
1935 +
1936 +/*** driver/apps-shared section ***/
1937 +
1938 +#define BCME_STRLEN 64
1939 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1940 +
1941 +
1942 +/*
1943 + * error codes could be added but the defined ones shouldn't be changed/deleted
1944 + * these error codes are exposed to the user code
1945 + * when ever a new error code is added to this list
1946 + * please update errorstring table with the related error string and
1947 + * update osl files with os specific errorcode map
1948 +*/
1949 +
1950 +#define BCME_ERROR -1 /* Error generic */
1951 +#define BCME_BADARG -2 /* Bad Argument */
1952 +#define BCME_BADOPTION -3 /* Bad option */
1953 +#define BCME_NOTUP -4 /* Not up */
1954 +#define BCME_NOTDOWN -5 /* Not down */
1955 +#define BCME_NOTAP -6 /* Not AP */
1956 +#define BCME_NOTSTA -7 /* Not STA */
1957 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1958 +#define BCME_RADIOOFF -9 /* Radio Off */
1959 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1960 +#define BCME_NOCLK -11 /* No Clock*/
1961 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1962 +#define BCME_BADBAND -13 /* BAD Band */
1963 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1964 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1965 +#define BCME_BUSY -16 /* Busy*/
1966 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1967 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1968 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1969 +#define BCME_BADCHAN -20 /* BAD Channel */
1970 +#define BCME_BADADDR -21 /* BAD Address*/
1971 +#define BCME_NORESOURCE -22 /* No resources*/
1972 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1973 +#define BCME_BADLEN -24 /* Bad Length*/
1974 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1975 +#define BCME_EPERM -26 /* Not Permitted */
1976 +#define BCME_NOMEM -27 /* No Memory */
1977 +#define BCME_ASSOCIATED -28 /* Associated */
1978 +#define BCME_RANGE -29 /* Range Error*/
1979 +#define BCME_NOTFOUND -30 /* Not found */
1980 +#define BCME_LAST BCME_NOTFOUND
1981 +
1982 +#ifndef ABS
1983 +#define ABS(a) (((a)<0)?-(a):(a))
1984 +#endif
1985 +
1986 +#ifndef MIN
1987 +#define MIN(a, b) (((a)<(b))?(a):(b))
1988 +#endif
1989 +
1990 +#ifndef MAX
1991 +#define MAX(a, b) (((a)>(b))?(a):(b))
1992 +#endif
1993 +
1994 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1995 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1996 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1997 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1998 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1999 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
2000 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
2001 +
2002 +/* bit map related macros */
2003 +#ifndef setbit
2004 +#define NBBY 8 /* 8 bits per byte */
2005 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
2006 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
2007 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
2008 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
2009 +#endif
2010 +
2011 +#define NBITS(type) (sizeof(type) * 8)
2012 +#define NBITVAL(bits) (1 << (bits))
2013 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
2014 +
2015 +/* crc defines */
2016 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
2017 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
2018 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
2019 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
2020 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
2021 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
2022 +
2023 +/* bcm_format_flags() bit description structure */
2024 +typedef struct bcm_bit_desc {
2025 + uint32 bit;
2026 + char* name;
2027 +} bcm_bit_desc_t;
2028 +
2029 +/* tag_ID/length/value_buffer tuple */
2030 +typedef struct bcm_tlv {
2031 + uint8 id;
2032 + uint8 len;
2033 + uint8 data[1];
2034 +} bcm_tlv_t;
2035 +
2036 +/* Check that bcm_tlv_t fits into the given buflen */
2037 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
2038 +
2039 +/* buffer length for ethernet address from bcm_ether_ntoa() */
2040 +#define ETHER_ADDR_STR_LEN 18
2041 +
2042 +/* unaligned load and store macros */
2043 +#ifdef IL_BIGENDIAN
2044 +static INLINE uint32
2045 +load32_ua(uint8 *a)
2046 +{
2047 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
2048 +}
2049 +
2050 +static INLINE void
2051 +store32_ua(uint8 *a, uint32 v)
2052 +{
2053 + a[0] = (v >> 24) & 0xff;
2054 + a[1] = (v >> 16) & 0xff;
2055 + a[2] = (v >> 8) & 0xff;
2056 + a[3] = v & 0xff;
2057 +}
2058 +
2059 +static INLINE uint16
2060 +load16_ua(uint8 *a)
2061 +{
2062 + return ((a[0] << 8) | a[1]);
2063 +}
2064 +
2065 +static INLINE void
2066 +store16_ua(uint8 *a, uint16 v)
2067 +{
2068 + a[0] = (v >> 8) & 0xff;
2069 + a[1] = v & 0xff;
2070 +}
2071 +
2072 +#else
2073 +
2074 +static INLINE uint32
2075 +load32_ua(uint8 *a)
2076 +{
2077 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
2078 +}
2079 +
2080 +static INLINE void
2081 +store32_ua(uint8 *a, uint32 v)
2082 +{
2083 + a[3] = (v >> 24) & 0xff;
2084 + a[2] = (v >> 16) & 0xff;
2085 + a[1] = (v >> 8) & 0xff;
2086 + a[0] = v & 0xff;
2087 +}
2088 +
2089 +static INLINE uint16
2090 +load16_ua(uint8 *a)
2091 +{
2092 + return ((a[1] << 8) | a[0]);
2093 +}
2094 +
2095 +static INLINE void
2096 +store16_ua(uint8 *a, uint16 v)
2097 +{
2098 + a[1] = (v >> 8) & 0xff;
2099 + a[0] = v & 0xff;
2100 +}
2101 +
2102 +#endif
2103 +
2104 +/* externs */
2105 +/* crc */
2106 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
2107 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
2108 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
2109 +/* format/print */
2110 +/* IE parsing */
2111 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
2112 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
2113 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
2114 +
2115 +/* bcmerror*/
2116 +extern const char *bcmerrorstr(int bcmerror);
2117 +
2118 +/* multi-bool data type: set of bools, mbool is true if any is set */
2119 +typedef uint32 mbool;
2120 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
2121 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
2122 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
2123 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
2124 +
2125 +/* power conversion */
2126 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
2127 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
2128 +
2129 +/* generic datastruct to help dump routines */
2130 +struct fielddesc {
2131 + char *nameandfmt;
2132 + uint32 offset;
2133 + uint32 len;
2134 +};
2135 +
2136 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
2137 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
2138 +
2139 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
2140 +
2141 +#endif /* _bcmutils_h_ */
2142 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h
2143 --- linux-2.4.32/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
2144 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-16 23:39:10.704821750 +0100
2145 @@ -0,0 +1,85 @@
2146 +/*
2147 + * bit manipulation utility functions
2148 + *
2149 + * Copyright 2005, Broadcom Corporation
2150 + * All Rights Reserved.
2151 + *
2152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2156 + * $Id$
2157 + */
2158 +
2159 +#ifndef _BITFUNCS_H
2160 +#define _BITFUNCS_H
2161 +
2162 +#include <typedefs.h>
2163 +
2164 +/* local prototypes */
2165 +static INLINE uint32 find_msbit(uint32 x);
2166 +
2167 +
2168 +/*
2169 + * find_msbit: returns index of most significant set bit in x, with index
2170 + * range defined as 0-31. NOTE: returns zero if input is zero.
2171 + */
2172 +
2173 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2174 +
2175 +/*
2176 + * Implementation for Pentium processors and gcc. Note that this
2177 + * instruction is actually very slow on some processors (e.g., family 5,
2178 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2179 + * implementation instead.
2180 + */
2181 +static INLINE uint32 find_msbit(uint32 x)
2182 +{
2183 + uint msbit;
2184 + __asm__("bsrl %1,%0"
2185 + :"=r" (msbit)
2186 + :"r" (x));
2187 + return msbit;
2188 +}
2189 +
2190 +#else
2191 +
2192 +/*
2193 + * Generic Implementation
2194 + */
2195 +
2196 +#define DB_POW_MASK16 0xffff0000
2197 +#define DB_POW_MASK8 0x0000ff00
2198 +#define DB_POW_MASK4 0x000000f0
2199 +#define DB_POW_MASK2 0x0000000c
2200 +#define DB_POW_MASK1 0x00000002
2201 +
2202 +static INLINE uint32 find_msbit(uint32 x)
2203 +{
2204 + uint32 temp_x = x;
2205 + uint msbit = 0;
2206 + if (temp_x & DB_POW_MASK16) {
2207 + temp_x >>= 16;
2208 + msbit = 16;
2209 + }
2210 + if (temp_x & DB_POW_MASK8) {
2211 + temp_x >>= 8;
2212 + msbit += 8;
2213 + }
2214 + if (temp_x & DB_POW_MASK4) {
2215 + temp_x >>= 4;
2216 + msbit += 4;
2217 + }
2218 + if (temp_x & DB_POW_MASK2) {
2219 + temp_x >>= 2;
2220 + msbit += 2;
2221 + }
2222 + if (temp_x & DB_POW_MASK1) {
2223 + msbit += 1;
2224 + }
2225 + return(msbit);
2226 +}
2227 +
2228 +#endif
2229 +
2230 +#endif /* _BITFUNCS_H */
2231 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h
2232 --- linux-2.4.32/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2233 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/cfe_osl.h 2005-12-16 23:39:10.704821750 +0100
2234 @@ -0,0 +1,191 @@
2235 +/*
2236 + * CFE boot loader OS Abstraction Layer.
2237 + *
2238 + * Copyright 2005, Broadcom Corporation
2239 + * All Rights Reserved.
2240 + *
2241 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2242 + * the contents of this file may not be disclosed to third parties, copied
2243 + * or duplicated in any form, in whole or in part, without the prior
2244 + * written permission of Broadcom Corporation.
2245 + *
2246 + * $Id$
2247 + */
2248 +
2249 +#ifndef _cfe_osl_h_
2250 +#define _cfe_osl_h_
2251 +
2252 +#include <lib_types.h>
2253 +#include <lib_string.h>
2254 +#include <lib_printf.h>
2255 +#include <lib_malloc.h>
2256 +#include <cpu_config.h>
2257 +#include <cfe_timer.h>
2258 +#include <cfe_iocb.h>
2259 +#include <cfe_devfuncs.h>
2260 +#include <addrspace.h>
2261 +
2262 +#include <typedefs.h>
2263 +
2264 +/* dump string */
2265 +extern int (*xprinthook)(const char *str);
2266 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2267 +
2268 +/* assert and panic */
2269 +#define ASSERT(exp) do {} while (0)
2270 +
2271 +/* PCMCIA attribute space access macros */
2272 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2273 + bzero(buf, size)
2274 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2275 + do {} while (0)
2276 +
2277 +/* PCI configuration space access macros */
2278 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2279 + (offset == 8 ? 0 : 0xffffffff)
2280 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2281 + do {} while (0)
2282 +
2283 +/* PCI device bus # and slot # */
2284 +#define OSL_PCI_BUS(osh) (0)
2285 +#define OSL_PCI_SLOT(osh) (0)
2286 +
2287 +/* register access macros */
2288 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2289 +#define rreg32(r) (*(volatile uint32*)(r))
2290 +#ifdef IL_BIGENDIAN
2291 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2292 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2293 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2294 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2295 +#else
2296 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2297 +#define rreg16(r) (*(volatile uint16*)(r))
2298 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2299 +#define rreg8(r) (*(volatile uint8*)(r))
2300 +#endif
2301 +#define R_REG(r) ({ \
2302 + __typeof(*(r)) __osl_v; \
2303 + switch (sizeof(*(r))) { \
2304 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2305 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2306 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2307 + } \
2308 + __osl_v; \
2309 +})
2310 +#define W_REG(r, v) do { \
2311 + switch (sizeof(*(r))) { \
2312 + case sizeof(uint8): wreg8((r), (v)); break; \
2313 + case sizeof(uint16): wreg16((r), (v)); break; \
2314 + case sizeof(uint32): wreg32((r), (v)); break; \
2315 + } \
2316 +} while (0)
2317 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2318 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2319 +
2320 +/* bcopy, bcmp, and bzero */
2321 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2322 +
2323 +#define osl_attach(pdev) ((osl_t*)pdev)
2324 +#define osl_detach(osh)
2325 +
2326 +/* general purpose memory allocation */
2327 +#define MALLOC(osh, size) KMALLOC((size),0)
2328 +#define MFREE(osh, addr, size) KFREE((addr))
2329 +#define MALLOCED(osh) (0)
2330 +#define MALLOC_DUMP(osh, buf, sz)
2331 +#define MALLOC_FAILED(osh) (0)
2332 +
2333 +/* uncached virtual address */
2334 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2335 +
2336 +/* host/bus architecture-specific address byte swap */
2337 +#define BUS_SWAP32(v) (v)
2338 +
2339 +/* get processor cycle count */
2340 +#define OSL_GETCYCLES(x) ((x) = 0)
2341 +
2342 +/* microsecond delay */
2343 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2344 +
2345 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2346 +
2347 +/* map/unmap physical to virtual I/O */
2348 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2349 +#define REG_UNMAP(va) do {} while (0)
2350 +
2351 +/* dereference an address that may cause a bus exception */
2352 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2353 +extern int osl_busprobe(uint32 *val, uint32 addr);
2354 +
2355 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2356 +#define DMA_CONSISTENT_ALIGN 4096
2357 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2358 + osl_dma_alloc_consistent((size), (pap))
2359 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2360 + osl_dma_free_consistent((void*)(va))
2361 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2362 +extern void osl_dma_free_consistent(void *va);
2363 +
2364 +/* map/unmap direction */
2365 +#define DMA_TX 1
2366 +#define DMA_RX 2
2367 +
2368 +/* map/unmap shared (dma-able) memory */
2369 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2370 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2371 + PHYSADDR((ulong)(va)); \
2372 +})
2373 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2374 + do {} while (0)
2375 +
2376 +/* shared (dma-able) memory access macros */
2377 +#define R_SM(r) *(r)
2378 +#define W_SM(r, v) (*(r) = (v))
2379 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2380 +
2381 +/* generic packet structure */
2382 +#define LBUFSZ 4096
2383 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2384 +struct lbuf {
2385 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2386 + struct lbuf *link; /* pointer to next lbuf if in a list */
2387 + uchar *head; /* start of buffer */
2388 + uchar *end; /* end of buffer */
2389 + uchar *data; /* start of data */
2390 + uchar *tail; /* end of data */
2391 + uint len; /* nbytes of data */
2392 + void *cookie; /* generic cookie */
2393 +};
2394 +
2395 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2396 +#define PKTBUFSZ 2048
2397 +
2398 +/* packet primitives */
2399 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2400 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2401 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2402 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2403 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2404 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2405 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2406 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2407 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2408 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2409 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2410 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2411 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2412 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2413 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2414 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2415 +#define PKTPRIO(lb) (0)
2416 +#define PKTSETPRIO(lb, x) do {} while (0)
2417 +extern struct lbuf *osl_pktget(uint len);
2418 +extern void osl_pktfree(struct lbuf *lb);
2419 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2420 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2421 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2422 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2423 +extern int osl_error(int bcmerror);
2424 +
2425 +#endif /* _cfe_osl_h_ */
2426 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h
2427 --- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2428 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h 2005-12-16 23:39:10.704821750 +0100
2429 @@ -0,0 +1,69 @@
2430 +/*
2431 + * Copyright 2005, Broadcom Corporation
2432 + * All Rights Reserved.
2433 + *
2434 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2435 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2436 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2437 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2438 + *
2439 + * $Id$
2440 + *
2441 +*/
2442 +
2443 +#ifndef _epivers_h_
2444 +#define _epivers_h_
2445 +
2446 +#ifdef linux
2447 +#include <linux/config.h>
2448 +#endif
2449 +
2450 +/* Vendor Name, ASCII, 32 chars max */
2451 +#ifdef COMPANYNAME
2452 +#define HPNA_VENDOR COMPANYNAME
2453 +#else
2454 +#define HPNA_VENDOR "Broadcom Corporation"
2455 +#endif
2456 +
2457 +/* Driver Date, ASCII, 32 chars max */
2458 +#define HPNA_DRV_BUILD_DATE __DATE__
2459 +
2460 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2461 +#define HPNA_HW_MFG_DATE "Not Specified"
2462 +
2463 +/* See documentation for Device Type values, 32 values max */
2464 +#ifndef HPNA_DEV_TYPE
2465 +
2466 +#if defined(CONFIG_BRCM_VJ)
2467 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2468 +
2469 +#elif defined(CONFIG_BCRM_93725)
2470 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2471 +
2472 +#else
2473 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2474 +
2475 +#endif
2476 +
2477 +#endif /* !HPNA_DEV_TYPE */
2478 +
2479 +
2480 +#define EPI_MAJOR_VERSION 3
2481 +
2482 +#define EPI_MINOR_VERSION 130
2483 +
2484 +#define EPI_RC_NUMBER 20
2485 +
2486 +#define EPI_INCREMENTAL_NUMBER 0
2487 +
2488 +#define EPI_BUILD_NUMBER 0
2489 +
2490 +#define EPI_VERSION 3,130,20,0
2491 +
2492 +#define EPI_VERSION_NUM 0x03821400
2493 +
2494 +/* Driver Version String, ASCII, 32 chars max */
2495 +#define EPI_VERSION_STR "3.130.20.0"
2496 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2497 +
2498 +#endif /* _epivers_h_ */
2499 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in
2500 --- linux-2.4.32/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2501 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/epivers.h.in 2005-12-16 23:39:10.704821750 +0100
2502 @@ -0,0 +1,69 @@
2503 +/*
2504 + * Copyright 2005, Broadcom Corporation
2505 + * All Rights Reserved.
2506 + *
2507 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2508 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2509 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2510 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2511 + *
2512 + * $Id$
2513 + *
2514 +*/
2515 +
2516 +#ifndef _epivers_h_
2517 +#define _epivers_h_
2518 +
2519 +#ifdef linux
2520 +#include <linux/config.h>
2521 +#endif
2522 +
2523 +/* Vendor Name, ASCII, 32 chars max */
2524 +#ifdef COMPANYNAME
2525 +#define HPNA_VENDOR COMPANYNAME
2526 +#else
2527 +#define HPNA_VENDOR "Broadcom Corporation"
2528 +#endif
2529 +
2530 +/* Driver Date, ASCII, 32 chars max */
2531 +#define HPNA_DRV_BUILD_DATE __DATE__
2532 +
2533 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2534 +#define HPNA_HW_MFG_DATE "Not Specified"
2535 +
2536 +/* See documentation for Device Type values, 32 values max */
2537 +#ifndef HPNA_DEV_TYPE
2538 +
2539 +#if defined(CONFIG_BRCM_VJ)
2540 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2541 +
2542 +#elif defined(CONFIG_BCRM_93725)
2543 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2544 +
2545 +#else
2546 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2547 +
2548 +#endif
2549 +
2550 +#endif /* !HPNA_DEV_TYPE */
2551 +
2552 +
2553 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2554 +
2555 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2556 +
2557 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2558 +
2559 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2560 +
2561 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2562 +
2563 +#define EPI_VERSION @EPI_VERSION@
2564 +
2565 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2566 +
2567 +/* Driver Version String, ASCII, 32 chars max */
2568 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2569 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2570 +
2571 +#endif /* _epivers_h_ */
2572 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h
2573 --- linux-2.4.32/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2574 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/etsockio.h 2005-12-16 23:39:10.704821750 +0100
2575 @@ -0,0 +1,59 @@
2576 +/*
2577 + * Driver-specific socket ioctls
2578 + * used by BSD, Linux, and PSOS
2579 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2580 + *
2581 + * Copyright 2005, Broadcom Corporation
2582 + * All Rights Reserved.
2583 + *
2584 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2585 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2586 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2587 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2588 + *
2589 + * $Id$
2590 + */
2591 +
2592 +#ifndef _etsockio_h_
2593 +#define _etsockio_h_
2594 +
2595 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2596 +
2597 +
2598 +#if defined(linux)
2599 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2600 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2601 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2602 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2603 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2604 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2605 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2606 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2607 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2608 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2609 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2610 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2611 +
2612 +#else /* !linux */
2613 +
2614 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2615 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2616 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2617 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2618 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2619 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2620 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2621 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2622 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2623 +
2624 +#endif
2625 +
2626 +/* arg to SIOCTXGEN */
2627 +struct txg {
2628 + uint32 num; /* number of frames to send */
2629 + uint32 delay; /* delay in microseconds between sending each */
2630 + uint32 size; /* size of ether frame to send */
2631 + uchar buf[1514]; /* starting ether frame data */
2632 +};
2633 +
2634 +#endif
2635 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flash.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h
2636 --- linux-2.4.32/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2637 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flash.h 2005-12-16 23:39:10.704821750 +0100
2638 @@ -0,0 +1,188 @@
2639 +/*
2640 + * flash.h: Common definitions for flash access.
2641 + *
2642 + * Copyright 2005, Broadcom Corporation
2643 + * All Rights Reserved.
2644 + *
2645 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2646 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2647 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2648 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2649 + *
2650 + * $Id$
2651 + */
2652 +
2653 +/* Types of flashes we know about */
2654 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2655 +
2656 +/* Commands to write/erase the flases */
2657 +typedef struct _flash_cmds{
2658 + flash_type_t type;
2659 + bool need_unlock;
2660 + uint16 pre_erase;
2661 + uint16 erase_block;
2662 + uint16 erase_chip;
2663 + uint16 write_word;
2664 + uint16 write_buf;
2665 + uint16 clear_csr;
2666 + uint16 read_csr;
2667 + uint16 read_id;
2668 + uint16 confirm;
2669 + uint16 read_array;
2670 +} flash_cmds_t;
2671 +
2672 +#define UNLOCK_CMD_WORDS 2
2673 +
2674 +typedef struct _unlock_cmd {
2675 + uint addr[UNLOCK_CMD_WORDS];
2676 + uint16 cmd[UNLOCK_CMD_WORDS];
2677 +} unlock_cmd_t;
2678 +
2679 +/* Flash descriptors */
2680 +typedef struct _flash_desc {
2681 + uint16 mfgid; /* Manufacturer Id */
2682 + uint16 devid; /* Device Id */
2683 + uint size; /* Total size in bytes */
2684 + uint width; /* Device width in bytes */
2685 + flash_type_t type; /* Device type old, S, J */
2686 + uint bsize; /* Block size */
2687 + uint nb; /* Number of blocks */
2688 + uint ff; /* First full block */
2689 + uint lf; /* Last full block */
2690 + uint nsub; /* Number of subblocks */
2691 + uint *subblocks; /* Offsets for subblocks */
2692 + char *desc; /* Description */
2693 +} flash_desc_t;
2694 +
2695 +
2696 +#ifdef DECLARE_FLASHES
2697 +flash_cmds_t sflash_cmd_t =
2698 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2699 +
2700 +flash_cmds_t flash_cmds[] = {
2701 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2702 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2703 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2704 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2705 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2706 + { 0 }
2707 +};
2708 +
2709 +unlock_cmd_t unlock_cmd_amd = {
2710 +#ifdef MIPSEB
2711 +/* addr: */ { 0x0aa8, 0x0556},
2712 +#else
2713 +/* addr: */ { 0x0aaa, 0x0554},
2714 +#endif
2715 +/* data: */ { 0xaa, 0x55}
2716 +};
2717 +
2718 +unlock_cmd_t unlock_cmd_sst = {
2719 +#ifdef MIPSEB
2720 +/* addr: */ { 0xaaa8, 0x5556},
2721 +#else
2722 +/* addr: */ { 0xaaaa, 0x5554},
2723 +#endif
2724 +/* data: */ { 0xaa, 0x55}
2725 +};
2726 +
2727 +#define AMD_CMD 0xaaa
2728 +#define SST_CMD 0xaaaa
2729 +
2730 +/* intel unlock block cmds */
2731 +#define INTEL_UNLOCK1 0x60
2732 +#define INTEL_UNLOCK2 0xD0
2733 +
2734 +/* Just eight blocks of 8KB byte each */
2735 +
2736 +uint blk8x8k[] = { 0x00000000,
2737 + 0x00002000,
2738 + 0x00004000,
2739 + 0x00006000,
2740 + 0x00008000,
2741 + 0x0000a000,
2742 + 0x0000c000,
2743 + 0x0000e000,
2744 + 0x00010000
2745 +};
2746 +
2747 +/* Funky AMD arrangement for 29xx800's */
2748 +uint amd800[] = { 0x00000000, /* 16KB */
2749 + 0x00004000, /* 32KB */
2750 + 0x0000c000, /* 8KB */
2751 + 0x0000e000, /* 8KB */
2752 + 0x00010000, /* 8KB */
2753 + 0x00012000, /* 8KB */
2754 + 0x00014000, /* 32KB */
2755 + 0x0001c000, /* 16KB */
2756 + 0x00020000
2757 +};
2758 +
2759 +/* AMD arrangement for 29xx160's */
2760 +uint amd4112[] = { 0x00000000, /* 32KB */
2761 + 0x00008000, /* 8KB */
2762 + 0x0000a000, /* 8KB */
2763 + 0x0000c000, /* 16KB */
2764 + 0x00010000
2765 +};
2766 +uint amd2114[] = { 0x00000000, /* 16KB */
2767 + 0x00004000, /* 8KB */
2768 + 0x00006000, /* 8KB */
2769 + 0x00008000, /* 32KB */
2770 + 0x00010000
2771 +};
2772 +
2773 +
2774 +flash_desc_t sflash_desc =
2775 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2776 +
2777 +flash_desc_t flashes[] = {
2778 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2779 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2780 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2781 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2782 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2783 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2784 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2785 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2786 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2787 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2788 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2789 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2790 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2791 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2792 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2793 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2794 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2795 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2796 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2797 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2798 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2799 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2800 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2801 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2802 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2803 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2804 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2805 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2806 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2807 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2808 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2809 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2810 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2811 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2812 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2813 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2814 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2815 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2816 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2817 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2818 +};
2819 +
2820 +#else
2821 +
2822 +extern flash_cmds_t flash_cmds[];
2823 +extern unlock_cmd_t unlock_cmd;
2824 +extern flash_desc_t flashes[];
2825 +
2826 +#endif
2827 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h
2828 --- linux-2.4.32/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2829 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/flashutl.h 2005-12-16 23:39:10.708822000 +0100
2830 @@ -0,0 +1,27 @@
2831 +/*
2832 + * BCM47XX FLASH driver interface
2833 + *
2834 + * Copyright 2005, Broadcom Corporation
2835 + * All Rights Reserved.
2836 + *
2837 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2838 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2839 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2840 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2841 + * $Id$
2842 + */
2843 +
2844 +#ifndef _flashutl_h_
2845 +#define _flashutl_h_
2846 +
2847 +
2848 +#ifndef _LANGUAGE_ASSEMBLY
2849 +
2850 +int sysFlashInit(char *flash_str);
2851 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2852 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2853 +void nvWrite(unsigned short *data, unsigned int len);
2854 +
2855 +#endif /* _LANGUAGE_ASSEMBLY */
2856 +
2857 +#endif /* _flashutl_h_ */
2858 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h
2859 --- linux-2.4.32/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2860 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hnddma.h 2005-12-16 23:39:10.708822000 +0100
2861 @@ -0,0 +1,71 @@
2862 +/*
2863 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2864 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2865 + *
2866 + * Copyright 2005, Broadcom Corporation
2867 + * All Rights Reserved.
2868 + *
2869 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2870 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2871 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2872 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2873 + * $Id$
2874 + */
2875 +
2876 +#ifndef _hnddma_h_
2877 +#define _hnddma_h_
2878 +
2879 +/* export structure */
2880 +typedef volatile struct {
2881 + /* rx error counters */
2882 + uint rxgiants; /* rx giant frames */
2883 + uint rxnobuf; /* rx out of dma descriptors */
2884 + /* tx error counters */
2885 + uint txnobuf; /* tx out of dma descriptors */
2886 +} hnddma_t;
2887 +
2888 +#ifndef di_t
2889 +#define di_t void
2890 +#endif
2891 +
2892 +#ifndef osl_t
2893 +#define osl_t void
2894 +#endif
2895 +
2896 +/* externs */
2897 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2898 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2899 +extern void dma_detach(di_t *di);
2900 +extern void dma_txreset(di_t *di);
2901 +extern void dma_rxreset(di_t *di);
2902 +extern void dma_txinit(di_t *di);
2903 +extern bool dma_txenabled(di_t *di);
2904 +extern void dma_rxinit(di_t *di);
2905 +extern void dma_rxenable(di_t *di);
2906 +extern bool dma_rxenabled(di_t *di);
2907 +extern void dma_txsuspend(di_t *di);
2908 +extern void dma_txresume(di_t *di);
2909 +extern bool dma_txsuspended(di_t *di);
2910 +extern bool dma_txsuspendedidle(di_t *di);
2911 +extern bool dma_txstopped(di_t *di);
2912 +extern bool dma_rxstopped(di_t *di);
2913 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2914 +extern void dma_fifoloopbackenable(di_t *di);
2915 +extern void *dma_rx(di_t *di);
2916 +extern void dma_rxfill(di_t *di);
2917 +extern void dma_txreclaim(di_t *di, bool forceall);
2918 +extern void dma_rxreclaim(di_t *di);
2919 +extern uintptr dma_getvar(di_t *di, char *name);
2920 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2921 +extern void *dma_peeknexttxp(di_t *di);
2922 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2923 +extern void dma_txblock(di_t *di);
2924 +extern void dma_txunblock(di_t *di);
2925 +extern uint dma_txactive(di_t *di);
2926 +extern void dma_txrotate(di_t *di);
2927 +
2928 +extern void dma_rxpiomode(dma32regs_t *);
2929 +extern void dma_txpioloopback(dma32regs_t *);
2930 +
2931 +
2932 +#endif /* _hnddma_h_ */
2933 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h
2934 --- linux-2.4.32/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2935 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/hndmips.h 2005-12-16 23:39:10.708822000 +0100
2936 @@ -0,0 +1,16 @@
2937 +/*
2938 + * Alternate include file for HND sbmips.h since CFE also ships with
2939 + * a sbmips.h.
2940 + *
2941 + * Copyright 2005, Broadcom Corporation
2942 + * All Rights Reserved.
2943 + *
2944 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2945 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2946 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2947 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2948 + *
2949 + * $Id$
2950 + */
2951 +
2952 +#include "sbmips.h"
2953 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h
2954 --- linux-2.4.32/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2955 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linux_osl.h 2005-12-16 23:39:10.708822000 +0100
2956 @@ -0,0 +1,371 @@
2957 +/*
2958 + * Linux OS Independent Layer
2959 + *
2960 + * Copyright 2005, Broadcom Corporation
2961 + * All Rights Reserved.
2962 + *
2963 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2964 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2965 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2966 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2967 + *
2968 + * $Id$
2969 + */
2970 +
2971 +#ifndef _linux_osl_h_
2972 +#define _linux_osl_h_
2973 +
2974 +#include <typedefs.h>
2975 +
2976 +/* use current 2.4.x calling conventions */
2977 +#include <linuxver.h>
2978 +
2979 +/* assert and panic */
2980 +#ifdef __GNUC__
2981 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2982 +#if GCC_VERSION > 30100
2983 +#define ASSERT(exp) do {} while (0)
2984 +#else
2985 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2986 +#define ASSERT(exp)
2987 +#endif
2988 +#endif
2989 +
2990 +/* microsecond delay */
2991 +#define OSL_DELAY(usec) osl_delay(usec)
2992 +extern void osl_delay(uint usec);
2993 +
2994 +/* PCMCIA attribute space access macros */
2995 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2996 +struct pcmcia_dev {
2997 + dev_link_t link; /* PCMCIA device pointer */
2998 + dev_node_t node; /* PCMCIA node structure */
2999 + void *base; /* Mapped attribute memory window */
3000 + size_t size; /* Size of window */
3001 + void *drv; /* Driver data */
3002 +};
3003 +#endif
3004 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3005 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
3006 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3007 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
3008 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
3009 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
3010 +
3011 +/* PCI configuration space access macros */
3012 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
3013 + osl_pci_read_config((osh), (offset), (size))
3014 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
3015 + osl_pci_write_config((osh), (offset), (size), (val))
3016 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
3017 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
3018 +
3019 +/* PCI device bus # and slot # */
3020 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
3021 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
3022 +extern uint osl_pci_bus(osl_t *osh);
3023 +extern uint osl_pci_slot(osl_t *osh);
3024 +
3025 +/* OSL initialization */
3026 +extern osl_t *osl_attach(void *pdev);
3027 +extern void osl_detach(osl_t *osh);
3028 +
3029 +/* host/bus architecture-specific byte swap */
3030 +#define BUS_SWAP32(v) (v)
3031 +
3032 +/* general purpose memory allocation */
3033 +
3034 +#if defined(BCMDBG_MEM)
3035 +
3036 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
3037 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
3038 +#define MALLOCED(osh) osl_malloced((osh))
3039 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
3040 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
3041 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
3042 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
3043 +
3044 +#else
3045 +
3046 +#define MALLOC(osh, size) osl_malloc((osh), (size))
3047 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
3048 +#define MALLOCED(osh) osl_malloced((osh))
3049 +
3050 +#endif /* BCMDBG_MEM */
3051 +
3052 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
3053 +
3054 +extern void *osl_malloc(osl_t *osh, uint size);
3055 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
3056 +extern uint osl_malloced(osl_t *osh);
3057 +extern uint osl_malloc_failed(osl_t *osh);
3058 +
3059 +/* allocate/free shared (dma-able) consistent memory */
3060 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
3061 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
3062 + osl_dma_alloc_consistent((osh), (size), (pap))
3063 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
3064 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
3065 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
3066 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
3067 +
3068 +/* map/unmap direction */
3069 +#define DMA_TX 1
3070 +#define DMA_RX 2
3071 +
3072 +/* map/unmap shared (dma-able) memory */
3073 +#define DMA_MAP(osh, va, size, direction, p) \
3074 + osl_dma_map((osh), (va), (size), (direction))
3075 +#define DMA_UNMAP(osh, pa, size, direction, p) \
3076 + osl_dma_unmap((osh), (pa), (size), (direction))
3077 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
3078 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
3079 +
3080 +/* register access macros */
3081 +#if defined(BCMJTAG)
3082 +#include <bcmjtag.h>
3083 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
3084 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
3085 +#endif
3086 +
3087 +/*
3088 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3089 + * Macros expand to calls to functions defined in linux_osl.c .
3090 + */
3091 +#ifndef BINOSL
3092 +
3093 +/* string library, kernel mode */
3094 +#define printf(fmt, args...) printk(fmt, ## args)
3095 +#include <linux/kernel.h>
3096 +#include <linux/string.h>
3097 +
3098 +/* register access macros */
3099 +#if !defined(BCMJTAG)
3100 +#ifndef IL_BIGENDIAN
3101 +#define R_REG(r) ( \
3102 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3103 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3104 + readl((volatile uint32*)(r)) \
3105 +)
3106 +#define W_REG(r, v) do { \
3107 + switch (sizeof(*(r))) { \
3108 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3109 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3110 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3111 + } \
3112 +} while (0)
3113 +#else /* IL_BIGENDIAN */
3114 +#define R_REG(r) ({ \
3115 + __typeof(*(r)) __osl_v; \
3116 + switch (sizeof(*(r))) { \
3117 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
3118 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
3119 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
3120 + } \
3121 + __osl_v; \
3122 +})
3123 +#define W_REG(r, v) do { \
3124 + switch (sizeof(*(r))) { \
3125 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
3126 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
3127 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3128 + } \
3129 +} while (0)
3130 +#endif
3131 +#endif
3132 +
3133 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3134 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3135 +
3136 +/* bcopy, bcmp, and bzero */
3137 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3138 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3139 +#define bzero(b, len) memset((b), '\0', (len))
3140 +
3141 +/* uncached virtual address */
3142 +#ifdef mips
3143 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3144 +#include <asm/addrspace.h>
3145 +#else
3146 +#define OSL_UNCACHED(va) (va)
3147 +#endif
3148 +
3149 +/* get processor cycle count */
3150 +#if defined(mips)
3151 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3152 +#elif defined(__i386__)
3153 +#define OSL_GETCYCLES(x) rdtscl((x))
3154 +#else
3155 +#define OSL_GETCYCLES(x) ((x) = 0)
3156 +#endif
3157 +
3158 +/* dereference an address that may cause a bus exception */
3159 +#ifdef mips
3160 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3161 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3162 +#else
3163 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3164 +#include <asm/paccess.h>
3165 +#endif
3166 +#else
3167 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3168 +#endif
3169 +
3170 +/* map/unmap physical to virtual I/O */
3171 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3172 +#define REG_UNMAP(va) iounmap((void *)(va))
3173 +
3174 +/* shared (dma-able) memory access macros */
3175 +#define R_SM(r) *(r)
3176 +#define W_SM(r, v) (*(r) = (v))
3177 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3178 +
3179 +/* packet primitives */
3180 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3181 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3182 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
3183 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
3184 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
3185 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3186 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
3187 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3188 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3189 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3190 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3191 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3192 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3193 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3194 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3195 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3196 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3197 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3198 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3199 +extern void osl_pktfree(void *skb);
3200 +
3201 +#else /* BINOSL */
3202 +
3203 +/* string library */
3204 +#ifndef LINUX_OSL
3205 +#undef printf
3206 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3207 +#undef sprintf
3208 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3209 +#undef strcmp
3210 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3211 +#undef strncmp
3212 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3213 +#undef strlen
3214 +#define strlen(s) osl_strlen((s))
3215 +#undef strcpy
3216 +#define strcpy(d, s) osl_strcpy((d), (s))
3217 +#undef strncpy
3218 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3219 +#endif
3220 +extern int osl_printf(const char *format, ...);
3221 +extern int osl_sprintf(char *buf, const char *format, ...);
3222 +extern int osl_strcmp(const char *s1, const char *s2);
3223 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3224 +extern int osl_strlen(const char *s);
3225 +extern char* osl_strcpy(char *d, const char *s);
3226 +extern char* osl_strncpy(char *d, const char *s, uint n);
3227 +
3228 +/* register access macros */
3229 +#if !defined(BCMJTAG)
3230 +#define R_REG(r) ( \
3231 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3232 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3233 + osl_readl((volatile uint32*)(r)) \
3234 +)
3235 +#define W_REG(r, v) do { \
3236 + switch (sizeof(*(r))) { \
3237 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3238 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3239 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3240 + } \
3241 +} while (0)
3242 +#endif
3243 +
3244 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3245 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3246 +extern uint8 osl_readb(volatile uint8 *r);
3247 +extern uint16 osl_readw(volatile uint16 *r);
3248 +extern uint32 osl_readl(volatile uint32 *r);
3249 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3250 +extern void osl_writew(uint16 v, volatile uint16 *r);
3251 +extern void osl_writel(uint32 v, volatile uint32 *r);
3252 +
3253 +/* bcopy, bcmp, and bzero */
3254 +extern void bcopy(const void *src, void *dst, int len);
3255 +extern int bcmp(const void *b1, const void *b2, int len);
3256 +extern void bzero(void *b, int len);
3257 +
3258 +/* uncached virtual address */
3259 +#define OSL_UNCACHED(va) osl_uncached((va))
3260 +extern void *osl_uncached(void *va);
3261 +
3262 +/* get processor cycle count */
3263 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3264 +extern uint osl_getcycles(void);
3265 +
3266 +/* dereference an address that may target abort */
3267 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3268 +extern int osl_busprobe(uint32 *val, uint32 addr);
3269 +
3270 +/* map/unmap physical to virtual */
3271 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3272 +#define REG_UNMAP(va) osl_reg_unmap((va))
3273 +extern void *osl_reg_map(uint32 pa, uint size);
3274 +extern void osl_reg_unmap(void *va);
3275 +
3276 +/* shared (dma-able) memory access macros */
3277 +#define R_SM(r) *(r)
3278 +#define W_SM(r, v) (*(r) = (v))
3279 +#define BZERO_SM(r, len) bzero((r), (len))
3280 +
3281 +/* packet primitives */
3282 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3283 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3284 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3285 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3286 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3287 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3288 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3289 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3290 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3291 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3292 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3293 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3294 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3295 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3296 +#define PKTLINK(skb) osl_pktlink((skb))
3297 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3298 +#define PKTPRIO(skb) osl_pktprio((skb))
3299 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3300 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3301 +extern void osl_pktfree(void *skb);
3302 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3303 +extern uint osl_pktlen(osl_t *osh, void *skb);
3304 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3305 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3306 +extern void *osl_pktnext(osl_t *osh, void *skb);
3307 +extern void osl_pktsetnext(void *skb, void *x);
3308 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3309 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3310 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3311 +extern void *osl_pktdup(osl_t *osh, void *skb);
3312 +extern void *osl_pktcookie(void *skb);
3313 +extern void osl_pktsetcookie(void *skb, void *x);
3314 +extern void *osl_pktlink(void *skb);
3315 +extern void osl_pktsetlink(void *skb, void *x);
3316 +extern uint osl_pktprio(void *skb);
3317 +extern void osl_pktsetprio(void *skb, uint x);
3318 +
3319 +#endif /* BINOSL */
3320 +
3321 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3322 +extern int osl_error(int bcmerror);
3323 +
3324 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3325 +#define PKTBUFSZ 2048
3326 +
3327 +#endif /* _linux_osl_h_ */
3328 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h
3329 --- linux-2.4.32/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3330 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/linuxver.h 2005-12-16 23:39:10.748824500 +0100
3331 @@ -0,0 +1,411 @@
3332 +/*
3333 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3334 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3335 + *
3336 + * Copyright 2005, Broadcom Corporation
3337 + * All Rights Reserved.
3338 + *
3339 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3340 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3341 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3342 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3343 + *
3344 + * $Id$
3345 + */
3346 +
3347 +#ifndef _linuxver_h_
3348 +#define _linuxver_h_
3349 +
3350 +#include <linux/config.h>
3351 +#include <linux/version.h>
3352 +
3353 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3354 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3355 +#ifdef __UNDEF_NO_VERSION__
3356 +#undef __NO_VERSION__
3357 +#else
3358 +#define __NO_VERSION__
3359 +#endif
3360 +#endif
3361 +
3362 +#if defined(MODULE) && defined(MODVERSIONS)
3363 +#include <linux/modversions.h>
3364 +#endif
3365 +
3366 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3367 +#include <linux/moduleparam.h>
3368 +#endif
3369 +
3370 +
3371 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3372 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3373 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3374 +#endif
3375 +
3376 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3377 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3378 +#include <linux/malloc.h>
3379 +#else
3380 +#include <linux/slab.h>
3381 +#endif
3382 +
3383 +#include <linux/types.h>
3384 +#include <linux/init.h>
3385 +#include <linux/mm.h>
3386 +#include <linux/string.h>
3387 +#include <linux/pci.h>
3388 +#include <linux/interrupt.h>
3389 +#include <linux/netdevice.h>
3390 +#include <asm/io.h>
3391 +
3392 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3393 +#include <linux/workqueue.h>
3394 +#else
3395 +#include <linux/tqueue.h>
3396 +#ifndef work_struct
3397 +#define work_struct tq_struct
3398 +#endif
3399 +#ifndef INIT_WORK
3400 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3401 +#endif
3402 +#ifndef schedule_work
3403 +#define schedule_work(_work) schedule_task((_work))
3404 +#endif
3405 +#ifndef flush_scheduled_work
3406 +#define flush_scheduled_work() flush_scheduled_tasks()
3407 +#endif
3408 +#endif
3409 +
3410 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3411 +/* Some distributions have their own 2.6.x compatibility layers */
3412 +#ifndef IRQ_NONE
3413 +typedef void irqreturn_t;
3414 +#define IRQ_NONE
3415 +#define IRQ_HANDLED
3416 +#define IRQ_RETVAL(x)
3417 +#endif
3418 +#else
3419 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3420 +#endif
3421 +
3422 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3423 +
3424 +#include <pcmcia/version.h>
3425 +#include <pcmcia/cs_types.h>
3426 +#include <pcmcia/cs.h>
3427 +#include <pcmcia/cistpl.h>
3428 +#include <pcmcia/cisreg.h>
3429 +#include <pcmcia/ds.h>
3430 +
3431 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3432 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3433 + * does this, but it's not in 2.4 so we do our own for now. */
3434 +static inline void
3435 +cs_error(client_handle_t handle, int func, int ret)
3436 +{
3437 + error_info_t err = { func, ret };
3438 + CardServices(ReportError, handle, &err);
3439 +}
3440 +#endif
3441 +
3442 +#endif /* CONFIG_PCMCIA */
3443 +
3444 +#ifndef __exit
3445 +#define __exit
3446 +#endif
3447 +#ifndef __devexit
3448 +#define __devexit
3449 +#endif
3450 +#ifndef __devinit
3451 +#define __devinit __init
3452 +#endif
3453 +#ifndef __devinitdata
3454 +#define __devinitdata
3455 +#endif
3456 +#ifndef __devexit_p
3457 +#define __devexit_p(x) x
3458 +#endif
3459 +
3460 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3461 +
3462 +#define pci_get_drvdata(dev) (dev)->sysdata
3463 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3464 +
3465 +/*
3466 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3467 + */
3468 +
3469 +struct pci_device_id {
3470 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3471 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3472 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3473 + unsigned long driver_data; /* Data private to the driver */
3474 +};
3475 +
3476 +struct pci_driver {
3477 + struct list_head node;
3478 + char *name;
3479 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3480 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3481 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3482 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3483 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3484 +};
3485 +
3486 +#define MODULE_DEVICE_TABLE(type, name)
3487 +#define PCI_ANY_ID (~0)
3488 +
3489 +/* compatpci.c */
3490 +#define pci_module_init pci_register_driver
3491 +extern int pci_register_driver(struct pci_driver *drv);
3492 +extern void pci_unregister_driver(struct pci_driver *drv);
3493 +
3494 +#endif /* PCI registration */
3495 +
3496 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3497 +#ifdef MODULE
3498 +#define module_init(x) int init_module(void) { return x(); }
3499 +#define module_exit(x) void cleanup_module(void) { x(); }
3500 +#else
3501 +#define module_init(x) __initcall(x);
3502 +#define module_exit(x) __exitcall(x);
3503 +#endif
3504 +#endif
3505 +
3506 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3507 +#define list_for_each(pos, head) \
3508 + for (pos = (head)->next; pos != (head); pos = pos->next)
3509 +#endif
3510 +
3511 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3512 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3513 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3514 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3515 +#endif
3516 +
3517 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3518 +#define pci_enable_device(dev) do { } while (0)
3519 +#endif
3520 +
3521 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3522 +#define net_device device
3523 +#endif
3524 +
3525 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3526 +
3527 +/*
3528 + * DMA mapping
3529 + *
3530 + * See linux/Documentation/DMA-mapping.txt
3531 + */
3532 +
3533 +#ifndef PCI_DMA_TODEVICE
3534 +#define PCI_DMA_TODEVICE 1
3535 +#define PCI_DMA_FROMDEVICE 2
3536 +#endif
3537 +
3538 +typedef u32 dma_addr_t;
3539 +
3540 +/* Pure 2^n version of get_order */
3541 +static inline int get_order(unsigned long size)
3542 +{
3543 + int order;
3544 +
3545 + size = (size-1) >> (PAGE_SHIFT-1);
3546 + order = -1;
3547 + do {
3548 + size >>= 1;
3549 + order++;
3550 + } while (size);
3551 + return order;
3552 +}
3553 +
3554 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3555 + dma_addr_t *dma_handle)
3556 +{
3557 + void *ret;
3558 + int gfp = GFP_ATOMIC | GFP_DMA;
3559 +
3560 + ret = (void *)__get_free_pages(gfp, get_order(size));
3561 +
3562 + if (ret != NULL) {
3563 + memset(ret, 0, size);
3564 + *dma_handle = virt_to_bus(ret);
3565 + }
3566 + return ret;
3567 +}
3568 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3569 + void *vaddr, dma_addr_t dma_handle)
3570 +{
3571 + free_pages((unsigned long)vaddr, get_order(size));
3572 +}
3573 +#ifdef ILSIM
3574 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3575 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3576 +#else
3577 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3578 +#define pci_unmap_single(cookie, address, size, dir)
3579 +#endif
3580 +
3581 +#endif /* DMA mapping */
3582 +
3583 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3584 +
3585 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3586 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3587 +
3588 +/* pcmcia-cs provides its own netdevice compatibility layer */
3589 +#ifndef _COMPAT_NETDEVICE_H
3590 +
3591 +/*
3592 + * SoftNet
3593 + *
3594 + * For pre-softnet kernels we need to tell the upper layer not to
3595 + * re-enter start_xmit() while we are in there. However softnet
3596 + * guarantees not to enter while we are in there so there is no need
3597 + * to do the netif_stop_queue() dance unless the transmit queue really
3598 + * gets stuck. This should also improve performance according to tests
3599 + * done by Aman Singla.
3600 + */
3601 +
3602 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3603 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3604 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3605 +
3606 +static inline void netif_start_queue(struct net_device *dev)
3607 +{
3608 + dev->tbusy = 0;
3609 + dev->interrupt = 0;
3610 + dev->start = 1;
3611 +}
3612 +
3613 +#define netif_queue_stopped(dev) (dev)->tbusy
3614 +#define netif_running(dev) (dev)->start
3615 +
3616 +#endif /* _COMPAT_NETDEVICE_H */
3617 +
3618 +#define netif_device_attach(dev) netif_start_queue(dev)
3619 +#define netif_device_detach(dev) netif_stop_queue(dev)
3620 +
3621 +/* 2.4.x renamed bottom halves to tasklets */
3622 +#define tasklet_struct tq_struct
3623 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3624 +{
3625 + queue_task(tasklet, &tq_immediate);
3626 + mark_bh(IMMEDIATE_BH);
3627 +}
3628 +
3629 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3630 + void (*func)(unsigned long),
3631 + unsigned long data)
3632 +{
3633 + tasklet->next = NULL;
3634 + tasklet->sync = 0;
3635 + tasklet->routine = (void (*)(void *))func;
3636 + tasklet->data = (void *)data;
3637 +}
3638 +#define tasklet_kill(tasklet) {do{} while(0);}
3639 +
3640 +/* 2.4.x introduced del_timer_sync() */
3641 +#define del_timer_sync(timer) del_timer(timer)
3642 +
3643 +#else
3644 +
3645 +#define netif_down(dev)
3646 +
3647 +#endif /* SoftNet */
3648 +
3649 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3650 +
3651 +/*
3652 + * Emit code to initialise a tq_struct's routine and data pointers
3653 + */
3654 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3655 + do { \
3656 + (_tq)->routine = _routine; \
3657 + (_tq)->data = _data; \
3658 + } while (0)
3659 +
3660 +/*
3661 + * Emit code to initialise all of a tq_struct
3662 + */
3663 +#define INIT_TQUEUE(_tq, _routine, _data) \
3664 + do { \
3665 + INIT_LIST_HEAD(&(_tq)->list); \
3666 + (_tq)->sync = 0; \
3667 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3668 + } while (0)
3669 +
3670 +#endif
3671 +
3672 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3673 +
3674 +/* Power management related routines */
3675 +
3676 +static inline int
3677 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3678 +{
3679 + int i;
3680 + if (buffer) {
3681 + for (i = 0; i < 16; i++)
3682 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3683 + }
3684 + return 0;
3685 +}
3686 +
3687 +static inline int
3688 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3689 +{
3690 + int i;
3691 +
3692 + if (buffer) {
3693 + for (i = 0; i < 16; i++)
3694 + pci_write_config_dword(dev,i * 4, buffer[i]);
3695 + }
3696 + /*
3697 + * otherwise, write the context information we know from bootup.
3698 + * This works around a problem where warm-booting from Windows
3699 + * combined with a D3(hot)->D0 transition causes PCI config
3700 + * header data to be forgotten.
3701 + */
3702 + else {
3703 + for (i = 0; i < 6; i ++)
3704 + pci_write_config_dword(dev,
3705 + PCI_BASE_ADDRESS_0 + (i * 4),
3706 + pci_resource_start(dev, i));
3707 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3708 + }
3709 + return 0;
3710 +}
3711 +
3712 +#endif /* PCI power management */
3713 +
3714 +/* Old cp0 access macros deprecated in 2.4.19 */
3715 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3716 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3717 +#endif
3718 +
3719 +/* Module refcount handled internally in 2.6.x */
3720 +#ifndef SET_MODULE_OWNER
3721 +#define SET_MODULE_OWNER(dev) do {} while (0)
3722 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3723 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3724 +#else
3725 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3726 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3727 +#endif
3728 +
3729 +#ifndef SET_NETDEV_DEV
3730 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3731 +#endif
3732 +
3733 +#ifndef HAVE_FREE_NETDEV
3734 +#define free_netdev(dev) kfree(dev)
3735 +#endif
3736 +
3737 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3738 +/* struct packet_type redefined in 2.6.x */
3739 +#define af_packet_priv data
3740 +#endif
3741 +
3742 +#endif /* _linuxver_h_ */
3743 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h
3744 --- linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3745 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h 2005-12-16 23:39:10.748824500 +0100
3746 @@ -0,0 +1,126 @@
3747 +/*
3748 + * HND Minimal OS Abstraction Layer.
3749 + *
3750 + * Copyright 2005, Broadcom Corporation
3751 + * All Rights Reserved.
3752 + *
3753 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3754 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3755 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3756 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3757 + *
3758 + * $Id$
3759 + */
3760 +
3761 +#ifndef _min_osl_h_
3762 +#define _min_osl_h_
3763 +
3764 +#include <typedefs.h>
3765 +#include <sbconfig.h>
3766 +#include <mipsinc.h>
3767 +
3768 +/* Cache support */
3769 +extern void caches_on(void);
3770 +extern void blast_dcache(void);
3771 +extern void blast_icache(void);
3772 +
3773 +/* uart output */
3774 +extern void putc(int c);
3775 +
3776 +/* lib functions */
3777 +extern int printf(const char *fmt, ...);
3778 +extern int sprintf(char *buf, const char *fmt, ...);
3779 +extern int strcmp(const char *s1, const char *s2);
3780 +extern int strncmp(const char *s1, const char *s2, uint n);
3781 +extern char *strcpy(char *dest, const char *src);
3782 +extern char *strncpy(char *dest, const char *src, uint n);
3783 +extern uint strlen(const char *s);
3784 +extern char *strchr(const char *str,int c);
3785 +extern char *strrchr(const char *str, int c);
3786 +extern char *strcat(char *d, const char *s);
3787 +extern void *memset(void *dest, int c, uint n);
3788 +extern void *memcpy(void *dest, const void *src, uint n);
3789 +extern int memcmp(const void *s1, const void *s2, uint n);
3790 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3791 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3792 +#define bzero(b, len) memset((b), '\0', (len))
3793 +
3794 +/* assert & debugging */
3795 +#define ASSERT(exp) do {} while (0)
3796 +
3797 +/* PCMCIA attribute space access macros */
3798 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3799 + ASSERT(0)
3800 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3801 + ASSERT(0)
3802 +
3803 +/* PCI configuration space access macros */
3804 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3805 + (offset == 8 ? 0 : 0xffffffff)
3806 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3807 + do {} while (0)
3808 +
3809 +/* PCI device bus # and slot # */
3810 +#define OSL_PCI_BUS(osh) (0)
3811 +#define OSL_PCI_SLOT(osh) (0)
3812 +
3813 +/* register access macros */
3814 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3815 +#define rreg32(r) (*(volatile uint32*)(r))
3816 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3817 +#define rreg16(r) (*(volatile uint16*)(r))
3818 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3819 +#define rreg8(r) (*(volatile uint8*)(r))
3820 +#define R_REG(r) ({ \
3821 + __typeof(*(r)) __osl_v; \
3822 + switch (sizeof(*(r))) { \
3823 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3824 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3825 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3826 + } \
3827 + __osl_v; \
3828 +})
3829 +#define W_REG(r, v) do { \
3830 + switch (sizeof(*(r))) { \
3831 + case sizeof(uint8): wreg8((r), (v)); break; \
3832 + case sizeof(uint16): wreg16((r), (v)); break; \
3833 + case sizeof(uint32): wreg32((r), (v)); break; \
3834 + } \
3835 +} while (0)
3836 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3837 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3838 +
3839 +/* general purpose memory allocation */
3840 +#define MALLOC(osh, size) malloc(size)
3841 +#define MFREE(osh, addr, size) free(addr)
3842 +#define MALLOCED(osh) 0
3843 +#define MALLOC_FAILED(osh) 0
3844 +#define MALLOC_DUMP(osh, buf, sz)
3845 +extern int free(void *ptr);
3846 +extern void *malloc(uint size);
3847 +
3848 +/* uncached virtual address */
3849 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3850 +
3851 +/* host/bus architecture-specific address byte swap */
3852 +#define BUS_SWAP32(v) (v)
3853 +
3854 +/* microsecond delay */
3855 +#define OSL_DELAY(usec) udelay(usec)
3856 +extern void udelay(uint32 usec);
3857 +
3858 +/* map/unmap physical to virtual I/O */
3859 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3860 +#define REG_UNMAP(va) do {} while (0)
3861 +
3862 +/* dereference an address that may cause a bus exception */
3863 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3864 +
3865 +/* Misc stubs */
3866 +#define osl_attach(pdev) ((osl_t*)pdev)
3867 +#define osl_detach(osh)
3868 +extern void *osl_init(void);
3869 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3870 +extern int osl_error(int);
3871 +
3872 +#endif /* _min_osl_h_ */
3873 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h
3874 --- linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3875 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-12-16 23:39:10.748824500 +0100
3876 @@ -0,0 +1,552 @@
3877 +/*
3878 + * HND Run Time Environment for standalone MIPS programs.
3879 + *
3880 + * Copyright 2005, Broadcom Corporation
3881 + * All Rights Reserved.
3882 + *
3883 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3884 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3885 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3886 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3887 + *
3888 + * $Id$
3889 + */
3890 +
3891 +#ifndef _MISPINC_H
3892 +#define _MISPINC_H
3893 +
3894 +
3895 +/* MIPS defines */
3896 +
3897 +#ifdef _LANGUAGE_ASSEMBLY
3898 +
3899 +/*
3900 + * Symbolic register names for 32 bit ABI
3901 + */
3902 +#define zero $0 /* wired zero */
3903 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3904 +#define v0 $2 /* return value */
3905 +#define v1 $3
3906 +#define a0 $4 /* argument registers */
3907 +#define a1 $5
3908 +#define a2 $6
3909 +#define a3 $7
3910 +#define t0 $8 /* caller saved */
3911 +#define t1 $9
3912 +#define t2 $10
3913 +#define t3 $11
3914 +#define t4 $12
3915 +#define t5 $13
3916 +#define t6 $14
3917 +#define t7 $15
3918 +#define s0 $16 /* callee saved */
3919 +#define s1 $17
3920 +#define s2 $18
3921 +#define s3 $19
3922 +#define s4 $20
3923 +#define s5 $21
3924 +#define s6 $22
3925 +#define s7 $23
3926 +#define t8 $24 /* caller saved */
3927 +#define t9 $25
3928 +#define jp $25 /* PIC jump register */
3929 +#define k0 $26 /* kernel scratch */
3930 +#define k1 $27
3931 +#define gp $28 /* global pointer */
3932 +#define sp $29 /* stack pointer */
3933 +#define fp $30 /* frame pointer */
3934 +#define s8 $30 /* same like fp! */
3935 +#define ra $31 /* return address */
3936 +
3937 +
3938 +/*
3939 + * CP0 Registers
3940 + */
3941 +
3942 +#define C0_INX $0
3943 +#define C0_RAND $1
3944 +#define C0_TLBLO0 $2
3945 +#define C0_TLBLO C0_TLBLO0
3946 +#define C0_TLBLO1 $3
3947 +#define C0_CTEXT $4
3948 +#define C0_PGMASK $5
3949 +#define C0_WIRED $6
3950 +#define C0_BADVADDR $8
3951 +#define C0_COUNT $9
3952 +#define C0_TLBHI $10
3953 +#define C0_COMPARE $11
3954 +#define C0_SR $12
3955 +#define C0_STATUS C0_SR
3956 +#define C0_CAUSE $13
3957 +#define C0_EPC $14
3958 +#define C0_PRID $15
3959 +#define C0_CONFIG $16
3960 +#define C0_LLADDR $17
3961 +#define C0_WATCHLO $18
3962 +#define C0_WATCHHI $19
3963 +#define C0_XCTEXT $20
3964 +#define C0_DIAGNOSTIC $22
3965 +#define C0_BROADCOM C0_DIAGNOSTIC
3966 +#define C0_PERFORMANCE $25
3967 +#define C0_ECC $26
3968 +#define C0_CACHEERR $27
3969 +#define C0_TAGLO $28
3970 +#define C0_TAGHI $29
3971 +#define C0_ERREPC $30
3972 +#define C0_DESAVE $31
3973 +
3974 +/*
3975 + * LEAF - declare leaf routine
3976 + */
3977 +#define LEAF(symbol) \
3978 + .globl symbol; \
3979 + .align 2; \
3980 + .type symbol,@function; \
3981 + .ent symbol,0; \
3982 +symbol: .frame sp,0,ra
3983 +
3984 +/*
3985 + * END - mark end of function
3986 + */
3987 +#define END(function) \
3988 + .end function; \
3989 + .size function,.-function
3990 +
3991 +#define _ULCAST_
3992 +
3993 +#else
3994 +
3995 +/*
3996 + * The following macros are especially useful for __asm__
3997 + * inline assembler.
3998 + */
3999 +#ifndef __STR
4000 +#define __STR(x) #x
4001 +#endif
4002 +#ifndef STR
4003 +#define STR(x) __STR(x)
4004 +#endif
4005 +
4006 +#define _ULCAST_ (unsigned long)
4007 +
4008 +
4009 +/*
4010 + * CP0 Registers
4011 + */
4012 +
4013 +#define C0_INX 0 /* CP0: TLB Index */
4014 +#define C0_RAND 1 /* CP0: TLB Random */
4015 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4016 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4017 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4018 +#define C0_CTEXT 4 /* CP0: Context */
4019 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4020 +#define C0_WIRED 6 /* CP0: TLB Wired */
4021 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4022 +#define C0_COUNT 9 /* CP0: Count */
4023 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4024 +#define C0_COMPARE 11 /* CP0: Compare */
4025 +#define C0_SR 12 /* CP0: Processor Status */
4026 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4027 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4028 +#define C0_EPC 14 /* CP0: Exception PC */
4029 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4030 +#define C0_CONFIG 16 /* CP0: Config */
4031 +#define C0_LLADDR 17 /* CP0: LLAddr */
4032 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4033 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4034 +#define C0_XCTEXT 20 /* CP0: XContext */
4035 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4036 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4037 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4038 +#define C0_ECC 26 /* CP0: ECC */
4039 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4040 +#define C0_TAGLO 28 /* CP0: TagLo */
4041 +#define C0_TAGHI 29 /* CP0: TagHi */
4042 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4043 +#define C0_DESAVE 31 /* CP0: DebugSave */
4044 +
4045 +#endif /* _LANGUAGE_ASSEMBLY */
4046 +
4047 +/*
4048 + * Memory segments (32bit kernel mode addresses)
4049 + */
4050 +#undef KUSEG
4051 +#undef KSEG0
4052 +#undef KSEG1
4053 +#undef KSEG2
4054 +#undef KSEG3
4055 +#define KUSEG 0x00000000
4056 +#define KSEG0 0x80000000
4057 +#define KSEG1 0xa0000000
4058 +#define KSEG2 0xc0000000
4059 +#define KSEG3 0xe0000000
4060 +#define PHYSADDR_MASK 0x1fffffff
4061 +
4062 +/*
4063 + * Map an address to a certain kernel segment
4064 + */
4065 +#undef PHYSADDR
4066 +#undef KSEG0ADDR
4067 +#undef KSEG1ADDR
4068 +#undef KSEG2ADDR
4069 +#undef KSEG3ADDR
4070 +
4071 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4072 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4073 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4074 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4075 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4076 +
4077 +
4078 +#ifndef Index_Invalidate_I
4079 +/*
4080 + * Cache Operations
4081 + */
4082 +#define Index_Invalidate_I 0x00
4083 +#define Index_Writeback_Inv_D 0x01
4084 +#define Index_Invalidate_SI 0x02
4085 +#define Index_Writeback_Inv_SD 0x03
4086 +#define Index_Load_Tag_I 0x04
4087 +#define Index_Load_Tag_D 0x05
4088 +#define Index_Load_Tag_SI 0x06
4089 +#define Index_Load_Tag_SD 0x07
4090 +#define Index_Store_Tag_I 0x08
4091 +#define Index_Store_Tag_D 0x09
4092 +#define Index_Store_Tag_SI 0x0A
4093 +#define Index_Store_Tag_SD 0x0B
4094 +#define Create_Dirty_Excl_D 0x0d
4095 +#define Create_Dirty_Excl_SD 0x0f
4096 +#define Hit_Invalidate_I 0x10
4097 +#define Hit_Invalidate_D 0x11
4098 +#define Hit_Invalidate_SI 0x12
4099 +#define Hit_Invalidate_SD 0x13
4100 +#define Fill_I 0x14
4101 +#define Hit_Writeback_Inv_D 0x15
4102 + /* 0x16 is unused */
4103 +#define Hit_Writeback_Inv_SD 0x17
4104 +#define R5K_Page_Invalidate_S 0x17
4105 +#define Hit_Writeback_I 0x18
4106 +#define Hit_Writeback_D 0x19
4107 + /* 0x1a is unused */
4108 +#define Hit_Writeback_SD 0x1b
4109 + /* 0x1c is unused */
4110 + /* 0x1e is unused */
4111 +#define Hit_Set_Virtual_SI 0x1e
4112 +#define Hit_Set_Virtual_SD 0x1f
4113 +#endif
4114 +
4115 +
4116 +/*
4117 + * R4x00 interrupt enable / cause bits
4118 + */
4119 +#define IE_SW0 (_ULCAST_(1) << 8)
4120 +#define IE_SW1 (_ULCAST_(1) << 9)
4121 +#define IE_IRQ0 (_ULCAST_(1) << 10)
4122 +#define IE_IRQ1 (_ULCAST_(1) << 11)
4123 +#define IE_IRQ2 (_ULCAST_(1) << 12)
4124 +#define IE_IRQ3 (_ULCAST_(1) << 13)
4125 +#define IE_IRQ4 (_ULCAST_(1) << 14)
4126 +#define IE_IRQ5 (_ULCAST_(1) << 15)
4127 +
4128 +#ifndef ST0_UM
4129 +/*
4130 + * Bitfields in the mips32 cp0 status register
4131 + */
4132 +#define ST0_IE 0x00000001
4133 +#define ST0_EXL 0x00000002
4134 +#define ST0_ERL 0x00000004
4135 +#define ST0_UM 0x00000010
4136 +#define ST0_SWINT0 0x00000100
4137 +#define ST0_SWINT1 0x00000200
4138 +#define ST0_HWINT0 0x00000400
4139 +#define ST0_HWINT1 0x00000800
4140 +#define ST0_HWINT2 0x00001000
4141 +#define ST0_HWINT3 0x00002000
4142 +#define ST0_HWINT4 0x00004000
4143 +#define ST0_HWINT5 0x00008000
4144 +#define ST0_IM 0x0000ff00
4145 +#define ST0_NMI 0x00080000
4146 +#define ST0_SR 0x00100000
4147 +#define ST0_TS 0x00200000
4148 +#define ST0_BEV 0x00400000
4149 +#define ST0_RE 0x02000000
4150 +#define ST0_RP 0x08000000
4151 +#define ST0_CU 0xf0000000
4152 +#define ST0_CU0 0x10000000
4153 +#define ST0_CU1 0x20000000
4154 +#define ST0_CU2 0x40000000
4155 +#define ST0_CU3 0x80000000
4156 +#endif
4157 +
4158 +
4159 +/*
4160 + * Bitfields in the mips32 cp0 cause register
4161 + */
4162 +#define C_EXC 0x0000007c
4163 +#define C_EXC_SHIFT 2
4164 +#define C_INT 0x0000ff00
4165 +#define C_INT_SHIFT 8
4166 +#define C_SW0 (_ULCAST_(1) << 8)
4167 +#define C_SW1 (_ULCAST_(1) << 9)
4168 +#define C_IRQ0 (_ULCAST_(1) << 10)
4169 +#define C_IRQ1 (_ULCAST_(1) << 11)
4170 +#define C_IRQ2 (_ULCAST_(1) << 12)
4171 +#define C_IRQ3 (_ULCAST_(1) << 13)
4172 +#define C_IRQ4 (_ULCAST_(1) << 14)
4173 +#define C_IRQ5 (_ULCAST_(1) << 15)
4174 +#define C_WP 0x00400000
4175 +#define C_IV 0x00800000
4176 +#define C_CE 0x30000000
4177 +#define C_CE_SHIFT 28
4178 +#define C_BD 0x80000000
4179 +
4180 +/* Values in C_EXC */
4181 +#define EXC_INT 0
4182 +#define EXC_TLBM 1
4183 +#define EXC_TLBL 2
4184 +#define EXC_TLBS 3
4185 +#define EXC_AEL 4
4186 +#define EXC_AES 5
4187 +#define EXC_IBE 6
4188 +#define EXC_DBE 7
4189 +#define EXC_SYS 8
4190 +#define EXC_BPT 9
4191 +#define EXC_RI 10
4192 +#define EXC_CU 11
4193 +#define EXC_OV 12
4194 +#define EXC_TR 13
4195 +#define EXC_WATCH 23
4196 +#define EXC_MCHK 24
4197 +
4198 +
4199 +/*
4200 + * Bits in the cp0 config register.
4201 + */
4202 +#define CONF_CM_CACHABLE_NO_WA 0
4203 +#define CONF_CM_CACHABLE_WA 1
4204 +#define CONF_CM_UNCACHED 2
4205 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4206 +#define CONF_CM_CACHABLE_CE 4
4207 +#define CONF_CM_CACHABLE_COW 5
4208 +#define CONF_CM_CACHABLE_CUW 6
4209 +#define CONF_CM_CACHABLE_ACCELERATED 7
4210 +#define CONF_CM_CMASK 7
4211 +#define CONF_CU (_ULCAST_(1) << 3)
4212 +#define CONF_DB (_ULCAST_(1) << 4)
4213 +#define CONF_IB (_ULCAST_(1) << 5)
4214 +#define CONF_SE (_ULCAST_(1) << 12)
4215 +#define CONF_SC (_ULCAST_(1) << 17)
4216 +#define CONF_AC (_ULCAST_(1) << 23)
4217 +#define CONF_HALT (_ULCAST_(1) << 25)
4218 +
4219 +
4220 +/*
4221 + * Bits in the cp0 config register select 1.
4222 + */
4223 +#define CONF1_FP 0x00000001 /* FPU present */
4224 +#define CONF1_EP 0x00000002 /* EJTAG present */
4225 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4226 +#define CONF1_WR 0x00000008 /* Watch registers present */
4227 +#define CONF1_PC 0x00000010 /* Performance counters present */
4228 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4229 +#define CONF1_DA_MASK 0x00000380
4230 +#define CONF1_DA_BASE 1
4231 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4232 +#define CONF1_DL_MASK 0x00001c00
4233 +#define CONF1_DL_BASE 2
4234 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4235 +#define CONF1_DS_MASK 0x0000e000
4236 +#define CONF1_DS_BASE 64
4237 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4238 +#define CONF1_IA_MASK 0x00070000
4239 +#define CONF1_IA_BASE 1
4240 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4241 +#define CONF1_IL_MASK 0x00380000
4242 +#define CONF1_IL_BASE 2
4243 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4244 +#define CONF1_IS_MASK 0x01c00000
4245 +#define CONF1_IS_BASE 64
4246 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4247 +#define CONF1_MS_SHIFT 25
4248 +
4249 +/* PRID register */
4250 +#define PRID_COPT_MASK 0xff000000
4251 +#define PRID_COMP_MASK 0x00ff0000
4252 +#define PRID_IMP_MASK 0x0000ff00
4253 +#define PRID_REV_MASK 0x000000ff
4254 +
4255 +#define PRID_COMP_LEGACY 0x000000
4256 +#define PRID_COMP_MIPS 0x010000
4257 +#define PRID_COMP_BROADCOM 0x020000
4258 +#define PRID_COMP_ALCHEMY 0x030000
4259 +#define PRID_COMP_SIBYTE 0x040000
4260 +#define PRID_IMP_BCM4710 0x4000
4261 +#define PRID_IMP_BCM3302 0x9000
4262 +#define PRID_IMP_BCM3303 0x9100
4263 +
4264 +#define PRID_IMP_UNKNOWN 0xff00
4265 +
4266 +#define BCM330X(id) \
4267 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4268 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4269 +
4270 +/* Bits in C0_BROADCOM */
4271 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4272 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4273 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4274 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4275 +
4276 +/* PreFetch Cache aka Read Ahead Cache */
4277 +
4278 +#define PFC_CR0 0xff400000 /* control reg 0 */
4279 +#define PFC_CR1 0xff400004 /* control reg 1 */
4280 +
4281 +/* PFC operations */
4282 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
4283 +#define PFC_D 0x00000002 /* Enable PFC use for data */
4284 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
4285 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
4286 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
4287 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
4288 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
4289 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
4290 +#define PFC_BRR 0x40000000 /* Bus error indication */
4291 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
4292 +
4293 +/* Handy defaults */
4294 +#define PFC_DISABLED 0
4295 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
4296 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
4297 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
4298 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
4299 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
4300 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
4301 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
4302 +
4303 +
4304 +/*
4305 + * These are the UART port assignments, expressed as offsets from the base
4306 + * register. These assignments should hold for any serial port based on
4307 + * a 8250, 16450, or 16550(A).
4308 + */
4309 +
4310 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4311 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4312 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4313 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4314 +#define UART_LCR 3 /* Out: Line Control Register */
4315 +#define UART_MCR 4 /* Out: Modem Control Register */
4316 +#define UART_LSR 5 /* In: Line Status Register */
4317 +#define UART_MSR 6 /* In: Modem Status Register */
4318 +#define UART_SCR 7 /* I/O: Scratch Register */
4319 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4320 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4321 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4322 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4323 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4324 +
4325 +
4326 +#ifndef _LANGUAGE_ASSEMBLY
4327 +
4328 +/*
4329 + * Macros to access the system control coprocessor
4330 + */
4331 +
4332 +#define MFC0(source, sel) \
4333 +({ \
4334 + int __res; \
4335 + __asm__ __volatile__( \
4336 + ".set\tnoreorder\n\t" \
4337 + ".set\tnoat\n\t" \
4338 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
4339 + "move\t%0,$1\n\t" \
4340 + ".set\tat\n\t" \
4341 + ".set\treorder" \
4342 + :"=r" (__res) \
4343 + : \
4344 + :"$1"); \
4345 + __res; \
4346 +})
4347 +
4348 +#define MTC0(source, sel, value) \
4349 +do { \
4350 + __asm__ __volatile__( \
4351 + ".set\tnoreorder\n\t" \
4352 + ".set\tnoat\n\t" \
4353 + "move\t$1,%z0\n\t" \
4354 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
4355 + ".set\tat\n\t" \
4356 + ".set\treorder" \
4357 + : \
4358 + :"jr" (value) \
4359 + :"$1"); \
4360 +} while (0)
4361 +
4362 +#define get_c0_count() \
4363 +({ \
4364 + int __res; \
4365 + __asm__ __volatile__( \
4366 + ".set\tnoreorder\n\t" \
4367 + ".set\tnoat\n\t" \
4368 + "mfc0\t%0,$9\n\t" \
4369 + ".set\tat\n\t" \
4370 + ".set\treorder" \
4371 + :"=r" (__res)); \
4372 + __res; \
4373 +})
4374 +
4375 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
4376 +{
4377 + uint lsz, sets, ways;
4378 +
4379 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4380 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
4381 + lsz = CONF1_IL_BASE << lsz;
4382 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
4383 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
4384 + *size = lsz * sets * ways;
4385 + *lsize = lsz;
4386 +}
4387 +
4388 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
4389 +{
4390 + uint lsz, sets, ways;
4391 +
4392 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
4393 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
4394 + lsz = CONF1_DL_BASE << lsz;
4395 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
4396 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
4397 + *size = lsz * sets * ways;
4398 + *lsize = lsz;
4399 +}
4400 +
4401 +#define cache_op(base, op) \
4402 + __asm__ __volatile__(" \
4403 + .set noreorder; \
4404 + .set mips3; \
4405 + cache %1, (%0); \
4406 + .set mips0; \
4407 + .set reorder" \
4408 + : \
4409 + : "r" (base), \
4410 + "i" (op));
4411 +
4412 +#define cache_unroll4(base, delta, op) \
4413 + __asm__ __volatile__(" \
4414 + .set noreorder; \
4415 + .set mips3; \
4416 + cache %1,0(%0); \
4417 + cache %1,delta(%0); \
4418 + cache %1,(2 * delta)(%0); \
4419 + cache %1,(3 * delta)(%0); \
4420 + .set mips0; \
4421 + .set reorder" \
4422 + : \
4423 + : "r" (base), \
4424 + "i" (op));
4425 +
4426 +#endif /* !_LANGUAGE_ASSEMBLY */
4427 +
4428 +#endif /* _MISPINC_H */
4429 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/nvports.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h
4430 --- linux-2.4.32/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4431 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h 2005-12-16 23:39:10.748824500 +0100
4432 @@ -0,0 +1,55 @@
4433 +/*
4434 + * BCM53xx RoboSwitch utility functions
4435 + *
4436 + * Copyright (C) 2002 Broadcom Corporation
4437 + * $Id$
4438 + */
4439 +
4440 +#ifndef _nvports_h_
4441 +#define _nvports_h_
4442 +
4443 +#define uint32 unsigned long
4444 +#define uint16 unsigned short
4445 +#define uint unsigned int
4446 +#define uint8 unsigned char
4447 +#define uint64 unsigned long long
4448 +
4449 +enum FORCE_PORT {
4450 + FORCE_OFF,
4451 + FORCE_10H,
4452 + FORCE_10F,
4453 + FORCE_100H,
4454 + FORCE_100F,
4455 + FORCE_DOWN,
4456 + POWER_OFF
4457 +};
4458 +
4459 +typedef struct _PORT_ATTRIBS
4460 +{
4461 + uint autoneg;
4462 + uint force;
4463 + uint native;
4464 +} PORT_ATTRIBS;
4465 +
4466 +extern uint
4467 +nvExistsPortAttrib(char *attrib, uint portno);
4468 +
4469 +extern int
4470 +nvExistsAnyForcePortAttrib(uint portno);
4471 +
4472 +extern void
4473 +nvSetPortAttrib(char *attrib, uint portno);
4474 +
4475 +extern void
4476 +nvUnsetPortAttrib(char *attrib, uint portno);
4477 +
4478 +extern void
4479 +nvUnsetAllForcePortAttrib(uint portno);
4480 +
4481 +extern PORT_ATTRIBS
4482 +nvGetSwitchPortAttribs(uint portno);
4483 +
4484 +#endif /* _nvports_h_ */
4485 +
4486 +
4487 +
4488 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h
4489 --- linux-2.4.32/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4490 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h 2005-12-16 23:39:10.748824500 +0100
4491 @@ -0,0 +1,42 @@
4492 +/*
4493 + * OS Abstraction Layer
4494 + *
4495 + * Copyright 2005, Broadcom Corporation
4496 + * All Rights Reserved.
4497 + *
4498 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4499 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4500 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4501 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4502 + * $Id$
4503 + */
4504 +
4505 +#ifndef _osl_h_
4506 +#define _osl_h_
4507 +
4508 +/* osl handle type forward declaration */
4509 +typedef struct os_handle osl_t;
4510 +
4511 +#if defined(linux)
4512 +#include <linux_osl.h>
4513 +#elif defined(NDIS)
4514 +#include <ndis_osl.h>
4515 +#elif defined(_CFE_)
4516 +#include <cfe_osl.h>
4517 +#elif defined(_HNDRTE_)
4518 +#include <hndrte_osl.h>
4519 +#elif defined(_MINOSL_)
4520 +#include <min_osl.h>
4521 +#elif PMON
4522 +#include <pmon_osl.h>
4523 +#elif defined(MACOSX)
4524 +#include <macosx_osl.h>
4525 +#else
4526 +#error "Unsupported OSL requested"
4527 +#endif
4528 +
4529 +/* handy */
4530 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4531 +#define MAXPRIO 7 /* 0-7 */
4532 +
4533 +#endif /* _osl_h_ */
4534 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h
4535 --- linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4536 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-12-16 23:39:10.752824750 +0100
4537 @@ -0,0 +1,451 @@
4538 +/*
4539 + * pcicfg.h: PCI configuration constants and structures.
4540 + *
4541 + * Copyright 2005, Broadcom Corporation
4542 + * All Rights Reserved.
4543 + *
4544 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4545 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4546 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4547 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4548 + *
4549 + * $Id$
4550 + */
4551 +
4552 +#ifndef _h_pci_
4553 +#define _h_pci_
4554 +
4555 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4556 +#ifndef PCI_MAX_BUS
4557 +#define PCI_MAX_BUS 0x100
4558 +#endif
4559 +#ifndef PCI_MAX_DEVICES
4560 +#define PCI_MAX_DEVICES 0x20
4561 +#endif
4562 +#ifndef PCI_MAX_FUNCTION
4563 +#define PCI_MAX_FUNCTION 0x8
4564 +#endif
4565 +
4566 +#ifndef PCI_INVALID_VENDORID
4567 +#define PCI_INVALID_VENDORID 0xffff
4568 +#endif
4569 +#ifndef PCI_INVALID_DEVICEID
4570 +#define PCI_INVALID_DEVICEID 0xffff
4571 +#endif
4572 +
4573 +
4574 +/* Convert between bus-slot-function-register and config addresses */
4575 +
4576 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4577 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4578 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4579 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
4580 +
4581 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4582 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4583 +#define PCICFG_FUN_MASK 7 /* Function mask */
4584 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4585 +
4586 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4587 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4588 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4589 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4590 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4591 +
4592 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4593 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4594 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4595 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4596 +
4597 +/* PCIE Config space accessing MACROS*/
4598 +
4599 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
4600 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
4601 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
4602 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
4603 +
4604 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
4605 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
4606 +#define PCIECFG_FUN_MASK 7 /* Function mask */
4607 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
4608 +
4609 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
4610 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
4611 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
4612 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
4613 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
4614 +
4615 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
4616 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
4617 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
4618 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
4619 +
4620 +
4621 +/* The actual config space */
4622 +
4623 +#define PCI_BAR_MAX 6
4624 +
4625 +#define PCI_ROM_BAR 8
4626 +
4627 +#define PCR_RSVDA_MAX 2
4628 +
4629 +/* pci config status reg has a bit to indicate that capability ptr is present*/
4630 +
4631 +#define PCI_CAPPTR_PRESENT 0x0010
4632 +
4633 +typedef struct _pci_config_regs {
4634 + unsigned short vendor;
4635 + unsigned short device;
4636 + unsigned short command;
4637 + unsigned short status;
4638 + unsigned char rev_id;
4639 + unsigned char prog_if;
4640 + unsigned char sub_class;
4641 + unsigned char base_class;
4642 + unsigned char cache_line_size;
4643 + unsigned char latency_timer;
4644 + unsigned char header_type;
4645 + unsigned char bist;
4646 + unsigned long base[PCI_BAR_MAX];
4647 + unsigned long cardbus_cis;
4648 + unsigned short subsys_vendor;
4649 + unsigned short subsys_id;
4650 + unsigned long baserom;
4651 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4652 + unsigned char int_line;
4653 + unsigned char int_pin;
4654 + unsigned char min_gnt;
4655 + unsigned char max_lat;
4656 + unsigned char dev_dep[192];
4657 +} pci_config_regs;
4658 +
4659 +#define SZPCR (sizeof (pci_config_regs))
4660 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4661 +
4662 +/* A structure for the config registers is nice, but in most
4663 + * systems the config space is not memory mapped, so we need
4664 + * filed offsetts. :-(
4665 + */
4666 +#define PCI_CFG_VID 0
4667 +#define PCI_CFG_DID 2
4668 +#define PCI_CFG_CMD 4
4669 +#define PCI_CFG_STAT 6
4670 +#define PCI_CFG_REV 8
4671 +#define PCI_CFG_PROGIF 9
4672 +#define PCI_CFG_SUBCL 0xa
4673 +#define PCI_CFG_BASECL 0xb
4674 +#define PCI_CFG_CLSZ 0xc
4675 +#define PCI_CFG_LATTIM 0xd
4676 +#define PCI_CFG_HDR 0xe
4677 +#define PCI_CFG_BIST 0xf
4678 +#define PCI_CFG_BAR0 0x10
4679 +#define PCI_CFG_BAR1 0x14
4680 +#define PCI_CFG_BAR2 0x18
4681 +#define PCI_CFG_BAR3 0x1c
4682 +#define PCI_CFG_BAR4 0x20
4683 +#define PCI_CFG_BAR5 0x24
4684 +#define PCI_CFG_CIS 0x28
4685 +#define PCI_CFG_SVID 0x2c
4686 +#define PCI_CFG_SSID 0x2e
4687 +#define PCI_CFG_ROMBAR 0x30
4688 +#define PCI_CFG_CAPPTR 0x34
4689 +#define PCI_CFG_INT 0x3c
4690 +#define PCI_CFG_PIN 0x3d
4691 +#define PCI_CFG_MINGNT 0x3e
4692 +#define PCI_CFG_MAXLAT 0x3f
4693 +
4694 +/* Classes and subclasses */
4695 +
4696 +typedef enum {
4697 + PCI_CLASS_OLD = 0,
4698 + PCI_CLASS_DASDI,
4699 + PCI_CLASS_NET,
4700 + PCI_CLASS_DISPLAY,
4701 + PCI_CLASS_MMEDIA,
4702 + PCI_CLASS_MEMORY,
4703 + PCI_CLASS_BRIDGE,
4704 + PCI_CLASS_COMM,
4705 + PCI_CLASS_BASE,
4706 + PCI_CLASS_INPUT,
4707 + PCI_CLASS_DOCK,
4708 + PCI_CLASS_CPU,
4709 + PCI_CLASS_SERIAL,
4710 + PCI_CLASS_INTELLIGENT = 0xe,
4711 + PCI_CLASS_SATELLITE,
4712 + PCI_CLASS_CRYPT,
4713 + PCI_CLASS_DSP,
4714 + PCI_CLASS_MAX
4715 +} pci_classes;
4716 +
4717 +typedef enum {
4718 + PCI_DASDI_SCSI,
4719 + PCI_DASDI_IDE,
4720 + PCI_DASDI_FLOPPY,
4721 + PCI_DASDI_IPI,
4722 + PCI_DASDI_RAID,
4723 + PCI_DASDI_OTHER = 0x80
4724 +} pci_dasdi_subclasses;
4725 +
4726 +typedef enum {
4727 + PCI_NET_ETHER,
4728 + PCI_NET_TOKEN,
4729 + PCI_NET_FDDI,
4730 + PCI_NET_ATM,
4731 + PCI_NET_OTHER = 0x80
4732 +} pci_net_subclasses;
4733 +
4734 +typedef enum {
4735 + PCI_DISPLAY_VGA,
4736 + PCI_DISPLAY_XGA,
4737 + PCI_DISPLAY_3D,
4738 + PCI_DISPLAY_OTHER = 0x80
4739 +} pci_display_subclasses;
4740 +
4741 +typedef enum {
4742 + PCI_MMEDIA_VIDEO,
4743 + PCI_MMEDIA_AUDIO,
4744 + PCI_MMEDIA_PHONE,
4745 + PCI_MEDIA_OTHER = 0x80
4746 +} pci_mmedia_subclasses;
4747 +
4748 +typedef enum {
4749 + PCI_MEMORY_RAM,
4750 + PCI_MEMORY_FLASH,
4751 + PCI_MEMORY_OTHER = 0x80
4752 +} pci_memory_subclasses;
4753 +
4754 +typedef enum {
4755 + PCI_BRIDGE_HOST,
4756 + PCI_BRIDGE_ISA,
4757 + PCI_BRIDGE_EISA,
4758 + PCI_BRIDGE_MC,
4759 + PCI_BRIDGE_PCI,
4760 + PCI_BRIDGE_PCMCIA,
4761 + PCI_BRIDGE_NUBUS,
4762 + PCI_BRIDGE_CARDBUS,
4763 + PCI_BRIDGE_RACEWAY,
4764 + PCI_BRIDGE_OTHER = 0x80
4765 +} pci_bridge_subclasses;
4766 +
4767 +typedef enum {
4768 + PCI_COMM_UART,
4769 + PCI_COMM_PARALLEL,
4770 + PCI_COMM_MULTIUART,
4771 + PCI_COMM_MODEM,
4772 + PCI_COMM_OTHER = 0x80
4773 +} pci_comm_subclasses;
4774 +
4775 +typedef enum {
4776 + PCI_BASE_PIC,
4777 + PCI_BASE_DMA,
4778 + PCI_BASE_TIMER,
4779 + PCI_BASE_RTC,
4780 + PCI_BASE_PCI_HOTPLUG,
4781 + PCI_BASE_OTHER = 0x80
4782 +} pci_base_subclasses;
4783 +
4784 +typedef enum {
4785 + PCI_INPUT_KBD,
4786 + PCI_INPUT_PEN,
4787 + PCI_INPUT_MOUSE,
4788 + PCI_INPUT_SCANNER,
4789 + PCI_INPUT_GAMEPORT,
4790 + PCI_INPUT_OTHER = 0x80
4791 +} pci_input_subclasses;
4792 +
4793 +typedef enum {
4794 + PCI_DOCK_GENERIC,
4795 + PCI_DOCK_OTHER = 0x80
4796 +} pci_dock_subclasses;
4797 +
4798 +typedef enum {
4799 + PCI_CPU_386,
4800 + PCI_CPU_486,
4801 + PCI_CPU_PENTIUM,
4802 + PCI_CPU_ALPHA = 0x10,
4803 + PCI_CPU_POWERPC = 0x20,
4804 + PCI_CPU_MIPS = 0x30,
4805 + PCI_CPU_COPROC = 0x40,
4806 + PCI_CPU_OTHER = 0x80
4807 +} pci_cpu_subclasses;
4808 +
4809 +typedef enum {
4810 + PCI_SERIAL_IEEE1394,
4811 + PCI_SERIAL_ACCESS,
4812 + PCI_SERIAL_SSA,
4813 + PCI_SERIAL_USB,
4814 + PCI_SERIAL_FIBER,
4815 + PCI_SERIAL_SMBUS,
4816 + PCI_SERIAL_OTHER = 0x80
4817 +} pci_serial_subclasses;
4818 +
4819 +typedef enum {
4820 + PCI_INTELLIGENT_I2O,
4821 +} pci_intelligent_subclasses;
4822 +
4823 +typedef enum {
4824 + PCI_SATELLITE_TV,
4825 + PCI_SATELLITE_AUDIO,
4826 + PCI_SATELLITE_VOICE,
4827 + PCI_SATELLITE_DATA,
4828 + PCI_SATELLITE_OTHER = 0x80
4829 +} pci_satellite_subclasses;
4830 +
4831 +typedef enum {
4832 + PCI_CRYPT_NETWORK,
4833 + PCI_CRYPT_ENTERTAINMENT,
4834 + PCI_CRYPT_OTHER = 0x80
4835 +} pci_crypt_subclasses;
4836 +
4837 +typedef enum {
4838 + PCI_DSP_DPIO,
4839 + PCI_DSP_OTHER = 0x80
4840 +} pci_dsp_subclasses;
4841 +
4842 +/* Header types */
4843 +typedef enum {
4844 + PCI_HEADER_NORMAL,
4845 + PCI_HEADER_BRIDGE,
4846 + PCI_HEADER_CARDBUS
4847 +} pci_header_types;
4848 +
4849 +
4850 +/* Overlay for a PCI-to-PCI bridge */
4851 +
4852 +#define PPB_RSVDA_MAX 2
4853 +#define PPB_RSVDD_MAX 8
4854 +
4855 +typedef struct _ppb_config_regs {
4856 + unsigned short vendor;
4857 + unsigned short device;
4858 + unsigned short command;
4859 + unsigned short status;
4860 + unsigned char rev_id;
4861 + unsigned char prog_if;
4862 + unsigned char sub_class;
4863 + unsigned char base_class;
4864 + unsigned char cache_line_size;
4865 + unsigned char latency_timer;
4866 + unsigned char header_type;
4867 + unsigned char bist;
4868 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4869 + unsigned char prim_bus;
4870 + unsigned char sec_bus;
4871 + unsigned char sub_bus;
4872 + unsigned char sec_lat;
4873 + unsigned char io_base;
4874 + unsigned char io_lim;
4875 + unsigned short sec_status;
4876 + unsigned short mem_base;
4877 + unsigned short mem_lim;
4878 + unsigned short pf_mem_base;
4879 + unsigned short pf_mem_lim;
4880 + unsigned long pf_mem_base_hi;
4881 + unsigned long pf_mem_lim_hi;
4882 + unsigned short io_base_hi;
4883 + unsigned short io_lim_hi;
4884 + unsigned short subsys_vendor;
4885 + unsigned short subsys_id;
4886 + unsigned long rsvd_b;
4887 + unsigned char rsvd_c;
4888 + unsigned char int_pin;
4889 + unsigned short bridge_ctrl;
4890 + unsigned char chip_ctrl;
4891 + unsigned char diag_ctrl;
4892 + unsigned short arb_ctrl;
4893 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4894 + unsigned char dev_dep[192];
4895 +} ppb_config_regs;
4896 +
4897 +
4898 +/* PCI CAPABILITY DEFINES */
4899 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
4900 +#define PCI_CAP_MSICAP_ID 0x05
4901 +#define PCI_CAP_PCIECAP_ID 0x10
4902 +
4903 +/* Data structure to define the Message Signalled Interrupt facility
4904 + * Valid for PCI and PCIE configurations */
4905 +typedef struct _pciconfig_cap_msi {
4906 + unsigned char capID;
4907 + unsigned char nextptr;
4908 + unsigned short msgctrl;
4909 + unsigned int msgaddr;
4910 +} pciconfig_cap_msi;
4911 +
4912 +/* Data structure to define the Power managment facility
4913 + * Valid for PCI and PCIE configurations */
4914 +typedef struct _pciconfig_cap_pwrmgmt {
4915 + unsigned char capID;
4916 + unsigned char nextptr;
4917 + unsigned short pme_cap;
4918 + unsigned short pme_sts_ctrl;
4919 + unsigned char pme_bridge_ext;
4920 + unsigned char data;
4921 +} pciconfig_cap_pwrmgmt;
4922 +
4923 +/* Data structure to define the PCIE capability */
4924 +typedef struct _pciconfig_cap_pcie {
4925 + unsigned char capID;
4926 + unsigned char nextptr;
4927 + unsigned short pcie_cap;
4928 + unsigned int dev_cap;
4929 + unsigned short dev_ctrl;
4930 + unsigned short dev_status;
4931 + unsigned int link_cap;
4932 + unsigned short link_ctrl;
4933 + unsigned short link_status;
4934 +} pciconfig_cap_pcie;
4935 +
4936 +/* PCIE Enhanced CAPABILITY DEFINES */
4937 +#define PCIE_EXTCFG_OFFSET 0x100
4938 +#define PCIE_ADVERRREP_CAPID 0x0001
4939 +#define PCIE_VC_CAPID 0x0002
4940 +#define PCIE_DEVSNUM_CAPID 0x0003
4941 +#define PCIE_PWRBUDGET_CAPID 0x0004
4942 +
4943 +/* Header to define the PCIE specific capabilities in the extended config space */
4944 +typedef struct _pcie_enhanced_caphdr {
4945 + unsigned short capID;
4946 + unsigned short cap_ver : 4;
4947 + unsigned short next_ptr : 12;
4948 +} pcie_enhanced_caphdr;
4949 +
4950 +
4951 +/* Everything below is BRCM HND proprietary */
4952 +
4953 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4954 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4955 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4956 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4957 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4958 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4959 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4960 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4961 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4962 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4963 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4964 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4965 +
4966 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4967 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4968 +
4969 +/* PCI_INT_STATUS */
4970 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4971 +
4972 +/* PCI_INT_MASK */
4973 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4974 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4975 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4976 +
4977 +/* PCI_SPROM_CONTROL */
4978 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4979 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4980 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4981 +
4982 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4983 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4984 +
4985 +/* PCI_CFG_CMD_STAT */
4986 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4987 +
4988 +#endif
4989 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pmon_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pmon_osl.h
4990 --- linux-2.4.32/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4991 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pmon_osl.h 2005-12-16 23:39:10.752824750 +0100
4992 @@ -0,0 +1,126 @@
4993 +/*
4994 + * MIPS PMON boot loader OS Abstraction Layer.
4995 + *
4996 + * Copyright 2005, Broadcom Corporation
4997 + * All Rights Reserved.
4998 + *
4999 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
5000 + * the contents of this file may not be disclosed to third parties, copied
5001 + * or duplicated in any form, in whole or in part, without the prior
5002 + * written permission of Broadcom Corporation.
5003 + * $Id$
5004 + */
5005 +
5006 +#ifndef _pmon_osl_h_
5007 +#define _pmon_osl_h_
5008 +
5009 +#include <typedefs.h>
5010 +#include <mips.h>
5011 +#include <string.h>
5012 +#include <utypes.h>
5013 +
5014 +extern int printf(char *fmt,...);
5015 +extern int sprintf(char *dst,char *fmt,...);
5016 +
5017 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
5018 +#define REG_MAP(pa, size) phy2k1((pa))
5019 +#define REG_UNMAP(va) /* nop */
5020 +
5021 +/* Common macros */
5022 +
5023 +#define BUSPROBE(val, addr) ((val) = *(addr))
5024 +
5025 +#define ASSERT(exp)
5026 +
5027 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
5028 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5029 +
5030 +/* kludge */
5031 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
5032 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
5033 +
5034 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
5035 +#define rreg32(r) (*(volatile uint32 *)(r))
5036 +#ifdef IL_BIGENDIAN
5037 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
5038 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
5039 +#else
5040 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
5041 +#define rreg16(r) (*(volatile uint16 *)(r))
5042 +#endif
5043 +
5044 +#include <memory.h>
5045 +#define bcopy(src, dst, len) memcpy(dst, src, len)
5046 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
5047 +#define bzero(b, len) memset(b, '\0', len)
5048 +
5049 +/* register access macros */
5050 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
5051 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
5052 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
5053 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
5054 +
5055 +#define R_SM(r) *(r)
5056 +#define W_SM(r, v) (*(r) = (v))
5057 +#define BZERO_SM(r, len) memset(r, '\0', len)
5058 +
5059 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
5060 +#define BUS_SWAP32(v) (v)
5061 +
5062 +#define OSL_DELAY(usec) delay_us(usec)
5063 +extern void delay_us(uint usec);
5064 +
5065 +#define OSL_GETCYCLES(x) ((x) = 0)
5066 +
5067 +#define osl_attach(pdev) (pdev)
5068 +#define osl_detach(osh)
5069 +
5070 +#define MALLOC(osh, size) malloc(size)
5071 +#define MFREE(osh, addr, size) free(addr)
5072 +#define MALLOCED(osh) (0)
5073 +#define MALLOC_DUMP(osh, buf, sz)
5074 +#define MALLOC_FAILED(osh)
5075 +extern void *malloc();
5076 +extern void free(void *addr);
5077 +
5078 +#define DMA_CONSISTENT_ALIGN sizeof (int)
5079 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
5080 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
5081 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
5082 +#define DMA_TX 0
5083 +#define DMA_RX 1
5084 +
5085 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
5086 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
5087 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
5088 +
5089 +struct lbuf {
5090 + struct lbuf *next; /* pointer to next lbuf on freelist */
5091 + uchar *buf; /* pointer to buffer */
5092 + uint len; /* nbytes of data */
5093 +};
5094 +
5095 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
5096 +#define PKTBUFSZ 2048
5097 +
5098 +/* packet primitives */
5099 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
5100 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
5101 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
5102 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
5103 +#define PKTHEADROOM(drv, lb) (0)
5104 +#define PKTTAILROOM(drv, lb) (0)
5105 +#define PKTNEXT(drv, lb) NULL
5106 +#define PKTSETNEXT(lb, x) ASSERT(0)
5107 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
5108 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
5109 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
5110 +#define PKTDUP(drv, lb) ASSERT(0)
5111 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
5112 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
5113 +#define PKTPRIO(lb) (0)
5114 +#define PKTSETPRIO(lb, x) do {} while (0)
5115 +extern void *et_pktget(void *drv, uint len, bool send);
5116 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
5117 +
5118 +#endif /* _pmon_osl_h_ */
5119 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/802.11.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/802.11.h
5120 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
5121 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/802.11.h 2005-12-16 23:39:10.752824750 +0100
5122 @@ -0,0 +1,930 @@
5123 +/*
5124 + * Copyright 2005, Broadcom Corporation
5125 + * All Rights Reserved.
5126 + *
5127 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5128 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5129 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5130 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5131 + *
5132 + * Fundamental types and constants relating to 802.11
5133 + *
5134 + * $Id$
5135 + */
5136 +
5137 +#ifndef _802_11_H_
5138 +#define _802_11_H_
5139 +
5140 +#ifndef _TYPEDEFS_H_
5141 +#include <typedefs.h>
5142 +#endif
5143 +
5144 +#ifndef _NET_ETHERNET_H_
5145 +#include <proto/ethernet.h>
5146 +#endif
5147 +
5148 +#include <proto/wpa.h>
5149 +
5150 +
5151 +/* enable structure packing */
5152 +#if defined(__GNUC__)
5153 +#define PACKED __attribute__((packed))
5154 +#else
5155 +#pragma pack(1)
5156 +#define PACKED
5157 +#endif
5158 +
5159 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
5160 +
5161 +/* Generic 802.11 frame constants */
5162 +#define DOT11_A3_HDR_LEN 24
5163 +#define DOT11_A4_HDR_LEN 30
5164 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
5165 +#define DOT11_FCS_LEN 4
5166 +#define DOT11_ICV_LEN 4
5167 +#define DOT11_ICV_AES_LEN 8
5168 +#define DOT11_QOS_LEN 2
5169 +
5170 +#define DOT11_KEY_INDEX_SHIFT 6
5171 +#define DOT11_IV_LEN 4
5172 +#define DOT11_IV_TKIP_LEN 8
5173 +#define DOT11_IV_AES_OCB_LEN 4
5174 +#define DOT11_IV_AES_CCM_LEN 8
5175 +
5176 +/* Includes MIC */
5177 +#define DOT11_MAX_MPDU_BODY_LEN 2304
5178 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
5179 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
5180 + DOT11_QOS_LEN + \
5181 + DOT11_IV_AES_CCM_LEN + \
5182 + DOT11_MAX_MPDU_BODY_LEN + \
5183 + DOT11_ICV_LEN + \
5184 + DOT11_FCS_LEN)
5185 +
5186 +#define DOT11_MAX_SSID_LEN 32
5187 +
5188 +/* dot11RTSThreshold */
5189 +#define DOT11_DEFAULT_RTS_LEN 2347
5190 +#define DOT11_MAX_RTS_LEN 2347
5191 +
5192 +/* dot11FragmentationThreshold */
5193 +#define DOT11_MIN_FRAG_LEN 256
5194 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
5195 +#define DOT11_DEFAULT_FRAG_LEN 2346
5196 +
5197 +/* dot11BeaconPeriod */
5198 +#define DOT11_MIN_BEACON_PERIOD 1
5199 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
5200 +
5201 +/* dot11DTIMPeriod */
5202 +#define DOT11_MIN_DTIM_PERIOD 1
5203 +#define DOT11_MAX_DTIM_PERIOD 0xFF
5204 +
5205 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
5206 +#define DOT11_LLC_SNAP_HDR_LEN 8
5207 +#define DOT11_OUI_LEN 3
5208 +struct dot11_llc_snap_header {
5209 + uint8 dsap; /* always 0xAA */
5210 + uint8 ssap; /* always 0xAA */
5211 + uint8 ctl; /* always 0x03 */
5212 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
5213 + Bridge-Tunnel: 0x00 0x00 0xF8 */
5214 + uint16 type; /* ethertype */
5215 +} PACKED;
5216 +
5217 +/* RFC1042 header used by 802.11 per 802.1H */
5218 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
5219 +
5220 +/* Generic 802.11 MAC header */
5221 +/*
5222 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
5223 + * The fields are defined such that the shorter 1, 2, and 3
5224 + * address headers just use the first k fields.
5225 + */
5226 +struct dot11_header {
5227 + uint16 fc; /* frame control */
5228 + uint16 durid; /* duration/ID */
5229 + struct ether_addr a1; /* address 1 */
5230 + struct ether_addr a2; /* address 2 */
5231 + struct ether_addr a3; /* address 3 */
5232 + uint16 seq; /* sequence control */
5233 + struct ether_addr a4; /* address 4 */
5234 +} PACKED;
5235 +
5236 +/* Control frames */
5237 +
5238 +struct dot11_rts_frame {
5239 + uint16 fc; /* frame control */
5240 + uint16 durid; /* duration/ID */
5241 + struct ether_addr ra; /* receiver address */
5242 + struct ether_addr ta; /* transmitter address */
5243 +} PACKED;
5244 +#define DOT11_RTS_LEN 16
5245 +
5246 +struct dot11_cts_frame {
5247 + uint16 fc; /* frame control */
5248 + uint16 durid; /* duration/ID */
5249 + struct ether_addr ra; /* receiver address */
5250 +} PACKED;
5251 +#define DOT11_CTS_LEN 10
5252 +
5253 +struct dot11_ack_frame {
5254 + uint16 fc; /* frame control */
5255 + uint16 durid; /* duration/ID */
5256 + struct ether_addr ra; /* receiver address */
5257 +} PACKED;
5258 +#define DOT11_ACK_LEN 10
5259 +
5260 +struct dot11_ps_poll_frame {
5261 + uint16 fc; /* frame control */
5262 + uint16 durid; /* AID */
5263 + struct ether_addr bssid; /* receiver address, STA in AP */
5264 + struct ether_addr ta; /* transmitter address */
5265 +} PACKED;
5266 +#define DOT11_PS_POLL_LEN 16
5267 +
5268 +struct dot11_cf_end_frame {
5269 + uint16 fc; /* frame control */
5270 + uint16 durid; /* duration/ID */
5271 + struct ether_addr ra; /* receiver address */
5272 + struct ether_addr bssid; /* transmitter address, STA in AP */
5273 +} PACKED;
5274 +#define DOT11_CS_END_LEN 16
5275 +
5276 +/* Management frame header */
5277 +struct dot11_management_header {
5278 + uint16 fc; /* frame control */
5279 + uint16 durid; /* duration/ID */
5280 + struct ether_addr da; /* receiver address */
5281 + struct ether_addr sa; /* transmitter address */
5282 + struct ether_addr bssid; /* BSS ID */
5283 + uint16 seq; /* sequence control */
5284 +} PACKED;
5285 +#define DOT11_MGMT_HDR_LEN 24
5286 +
5287 +/* Management frame payloads */
5288 +
5289 +struct dot11_bcn_prb {
5290 + uint32 timestamp[2];
5291 + uint16 beacon_interval;
5292 + uint16 capability;
5293 +} PACKED;
5294 +#define DOT11_BCN_PRB_LEN 12
5295 +
5296 +struct dot11_auth {
5297 + uint16 alg; /* algorithm */
5298 + uint16 seq; /* sequence control */
5299 + uint16 status; /* status code */
5300 +} PACKED;
5301 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
5302 +
5303 +struct dot11_assoc_req {
5304 + uint16 capability; /* capability information */
5305 + uint16 listen; /* listen interval */
5306 +} PACKED;
5307 +#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
5308 +
5309 +struct dot11_reassoc_req {
5310 + uint16 capability; /* capability information */
5311 + uint16 listen; /* listen interval */
5312 + struct ether_addr ap; /* Current AP address */
5313 +} PACKED;
5314 +#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
5315 +
5316 +struct dot11_assoc_resp {
5317 + uint16 capability; /* capability information */
5318 + uint16 status; /* status code */
5319 + uint16 aid; /* association ID */
5320 +} PACKED;
5321 +
5322 +struct dot11_action_measure {
5323 + uint8 category;
5324 + uint8 action;
5325 + uint8 token;
5326 + uint8 data[1];
5327 +} PACKED;
5328 +#define DOT11_ACTION_MEASURE_LEN 3
5329 +
5330 +struct dot11_action_switch_channel {
5331 + uint8 category;
5332 + uint8 action;
5333 + uint8 data[5]; /* for switch IE */
5334 +} PACKED;
5335 +
5336 +/**************
5337 + 802.11h related definitions.
5338 +**************/
5339 +typedef struct {
5340 + uint8 id;
5341 + uint8 len;
5342 + uint8 power;
5343 +} dot11_power_cnst_t;
5344 +
5345 +typedef struct {
5346 + uint8 min;
5347 + uint8 max;
5348 +} dot11_power_cap_t;
5349 +
5350 +typedef struct {
5351 + uint8 id;
5352 + uint8 len;
5353 + uint8 tx_pwr;
5354 + uint8 margin;
5355 +} dot11_tpc_rep_t;
5356 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
5357 +
5358 +typedef struct {
5359 + uint8 id;
5360 + uint8 len;
5361 + uint8 first_channel;
5362 + uint8 num_channels;
5363 +} dot11_supp_channels_t;
5364 +
5365 +/* csa mode type */
5366 +#define DOT11_CSA_MODE_ADVISORY 0
5367 +#define DOT11_CSA_MODE_NO_TX 1
5368 +struct dot11_channel_switch {
5369 + uint8 id;
5370 + uint8 len;
5371 + uint8 mode;
5372 + uint8 channel;
5373 + uint8 count;
5374 +} PACKED;
5375 +typedef struct dot11_channel_switch dot11_channel_switch_t;
5376 +
5377 +/* length of IE data, not including 2 byte header */
5378 +#define DOT11_SWITCH_IE_LEN 3
5379 +
5380 +/* 802.11h Measurement Request/Report IEs */
5381 +/* Measurement Type field */
5382 +#define DOT11_MEASURE_TYPE_BASIC 0
5383 +#define DOT11_MEASURE_TYPE_CCA 1
5384 +#define DOT11_MEASURE_TYPE_RPI 2
5385 +
5386 +/* Measurement Mode field */
5387 +
5388 +/* Measurement Request Modes */
5389 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
5390 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
5391 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
5392 +/* Measurement Report Modes */
5393 +#define DOT11_MEASURE_MODE_LATE (1<<0)
5394 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
5395 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
5396 +/* Basic Measurement Map bits */
5397 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
5398 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
5399 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
5400 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
5401 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
5402 +
5403 +typedef struct {
5404 + uint8 id;
5405 + uint8 len;
5406 + uint8 token;
5407 + uint8 mode;
5408 + uint8 type;
5409 + uint8 channel;
5410 + uint8 start_time[8];
5411 + uint16 duration;
5412 +} dot11_meas_req_t;
5413 +#define DOT11_MNG_IE_MREQ_LEN 14
5414 +/* length of Measure Request IE data not including variable len */
5415 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5416 +
5417 +struct dot11_meas_rep {
5418 + uint8 id;
5419 + uint8 len;
5420 + uint8 token;
5421 + uint8 mode;
5422 + uint8 type;
5423 + union
5424 + {
5425 + struct {
5426 + uint8 channel;
5427 + uint8 start_time[8];
5428 + uint16 duration;
5429 + uint8 map;
5430 + } PACKED basic;
5431 + uint8 data[1];
5432 + } PACKED rep;
5433 +} PACKED;
5434 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5435 +
5436 +/* length of Measure Report IE data not including variable len */
5437 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5438 +
5439 +struct dot11_meas_rep_basic {
5440 + uint8 channel;
5441 + uint8 start_time[8];
5442 + uint16 duration;
5443 + uint8 map;
5444 +} PACKED;
5445 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5446 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5447 +
5448 +struct dot11_quiet {
5449 + uint8 id;
5450 + uint8 len;
5451 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5452 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5453 + uint16 duration;/* Length of quiet period, in TU's */
5454 + uint16 offset; /* TU's offset from TBTT in Count field */
5455 +} PACKED;
5456 +typedef struct dot11_quiet dot11_quiet_t;
5457 +
5458 +typedef struct {
5459 + uint8 channel;
5460 + uint8 map;
5461 +} chan_map_tuple_t;
5462 +
5463 +typedef struct {
5464 + uint8 id;
5465 + uint8 len;
5466 + uint8 eaddr[ETHER_ADDR_LEN];
5467 + uint8 interval;
5468 + chan_map_tuple_t map[1];
5469 +} dot11_ibss_dfs_t;
5470 +
5471 +/* WME Elements */
5472 +#define WME_OUI "\x00\x50\xf2"
5473 +#define WME_VER 1
5474 +#define WME_TYPE 2
5475 +#define WME_SUBTYPE_IE 0 /* Information Element */
5476 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5477 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5478 +
5479 +/* WME Access Category Indices (ACIs) */
5480 +#define AC_BE 0 /* Best Effort */
5481 +#define AC_BK 1 /* Background */
5482 +#define AC_VI 2 /* Video */
5483 +#define AC_VO 3 /* Voice */
5484 +#define AC_MAX 4
5485 +
5486 +/* WME Information Element (IE) */
5487 +struct wme_ie {
5488 + uint8 oui[3];
5489 + uint8 type;
5490 + uint8 subtype;
5491 + uint8 version;
5492 + uint8 acinfo;
5493 +} PACKED;
5494 +typedef struct wme_ie wme_ie_t;
5495 +#define WME_IE_LEN 7
5496 +
5497 +struct wme_acparam {
5498 + uint8 ACI;
5499 + uint8 ECW;
5500 + uint16 TXOP; /* stored in network order (ls octet first) */
5501 +} PACKED;
5502 +typedef struct wme_acparam wme_acparam_t;
5503 +
5504 +/* WME Parameter Element (PE) */
5505 +struct wme_params {
5506 + uint8 oui[3];
5507 + uint8 type;
5508 + uint8 subtype;
5509 + uint8 version;
5510 + uint8 acinfo;
5511 + uint8 rsvd;
5512 + wme_acparam_t acparam[4];
5513 +} PACKED;
5514 +typedef struct wme_params wme_params_t;
5515 +#define WME_PARAMS_IE_LEN 24
5516 +
5517 +/* acinfo */
5518 +#define WME_COUNT_MASK 0x0f
5519 +/* ACI */
5520 +#define WME_AIFS_MASK 0x0f
5521 +#define WME_ACM_MASK 0x10
5522 +#define WME_ACI_MASK 0x60
5523 +#define WME_ACI_SHIFT 5
5524 +/* ECW */
5525 +#define WME_CWMIN_MASK 0x0f
5526 +#define WME_CWMAX_MASK 0xf0
5527 +#define WME_CWMAX_SHIFT 4
5528 +
5529 +#define WME_TXOP_UNITS 32
5530 +
5531 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5532 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5533 +#define WME_AC_BK_ACI_STA 0x27
5534 +#define WME_AC_BK_ECW_STA 0xA4
5535 +#define WME_AC_BK_TXOP_STA 0x0000
5536 +#define WME_AC_BE_ACI_STA 0x03
5537 +#define WME_AC_BE_ECW_STA 0xA4
5538 +#define WME_AC_BE_TXOP_STA 0x0000
5539 +#define WME_AC_VI_ACI_STA 0x42
5540 +#define WME_AC_VI_ECW_STA 0x43
5541 +#define WME_AC_VI_TXOP_STA 0x005e
5542 +#define WME_AC_VO_ACI_STA 0x62
5543 +#define WME_AC_VO_ECW_STA 0x32
5544 +#define WME_AC_VO_TXOP_STA 0x002f
5545 +
5546 +#define WME_AC_BK_ACI_AP 0x27
5547 +#define WME_AC_BK_ECW_AP 0xA4
5548 +#define WME_AC_BK_TXOP_AP 0x0000
5549 +#define WME_AC_BE_ACI_AP 0x03
5550 +#define WME_AC_BE_ECW_AP 0x64
5551 +#define WME_AC_BE_TXOP_AP 0x0000
5552 +#define WME_AC_VI_ACI_AP 0x41
5553 +#define WME_AC_VI_ECW_AP 0x43
5554 +#define WME_AC_VI_TXOP_AP 0x005e
5555 +#define WME_AC_VO_ACI_AP 0x61
5556 +#define WME_AC_VO_ECW_AP 0x32
5557 +#define WME_AC_VO_TXOP_AP 0x002f
5558 +
5559 +/* WME Traffic Specification (TSPEC) element */
5560 +#define WME_SUBTYPE_TSPEC 2
5561 +#define WME_TSPEC_HDR_LEN 2
5562 +#define WME_TSPEC_BODY_OFF 2
5563 +struct wme_tspec {
5564 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5565 + uint8 type; /* WME_TYPE */
5566 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5567 + uint8 version; /* WME_VERSION */
5568 + uint16 ts_info; /* TS Info */
5569 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5570 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5571 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5572 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5573 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5574 + uint32 service_start; /* Service Start Time (us) */
5575 + uint32 min_rate; /* Minimum Data Rate (bps) */
5576 + uint32 mean_rate; /* Mean Data Rate (bps) */
5577 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5578 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5579 + uint32 peak_rate; /* Peak Data Rate (bps) */
5580 + uint32 delay_bound; /* Delay Bound (us) */
5581 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5582 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5583 +} PACKED;
5584 +typedef struct wme_tspec wme_tspec_t;
5585 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5586 +
5587 +/* ts_info */
5588 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5589 +#define TS_INFO_PRIO_SHIFT_HI 11
5590 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5591 +#define TS_INFO_PRIO_SHIFT_LO 1
5592 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5593 +#define TS_INFO_CONTENTION_SHIFT 7
5594 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5595 +#define TS_INFO_DIRECTION_SHIFT 5
5596 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5597 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5598 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5599 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5600 +
5601 +/* nom_msdu_size */
5602 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5603 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5604 +
5605 +/* surplus_bandwidth */
5606 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5607 +#define INTEGER_SHIFT 13
5608 +#define FRACTION_MASK 0x1FFF
5609 +
5610 +/* Management Notification Frame */
5611 +struct dot11_management_notification {
5612 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5613 + uint8 action;
5614 + uint8 token;
5615 + uint8 status;
5616 + uint8 data[1]; /* Elements */
5617 +} PACKED;
5618 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5619 +
5620 +/* WME Action Codes */
5621 +#define WME_SETUP_REQUEST 0
5622 +#define WME_SETUP_RESPONSE 1
5623 +#define WME_TEARDOWN 2
5624 +
5625 +/* WME Setup Response Status Codes */
5626 +#define WME_ADMISSION_ACCEPTED 0
5627 +#define WME_INVALID_PARAMETERS 1
5628 +#define WME_ADMISSION_REFUSED 3
5629 +
5630 +/* Macro to take a pointer to a beacon or probe response
5631 + * header and return the char* pointer to the SSID info element
5632 + */
5633 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5634 +
5635 +/* Authentication frame payload constants */
5636 +#define DOT11_OPEN_SYSTEM 0
5637 +#define DOT11_SHARED_KEY 1
5638 +#define DOT11_CHALLENGE_LEN 128
5639 +
5640 +/* Frame control macros */
5641 +#define FC_PVER_MASK 0x3
5642 +#define FC_PVER_SHIFT 0
5643 +#define FC_TYPE_MASK 0xC
5644 +#define FC_TYPE_SHIFT 2
5645 +#define FC_SUBTYPE_MASK 0xF0
5646 +#define FC_SUBTYPE_SHIFT 4
5647 +#define FC_TODS 0x100
5648 +#define FC_TODS_SHIFT 8
5649 +#define FC_FROMDS 0x200
5650 +#define FC_FROMDS_SHIFT 9
5651 +#define FC_MOREFRAG 0x400
5652 +#define FC_MOREFRAG_SHIFT 10
5653 +#define FC_RETRY 0x800
5654 +#define FC_RETRY_SHIFT 11
5655 +#define FC_PM 0x1000
5656 +#define FC_PM_SHIFT 12
5657 +#define FC_MOREDATA 0x2000
5658 +#define FC_MOREDATA_SHIFT 13
5659 +#define FC_WEP 0x4000
5660 +#define FC_WEP_SHIFT 14
5661 +#define FC_ORDER 0x8000
5662 +#define FC_ORDER_SHIFT 15
5663 +
5664 +/* sequence control macros */
5665 +#define SEQNUM_SHIFT 4
5666 +#define FRAGNUM_MASK 0xF
5667 +
5668 +/* Frame Control type/subtype defs */
5669 +
5670 +/* FC Types */
5671 +#define FC_TYPE_MNG 0
5672 +#define FC_TYPE_CTL 1
5673 +#define FC_TYPE_DATA 2
5674 +
5675 +/* Management Subtypes */
5676 +#define FC_SUBTYPE_ASSOC_REQ 0
5677 +#define FC_SUBTYPE_ASSOC_RESP 1
5678 +#define FC_SUBTYPE_REASSOC_REQ 2
5679 +#define FC_SUBTYPE_REASSOC_RESP 3
5680 +#define FC_SUBTYPE_PROBE_REQ 4
5681 +#define FC_SUBTYPE_PROBE_RESP 5
5682 +#define FC_SUBTYPE_BEACON 8
5683 +#define FC_SUBTYPE_ATIM 9
5684 +#define FC_SUBTYPE_DISASSOC 10
5685 +#define FC_SUBTYPE_AUTH 11
5686 +#define FC_SUBTYPE_DEAUTH 12
5687 +#define FC_SUBTYPE_ACTION 13
5688 +
5689 +/* Control Subtypes */
5690 +#define FC_SUBTYPE_PS_POLL 10
5691 +#define FC_SUBTYPE_RTS 11
5692 +#define FC_SUBTYPE_CTS 12
5693 +#define FC_SUBTYPE_ACK 13
5694 +#define FC_SUBTYPE_CF_END 14
5695 +#define FC_SUBTYPE_CF_END_ACK 15
5696 +
5697 +/* Data Subtypes */
5698 +#define FC_SUBTYPE_DATA 0
5699 +#define FC_SUBTYPE_DATA_CF_ACK 1
5700 +#define FC_SUBTYPE_DATA_CF_POLL 2
5701 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5702 +#define FC_SUBTYPE_NULL 4
5703 +#define FC_SUBTYPE_CF_ACK 5
5704 +#define FC_SUBTYPE_CF_POLL 6
5705 +#define FC_SUBTYPE_CF_ACK_POLL 7
5706 +#define FC_SUBTYPE_QOS_DATA 8
5707 +#define FC_SUBTYPE_QOS_NULL 12
5708 +
5709 +/* type-subtype combos */
5710 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5711 +
5712 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5713 +
5714 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5715 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5716 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5717 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5718 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5719 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5720 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5721 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5722 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5723 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5724 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5725 +
5726 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5727 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5728 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5729 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5730 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5731 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5732 +
5733 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5734 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5735 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5736 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5737 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5738 +
5739 +/* QoS Control Field */
5740 +
5741 +/* 802.1D Tag */
5742 +#define QOS_PRIO_SHIFT 0
5743 +#define QOS_PRIO_MASK 0x0007
5744 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5745 +
5746 +#define QOS_TID_SHIFT 0
5747 +#define QOS_TID_MASK 0x000f
5748 +#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
5749 +
5750 +/* Ack Policy (0 means Acknowledge) */
5751 +#define QOS_ACK_SHIFT 5
5752 +#define QOS_ACK_MASK 0x0060
5753 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5754 +
5755 +/* Management Frames */
5756 +
5757 +/* Management Frame Constants */
5758 +
5759 +/* Fixed fields */
5760 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5761 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5762 +#define DOT11_MNG_BEACON_INT_LEN 2
5763 +#define DOT11_MNG_CAP_LEN 2
5764 +#define DOT11_MNG_AP_ADDR_LEN 6
5765 +#define DOT11_MNG_LISTEN_INT_LEN 2
5766 +#define DOT11_MNG_REASON_LEN 2
5767 +#define DOT11_MNG_AID_LEN 2
5768 +#define DOT11_MNG_STATUS_LEN 2
5769 +#define DOT11_MNG_TIMESTAMP_LEN 8
5770 +
5771 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5772 +#define DOT11_AID_MASK 0x3fff
5773 +
5774 +/* Reason Codes */
5775 +#define DOT11_RC_RESERVED 0
5776 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5777 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5778 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5779 + leaving (or has left) IBSS or ESS */
5780 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5781 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5782 + all currently associated stations */
5783 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5784 + nonauthenticated station */
5785 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5786 + nonassociated station */
5787 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5788 + leaving (or has left) BSS */
5789 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5790 + not authenticated with responding station */
5791 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5792 +
5793 +/* Status Codes */
5794 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5795 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5796 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5797 + in the Capability Information field */
5798 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5799 + confirm that association exists */
5800 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5801 + the scope of this standard */
5802 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5803 + specified authentication algorithm */
5804 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5805 + authentication transaction sequence number
5806 + out of expected sequence */
5807 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5808 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5809 + for next frame in sequence */
5810 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5811 + handle additional associated stations */
5812 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5813 + not supporting all of the data rates in the
5814 + BSSBasicRateSet parameter */
5815 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5816 + not supporting the Short Preamble option */
5817 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5818 + not supporting the PBCC Modulation option */
5819 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5820 + not supporting the Channel Agility option */
5821 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5822 + capability is required. */
5823 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5824 + Power Cap element is unacceptable. */
5825 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5826 + Supported Channel element is unacceptable */
5827 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5828 + not supporting the Short Slot Time option */
5829 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5830 + not supporting the ER-PBCC Modulation option */
5831 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5832 + not supporting the DSS-OFDM option */
5833 +
5834 +/* Info Elts, length of INFORMATION portion of Info Elts */
5835 +#define DOT11_MNG_DS_PARAM_LEN 1
5836 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5837 +
5838 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5839 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5840 +#define DOT11_MNG_TIM_FIXED_LEN 3
5841 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5842 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5843 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5844 +#define DOT11_MNG_TIM_PVB 3
5845 +
5846 +/* TLV defines */
5847 +#define TLV_TAG_OFF 0
5848 +#define TLV_LEN_OFF 1
5849 +#define TLV_HDR_LEN 2
5850 +#define TLV_BODY_OFF 2
5851 +
5852 +/* Management Frame Information Element IDs */
5853 +#define DOT11_MNG_SSID_ID 0
5854 +#define DOT11_MNG_RATES_ID 1
5855 +#define DOT11_MNG_FH_PARMS_ID 2
5856 +#define DOT11_MNG_DS_PARMS_ID 3
5857 +#define DOT11_MNG_CF_PARMS_ID 4
5858 +#define DOT11_MNG_TIM_ID 5
5859 +#define DOT11_MNG_IBSS_PARMS_ID 6
5860 +#define DOT11_MNG_COUNTRY_ID 7
5861 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5862 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5863 +#define DOT11_MNG_REQUEST_ID 10
5864 +#define DOT11_MNG_CHALLENGE_ID 16
5865 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5866 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5867 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5868 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5869 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5870 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5871 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5872 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5873 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5874 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5875 +#define DOT11_MNG_ERP_ID 42
5876 +#define DOT11_MNG_NONERP_ID 47
5877 +#ifdef BCMWPA2
5878 +#define DOT11_MNG_RSN_ID 48
5879 +#endif /* BCMWPA2 */
5880 +#define DOT11_MNG_EXT_RATES_ID 50
5881 +#define DOT11_MNG_WPA_ID 221
5882 +#define DOT11_MNG_PROPR_ID 221
5883 +
5884 +/* ERP info element bit values */
5885 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5886 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5887 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5888 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5889 +
5890 +/* Capability Information Field */
5891 +#define DOT11_CAP_ESS 0x0001
5892 +#define DOT11_CAP_IBSS 0x0002
5893 +#define DOT11_CAP_POLLABLE 0x0004
5894 +#define DOT11_CAP_POLL_RQ 0x0008
5895 +#define DOT11_CAP_PRIVACY 0x0010
5896 +#define DOT11_CAP_SHORT 0x0020
5897 +#define DOT11_CAP_PBCC 0x0040
5898 +#define DOT11_CAP_AGILITY 0x0080
5899 +#define DOT11_CAP_SPECTRUM 0x0100
5900 +#define DOT11_CAP_SHORTSLOT 0x0400
5901 +#define DOT11_CAP_CCK_OFDM 0x2000
5902 +
5903 +/* Action Frame Constants */
5904 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5905 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5906 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5907 +
5908 +#define DOT11_ACTION_ID_M_REQ 0
5909 +#define DOT11_ACTION_ID_M_REP 1
5910 +#define DOT11_ACTION_ID_TPC_REQ 2
5911 +#define DOT11_ACTION_ID_TPC_REP 3
5912 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5913 +
5914 +/* MLME Enumerations */
5915 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5916 +#define DOT11_BSSTYPE_INDEPENDENT 1
5917 +#define DOT11_BSSTYPE_ANY 2
5918 +#define DOT11_SCANTYPE_ACTIVE 0
5919 +#define DOT11_SCANTYPE_PASSIVE 1
5920 +
5921 +/* 802.11 A PHY constants */
5922 +#define APHY_SLOT_TIME 9
5923 +#define APHY_SIFS_TIME 16
5924 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5925 +#define APHY_PREAMBLE_TIME 16
5926 +#define APHY_SIGNAL_TIME 4
5927 +#define APHY_SYMBOL_TIME 4
5928 +#define APHY_SERVICE_NBITS 16
5929 +#define APHY_TAIL_NBITS 6
5930 +#define APHY_CWMIN 15
5931 +
5932 +/* 802.11 B PHY constants */
5933 +#define BPHY_SLOT_TIME 20
5934 +#define BPHY_SIFS_TIME 10
5935 +#define BPHY_DIFS_TIME 50
5936 +#define BPHY_PLCP_TIME 192
5937 +#define BPHY_PLCP_SHORT_TIME 96
5938 +#define BPHY_CWMIN 31
5939 +
5940 +/* 802.11 G constants */
5941 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5942 +
5943 +#define PHY_CWMAX 1023
5944 +
5945 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5946 +
5947 +/* dot11Counters Table - 802.11 spec., Annex D */
5948 +typedef struct d11cnt {
5949 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5950 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5951 + uint32 txfail; /* dot11FailedCount */
5952 + uint32 txretry; /* dot11RetryCount */
5953 + uint32 txretrie; /* dot11MultipleRetryCount */
5954 + uint32 rxdup; /* dot11FrameduplicateCount */
5955 + uint32 txrts; /* dot11RTSSuccessCount */
5956 + uint32 txnocts; /* dot11RTSFailureCount */
5957 + uint32 txnoack; /* dot11ACKFailureCount */
5958 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5959 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5960 + uint32 rxcrc; /* dot11FCSErrorCount */
5961 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5962 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5963 +} d11cnt_t;
5964 +
5965 +/* BRCM OUI */
5966 +#define BRCM_OUI "\x00\x10\x18"
5967 +
5968 +/* BRCM info element */
5969 +struct brcm_ie {
5970 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5971 + uchar len;
5972 + uchar oui[3];
5973 + uchar ver;
5974 + uchar assoc; /* # of assoc STAs */
5975 + uchar flags; /* misc flags */
5976 +} PACKED;
5977 +#define BRCM_IE_LEN 8
5978 +typedef struct brcm_ie brcm_ie_t;
5979 +#define BRCM_IE_VER 2
5980 +#define BRCM_IE_LEGACY_AES_VER 1
5981 +
5982 +/* brcm_ie flags */
5983 +#define BRF_ABCAP 0x1 /* afterburner capable */
5984 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5985 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5986 +#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
5987 +#define BRF_ABCOUNTER_SHIFT 4
5988 +
5989 +#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
5990 +#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
5991 +
5992 +
5993 +/* OUI for BRCM proprietary IE */
5994 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5995 +
5996 +/* Vendor IE structure */
5997 +struct vndr_ie {
5998 + uchar id;
5999 + uchar len;
6000 + uchar oui [3];
6001 + uchar data [1]; /* Variable size data */
6002 +}PACKED;
6003 +typedef struct vndr_ie vndr_ie_t;
6004 +
6005 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
6006 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
6007 +#define VNDR_IE_MAX_LEN 256
6008 +
6009 +/* WPA definitions */
6010 +#define WPA_VERSION 1
6011 +#define WPA_OUI "\x00\x50\xF2"
6012 +
6013 +#ifdef BCMWPA2
6014 +#define WPA2_VERSION 1
6015 +#define WPA2_VERSION_LEN 2
6016 +#define WPA2_OUI "\x00\x0F\xAC"
6017 +#endif /* BCMWPA2 */
6018 +
6019 +#define WPA_OUI_LEN 3
6020 +
6021 +/* RSN authenticated key managment suite */
6022 +#define RSN_AKM_NONE 0 /* None (IBSS) */
6023 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
6024 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
6025 +
6026 +
6027 +/* Key related defines */
6028 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
6029 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
6030 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
6031 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
6032 +
6033 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
6034 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
6035 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
6036 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
6037 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
6038 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
6039 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
6040 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
6041 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
6042 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
6043 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
6044 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
6045 +#define AES_KEY_SIZE 16 /* size of AES key */
6046 +
6047 +#undef PACKED
6048 +#if !defined(__GNUC__)
6049 +#pragma pack()
6050 +#endif
6051 +
6052 +#endif /* _802_11_H_ */
6053 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmeth.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h
6054 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
6055 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-12-16 23:39:10.756825000 +0100
6056 @@ -0,0 +1,103 @@
6057 +/*
6058 + * Broadcom Ethernettype protocol definitions
6059 + *
6060 + * Copyright 2005, Broadcom Corporation
6061 + * All Rights Reserved.
6062 + *
6063 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6064 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6065 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6066 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6067 + *
6068 + */
6069 +
6070 +/*
6071 + * Broadcom Ethernet protocol defines
6072 + *
6073 + */
6074 +
6075 +#ifndef _BCMETH_H_
6076 +#define _BCMETH_H_
6077 +
6078 +/* enable structure packing */
6079 +#if defined(__GNUC__)
6080 +#define PACKED __attribute__((packed))
6081 +#else
6082 +#pragma pack(1)
6083 +#define PACKED
6084 +#endif
6085 +
6086 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
6087 +
6088 +/*
6089 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
6090 + * in one of two formats: (only subtypes 32768-65535 are in use now)
6091 + *
6092 + * subtypes 0-32767:
6093 + * 8 bit subtype (0-127)
6094 + * 8 bit length in bytes (0-255)
6095 + *
6096 + * subtypes 32768-65535:
6097 + * 16 bit big-endian subtype
6098 + * 16 bit big-endian length in bytes (0-65535)
6099 + *
6100 + * length is the number of additional bytes beyond the 4 or 6 byte header
6101 + *
6102 + * Reserved values:
6103 + * 0 reserved
6104 + * 5-15 reserved for iLine protocol assignments
6105 + * 17-126 reserved, assignable
6106 + * 127 reserved
6107 + * 32768 reserved
6108 + * 32769-65534 reserved, assignable
6109 + * 65535 reserved
6110 + */
6111 +
6112 +/*
6113 + * While adding the subtypes and their specific processing code make sure
6114 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
6115 + */
6116 +
6117 +#define BCMILCP_SUBTYPE_RATE 1
6118 +#define BCMILCP_SUBTYPE_LINK 2
6119 +#define BCMILCP_SUBTYPE_CSA 3
6120 +#define BCMILCP_SUBTYPE_LARQ 4
6121 +#define BCMILCP_SUBTYPE_VENDOR 5
6122 +#define BCMILCP_SUBTYPE_FLH 17
6123 +
6124 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
6125 +#define BCMILCP_SUBTYPE_CERT 32770
6126 +#define BCMILCP_SUBTYPE_SES 32771
6127 +
6128 +
6129 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
6130 +#define BCMILCP_BCM_SUBTYPE_EVENT 1
6131 +#define BCMILCP_BCM_SUBTYPE_SES 2
6132 +/*
6133 +The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
6134 +within BCMILCP_BCM_SUBTYPE_EVENT type messages
6135 +*/
6136 +/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
6137 +
6138 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
6139 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
6140 +
6141 +/* These fields are stored in network order */
6142 +typedef struct bcmeth_hdr
6143 +{
6144 + uint16 subtype; /* Vendor specific..32769*/
6145 + uint16 length;
6146 + uint8 version; /* Version is 0*/
6147 + uint8 oui[3]; /* Broadcom OUI*/
6148 + /* user specific Data */
6149 + uint16 usr_subtype;
6150 +} PACKED bcmeth_hdr_t;
6151 +
6152 +
6153 +
6154 +#undef PACKED
6155 +#if !defined(__GNUC__)
6156 +#pragma pack()
6157 +#endif
6158 +
6159 +#endif
6160 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmip.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmip.h
6161 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
6162 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/bcmip.h 2005-12-16 23:39:10.756825000 +0100
6163 @@ -0,0 +1,42 @@
6164 +/*
6165 + * Copyright 2005, Broadcom Corporation
6166 + * All Rights Reserved.
6167 + *
6168 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
6169 + * the contents of this file may not be disclosed to third parties, copied
6170 + * or duplicated in any form, in whole or in part, without the prior
6171 + * written permission of Broadcom Corporation.
6172 + *
6173 + * Fundamental constants relating to IP Protocol
6174 + *
6175 + * $Id$
6176 + */
6177 +
6178 +#ifndef _bcmip_h_
6179 +#define _bcmip_h_
6180 +
6181 +/* IP header */
6182 +#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
6183 +#define IPV4_TOS_OFFSET 1 /* TOS offset */
6184 +#define IPV4_PROT_OFFSET 9 /* protocol type offset */
6185 +#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
6186 +#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
6187 +#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
6188 +
6189 +#define IPV4_VER_MASK 0xf0
6190 +#define IPV4_IHL_MASK 0x0f
6191 +
6192 +#define IPV4_PROT_UDP 17 /* UDP protocol type */
6193 +
6194 +#define IPV4_ADDR_LEN 4 /* IP v4 address length */
6195 +
6196 +#define IPV4_VER_NUM 0x40 /* IP v4 version number */
6197 +
6198 +/* NULL IP address check */
6199 +#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
6200 + ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
6201 +
6202 +#define IPV4_ADDR_STR_LEN 16
6203 +
6204 +#endif /* #ifndef _bcmip_h_ */
6205 +
6206 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/ethernet.h
6207 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
6208 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-16 23:39:10.756825000 +0100
6209 @@ -0,0 +1,169 @@
6210 +/*******************************************************************************
6211 + * $Id$
6212 + * Copyright 2005, Broadcom Corporation
6213 + * All Rights Reserved.
6214 + *
6215 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6216 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6217 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6218 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6219 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
6220 + ******************************************************************************/
6221 +
6222 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
6223 +#define _NET_ETHERNET_H_
6224 +
6225 +#ifndef _TYPEDEFS_H_
6226 +#include "typedefs.h"
6227 +#endif
6228 +
6229 +/* enable structure packing */
6230 +#if defined(__GNUC__)
6231 +#define PACKED __attribute__((packed))
6232 +#else
6233 +#pragma pack(1)
6234 +#define PACKED
6235 +#endif
6236 +
6237 +/*
6238 + * The number of bytes in an ethernet (MAC) address.
6239 + */
6240 +#define ETHER_ADDR_LEN 6
6241 +
6242 +/*
6243 + * The number of bytes in the type field.
6244 + */
6245 +#define ETHER_TYPE_LEN 2
6246 +
6247 +/*
6248 + * The number of bytes in the trailing CRC field.
6249 + */
6250 +#define ETHER_CRC_LEN 4
6251 +
6252 +/*
6253 + * The length of the combined header.
6254 + */
6255 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
6256 +
6257 +/*
6258 + * The minimum packet length.
6259 + */
6260 +#define ETHER_MIN_LEN 64
6261 +
6262 +/*
6263 + * The minimum packet user data length.
6264 + */
6265 +#define ETHER_MIN_DATA 46
6266 +
6267 +/*
6268 + * The maximum packet length.
6269 + */
6270 +#define ETHER_MAX_LEN 1518
6271 +
6272 +/*
6273 + * The maximum packet user data length.
6274 + */
6275 +#define ETHER_MAX_DATA 1500
6276 +
6277 +/* ether types */
6278 +#define ETHER_TYPE_IP 0x0800 /* IP */
6279 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
6280 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
6281 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
6282 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
6283 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
6284 +
6285 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
6286 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
6287 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
6288 +
6289 +/* ether header */
6290 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
6291 +#define ETHER_SRC_OFFSET 6 /* src address offset */
6292 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
6293 +
6294 +/*
6295 + * A macro to validate a length with
6296 + */
6297 +#define ETHER_IS_VALID_LEN(foo) \
6298 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
6299 +
6300 +
6301 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
6302 +/*
6303 + * Structure of a 10Mb/s Ethernet header.
6304 + */
6305 +struct ether_header {
6306 + uint8 ether_dhost[ETHER_ADDR_LEN];
6307 + uint8 ether_shost[ETHER_ADDR_LEN];
6308 + uint16 ether_type;
6309 +} PACKED;
6310 +
6311 +/*
6312 + * Structure of a 48-bit Ethernet address.
6313 + */
6314 +struct ether_addr {
6315 + uint8 octet[ETHER_ADDR_LEN];
6316 +} PACKED;
6317 +#endif
6318 +
6319 +/*
6320 + * Takes a pointer, sets locally admininistered
6321 + * address bit in the 48-bit Ethernet address.
6322 + */
6323 +#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
6324 + (((uint8 *)(ea))[0] | 2) )
6325 +
6326 +/*
6327 + * Takes a pointer, returns true if a 48-bit multicast address
6328 + * (including broadcast, since it is all ones)
6329 + */
6330 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
6331 +
6332 +
6333 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
6334 +#define ether_cmp(a, b) ( \
6335 + !(((short*)a)[0] == ((short*)b)[0]) | \
6336 + !(((short*)a)[1] == ((short*)b)[1]) | \
6337 + !(((short*)a)[2] == ((short*)b)[2]))
6338 +
6339 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
6340 +#define ether_copy(s, d) { \
6341 + ((short*)d)[0] = ((short*)s)[0]; \
6342 + ((short*)d)[1] = ((short*)s)[1]; \
6343 + ((short*)d)[2] = ((short*)s)[2]; }
6344 +
6345 +/*
6346 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
6347 + */
6348 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
6349 + ((uint8 *)(ea))[1] & \
6350 + ((uint8 *)(ea))[2] & \
6351 + ((uint8 *)(ea))[3] & \
6352 + ((uint8 *)(ea))[4] & \
6353 + ((uint8 *)(ea))[5]) == 0xff)
6354 +
6355 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
6356 +
6357 +/*
6358 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
6359 + */
6360 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
6361 + ((uint8 *)(ea))[1] | \
6362 + ((uint8 *)(ea))[2] | \
6363 + ((uint8 *)(ea))[3] | \
6364 + ((uint8 *)(ea))[4] | \
6365 + ((uint8 *)(ea))[5]) == 0)
6366 +
6367 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
6368 +#define DSCP_MASK 0xFC /* upper 6 bits */
6369 +#define DSCP_SHIFT 2
6370 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
6371 +#define DSCP_WME_PRI_SHIFT 5
6372 +
6373 +#undef PACKED
6374 +#if !defined(__GNUC__)
6375 +#pragma pack()
6376 +#endif
6377 +
6378 +#endif /* _NET_ETHERNET_H_ */
6379 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/vlan.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/vlan.h
6380 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
6381 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/vlan.h 2005-12-16 23:39:10.756825000 +0100
6382 @@ -0,0 +1,50 @@
6383 +/*
6384 + * 802.1Q VLAN protocol definitions
6385 + *
6386 + * Copyright 2005, Broadcom Corporation
6387 + * All Rights Reserved.
6388 + *
6389 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6390 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6391 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6392 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6393 + *
6394 + * $Id$
6395 + */
6396 +
6397 +#ifndef _vlan_h_
6398 +#define _vlan_h_
6399 +
6400 +/* enable structure packing */
6401 +#if defined(__GNUC__)
6402 +#define PACKED __attribute__((packed))
6403 +#else
6404 +#pragma pack(1)
6405 +#define PACKED
6406 +#endif
6407 +
6408 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
6409 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
6410 +#define VLAN_PRI_SHIFT 13 /* user priority */
6411 +
6412 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
6413 +
6414 +#define VLAN_TAG_LEN 4
6415 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
6416 +
6417 +struct ethervlan_header {
6418 + uint8 ether_dhost[ETHER_ADDR_LEN];
6419 + uint8 ether_shost[ETHER_ADDR_LEN];
6420 + uint16 vlan_type; /* 0x8100 */
6421 + uint16 vlan_tag; /* priority, cfi and vid */
6422 + uint16 ether_type;
6423 +};
6424 +
6425 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
6426 +
6427 +#undef PACKED
6428 +#if !defined(__GNUC__)
6429 +#pragma pack()
6430 +#endif
6431 +
6432 +#endif /* _vlan_h_ */
6433 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/proto/wpa.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/wpa.h
6434 --- linux-2.4.32/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
6435 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/proto/wpa.h 2005-12-16 23:39:10.756825000 +0100
6436 @@ -0,0 +1,140 @@
6437 +/*
6438 + * Fundamental types and constants relating to WPA
6439 + *
6440 + * Copyright 2005, Broadcom Corporation
6441 + * All Rights Reserved.
6442 + *
6443 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6444 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6445 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6446 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6447 + *
6448 + * $Id$
6449 + */
6450 +
6451 +#ifndef _proto_wpa_h_
6452 +#define _proto_wpa_h_
6453 +
6454 +#include <typedefs.h>
6455 +#include <proto/ethernet.h>
6456 +
6457 +/* enable structure packing */
6458 +#if defined(__GNUC__)
6459 +#define PACKED __attribute__((packed))
6460 +#else
6461 +#pragma pack(1)
6462 +#define PACKED
6463 +#endif
6464 +
6465 +/* Reason Codes */
6466 +
6467 +/* 10 and 11 are from TGh. */
6468 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
6469 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
6470 +/* 12 is unused */
6471 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
6472 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
6473 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
6474 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
6475 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
6476 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
6477 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6478 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6479 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6480 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6481 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6482 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6483 +
6484 +#define WPA2_PMKID_LEN 16
6485 +
6486 +/* WPA IE fixed portion */
6487 +typedef struct
6488 +{
6489 + uint8 tag; /* TAG */
6490 + uint8 length; /* TAG length */
6491 + uint8 oui[3]; /* IE OUI */
6492 + uint8 oui_type; /* OUI type */
6493 + struct {
6494 + uint8 low;
6495 + uint8 high;
6496 + } PACKED version; /* IE version */
6497 +} PACKED wpa_ie_fixed_t;
6498 +#define WPA_IE_OUITYPE_LEN 4
6499 +#define WPA_IE_FIXED_LEN 8
6500 +#define WPA_IE_TAG_FIXED_LEN 6
6501 +
6502 +typedef struct {
6503 + uint8 tag; /* TAG */
6504 + uint8 length; /* TAG length */
6505 + struct {
6506 + uint8 low;
6507 + uint8 high;
6508 + } PACKED version; /* IE version */
6509 +} PACKED wpa_rsn_ie_fixed_t;
6510 +#define WPA_RSN_IE_FIXED_LEN 4
6511 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6512 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6513 +
6514 +/* WPA suite/multicast suite */
6515 +typedef struct
6516 +{
6517 + uint8 oui[3];
6518 + uint8 type;
6519 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6520 +#define WPA_SUITE_LEN 4
6521 +
6522 +/* WPA unicast suite list/key management suite list */
6523 +typedef struct
6524 +{
6525 + struct {
6526 + uint8 low;
6527 + uint8 high;
6528 + } PACKED count;
6529 + wpa_suite_t list[1];
6530 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6531 +#define WPA_IE_SUITE_COUNT_LEN 2
6532 +typedef struct
6533 +{
6534 + struct {
6535 + uint8 low;
6536 + uint8 high;
6537 + } PACKED count;
6538 + wpa_pmkid_t list[1];
6539 +} PACKED wpa_pmkid_list_t;
6540 +
6541 +/* WPA cipher suites */
6542 +#define WPA_CIPHER_NONE 0 /* None */
6543 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6544 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6545 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6546 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6547 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6548 +
6549 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6550 + (cipher) == WPA_CIPHER_WEP_40 || \
6551 + (cipher) == WPA_CIPHER_WEP_104 || \
6552 + (cipher) == WPA_CIPHER_TKIP || \
6553 + (cipher) == WPA_CIPHER_AES_OCB || \
6554 + (cipher) == WPA_CIPHER_AES_CCM)
6555 +
6556 +/* WPA TKIP countermeasures parameters */
6557 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6558 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6559 +
6560 +/* WPA capabilities defined in 802.11i */
6561 +#define WPA_CAP_4_REPLAY_CNTRS 2
6562 +#define WPA_CAP_16_REPLAY_CNTRS 3
6563 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6564 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6565 +
6566 +/* WPA Specific defines */
6567 +#define WPA_CAP_LEN 2
6568 +
6569 +#define WPA_CAP_WPA2_PREAUTH 1
6570 +
6571 +#undef PACKED
6572 +#if !defined(__GNUC__)
6573 +#pragma pack()
6574 +#endif
6575 +
6576 +#endif /* _proto_wpa_h_ */
6577 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/rts/crc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/rts/crc.h
6578 --- linux-2.4.32/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6579 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/rts/crc.h 2005-12-16 23:39:10.928835750 +0100
6580 @@ -0,0 +1,69 @@
6581 +/*******************************************************************************
6582 + * $Id$
6583 + * Copyright 2005, Broadcom Corporation
6584 + * All Rights Reserved.
6585 + *
6586 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6587 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6588 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6589 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6590 + * crc.h - a function to compute crc for iLine10 headers
6591 + ******************************************************************************/
6592 +
6593 +#ifndef _RTS_CRC_H_
6594 +#define _RTS_CRC_H_ 1
6595 +
6596 +#include "typedefs.h"
6597 +
6598 +#ifdef __cplusplus
6599 +extern "C" {
6600 +#endif
6601 +
6602 +
6603 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6604 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6605 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6606 +
6607 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6608 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6609 +
6610 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6611 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6612 +
6613 +void hcs(uint8 *, uint);
6614 +uint8 crc8(uint8 *, uint, uint8);
6615 +uint16 crc16(uint8 *, uint, uint16);
6616 +uint32 crc32(uint8 *, uint, uint32);
6617 +
6618 +/* macros for common usage */
6619 +
6620 +#define APPEND_CRC8(pbytes, nbytes) \
6621 +do { \
6622 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6623 + (pbytes)[(nbytes)] = tmp; \
6624 + (nbytes) += 1; \
6625 +} while (0)
6626 +
6627 +#define APPEND_CRC16(pbytes, nbytes) \
6628 +do { \
6629 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6630 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6631 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6632 + (nbytes) += 2; \
6633 +} while (0)
6634 +
6635 +#define APPEND_CRC32(pbytes, nbytes) \
6636 +do { \
6637 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6638 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6639 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6640 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6641 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6642 + (nbytes) += 4; \
6643 +} while (0)
6644 +
6645 +#ifdef __cplusplus
6646 +}
6647 +#endif
6648 +
6649 +#endif /* _RTS_CRC_H_ */
6650 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h
6651 --- linux-2.4.32/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6652 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbchipc.h 2005-12-16 23:39:10.932836000 +0100
6653 @@ -0,0 +1,440 @@
6654 +/*
6655 + * SiliconBackplane Chipcommon core hardware definitions.
6656 + *
6657 + * The chipcommon core provides chip identification, SB control,
6658 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6659 + * gpio interface, extbus, and support for serial and parallel flashes.
6660 + *
6661 + * $Id$
6662 + * Copyright 2005, Broadcom Corporation
6663 + * All Rights Reserved.
6664 + *
6665 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6666 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6667 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6668 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6669 + *
6670 + */
6671 +
6672 +#ifndef _SBCHIPC_H
6673 +#define _SBCHIPC_H
6674 +
6675 +
6676 +#ifndef _LANGUAGE_ASSEMBLY
6677 +
6678 +/* cpp contortions to concatenate w/arg prescan */
6679 +#ifndef PAD
6680 +#define _PADLINE(line) pad ## line
6681 +#define _XSTR(line) _PADLINE(line)
6682 +#define PAD _XSTR(__LINE__)
6683 +#endif /* PAD */
6684 +
6685 +typedef volatile struct {
6686 + uint32 chipid; /* 0x0 */
6687 + uint32 capabilities;
6688 + uint32 corecontrol; /* corerev >= 1 */
6689 + uint32 bist;
6690 +
6691 + /* OTP */
6692 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6693 + uint32 otpcontrol;
6694 + uint32 otpprog;
6695 + uint32 PAD;
6696 +
6697 + /* Interrupt control */
6698 + uint32 intstatus; /* 0x20 */
6699 + uint32 intmask;
6700 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6701 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6702 +
6703 + /* Jtag Master */
6704 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6705 + uint32 jtagir;
6706 + uint32 jtagdr;
6707 + uint32 jtagctrl;
6708 +
6709 + /* serial flash interface registers */
6710 + uint32 flashcontrol; /* 0x40 */
6711 + uint32 flashaddress;
6712 + uint32 flashdata;
6713 + uint32 PAD[1];
6714 +
6715 + /* Silicon backplane configuration broadcast control */
6716 + uint32 broadcastaddress; /* 0x50 */
6717 + uint32 broadcastdata;
6718 + uint32 PAD[2];
6719 +
6720 + /* gpio - cleared only by power-on-reset */
6721 + uint32 gpioin; /* 0x60 */
6722 + uint32 gpioout;
6723 + uint32 gpioouten;
6724 + uint32 gpiocontrol;
6725 + uint32 gpiointpolarity;
6726 + uint32 gpiointmask;
6727 + uint32 PAD[2];
6728 +
6729 + /* Watchdog timer */
6730 + uint32 watchdog; /* 0x80 */
6731 + uint32 PAD[1];
6732 +
6733 + /*GPIO based LED powersave registers corerev >= 16*/
6734 + uint32 gpiotimerval; /*0x88 */
6735 + uint32 gpiotimeroutmask;
6736 +
6737 + /* clock control */
6738 + uint32 clockcontrol_n; /* 0x90 */
6739 + uint32 clockcontrol_sb; /* aka m0 */
6740 + uint32 clockcontrol_pci; /* aka m1 */
6741 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6742 + uint32 clockcontrol_mips; /* aka m3 */
6743 + uint32 clkdiv; /* corerev >= 3 */
6744 + uint32 PAD[2];
6745 +
6746 + /* pll delay registers (corerev >= 4) */
6747 + uint32 pll_on_delay; /* 0xb0 */
6748 + uint32 fref_sel_delay;
6749 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6750 + uint32 PAD[1];
6751 +
6752 + /* Instaclock registers (corerev >= 10) */
6753 + uint32 system_clk_ctl; /* 0xc0 */
6754 + uint32 clkstatestretch;
6755 + uint32 PAD[14];
6756 +
6757 + /* ExtBus control registers (corerev >= 3) */
6758 + uint32 pcmcia_config; /* 0x100 */
6759 + uint32 pcmcia_memwait;
6760 + uint32 pcmcia_attrwait;
6761 + uint32 pcmcia_iowait;
6762 + uint32 ide_config;
6763 + uint32 ide_memwait;
6764 + uint32 ide_attrwait;
6765 + uint32 ide_iowait;
6766 + uint32 prog_config;
6767 + uint32 prog_waitcount;
6768 + uint32 flash_config;
6769 + uint32 flash_waitcount;
6770 + uint32 PAD[116];
6771 +
6772 + /* uarts */
6773 + uint8 uart0data; /* 0x300 */
6774 + uint8 uart0imr;
6775 + uint8 uart0fcr;
6776 + uint8 uart0lcr;
6777 + uint8 uart0mcr;
6778 + uint8 uart0lsr;
6779 + uint8 uart0msr;
6780 + uint8 uart0scratch;
6781 + uint8 PAD[248]; /* corerev >= 1 */
6782 +
6783 + uint8 uart1data; /* 0x400 */
6784 + uint8 uart1imr;
6785 + uint8 uart1fcr;
6786 + uint8 uart1lcr;
6787 + uint8 uart1mcr;
6788 + uint8 uart1lsr;
6789 + uint8 uart1msr;
6790 + uint8 uart1scratch;
6791 +} chipcregs_t;
6792 +
6793 +#endif /* _LANGUAGE_ASSEMBLY */
6794 +
6795 +#define CC_CHIPID 0
6796 +#define CC_CAPABILITIES 4
6797 +#define CC_JTAGCMD 0x30
6798 +#define CC_JTAGIR 0x34
6799 +#define CC_JTAGDR 0x38
6800 +#define CC_JTAGCTRL 0x3c
6801 +#define CC_WATCHDOG 0x80
6802 +#define CC_CLKC_N 0x90
6803 +#define CC_CLKC_M0 0x94
6804 +#define CC_CLKC_M1 0x98
6805 +#define CC_CLKC_M2 0x9c
6806 +#define CC_CLKC_M3 0xa0
6807 +#define CC_CLKDIV 0xa4
6808 +#define CC_SYS_CLK_CTL 0xc0
6809 +#define CC_OTP 0x800
6810 +
6811 +/* chipid */
6812 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6813 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6814 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6815 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6816 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6817 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6818 +#define CID_CC_SHIFT 24
6819 +
6820 +/* capabilities */
6821 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6822 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6823 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6824 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6825 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6826 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6827 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6828 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6829 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6830 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6831 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6832 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6833 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6834 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6835 +
6836 +/* PLL type */
6837 +#define PLL_NONE 0x00000000
6838 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6839 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6840 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6841 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6842 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6843 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6844 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6845 +
6846 +/* corecontrol */
6847 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6848 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6849 +
6850 +/* Fields in the otpstatus register */
6851 +#define OTPS_PROGFAIL 0x80000000
6852 +#define OTPS_PROTECT 0x00000007
6853 +#define OTPS_HW_PROTECT 0x00000001
6854 +#define OTPS_SW_PROTECT 0x00000002
6855 +#define OTPS_CID_PROTECT 0x00000004
6856 +
6857 +/* Fields in the otpcontrol register */
6858 +#define OTPC_RECWAIT 0xff000000
6859 +#define OTPC_PROGWAIT 0x00ffff00
6860 +#define OTPC_PRW_SHIFT 8
6861 +#define OTPC_MAXFAIL 0x00000038
6862 +#define OTPC_VSEL 0x00000006
6863 +#define OTPC_SELVL 0x00000001
6864 +
6865 +/* Fields in otpprog */
6866 +#define OTPP_COL_MASK 0x000000ff
6867 +#define OTPP_ROW_MASK 0x0000ff00
6868 +#define OTPP_ROW_SHIFT 8
6869 +#define OTPP_READERR 0x10000000
6870 +#define OTPP_VALUE 0x20000000
6871 +#define OTPP_VALUE_SHIFT 29
6872 +#define OTPP_READ 0x40000000
6873 +#define OTPP_START 0x80000000
6874 +#define OTPP_BUSY 0x80000000
6875 +
6876 +/* jtagcmd */
6877 +#define JCMD_START 0x80000000
6878 +#define JCMD_BUSY 0x80000000
6879 +#define JCMD_PAUSE 0x40000000
6880 +#define JCMD0_ACC_MASK 0x0000f000
6881 +#define JCMD0_ACC_IRDR 0x00000000
6882 +#define JCMD0_ACC_DR 0x00001000
6883 +#define JCMD0_ACC_IR 0x00002000
6884 +#define JCMD0_ACC_RESET 0x00003000
6885 +#define JCMD0_ACC_IRPDR 0x00004000
6886 +#define JCMD0_ACC_PDR 0x00005000
6887 +#define JCMD0_IRW_MASK 0x00000f00
6888 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6889 +#define JCMD_ACC_IRDR 0x00000000
6890 +#define JCMD_ACC_DR 0x00010000
6891 +#define JCMD_ACC_IR 0x00020000
6892 +#define JCMD_ACC_RESET 0x00030000
6893 +#define JCMD_ACC_IRPDR 0x00040000
6894 +#define JCMD_ACC_PDR 0x00050000
6895 +#define JCMD_IRW_MASK 0x00001f00
6896 +#define JCMD_IRW_SHIFT 8
6897 +#define JCMD_DRW_MASK 0x0000003f
6898 +
6899 +/* jtagctrl */
6900 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6901 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6902 +#define JCTRL_EN 1 /* Enable Jtag master */
6903 +
6904 +/* Fields in clkdiv */
6905 +#define CLKD_SFLASH 0x0f000000
6906 +#define CLKD_SFLASH_SHIFT 24
6907 +#define CLKD_OTP 0x000f0000
6908 +#define CLKD_OTP_SHIFT 16
6909 +#define CLKD_JTAG 0x00000f00
6910 +#define CLKD_JTAG_SHIFT 8
6911 +#define CLKD_UART 0x000000ff
6912 +
6913 +/* intstatus/intmask */
6914 +#define CI_GPIO 0x00000001 /* gpio intr */
6915 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6916 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6917 +
6918 +/* slow_clk_ctl */
6919 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6920 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6921 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6922 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6923 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6924 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6925 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6926 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6927 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6928 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6929 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6930 +#define SCC_CD_SHIFT 16
6931 +
6932 +/* system_clk_ctl */
6933 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6934 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6935 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6936 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6937 +#define SYCC_HR 0x00000010 /* Force HT */
6938 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
6939 +#define SYCC_CD_SHIFT 16
6940 +
6941 +/* gpiotimerval*/
6942 +#define GPIO_ONTIME_SHIFT 16
6943 +
6944 +/* clockcontrol_n */
6945 +#define CN_N1_MASK 0x3f /* n1 control */
6946 +#define CN_N2_MASK 0x3f00 /* n2 control */
6947 +#define CN_N2_SHIFT 8
6948 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6949 +#define CN_PLLC_SHIFT 16
6950 +
6951 +/* clockcontrol_sb/pci/uart */
6952 +#define CC_M1_MASK 0x3f /* m1 control */
6953 +#define CC_M2_MASK 0x3f00 /* m2 control */
6954 +#define CC_M2_SHIFT 8
6955 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6956 +#define CC_M3_SHIFT 16
6957 +#define CC_MC_MASK 0x1f000000 /* mux control */
6958 +#define CC_MC_SHIFT 24
6959 +
6960 +/* N3M Clock control magic field values */
6961 +#define CC_F6_2 0x02 /* A factor of 2 in */
6962 +#define CC_F6_3 0x03 /* 6-bit fields like */
6963 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6964 +#define CC_F6_5 0x09
6965 +#define CC_F6_6 0x11
6966 +#define CC_F6_7 0x21
6967 +
6968 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6969 +
6970 +#define CC_MC_BYPASS 0x08
6971 +#define CC_MC_M1 0x04
6972 +#define CC_MC_M1M2 0x02
6973 +#define CC_MC_M1M2M3 0x01
6974 +#define CC_MC_M1M3 0x11
6975 +
6976 +/* Type 2 Clock control magic field values */
6977 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6978 +#define CC_T2M2_BIAS 3 /* m2 bias */
6979 +
6980 +#define CC_T2MC_M1BYP 1
6981 +#define CC_T2MC_M2BYP 2
6982 +#define CC_T2MC_M3BYP 4
6983 +
6984 +/* Type 6 Clock control magic field values */
6985 +#define CC_T6_MMASK 1 /* bits of interest in m */
6986 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6987 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6988 +#define SB2MIPS_T6(sb) (2 * (sb))
6989 +
6990 +/* Common clock base */
6991 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6992 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6993 +
6994 +/* Clock control values for 200Mhz in 5350 */
6995 +#define CLKC_5350_N 0x0311
6996 +#define CLKC_5350_M 0x04020009
6997 +
6998 +/* Flash types in the chipcommon capabilities register */
6999 +#define FLASH_NONE 0x000 /* No flash */
7000 +#define SFLASH_ST 0x100 /* ST serial flash */
7001 +#define SFLASH_AT 0x200 /* Atmel serial flash */
7002 +#define PFLASH 0x700 /* Parallel flash */
7003 +
7004 +/* Bits in the config registers */
7005 +#define CC_CFG_EN 0x0001 /* Enable */
7006 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
7007 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
7008 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
7009 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
7010 +#define CC_CFG_EM_IDE 0x000a /* IDE */
7011 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
7012 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
7013 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
7014 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
7015 +
7016 +/* Start/busy bit in flashcontrol */
7017 +#define SFLASH_START 0x80000000
7018 +#define SFLASH_BUSY SFLASH_START
7019 +
7020 +/* flashcontrol opcodes for ST flashes */
7021 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
7022 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
7023 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
7024 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
7025 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
7026 +#define SFLASH_ST_PP 0x0302 /* Page Program */
7027 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
7028 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
7029 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
7030 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
7031 +
7032 +/* Status register bits for ST flashes */
7033 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
7034 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
7035 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
7036 +#define SFLASH_ST_BP_SHIFT 2
7037 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
7038 +
7039 +/* flashcontrol opcodes for Atmel flashes */
7040 +#define SFLASH_AT_READ 0x07e8
7041 +#define SFLASH_AT_PAGE_READ 0x07d2
7042 +#define SFLASH_AT_BUF1_READ
7043 +#define SFLASH_AT_BUF2_READ
7044 +#define SFLASH_AT_STATUS 0x01d7
7045 +#define SFLASH_AT_BUF1_WRITE 0x0384
7046 +#define SFLASH_AT_BUF2_WRITE 0x0387
7047 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
7048 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
7049 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
7050 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
7051 +#define SFLASH_AT_PAGE_ERASE 0x0281
7052 +#define SFLASH_AT_BLOCK_ERASE 0x0250
7053 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
7054 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
7055 +#define SFLASH_AT_BUF1_LOAD 0x0253
7056 +#define SFLASH_AT_BUF2_LOAD 0x0255
7057 +#define SFLASH_AT_BUF1_COMPARE 0x0260
7058 +#define SFLASH_AT_BUF2_COMPARE 0x0261
7059 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
7060 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
7061 +
7062 +/* Status register bits for Atmel flashes */
7063 +#define SFLASH_AT_READY 0x80
7064 +#define SFLASH_AT_MISMATCH 0x40
7065 +#define SFLASH_AT_ID_MASK 0x38
7066 +#define SFLASH_AT_ID_SHIFT 3
7067 +
7068 +/* OTP regions */
7069 +#define OTP_HW_REGION OTPS_HW_PROTECT
7070 +#define OTP_SW_REGION OTPS_SW_PROTECT
7071 +#define OTP_CID_REGION OTPS_CID_PROTECT
7072 +
7073 +/* OTP regions (Byte offsets from otp size) */
7074 +#define OTP_SWLIM_OFF (-8)
7075 +#define OTP_CIDBASE_OFF 0
7076 +#define OTP_CIDLIM_OFF 8
7077 +
7078 +/* Predefined OTP words (Word offset from otp size) */
7079 +#define OTP_BOUNDARY_OFF (-4)
7080 +#define OTP_HWSIGN_OFF (-3)
7081 +#define OTP_SWSIGN_OFF (-2)
7082 +#define OTP_CIDSIGN_OFF (-1)
7083 +
7084 +#define OTP_CID_OFF 0
7085 +#define OTP_PKG_OFF 1
7086 +#define OTP_FID_OFF 2
7087 +#define OTP_RSV_OFF 3
7088 +#define OTP_LIM_OFF 4
7089 +
7090 +#define OTP_SIGNATURE 0x578a
7091 +#define OTP_MAGIC 0x4e56
7092 +
7093 +#endif /* _SBCHIPC_H */
7094 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h
7095 --- linux-2.4.32/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
7096 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbconfig.h 2005-12-16 23:39:10.932836000 +0100
7097 @@ -0,0 +1,342 @@
7098 +/*
7099 + * Broadcom SiliconBackplane hardware register definitions.
7100 + *
7101 + * Copyright 2005, Broadcom Corporation
7102 + * All Rights Reserved.
7103 + *
7104 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7105 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7106 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7107 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7108 + * $Id$
7109 + */
7110 +
7111 +#ifndef _SBCONFIG_H
7112 +#define _SBCONFIG_H
7113 +
7114 +/* cpp contortions to concatenate w/arg prescan */
7115 +#ifndef PAD
7116 +#define _PADLINE(line) pad ## line
7117 +#define _XSTR(line) _PADLINE(line)
7118 +#define PAD _XSTR(__LINE__)
7119 +#endif
7120 +
7121 +/*
7122 + * SiliconBackplane Address Map.
7123 + * All regions may not exist on all chips.
7124 + */
7125 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
7126 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
7127 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
7128 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
7129 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
7130 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
7131 +
7132 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
7133 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
7134 +
7135 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
7136 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
7137 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
7138 +
7139 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
7140 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
7141 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
7142 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
7143 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
7144 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
7145 +
7146 +
7147 +/* enumeration space related defs */
7148 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
7149 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
7150 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
7151 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
7152 +
7153 +/* mips address */
7154 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
7155 +
7156 +/*
7157 + * Sonics Configuration Space Registers.
7158 + */
7159 +#define SBIPSFLAG 0x08
7160 +#define SBTPSFLAG 0x18
7161 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
7162 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
7163 +#define SBADMATCH3 0x60
7164 +#define SBADMATCH2 0x68
7165 +#define SBADMATCH1 0x70
7166 +#define SBIMSTATE 0x90
7167 +#define SBINTVEC 0x94
7168 +#define SBTMSTATELOW 0x98
7169 +#define SBTMSTATEHIGH 0x9c
7170 +#define SBBWA0 0xa0
7171 +#define SBIMCONFIGLOW 0xa8
7172 +#define SBIMCONFIGHIGH 0xac
7173 +#define SBADMATCH0 0xb0
7174 +#define SBTMCONFIGLOW 0xb8
7175 +#define SBTMCONFIGHIGH 0xbc
7176 +#define SBBCONFIG 0xc0
7177 +#define SBBSTATE 0xc8
7178 +#define SBACTCNFG 0xd8
7179 +#define SBFLAGST 0xe8
7180 +#define SBIDLOW 0xf8
7181 +#define SBIDHIGH 0xfc
7182 +
7183 +#ifndef _LANGUAGE_ASSEMBLY
7184 +
7185 +typedef volatile struct _sbconfig {
7186 + uint32 PAD[2];
7187 + uint32 sbipsflag; /* initiator port ocp slave flag */
7188 + uint32 PAD[3];
7189 + uint32 sbtpsflag; /* target port ocp slave flag */
7190 + uint32 PAD[11];
7191 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
7192 + uint32 PAD;
7193 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
7194 + uint32 PAD[3];
7195 + uint32 sbadmatch3; /* address match3 */
7196 + uint32 PAD;
7197 + uint32 sbadmatch2; /* address match2 */
7198 + uint32 PAD;
7199 + uint32 sbadmatch1; /* address match1 */
7200 + uint32 PAD[7];
7201 + uint32 sbimstate; /* initiator agent state */
7202 + uint32 sbintvec; /* interrupt mask */
7203 + uint32 sbtmstatelow; /* target state */
7204 + uint32 sbtmstatehigh; /* target state */
7205 + uint32 sbbwa0; /* bandwidth allocation table0 */
7206 + uint32 PAD;
7207 + uint32 sbimconfiglow; /* initiator configuration */
7208 + uint32 sbimconfighigh; /* initiator configuration */
7209 + uint32 sbadmatch0; /* address match0 */
7210 + uint32 PAD;
7211 + uint32 sbtmconfiglow; /* target configuration */
7212 + uint32 sbtmconfighigh; /* target configuration */
7213 + uint32 sbbconfig; /* broadcast configuration */
7214 + uint32 PAD;
7215 + uint32 sbbstate; /* broadcast state */
7216 + uint32 PAD[3];
7217 + uint32 sbactcnfg; /* activate configuration */
7218 + uint32 PAD[3];
7219 + uint32 sbflagst; /* current sbflags */
7220 + uint32 PAD[3];
7221 + uint32 sbidlow; /* identification */
7222 + uint32 sbidhigh; /* identification */
7223 +} sbconfig_t;
7224 +
7225 +#endif /* _LANGUAGE_ASSEMBLY */
7226 +
7227 +/* sbipsflag */
7228 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
7229 +#define SBIPS_INT1_SHIFT 0
7230 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
7231 +#define SBIPS_INT2_SHIFT 8
7232 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
7233 +#define SBIPS_INT3_SHIFT 16
7234 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
7235 +#define SBIPS_INT4_SHIFT 24
7236 +
7237 +/* sbtpsflag */
7238 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
7239 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
7240 +
7241 +/* sbtmerrlog */
7242 +#define SBTMEL_CM 0x00000007 /* command */
7243 +#define SBTMEL_CI 0x0000ff00 /* connection id */
7244 +#define SBTMEL_EC 0x0f000000 /* error code */
7245 +#define SBTMEL_ME 0x80000000 /* multiple error */
7246 +
7247 +/* sbimstate */
7248 +#define SBIM_PC 0xf /* pipecount */
7249 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
7250 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
7251 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
7252 +#define SBIM_AP_TK 0x20 /* use token only */
7253 +#define SBIM_AP_RSV 0x30 /* reserved */
7254 +#define SBIM_IBE 0x20000 /* inbanderror */
7255 +#define SBIM_TO 0x40000 /* timeout */
7256 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
7257 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
7258 +
7259 +/* sbtmstatelow */
7260 +#define SBTML_RESET 0x1 /* reset */
7261 +#define SBTML_REJ_MASK 0x6 /* reject */
7262 +#define SBTML_REJ_SHIFT 1
7263 +#define SBTML_CLK 0x10000 /* clock enable */
7264 +#define SBTML_FGC 0x20000 /* force gated clocks on */
7265 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
7266 +#define SBTML_PE 0x40000000 /* pme enable */
7267 +#define SBTML_BE 0x80000000 /* bist enable */
7268 +
7269 +/* sbtmstatehigh */
7270 +#define SBTMH_SERR 0x1 /* serror */
7271 +#define SBTMH_INT 0x2 /* interrupt */
7272 +#define SBTMH_BUSY 0x4 /* busy */
7273 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
7274 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
7275 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
7276 +#define SBTMH_GCR 0x20000000 /* gated clock request */
7277 +#define SBTMH_BISTF 0x40000000 /* bist failed */
7278 +#define SBTMH_BISTD 0x80000000 /* bist done */
7279 +
7280 +
7281 +/* sbbwa0 */
7282 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
7283 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
7284 +#define SBBWA_TAB1_SHIFT 16
7285 +
7286 +/* sbimconfiglow */
7287 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
7288 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
7289 +#define SBIMCL_RTO_SHIFT 4
7290 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
7291 +#define SBIMCL_CID_SHIFT 16
7292 +
7293 +/* sbimconfighigh */
7294 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
7295 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
7296 +#define SBIMCH_TEM_SHIFT 4
7297 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
7298 +#define SBIMCH_BEM_SHIFT 6
7299 +
7300 +/* sbadmatch0 */
7301 +#define SBAM_TYPE_MASK 0x3 /* address type */
7302 +#define SBAM_AD64 0x4 /* reserved */
7303 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
7304 +#define SBAM_ADINT0_SHIFT 3
7305 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
7306 +#define SBAM_ADINT1_SHIFT 3
7307 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
7308 +#define SBAM_ADINT2_SHIFT 3
7309 +#define SBAM_ADEN 0x400 /* enable */
7310 +#define SBAM_ADNEG 0x800 /* negative decode */
7311 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
7312 +#define SBAM_BASE0_SHIFT 8
7313 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
7314 +#define SBAM_BASE1_SHIFT 12
7315 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
7316 +#define SBAM_BASE2_SHIFT 16
7317 +
7318 +/* sbtmconfiglow */
7319 +#define SBTMCL_CD_MASK 0xff /* clock divide */
7320 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
7321 +#define SBTMCL_CO_SHIFT 11
7322 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
7323 +#define SBTMCL_IF_SHIFT 18
7324 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
7325 +#define SBTMCL_IM_SHIFT 24
7326 +
7327 +/* sbtmconfighigh */
7328 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
7329 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
7330 +#define SBTMCH_RM_SHIFT 2
7331 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
7332 +#define SBTMCH_SM_SHIFT 4
7333 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
7334 +#define SBTMCH_EM_SHIFT 8
7335 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
7336 +#define SBTMCH_IM_SHIFT 10
7337 +
7338 +/* sbbconfig */
7339 +#define SBBC_LAT_MASK 0x3 /* sb latency */
7340 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
7341 +#define SBBC_MAX0_SHIFT 16
7342 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
7343 +#define SBBC_MAX1_SHIFT 20
7344 +
7345 +/* sbbstate */
7346 +#define SBBS_SRD 0x1 /* st reg disable */
7347 +#define SBBS_HRD 0x2 /* hold reg disable */
7348 +
7349 +/* sbidlow */
7350 +#define SBIDL_CS_MASK 0x3 /* config space */
7351 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
7352 +#define SBIDL_AR_SHIFT 3
7353 +#define SBIDL_SYNCH 0x40 /* sync */
7354 +#define SBIDL_INIT 0x80 /* initiator */
7355 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
7356 +#define SBIDL_MINLAT_SHIFT 8
7357 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
7358 +#define SBIDL_MAXLAT_SHIFT 12
7359 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
7360 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
7361 +#define SBIDL_CW_SHIFT 18
7362 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
7363 +#define SBIDL_TP_SHIFT 20
7364 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
7365 +#define SBIDL_IP_SHIFT 24
7366 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
7367 +#define SBIDL_RV_SHIFT 28
7368 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
7369 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
7370 +
7371 +/* sbidhigh */
7372 +#define SBIDH_RC_MASK 0x000f /* revision code */
7373 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
7374 +#define SBIDH_RCE_SHIFT 8
7375 +#define SBCOREREV(sbidh) \
7376 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
7377 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
7378 +#define SBIDH_CC_SHIFT 4
7379 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
7380 +#define SBIDH_VC_SHIFT 16
7381 +
7382 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
7383 +
7384 +/* vendor codes */
7385 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
7386 +
7387 +/* core codes */
7388 +#define SB_CC 0x800 /* chipcommon core */
7389 +#define SB_ILINE20 0x801 /* iline20 core */
7390 +#define SB_SDRAM 0x803 /* sdram core */
7391 +#define SB_PCI 0x804 /* pci core */
7392 +#define SB_MIPS 0x805 /* mips core */
7393 +#define SB_ENET 0x806 /* enet mac core */
7394 +#define SB_CODEC 0x807 /* v90 codec core */
7395 +#define SB_USB 0x808 /* usb 1.1 host/device core */
7396 +#define SB_ADSL 0x809 /* ADSL core */
7397 +#define SB_ILINE100 0x80a /* iline100 core */
7398 +#define SB_IPSEC 0x80b /* ipsec core */
7399 +#define SB_PCMCIA 0x80d /* pcmcia core */
7400 +#define SB_SOCRAM 0x80e /* internal memory core */
7401 +#define SB_MEMC 0x80f /* memc sdram core */
7402 +#define SB_EXTIF 0x811 /* external interface core */
7403 +#define SB_D11 0x812 /* 802.11 MAC core */
7404 +#define SB_MIPS33 0x816 /* mips3302 core */
7405 +#define SB_USB11H 0x817 /* usb 1.1 host core */
7406 +#define SB_USB11D 0x818 /* usb 1.1 device core */
7407 +#define SB_USB20H 0x819 /* usb 2.0 host core */
7408 +#define SB_USB20D 0x81a /* usb 2.0 device core */
7409 +#define SB_SDIOH 0x81b /* sdio host core */
7410 +#define SB_ROBO 0x81c /* roboswitch core */
7411 +#define SB_ATA100 0x81d /* parallel ATA core */
7412 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
7413 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
7414 +#define SB_PCIE 0x820 /* pci express core */
7415 +#define SB_SRAMC 0x822 /* SRAM controller core */
7416 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
7417 +
7418 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
7419 +
7420 +/* Not really related to Silicon Backplane, but a couple of software
7421 + * conventions for the use the flash space:
7422 + */
7423 +
7424 +/* Minumum amount of flash we support */
7425 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
7426 +
7427 +/* A boot/binary may have an embedded block that describes its size */
7428 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
7429 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
7430 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
7431 +#define BISZ_TXTST_IDX 1 /* 1: text start */
7432 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
7433 +#define BISZ_DATAST_IDX 3 /* 3: text start */
7434 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
7435 +#define BISZ_BSSST_IDX 5 /* 5: text start */
7436 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
7437 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
7438 +
7439 +#endif /* _SBCONFIG_H */
7440 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbextif.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbextif.h
7441 --- linux-2.4.32/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
7442 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbextif.h 2005-12-16 23:39:10.932836000 +0100
7443 @@ -0,0 +1,242 @@
7444 +/*
7445 + * Hardware-specific External Interface I/O core definitions
7446 + * for the BCM47xx family of SiliconBackplane-based chips.
7447 + *
7448 + * The External Interface core supports a total of three external chip selects
7449 + * supporting external interfaces. One of the external chip selects is
7450 + * used for Flash, one is used for PCMCIA, and the other may be
7451 + * programmed to support either a synchronous interface or an
7452 + * asynchronous interface. The asynchronous interface can be used to
7453 + * support external devices such as UARTs and the BCM2019 Bluetooth
7454 + * baseband processor.
7455 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7456 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7457 + *
7458 + * Copyright 2005, Broadcom Corporation
7459 + * All Rights Reserved.
7460 + *
7461 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7462 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7463 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7464 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7465 + * $Id$
7466 + */
7467 +
7468 +#ifndef _SBEXTIF_H
7469 +#define _SBEXTIF_H
7470 +
7471 +/* external interface address space */
7472 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
7473 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
7474 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
7475 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
7476 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
7477 +
7478 +/* cpp contortions to concatenate w/arg prescan */
7479 +#ifndef PAD
7480 +#define _PADLINE(line) pad ## line
7481 +#define _XSTR(line) _PADLINE(line)
7482 +#define PAD _XSTR(__LINE__)
7483 +#endif /* PAD */
7484 +
7485 +/*
7486 + * The multiple instances of output and output enable registers
7487 + * are present to allow driver software for multiple cores to control
7488 + * gpio outputs without needing to share a single register pair.
7489 + */
7490 +struct gpiouser {
7491 + uint32 out;
7492 + uint32 outen;
7493 +};
7494 +#define NGPIOUSER 5
7495 +
7496 +typedef volatile struct {
7497 + uint32 corecontrol;
7498 + uint32 extstatus;
7499 + uint32 PAD[2];
7500 +
7501 + /* pcmcia control registers */
7502 + uint32 pcmcia_config;
7503 + uint32 pcmcia_memwait;
7504 + uint32 pcmcia_attrwait;
7505 + uint32 pcmcia_iowait;
7506 +
7507 + /* programmable interface control registers */
7508 + uint32 prog_config;
7509 + uint32 prog_waitcount;
7510 +
7511 + /* flash control registers */
7512 + uint32 flash_config;
7513 + uint32 flash_waitcount;
7514 + uint32 PAD[4];
7515 +
7516 + uint32 watchdog;
7517 +
7518 + /* clock control */
7519 + uint32 clockcontrol_n;
7520 + uint32 clockcontrol_sb;
7521 + uint32 clockcontrol_pci;
7522 + uint32 clockcontrol_mii;
7523 + uint32 PAD[3];
7524 +
7525 + /* gpio */
7526 + uint32 gpioin;
7527 + struct gpiouser gpio[NGPIOUSER];
7528 + uint32 PAD;
7529 + uint32 ejtagouten;
7530 + uint32 gpiointpolarity;
7531 + uint32 gpiointmask;
7532 + uint32 PAD[153];
7533 +
7534 + uint8 uartdata;
7535 + uint8 PAD[3];
7536 + uint8 uartimer;
7537 + uint8 PAD[3];
7538 + uint8 uartfcr;
7539 + uint8 PAD[3];
7540 + uint8 uartlcr;
7541 + uint8 PAD[3];
7542 + uint8 uartmcr;
7543 + uint8 PAD[3];
7544 + uint8 uartlsr;
7545 + uint8 PAD[3];
7546 + uint8 uartmsr;
7547 + uint8 PAD[3];
7548 + uint8 uartscratch;
7549 + uint8 PAD[3];
7550 +} extifregs_t;
7551 +
7552 +/* corecontrol */
7553 +#define CC_UE (1 << 0) /* uart enable */
7554 +
7555 +/* extstatus */
7556 +#define ES_EM (1 << 0) /* endian mode (ro) */
7557 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7558 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7559 +
7560 +/* gpio bit mask */
7561 +#define GPIO_BIT0 (1 << 0)
7562 +#define GPIO_BIT1 (1 << 1)
7563 +#define GPIO_BIT2 (1 << 2)
7564 +#define GPIO_BIT3 (1 << 3)
7565 +#define GPIO_BIT4 (1 << 4)
7566 +#define GPIO_BIT5 (1 << 5)
7567 +#define GPIO_BIT6 (1 << 6)
7568 +#define GPIO_BIT7 (1 << 7)
7569 +
7570 +
7571 +/* pcmcia/prog/flash_config */
7572 +#define CF_EN (1 << 0) /* enable */
7573 +#define CF_EM_MASK 0xe /* mode */
7574 +#define CF_EM_SHIFT 1
7575 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7576 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7577 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7578 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7579 +#define CF_BS (1 << 5) /* byteswap */
7580 +#define CF_CD_MASK 0xc0 /* clock divider */
7581 +#define CF_CD_SHIFT 6
7582 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7583 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7584 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7585 +#define CF_CE (1 << 8) /* clock enable */
7586 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7587 +
7588 +/* pcmcia_memwait */
7589 +#define PM_W0_MASK 0x3f /* waitcount0 */
7590 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7591 +#define PM_W1_SHIFT 8
7592 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7593 +#define PM_W2_SHIFT 16
7594 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7595 +#define PM_W3_SHIFT 24
7596 +
7597 +/* pcmcia_attrwait */
7598 +#define PA_W0_MASK 0x3f /* waitcount0 */
7599 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7600 +#define PA_W1_SHIFT 8
7601 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7602 +#define PA_W2_SHIFT 16
7603 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7604 +#define PA_W3_SHIFT 24
7605 +
7606 +/* pcmcia_iowait */
7607 +#define PI_W0_MASK 0x3f /* waitcount0 */
7608 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7609 +#define PI_W1_SHIFT 8
7610 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7611 +#define PI_W2_SHIFT 16
7612 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7613 +#define PI_W3_SHIFT 24
7614 +
7615 +/* prog_waitcount */
7616 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7617 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7618 +#define PW_W1_SHIFT 8
7619 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7620 +#define PW_W2_SHIFT 16
7621 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7622 +#define PW_W3_SHIFT 24
7623 +
7624 +#define PW_W0 0x0000000c
7625 +#define PW_W1 0x00000a00
7626 +#define PW_W2 0x00020000
7627 +#define PW_W3 0x01000000
7628 +
7629 +/* flash_waitcount */
7630 +#define FW_W0_MASK 0x1f /* waitcount0 */
7631 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7632 +#define FW_W1_SHIFT 8
7633 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7634 +#define FW_W2_SHIFT 16
7635 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7636 +#define FW_W3_SHIFT 24
7637 +
7638 +/* watchdog */
7639 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7640 +
7641 +/* clockcontrol_n */
7642 +#define CN_N1_MASK 0x3f /* n1 control */
7643 +#define CN_N2_MASK 0x3f00 /* n2 control */
7644 +#define CN_N2_SHIFT 8
7645 +
7646 +/* clockcontrol_sb/pci/mii */
7647 +#define CC_M1_MASK 0x3f /* m1 control */
7648 +#define CC_M2_MASK 0x3f00 /* m2 control */
7649 +#define CC_M2_SHIFT 8
7650 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7651 +#define CC_M3_SHIFT 16
7652 +#define CC_MC_MASK 0x1f000000 /* mux control */
7653 +#define CC_MC_SHIFT 24
7654 +
7655 +/* Clock control default values */
7656 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7657 +#define CC_DEF_100 0x04020011
7658 +#define CC_DEF_33 0x11030011
7659 +#define CC_DEF_25 0x11050011
7660 +
7661 +/* Clock control values for 125Mhz */
7662 +#define CC_125_N 0x0802
7663 +#define CC_125_M 0x04020009
7664 +#define CC_125_M25 0x11090009
7665 +#define CC_125_M33 0x11090005
7666 +
7667 +/* Clock control magic field values */
7668 +#define CC_F6_2 0x02 /* A factor of 2 in */
7669 +#define CC_F6_3 0x03 /* 6-bit fields like */
7670 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7671 +#define CC_F6_5 0x09
7672 +#define CC_F6_6 0x11
7673 +#define CC_F6_7 0x21
7674 +
7675 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7676 +
7677 +#define CC_MC_BYPASS 0x08
7678 +#define CC_MC_M1 0x04
7679 +#define CC_MC_M1M2 0x02
7680 +#define CC_MC_M1M2M3 0x01
7681 +#define CC_MC_M1M3 0x11
7682 +
7683 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7684 +
7685 +#endif /* _SBEXTIF_H */
7686 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbhnddma.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbhnddma.h
7687 --- linux-2.4.32/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
7688 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbhnddma.h 2005-12-16 23:39:10.932836000 +0100
7689 @@ -0,0 +1,312 @@
7690 +/*
7691 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
7692 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7693 + *
7694 + * Copyright 2005, Broadcom Corporation
7695 + * All Rights Reserved.
7696 + *
7697 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7698 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7699 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7700 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7701 + * $Id$
7702 + */
7703 +
7704 +#ifndef _sbhnddma_h_
7705 +#define _sbhnddma_h_
7706 +
7707 +
7708 +/* 2byte-wide pio register set per channel(xmt or rcv) */
7709 +typedef volatile struct {
7710 + uint16 fifocontrol;
7711 + uint16 fifodata;
7712 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
7713 + uint16 PAD;
7714 +} pio2regs_t;
7715 +
7716 +/* a pair of pio channels(tx and rx) */
7717 +typedef volatile struct {
7718 + pio2regs_t tx;
7719 + pio2regs_t rx;
7720 +} pio2regp_t;
7721 +
7722 +/* 4byte-wide pio register set per channel(xmt or rcv) */
7723 +typedef volatile struct {
7724 + uint32 fifocontrol;
7725 + uint32 fifodata;
7726 +} pio4regs_t;
7727 +
7728 +/* a pair of pio channels(tx and rx) */
7729 +typedef volatile struct {
7730 + pio4regs_t tx;
7731 + pio4regs_t rx;
7732 +} pio4regp_t;
7733 +
7734 +
7735 +
7736 +/* DMA structure:
7737 + * support two DMA engines: 32 bits address or 64 bit addressing
7738 + * basic DMA register set is per channel(transmit or receive)
7739 + * a pair of channels is defined for convenience
7740 + */
7741 +
7742 +
7743 +/*** 32 bits addressing ***/
7744 +
7745 +/* dma registers per channel(xmt or rcv) */
7746 +typedef volatile struct {
7747 + uint32 control; /* enable, et al */
7748 + uint32 addr; /* descriptor ring base address (4K aligned) */
7749 + uint32 ptr; /* last descriptor posted to chip */
7750 + uint32 status; /* current active descriptor, et al */
7751 +} dma32regs_t;
7752 +
7753 +typedef volatile struct {
7754 + dma32regs_t xmt; /* dma tx channel */
7755 + dma32regs_t rcv; /* dma rx channel */
7756 +} dma32regp_t;
7757 +
7758 +typedef volatile struct { /* diag access */
7759 + uint32 fifoaddr; /* diag address */
7760 + uint32 fifodatalow; /* low 32bits of data */
7761 + uint32 fifodatahigh; /* high 32bits of data */
7762 + uint32 pad; /* reserved */
7763 +} dma32diag_t;
7764 +
7765 +/*
7766 + * DMA Descriptor
7767 + * Descriptors are only read by the hardware, never written back.
7768 + */
7769 +typedef volatile struct {
7770 + uint32 ctrl; /* misc control bits & bufcount */
7771 + uint32 addr; /* data buffer address */
7772 +} dma32dd_t;
7773 +
7774 +/*
7775 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
7776 + */
7777 +#define D32MAXRINGSZ 4096
7778 +#define D32RINGALIGN 4096
7779 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
7780 +
7781 +/* transmit channel control */
7782 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7783 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7784 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7785 +#define XC_FL ((uint32)1 << 4) /* flush request */
7786 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
7787 +#define XC_AE_SHIFT 16
7788 +
7789 +/* transmit descriptor table pointer */
7790 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7791 +
7792 +/* transmit channel status */
7793 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7794 +#define XS_XS_MASK 0xf000 /* transmit state */
7795 +#define XS_XS_SHIFT 12
7796 +#define XS_XS_DISABLED 0x0000 /* disabled */
7797 +#define XS_XS_ACTIVE 0x1000 /* active */
7798 +#define XS_XS_IDLE 0x2000 /* idle wait */
7799 +#define XS_XS_STOPPED 0x3000 /* stopped */
7800 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7801 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7802 +#define XS_XE_SHIFT 16
7803 +#define XS_XE_NOERR 0x00000 /* no error */
7804 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7805 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7806 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7807 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7808 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
7809 +#define XS_AD_SHIFT 20
7810 +
7811 +/* receive channel control */
7812 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7813 +#define RC_RO_MASK 0xfe /* receive frame offset */
7814 +#define RC_RO_SHIFT 1
7815 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7816 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
7817 +#define RC_AE_SHIFT 16
7818 +
7819 +/* receive descriptor table pointer */
7820 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7821 +
7822 +/* receive channel status */
7823 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7824 +#define RS_RS_MASK 0xf000 /* receive state */
7825 +#define RS_RS_SHIFT 12
7826 +#define RS_RS_DISABLED 0x0000 /* disabled */
7827 +#define RS_RS_ACTIVE 0x1000 /* active */
7828 +#define RS_RS_IDLE 0x2000 /* idle wait */
7829 +#define RS_RS_STOPPED 0x3000 /* reserved */
7830 +#define RS_RE_MASK 0xf0000 /* receive errors */
7831 +#define RS_RE_SHIFT 16
7832 +#define RS_RE_NOERR 0x00000 /* no error */
7833 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7834 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7835 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7836 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7837 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
7838 +#define RS_AD_SHIFT 20
7839 +
7840 +/* fifoaddr */
7841 +#define FA_OFF_MASK 0xffff /* offset */
7842 +#define FA_SEL_MASK 0xf0000 /* select */
7843 +#define FA_SEL_SHIFT 16
7844 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7845 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7846 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7847 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7848 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7849 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7850 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7851 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7852 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
7853 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7854 +
7855 +/* descriptor control flags */
7856 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7857 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
7858 +#define CTRL_AE_SHIFT 16
7859 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7860 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7861 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7862 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7863 +
7864 +/* control flags in the range [27:20] are core-specific and not defined here */
7865 +#define CTRL_CORE_MASK 0x0ff00000
7866 +
7867 +/*** 64 bits addressing ***/
7868 +
7869 +/* dma registers per channel(xmt or rcv) */
7870 +typedef volatile struct {
7871 + uint32 control; /* enable, et al */
7872 + uint32 ptr; /* last descriptor posted to chip */
7873 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
7874 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
7875 + uint32 status0; /* current descriptor, xmt state */
7876 + uint32 status1; /* active descriptor, xmt error */
7877 +} dma64regs_t;
7878 +
7879 +typedef volatile struct {
7880 + dma64regs_t tx; /* dma64 tx channel */
7881 + dma64regs_t rx; /* dma64 rx channel */
7882 +} dma64regp_t;
7883 +
7884 +typedef volatile struct { /* diag access */
7885 + uint32 fifoaddr; /* diag address */
7886 + uint32 fifodatalow; /* low 32bits of data */
7887 + uint32 fifodatahigh; /* high 32bits of data */
7888 + uint32 pad; /* reserved */
7889 +} dma64diag_t;
7890 +
7891 +/*
7892 + * DMA Descriptor
7893 + * Descriptors are only read by the hardware, never written back.
7894 + */
7895 +typedef volatile struct {
7896 + uint32 ctrl1; /* misc control bits & bufcount */
7897 + uint32 ctrl2; /* buffer count and address extension */
7898 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
7899 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
7900 +} dma64dd_t;
7901 +
7902 +/*
7903 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
7904 + */
7905 +#define D64MAXRINGSZ 8192
7906 +#define D64RINGALIGN 8192
7907 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
7908 +
7909 +/* transmit channel control */
7910 +#define D64_XC_XE 0x00000001 /* transmit enable */
7911 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
7912 +#define D64_XC_LE 0x00000004 /* loopback enable */
7913 +#define D64_XC_FL 0x00000010 /* flush request */
7914 +#define D64_XC_AE 0x00110000 /* address extension bits */
7915 +#define D64_XC_AE_SHIFT 16
7916 +
7917 +/* transmit descriptor table pointer */
7918 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
7919 +
7920 +/* transmit channel status */
7921 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
7922 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
7923 +#define D64_XS0_XS_SHIFT 28
7924 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
7925 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
7926 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
7927 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
7928 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
7929 +
7930 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
7931 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
7932 +#define D64_XS1_XE_SHIFT 28
7933 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
7934 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
7935 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
7936 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
7937 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
7938 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
7939 +
7940 +/* receive channel control */
7941 +#define D64_RC_RE 0x00000001 /* receive enable */
7942 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
7943 +#define D64_RC_RO_SHIFT 1
7944 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
7945 +#define D64_RC_AE 0x00110000 /* address extension bits */
7946 +#define D64_RC_AE_SHIFT 16
7947 +
7948 +/* receive descriptor table pointer */
7949 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
7950 +
7951 +/* receive channel status */
7952 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
7953 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
7954 +#define D64_RS0_RS_SHIFT 28
7955 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
7956 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
7957 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
7958 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
7959 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
7960 +
7961 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
7962 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
7963 +#define D64_RS1_RE_SHIFT 28
7964 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
7965 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
7966 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
7967 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
7968 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
7969 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
7970 +
7971 +/* fifoaddr */
7972 +#define D64_FA_OFF_MASK 0xffff /* offset */
7973 +#define D64_FA_SEL_MASK 0xf0000 /* select */
7974 +#define D64_FA_SEL_SHIFT 16
7975 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
7976 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
7977 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
7978 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
7979 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
7980 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7981 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
7982 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7983 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
7984 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7985 +
7986 +/* descriptor control flags 1 */
7987 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
7988 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
7989 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
7990 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
7991 +
7992 +/* descriptor control flags 2 */
7993 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
7994 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
7995 +#define D64_CTRL2_AE_SHIFT 16
7996 +
7997 +/* control flags in the range [27:20] are core-specific and not defined here */
7998 +#define D64_CTRL_CORE_MASK 0x0ff00000
7999 +
8000 +
8001 +#endif /* _sbhnddma_h_ */
8002 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbmemc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmemc.h
8003 --- linux-2.4.32/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
8004 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmemc.h 2005-12-16 23:39:10.932836000 +0100
8005 @@ -0,0 +1,148 @@
8006 +/*
8007 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
8008 + *
8009 + * Copyright 2005, Broadcom Corporation
8010 + * All Rights Reserved.
8011 + *
8012 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8013 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8014 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8015 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8016 + *
8017 + * $Id$
8018 + */
8019 +
8020 +#ifndef _SBMEMC_H
8021 +#define _SBMEMC_H
8022 +
8023 +#ifdef _LANGUAGE_ASSEMBLY
8024 +
8025 +#define MEMC_CONTROL 0x00
8026 +#define MEMC_CONFIG 0x04
8027 +#define MEMC_REFRESH 0x08
8028 +#define MEMC_BISTSTAT 0x0c
8029 +#define MEMC_MODEBUF 0x10
8030 +#define MEMC_BKCLS 0x14
8031 +#define MEMC_PRIORINV 0x18
8032 +#define MEMC_DRAMTIM 0x1c
8033 +#define MEMC_INTSTAT 0x20
8034 +#define MEMC_INTMASK 0x24
8035 +#define MEMC_INTINFO 0x28
8036 +#define MEMC_NCDLCTL 0x30
8037 +#define MEMC_RDNCDLCOR 0x34
8038 +#define MEMC_WRNCDLCOR 0x38
8039 +#define MEMC_MISCDLYCTL 0x3c
8040 +#define MEMC_DQSGATENCDL 0x40
8041 +#define MEMC_SPARE 0x44
8042 +#define MEMC_TPADDR 0x48
8043 +#define MEMC_TPDATA 0x4c
8044 +#define MEMC_BARRIER 0x50
8045 +#define MEMC_CORE 0x54
8046 +
8047 +
8048 +#else
8049 +
8050 +/* Sonics side: MEMC core registers */
8051 +typedef volatile struct sbmemcregs {
8052 + uint32 control;
8053 + uint32 config;
8054 + uint32 refresh;
8055 + uint32 biststat;
8056 + uint32 modebuf;
8057 + uint32 bkcls;
8058 + uint32 priorinv;
8059 + uint32 dramtim;
8060 + uint32 intstat;
8061 + uint32 intmask;
8062 + uint32 intinfo;
8063 + uint32 reserved1;
8064 + uint32 ncdlctl;
8065 + uint32 rdncdlcor;
8066 + uint32 wrncdlcor;
8067 + uint32 miscdlyctl;
8068 + uint32 dqsgatencdl;
8069 + uint32 spare;
8070 + uint32 tpaddr;
8071 + uint32 tpdata;
8072 + uint32 barrier;
8073 + uint32 core;
8074 +} sbmemcregs_t;
8075 +
8076 +#endif
8077 +
8078 +/* MEMC Core Init values (OCP ID 0x80f) */
8079 +
8080 +/* For sdr: */
8081 +#define MEMC_SD_CONFIG_INIT 0x00048000
8082 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
8083 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
8084 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
8085 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
8086 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
8087 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
8088 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
8089 +#define MEMC_SD_CONTROL_INIT0 0x00000002
8090 +#define MEMC_SD_CONTROL_INIT1 0x00000008
8091 +#define MEMC_SD_CONTROL_INIT2 0x00000004
8092 +#define MEMC_SD_CONTROL_INIT3 0x00000010
8093 +#define MEMC_SD_CONTROL_INIT4 0x00000001
8094 +#define MEMC_SD_MODEBUF_INIT 0x00000000
8095 +#define MEMC_SD_REFRESH_INIT 0x0000840f
8096 +
8097 +
8098 +/* This is for SDRM8X8X4 */
8099 +#define MEMC_SDR_INIT 0x0008
8100 +#define MEMC_SDR_MODE 0x32
8101 +#define MEMC_SDR_NCDL 0x00020032
8102 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
8103 +
8104 +/* For ddr: */
8105 +#define MEMC_CONFIG_INIT 0x00048000
8106 +#define MEMC_DRAMTIM2_INIT 0x000754d8
8107 +#define MEMC_DRAMTIM25_INIT 0x000754d9
8108 +#define MEMC_RDNCDLCOR_INIT 0x00000000
8109 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
8110 +#define MEMC_WRNCDLCOR_INIT 0x49351200
8111 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
8112 +#define MEMC_DQSGATENCDL_INIT 0x00030000
8113 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
8114 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
8115 +#define MEMC_NCDLCTL_INIT 0x00002001
8116 +#define MEMC_CONTROL_INIT0 0x00000002
8117 +#define MEMC_CONTROL_INIT1 0x00000008
8118 +#define MEMC_MODEBUF_INIT0 0x00004000
8119 +#define MEMC_CONTROL_INIT2 0x00000010
8120 +#define MEMC_MODEBUF_INIT1 0x00000100
8121 +#define MEMC_CONTROL_INIT3 0x00000010
8122 +#define MEMC_CONTROL_INIT4 0x00000008
8123 +#define MEMC_REFRESH_INIT 0x0000840f
8124 +#define MEMC_CONTROL_INIT5 0x00000004
8125 +#define MEMC_MODEBUF_INIT2 0x00000000
8126 +#define MEMC_CONTROL_INIT6 0x00000010
8127 +#define MEMC_CONTROL_INIT7 0x00000001
8128 +
8129 +
8130 +/* This is for DDRM16X16X2 */
8131 +#define MEMC_DDR_INIT 0x0009
8132 +#define MEMC_DDR_MODE 0x62
8133 +#define MEMC_DDR_NCDL 0x0005050a
8134 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
8135 +
8136 +/* mask for sdr/ddr calibration registers */
8137 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
8138 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
8139 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
8140 +
8141 +/* masks for miscdlyctl registers */
8142 +#define MEMC_MISC_SM_MASK 0x30000000
8143 +#define MEMC_MISC_SM_SHIFT 28
8144 +#define MEMC_MISC_SD_MASK 0x0f000000
8145 +#define MEMC_MISC_SD_SHIFT 24
8146 +
8147 +/* hw threshhold for calculating wr/rd for sdr memc */
8148 +#define MEMC_CD_THRESHOLD 128
8149 +
8150 +/* Low bit of init register says if memc is ddr or sdr */
8151 +#define MEMC_CONFIG_DDR 0x00000001
8152 +
8153 +#endif /* _SBMEMC_H */
8154 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbmips.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmips.h
8155 --- linux-2.4.32/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
8156 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbmips.h 2005-12-16 23:39:10.936836250 +0100
8157 @@ -0,0 +1,62 @@
8158 +/*
8159 + * Broadcom SiliconBackplane MIPS definitions
8160 + *
8161 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
8162 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
8163 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
8164 + * interface. The core revision is stored in the SB ID register in SB
8165 + * configuration space.
8166 + *
8167 + * Copyright 2005, Broadcom Corporation
8168 + * All Rights Reserved.
8169 + *
8170 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8171 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8172 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8173 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8174 + *
8175 + * $Id$
8176 + */
8177 +
8178 +#ifndef _SBMIPS_H
8179 +#define _SBMIPS_H
8180 +
8181 +#include <mipsinc.h>
8182 +
8183 +#ifndef _LANGUAGE_ASSEMBLY
8184 +
8185 +/* cpp contortions to concatenate w/arg prescan */
8186 +#ifndef PAD
8187 +#define _PADLINE(line) pad ## line
8188 +#define _XSTR(line) _PADLINE(line)
8189 +#define PAD _XSTR(__LINE__)
8190 +#endif /* PAD */
8191 +
8192 +typedef volatile struct {
8193 + uint32 corecontrol;
8194 + uint32 PAD[2];
8195 + uint32 biststatus;
8196 + uint32 PAD[4];
8197 + uint32 intstatus;
8198 + uint32 intmask;
8199 + uint32 timer;
8200 +} mipsregs_t;
8201 +
8202 +extern uint32 sb_flag(sb_t *sbh);
8203 +extern uint sb_irq(sb_t *sbh);
8204 +
8205 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
8206 +
8207 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
8208 +extern void sb_jtagm_disable(void *h);
8209 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
8210 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
8211 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
8212 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
8213 +extern void BCMINIT(enable_pfc)(uint32 mode);
8214 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
8215 +
8216 +
8217 +#endif /* _LANGUAGE_ASSEMBLY */
8218 +
8219 +#endif /* _SBMIPS_H */
8220 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpcie.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcie.h
8221 --- linux-2.4.32/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
8222 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcie.h 2005-12-16 23:39:10.936836250 +0100
8223 @@ -0,0 +1,199 @@
8224 +/*
8225 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
8226 + *
8227 + * $Id:
8228 + * Copyright 2005, Broadcom Corporation
8229 + * All Rights Reserved.
8230 + *
8231 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8232 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8233 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8234 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8235 + */
8236 +
8237 +#ifndef _SBPCIE_H
8238 +#define _SBPCIE_H
8239 +
8240 +/* cpp contortions to concatenate w/arg prescan */
8241 +#ifndef PAD
8242 +#define _PADLINE(line) pad ## line
8243 +#define _XSTR(line) _PADLINE(line)
8244 +#define PAD _XSTR(__LINE__)
8245 +#endif
8246 +
8247 +/* PCIE Enumeration space offsets*/
8248 +#define PCIE_CORE_CONFIG_OFFSET 0x0
8249 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
8250 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
8251 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
8252 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
8253 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
8254 +#define PCIE_SBCONFIG_OFFSET 0xE00
8255 +
8256 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
8257 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
8258 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
8259 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
8260 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
8261 +
8262 +/* SB side: PCIE core and host control registers */
8263 +typedef struct sbpcieregs {
8264 +
8265 + uint32 PAD[3];
8266 + uint32 biststatus; /* bist Status: 0x00C*/
8267 + uint32 PAD[6];
8268 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
8269 + uint32 PAD[54];
8270 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
8271 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
8272 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
8273 + uint32 PAD[4];
8274 +
8275 + /* pcie core supports in direct access to config space */
8276 + uint32 configaddr; /* pcie config space access: Address field: 0x120*/
8277 + uint32 configdata; /* pcie config space access: Data field: 0x124*/
8278 +
8279 + /* mdio access to serdes */
8280 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
8281 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
8282 +
8283 + /* pcie protocol phy/dllp/tlp register access mechanism*/
8284 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
8285 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
8286 +
8287 + uint32 PAD[434];
8288 + uint16 sprom[36]; /* SPROM shadow Area */
8289 +} sbpcieregs_t;
8290 +
8291 +/* SB to PCIE translation masks */
8292 +#define SBTOPCIE0_MASK 0xfc000000
8293 +#define SBTOPCIE1_MASK 0xfc000000
8294 +#define SBTOPCIE2_MASK 0xc0000000
8295 +
8296 +/* Access type bits (0:1)*/
8297 +#define SBTOPCIE_MEM 0
8298 +#define SBTOPCIE_IO 1
8299 +#define SBTOPCIE_CFG0 2
8300 +#define SBTOPCIE_CFG1 3
8301 +
8302 +/*Prefetch enable bit 2*/
8303 +#define SBTOPCIE_PF 4
8304 +
8305 +/*Write Burst enable for memory write bit 3*/
8306 +#define SBTOPCIE_WR_BURST 8
8307 +
8308 +/* config access */
8309 +#define CONFIGADDR_FUNC_MASK 0x7000
8310 +#define CONFIGADDR_FUNC_SHF 12
8311 +#define CONFIGADDR_REG_MASK 0x0FFF
8312 +#define CONFIGADDR_REG_SHF 0
8313 +
8314 +/* PCIE protocol regs Indirect Address */
8315 +#define PCIEADDR_PROT_MASK 0x300
8316 +#define PCIEADDR_PROT_SHF 8
8317 +#define PCIEADDR_PL_TLP 0
8318 +#define PCIEADDR_PL_DLLP 1
8319 +#define PCIEADDR_PL_PLP 2
8320 +
8321 +/* PCIE protocol PHY diagnostic registers */
8322 +#define PCIE_PLP_MODEREG 0x200 /* Mode*/
8323 +#define PCIE_PLP_STATUSREG 0x204 /* Status*/
8324 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
8325 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
8326 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
8327 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
8328 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
8329 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
8330 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
8331 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
8332 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
8333 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
8334 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
8335 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
8336 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
8337 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
8338 +
8339 +/* PCIE protocol DLLP diagnostic registers */
8340 +#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
8341 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
8342 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
8343 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
8344 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
8345 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
8346 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
8347 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
8348 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
8349 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
8350 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
8351 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
8352 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
8353 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
8354 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
8355 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
8356 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
8357 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
8358 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
8359 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
8360 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
8361 +
8362 +/* PCIE protocol TLP diagnostic registers */
8363 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
8364 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
8365 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
8366 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
8367 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
8368 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
8369 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
8370 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
8371 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
8372 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
8373 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
8374 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
8375 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
8376 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
8377 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
8378 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
8379 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
8380 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
8381 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
8382 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
8383 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
8384 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
8385 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
8386 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
8387 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
8388 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
8389 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
8390 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
8391 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
8392 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
8393 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
8394 +
8395 +/* MDIO control */
8396 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
8397 +#define MDIOCTL_DIVISOR_VAL 0x2
8398 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
8399 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
8400 +
8401 +/* MDIO Data */
8402 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
8403 +#define MDIODATA_TA 0x00020000 /* Turnaround */
8404 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
8405 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
8406 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
8407 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
8408 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
8409 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
8410 +#define MDIODATA_START 0x40000000 /* start of Transaction */
8411 +
8412 +/* MDIO devices (SERDES modules) */
8413 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
8414 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
8415 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
8416 +
8417 +/* SERDES registers */
8418 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
8419 +#define SERDES_RX_CDR 6 /* CDR */
8420 +#define SERDES_RX_CDRBW 7 /* CDR BW */
8421 +
8422 +#endif /* _SBPCIE_H */
8423 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpci.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpci.h
8424 --- linux-2.4.32/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
8425 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpci.h 2005-12-16 23:39:10.936836250 +0100
8426 @@ -0,0 +1,122 @@
8427 +/*
8428 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
8429 + *
8430 + * $Id$
8431 + * Copyright 2005, Broadcom Corporation
8432 + * All Rights Reserved.
8433 + *
8434 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8435 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8436 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8437 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8438 + */
8439 +
8440 +#ifndef _SBPCI_H
8441 +#define _SBPCI_H
8442 +
8443 +/* cpp contortions to concatenate w/arg prescan */
8444 +#ifndef PAD
8445 +#define _PADLINE(line) pad ## line
8446 +#define _XSTR(line) _PADLINE(line)
8447 +#define PAD _XSTR(__LINE__)
8448 +#endif
8449 +
8450 +/* Sonics side: PCI core and host control registers */
8451 +typedef struct sbpciregs {
8452 + uint32 control; /* PCI control */
8453 + uint32 PAD[3];
8454 + uint32 arbcontrol; /* PCI arbiter control */
8455 + uint32 PAD[3];
8456 + uint32 intstatus; /* Interrupt status */
8457 + uint32 intmask; /* Interrupt mask */
8458 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
8459 + uint32 PAD[9];
8460 + uint32 bcastaddr; /* Sonics broadcast address */
8461 + uint32 bcastdata; /* Sonics broadcast data */
8462 + uint32 PAD[2];
8463 + uint32 gpioin; /* ro: gpio input (>=rev2) */
8464 + uint32 gpioout; /* rw: gpio output (>=rev2) */
8465 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
8466 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
8467 + uint32 PAD[36];
8468 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
8469 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
8470 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
8471 + uint32 PAD[445];
8472 + uint16 sprom[36]; /* SPROM shadow Area */
8473 + uint32 PAD[46];
8474 +} sbpciregs_t;
8475 +
8476 +/* PCI control */
8477 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
8478 +#define PCI_RST 0x02 /* Value driven out to pin */
8479 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
8480 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
8481 +
8482 +/* PCI arbiter control */
8483 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
8484 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
8485 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
8486 +#define PCI_PARKID_SHIFT 1
8487 +#define PCI_PARKID_LAST 0 /* Last requestor */
8488 +#define PCI_PARKID_4710 1 /* 4710 */
8489 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
8490 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
8491 +
8492 +/* Interrupt status/mask */
8493 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
8494 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
8495 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
8496 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
8497 +#define PCI_PME 0x10 /* PCI PME# is asserted */
8498 +
8499 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
8500 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
8501 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
8502 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
8503 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
8504 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
8505 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
8506 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
8507 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
8508 +
8509 +/* Sonics broadcast address */
8510 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
8511 +
8512 +/* Sonics to PCI translation types */
8513 +#define SBTOPCI0_MASK 0xfc000000
8514 +#define SBTOPCI1_MASK 0xfc000000
8515 +#define SBTOPCI2_MASK 0xc0000000
8516 +#define SBTOPCI_MEM 0
8517 +#define SBTOPCI_IO 1
8518 +#define SBTOPCI_CFG0 2
8519 +#define SBTOPCI_CFG1 3
8520 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
8521 +#define SBTOPCI_BURST 0x8 /* burst enable */
8522 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
8523 +#define SBTOPCI_RC_READ 0x00 /* memory read */
8524 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
8525 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
8526 +
8527 +/* PCI core index in SROM shadow area */
8528 +#define SRSH_PI_OFFSET 0 /* first word */
8529 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
8530 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
8531 +
8532 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
8533 +#define cap_list rsvd_a[0]
8534 +#define bar0_window dev_dep[0x80 - 0x40]
8535 +#define bar1_window dev_dep[0x84 - 0x40]
8536 +#define sprom_control dev_dep[0x88 - 0x40]
8537 +
8538 +#ifndef _LANGUAGE_ASSEMBLY
8539 +
8540 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8541 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8542 +extern void sbpci_ban(uint16 core);
8543 +extern int sbpci_init(sb_t *sbh);
8544 +extern void sbpci_check(sb_t *sbh);
8545 +
8546 +#endif /* !_LANGUAGE_ASSEMBLY */
8547 +
8548 +#endif /* _SBPCI_H */
8549 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbpcmcia.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcmcia.h
8550 --- linux-2.4.32/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
8551 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbpcmcia.h 2005-12-16 23:39:10.936836250 +0100
8552 @@ -0,0 +1,146 @@
8553 +/*
8554 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
8555 + *
8556 + * $Id$
8557 + * Copyright 2005, Broadcom Corporation
8558 + * All Rights Reserved.
8559 + *
8560 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8561 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8562 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8563 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8564 + */
8565 +
8566 +#ifndef _SBPCMCIA_H
8567 +#define _SBPCMCIA_H
8568 +
8569 +
8570 +/* All the addresses that are offsets in attribute space are divided
8571 + * by two to account for the fact that odd bytes are invalid in
8572 + * attribute space and our read/write routines make the space appear
8573 + * as if they didn't exist. Still we want to show the original numbers
8574 + * as documented in the hnd_pcmcia core manual.
8575 + */
8576 +
8577 +/* PCMCIA Function Configuration Registers */
8578 +#define PCMCIA_FCR (0x700 / 2)
8579 +
8580 +#define FCR0_OFF 0
8581 +#define FCR1_OFF (0x40 / 2)
8582 +#define FCR2_OFF (0x80 / 2)
8583 +#define FCR3_OFF (0xc0 / 2)
8584 +
8585 +#define PCMCIA_FCR0 (0x700 / 2)
8586 +#define PCMCIA_FCR1 (0x740 / 2)
8587 +#define PCMCIA_FCR2 (0x780 / 2)
8588 +#define PCMCIA_FCR3 (0x7c0 / 2)
8589 +
8590 +/* Standard PCMCIA FCR registers */
8591 +
8592 +#define PCMCIA_COR 0
8593 +
8594 +#define COR_RST 0x80
8595 +#define COR_LEV 0x40
8596 +#define COR_IRQEN 0x04
8597 +#define COR_BLREN 0x01
8598 +#define COR_FUNEN 0x01
8599 +
8600 +
8601 +#define PCICIA_FCSR (2 / 2)
8602 +#define PCICIA_PRR (4 / 2)
8603 +#define PCICIA_SCR (6 / 2)
8604 +#define PCICIA_ESR (8 / 2)
8605 +
8606 +
8607 +#define PCM_MEMOFF 0x0000
8608 +#define F0_MEMOFF 0x1000
8609 +#define F1_MEMOFF 0x2000
8610 +#define F2_MEMOFF 0x3000
8611 +#define F3_MEMOFF 0x4000
8612 +
8613 +/* Memory base in the function fcr's */
8614 +#define MEM_ADDR0 (0x728 / 2)
8615 +#define MEM_ADDR1 (0x72a / 2)
8616 +#define MEM_ADDR2 (0x72c / 2)
8617 +
8618 +/* PCMCIA base plus Srom access in fcr0: */
8619 +#define PCMCIA_ADDR0 (0x072e / 2)
8620 +#define PCMCIA_ADDR1 (0x0730 / 2)
8621 +#define PCMCIA_ADDR2 (0x0732 / 2)
8622 +
8623 +#define MEM_SEG (0x0734 / 2)
8624 +#define SROM_CS (0x0736 / 2)
8625 +#define SROM_DATAL (0x0738 / 2)
8626 +#define SROM_DATAH (0x073a / 2)
8627 +#define SROM_ADDRL (0x073c / 2)
8628 +#define SROM_ADDRH (0x073e / 2)
8629 +
8630 +/* Values for srom_cs: */
8631 +#define SROM_IDLE 0
8632 +#define SROM_WRITE 1
8633 +#define SROM_READ 2
8634 +#define SROM_WEN 4
8635 +#define SROM_WDS 7
8636 +#define SROM_DONE 8
8637 +
8638 +/* CIS stuff */
8639 +
8640 +/* The CIS stops where the FCRs start */
8641 +#define CIS_SIZE PCMCIA_FCR
8642 +
8643 +/* Standard tuples we know about */
8644 +
8645 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
8646 +#define CISTPL_FUNCE 0x22 /* Function extensions */
8647 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
8648 +
8649 +/* Function extensions for LANs */
8650 +
8651 +#define LAN_TECH 1 /* Technology type */
8652 +#define LAN_SPEED 2 /* Raw bit rate */
8653 +#define LAN_MEDIA 3 /* Transmission media */
8654 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
8655 +#define LAN_CONN 5 /* Connector standard */
8656 +
8657 +
8658 +/* CFTable */
8659 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
8660 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
8661 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
8662 +
8663 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
8664 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
8665 + */
8666 +
8667 +#define CISTPL_BRCM_HNBU 0x80
8668 +
8669 +/* Subtypes of BRCM_HNBU: */
8670 +
8671 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
8672 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
8673 + * device id and chiprev
8674 + */
8675 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
8676 +#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
8677 + * or 9 (sromrev > 1) bytes */
8678 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
8679 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
8680 +#define HNBU_AA 0x06 /* Antennas available */
8681 +#define HNBU_AG 0x07 /* Antenna gain */
8682 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
8683 +#define HNBU_LEDS 0x09 /* LED set */
8684 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
8685 + * in rev 2
8686 + */
8687 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
8688 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
8689 +
8690 +
8691 +/* sbtmstatelow */
8692 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
8693 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
8694 +
8695 +/* sbtmstatehigh */
8696 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
8697 +
8698 +#endif /* _SBPCMCIA_H */
8699 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbsdram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsdram.h
8700 --- linux-2.4.32/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
8701 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsdram.h 2005-12-16 23:39:10.936836250 +0100
8702 @@ -0,0 +1,75 @@
8703 +/*
8704 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
8705 + *
8706 + * Copyright 2005, Broadcom Corporation
8707 + * All Rights Reserved.
8708 + *
8709 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8710 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8711 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8712 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8713 + * $Id$
8714 + */
8715 +
8716 +#ifndef _SBSDRAM_H
8717 +#define _SBSDRAM_H
8718 +
8719 +#ifndef _LANGUAGE_ASSEMBLY
8720 +
8721 +/* Sonics side: SDRAM core registers */
8722 +typedef volatile struct sbsdramregs {
8723 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
8724 + uint32 config; /* Initializes external SDRAM mode register */
8725 + uint32 refresh; /* Controls external SDRAM refresh rate */
8726 + uint32 pad1;
8727 + uint32 pad2;
8728 +} sbsdramregs_t;
8729 +
8730 +#endif
8731 +
8732 +/* SDRAM initialization control (initcontrol) register bits */
8733 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
8734 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
8735 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
8736 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
8737 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
8738 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
8739 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
8740 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
8741 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
8742 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
8743 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
8744 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
8745 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
8746 +
8747 +/* SDRAM configuration (config) register bits */
8748 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
8749 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
8750 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
8751 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
8752 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
8753 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
8754 +
8755 +/* SDRAM refresh control (refresh) register bits */
8756 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
8757 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
8758 +
8759 +/* SDRAM Core default Init values (OCP ID 0x803) */
8760 +#define SDRAM_INIT MEM4MX16X2
8761 +#define SDRAM_CONFIG SDRAM_BURSTFULL
8762 +#define SDRAM_REFRESH SDRAM_REF(0x40)
8763 +
8764 +#define MEM1MX16 0x009 /* 2 MB */
8765 +#define MEM1MX16X2 0x409 /* 4 MB */
8766 +#define MEM2MX8X2 0x809 /* 4 MB */
8767 +#define MEM2MX8X4 0xc09 /* 8 MB */
8768 +#define MEM2MX32 0x439 /* 8 MB */
8769 +#define MEM4MX16 0x019 /* 8 MB */
8770 +#define MEM4MX16X2 0x419 /* 16 MB */
8771 +#define MEM8MX8X2 0x819 /* 16 MB */
8772 +#define MEM8MX16 0x829 /* 16 MB */
8773 +#define MEM4MX32 0x429 /* 16 MB */
8774 +#define MEM8MX8X4 0xc19 /* 32 MB */
8775 +#define MEM8MX16X2 0xc29 /* 32 MB */
8776 +
8777 +#endif /* _SBSDRAM_H */
8778 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbsocram.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsocram.h
8779 --- linux-2.4.32/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
8780 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbsocram.h 2005-12-16 23:39:10.936836250 +0100
8781 @@ -0,0 +1,37 @@
8782 +/*
8783 + * BCM47XX Sonics SiliconBackplane embedded ram core
8784 + *
8785 + * Copyright 2005, Broadcom Corporation
8786 + * All Rights Reserved.
8787 + *
8788 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8789 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8790 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8791 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8792 + *
8793 + * $Id$
8794 + */
8795 +
8796 +#ifndef _SBSOCRAM_H
8797 +#define _SBSOCRAM_H
8798 +
8799 +#define SOCRAM_MEMSIZE 0x00
8800 +#define SOCRAM_BISTSTAT 0x0c
8801 +
8802 +
8803 +#ifndef _LANGUAGE_ASSEMBLY
8804 +
8805 +/* Memcsocram core registers */
8806 +typedef volatile struct sbsocramregs {
8807 + uint32 memsize;
8808 + uint32 biststat;
8809 +} sbsocramregs_t;
8810 +
8811 +#endif
8812 +
8813 +/* Them memory size is 2 to the power of the following
8814 + * base added to the contents of the memsize register.
8815 + */
8816 +#define SOCRAM_MEMSIZE_BASESHIFT 16
8817 +
8818 +#endif /* _SBSOCRAM_H */
8819 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sbutils.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbutils.h
8820 --- linux-2.4.32/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8821 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sbutils.h 2005-12-16 23:39:10.936836250 +0100
8822 @@ -0,0 +1,140 @@
8823 +/*
8824 + * Misc utility routines for accessing chip-specific features
8825 + * of Broadcom HNBU SiliconBackplane-based chips.
8826 + *
8827 + * Copyright 2005, Broadcom Corporation
8828 + * All Rights Reserved.
8829 + *
8830 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8831 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8832 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8833 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8834 + *
8835 + * $Id$
8836 + */
8837 +
8838 +#ifndef _sbutils_h_
8839 +#define _sbutils_h_
8840 +
8841 +/*
8842 + * Datastructure to export all chip specific common variables
8843 + * public (read-only) portion of sbutils handle returned by
8844 + * sb_attach()/sb_kattach()
8845 +*/
8846 +
8847 +struct sb_pub {
8848 +
8849 + uint bustype; /* SB_BUS, PCI_BUS */
8850 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
8851 + uint buscorerev; /* buscore rev */
8852 + uint buscoreidx; /* buscore index */
8853 + int ccrev; /* chip common core rev */
8854 + uint boardtype; /* board type */
8855 + uint boardvendor; /* board vendor */
8856 + uint chip; /* chip number */
8857 + uint chiprev; /* chip revision */
8858 + uint chippkg; /* chip package option */
8859 + uint sonicsrev; /* sonics backplane rev */
8860 +};
8861 +
8862 +typedef const struct sb_pub sb_t;
8863 +
8864 +/*
8865 + * Many of the routines below take an 'sbh' handle as their first arg.
8866 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8867 + * At any one time, the sbh is logically focused on one particular sb core
8868 + * (the "current core").
8869 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8870 + */
8871 +
8872 +/* exported externs */
8873 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
8874 +extern sb_t * BCMINIT(sb_kattach)(void);
8875 +extern void sb_detach(sb_t *sbh);
8876 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
8877 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
8878 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
8879 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
8880 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
8881 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
8882 +extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
8883 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
8884 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
8885 +extern uint sb_bus(sb_t *sbh);
8886 +extern uint sb_buscoretype(sb_t *sbh);
8887 +extern uint sb_buscorerev(sb_t *sbh);
8888 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8889 +extern uint sb_coreid(sb_t *sbh);
8890 +extern uint sb_coreidx(sb_t *sbh);
8891 +extern uint sb_coreunit(sb_t *sbh);
8892 +extern uint sb_corevendor(sb_t *sbh);
8893 +extern uint sb_corerev(sb_t *sbh);
8894 +extern void *sb_osh(sb_t *sbh);
8895 +extern void *sb_coreregs(sb_t *sbh);
8896 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8897 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8898 +extern bool sb_iscoreup(sb_t *sbh);
8899 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8900 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8901 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
8902 +extern void sb_commit(sb_t *sbh);
8903 +extern uint32 sb_base(uint32 admatch);
8904 +extern uint32 sb_size(uint32 admatch);
8905 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
8906 +extern void sb_core_tofixup(sb_t *sbh);
8907 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8908 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8909 +extern uint32 sb_clock(sb_t *sbh);
8910 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8911 +extern void sb_pcmcia_init(sb_t *sbh);
8912 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8913 +extern void *sb_gpiosetcore(sb_t *sbh);
8914 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8915 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8916 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8917 +extern uint32 sb_gpioin(sb_t *sbh);
8918 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8919 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8920 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8921 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8922 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8923 +
8924 +extern void sb_clkctl_init(sb_t *sbh);
8925 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8926 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8927 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8928 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
8929 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
8930 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8931 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
8932 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
8933 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8934 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8935 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8936 +
8937 +
8938 +
8939 +/*
8940 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8941 +* The returned path is NULL terminated and has trailing '/'.
8942 +* Return 0 on success, nonzero otherwise.
8943 +*/
8944 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8945 +
8946 +/* clkctl xtal what flags */
8947 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8948 +#define PLL 0x2 /* main chip pll */
8949 +
8950 +/* clkctl clk mode */
8951 +#define CLK_FAST 0 /* force fast (pll) clock */
8952 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8953 +
8954 +
8955 +/* GPIO usage priorities */
8956 +#define GPIO_DRV_PRIORITY 0
8957 +#define GPIO_APP_PRIORITY 1
8958 +
8959 +/* device path */
8960 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8961 +
8962 +#endif /* _sbutils_h_ */
8963 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/sflash.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/sflash.h
8964 --- linux-2.4.32/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8965 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/sflash.h 2005-12-16 23:39:10.936836250 +0100
8966 @@ -0,0 +1,36 @@
8967 +/*
8968 + * Broadcom SiliconBackplane chipcommon serial flash interface
8969 + *
8970 + * Copyright 2005, Broadcom Corporation
8971 + * All Rights Reserved.
8972 + *
8973 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8974 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8975 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8976 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8977 + *
8978 + * $Id$
8979 + */
8980 +
8981 +#ifndef _sflash_h_
8982 +#define _sflash_h_
8983 +
8984 +#include <typedefs.h>
8985 +#include <sbchipc.h>
8986 +
8987 +struct sflash {
8988 + uint blocksize; /* Block size */
8989 + uint numblocks; /* Number of blocks */
8990 + uint32 type; /* Type */
8991 + uint size; /* Total size in bytes */
8992 +};
8993 +
8994 +/* Utility functions */
8995 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8996 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8997 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8998 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8999 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
9000 +extern struct sflash * sflash_init(chipcregs_t *cc);
9001 +
9002 +#endif /* _sflash_h_ */
9003 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/trxhdr.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/trxhdr.h
9004 --- linux-2.4.32/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
9005 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/trxhdr.h 2005-12-16 23:39:10.940836500 +0100
9006 @@ -0,0 +1,33 @@
9007 +/*
9008 + * TRX image file header format.
9009 + *
9010 + * Copyright 2005, Broadcom Corporation
9011 + * All Rights Reserved.
9012 + *
9013 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9014 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9015 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9016 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9017 + *
9018 + * $Id$
9019 + */
9020 +
9021 +#include <typedefs.h>
9022 +
9023 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
9024 +#define TRX_VERSION 1
9025 +#define TRX_MAX_LEN 0x3A0000
9026 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
9027 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
9028 +#define TRX_MAX_OFFSET 3
9029 +
9030 +struct trx_header {
9031 + uint32 magic; /* "HDR0" */
9032 + uint32 len; /* Length of file including header */
9033 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
9034 + uint32 flag_version; /* 0:15 flags, 16:31 version */
9035 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
9036 +};
9037 +
9038 +/* Compatibility */
9039 +typedef struct trx_header TRXHDR, *PTRXHDR;
9040 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/typedefs.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/typedefs.h
9041 --- linux-2.4.32/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
9042 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/typedefs.h 2005-12-16 23:39:10.940836500 +0100
9043 @@ -0,0 +1,326 @@
9044 +/*
9045 + * Copyright 2005, Broadcom Corporation
9046 + * All Rights Reserved.
9047 + *
9048 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9049 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9050 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9051 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9052 + * $Id$
9053 + */
9054 +
9055 +#ifndef _TYPEDEFS_H_
9056 +#define _TYPEDEFS_H_
9057 +
9058 +
9059 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
9060 + * typedef file "site_typedefs.h".
9061 + *
9062 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
9063 + * section of this file makes inferences about the compile environment
9064 + * based on defined symbols and possibly compiler pragmas.
9065 + *
9066 + * Following these two sections is the "Default Typedefs"
9067 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
9068 + * defined. This section has a default set of typedefs and a few
9069 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
9070 + */
9071 +
9072 +#ifdef SITE_TYPEDEFS
9073 +
9074 +/*******************************************************************************
9075 + * Site Specific Typedefs
9076 + *******************************************************************************/
9077 +
9078 +#include "site_typedefs.h"
9079 +
9080 +#else
9081 +
9082 +/*******************************************************************************
9083 + * Inferred Typedefs
9084 + *******************************************************************************/
9085 +
9086 +/* Infer the compile environment based on preprocessor symbols and pramas.
9087 + * Override type definitions as needed, and include configuration dependent
9088 + * header files to define types.
9089 + */
9090 +
9091 +#ifdef __cplusplus
9092 +
9093 +#define TYPEDEF_BOOL
9094 +#ifndef FALSE
9095 +#define FALSE false
9096 +#endif
9097 +#ifndef TRUE
9098 +#define TRUE true
9099 +#endif
9100 +
9101 +#else /* ! __cplusplus */
9102 +
9103 +#if defined(_WIN32)
9104 +
9105 +#define TYPEDEF_BOOL
9106 +typedef unsigned char bool; /* consistent w/BOOL */
9107 +
9108 +#endif /* _WIN32 */
9109 +
9110 +#endif /* ! __cplusplus */
9111 +
9112 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
9113 +#if defined(_WIN64)
9114 +#include <basetsd.h>
9115 +#define TYPEDEF_UINTPTR
9116 +typedef ULONG_PTR uintptr;
9117 +#endif
9118 +
9119 +#ifdef _HNDRTE_
9120 +typedef long unsigned int size_t;
9121 +#endif
9122 +
9123 +#ifdef _MSC_VER /* Microsoft C */
9124 +#define TYPEDEF_INT64
9125 +#define TYPEDEF_UINT64
9126 +typedef signed __int64 int64;
9127 +typedef unsigned __int64 uint64;
9128 +#endif
9129 +
9130 +#if defined(MACOSX) && defined(KERNEL)
9131 +#define TYPEDEF_BOOL
9132 +#endif
9133 +
9134 +
9135 +#if defined(linux)
9136 +#define TYPEDEF_UINT
9137 +#define TYPEDEF_USHORT
9138 +#define TYPEDEF_ULONG
9139 +#endif
9140 +
9141 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9142 +#define TYPEDEF_UINT
9143 +#define TYPEDEF_USHORT
9144 +#endif
9145 +
9146 +
9147 +/* Do not support the (u)int64 types with strict ansi for GNU C */
9148 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
9149 +#define TYPEDEF_INT64
9150 +#define TYPEDEF_UINT64
9151 +#endif
9152 +
9153 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
9154 + * for singned or unsigned */
9155 +#if defined(__ICL)
9156 +
9157 +#define TYPEDEF_INT64
9158 +
9159 +#if defined(__STDC__)
9160 +#define TYPEDEF_UINT64
9161 +#endif
9162 +
9163 +#endif /* __ICL */
9164 +
9165 +
9166 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9167 +
9168 +/* pick up ushort & uint from standard types.h */
9169 +#if defined(linux) && defined(__KERNEL__)
9170 +
9171 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
9172 +
9173 +#else
9174 +
9175 +#include <sys/types.h>
9176 +
9177 +#endif
9178 +
9179 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
9180 +
9181 +#if defined(MACOSX) && defined(KERNEL)
9182 +#include <IOKit/IOTypes.h>
9183 +#endif
9184 +
9185 +
9186 +/* use the default typedefs in the next section of this file */
9187 +#define USE_TYPEDEF_DEFAULTS
9188 +
9189 +#endif /* SITE_TYPEDEFS */
9190 +
9191 +
9192 +/*******************************************************************************
9193 + * Default Typedefs
9194 + *******************************************************************************/
9195 +
9196 +#ifdef USE_TYPEDEF_DEFAULTS
9197 +#undef USE_TYPEDEF_DEFAULTS
9198 +
9199 +#ifndef TYPEDEF_BOOL
9200 +typedef /*@abstract@*/ unsigned char bool;
9201 +#endif
9202 +
9203 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
9204 +
9205 +#ifndef TYPEDEF_UCHAR
9206 +typedef unsigned char uchar;
9207 +#endif
9208 +
9209 +#ifndef TYPEDEF_USHORT
9210 +typedef unsigned short ushort;
9211 +#endif
9212 +
9213 +#ifndef TYPEDEF_UINT
9214 +typedef unsigned int uint;
9215 +#endif
9216 +
9217 +#ifndef TYPEDEF_ULONG
9218 +typedef unsigned long ulong;
9219 +#endif
9220 +
9221 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
9222 +
9223 +#ifndef TYPEDEF_UINT8
9224 +typedef unsigned char uint8;
9225 +#endif
9226 +
9227 +#ifndef TYPEDEF_UINT16
9228 +typedef unsigned short uint16;
9229 +#endif
9230 +
9231 +#ifndef TYPEDEF_UINT32
9232 +typedef unsigned int uint32;
9233 +#endif
9234 +
9235 +#ifndef TYPEDEF_UINT64
9236 +typedef unsigned long long uint64;
9237 +#endif
9238 +
9239 +#ifndef TYPEDEF_UINTPTR
9240 +typedef unsigned int uintptr;
9241 +#endif
9242 +
9243 +#ifndef TYPEDEF_INT8
9244 +typedef signed char int8;
9245 +#endif
9246 +
9247 +#ifndef TYPEDEF_INT16
9248 +typedef signed short int16;
9249 +#endif
9250 +
9251 +#ifndef TYPEDEF_INT32
9252 +typedef signed int int32;
9253 +#endif
9254 +
9255 +#ifndef TYPEDEF_INT64
9256 +typedef signed long long int64;
9257 +#endif
9258 +
9259 +/*----------------------- define float32/64, float_t -----------------------*/
9260 +
9261 +#ifndef TYPEDEF_FLOAT32
9262 +typedef float float32;
9263 +#endif
9264 +
9265 +#ifndef TYPEDEF_FLOAT64
9266 +typedef double float64;
9267 +#endif
9268 +
9269 +/*
9270 + * abstracted floating point type allows for compile time selection of
9271 + * single or double precision arithmetic. Compiling with -DFLOAT32
9272 + * selects single precision; the default is double precision.
9273 + */
9274 +
9275 +#ifndef TYPEDEF_FLOAT_T
9276 +
9277 +#if defined(FLOAT32)
9278 +typedef float32 float_t;
9279 +#else /* default to double precision floating point */
9280 +typedef float64 float_t;
9281 +#endif
9282 +
9283 +#endif /* TYPEDEF_FLOAT_T */
9284 +
9285 +/*----------------------- define macro values -----------------------------*/
9286 +
9287 +#ifndef FALSE
9288 +#define FALSE 0
9289 +#endif
9290 +
9291 +#ifndef TRUE
9292 +#define TRUE 1
9293 +#endif
9294 +
9295 +#ifndef NULL
9296 +#define NULL 0
9297 +#endif
9298 +
9299 +#ifndef OFF
9300 +#define OFF 0
9301 +#endif
9302 +
9303 +#ifndef ON
9304 +#define ON 1
9305 +#endif
9306 +
9307 +#define AUTO (-1)
9308 +
9309 +/* Reclaiming text and data :
9310 + The following macros specify special linker sections that can be reclaimed
9311 + after a system is considered 'up'.
9312 + */
9313 +#if defined(__GNUC__) && defined(BCMRECLAIM)
9314 +extern bool bcmreclaimed;
9315 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
9316 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
9317 +#define BCMINIT(_id) _id##_ini
9318 +#else
9319 +#define BCMINITDATA(_data) _data
9320 +#define BCMINITFN(_fn) _fn
9321 +#define BCMINIT(_id) _id
9322 +#define bcmreclaimed 0
9323 +#endif
9324 +
9325 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
9326 +
9327 +#ifndef PTRSZ
9328 +#define PTRSZ sizeof (char*)
9329 +#endif
9330 +
9331 +#ifndef INLINE
9332 +
9333 +#ifdef _MSC_VER
9334 +
9335 +#define INLINE __inline
9336 +
9337 +#elif __GNUC__
9338 +
9339 +#define INLINE __inline__
9340 +
9341 +#else
9342 +
9343 +#define INLINE
9344 +
9345 +#endif /* _MSC_VER */
9346 +
9347 +#endif /* INLINE */
9348 +
9349 +#undef TYPEDEF_BOOL
9350 +#undef TYPEDEF_UCHAR
9351 +#undef TYPEDEF_USHORT
9352 +#undef TYPEDEF_UINT
9353 +#undef TYPEDEF_ULONG
9354 +#undef TYPEDEF_UINT8
9355 +#undef TYPEDEF_UINT16
9356 +#undef TYPEDEF_UINT32
9357 +#undef TYPEDEF_UINT64
9358 +#undef TYPEDEF_UINTPTR
9359 +#undef TYPEDEF_INT8
9360 +#undef TYPEDEF_INT16
9361 +#undef TYPEDEF_INT32
9362 +#undef TYPEDEF_INT64
9363 +#undef TYPEDEF_FLOAT32
9364 +#undef TYPEDEF_FLOAT64
9365 +#undef TYPEDEF_FLOAT_T
9366 +
9367 +#endif /* USE_TYPEDEF_DEFAULTS */
9368 +
9369 +#endif /* _TYPEDEFS_H_ */
9370 diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/wlioctl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/wlioctl.h
9371 --- linux-2.4.32/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
9372 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/wlioctl.h 2005-12-16 23:39:10.940836500 +0100
9373 @@ -0,0 +1,1030 @@
9374 +/*
9375 + * Custom OID/ioctl definitions for
9376 + * Broadcom 802.11abg Networking Device Driver
9377 + *
9378 + * Definitions subject to change without notice.
9379 + *
9380 + * Copyright 2005, Broadcom Corporation
9381 + * All Rights Reserved.
9382 + *
9383 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9384 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9385 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9386 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9387 + *
9388 + * $Id$
9389 + */
9390 +
9391 +#ifndef _wlioctl_h_
9392 +#define _wlioctl_h_
9393 +
9394 +#include <typedefs.h>
9395 +#include <proto/ethernet.h>
9396 +#include <proto/bcmeth.h>
9397 +#include <proto/bcmevent.h>
9398 +#include <proto/802.11.h>
9399 +
9400 +/* require default structure packing */
9401 +#if !defined(__GNUC__)
9402 +#pragma pack(push,8)
9403 +#endif
9404 +
9405 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
9406 +
9407 +typedef struct wl_rateset {
9408 + uint32 count; /* # rates in this set */
9409 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
9410 +} wl_rateset_t;
9411 +
9412 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
9413 +#define WL_CHANSPEC_BAND_MASK 0xf000
9414 +#define WL_CHANSPEC_BAND_SHIFT 12
9415 +#define WL_CHANSPEC_BAND_A 0x1000
9416 +#define WL_CHANSPEC_BAND_B 0x2000
9417 +
9418 +/*
9419 + * Per-bss information structure.
9420 + */
9421 +
9422 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
9423 +
9424 +typedef struct wl_bss_info {
9425 + uint32 version; /* version field */
9426 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
9427 + struct ether_addr BSSID;
9428 + uint16 beacon_period; /* units are Kusec */
9429 + uint16 capability; /* Capability information */
9430 + uint8 SSID_len;
9431 + uint8 SSID[32];
9432 + struct {
9433 + uint count; /* # rates in this set */
9434 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
9435 + } rateset; /* supported rates */
9436 + uint8 channel; /* Channel no. */
9437 + uint16 atim_window; /* units are Kusec */
9438 + uint8 dtim_period; /* DTIM period */
9439 + int16 RSSI; /* receive signal strength (in dBm) */
9440 + int8 phy_noise; /* noise (in dBm) */
9441 + uint32 ie_length; /* byte length of Information Elements */
9442 + /* variable length Information Elements */
9443 +} wl_bss_info_t;
9444 +
9445 +typedef struct wlc_ssid {
9446 + uint32 SSID_len;
9447 + uchar SSID[32];
9448 +} wlc_ssid_t;
9449 +
9450 +typedef struct wl_scan_params {
9451 + wlc_ssid_t ssid; /* default is {0, ""} */
9452 + struct ether_addr bssid;/* default is bcast */
9453 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
9454 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
9455 + int32 nprobes; /* -1 use default, number of probes per channel */
9456 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
9457 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
9458 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
9459 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
9460 + uint16 channel_list[1]; /* list of chanspecs */
9461 +} wl_scan_params_t;
9462 +/* size of wl_scan_params not including variable length array */
9463 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
9464 +
9465 +typedef struct wl_scan_results {
9466 + uint32 buflen;
9467 + uint32 version;
9468 + uint32 count;
9469 + wl_bss_info_t bss_info[1];
9470 +} wl_scan_results_t;
9471 +/* size of wl_scan_results not including variable length array */
9472 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
9473 +
9474 +/* uint32 list */
9475 +typedef struct wl_uint32_list {
9476 + /* in - # of elements, out - # of entries */
9477 + uint32 count;
9478 + /* variable length uint32 list */
9479 + uint32 element[1];
9480 +} wl_uint32_list_t;
9481 +
9482 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
9483 +
9484 +typedef struct wl_channels_in_country {
9485 + uint32 buflen;
9486 + uint32 band;
9487 + char country_abbrev[WLC_CNTRY_BUF_SZ];
9488 + uint32 count;
9489 + uint32 channel[1];
9490 +} wl_channels_in_country_t;
9491 +
9492 +typedef struct wl_country_list {
9493 + uint32 buflen;
9494 + uint32 band_set;
9495 + uint32 band;
9496 + uint32 count;
9497 + char country_abbrev[1];
9498 +} wl_country_list_t;
9499 +
9500 +#define WL_RM_TYPE_BASIC 1
9501 +#define WL_RM_TYPE_CCA 2
9502 +#define WL_RM_TYPE_RPI 3
9503 +
9504 +#define WL_RM_FLAG_PARALLEL (1<<0)
9505 +
9506 +#define WL_RM_FLAG_LATE (1<<1)
9507 +#define WL_RM_FLAG_INCAPABLE (1<<2)
9508 +#define WL_RM_FLAG_REFUSED (1<<3)
9509 +
9510 +typedef struct wl_rm_req_elt {
9511 + int8 type;
9512 + int8 flags;
9513 + uint16 chanspec;
9514 + uint32 token; /* token for this measurement */
9515 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9516 + uint32 tsf_l; /* TSF low 32-bits */
9517 + uint32 dur; /* TUs */
9518 +} wl_rm_req_elt_t;
9519 +
9520 +typedef struct wl_rm_req {
9521 + uint32 token; /* overall measurement set token */
9522 + uint32 count; /* number of measurement reqests */
9523 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
9524 +} wl_rm_req_t;
9525 +#define WL_RM_REQ_FIXED_LEN 8
9526 +
9527 +typedef struct wl_rm_rep_elt {
9528 + int8 type;
9529 + int8 flags;
9530 + uint16 chanspec;
9531 + uint32 token; /* token for this measurement */
9532 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9533 + uint32 tsf_l; /* TSF low 32-bits */
9534 + uint32 dur; /* TUs */
9535 + uint32 len; /* byte length of data block */
9536 + uint8 data[1]; /* variable length data block */
9537 +} wl_rm_rep_elt_t;
9538 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
9539 +
9540 +#define WL_RPI_REP_BIN_NUM 8
9541 +typedef struct wl_rm_rpi_rep {
9542 + uint8 rpi[WL_RPI_REP_BIN_NUM];
9543 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
9544 +} wl_rm_rpi_rep_t;
9545 +
9546 +typedef struct wl_rm_rep {
9547 + uint32 token; /* overall measurement set token */
9548 + uint32 len; /* length of measurement report block */
9549 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
9550 +} wl_rm_rep_t;
9551 +#define WL_RM_REP_FIXED_LEN 8
9552 +
9553 +
9554 +#if defined(BCMSUP_PSK)
9555 +typedef enum sup_auth_status {
9556 + WLC_SUP_DISCONNECTED = 0,
9557 + WLC_SUP_CONNECTING,
9558 + WLC_SUP_IDREQUIRED,
9559 + WLC_SUP_AUTHENTICATING,
9560 + WLC_SUP_AUTHENTICATED,
9561 + WLC_SUP_KEYXCHANGE,
9562 + WLC_SUP_KEYED,
9563 + WLC_SUP_TIMEOUT
9564 +} sup_auth_status_t;
9565 +#endif /* BCMCCX | BCMSUP_PSK */
9566 +
9567 +/* Enumerate crypto algorithms */
9568 +#define CRYPTO_ALGO_OFF 0
9569 +#define CRYPTO_ALGO_WEP1 1
9570 +#define CRYPTO_ALGO_TKIP 2
9571 +#define CRYPTO_ALGO_WEP128 3
9572 +#define CRYPTO_ALGO_AES_CCM 4
9573 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
9574 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
9575 +#define CRYPTO_ALGO_NALG 7
9576 +
9577 +#define WSEC_GEN_MIC_ERROR 0x0001
9578 +#define WSEC_GEN_REPLAY 0x0002
9579 +
9580 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
9581 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
9582 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
9583 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
9584 +
9585 +typedef struct wl_wsec_key {
9586 + uint32 index; /* key index */
9587 + uint32 len; /* key length */
9588 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
9589 + uint32 pad_1[18];
9590 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
9591 + uint32 flags; /* misc flags */
9592 + uint32 pad_2[2];
9593 + int pad_3;
9594 + int iv_initialized; /* has IV been initialized already? */
9595 + int pad_4;
9596 + /* Rx IV */
9597 + struct {
9598 + uint32 hi; /* upper 32 bits of IV */
9599 + uint16 lo; /* lower 16 bits of IV */
9600 + } rxiv;
9601 + uint32 pad_5[2];
9602 + struct ether_addr ea; /* per station */
9603 +} wl_wsec_key_t;
9604 +
9605 +
9606 +#define WSEC_MIN_PSK_LEN 8
9607 +#define WSEC_MAX_PSK_LEN 64
9608 +
9609 +/* Flag for key material needing passhash'ing */
9610 +#define WSEC_PASSPHRASE (1<<0)
9611 +
9612 +/* recepticle for WLC_SET_WSEC_PMK parameter */
9613 +typedef struct {
9614 + ushort key_len; /* octets in key material */
9615 + ushort flags; /* key handling qualification */
9616 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
9617 +} wsec_pmk_t;
9618 +
9619 +/* wireless security bitvec */
9620 +#define WEP_ENABLED 0x0001
9621 +#define TKIP_ENABLED 0x0002
9622 +#define AES_ENABLED 0x0004
9623 +#define WSEC_SWFLAG 0x0008
9624 +#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
9625 +
9626 +/* WPA authentication mode bitvec */
9627 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
9628 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
9629 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
9630 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
9631 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
9632 +
9633 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
9634 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
9635 +
9636 +
9637 +
9638 +/* pmkid */
9639 +#define MAXPMKID 16
9640 +
9641 +typedef struct _pmkid
9642 +{
9643 + struct ether_addr BSSID;
9644 + uint8 PMKID[WPA2_PMKID_LEN];
9645 +} pmkid_t;
9646 +
9647 +typedef struct _pmkid_list
9648 +{
9649 + uint32 npmkid;
9650 + pmkid_t pmkid[1];
9651 +} pmkid_list_t;
9652 +
9653 +typedef struct _pmkid_cand {
9654 + struct ether_addr BSSID;
9655 + uint8 preauth;
9656 +} pmkid_cand_t;
9657 +
9658 +typedef struct _pmkid_cand_list {
9659 + uint32 npmkid_cand;
9660 + pmkid_cand_t pmkid_cand[1];
9661 +} pmkid_cand_list_t;
9662 +
9663 +
9664 +typedef struct wl_led_info {
9665 + uint32 index; /* led index */
9666 + uint32 behavior;
9667 + bool activehi;
9668 +} wl_led_info_t;
9669 +
9670 +typedef struct wlc_assoc_info {
9671 + uint32 req_len;
9672 + uint32 resp_len;
9673 + uint32 flags;
9674 + struct dot11_assoc_req req;
9675 + struct ether_addr reassoc_bssid; /* used in reassoc's */
9676 + struct dot11_assoc_resp resp;
9677 +} wl_assoc_info_t;
9678 +/* flags */
9679 +#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
9680 +/* srom read/write struct passed through ioctl */
9681 +typedef struct {
9682 + uint byteoff; /* byte offset */
9683 + uint nbytes; /* number of bytes */
9684 + uint16 buf[1];
9685 +} srom_rw_t;
9686 +
9687 +/* R_REG and W_REG struct passed through ioctl */
9688 +typedef struct {
9689 + uint32 byteoff; /* byte offset of the field in d11regs_t */
9690 + uint32 val; /* read/write value of the field */
9691 + uint32 size; /* sizeof the field */
9692 + uint band; /* band (optional) */
9693 +} rw_reg_t;
9694 +
9695 +/* Structure used by GET/SET_ATTEN ioctls */
9696 +typedef struct {
9697 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
9698 + uint16 bb; /* Baseband attenuation */
9699 + uint16 radio; /* Radio attenuation */
9700 + uint16 txctl1; /* Radio TX_CTL1 value */
9701 +} atten_t;
9702 +
9703 +/* Used to get specific STA parameters */
9704 +typedef struct {
9705 + uint32 val;
9706 + struct ether_addr ea;
9707 +} scb_val_t;
9708 +
9709 +
9710 +/* Event data type */
9711 +typedef struct wlc_event {
9712 + wl_event_msg_t event; /* encapsulated event */
9713 + struct ether_addr *addr; /* used to keep a trace of the potential present of
9714 + an address in wlc_event_msg_t */
9715 + void *data; /* used to hang additional data on an event */
9716 + struct wlc_event *next; /* enables ordered list of pending events */
9717 +} wlc_event_t;
9718 +
9719 +#define BCM_MAC_STATUS_INDICATION (0x40010200L)
9720 +
9721 +typedef struct {
9722 + uint16 ver; /* version of this struct */
9723 + uint16 len; /* length in bytes of this structure */
9724 + uint16 cap; /* sta's advertized capabilities */
9725 + uint32 flags; /* flags defined below */
9726 + uint32 idle; /* time since data pkt rx'd from sta */
9727 + struct ether_addr ea; /* Station address */
9728 + wl_rateset_t rateset; /* rateset in use */
9729 + uint32 in; /* seconds elapsed since associated */
9730 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
9731 +} sta_info_t;
9732 +
9733 +#define WL_STA_VER 2
9734 +
9735 +/* flags fields */
9736 +#define WL_STA_BRCM 0x01
9737 +#define WL_STA_WME 0x02
9738 +#define WL_STA_ABCAP 0x04
9739 +#define WL_STA_AUTHE 0x08
9740 +#define WL_STA_ASSOC 0x10
9741 +#define WL_STA_AUTHO 0x20
9742 +#define WL_STA_WDS 0x40
9743 +#define WL_WDS_LINKUP 0x80
9744 +
9745 +
9746 +/*
9747 + * Country locale determines which channels are available to us.
9748 + */
9749 +typedef enum _wlc_locale {
9750 + WLC_WW = 0, /* Worldwide */
9751 + WLC_THA, /* Thailand */
9752 + WLC_ISR, /* Israel */
9753 + WLC_JDN, /* Jordan */
9754 + WLC_PRC, /* China */
9755 + WLC_JPN, /* Japan */
9756 + WLC_FCC, /* USA */
9757 + WLC_EUR, /* Europe */
9758 + WLC_USL, /* US Low Band only */
9759 + WLC_JPH, /* Japan High Band only */
9760 + WLC_ALL, /* All the channels in this band */
9761 + WLC_11D, /* Represents locale recieved by 11d beacons */
9762 + WLC_LAST_LOCALE,
9763 + WLC_UNDEFINED_LOCALE = 0xf
9764 +} wlc_locale_t;
9765 +
9766 +/* channel encoding */
9767 +typedef struct channel_info {
9768 + int hw_channel;
9769 + int target_channel;
9770 + int scan_channel;
9771 +} channel_info_t;
9772 +
9773 +/* For ioctls that take a list of MAC addresses */
9774 +struct maclist {
9775 + uint count; /* number of MAC addresses */
9776 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
9777 +};
9778 +
9779 +/* get pkt count struct passed through ioctl */
9780 +typedef struct get_pktcnt {
9781 + uint rx_good_pkt;
9782 + uint rx_bad_pkt;
9783 + uint tx_good_pkt;
9784 + uint tx_bad_pkt;
9785 +} get_pktcnt_t;
9786 +
9787 +/* Linux network driver ioctl encoding */
9788 +typedef struct wl_ioctl {
9789 + uint cmd; /* common ioctl definition */
9790 + void *buf; /* pointer to user buffer */
9791 + uint len; /* length of user buffer */
9792 + bool set; /* get or set request (optional) */
9793 + uint used; /* bytes read or written (optional) */
9794 + uint needed; /* bytes needed (optional) */
9795 +} wl_ioctl_t;
9796 +
9797 +/*
9798 + * Structure for passing hardware and software
9799 + * revision info up from the driver.
9800 + */
9801 +typedef struct wlc_rev_info {
9802 + uint vendorid; /* PCI vendor id */
9803 + uint deviceid; /* device id of chip */
9804 + uint radiorev; /* radio revision */
9805 + uint chiprev; /* chip revision */
9806 + uint corerev; /* core revision */
9807 + uint boardid; /* board identifier (usu. PCI sub-device id) */
9808 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
9809 + uint boardrev; /* board revision */
9810 + uint driverrev; /* driver version */
9811 + uint ucoderev; /* microcode version */
9812 + uint bus; /* bus type */
9813 + uint chipnum; /* chip number */
9814 +} wlc_rev_info_t;
9815 +
9816 +#define WL_BRAND_MAX 10
9817 +typedef struct wl_instance_info {
9818 + uint instance;
9819 + char brand[WL_BRAND_MAX];
9820 +} wl_instance_info_t;
9821 +
9822 +/* check this magic number */
9823 +#define WLC_IOCTL_MAGIC 0x14e46c77
9824 +
9825 +/* bump this number if you change the ioctl interface */
9826 +#define WLC_IOCTL_VERSION 1
9827 +
9828 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
9829 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
9830 +
9831 +/* common ioctl definitions */
9832 +#define WLC_GET_MAGIC 0
9833 +#define WLC_GET_VERSION 1
9834 +#define WLC_UP 2
9835 +#define WLC_DOWN 3
9836 +#define WLC_DUMP 6
9837 +#define WLC_GET_MSGLEVEL 7
9838 +#define WLC_SET_MSGLEVEL 8
9839 +#define WLC_GET_PROMISC 9
9840 +#define WLC_SET_PROMISC 10
9841 +#define WLC_GET_RATE 12
9842 +/* #define WLC_SET_RATE 13 */ /* no longer supported */
9843 +#define WLC_GET_INSTANCE 14
9844 +/* #define WLC_GET_FRAG 15 */ /* no longer supported */
9845 +/* #define WLC_SET_FRAG 16 */ /* no longer supported */
9846 +/* #define WLC_GET_RTS 17 */ /* no longer supported */
9847 +/* #define WLC_SET_RTS 18 */ /* no longer supported */
9848 +#define WLC_GET_INFRA 19
9849 +#define WLC_SET_INFRA 20
9850 +#define WLC_GET_AUTH 21
9851 +#define WLC_SET_AUTH 22
9852 +#define WLC_GET_BSSID 23
9853 +#define WLC_SET_BSSID 24
9854 +#define WLC_GET_SSID 25
9855 +#define WLC_SET_SSID 26
9856 +#define WLC_RESTART 27
9857 +#define WLC_GET_CHANNEL 29
9858 +#define WLC_SET_CHANNEL 30
9859 +#define WLC_GET_SRL 31
9860 +#define WLC_SET_SRL 32
9861 +#define WLC_GET_LRL 33
9862 +#define WLC_SET_LRL 34
9863 +#define WLC_GET_PLCPHDR 35
9864 +#define WLC_SET_PLCPHDR 36
9865 +#define WLC_GET_RADIO 37
9866 +#define WLC_SET_RADIO 38
9867 +#define WLC_GET_PHYTYPE 39
9868 +/* #define WLC_GET_WEP 42 */ /* no longer supported */
9869 +/* #define WLC_SET_WEP 43 */ /* no longer supported */
9870 +#define WLC_GET_KEY 44
9871 +#define WLC_SET_KEY 45
9872 +#define WLC_GET_REGULATORY 46
9873 +#define WLC_SET_REGULATORY 47
9874 +#define WLC_SCAN 50
9875 +#define WLC_SCAN_RESULTS 51
9876 +#define WLC_DISASSOC 52
9877 +#define WLC_REASSOC 53
9878 +#define WLC_GET_ROAM_TRIGGER 54
9879 +#define WLC_SET_ROAM_TRIGGER 55
9880 +#define WLC_GET_TXANT 61
9881 +#define WLC_SET_TXANT 62
9882 +#define WLC_GET_ANTDIV 63
9883 +#define WLC_SET_ANTDIV 64
9884 +/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
9885 +/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
9886 +#define WLC_GET_CLOSED 67
9887 +#define WLC_SET_CLOSED 68
9888 +#define WLC_GET_MACLIST 69
9889 +#define WLC_SET_MACLIST 70
9890 +#define WLC_GET_RATESET 71
9891 +#define WLC_SET_RATESET 72
9892 +#define WLC_GET_LOCALE 73
9893 +#define WLC_LONGTRAIN 74
9894 +#define WLC_GET_BCNPRD 75
9895 +#define WLC_SET_BCNPRD 76
9896 +#define WLC_GET_DTIMPRD 77
9897 +#define WLC_SET_DTIMPRD 78
9898 +#define WLC_GET_SROM 79
9899 +#define WLC_SET_SROM 80
9900 +#define WLC_GET_WEP_RESTRICT 81
9901 +#define WLC_SET_WEP_RESTRICT 82
9902 +#define WLC_GET_COUNTRY 83
9903 +#define WLC_SET_COUNTRY 84
9904 +#define WLC_GET_REVINFO 98
9905 +#define WLC_GET_MACMODE 105
9906 +#define WLC_SET_MACMODE 106
9907 +#define WLC_GET_GMODE 109
9908 +#define WLC_SET_GMODE 110
9909 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
9910 +#define WLC_GET_SCANSUPPRESS 115
9911 +#define WLC_SET_SCANSUPPRESS 116
9912 +#define WLC_GET_AP 117
9913 +#define WLC_SET_AP 118
9914 +#define WLC_GET_EAP_RESTRICT 119
9915 +#define WLC_SET_EAP_RESTRICT 120
9916 +#define WLC_GET_WDSLIST 123
9917 +#define WLC_SET_WDSLIST 124
9918 +#define WLC_GET_RSSI 127
9919 +#define WLC_GET_WSEC 133
9920 +#define WLC_SET_WSEC 134
9921 +#define WLC_GET_BSS_INFO 136
9922 +#define WLC_GET_LAZYWDS 138
9923 +#define WLC_SET_LAZYWDS 139
9924 +#define WLC_GET_BANDLIST 140
9925 +#define WLC_GET_BAND 141
9926 +#define WLC_SET_BAND 142
9927 +#define WLC_GET_SHORTSLOT 144
9928 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
9929 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
9930 +#define WLC_GET_SHORTSLOT_RESTRICT 147
9931 +#define WLC_SET_SHORTSLOT_RESTRICT 148
9932 +#define WLC_GET_GMODE_PROTECTION 149
9933 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
9934 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
9935 +#define WLC_UPGRADE 152
9936 +/* #define WLC_GET_MRATE 153 */ /* no longer supported */
9937 +/* #define WLC_SET_MRATE 154 */ /* no longer supported */
9938 +#define WLC_GET_ASSOCLIST 159
9939 +#define WLC_GET_CLK 160
9940 +#define WLC_SET_CLK 161
9941 +#define WLC_GET_UP 162
9942 +#define WLC_OUT 163
9943 +#define WLC_GET_WPA_AUTH 164
9944 +#define WLC_SET_WPA_AUTH 165
9945 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
9946 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
9947 +#define WLC_GET_PHYLIST 180
9948 +#define WLC_GET_KEY_SEQ 183
9949 +#define WLC_GET_GMODE_PROTECTION_CTS 198
9950 +#define WLC_SET_GMODE_PROTECTION_CTS 199
9951 +#define WLC_GET_PIOMODE 203
9952 +#define WLC_SET_PIOMODE 204
9953 +#define WLC_SET_LED 209
9954 +#define WLC_GET_LED 210
9955 +#define WLC_GET_CHANNEL_SEL 215
9956 +#define WLC_START_CHANNEL_SEL 216
9957 +#define WLC_GET_VALID_CHANNELS 217
9958 +#define WLC_GET_FAKEFRAG 218
9959 +#define WLC_SET_FAKEFRAG 219
9960 +#define WLC_GET_WET 230
9961 +#define WLC_SET_WET 231
9962 +#define WLC_GET_KEY_PRIMARY 235
9963 +#define WLC_SET_KEY_PRIMARY 236
9964 +#define WLC_GET_RADAR 242
9965 +#define WLC_SET_RADAR 243
9966 +#define WLC_SET_SPECT_MANAGMENT 244
9967 +#define WLC_GET_SPECT_MANAGMENT 245
9968 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
9969 +#define WLC_SET_CS_SCAN_TIMER 248
9970 +#define WLC_GET_CS_SCAN_TIMER 249
9971 +#define WLC_SEND_PWR_CONSTRAINT 254
9972 +#define WLC_CURRENT_PWR 256
9973 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
9974 +#define WLC_GET_COUNTRY_LIST 261
9975 +#define WLC_GET_VAR 262 /* get value of named variable */
9976 +#define WLC_SET_VAR 263 /* set named variable to value */
9977 +#define WLC_NVRAM_GET 264
9978 +#define WLC_NVRAM_SET 265
9979 +#define WLC_SET_WSEC_PMK 268
9980 +#define WLC_GET_AUTH_MODE 269
9981 +#define WLC_SET_AUTH_MODE 270
9982 +#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
9983 +#define WLC_NVOTPW 274
9984 +/* #define WLC_OTPW 275 */ /* no longer supported */
9985 +#define WLC_SET_LOCALE 278
9986 +#define WLC_LAST 279 /* do not change - use get_var/set_var */
9987 +
9988 +/*
9989 + * Minor kludge alert:
9990 + * Duplicate a few definitions that irelay requires from epiioctl.h here
9991 + * so caller doesn't have to include this file and epiioctl.h .
9992 + * If this grows any more, it would be time to move these irelay-specific
9993 + * definitions out of the epiioctl.h and into a separate driver common file.
9994 + */
9995 +#ifndef EPICTRL_COOKIE
9996 +#define EPICTRL_COOKIE 0xABADCEDE
9997 +#endif
9998 +
9999 +/* vx wlc ioctl's offset */
10000 +#define CMN_IOCTL_OFF 0x180
10001 +
10002 +/*
10003 + * custom OID support
10004 + *
10005 + * 0xFF - implementation specific OID
10006 + * 0xE4 - first byte of Broadcom PCI vendor ID
10007 + * 0x14 - second byte of Broadcom PCI vendor ID
10008 + * 0xXX - the custom OID number
10009 + */
10010 +
10011 +/* begin 0x1f values beyond the start of the ET driver range. */
10012 +#define WL_OID_BASE 0xFFE41420
10013 +
10014 +/* NDIS overrides */
10015 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
10016 +#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
10017 +
10018 +#define WL_DECRYPT_STATUS_SUCCESS 1
10019 +#define WL_DECRYPT_STATUS_FAILURE 2
10020 +#define WL_DECRYPT_STATUS_UNKNOWN 3
10021 +
10022 +/* allows user-mode app to poll the status of USB image upgrade */
10023 +#define WLC_UPGRADE_SUCCESS 0
10024 +#define WLC_UPGRADE_PENDING 1
10025 +
10026 +#ifdef CONFIG_USBRNDIS_RETAIL
10027 +/* struct passed in for WLC_NDCONFIG_ITEM */
10028 +typedef struct {
10029 + char *name;
10030 + void *param;
10031 +} ndconfig_item_t;
10032 +#endif
10033 +
10034 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
10035 +#define WL_RADIO_SW_DISABLE (1<<0)
10036 +#define WL_RADIO_HW_DISABLE (1<<1)
10037 +#define WL_RADIO_MPC_DISABLE (1<<2)
10038 +#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
10039 +
10040 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
10041 +#define WL_TXPWR_OVERRIDE (1<<31)
10042 +
10043 +/* "diag" iovar argument and error code */
10044 +#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
10045 +#define WL_DIAG_MEMORY 3 /* d11 memory test */
10046 +#define WL_DIAG_LED 4 /* LED test */
10047 +#define WL_DIAG_REG 5 /* d11/phy register test */
10048 +#define WL_DIAG_SROM 6 /* srom read/crc test */
10049 +#define WL_DIAG_DMA 7 /* DMA test */
10050 +
10051 +#define WL_DIAGERR_SUCCESS 0
10052 +#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
10053 +#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
10054 +#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
10055 +#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
10056 +#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
10057 +#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
10058 +#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
10059 +#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
10060 +#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
10061 +#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
10062 +
10063 +/* Bus types */
10064 +#define WL_SB_BUS 0 /* Silicon Backplane */
10065 +#define WL_PCI_BUS 1 /* PCI target */
10066 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
10067 +
10068 +/* band types */
10069 +#define WLC_BAND_AUTO 0 /* auto-select */
10070 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
10071 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
10072 +#define WLC_BAND_ALL 3 /* all bands */
10073 +
10074 +/* phy types (returned by WLC_GET_PHYTPE) */
10075 +#define WLC_PHY_TYPE_A 0
10076 +#define WLC_PHY_TYPE_B 1
10077 +#define WLC_PHY_TYPE_G 2
10078 +#define WLC_PHY_TYPE_NULL 0xf
10079 +
10080 +/* MAC list modes */
10081 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
10082 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
10083 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
10084 +
10085 +/*
10086 + *
10087 + */
10088 +#define GMODE_LEGACY_B 0
10089 +#define GMODE_AUTO 1
10090 +#define GMODE_ONLY 2
10091 +#define GMODE_B_DEFERRED 3
10092 +#define GMODE_PERFORMANCE 4
10093 +#define GMODE_LRS 5
10094 +#define GMODE_MAX 6
10095 +
10096 +/* values for PLCPHdr_override */
10097 +#define WLC_PLCP_AUTO -1
10098 +#define WLC_PLCP_SHORT 0
10099 +#define WLC_PLCP_LONG 1
10100 +
10101 +/* values for g_protection_override */
10102 +#define WLC_G_PROTECTION_AUTO -1
10103 +#define WLC_G_PROTECTION_OFF 0
10104 +#define WLC_G_PROTECTION_ON 1
10105 +
10106 +/* values for g_protection_control */
10107 +#define WLC_G_PROTECTION_CTL_OFF 0
10108 +#define WLC_G_PROTECTION_CTL_LOCAL 1
10109 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
10110 +
10111 +/* Values for PM */
10112 +#define PM_OFF 0
10113 +#define PM_MAX 1
10114 +#define PM_FAST 2
10115 +
10116 +
10117 +
10118 +typedef struct {
10119 + int npulses; /* required number of pulses at n * t_int */
10120 + int ncontig; /* required number of pulses at t_int */
10121 + int min_pw; /* minimum pulse width (20 MHz clocks) */
10122 + int max_pw; /* maximum pulse width (20 MHz clocks) */
10123 + uint16 thresh0; /* Radar detection, thresh 0 */
10124 + uint16 thresh1; /* Radar detection, thresh 1 */
10125 +} wl_radar_args_t;
10126 +
10127 +/* radar iovar SET defines */
10128 +#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
10129 +#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
10130 +#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
10131 +
10132 +/* dfs_status iovar-related defines */
10133 +
10134 +/* cac - channel availability check,
10135 + * ism - in-service monitoring
10136 + * csa - channel switching anouncement
10137 + */
10138 +
10139 +/* cac state values */
10140 +#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
10141 +#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
10142 +#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
10143 +#define WL_DFS_CACSTATE_CSA 3 /* csa */
10144 +#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
10145 +#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
10146 +#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
10147 +#define WL_DFS_CACSTATES 7 /* this many states exist */
10148 +
10149 +/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
10150 +typedef struct {
10151 + uint state; /* noted by WL_DFS_CACSTATE_XX. */
10152 + uint duration; /* time spent in ms in state. */
10153 + /* as dfs enters ISM state, it removes the operational channel from quiet channel list
10154 + * and notes the channel in channel_cleared. set to 0 if no channel is cleared
10155 + */
10156 + uint channel_cleared;
10157 +} wl_dfs_status_t;
10158 +
10159 +#define NUM_PWRCTRL_RATES 12
10160 +
10161 +
10162 +/* 802.11h enforcement levels */
10163 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
10164 +#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
10165 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
10166 +#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
10167 +
10168 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
10169 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
10170 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
10171 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
10172 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
10173 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
10174 +
10175 +#define WL_MPC_VAL 0x00400000
10176 +#define WL_APSTA_VAL 0x00800000
10177 +#define WL_DFS_VAL 0x01000000
10178 +
10179 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
10180 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
10181 +
10182 +/* led per-pin behaviors */
10183 +#define WL_LED_OFF 0 /* always off */
10184 +#define WL_LED_ON 1 /* always on */
10185 +#define WL_LED_ACTIVITY 2 /* activity */
10186 +#define WL_LED_RADIO 3 /* radio enabled */
10187 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
10188 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
10189 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
10190 +#define WL_LED_WI1 7
10191 +#define WL_LED_WI2 8
10192 +#define WL_LED_WI3 9
10193 +#define WL_LED_ASSOC 10 /* associated state indicator */
10194 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
10195 +#define WL_LED_NUMBEHAVIOR 12
10196 +
10197 +/* led behavior numeric value format */
10198 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
10199 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
10200 +
10201 +
10202 +/* WDS link local endpoint WPA role */
10203 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
10204 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
10205 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
10206 +
10207 +/* number of bytes needed to define a 128-bit mask for MAC event reporting */
10208 +#define WL_EVENTING_MASK_LEN 16
10209 +
10210 +/* Structures and constants used for "vndr_ie" IOVar interface */
10211 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
10212 +
10213 +/* 802.11 Mgmt Packet flags */
10214 +#define VNDR_IE_BEACON_FLAG 0x1
10215 +#define VNDR_IE_PRBRSP_FLAG 0x2
10216 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
10217 +#define VNDR_IE_AUTHRSP_FLAG 0x8
10218 +
10219 +typedef struct {
10220 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
10221 + vndr_ie_t vndr_ie_data; /* vendor IE data */
10222 +} vndr_ie_info_t;
10223 +
10224 +typedef struct {
10225 + int iecount; /* number of entries in the vndr_ie_list[] array */
10226 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
10227 +} vndr_ie_buf_t;
10228 +
10229 +typedef struct {
10230 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
10231 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
10232 +} vndr_ie_setbuf_t;
10233 +
10234 +/* join target preference types */
10235 +#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
10236 +#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
10237 +#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
10238 +
10239 +/* band preference */
10240 +#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
10241 + /* others use WLC_BAND_XXXX as values */
10242 +
10243 +/* any multicast cipher suite */
10244 +#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
10245 +
10246 +#if !defined(__GNUC__)
10247 +#pragma pack(pop)
10248 +#endif
10249 +
10250 +#define NFIFO 6 /* # tx/rx fifopairs */
10251 +
10252 +#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
10253 +
10254 +typedef struct {
10255 + uint16 version; /* see definition of WL_CNT_T_VERSION */
10256 + uint16 length; /* length of entire structure */
10257 +
10258 + /* transmit stat counters */
10259 + uint32 txframe; /* tx data frames */
10260 + uint32 txbyte; /* tx data bytes */
10261 + uint32 txretrans; /* tx mac retransmits */
10262 + uint32 txerror; /* tx data errors */
10263 + uint32 txctl; /* tx management frames */
10264 + uint32 txprshort; /* tx short preamble frames */
10265 + uint32 txserr; /* tx status errors */
10266 + uint32 txnobuf; /* tx out of buffers errors */
10267 + uint32 txnoassoc; /* tx discard because we're not associated */
10268 + uint32 txrunt; /* tx runt frames */
10269 + uint32 txchit; /* tx header cache hit (fastpath) */
10270 + uint32 txcmiss; /* tx header cache miss (slowpath) */
10271 +
10272 + /* transmit chip error counters */
10273 + uint32 txuflo; /* tx fifo underflows */
10274 + uint32 txphyerr; /* tx phy errors (indicated in tx status) */
10275 + uint32 txphycrs;
10276 +
10277 + /* receive stat counters */
10278 + uint32 rxframe; /* rx data frames */
10279 + uint32 rxbyte; /* rx data bytes */
10280 + uint32 rxerror; /* rx data errors */
10281 + uint32 rxctl; /* rx management frames */
10282 + uint32 rxnobuf; /* rx out of buffers errors */
10283 + uint32 rxnondata; /* rx non data frames in the data channel errors */
10284 + uint32 rxbadds; /* rx bad DS errors */
10285 + uint32 rxbadcm; /* rx bad control or management frames */
10286 + uint32 rxfragerr; /* rx fragmentation errors */
10287 + uint32 rxrunt; /* rx runt frames */
10288 + uint32 rxgiant; /* rx giant frames */
10289 + uint32 rxnoscb; /* rx no scb error */
10290 + uint32 rxbadproto; /* rx invalid frames */
10291 + uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
10292 + uint32 rxbadda; /* rx frames tossed for invalid da */
10293 + uint32 rxfilter; /* rx frames filtered out */
10294 +
10295 + /* receive chip error counters */
10296 + uint32 rxoflo; /* rx fifo overflow errors */
10297 + uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
10298 +
10299 + uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
10300 + uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
10301 + uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
10302 +
10303 + /* misc counters */
10304 + uint32 dmade; /* tx/rx dma descriptor errors */
10305 + uint32 dmada; /* tx/rx dma data errors */
10306 + uint32 dmape; /* tx/rx dma descriptor protocol errors */
10307 + uint32 reset; /* reset count */
10308 + uint32 tbtt; /* cnts the TBTT int's */
10309 + uint32 txdmawar;
10310 +
10311 + /* MAC counters: 32-bit version of d11.h's macstat_t */
10312 + uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
10313 + Control Management (includes retransmissions) */
10314 + uint32 txrtsfrm; /* number of RTS sent out by the MAC */
10315 + uint32 txctsfrm; /* number of CTS sent out by the MAC */
10316 + uint32 txackfrm; /* number of ACK frames sent out */
10317 + uint32 txdnlfrm; /* Not used */
10318 + uint32 txbcnfrm; /* beacons transmitted */
10319 + uint32 txfunfl[8]; /* per-fifo tx underflows */
10320 + uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
10321 + uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
10322 + driver enqueued frames*/
10323 + uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
10324 + uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
10325 + uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
10326 + data/control/management*/
10327 + uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
10328 + uint32 rxbadplcp; /* parity check of the PLCP header failed */
10329 + uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
10330 + uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
10331 + uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
10332 + uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
10333 + uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
10334 + uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
10335 + uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
10336 + uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
10337 + uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
10338 + uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
10339 + uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
10340 + uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
10341 + uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
10342 + uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
10343 + uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
10344 + uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
10345 + to see these) */
10346 + uint32 rxbeaconmbss; /* beacons received from member of BSS */
10347 + uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
10348 + uint32 rxbeaconobss; /* beacons received from other BSS */
10349 + uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
10350 + response */
10351 + uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
10352 + uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
10353 + uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
10354 + uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
10355 + uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
10356 + uint32 pmqovfl; /* Number of PMQ overflows */
10357 + uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
10358 + uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
10359 + uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
10360 + uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
10361 + uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
10362 + a probe response could not be sent out within the time limit defined
10363 + in M_PRS_MAXTIME */
10364 + uint32 rxnack; /* Number of NACKS received (Afterburner) */
10365 + uint32 frmscons; /* Number of frames completed without transmission because of an
10366 + Afterburner re-queue */
10367 + uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
10368 + uint32 txglitch_nack; /* obsolete */
10369 + uint32 txburst; /* obsolete */
10370 + uint32 rxburst; /* obsolete */
10371 +
10372 + /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
10373 + uint32 txfrag; /* dot11TransmittedFragmentCount */
10374 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
10375 + uint32 txfail; /* dot11FailedCount */
10376 + uint32 txretry; /* dot11RetryCount */
10377 + uint32 txretrie; /* dot11MultipleRetryCount */
10378 + uint32 rxdup; /* dot11FrameduplicateCount */
10379 + uint32 txrts; /* dot11RTSSuccessCount */
10380 + uint32 txnocts; /* dot11RTSFailureCount */
10381 + uint32 txnoack; /* dot11ACKFailureCount */
10382 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
10383 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
10384 + uint32 rxcrc; /* dot11FCSErrorCount */
10385 + uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
10386 + uint32 rxundec; /* dot11WEPUndecryptableCount */
10387 +
10388 + /* WPA2 counters (see rxundec for DecryptFailureCount) */
10389 + uint32 tkipmicfaill; /* TKIPLocalMICFailures */
10390 + uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
10391 + uint32 tkipreplay; /* TKIPReplays */
10392 + uint32 ccmpfmterr; /* CCMPFormatErrors */
10393 + uint32 ccmpreplay; /* CCMPReplays */
10394 + uint32 ccmpundec; /* CCMPDecryptErrors */
10395 + uint32 fourwayfail; /* FourWayHandshakeFailures */
10396 + uint32 wepundec; /* dot11WEPUndecryptableCount */
10397 + uint32 wepicverr; /* dot11WEPICVErrorCount */
10398 + uint32 decsuccess; /* DecryptSuccessCount */
10399 + uint32 tkipicverr; /* TKIPICVErrorCount */
10400 + uint32 wepexcluded; /* dot11WEPExcludedCount */
10401 +} wl_cnt_t;
10402 +
10403 +#endif /* _wlioctl_h_ */
10404 diff -Nur linux-2.4.32/arch/mips/bcm947xx/Makefile linux-2.4.32-brcm/arch/mips/bcm947xx/Makefile
10405 --- linux-2.4.32/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
10406 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/Makefile 2005-12-19 01:56:51.733868750 +0100
10407 @@ -0,0 +1,15 @@
10408 +#
10409 +# Makefile for the BCM947xx specific kernel interface routines
10410 +# under Linux.
10411 +#
10412 +
10413 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
10414 +
10415 +O_TARGET := bcm947xx.o
10416 +
10417 +export-objs := nvram_linux.o setup.o
10418 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
10419 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
10420 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
10421 +
10422 +include $(TOPDIR)/Rules.make
10423 diff -Nur linux-2.4.32/arch/mips/bcm947xx/nvram.c linux-2.4.32-brcm/arch/mips/bcm947xx/nvram.c
10424 --- linux-2.4.32/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
10425 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/nvram.c 2005-12-19 01:05:00.079582750 +0100
10426 @@ -0,0 +1,320 @@
10427 +/*
10428 + * NVRAM variable manipulation (common)
10429 + *
10430 + * Copyright 2004, Broadcom Corporation
10431 + * All Rights Reserved.
10432 + *
10433 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10434 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10435 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10436 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10437 + *
10438 + */
10439 +
10440 +#include <typedefs.h>
10441 +#include <osl.h>
10442 +#include <bcmendian.h>
10443 +#include <bcmnvram.h>
10444 +#include <bcmutils.h>
10445 +#include <sbsdram.h>
10446 +
10447 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
10448 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
10449 +extern int BCMINIT(_nvram_read)(void *buf);
10450 +
10451 +char * BCMINIT(_nvram_get)(const char *name);
10452 +int BCMINIT(_nvram_set)(const char *name, const char *value);
10453 +int BCMINIT(_nvram_unset)(const char *name);
10454 +int BCMINIT(_nvram_getall)(char *buf, int count);
10455 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
10456 +int BCMINIT(_nvram_init)(void);
10457 +void BCMINIT(_nvram_exit)(void);
10458 +
10459 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
10460 +static struct nvram_tuple * nvram_dead;
10461 +
10462 +/* Free all tuples. Should be locked. */
10463 +static void
10464 +BCMINITFN(nvram_free)(void)
10465 +{
10466 + uint i;
10467 + struct nvram_tuple *t, *next;
10468 +
10469 + /* Free hash table */
10470 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10471 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
10472 + next = t->next;
10473 + BCMINIT(_nvram_free)(t);
10474 + }
10475 + BCMINIT(nvram_hash)[i] = NULL;
10476 + }
10477 +
10478 + /* Free dead table */
10479 + for (t = nvram_dead; t; t = next) {
10480 + next = t->next;
10481 + BCMINIT(_nvram_free)(t);
10482 + }
10483 + nvram_dead = NULL;
10484 +
10485 + /* Indicate to per-port code that all tuples have been freed */
10486 + BCMINIT(_nvram_free)(NULL);
10487 +}
10488 +
10489 +/* String hash */
10490 +static INLINE uint
10491 +hash(const char *s)
10492 +{
10493 + uint hash = 0;
10494 +
10495 + while (*s)
10496 + hash = 31 * hash + *s++;
10497 +
10498 + return hash;
10499 +}
10500 +
10501 +/* (Re)initialize the hash table. Should be locked. */
10502 +static int
10503 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
10504 +{
10505 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
10506 +
10507 + /* (Re)initialize hash table */
10508 + BCMINIT(nvram_free)();
10509 +
10510 + /* Parse and set "name=value\0 ... \0\0" */
10511 + name = (char *) &header[1];
10512 + end = (char *) header + NVRAM_SPACE - 2;
10513 + end[0] = end[1] = '\0';
10514 + for (; *name; name = value + strlen(value) + 1) {
10515 + if (!(eq = strchr(name, '=')))
10516 + break;
10517 + *eq = '\0';
10518 + value = eq + 1;
10519 + BCMINIT(_nvram_set)(name, value);
10520 + *eq = '=';
10521 + }
10522 +
10523 + /* Set special SDRAM parameters */
10524 + if (!BCMINIT(_nvram_get)("sdram_init")) {
10525 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
10526 + BCMINIT(_nvram_set)("sdram_init", buf);
10527 + }
10528 + if (!BCMINIT(_nvram_get)("sdram_config")) {
10529 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
10530 + BCMINIT(_nvram_set)("sdram_config", buf);
10531 + }
10532 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
10533 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
10534 + BCMINIT(_nvram_set)("sdram_refresh", buf);
10535 + }
10536 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
10537 + sprintf(buf, "0x%08X", header->config_ncdl);
10538 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
10539 + }
10540 +
10541 + return 0;
10542 +}
10543 +
10544 +/* Get the value of an NVRAM variable. Should be locked. */
10545 +char *
10546 +BCMINITFN(_nvram_get)(const char *name)
10547 +{
10548 + uint i;
10549 + struct nvram_tuple *t;
10550 + char *value;
10551 +
10552 + if (!name)
10553 + return NULL;
10554 +
10555 + /* Hash the name */
10556 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10557 +
10558 + /* Find the associated tuple in the hash table */
10559 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
10560 +
10561 + value = t ? t->value : NULL;
10562 +
10563 + return value;
10564 +}
10565 +
10566 +/* Get the value of an NVRAM variable. Should be locked. */
10567 +int
10568 +BCMINITFN(_nvram_set)(const char *name, const char *value)
10569 +{
10570 + uint i;
10571 + struct nvram_tuple *t, *u, **prev;
10572 +
10573 + /* Hash the name */
10574 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10575 +
10576 + /* Find the associated tuple in the hash table */
10577 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10578 +
10579 + /* (Re)allocate tuple */
10580 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
10581 + return -12; /* -ENOMEM */
10582 +
10583 + /* Value reallocated */
10584 + if (t && t == u)
10585 + return 0;
10586 +
10587 + /* Move old tuple to the dead table */
10588 + if (t) {
10589 + *prev = t->next;
10590 + t->next = nvram_dead;
10591 + nvram_dead = t;
10592 + }
10593 +
10594 + /* Add new tuple to the hash table */
10595 + u->next = BCMINIT(nvram_hash)[i];
10596 + BCMINIT(nvram_hash)[i] = u;
10597 +
10598 + return 0;
10599 +}
10600 +
10601 +/* Unset the value of an NVRAM variable. Should be locked. */
10602 +int
10603 +BCMINITFN(_nvram_unset)(const char *name)
10604 +{
10605 + uint i;
10606 + struct nvram_tuple *t, **prev;
10607 +
10608 + if (!name)
10609 + return 0;
10610 +
10611 + /* Hash the name */
10612 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10613 +
10614 + /* Find the associated tuple in the hash table */
10615 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10616 +
10617 + /* Move it to the dead table */
10618 + if (t) {
10619 + *prev = t->next;
10620 + t->next = nvram_dead;
10621 + nvram_dead = t;
10622 + }
10623 +
10624 + return 0;
10625 +}
10626 +
10627 +/* Get all NVRAM variables. Should be locked. */
10628 +int
10629 +BCMINITFN(_nvram_getall)(char *buf, int count)
10630 +{
10631 + uint i;
10632 + struct nvram_tuple *t;
10633 + int len = 0;
10634 +
10635 + bzero(buf, count);
10636 +
10637 + /* Write name=value\0 ... \0\0 */
10638 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10639 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10640 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
10641 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
10642 + else
10643 + break;
10644 + }
10645 + }
10646 +
10647 + return 0;
10648 +}
10649 +
10650 +/* Regenerate NVRAM. Should be locked. */
10651 +int
10652 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
10653 +{
10654 + char *init, *config, *refresh, *ncdl;
10655 + char *ptr, *end;
10656 + int i;
10657 + struct nvram_tuple *t;
10658 + struct nvram_header tmp;
10659 + uint8 crc;
10660 +
10661 + /* Regenerate header */
10662 + header->magic = NVRAM_MAGIC;
10663 + header->crc_ver_init = (NVRAM_VERSION << 8);
10664 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
10665 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
10666 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
10667 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
10668 + header->crc_ver_init |= SDRAM_INIT << 16;
10669 + header->config_refresh = SDRAM_CONFIG;
10670 + header->config_refresh |= SDRAM_REFRESH << 16;
10671 + header->config_ncdl = 0;
10672 + } else {
10673 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
10674 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
10675 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
10676 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
10677 + }
10678 +
10679 + /* Clear data area */
10680 + ptr = (char *) header + sizeof(struct nvram_header);
10681 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
10682 +
10683 + /* Leave space for a double NUL at the end */
10684 + end = (char *) header + NVRAM_SPACE - 2;
10685 +
10686 + /* Write out all tuples */
10687 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10688 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10689 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
10690 + break;
10691 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
10692 + }
10693 + }
10694 +
10695 + /* End with a double NUL */
10696 + ptr += 2;
10697 +
10698 + /* Set new length */
10699 + header->len = ROUNDUP(ptr - (char *) header, 4);
10700 +
10701 + /* Little-endian CRC8 over the last 11 bytes of the header */
10702 + tmp.crc_ver_init = htol32(header->crc_ver_init);
10703 + tmp.config_refresh = htol32(header->config_refresh);
10704 + tmp.config_ncdl = htol32(header->config_ncdl);
10705 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
10706 +
10707 + /* Continue CRC8 over data bytes */
10708 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
10709 +
10710 + /* Set new CRC8 */
10711 + header->crc_ver_init |= crc;
10712 +
10713 + /* Reinitialize hash table */
10714 + return BCMINIT(nvram_rehash)(header);
10715 +}
10716 +
10717 +/* Initialize hash table. Should be locked. */
10718 +int
10719 +BCMINITFN(_nvram_init)(void)
10720 +{
10721 + struct nvram_header *header;
10722 + int ret;
10723 + void *osh;
10724 +
10725 + /* get kernel osl handler */
10726 + osh = osl_attach(NULL);
10727 +
10728 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
10729 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
10730 + return -12; /* -ENOMEM */
10731 + }
10732 +
10733 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
10734 + header->magic == NVRAM_MAGIC)
10735 + BCMINIT(nvram_rehash)(header);
10736 +
10737 + MFREE(osh, header, NVRAM_SPACE);
10738 + return ret;
10739 +}
10740 +
10741 +/* Free hash table. Should be locked. */
10742 +void
10743 +BCMINITFN(_nvram_exit)(void)
10744 +{
10745 + BCMINIT(nvram_free)();
10746 +}
10747 diff -Nur linux-2.4.32/arch/mips/bcm947xx/nvram_linux.c linux-2.4.32-brcm/arch/mips/bcm947xx/nvram_linux.c
10748 --- linux-2.4.32/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
10749 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/nvram_linux.c 2005-12-19 01:09:59.782313000 +0100
10750 @@ -0,0 +1,653 @@
10751 +/*
10752 + * NVRAM variable manipulation (Linux kernel half)
10753 + *
10754 + * Copyright 2005, Broadcom Corporation
10755 + * All Rights Reserved.
10756 + *
10757 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10758 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10759 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10760 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10761 + *
10762 + */
10763 +
10764 +#include <linux/config.h>
10765 +#include <linux/init.h>
10766 +#include <linux/module.h>
10767 +#include <linux/kernel.h>
10768 +#include <linux/string.h>
10769 +#include <linux/interrupt.h>
10770 +#include <linux/spinlock.h>
10771 +#include <linux/slab.h>
10772 +#include <linux/bootmem.h>
10773 +#include <linux/wrapper.h>
10774 +#include <linux/fs.h>
10775 +#include <linux/miscdevice.h>
10776 +#include <linux/mtd/mtd.h>
10777 +#include <asm/addrspace.h>
10778 +#include <asm/io.h>
10779 +#include <asm/uaccess.h>
10780 +
10781 +#include <typedefs.h>
10782 +#include <bcmendian.h>
10783 +#include <bcmnvram.h>
10784 +#include <bcmutils.h>
10785 +#include <sbconfig.h>
10786 +#include <sbchipc.h>
10787 +#include <sbutils.h>
10788 +#include <sbmips.h>
10789 +#include <sflash.h>
10790 +
10791 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
10792 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
10793 +
10794 +#ifdef MODULE
10795 +
10796 +#define early_nvram_get(name) nvram_get(name)
10797 +
10798 +#else /* !MODULE */
10799 +
10800 +/* Global SB handle */
10801 +extern void *bcm947xx_sbh;
10802 +extern spinlock_t bcm947xx_sbh_lock;
10803 +
10804 +static int cfe_env;
10805 +extern char *cfe_env_get(char *nv_buf, const char *name);
10806 +
10807 +/* Convenience */
10808 +#define sbh bcm947xx_sbh
10809 +#define sbh_lock bcm947xx_sbh_lock
10810 +#define KB * 1024
10811 +#define MB * 1024 * 1024
10812 +
10813 +/* Probe for NVRAM header */
10814 +static void __init
10815 +early_nvram_init(void)
10816 +{
10817 + struct nvram_header *header;
10818 + chipcregs_t *cc;
10819 + struct sflash *info = NULL;
10820 + int i;
10821 + uint32 base, off, lim;
10822 + u32 *src, *dst;
10823 +
10824 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10825 + base = KSEG1ADDR(SB_FLASH2);
10826 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
10827 + case PFLASH:
10828 + lim = SB_FLASH2_SZ;
10829 + break;
10830 +
10831 + case SFLASH_ST:
10832 + case SFLASH_AT:
10833 + if ((info = sflash_init(cc)) == NULL)
10834 + return;
10835 + lim = info->size;
10836 + break;
10837 +
10838 + case FLASH_NONE:
10839 + default:
10840 + return;
10841 + }
10842 + } else {
10843 + /* extif assumed, Stop at 4 MB */
10844 + base = KSEG1ADDR(SB_FLASH1);
10845 + lim = SB_FLASH1_SZ;
10846 + }
10847 +
10848 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
10849 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
10850 + dst = (u32 *) nvram_buf;
10851 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
10852 + printk("early_nvram_init: WGT634U NVRAM found.\n");
10853 +
10854 + for (i = 0; i < 0x1ff0; i++) {
10855 + if (*src == 0xFFFFFFFF)
10856 + break;
10857 + *dst++ = *src++;
10858 + }
10859 + cfe_env = 1;
10860 + return;
10861 + }
10862 +
10863 + off = FLASH_MIN;
10864 + while (off <= lim) {
10865 + /* Windowed flash access */
10866 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
10867 + if (header->magic == NVRAM_MAGIC)
10868 + goto found;
10869 + off <<= 1;
10870 + }
10871 +
10872 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
10873 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
10874 + if (header->magic == NVRAM_MAGIC)
10875 + goto found;
10876 +
10877 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
10878 + if (header->magic == NVRAM_MAGIC)
10879 + goto found;
10880 +
10881 + printk("early_nvram_init: NVRAM not found\n");
10882 + return;
10883 +
10884 +found:
10885 + src = (u32 *) header;
10886 + dst = (u32 *) nvram_buf;
10887 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
10888 + *dst++ = *src++;
10889 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
10890 + *dst++ = ltoh32(*src++);
10891 +}
10892 +
10893 +/* Early (before mm or mtd) read-only access to NVRAM */
10894 +static char * __init
10895 +early_nvram_get(const char *name)
10896 +{
10897 + char *var, *value, *end, *eq;
10898 +
10899 + if (!name)
10900 + return NULL;
10901 +
10902 + /* Too early? */
10903 + if (sbh == NULL)
10904 + return NULL;
10905 +
10906 + if (!nvram_buf[0])
10907 + early_nvram_init();
10908 +
10909 + if (cfe_env)
10910 + return cfe_env_get(nvram_buf, name);
10911 +
10912 + /* Look for name=value and return value */
10913 + var = &nvram_buf[sizeof(struct nvram_header)];
10914 + end = nvram_buf + sizeof(nvram_buf) - 2;
10915 + end[0] = end[1] = '\0';
10916 + for (; *var; var = value + strlen(value) + 1) {
10917 + if (!(eq = strchr(var, '=')))
10918 + break;
10919 + value = eq + 1;
10920 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
10921 + return value;
10922 + }
10923 +
10924 + return NULL;
10925 +}
10926 +
10927 +#endif /* !MODULE */
10928 +
10929 +extern char * _nvram_get(const char *name);
10930 +extern int _nvram_set(const char *name, const char *value);
10931 +extern int _nvram_unset(const char *name);
10932 +extern int _nvram_getall(char *buf, int count);
10933 +extern int _nvram_commit(struct nvram_header *header);
10934 +extern int _nvram_init(void);
10935 +extern void _nvram_exit(void);
10936 +
10937 +/* Globals */
10938 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
10939 +static struct semaphore nvram_sem;
10940 +static unsigned long nvram_offset = 0;
10941 +static int nvram_major = -1;
10942 +static devfs_handle_t nvram_handle = NULL;
10943 +static struct mtd_info *nvram_mtd = NULL;
10944 +
10945 +int
10946 +_nvram_read(char *buf)
10947 +{
10948 + struct nvram_header *header = (struct nvram_header *) buf;
10949 + size_t len;
10950 +
10951 + if (!nvram_mtd ||
10952 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
10953 + len != NVRAM_SPACE ||
10954 + header->magic != NVRAM_MAGIC) {
10955 + /* Maybe we can recover some data from early initialization */
10956 + memcpy(buf, nvram_buf, NVRAM_SPACE);
10957 + }
10958 +
10959 + return 0;
10960 +}
10961 +
10962 +struct nvram_tuple *
10963 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
10964 +{
10965 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
10966 + return NULL;
10967 +
10968 + if (!t) {
10969 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
10970 + return NULL;
10971 +
10972 + /* Copy name */
10973 + t->name = (char *) &t[1];
10974 + strcpy(t->name, name);
10975 +
10976 + t->value = NULL;
10977 + }
10978 +
10979 + /* Copy value */
10980 + if (!t->value || strcmp(t->value, value)) {
10981 + t->value = &nvram_buf[nvram_offset];
10982 + strcpy(t->value, value);
10983 + nvram_offset += strlen(value) + 1;
10984 + }
10985 +
10986 + return t;
10987 +}
10988 +
10989 +void
10990 +_nvram_free(struct nvram_tuple *t)
10991 +{
10992 + if (!t)
10993 + nvram_offset = 0;
10994 + else
10995 + kfree(t);
10996 +}
10997 +
10998 +int
10999 +nvram_set(const char *name, const char *value)
11000 +{
11001 + unsigned long flags;
11002 + int ret;
11003 + struct nvram_header *header;
11004 +
11005 + spin_lock_irqsave(&nvram_lock, flags);
11006 + if ((ret = _nvram_set(name, value))) {
11007 + /* Consolidate space and try again */
11008 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
11009 + if (_nvram_commit(header) == 0)
11010 + ret = _nvram_set(name, value);
11011 + kfree(header);
11012 + }
11013 + }
11014 + spin_unlock_irqrestore(&nvram_lock, flags);
11015 +
11016 + return ret;
11017 +}
11018 +
11019 +char *
11020 +real_nvram_get(const char *name)
11021 +{
11022 + unsigned long flags;
11023 + char *value;
11024 +
11025 + spin_lock_irqsave(&nvram_lock, flags);
11026 + value = _nvram_get(name);
11027 + spin_unlock_irqrestore(&nvram_lock, flags);
11028 +
11029 + return value;
11030 +}
11031 +
11032 +char *
11033 +nvram_get(const char *name)
11034 +{
11035 + if (nvram_major >= 0)
11036 + return real_nvram_get(name);
11037 + else
11038 + return early_nvram_get(name);
11039 +}
11040 +
11041 +int
11042 +nvram_unset(const char *name)
11043 +{
11044 + unsigned long flags;
11045 + int ret;
11046 +
11047 + spin_lock_irqsave(&nvram_lock, flags);
11048 + ret = _nvram_unset(name);
11049 + spin_unlock_irqrestore(&nvram_lock, flags);
11050 +
11051 + return ret;
11052 +}
11053 +
11054 +static void
11055 +erase_callback(struct erase_info *done)
11056 +{
11057 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
11058 + wake_up(wait_q);
11059 +}
11060 +
11061 +int
11062 +nvram_commit(void)
11063 +{
11064 + char *buf;
11065 + size_t erasesize, len;
11066 + unsigned int i;
11067 + int ret;
11068 + struct nvram_header *header;
11069 + unsigned long flags;
11070 + u_int32_t offset;
11071 + DECLARE_WAITQUEUE(wait, current);
11072 + wait_queue_head_t wait_q;
11073 + struct erase_info erase;
11074 +
11075 + if (!nvram_mtd) {
11076 + printk("nvram_commit: NVRAM not found\n");
11077 + return -ENODEV;
11078 + }
11079 +
11080 + if (in_interrupt()) {
11081 + printk("nvram_commit: not committing in interrupt\n");
11082 + return -EINVAL;
11083 + }
11084 +
11085 + /* Backup sector blocks to be erased */
11086 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
11087 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
11088 + printk("nvram_commit: out of memory\n");
11089 + return -ENOMEM;
11090 + }
11091 +
11092 + down(&nvram_sem);
11093 +
11094 + if ((i = erasesize - NVRAM_SPACE) > 0) {
11095 + offset = nvram_mtd->size - erasesize;
11096 + len = 0;
11097 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
11098 + if (ret || len != i) {
11099 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
11100 + ret = -EIO;
11101 + goto done;
11102 + }
11103 + header = (struct nvram_header *)(buf + i);
11104 + } else {
11105 + offset = nvram_mtd->size - NVRAM_SPACE;
11106 + header = (struct nvram_header *)buf;
11107 + }
11108 +
11109 + /* Regenerate NVRAM */
11110 + spin_lock_irqsave(&nvram_lock, flags);
11111 + ret = _nvram_commit(header);
11112 + spin_unlock_irqrestore(&nvram_lock, flags);
11113 + if (ret)
11114 + goto done;
11115 +
11116 + /* Erase sector blocks */
11117 + init_waitqueue_head(&wait_q);
11118 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
11119 + erase.mtd = nvram_mtd;
11120 + erase.addr = offset;
11121 + erase.len = nvram_mtd->erasesize;
11122 + erase.callback = erase_callback;
11123 + erase.priv = (u_long) &wait_q;
11124 +
11125 + set_current_state(TASK_INTERRUPTIBLE);
11126 + add_wait_queue(&wait_q, &wait);
11127 +
11128 + /* Unlock sector blocks */
11129 + if (nvram_mtd->unlock)
11130 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
11131 +
11132 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
11133 + set_current_state(TASK_RUNNING);
11134 + remove_wait_queue(&wait_q, &wait);
11135 + printk("nvram_commit: erase error\n");
11136 + goto done;
11137 + }
11138 +
11139 + /* Wait for erase to finish */
11140 + schedule();
11141 + remove_wait_queue(&wait_q, &wait);
11142 + }
11143 +
11144 + /* Write partition up to end of data area */
11145 + offset = nvram_mtd->size - erasesize;
11146 + i = erasesize - NVRAM_SPACE + header->len;
11147 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
11148 + if (ret || len != i) {
11149 + printk("nvram_commit: write error\n");
11150 + ret = -EIO;
11151 + goto done;
11152 + }
11153 +
11154 + offset = nvram_mtd->size - erasesize;
11155 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
11156 +
11157 + done:
11158 + up(&nvram_sem);
11159 + kfree(buf);
11160 + return ret;
11161 +}
11162 +
11163 +int
11164 +nvram_getall(char *buf, int count)
11165 +{
11166 + unsigned long flags;
11167 + int ret;
11168 +
11169 + spin_lock_irqsave(&nvram_lock, flags);
11170 + ret = _nvram_getall(buf, count);
11171 + spin_unlock_irqrestore(&nvram_lock, flags);
11172 +
11173 + return ret;
11174 +}
11175 +
11176 +EXPORT_SYMBOL(nvram_get);
11177 +EXPORT_SYMBOL(nvram_getall);
11178 +EXPORT_SYMBOL(nvram_set);
11179 +EXPORT_SYMBOL(nvram_unset);
11180 +EXPORT_SYMBOL(nvram_commit);
11181 +
11182 +/* User mode interface below */
11183 +
11184 +static ssize_t
11185 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
11186 +{
11187 + char tmp[100], *name = tmp, *value;
11188 + ssize_t ret;
11189 + unsigned long off;
11190 +
11191 + if (count > sizeof(tmp)) {
11192 + if (!(name = kmalloc(count, GFP_KERNEL)))
11193 + return -ENOMEM;
11194 + }
11195 +
11196 + if (copy_from_user(name, buf, count)) {
11197 + ret = -EFAULT;
11198 + goto done;
11199 + }
11200 +
11201 + if (*name == '\0') {
11202 + /* Get all variables */
11203 + ret = nvram_getall(name, count);
11204 + if (ret == 0) {
11205 + if (copy_to_user(buf, name, count)) {
11206 + ret = -EFAULT;
11207 + goto done;
11208 + }
11209 + ret = count;
11210 + }
11211 + } else {
11212 + if (!(value = nvram_get(name))) {
11213 + ret = 0;
11214 + goto done;
11215 + }
11216 +
11217 + /* Provide the offset into mmap() space */
11218 + off = (unsigned long) value - (unsigned long) nvram_buf;
11219 +
11220 + if (put_user(off, (unsigned long *) buf)) {
11221 + ret = -EFAULT;
11222 + goto done;
11223 + }
11224 +
11225 + ret = sizeof(unsigned long);
11226 + }
11227 +
11228 + flush_cache_all();
11229 +
11230 +done:
11231 + if (name != tmp)
11232 + kfree(name);
11233 +
11234 + return ret;
11235 +}
11236 +
11237 +static ssize_t
11238 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
11239 +{
11240 + char tmp[100], *name = tmp, *value;
11241 + ssize_t ret;
11242 +
11243 + if (count > sizeof(tmp)) {
11244 + if (!(name = kmalloc(count, GFP_KERNEL)))
11245 + return -ENOMEM;
11246 + }
11247 +
11248 + if (copy_from_user(name, buf, count)) {
11249 + ret = -EFAULT;
11250 + goto done;
11251 + }
11252 +
11253 + value = name;
11254 + name = strsep(&value, "=");
11255 + if (value)
11256 + ret = nvram_set(name, value) ? : count;
11257 + else
11258 + ret = nvram_unset(name) ? : count;
11259 +
11260 + done:
11261 + if (name != tmp)
11262 + kfree(name);
11263 +
11264 + return ret;
11265 +}
11266 +
11267 +static int
11268 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
11269 +{
11270 + if (cmd != NVRAM_MAGIC)
11271 + return -EINVAL;
11272 + return nvram_commit();
11273 +}
11274 +
11275 +static int
11276 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
11277 +{
11278 + unsigned long offset = virt_to_phys(nvram_buf);
11279 +
11280 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
11281 + vma->vm_page_prot))
11282 + return -EAGAIN;
11283 +
11284 + return 0;
11285 +}
11286 +
11287 +static int
11288 +dev_nvram_open(struct inode *inode, struct file * file)
11289 +{
11290 + MOD_INC_USE_COUNT;
11291 + return 0;
11292 +}
11293 +
11294 +static int
11295 +dev_nvram_release(struct inode *inode, struct file * file)
11296 +{
11297 + MOD_DEC_USE_COUNT;
11298 + return 0;
11299 +}
11300 +
11301 +static struct file_operations dev_nvram_fops = {
11302 + owner: THIS_MODULE,
11303 + open: dev_nvram_open,
11304 + release: dev_nvram_release,
11305 + read: dev_nvram_read,
11306 + write: dev_nvram_write,
11307 + ioctl: dev_nvram_ioctl,
11308 + mmap: dev_nvram_mmap,
11309 +};
11310 +
11311 +static void
11312 +dev_nvram_exit(void)
11313 +{
11314 + int order = 0;
11315 + struct page *page, *end;
11316 +
11317 + if (nvram_handle)
11318 + devfs_unregister(nvram_handle);
11319 +
11320 + if (nvram_major >= 0)
11321 + devfs_unregister_chrdev(nvram_major, "nvram");
11322 +
11323 + if (nvram_mtd)
11324 + put_mtd_device(nvram_mtd);
11325 +
11326 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11327 + order++;
11328 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11329 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11330 + mem_map_unreserve(page);
11331 +
11332 + _nvram_exit();
11333 +}
11334 +
11335 +static int __init
11336 +dev_nvram_init(void)
11337 +{
11338 + int order = 0, ret = 0;
11339 + struct page *page, *end;
11340 + unsigned int i;
11341 +
11342 + /* Allocate and reserve memory to mmap() */
11343 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11344 + order++;
11345 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11346 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11347 + mem_map_reserve(page);
11348 +
11349 +#ifdef CONFIG_MTD
11350 + /* Find associated MTD device */
11351 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
11352 + nvram_mtd = get_mtd_device(NULL, i);
11353 + if (nvram_mtd) {
11354 + if (!strcmp(nvram_mtd->name, "nvram") &&
11355 + nvram_mtd->size >= NVRAM_SPACE)
11356 + break;
11357 + put_mtd_device(nvram_mtd);
11358 + }
11359 + }
11360 + if (i >= MAX_MTD_DEVICES)
11361 + nvram_mtd = NULL;
11362 +#endif
11363 +
11364 + /* Initialize hash table lock */
11365 + spin_lock_init(&nvram_lock);
11366 +
11367 + /* Initialize commit semaphore */
11368 + init_MUTEX(&nvram_sem);
11369 +
11370 + /* Register char device */
11371 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
11372 + ret = nvram_major;
11373 + goto err;
11374 + }
11375 +
11376 + /* Initialize hash table */
11377 + _nvram_init();
11378 +
11379 + /* Create /dev/nvram handle */
11380 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
11381 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
11382 +
11383 + /* Set the SDRAM NCDL value into NVRAM if not already done */
11384 + if (getintvar(NULL, "sdram_ncdl") == 0) {
11385 + unsigned int ncdl;
11386 + char buf[] = "0x00000000";
11387 +
11388 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
11389 + sprintf(buf, "0x%08x", ncdl);
11390 + nvram_set("sdram_ncdl", buf);
11391 + nvram_commit();
11392 + }
11393 + }
11394 +
11395 + return 0;
11396 +
11397 + err:
11398 + dev_nvram_exit();
11399 + return ret;
11400 +}
11401 +
11402 +module_init(dev_nvram_init);
11403 +module_exit(dev_nvram_exit);
11404 diff -Nur linux-2.4.32/arch/mips/bcm947xx/pcibios.c linux-2.4.32-brcm/arch/mips/bcm947xx/pcibios.c
11405 --- linux-2.4.32/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
11406 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/pcibios.c 2005-12-16 23:39:10.944836750 +0100
11407 @@ -0,0 +1,355 @@
11408 +/*
11409 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
11410 + *
11411 + * Copyright 2005, Broadcom Corporation
11412 + * All Rights Reserved.
11413 + *
11414 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11415 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11416 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11417 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11418 + *
11419 + * $Id$
11420 + */
11421 +
11422 +#include <linux/config.h>
11423 +#include <linux/types.h>
11424 +#include <linux/kernel.h>
11425 +#include <linux/sched.h>
11426 +#include <linux/pci.h>
11427 +#include <linux/init.h>
11428 +#include <linux/delay.h>
11429 +#include <asm/io.h>
11430 +#include <asm/irq.h>
11431 +#include <asm/paccess.h>
11432 +
11433 +#include <typedefs.h>
11434 +#include <bcmutils.h>
11435 +#include <sbconfig.h>
11436 +#include <sbutils.h>
11437 +#include <sbpci.h>
11438 +#include <pcicfg.h>
11439 +#include <bcmdevs.h>
11440 +#include <bcmnvram.h>
11441 +
11442 +/* Global SB handle */
11443 +extern sb_t *bcm947xx_sbh;
11444 +extern spinlock_t bcm947xx_sbh_lock;
11445 +
11446 +/* Convenience */
11447 +#define sbh bcm947xx_sbh
11448 +#define sbh_lock bcm947xx_sbh_lock
11449 +
11450 +static int
11451 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
11452 +{
11453 + unsigned long flags;
11454 + int ret;
11455 +
11456 + spin_lock_irqsave(&sbh_lock, flags);
11457 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11458 + spin_unlock_irqrestore(&sbh_lock, flags);
11459 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11460 +}
11461 +
11462 +static int
11463 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
11464 +{
11465 + unsigned long flags;
11466 + int ret;
11467 +
11468 + spin_lock_irqsave(&sbh_lock, flags);
11469 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11470 + spin_unlock_irqrestore(&sbh_lock, flags);
11471 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11472 +}
11473 +
11474 +static int
11475 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
11476 +{
11477 + unsigned long flags;
11478 + int ret;
11479 +
11480 + spin_lock_irqsave(&sbh_lock, flags);
11481 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11482 + spin_unlock_irqrestore(&sbh_lock, flags);
11483 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11484 +}
11485 +
11486 +static int
11487 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
11488 +{
11489 + unsigned long flags;
11490 + int ret;
11491 +
11492 + spin_lock_irqsave(&sbh_lock, flags);
11493 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11494 + spin_unlock_irqrestore(&sbh_lock, flags);
11495 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11496 +}
11497 +
11498 +static int
11499 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
11500 +{
11501 + unsigned long flags;
11502 + int ret;
11503 +
11504 + spin_lock_irqsave(&sbh_lock, flags);
11505 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11506 + spin_unlock_irqrestore(&sbh_lock, flags);
11507 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11508 +}
11509 +
11510 +static int
11511 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
11512 +{
11513 + unsigned long flags;
11514 + int ret;
11515 +
11516 + spin_lock_irqsave(&sbh_lock, flags);
11517 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11518 + spin_unlock_irqrestore(&sbh_lock, flags);
11519 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11520 +}
11521 +
11522 +static struct pci_ops pcibios_ops = {
11523 + sbpci_read_config_byte,
11524 + sbpci_read_config_word,
11525 + sbpci_read_config_dword,
11526 + sbpci_write_config_byte,
11527 + sbpci_write_config_word,
11528 + sbpci_write_config_dword
11529 +};
11530 +
11531 +
11532 +void __init
11533 +pcibios_init(void)
11534 +{
11535 + ulong flags;
11536 +
11537 + if (!(sbh = sb_kattach()))
11538 + panic("sb_kattach failed");
11539 + spin_lock_init(&sbh_lock);
11540 +
11541 + spin_lock_irqsave(&sbh_lock, flags);
11542 + sbpci_init(sbh);
11543 + spin_unlock_irqrestore(&sbh_lock, flags);
11544 +
11545 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11546 +
11547 + mdelay(300); //By Joey for Atheros Card
11548 +
11549 + /* Scan the SB bus */
11550 + pci_scan_bus(0, &pcibios_ops, NULL);
11551 +
11552 +}
11553 +
11554 +char * __init
11555 +pcibios_setup(char *str)
11556 +{
11557 + if (!strncmp(str, "ban=", 4)) {
11558 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
11559 + return NULL;
11560 + }
11561 +
11562 + return (str);
11563 +}
11564 +
11565 +static u32 pci_iobase = 0x100;
11566 +static u32 pci_membase = SB_PCI_DMA;
11567 +
11568 +void __init
11569 +pcibios_fixup_bus(struct pci_bus *b)
11570 +{
11571 + struct list_head *ln;
11572 + struct pci_dev *d;
11573 + struct resource *res;
11574 + int pos, size;
11575 + u32 *base;
11576 + u8 irq;
11577 +
11578 + printk("PCI: Fixing up bus %d\n", b->number);
11579 +
11580 + /* Fix up SB */
11581 + if (b->number == 0) {
11582 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11583 + d = pci_dev_b(ln);
11584 + /* Fix up interrupt lines */
11585 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
11586 + d->irq = irq + 2;
11587 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11588 + }
11589 + }
11590 +
11591 + /* Fix up external PCI */
11592 + else {
11593 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11594 + d = pci_dev_b(ln);
11595 + /* Fix up resource bases */
11596 + for (pos = 0; pos < 6; pos++) {
11597 + res = &d->resource[pos];
11598 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
11599 + if (res->end) {
11600 + size = res->end - res->start + 1;
11601 + if (*base & (size - 1))
11602 + *base = (*base + size) & ~(size - 1);
11603 + res->start = *base;
11604 + res->end = res->start + size - 1;
11605 + *base += size;
11606 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11607 + }
11608 + /* Fix up PCI bridge BAR0 only */
11609 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
11610 + break;
11611 + }
11612 + /* Fix up interrupt lines */
11613 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11614 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11615 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11616 + }
11617 + }
11618 +}
11619 +
11620 +unsigned int
11621 +pcibios_assign_all_busses(void)
11622 +{
11623 + return 1;
11624 +}
11625 +
11626 +void
11627 +pcibios_align_resource(void *data, struct resource *res,
11628 + unsigned long size, unsigned long align)
11629 +{
11630 +}
11631 +
11632 +int
11633 +pcibios_enable_resources(struct pci_dev *dev)
11634 +{
11635 + u16 cmd, old_cmd;
11636 + int idx;
11637 + struct resource *r;
11638 +
11639 + /* External PCI only */
11640 + if (dev->bus->number == 0)
11641 + return 0;
11642 +
11643 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11644 + old_cmd = cmd;
11645 + for(idx=0; idx<6; idx++) {
11646 + r = &dev->resource[idx];
11647 + if (r->flags & IORESOURCE_IO)
11648 + cmd |= PCI_COMMAND_IO;
11649 + if (r->flags & IORESOURCE_MEM)
11650 + cmd |= PCI_COMMAND_MEMORY;
11651 + }
11652 + if (dev->resource[PCI_ROM_RESOURCE].start)
11653 + cmd |= PCI_COMMAND_MEMORY;
11654 + if (cmd != old_cmd) {
11655 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
11656 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11657 + }
11658 + return 0;
11659 +}
11660 +
11661 +int
11662 +pcibios_enable_device(struct pci_dev *dev, int mask)
11663 +{
11664 + ulong flags;
11665 + uint coreidx;
11666 +
11667 + /* External PCI device enable */
11668 + if (dev->bus->number != 0)
11669 + return pcibios_enable_resources(dev);
11670 +
11671 + /* These cores come out of reset enabled */
11672 + if (dev->device == SB_MIPS ||
11673 + dev->device == SB_MIPS33 ||
11674 + dev->device == SB_EXTIF ||
11675 + dev->device == SB_CC)
11676 + return 0;
11677 +
11678 + spin_lock_irqsave(&sbh_lock, flags);
11679 + coreidx = sb_coreidx(sbh);
11680 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
11681 + return PCIBIOS_DEVICE_NOT_FOUND;
11682 +
11683 + /*
11684 + * The USB core requires a special bit to be set during core
11685 + * reset to enable host (OHCI) mode. Resetting the SB core in
11686 + * pcibios_enable_device() is a hack for compatibility with
11687 + * vanilla usb-ohci so that it does not have to know about
11688 + * SB. A driver that wants to use the USB core in device mode
11689 + * should know about SB and should reset the bit back to 0
11690 + * after calling pcibios_enable_device().
11691 + */
11692 + if (sb_coreid(sbh) == SB_USB) {
11693 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11694 + sb_core_reset(sbh, 1 << 29);
11695 + } else
11696 + sb_core_reset(sbh, 0);
11697 +
11698 + sb_setcoreidx(sbh, coreidx);
11699 + spin_unlock_irqrestore(&sbh_lock, flags);
11700 +
11701 + return 0;
11702 +}
11703 +
11704 +void
11705 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
11706 + struct resource *res, int resource)
11707 +{
11708 + unsigned long where, size;
11709 + u32 reg;
11710 +
11711 + /* External PCI only */
11712 + if (dev->bus->number == 0)
11713 + return;
11714 +
11715 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
11716 + size = res->end - res->start;
11717 + pci_read_config_dword(dev, where, &reg);
11718 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
11719 + pci_write_config_dword(dev, where, reg);
11720 +}
11721 +
11722 +static void __init
11723 +quirk_sbpci_bridge(struct pci_dev *dev)
11724 +{
11725 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11726 + return;
11727 +
11728 + printk("PCI: Fixing up bridge\n");
11729 +
11730 + /* Enable PCI bridge bus mastering and memory space */
11731 + pci_set_master(dev);
11732 + pcibios_enable_resources(dev);
11733 +
11734 + /* Enable PCI bridge BAR1 prefetch and burst */
11735 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11736 +}
11737 +
11738 +struct pci_fixup pcibios_fixups[] = {
11739 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
11740 + { 0 }
11741 +};
11742 +
11743 +/*
11744 + * If we set up a device for bus mastering, we need to check the latency
11745 + * timer as certain crappy BIOSes forget to set it properly.
11746 + */
11747 +unsigned int pcibios_max_latency = 255;
11748 +
11749 +void pcibios_set_master(struct pci_dev *dev)
11750 +{
11751 + u8 lat;
11752 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
11753 + if (lat < 16)
11754 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
11755 + else if (lat > pcibios_max_latency)
11756 + lat = pcibios_max_latency;
11757 + else
11758 + return;
11759 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
11760 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
11761 +}
11762 +
11763 diff -Nur linux-2.4.32/arch/mips/bcm947xx/prom.c linux-2.4.32-brcm/arch/mips/bcm947xx/prom.c
11764 --- linux-2.4.32/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11765 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/prom.c 2005-12-16 23:39:10.944836750 +0100
11766 @@ -0,0 +1,41 @@
11767 +/*
11768 + * Early initialization code for BCM94710 boards
11769 + *
11770 + * Copyright 2004, Broadcom Corporation
11771 + * All Rights Reserved.
11772 + *
11773 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11774 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11775 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11776 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11777 + *
11778 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
11779 + */
11780 +
11781 +#include <linux/config.h>
11782 +#include <linux/init.h>
11783 +#include <linux/kernel.h>
11784 +#include <linux/types.h>
11785 +#include <asm/bootinfo.h>
11786 +
11787 +void __init
11788 +prom_init(int argc, const char **argv)
11789 +{
11790 + unsigned long mem;
11791 +
11792 + mips_machgroup = MACH_GROUP_BRCM;
11793 + mips_machtype = MACH_BCM947XX;
11794 +
11795 + /* Figure out memory size by finding aliases */
11796 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11797 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11798 + *(unsigned long *)(prom_init))
11799 + break;
11800 + }
11801 + add_memory_region(0, mem, BOOT_MEM_RAM);
11802 +}
11803 +
11804 +void __init
11805 +prom_free_prom_memory(void)
11806 +{
11807 +}
11808 diff -Nur linux-2.4.32/arch/mips/bcm947xx/sbmips.c linux-2.4.32-brcm/arch/mips/bcm947xx/sbmips.c
11809 --- linux-2.4.32/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
11810 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/sbmips.c 2005-12-16 23:39:10.944836750 +0100
11811 @@ -0,0 +1,1038 @@
11812 +/*
11813 + * BCM47XX Sonics SiliconBackplane MIPS core routines
11814 + *
11815 + * Copyright 2005, Broadcom Corporation
11816 + * All Rights Reserved.
11817 + *
11818 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11819 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11820 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11821 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11822 + *
11823 + * $Id$
11824 + */
11825 +
11826 +#include <typedefs.h>
11827 +#include <osl.h>
11828 +#include <sbutils.h>
11829 +#include <bcmdevs.h>
11830 +#include <bcmnvram.h>
11831 +#include <bcmutils.h>
11832 +#include <hndmips.h>
11833 +#include <sbconfig.h>
11834 +#include <sbextif.h>
11835 +#include <sbchipc.h>
11836 +#include <sbmemc.h>
11837 +#include <mipsinc.h>
11838 +#include <sbutils.h>
11839 +
11840 +/*
11841 + * Returns TRUE if an external UART exists at the given base
11842 + * register.
11843 + */
11844 +static bool
11845 +BCMINITFN(serial_exists)(uint8 *regs)
11846 +{
11847 + uint8 save_mcr, status1;
11848 +
11849 + save_mcr = R_REG(&regs[UART_MCR]);
11850 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
11851 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
11852 + W_REG(&regs[UART_MCR], save_mcr);
11853 +
11854 + return (status1 == 0x90);
11855 +}
11856 +
11857 +/*
11858 + * Initializes UART access. The callback function will be called once
11859 + * per found UART.
11860 + */
11861 +void
11862 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
11863 +{
11864 + void *regs;
11865 + ulong base;
11866 + uint irq;
11867 + int i, n;
11868 +
11869 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
11870 + extifregs_t *eir = (extifregs_t *) regs;
11871 + sbconfig_t *sb;
11872 +
11873 + /* Determine external UART register base */
11874 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
11875 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
11876 +
11877 + /* Determine IRQ */
11878 + irq = sb_irq(sbh);
11879 +
11880 + /* Disable GPIO interrupt initially */
11881 + W_REG(&eir->gpiointpolarity, 0);
11882 + W_REG(&eir->gpiointmask, 0);
11883 +
11884 + /* Search for external UARTs */
11885 + n = 2;
11886 + for (i = 0; i < 2; i++) {
11887 + regs = (void *) REG_MAP(base + (i * 8), 8);
11888 + if (BCMINIT(serial_exists)(regs)) {
11889 + /* Set GPIO 1 to be the external UART IRQ */
11890 + W_REG(&eir->gpiointmask, 2);
11891 + if (add)
11892 + add(regs, irq, 13500000, 0);
11893 + }
11894 + }
11895 +
11896 + /* Add internal UART if enabled */
11897 + if (R_REG(&eir->corecontrol) & CC_UE)
11898 + if (add)
11899 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
11900 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
11901 + chipcregs_t *cc = (chipcregs_t *) regs;
11902 + uint32 rev, cap, pll, baud_base, div;
11903 +
11904 + /* Determine core revision and capabilities */
11905 + rev = sb_corerev(sbh);
11906 + cap = R_REG(&cc->capabilities);
11907 + pll = cap & CAP_PLL_MASK;
11908 +
11909 + /* Determine IRQ */
11910 + irq = sb_irq(sbh);
11911 +
11912 + if (pll == PLL_TYPE1) {
11913 + /* PLL clock */
11914 + baud_base = sb_clock_rate(pll,
11915 + R_REG(&cc->clockcontrol_n),
11916 + R_REG(&cc->clockcontrol_m2));
11917 + div = 1;
11918 + } else {
11919 + if (rev >= 11) {
11920 + /* Fixed ALP clock */
11921 + baud_base = 20000000;
11922 + div = 1;
11923 + /* Set the override bit so we don't divide it */
11924 + W_REG(&cc->corecontrol, CC_UARTCLKO);
11925 + } else if (rev >= 3) {
11926 + /* Internal backplane clock */
11927 + baud_base = sb_clock(sbh);
11928 + div = 2; /* Minimum divisor */
11929 + W_REG(&cc->clkdiv,
11930 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
11931 + } else {
11932 + /* Fixed internal backplane clock */
11933 + baud_base = 88000000;
11934 + div = 48;
11935 + }
11936 +
11937 + /* Clock source depends on strapping if UartClkOverride is unset */
11938 + if ((rev > 0) &&
11939 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
11940 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
11941 + /* Internal divided backplane clock */
11942 + baud_base /= div;
11943 + } else {
11944 + /* Assume external clock of 1.8432 MHz */
11945 + baud_base = 1843200;
11946 + }
11947 + }
11948 + }
11949 +
11950 + /* Add internal UARTs */
11951 + n = cap & CAP_UARTS_MASK;
11952 + for (i = 0; i < n; i++) {
11953 + /* Register offset changed after revision 0 */
11954 + if (rev)
11955 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
11956 + else
11957 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
11958 +
11959 + if (add)
11960 + add(regs, irq, baud_base, 0);
11961 + }
11962 + }
11963 +}
11964 +
11965 +/*
11966 + * Initialize jtag master and return handle for
11967 + * jtag_rwreg. Returns NULL on failure.
11968 + */
11969 +void *
11970 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
11971 +{
11972 + void *regs;
11973 +
11974 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
11975 + chipcregs_t *cc = (chipcregs_t *) regs;
11976 + uint32 tmp;
11977 +
11978 + /*
11979 + * Determine jtagm availability from
11980 + * core revision and capabilities.
11981 + */
11982 + tmp = sb_corerev(sbh);
11983 + /*
11984 + * Corerev 10 has jtagm, but the only chip
11985 + * with it does not have a mips, and
11986 + * the layout of the jtagcmd register is
11987 + * different. We'll only accept >= 11.
11988 + */
11989 + if (tmp < 11)
11990 + return (NULL);
11991 +
11992 + tmp = R_REG(&cc->capabilities);
11993 + if ((tmp & CAP_JTAGP) == 0)
11994 + return (NULL);
11995 +
11996 + /* Set clock divider if requested */
11997 + if (clkd != 0) {
11998 + tmp = R_REG(&cc->clkdiv);
11999 + tmp = (tmp & ~CLKD_JTAG) |
12000 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
12001 + W_REG(&cc->clkdiv, tmp);
12002 + }
12003 +
12004 + /* Enable jtagm */
12005 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
12006 + W_REG(&cc->jtagctrl, tmp);
12007 + }
12008 +
12009 + return (regs);
12010 +}
12011 +
12012 +void
12013 +sb_jtagm_disable(void *h)
12014 +{
12015 + chipcregs_t *cc = (chipcregs_t *)h;
12016 +
12017 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
12018 +}
12019 +
12020 +/*
12021 + * Read/write a jtag register. Assumes a target with
12022 + * 8 bit IR and 32 bit DR.
12023 + */
12024 +#define IRWIDTH 8
12025 +#define DRWIDTH 32
12026 +uint32
12027 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
12028 +{
12029 + chipcregs_t *cc = (chipcregs_t *) h;
12030 + uint32 tmp;
12031 +
12032 + W_REG(&cc->jtagir, ir);
12033 + W_REG(&cc->jtagdr, dr);
12034 + tmp = JCMD_START | JCMD_ACC_IRDR |
12035 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
12036 + (DRWIDTH - 1);
12037 + W_REG(&cc->jtagcmd, tmp);
12038 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
12039 + /* OSL_DELAY(1); */
12040 + }
12041 +
12042 + tmp = R_REG(&cc->jtagdr);
12043 + return (tmp);
12044 +}
12045 +
12046 +/* Returns the SB interrupt flag of the current core. */
12047 +uint32
12048 +sb_flag(sb_t *sbh)
12049 +{
12050 + void *regs;
12051 + sbconfig_t *sb;
12052 +
12053 + regs = sb_coreregs(sbh);
12054 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12055 +
12056 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
12057 +}
12058 +
12059 +static const uint32 sbips_int_mask[] = {
12060 + 0,
12061 + SBIPS_INT1_MASK,
12062 + SBIPS_INT2_MASK,
12063 + SBIPS_INT3_MASK,
12064 + SBIPS_INT4_MASK
12065 +};
12066 +
12067 +static const uint32 sbips_int_shift[] = {
12068 + 0,
12069 + 0,
12070 + SBIPS_INT2_SHIFT,
12071 + SBIPS_INT3_SHIFT,
12072 + SBIPS_INT4_SHIFT
12073 +};
12074 +
12075 +/*
12076 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
12077 + * 0 is returned.
12078 + */
12079 +uint
12080 +sb_irq(sb_t *sbh)
12081 +{
12082 + uint idx;
12083 + void *regs;
12084 + sbconfig_t *sb;
12085 + uint32 flag, sbipsflag;
12086 + uint irq = 0;
12087 +
12088 + flag = sb_flag(sbh);
12089 +
12090 + idx = sb_coreidx(sbh);
12091 +
12092 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
12093 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
12094 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12095 +
12096 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
12097 + sbipsflag = R_REG(&sb->sbipsflag);
12098 + for (irq = 1; irq <= 4; irq++) {
12099 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
12100 + break;
12101 + }
12102 + if (irq == 5)
12103 + irq = 0;
12104 + }
12105 +
12106 + sb_setcoreidx(sbh, idx);
12107 +
12108 + return irq;
12109 +}
12110 +
12111 +/* Clears the specified MIPS IRQ. */
12112 +static void
12113 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
12114 +{
12115 + void *regs;
12116 + sbconfig_t *sb;
12117 +
12118 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
12119 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
12120 + ASSERT(regs);
12121 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12122 +
12123 + if (irq == 0)
12124 + W_REG(&sb->sbintvec, 0);
12125 + else
12126 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
12127 +}
12128 +
12129 +/*
12130 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
12131 + * IRQ 0 may be assigned more than once.
12132 + */
12133 +static void
12134 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
12135 +{
12136 + void *regs;
12137 + sbconfig_t *sb;
12138 + uint32 flag;
12139 +
12140 + regs = sb_setcore(sbh, coreid, coreunit);
12141 + ASSERT(regs);
12142 + flag = sb_flag(sbh);
12143 +
12144 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
12145 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
12146 + ASSERT(regs);
12147 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12148 +
12149 + if (irq == 0)
12150 + OR_REG(&sb->sbintvec, 1 << flag);
12151 + else {
12152 + flag <<= sbips_int_shift[irq];
12153 + ASSERT(!(flag & ~sbips_int_mask[irq]));
12154 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
12155 + W_REG(&sb->sbipsflag, flag);
12156 + }
12157 +}
12158 +
12159 +/*
12160 + * Initializes clocks and interrupts. SB and NVRAM access must be
12161 + * initialized prior to calling.
12162 + */
12163 +void
12164 +BCMINITFN(sb_mips_init)(sb_t *sbh)
12165 +{
12166 + ulong hz, ns, tmp;
12167 + extifregs_t *eir;
12168 + chipcregs_t *cc;
12169 + char *value;
12170 + uint irq;
12171 +
12172 + /* Figure out current SB clock speed */
12173 + if ((hz = sb_clock(sbh)) == 0)
12174 + hz = 100000000;
12175 + ns = 1000000000 / hz;
12176 +
12177 + /* Setup external interface timing */
12178 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
12179 + /* Initialize extif so we can get to the LEDs and external UART */
12180 + W_REG(&eir->prog_config, CF_EN);
12181 +
12182 + /* Set timing for the flash */
12183 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12184 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
12185 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12186 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12187 +
12188 + /* Set programmable interface timing for external uart */
12189 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12190 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
12191 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
12192 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12193 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12194 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
12195 + /* Set timing for the flash */
12196 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12197 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
12198 + tmp |= CEIL(120, ns); /* W0 = 120nS */
12199 +
12200 + // Added by Chen-I for 5365
12201 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12202 + {
12203 + W_REG(&cc->flash_waitcount, tmp);
12204 + W_REG(&cc->pcmcia_memwait, tmp);
12205 + }
12206 + else
12207 + {
12208 + if (sb_corerev(sbh) < 9)
12209 + W_REG(&cc->flash_waitcount, tmp);
12210 +
12211 + if ((sb_corerev(sbh) < 9) ||
12212 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
12213 + W_REG(&cc->pcmcia_memwait, tmp);
12214 + }
12215 + }
12216 + }
12217 +
12218 + /* Chip specific initialization */
12219 + switch (BCMINIT(sb_chip)(sbh)) {
12220 + case BCM4710_DEVICE_ID:
12221 + /* Clear interrupt map */
12222 + for (irq = 0; irq <= 4; irq++)
12223 + BCMINIT(sb_clearirq)(sbh, irq);
12224 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
12225 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
12226 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
12227 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
12228 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
12229 + ASSERT(eir);
12230 + value = BCMINIT(nvram_get)("et0phyaddr");
12231 + if (value && !strcmp(value, "31")) {
12232 + /* Enable internal UART */
12233 + W_REG(&eir->corecontrol, CC_UE);
12234 + /* Give USB its own interrupt */
12235 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
12236 + } else {
12237 + /* Disable internal UART */
12238 + W_REG(&eir->corecontrol, 0);
12239 + /* Give Ethernet its own interrupt */
12240 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
12241 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
12242 + }
12243 + break;
12244 + case BCM5350_DEVICE_ID:
12245 + /* Clear interrupt map */
12246 + for (irq = 0; irq <= 4; irq++)
12247 + BCMINIT(sb_clearirq)(sbh, irq);
12248 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
12249 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
12250 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
12251 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
12252 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
12253 + break;
12254 + }
12255 +}
12256 +
12257 +uint32
12258 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
12259 +{
12260 + extifregs_t *eir;
12261 + chipcregs_t *cc;
12262 + uint32 n, m;
12263 + uint idx;
12264 + uint32 pll_type, rate = 0;
12265 +
12266 + /* get index of the current core */
12267 + idx = sb_coreidx(sbh);
12268 + pll_type = PLL_TYPE1;
12269 +
12270 + /* switch to extif or chipc core */
12271 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12272 + n = R_REG(&eir->clockcontrol_n);
12273 + m = R_REG(&eir->clockcontrol_sb);
12274 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12275 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12276 + n = R_REG(&cc->clockcontrol_n);
12277 + if ((pll_type == PLL_TYPE2) ||
12278 + (pll_type == PLL_TYPE4) ||
12279 + (pll_type == PLL_TYPE6) ||
12280 + (pll_type == PLL_TYPE7))
12281 + m = R_REG(&cc->clockcontrol_mips);
12282 + else if (pll_type == PLL_TYPE5) {
12283 + rate = 200000000;
12284 + goto out;
12285 + }
12286 + else if (pll_type == PLL_TYPE3) {
12287 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
12288 + rate = 200000000;
12289 + goto out;
12290 + } else
12291 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
12292 + } else
12293 + m = R_REG(&cc->clockcontrol_sb);
12294 + } else
12295 + goto out;
12296 +
12297 + // Added by Chen-I for 5365
12298 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12299 + rate = 100000000;
12300 + else
12301 + /* calculate rate */
12302 + rate = sb_clock_rate(pll_type, n, m);
12303 +
12304 + if (pll_type == PLL_TYPE6)
12305 + rate = SB2MIPS_T6(rate);
12306 +
12307 +out:
12308 + /* switch back to previous core */
12309 + sb_setcoreidx(sbh, idx);
12310 +
12311 + return rate;
12312 +}
12313 +
12314 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
12315 +
12316 +static void
12317 +BCMINITFN(handler)(void)
12318 +{
12319 + /* Step 11 */
12320 + __asm__ (
12321 + ".set\tmips32\n\t"
12322 + "ssnop\n\t"
12323 + "ssnop\n\t"
12324 + /* Disable interrupts */
12325 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
12326 + "mfc0 $15, $12\n\t"
12327 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
12328 + "li $14, -31746\n\t"
12329 + "and $15, $15, $14\n\t"
12330 + "mtc0 $15, $12\n\t"
12331 + "eret\n\t"
12332 + "nop\n\t"
12333 + "nop\n\t"
12334 + ".set\tmips0"
12335 + );
12336 +}
12337 +
12338 +/* The following MUST come right after handler() */
12339 +static void
12340 +BCMINITFN(afterhandler)(void)
12341 +{
12342 +}
12343 +
12344 +/*
12345 + * Set the MIPS, backplane and PCI clocks as closely as possible.
12346 + */
12347 +bool
12348 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
12349 +{
12350 + extifregs_t *eir = NULL;
12351 + chipcregs_t *cc = NULL;
12352 + mipsregs_t *mipsr = NULL;
12353 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
12354 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
12355 + uint32 pll_type, sync_mode;
12356 + uint ic_size, ic_lsize;
12357 + uint idx, i;
12358 + typedef struct {
12359 + uint32 mipsclock;
12360 + uint16 n;
12361 + uint32 sb;
12362 + uint32 pci33;
12363 + uint32 pci25;
12364 + } n3m_table_t;
12365 + static n3m_table_t BCMINITDATA(type1_table)[] = {
12366 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
12367 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
12368 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
12369 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
12370 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
12371 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
12372 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
12373 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
12374 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
12375 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
12376 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
12377 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
12378 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
12379 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
12380 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
12381 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
12382 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
12383 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
12384 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
12385 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
12386 + };
12387 + typedef struct {
12388 + uint32 mipsclock;
12389 + uint16 n;
12390 + uint32 m2; /* that is the clockcontrol_m2 */
12391 + } type3_table_t;
12392 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
12393 + { 150000000, 0x311, 0x4020005 },
12394 + { 200000000, 0x311, 0x4020003 },
12395 + };
12396 + typedef struct {
12397 + uint32 mipsclock;
12398 + uint32 sbclock;
12399 + uint16 n;
12400 + uint32 sb;
12401 + uint32 pci33;
12402 + uint32 m2;
12403 + uint32 m3;
12404 + uint32 ratio_cfg;
12405 + uint32 ratio_parm;
12406 + } n4m_table_t;
12407 +
12408 + static n4m_table_t BCMINITDATA(type2_table)[] = {
12409 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12410 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12411 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
12412 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12413 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12414 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12415 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12416 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12417 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12418 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12419 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12420 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12421 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12422 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12423 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12424 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12425 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
12426 + };
12427 +
12428 + static n4m_table_t BCMINITDATA(type4_table)[] = {
12429 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12430 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12431 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12432 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12433 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12434 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12435 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12436 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12437 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
12438 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12439 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
12440 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12441 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
12442 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12443 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12444 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12445 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12446 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12447 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
12448 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
12449 + };
12450 +
12451 + static n4m_table_t BCMINITDATA(type7_table)[] = {
12452 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12453 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12454 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12455 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
12456 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12457 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12458 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12459 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12460 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12461 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12462 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12463 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12464 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
12465 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
12466 + };
12467 +
12468 + ulong start, end, dst;
12469 + bool ret = FALSE;
12470 +
12471 + /* get index of the current core */
12472 + idx = sb_coreidx(sbh);
12473 + clockcontrol_m2 = NULL;
12474 +
12475 + /* switch to extif or chipc core */
12476 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12477 + pll_type = PLL_TYPE1;
12478 + clockcontrol_n = &eir->clockcontrol_n;
12479 + clockcontrol_sb = &eir->clockcontrol_sb;
12480 + clockcontrol_pci = &eir->clockcontrol_pci;
12481 + clockcontrol_m2 = &cc->clockcontrol_m2;
12482 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12483 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12484 + if (pll_type == PLL_TYPE6) {
12485 + clockcontrol_n = NULL;
12486 + clockcontrol_sb = NULL;
12487 + clockcontrol_pci = NULL;
12488 + } else {
12489 + clockcontrol_n = &cc->clockcontrol_n;
12490 + clockcontrol_sb = &cc->clockcontrol_sb;
12491 + clockcontrol_pci = &cc->clockcontrol_pci;
12492 + clockcontrol_m2 = &cc->clockcontrol_m2;
12493 + }
12494 + } else
12495 + goto done;
12496 +
12497 + if (pll_type == PLL_TYPE6) {
12498 + /* Silence compilers */
12499 + orig_n = orig_sb = orig_pci = 0;
12500 + } else {
12501 + /* Store the current clock register values */
12502 + orig_n = R_REG(clockcontrol_n);
12503 + orig_sb = R_REG(clockcontrol_sb);
12504 + orig_pci = R_REG(clockcontrol_pci);
12505 + }
12506 +
12507 + if (pll_type == PLL_TYPE1) {
12508 + /* Keep the current PCI clock if not specified */
12509 + if (pciclock == 0) {
12510 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
12511 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
12512 + }
12513 +
12514 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12515 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
12516 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
12517 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
12518 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
12519 + break;
12520 + }
12521 + if (i == 0) {
12522 + ret = FALSE;
12523 + goto done;
12524 + } else {
12525 + ret = TRUE;
12526 + i--;
12527 + }
12528 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
12529 +
12530 + /* No PLL change */
12531 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
12532 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
12533 + (orig_pci == BCMINIT(type1_table)[i].pci33))
12534 + goto done;
12535 +
12536 + /* Set the PLL controls */
12537 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
12538 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
12539 + if (pciclock == 25000000)
12540 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
12541 + else
12542 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
12543 +
12544 + /* Reset */
12545 + sb_watchdog(sbh, 1);
12546 +
12547 + while (1);
12548 + } else if ((pll_type == PLL_TYPE3) &&
12549 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
12550 + /* 5350 */
12551 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12552 +
12553 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
12554 + if (type3_table[i].mipsclock > mipsclock)
12555 + break;
12556 + }
12557 + if (i == 0) {
12558 + ret = FALSE;
12559 + goto done;
12560 + } else {
12561 + ret = TRUE;
12562 + i--;
12563 + }
12564 + ASSERT(type3_table[i].mipsclock <= mipsclock);
12565 +
12566 + /* No PLL change */
12567 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12568 + if ((orig_n == type3_table[i].n) &&
12569 + (orig_m2 == type3_table[i].m2)) {
12570 + goto done;
12571 + }
12572 +
12573 + /* Set the PLL controls */
12574 + W_REG(clockcontrol_n, type3_table[i].n);
12575 + W_REG(clockcontrol_m2, type3_table[i].m2);
12576 +
12577 + /* Reset */
12578 + sb_watchdog(sbh, 1);
12579 + while (1);
12580 + } else if ((pll_type == PLL_TYPE2) ||
12581 + (pll_type == PLL_TYPE4) ||
12582 + (pll_type == PLL_TYPE6) ||
12583 + (pll_type == PLL_TYPE7)) {
12584 + n4m_table_t *table = NULL, *te;
12585 + uint tabsz = 0;
12586 +
12587 + ASSERT(cc);
12588 +
12589 + orig_mips = R_REG(&cc->clockcontrol_mips);
12590 +
12591 + if (pll_type == PLL_TYPE6) {
12592 + uint32 new_mips = 0;
12593 +
12594 + ret = TRUE;
12595 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
12596 + new_mips = CC_T6_MMASK;
12597 +
12598 + if (orig_mips == new_mips)
12599 + goto done;
12600 +
12601 + W_REG(&cc->clockcontrol_mips, new_mips);
12602 + goto end_fill;
12603 + }
12604 +
12605 + if (pll_type == PLL_TYPE2) {
12606 + table = BCMINIT(type2_table);
12607 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
12608 + } else if (pll_type == PLL_TYPE4) {
12609 + table = BCMINIT(type4_table);
12610 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
12611 + } else if (pll_type == PLL_TYPE7) {
12612 + table = BCMINIT(type7_table);
12613 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
12614 + } else
12615 + ASSERT("No table for plltype" == NULL);
12616 +
12617 + /* Store the current clock register values */
12618 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12619 + orig_ratio_parm = 0;
12620 + orig_ratio_cfg = 0;
12621 +
12622 + /* Look up current ratio */
12623 + for (i = 0; i < tabsz; i++) {
12624 + if ((orig_n == table[i].n) &&
12625 + (orig_sb == table[i].sb) &&
12626 + (orig_pci == table[i].pci33) &&
12627 + (orig_m2 == table[i].m2) &&
12628 + (orig_mips == table[i].m3)) {
12629 + orig_ratio_parm = table[i].ratio_parm;
12630 + orig_ratio_cfg = table[i].ratio_cfg;
12631 + break;
12632 + }
12633 + }
12634 +
12635 + /* Search for the closest MIPS clock greater or equal to a preferred value */
12636 + for (i = 0; i < tabsz; i++) {
12637 + ASSERT(table[i].mipsclock ==
12638 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
12639 + if ((mipsclock <= table[i].mipsclock) &&
12640 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
12641 + break;
12642 + }
12643 + if (i == tabsz) {
12644 + ret = FALSE;
12645 + goto done;
12646 + } else {
12647 + te = &table[i];
12648 + ret = TRUE;
12649 + }
12650 +
12651 + /* No PLL change */
12652 + if ((orig_n == te->n) &&
12653 + (orig_sb == te->sb) &&
12654 + (orig_pci == te->pci33) &&
12655 + (orig_m2 == te->m2) &&
12656 + (orig_mips == te->m3))
12657 + goto done;
12658 +
12659 + /* Set the PLL controls */
12660 + W_REG(clockcontrol_n, te->n);
12661 + W_REG(clockcontrol_sb, te->sb);
12662 + W_REG(clockcontrol_pci, te->pci33);
12663 + W_REG(&cc->clockcontrol_m2, te->m2);
12664 + W_REG(&cc->clockcontrol_mips, te->m3);
12665 +
12666 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
12667 + if ((pll_type == PLL_TYPE7) &&
12668 + (te->sb != te->m2) &&
12669 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
12670 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
12671 +
12672 + /* No ratio change */
12673 + if (orig_ratio_parm == te->ratio_parm)
12674 + goto end_fill;
12675 +
12676 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
12677 +
12678 + /* Preload the code into the cache */
12679 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
12680 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
12681 + while (start < end) {
12682 + cache_op(start, Fill_I);
12683 + start += ic_lsize;
12684 + }
12685 +
12686 + /* Copy the handler */
12687 + start = (ulong) &BCMINIT(handler);
12688 + end = (ulong) &BCMINIT(afterhandler);
12689 + dst = KSEG1ADDR(0x180);
12690 + for (i = 0; i < (end - start); i += 4)
12691 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
12692 +
12693 + /* Preload handler into the cache one line at a time */
12694 + for (i = 0; i < (end - start); i += 4)
12695 + cache_op(dst + i, Fill_I);
12696 +
12697 + /* Clear BEV bit */
12698 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
12699 +
12700 + /* Enable interrupts */
12701 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
12702 +
12703 + /* Enable MIPS timer interrupt */
12704 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
12705 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
12706 + ASSERT(mipsr);
12707 + W_REG(&mipsr->intmask, 1);
12708 +
12709 + start_fill:
12710 + /* step 1, set clock ratios */
12711 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
12712 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
12713 +
12714 + /* step 2: program timer intr */
12715 + W_REG(&mipsr->timer, 100);
12716 + (void) R_REG(&mipsr->timer);
12717 +
12718 + /* step 3, switch to async */
12719 + sync_mode = MFC0(C0_BROADCOM, 4);
12720 + MTC0(C0_BROADCOM, 4, 1 << 22);
12721 +
12722 + /* step 4, set cfg active */
12723 + MTC0(C0_BROADCOM, 2, 0x9);
12724 +
12725 +
12726 + /* steps 5 & 6 */
12727 + __asm__ __volatile__ (
12728 + ".set\tmips3\n\t"
12729 + "wait\n\t"
12730 + ".set\tmips0"
12731 + );
12732 +
12733 + /* step 7, clear cfg_active */
12734 + MTC0(C0_BROADCOM, 2, 0);
12735 +
12736 + /* Additional Step: set back to orig sync mode */
12737 + MTC0(C0_BROADCOM, 4, sync_mode);
12738 +
12739 + /* step 8, fake soft reset */
12740 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
12741 +
12742 + end_fill:
12743 + /* step 9 set watchdog timer */
12744 + sb_watchdog(sbh, 20);
12745 + (void) R_REG(&cc->chipid);
12746 +
12747 + /* step 11 */
12748 + __asm__ __volatile__ (
12749 + ".set\tmips3\n\t"
12750 + "sync\n\t"
12751 + "wait\n\t"
12752 + ".set\tmips0"
12753 + );
12754 + while (1);
12755 + }
12756 +
12757 +done:
12758 + /* switch back to previous core */
12759 + sb_setcoreidx(sbh, idx);
12760 +
12761 + return ret;
12762 +}
12763 +
12764 +/*
12765 + * This also must be run from the cache on 47xx
12766 + * so there are no mips core BIU ops in progress
12767 + * when the PFC is enabled.
12768 + */
12769 +
12770 +static void
12771 +BCMINITFN(_enable_pfc)(uint32 mode)
12772 +{
12773 + /* write range */
12774 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
12775 +
12776 + /* enable */
12777 + *(volatile uint32 *)PFC_CR0 = mode;
12778 +}
12779 +
12780 +void
12781 +BCMINITFN(enable_pfc)(uint32 mode)
12782 +{
12783 + ulong start, end;
12784 + int i;
12785 +
12786 + /* If auto then choose the correct mode for this
12787 + platform, currently we only ever select one mode */
12788 + if (mode == PFC_AUTO)
12789 + mode = PFC_INST;
12790 +
12791 + /* enable prefetch cache if available */
12792 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
12793 + start = (ulong) &BCMINIT(_enable_pfc);
12794 + end = (ulong) &BCMINIT(enable_pfc);
12795 +
12796 + /* Preload handler into the cache one line at a time */
12797 + for (i = 0; i < (end - start); i += 4)
12798 + cache_op(start + i, Fill_I);
12799 +
12800 + BCMINIT(_enable_pfc)(mode);
12801 + }
12802 +}
12803 +
12804 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
12805 +uint32
12806 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
12807 +{
12808 + sbmemcregs_t *memc;
12809 + uint32 ret = 0;
12810 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
12811 + uint idx, rev;
12812 +
12813 + idx = sb_coreidx(sbh);
12814 +
12815 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
12816 + if (memc == 0)
12817 + goto out;
12818 +
12819 + rev = sb_corerev(sbh);
12820 +
12821 + config = R_REG(&memc->config);
12822 + wr = R_REG(&memc->wrncdlcor);
12823 + rd = R_REG(&memc->rdncdlcor);
12824 + misc = R_REG(&memc->miscdlyctl);
12825 + dqsg = R_REG(&memc->dqsgatencdl);
12826 +
12827 + rd &= MEMC_RDNCDLCOR_RD_MASK;
12828 + wr &= MEMC_WRNCDLCOR_WR_MASK;
12829 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
12830 +
12831 + if (config & MEMC_CONFIG_DDR) {
12832 + ret = (wr << 16) | (rd << 8) | dqsg;
12833 + } else {
12834 + if (rev > 0)
12835 + cd = rd;
12836 + else
12837 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
12838 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
12839 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
12840 + ret = (sm << 16) | (sd << 8) | cd;
12841 + }
12842 +
12843 +out:
12844 + /* switch back to previous core */
12845 + sb_setcoreidx(sbh, idx);
12846 +
12847 + return ret;
12848 +}
12849 +
12850 diff -Nur linux-2.4.32/arch/mips/bcm947xx/sbpci.c linux-2.4.32-brcm/arch/mips/bcm947xx/sbpci.c
12851 --- linux-2.4.32/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
12852 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/sbpci.c 2005-12-16 23:39:10.948837000 +0100
12853 @@ -0,0 +1,588 @@
12854 +/*
12855 + * Low-Level PCI and SB support for BCM47xx
12856 + *
12857 + * Copyright 2005, Broadcom Corporation
12858 + * All Rights Reserved.
12859 + *
12860 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12861 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12862 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12863 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12864 + *
12865 + * $Id$
12866 + */
12867 +
12868 +#include <typedefs.h>
12869 +#include <pcicfg.h>
12870 +#include <bcmdevs.h>
12871 +#include <sbconfig.h>
12872 +#include <osl.h>
12873 +#include <sbutils.h>
12874 +#include <sbpci.h>
12875 +#include <bcmendian.h>
12876 +#include <bcmutils.h>
12877 +#include <bcmnvram.h>
12878 +#include <hndmips.h>
12879 +
12880 +/* Can free sbpci_init() memory after boot */
12881 +#ifndef linux
12882 +#define __init
12883 +#endif
12884 +
12885 +/* Emulated configuration space */
12886 +static pci_config_regs sb_config_regs[SB_MAXCORES];
12887 +
12888 +/* Banned cores */
12889 +static uint16 pci_ban[32] = { 0 };
12890 +static uint pci_banned = 0;
12891 +
12892 +/* CardBus mode */
12893 +static bool cardbus = FALSE;
12894 +
12895 +/* Disable PCI host core */
12896 +static bool pci_disabled = FALSE;
12897 +
12898 +/*
12899 + * Functions for accessing external PCI configuration space
12900 + */
12901 +
12902 +/* Assume one-hot slot wiring */
12903 +#define PCI_SLOT_MAX 16
12904 +
12905 +static uint32
12906 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
12907 +{
12908 + uint coreidx;
12909 + sbpciregs_t *regs;
12910 + uint32 addr = 0;
12911 +
12912 + /* CardBusMode supports only one device */
12913 + if (cardbus && dev > 1)
12914 + return 0;
12915 +
12916 + coreidx = sb_coreidx(sbh);
12917 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
12918 +
12919 + /* Type 0 transaction */
12920 + if (bus == 1) {
12921 + /* Skip unwired slots */
12922 + if (dev < PCI_SLOT_MAX) {
12923 + /* Slide the PCI window to the appropriate slot */
12924 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
12925 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
12926 + (func << 8) | (off & ~3);
12927 + }
12928 + }
12929 +
12930 + /* Type 1 transaction */
12931 + else {
12932 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
12933 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
12934 + }
12935 +
12936 + sb_setcoreidx(sbh, coreidx);
12937 +
12938 + return addr;
12939 +}
12940 +
12941 +static int
12942 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12943 +{
12944 + uint32 addr, *reg = NULL, val;
12945 + int ret = 0;
12946 +
12947 + if (pci_disabled ||
12948 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12949 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12950 + BUSPROBE(val, reg))
12951 + val = 0xffffffff;
12952 +
12953 + val >>= 8 * (off & 3);
12954 + if (len == 4)
12955 + *((uint32 *) buf) = val;
12956 + else if (len == 2)
12957 + *((uint16 *) buf) = (uint16) val;
12958 + else if (len == 1)
12959 + *((uint8 *) buf) = (uint8) val;
12960 + else
12961 + ret = -1;
12962 +
12963 + if (reg)
12964 + REG_UNMAP(reg);
12965 +
12966 + return ret;
12967 +}
12968 +
12969 +static int
12970 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12971 +{
12972 + uint32 addr, *reg = NULL, val;
12973 + int ret = 0;
12974 +
12975 + if (pci_disabled ||
12976 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12977 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12978 + BUSPROBE(val, reg))
12979 + goto done;
12980 +
12981 + if (len == 4)
12982 + val = *((uint32 *) buf);
12983 + else if (len == 2) {
12984 + val &= ~(0xffff << (8 * (off & 3)));
12985 + val |= *((uint16 *) buf) << (8 * (off & 3));
12986 + } else if (len == 1) {
12987 + val &= ~(0xff << (8 * (off & 3)));
12988 + val |= *((uint8 *) buf) << (8 * (off & 3));
12989 + } else
12990 + ret = -1;
12991 +
12992 + W_REG(reg, val);
12993 +
12994 + done:
12995 + if (reg)
12996 + REG_UNMAP(reg);
12997 +
12998 + return ret;
12999 +}
13000 +
13001 +/*
13002 + * Functions for accessing translated SB configuration space
13003 + */
13004 +
13005 +static int
13006 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
13007 +{
13008 + pci_config_regs *cfg;
13009 +
13010 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
13011 + return -1;
13012 + cfg = &sb_config_regs[dev];
13013 +
13014 + ASSERT(ISALIGNED(off, len));
13015 + ASSERT(ISALIGNED((uintptr)buf, len));
13016 +
13017 + if (len == 4)
13018 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
13019 + else if (len == 2)
13020 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
13021 + else if (len == 1)
13022 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
13023 + else
13024 + return -1;
13025 +
13026 + return 0;
13027 +}
13028 +
13029 +static int
13030 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
13031 +{
13032 + uint coreidx, n;
13033 + void *regs;
13034 + sbconfig_t *sb;
13035 + pci_config_regs *cfg;
13036 +
13037 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
13038 + return -1;
13039 + cfg = &sb_config_regs[dev];
13040 +
13041 + ASSERT(ISALIGNED(off, len));
13042 + ASSERT(ISALIGNED((uintptr)buf, len));
13043 +
13044 + /* Emulate BAR sizing */
13045 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
13046 + len == 4 && *((uint32 *) buf) == ~0) {
13047 + coreidx = sb_coreidx(sbh);
13048 + if ((regs = sb_setcoreidx(sbh, dev))) {
13049 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13050 + /* Highest numbered address match register */
13051 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
13052 + if (off == OFFSETOF(pci_config_regs, base[0]))
13053 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
13054 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
13055 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
13056 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
13057 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
13058 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
13059 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
13060 + }
13061 + sb_setcoreidx(sbh, coreidx);
13062 + return 0;
13063 + }
13064 +
13065 + if (len == 4)
13066 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
13067 + else if (len == 2)
13068 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
13069 + else if (len == 1)
13070 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
13071 + else
13072 + return -1;
13073 +
13074 + return 0;
13075 +}
13076 +
13077 +int
13078 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
13079 +{
13080 + if (bus == 0)
13081 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
13082 + else
13083 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
13084 +}
13085 +
13086 +int
13087 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
13088 +{
13089 + if (bus == 0)
13090 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
13091 + else
13092 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
13093 +}
13094 +
13095 +void
13096 +sbpci_ban(uint16 core)
13097 +{
13098 + if (pci_banned < ARRAYSIZE(pci_ban))
13099 + pci_ban[pci_banned++] = core;
13100 +}
13101 +
13102 +static int
13103 +sbpci_init_pci(sb_t *sbh)
13104 +{
13105 + uint chip, chiprev, chippkg, host;
13106 + uint32 boardflags;
13107 + sbpciregs_t *pci;
13108 + sbconfig_t *sb;
13109 + uint32 val;
13110 +
13111 + chip = sb_chip(sbh);
13112 + chiprev = sb_chiprev(sbh);
13113 + chippkg = sb_chippkg(sbh);
13114 +
13115 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
13116 + printf("PCI: no core\n");
13117 + pci_disabled = TRUE;
13118 + return -1;
13119 + }
13120 + sb_core_reset(sbh, 0);
13121 +
13122 + boardflags = (uint32) getintvar(NULL, "boardflags");
13123 +
13124 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
13125 + pci_disabled = TRUE;
13126 +
13127 + /*
13128 + * The 200-pin BCM4712 package does not bond out PCI. Even when
13129 + * PCI is bonded out, some boards may leave the pins
13130 + * floating.
13131 + */
13132 + if (((chip == BCM4712_DEVICE_ID) &&
13133 + ((chippkg == BCM4712SMALL_PKG_ID) ||
13134 + (chippkg == BCM4712MID_PKG_ID))) ||
13135 + (boardflags & BFL_NOPCI))
13136 + pci_disabled = TRUE;
13137 +
13138 + /*
13139 + * If the PCI core should not be touched (disabled, not bonded
13140 + * out, or pins floating), do not even attempt to access core
13141 + * registers. Otherwise, try to determine if it is in host
13142 + * mode.
13143 + */
13144 + if (pci_disabled)
13145 + host = 0;
13146 + else
13147 + host = !BUSPROBE(val, &pci->control);
13148 +
13149 + if (!host) {
13150 + /* Disable PCI interrupts in client mode */
13151 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
13152 + W_REG(&sb->sbintvec, 0);
13153 +
13154 + /* Disable the PCI bridge in client mode */
13155 + sbpci_ban(SB_PCI);
13156 + printf("PCI: Disabled\n");
13157 + } else {
13158 + /* Reset the external PCI bus and enable the clock */
13159 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
13160 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
13161 + OSL_DELAY(150); /* delay > 100 us */
13162 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
13163 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
13164 + OSL_DELAY(1); /* delay 1 us */
13165 +
13166 + /* Enable CardBusMode */
13167 + cardbus = nvram_match("cardbus", "1");
13168 + if (cardbus) {
13169 + printf("PCI: Enabling CardBus\n");
13170 + /* GPIO 1 resets the CardBus device on bcm94710ap */
13171 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
13172 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
13173 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
13174 + }
13175 +
13176 + /* 64 MB I/O access window */
13177 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
13178 + /* 64 MB configuration access window */
13179 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
13180 + /* 1 GB memory access window */
13181 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
13182 +
13183 + /* Enable PCI bridge BAR0 prefetch and burst */
13184 + val = 6;
13185 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
13186 +
13187 + /* Enable PCI interrupts */
13188 + W_REG(&pci->intmask, PCI_INTA);
13189 + }
13190 +
13191 + return 0;
13192 +}
13193 +
13194 +static int
13195 +sbpci_init_cores(sb_t *sbh)
13196 +{
13197 + uint chip, chiprev, chippkg, coreidx, i;
13198 + sbconfig_t *sb;
13199 + pci_config_regs *cfg;
13200 + void *regs;
13201 + char varname[8];
13202 + uint wlidx = 0;
13203 + uint16 vendor, core;
13204 + uint8 class, subclass, progif;
13205 + uint32 val;
13206 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
13207 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
13208 +
13209 + chip = sb_chip(sbh);
13210 + chiprev = sb_chiprev(sbh);
13211 + chippkg = sb_chippkg(sbh);
13212 + coreidx = sb_coreidx(sbh);
13213 +
13214 + /* Scan the SB bus */
13215 + bzero(sb_config_regs, sizeof(sb_config_regs));
13216 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
13217 + cfg->vendor = 0xffff;
13218 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
13219 + continue;
13220 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13221 +
13222 + /* Read ID register and parse vendor and core */
13223 + val = R_REG(&sb->sbidhigh);
13224 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
13225 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
13226 + progif = 0;
13227 +
13228 + /* Check if this core is banned */
13229 + for (i = 0; i < pci_banned; i++)
13230 + if (core == pci_ban[i])
13231 + break;
13232 + if (i < pci_banned)
13233 + continue;
13234 +
13235 + /* Known vendor translations */
13236 + switch (vendor) {
13237 + case SB_VEND_BCM:
13238 + vendor = VENDOR_BROADCOM;
13239 + break;
13240 + }
13241 +
13242 + /* Determine class based on known core codes */
13243 + switch (core) {
13244 + case SB_ILINE20:
13245 + class = PCI_CLASS_NET;
13246 + subclass = PCI_NET_ETHER;
13247 + core = BCM47XX_ILINE_ID;
13248 + break;
13249 + case SB_ILINE100:
13250 + class = PCI_CLASS_NET;
13251 + subclass = PCI_NET_ETHER;
13252 + core = BCM4610_ILINE_ID;
13253 + break;
13254 + case SB_ENET:
13255 + class = PCI_CLASS_NET;
13256 + subclass = PCI_NET_ETHER;
13257 + core = BCM47XX_ENET_ID;
13258 + break;
13259 + case SB_SDRAM:
13260 + case SB_MEMC:
13261 + class = PCI_CLASS_MEMORY;
13262 + subclass = PCI_MEMORY_RAM;
13263 + break;
13264 + case SB_PCI:
13265 + class = PCI_CLASS_BRIDGE;
13266 + subclass = PCI_BRIDGE_PCI;
13267 + break;
13268 + case SB_MIPS:
13269 + case SB_MIPS33:
13270 + class = PCI_CLASS_CPU;
13271 + subclass = PCI_CPU_MIPS;
13272 + break;
13273 + case SB_CODEC:
13274 + class = PCI_CLASS_COMM;
13275 + subclass = PCI_COMM_MODEM;
13276 + core = BCM47XX_V90_ID;
13277 + break;
13278 + case SB_USB:
13279 + class = PCI_CLASS_SERIAL;
13280 + subclass = PCI_SERIAL_USB;
13281 + progif = 0x10; /* OHCI */
13282 + core = BCM47XX_USB_ID;
13283 + break;
13284 + case SB_USB11H:
13285 + class = PCI_CLASS_SERIAL;
13286 + subclass = PCI_SERIAL_USB;
13287 + progif = 0x10; /* OHCI */
13288 + core = BCM47XX_USBH_ID;
13289 + break;
13290 + case SB_USB11D:
13291 + class = PCI_CLASS_SERIAL;
13292 + subclass = PCI_SERIAL_USB;
13293 + core = BCM47XX_USBD_ID;
13294 + break;
13295 + case SB_IPSEC:
13296 + class = PCI_CLASS_CRYPT;
13297 + subclass = PCI_CRYPT_NETWORK;
13298 + core = BCM47XX_IPSEC_ID;
13299 + break;
13300 + case SB_ROBO:
13301 + class = PCI_CLASS_NET;
13302 + subclass = PCI_NET_OTHER;
13303 + core = BCM47XX_ROBO_ID;
13304 + break;
13305 + case SB_EXTIF:
13306 + case SB_CC:
13307 + class = PCI_CLASS_MEMORY;
13308 + subclass = PCI_MEMORY_FLASH;
13309 + break;
13310 + case SB_D11:
13311 + class = PCI_CLASS_NET;
13312 + subclass = PCI_NET_OTHER;
13313 + /* Let an nvram variable override this */
13314 + sprintf(varname, "wl%did", wlidx);
13315 + wlidx++;
13316 + if ((core = getintvar(NULL, varname)) == 0) {
13317 + if (chip == BCM4712_DEVICE_ID) {
13318 + if (chippkg == BCM4712SMALL_PKG_ID)
13319 + core = BCM4306_D11G_ID;
13320 + else
13321 + core = BCM4306_D11DUAL_ID;
13322 + } else {
13323 + /* 4310 */
13324 + core = BCM4310_D11B_ID;
13325 + }
13326 + }
13327 + break;
13328 +
13329 + default:
13330 + class = subclass = progif = 0xff;
13331 + break;
13332 + }
13333 +
13334 + /* Supported translations */
13335 + cfg->vendor = htol16(vendor);
13336 + cfg->device = htol16(core);
13337 + cfg->rev_id = chiprev;
13338 + cfg->prog_if = progif;
13339 + cfg->sub_class = subclass;
13340 + cfg->base_class = class;
13341 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
13342 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
13343 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
13344 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
13345 + cfg->base[4] = 0;
13346 + cfg->base[5] = 0;
13347 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
13348 + cfg->header_type = PCI_HEADER_BRIDGE;
13349 + else
13350 + cfg->header_type = PCI_HEADER_NORMAL;
13351 + /* Save core interrupt flag */
13352 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
13353 + /* Default to MIPS shared interrupt 0 */
13354 + cfg->int_line = 0;
13355 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
13356 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
13357 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
13358 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13359 + val = R_REG(&sb->sbipsflag);
13360 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
13361 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
13362 + break;
13363 + }
13364 + if (cfg->int_line > 4)
13365 + cfg->int_line = 0;
13366 + }
13367 + /* Emulated core */
13368 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
13369 + }
13370 +
13371 + sb_setcoreidx(sbh, coreidx);
13372 + return 0;
13373 +}
13374 +
13375 +int __init
13376 +sbpci_init(sb_t *sbh)
13377 +{
13378 + sbpci_init_pci(sbh);
13379 + sbpci_init_cores(sbh);
13380 + return 0;
13381 +}
13382 +
13383 +void
13384 +sbpci_check(sb_t *sbh)
13385 +{
13386 + uint coreidx;
13387 + sbpciregs_t *pci;
13388 + uint32 sbtopci1;
13389 + uint32 buf[64], *ptr, i;
13390 + ulong pa;
13391 + volatile uint j;
13392 +
13393 + coreidx = sb_coreidx(sbh);
13394 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
13395 +
13396 + /* Clear the test array */
13397 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
13398 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13399 + memset(ptr, 0, sizeof(buf));
13400 +
13401 + /* Point PCI window 1 to memory */
13402 + sbtopci1 = R_REG(&pci->sbtopci1);
13403 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
13404 +
13405 + /* Fill the test array via PCI window 1 */
13406 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
13407 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13408 + for (j = 0; j < 2; j++);
13409 + W_REG(&ptr[i], i);
13410 + }
13411 + REG_UNMAP(ptr);
13412 +
13413 + /* Restore PCI window 1 */
13414 + W_REG(&pci->sbtopci1, sbtopci1);
13415 +
13416 + /* Check the test array */
13417 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
13418 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13419 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13420 + if (ptr[i] != i)
13421 + break;
13422 + }
13423 +
13424 + /* Change the clock if the test fails */
13425 + if (i < ARRAYSIZE(buf)) {
13426 + uint32 req, cur;
13427 +
13428 + cur = sb_clock(sbh);
13429 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
13430 + for (req = 104000000; req < 176000000; req += 4000000) {
13431 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
13432 + /* This will only reset if the clocks are valid and have changed */
13433 + sb_mips_setclock(sbh, req, 0, 0);
13434 + }
13435 + /* Should not reach here */
13436 + ASSERT(0);
13437 + }
13438 +
13439 + sb_setcoreidx(sbh, coreidx);
13440 +}
13441 +
13442 diff -Nur linux-2.4.32/arch/mips/bcm947xx/setup.c linux-2.4.32-brcm/arch/mips/bcm947xx/setup.c
13443 --- linux-2.4.32/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
13444 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/setup.c 2005-12-20 00:29:40.187416500 +0100
13445 @@ -0,0 +1,234 @@
13446 +/*
13447 + * Generic setup routines for Broadcom MIPS boards
13448 + *
13449 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
13450 + *
13451 + * This program is free software; you can redistribute it and/or modify it
13452 + * under the terms of the GNU General Public License as published by the
13453 + * Free Software Foundation; either version 2 of the License, or (at your
13454 + * option) any later version.
13455 + *
13456 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13457 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13458 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13459 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13460 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
13461 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13462 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
13463 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13464 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
13465 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13466 + *
13467 + * You should have received a copy of the GNU General Public License along
13468 + * with this program; if not, write to the Free Software Foundation, Inc.,
13469 + * 675 Mass Ave, Cambridge, MA 02139, USA.
13470 + *
13471 + *
13472 + * Copyright 2005, Broadcom Corporation
13473 + * All Rights Reserved.
13474 + *
13475 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13476 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13477 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13478 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13479 + *
13480 + */
13481 +
13482 +#include <linux/config.h>
13483 +#include <linux/init.h>
13484 +#include <linux/kernel.h>
13485 +#include <linux/module.h>
13486 +#include <linux/serialP.h>
13487 +#include <linux/ide.h>
13488 +#include <asm/bootinfo.h>
13489 +#include <asm/cpu.h>
13490 +#include <asm/time.h>
13491 +#include <asm/reboot.h>
13492 +
13493 +#include <typedefs.h>
13494 +#include <osl.h>
13495 +#include <sbutils.h>
13496 +#include <bcmutils.h>
13497 +#include <bcmnvram.h>
13498 +#include <sbmips.h>
13499 +#include <trxhdr.h>
13500 +
13501 +/* Global SB handle */
13502 +sb_t *bcm947xx_sbh = NULL;
13503 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
13504 +
13505 +/* Convenience */
13506 +#define sbh bcm947xx_sbh
13507 +#define sbh_lock bcm947xx_sbh_lock
13508 +
13509 +extern void bcm947xx_time_init(void);
13510 +extern void bcm947xx_timer_setup(struct irqaction *irq);
13511 +
13512 +#ifdef CONFIG_REMOTE_DEBUG
13513 +extern void set_debug_traps(void);
13514 +extern void rs_kgdb_hook(struct serial_state *);
13515 +extern void breakpoint(void);
13516 +#endif
13517 +
13518 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13519 +extern struct ide_ops std_ide_ops;
13520 +#endif
13521 +
13522 +/* Kernel command line */
13523 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
13524 +
13525 +void
13526 +bcm947xx_machine_restart(char *command)
13527 +{
13528 + printk("Please stand by while rebooting the system...\n");
13529 +
13530 + /* Set the watchdog timer to reset immediately */
13531 + __cli();
13532 + sb_watchdog(sbh, 1);
13533 + while (1);
13534 +}
13535 +
13536 +void
13537 +bcm947xx_machine_halt(void)
13538 +{
13539 + printk("System halted\n");
13540 +
13541 + /* Disable interrupts and watchdog and spin forever */
13542 + __cli();
13543 + sb_watchdog(sbh, 0);
13544 + while (1);
13545 +}
13546 +
13547 +#ifdef CONFIG_SERIAL
13548 +
13549 +static int ser_line = 0;
13550 +
13551 +typedef struct {
13552 + void *regs;
13553 + uint irq;
13554 + uint baud_base;
13555 + uint reg_shift;
13556 +} serial_port;
13557 +
13558 +static serial_port ports[4];
13559 +static int num_ports = 0;
13560 +
13561 +static void
13562 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
13563 +{
13564 + ports[num_ports].regs = regs;
13565 + ports[num_ports].irq = irq;
13566 + ports[num_ports].baud_base = baud_base;
13567 + ports[num_ports].reg_shift = reg_shift;
13568 + num_ports++;
13569 +}
13570 +
13571 +static void
13572 +do_serial_add(serial_port *port)
13573 +{
13574 + void *regs;
13575 + uint irq;
13576 + uint baud_base;
13577 + uint reg_shift;
13578 + struct serial_struct s;
13579 +
13580 + regs = port->regs;
13581 + irq = port->irq;
13582 + baud_base = port->baud_base;
13583 + reg_shift = port->reg_shift;
13584 +
13585 + memset(&s, 0, sizeof(s));
13586 +
13587 + s.line = ser_line++;
13588 + s.iomem_base = regs;
13589 + s.irq = irq + 2;
13590 + s.baud_base = baud_base / 16;
13591 + s.flags = ASYNC_BOOT_AUTOCONF;
13592 + s.io_type = SERIAL_IO_MEM;
13593 + s.iomem_reg_shift = reg_shift;
13594 +
13595 + if (early_serial_setup(&s) != 0) {
13596 + printk(KERN_ERR "Serial setup failed!\n");
13597 + }
13598 +}
13599 +
13600 +#endif /* CONFIG_SERIAL */
13601 +
13602 +void __init
13603 +brcm_setup(void)
13604 +{
13605 + char *s;
13606 + int i;
13607 + char *value;
13608 +
13609 + /* Get global SB handle */
13610 + sbh = sb_kattach();
13611 +
13612 + /* Initialize clocks and interrupts */
13613 + sb_mips_init(sbh);
13614 +
13615 + if (BCM330X(current_cpu_data.processor_id) &&
13616 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
13617 + /*
13618 + * Now that the sbh is inited set the proper PFC value
13619 + */
13620 + printk("Setting the PFC to its default value\n");
13621 + enable_pfc(PFC_AUTO);
13622 + }
13623 +
13624 +
13625 +#ifdef CONFIG_SERIAL
13626 + sb_serial_init(sbh, serial_add);
13627 +
13628 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
13629 + /* Initialize UARTs */
13630 + s = nvram_get("kernel_args");
13631 + if (!s) s = "";
13632 + if (!strncmp(s, "console=ttyS1", 13)) {
13633 + for (i = num_ports; i; i--)
13634 + do_serial_add(&ports[i - 1]);
13635 + } else {
13636 + for (i = 0; i < num_ports; i++)
13637 + do_serial_add(&ports[i]);
13638 + }
13639 +#endif
13640 +
13641 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13642 + ide_ops = &std_ide_ops;
13643 +#endif
13644 +
13645 + /* Override default command line arguments */
13646 + value = nvram_get("kernel_cmdline");
13647 + if (value && strlen(value) && strncmp(value, "empty", 5))
13648 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
13649 +
13650 +
13651 + /* Generic setup */
13652 + _machine_restart = bcm947xx_machine_restart;
13653 + _machine_halt = bcm947xx_machine_halt;
13654 + _machine_power_off = bcm947xx_machine_halt;
13655 +
13656 + board_time_init = bcm947xx_time_init;
13657 + board_timer_setup = bcm947xx_timer_setup;
13658 +}
13659 +
13660 +const char *
13661 +get_system_type(void)
13662 +{
13663 + static char s[32];
13664 +
13665 + if (bcm947xx_sbh) {
13666 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
13667 + sb_chiprev(bcm947xx_sbh));
13668 + return s;
13669 + }
13670 + else
13671 + return "Broadcom BCM947XX";
13672 +}
13673 +
13674 +void __init
13675 +bus_error_init(void)
13676 +{
13677 +}
13678 +
13679 +EXPORT_SYMBOL(bcm947xx_sbh);
13680 diff -Nur linux-2.4.32/arch/mips/bcm947xx/sflash.c linux-2.4.32-brcm/arch/mips/bcm947xx/sflash.c
13681 --- linux-2.4.32/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
13682 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/sflash.c 2005-12-16 23:39:10.948837000 +0100
13683 @@ -0,0 +1,418 @@
13684 +/*
13685 + * Broadcom SiliconBackplane chipcommon serial flash interface
13686 + *
13687 + * Copyright 2005, Broadcom Corporation
13688 + * All Rights Reserved.
13689 + *
13690 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13691 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13692 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13693 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13694 + *
13695 + * $Id$
13696 + */
13697 +
13698 +#include <osl.h>
13699 +#include <typedefs.h>
13700 +#include <sbconfig.h>
13701 +#include <sbchipc.h>
13702 +#include <mipsinc.h>
13703 +#include <bcmutils.h>
13704 +#include <bcmdevs.h>
13705 +#include <sflash.h>
13706 +
13707 +/* Private global state */
13708 +static struct sflash sflash;
13709 +
13710 +/* Issue a serial flash command */
13711 +static INLINE void
13712 +sflash_cmd(chipcregs_t *cc, uint opcode)
13713 +{
13714 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
13715 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
13716 +}
13717 +
13718 +/* Initialize serial flash access */
13719 +struct sflash *
13720 +sflash_init(chipcregs_t *cc)
13721 +{
13722 + uint32 id, id2;
13723 +
13724 + bzero(&sflash, sizeof(sflash));
13725 +
13726 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
13727 +
13728 + switch (sflash.type) {
13729 + case SFLASH_ST:
13730 + /* Probe for ST chips */
13731 + sflash_cmd(cc, SFLASH_ST_DP);
13732 + sflash_cmd(cc, SFLASH_ST_RES);
13733 + id = R_REG(&cc->flashdata);
13734 + switch (id) {
13735 + case 0x11:
13736 + /* ST M25P20 2 Mbit Serial Flash */
13737 + sflash.blocksize = 64 * 1024;
13738 + sflash.numblocks = 4;
13739 + break;
13740 + case 0x12:
13741 + /* ST M25P40 4 Mbit Serial Flash */
13742 + sflash.blocksize = 64 * 1024;
13743 + sflash.numblocks = 8;
13744 + break;
13745 + case 0x13:
13746 + /* ST M25P80 8 Mbit Serial Flash */
13747 + sflash.blocksize = 64 * 1024;
13748 + sflash.numblocks = 16;
13749 + break;
13750 + case 0x14:
13751 + /* ST M25P16 16 Mbit Serial Flash */
13752 + sflash.blocksize = 64 * 1024;
13753 + sflash.numblocks = 32;
13754 + break;
13755 + case 0x15:
13756 + /* ST M25P32 32 Mbit Serial Flash */
13757 + sflash.blocksize = 64 * 1024;
13758 + sflash.numblocks = 64;
13759 + break;
13760 + case 0xbf:
13761 + W_REG(&cc->flashaddress, 1);
13762 + sflash_cmd(cc, SFLASH_ST_RES);
13763 + id2 = R_REG(&cc->flashdata);
13764 + if (id2 == 0x44) {
13765 + /* SST M25VF80 4 Mbit Serial Flash */
13766 + sflash.blocksize = 64 * 1024;
13767 + sflash.numblocks = 8;
13768 + }
13769 + break;
13770 + }
13771 + break;
13772 +
13773 + case SFLASH_AT:
13774 + /* Probe for Atmel chips */
13775 + sflash_cmd(cc, SFLASH_AT_STATUS);
13776 + id = R_REG(&cc->flashdata) & 0x3c;
13777 + switch (id) {
13778 + case 0xc:
13779 + /* Atmel AT45DB011 1Mbit Serial Flash */
13780 + sflash.blocksize = 256;
13781 + sflash.numblocks = 512;
13782 + break;
13783 + case 0x14:
13784 + /* Atmel AT45DB021 2Mbit Serial Flash */
13785 + sflash.blocksize = 256;
13786 + sflash.numblocks = 1024;
13787 + break;
13788 + case 0x1c:
13789 + /* Atmel AT45DB041 4Mbit Serial Flash */
13790 + sflash.blocksize = 256;
13791 + sflash.numblocks = 2048;
13792 + break;
13793 + case 0x24:
13794 + /* Atmel AT45DB081 8Mbit Serial Flash */
13795 + sflash.blocksize = 256;
13796 + sflash.numblocks = 4096;
13797 + break;
13798 + case 0x2c:
13799 + /* Atmel AT45DB161 16Mbit Serial Flash */
13800 + sflash.blocksize = 512;
13801 + sflash.numblocks = 4096;
13802 + break;
13803 + case 0x34:
13804 + /* Atmel AT45DB321 32Mbit Serial Flash */
13805 + sflash.blocksize = 512;
13806 + sflash.numblocks = 8192;
13807 + break;
13808 + case 0x3c:
13809 + /* Atmel AT45DB642 64Mbit Serial Flash */
13810 + sflash.blocksize = 1024;
13811 + sflash.numblocks = 8192;
13812 + break;
13813 + }
13814 + break;
13815 + }
13816 +
13817 + sflash.size = sflash.blocksize * sflash.numblocks;
13818 + return sflash.size ? &sflash : NULL;
13819 +}
13820 +
13821 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
13822 +int
13823 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
13824 +{
13825 + int cnt;
13826 + uint32 *from, *to;
13827 +
13828 + if (!len)
13829 + return 0;
13830 +
13831 + if ((offset + len) > sflash.size)
13832 + return -22;
13833 +
13834 + if ((len >= 4) && (offset & 3))
13835 + cnt = 4 - (offset & 3);
13836 + else if ((len >= 4) && ((uint32)buf & 3))
13837 + cnt = 4 - ((uint32)buf & 3);
13838 + else
13839 + cnt = len;
13840 +
13841 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
13842 + to = (uint32 *)buf;
13843 +
13844 + if (cnt < 4) {
13845 + bcopy(from, to, cnt);
13846 + return cnt;
13847 + }
13848 +
13849 + while (cnt >= 4) {
13850 + *to++ = *from++;
13851 + cnt -= 4;
13852 + }
13853 +
13854 + return (len - cnt);
13855 +}
13856 +
13857 +/* Poll for command completion. Returns zero when complete. */
13858 +int
13859 +sflash_poll(chipcregs_t *cc, uint offset)
13860 +{
13861 + if (offset >= sflash.size)
13862 + return -22;
13863 +
13864 + switch (sflash.type) {
13865 + case SFLASH_ST:
13866 + /* Check for ST Write In Progress bit */
13867 + sflash_cmd(cc, SFLASH_ST_RDSR);
13868 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
13869 + case SFLASH_AT:
13870 + /* Check for Atmel Ready bit */
13871 + sflash_cmd(cc, SFLASH_AT_STATUS);
13872 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
13873 + }
13874 +
13875 + return 0;
13876 +}
13877 +
13878 +/* Write len bytes starting at offset into buf. Returns number of bytes
13879 + * written. Caller should poll for completion.
13880 + */
13881 +int
13882 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13883 +{
13884 + struct sflash *sfl;
13885 + int ret = 0;
13886 + bool is4712b0;
13887 + uint32 page, byte, mask;
13888 +
13889 + if (!len)
13890 + return 0;
13891 +
13892 + if ((offset + len) > sflash.size)
13893 + return -22;
13894 +
13895 + sfl = &sflash;
13896 + switch (sfl->type) {
13897 + case SFLASH_ST:
13898 + mask = R_REG(&cc->chipid);
13899 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
13900 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
13901 + /* Enable writes */
13902 + sflash_cmd(cc, SFLASH_ST_WREN);
13903 + if (is4712b0) {
13904 + mask = 1 << 14;
13905 + W_REG(&cc->flashaddress, offset);
13906 + W_REG(&cc->flashdata, *buf++);
13907 + /* Set chip select */
13908 + OR_REG(&cc->gpioout, mask);
13909 + /* Issue a page program with the first byte */
13910 + sflash_cmd(cc, SFLASH_ST_PP);
13911 + ret = 1;
13912 + offset++;
13913 + len--;
13914 + while (len > 0) {
13915 + if ((offset & 255) == 0) {
13916 + /* Page boundary, drop cs and return */
13917 + AND_REG(&cc->gpioout, ~mask);
13918 + if (!sflash_poll(cc, offset)) {
13919 + /* Flash rejected command */
13920 + return -11;
13921 + }
13922 + return ret;
13923 + } else {
13924 + /* Write single byte */
13925 + sflash_cmd(cc, *buf++);
13926 + }
13927 + ret++;
13928 + offset++;
13929 + len--;
13930 + }
13931 + /* All done, drop cs if needed */
13932 + if ((offset & 255) != 1) {
13933 + /* Drop cs */
13934 + AND_REG(&cc->gpioout, ~mask);
13935 + if (!sflash_poll(cc, offset)) {
13936 + /* Flash rejected command */
13937 + return -12;
13938 + }
13939 + }
13940 + } else {
13941 + ret = 1;
13942 + W_REG(&cc->flashaddress, offset);
13943 + W_REG(&cc->flashdata, *buf);
13944 + /* Page program */
13945 + sflash_cmd(cc, SFLASH_ST_PP);
13946 + }
13947 + break;
13948 + case SFLASH_AT:
13949 + mask = sfl->blocksize - 1;
13950 + page = (offset & ~mask) << 1;
13951 + byte = offset & mask;
13952 + /* Read main memory page into buffer 1 */
13953 + if (byte || len < sfl->blocksize) {
13954 + W_REG(&cc->flashaddress, page);
13955 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
13956 + /* 250 us for AT45DB321B */
13957 + SPINWAIT(sflash_poll(cc, offset), 1000);
13958 + ASSERT(!sflash_poll(cc, offset));
13959 + }
13960 + /* Write into buffer 1 */
13961 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
13962 + W_REG(&cc->flashaddress, byte++);
13963 + W_REG(&cc->flashdata, *buf++);
13964 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
13965 + }
13966 + /* Write buffer 1 into main memory page */
13967 + W_REG(&cc->flashaddress, page);
13968 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
13969 + break;
13970 + }
13971 +
13972 + return ret;
13973 +}
13974 +
13975 +/* Erase a region. Returns number of bytes scheduled for erasure.
13976 + * Caller should poll for completion.
13977 + */
13978 +int
13979 +sflash_erase(chipcregs_t *cc, uint offset)
13980 +{
13981 + struct sflash *sfl;
13982 +
13983 + if (offset >= sflash.size)
13984 + return -22;
13985 +
13986 + sfl = &sflash;
13987 + switch (sfl->type) {
13988 + case SFLASH_ST:
13989 + sflash_cmd(cc, SFLASH_ST_WREN);
13990 + W_REG(&cc->flashaddress, offset);
13991 + sflash_cmd(cc, SFLASH_ST_SE);
13992 + return sfl->blocksize;
13993 + case SFLASH_AT:
13994 + W_REG(&cc->flashaddress, offset << 1);
13995 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
13996 + return sfl->blocksize;
13997 + }
13998 +
13999 + return 0;
14000 +}
14001 +
14002 +/*
14003 + * writes the appropriate range of flash, a NULL buf simply erases
14004 + * the region of flash
14005 + */
14006 +int
14007 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
14008 +{
14009 + struct sflash *sfl;
14010 + uchar *block = NULL, *cur_ptr, *blk_ptr;
14011 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
14012 + uint blk_offset, blk_len, copied;
14013 + int bytes, ret = 0;
14014 +
14015 + /* Check address range */
14016 + if (len <= 0)
14017 + return 0;
14018 +
14019 + sfl = &sflash;
14020 + if ((offset + len) > sfl->size)
14021 + return -1;
14022 +
14023 + blocksize = sfl->blocksize;
14024 + mask = blocksize - 1;
14025 +
14026 + /* Allocate a block of mem */
14027 + if (!(block = MALLOC(NULL, blocksize)))
14028 + return -1;
14029 +
14030 + while (len) {
14031 + /* Align offset */
14032 + cur_offset = offset & ~mask;
14033 + cur_length = blocksize;
14034 + cur_ptr = block;
14035 +
14036 + remainder = blocksize - (offset & mask);
14037 + if (len < remainder)
14038 + cur_retlen = len;
14039 + else
14040 + cur_retlen = remainder;
14041 +
14042 + /* buf == NULL means erase only */
14043 + if (buf) {
14044 + /* Copy existing data into holding block if necessary */
14045 + if ((offset & mask) || (len < blocksize)) {
14046 + blk_offset = cur_offset;
14047 + blk_len = cur_length;
14048 + blk_ptr = cur_ptr;
14049 +
14050 + /* Copy entire block */
14051 + while(blk_len) {
14052 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
14053 + blk_offset += copied;
14054 + blk_len -= copied;
14055 + blk_ptr += copied;
14056 + }
14057 + }
14058 +
14059 + /* Copy input data into holding block */
14060 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
14061 + }
14062 +
14063 + /* Erase block */
14064 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
14065 + goto done;
14066 + while (sflash_poll(cc, (uint) cur_offset));
14067 +
14068 + /* buf == NULL means erase only */
14069 + if (!buf) {
14070 + offset += cur_retlen;
14071 + len -= cur_retlen;
14072 + continue;
14073 + }
14074 +
14075 + /* Write holding block */
14076 + while (cur_length > 0) {
14077 + if ((bytes = sflash_write(cc,
14078 + (uint) cur_offset,
14079 + (uint) cur_length,
14080 + (uchar *) cur_ptr)) < 0) {
14081 + ret = bytes;
14082 + goto done;
14083 + }
14084 + while (sflash_poll(cc, (uint) cur_offset));
14085 + cur_offset += bytes;
14086 + cur_length -= bytes;
14087 + cur_ptr += bytes;
14088 + }
14089 +
14090 + offset += cur_retlen;
14091 + len -= cur_retlen;
14092 + buf += cur_retlen;
14093 + }
14094 +
14095 + ret = len;
14096 +done:
14097 + if (block)
14098 + MFREE(NULL, block, blocksize);
14099 + return ret;
14100 +}
14101 +
14102 diff -Nur linux-2.4.32/arch/mips/bcm947xx/time.c linux-2.4.32-brcm/arch/mips/bcm947xx/time.c
14103 --- linux-2.4.32/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
14104 +++ linux-2.4.32-brcm/arch/mips/bcm947xx/time.c 2005-12-16 23:39:10.948837000 +0100
14105 @@ -0,0 +1,118 @@
14106 +/*
14107 + * Copyright 2004, Broadcom Corporation
14108 + * All Rights Reserved.
14109 + *
14110 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14111 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14112 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14113 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14114 + *
14115 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
14116 + */
14117 +#include <linux/config.h>
14118 +#include <linux/init.h>
14119 +#include <linux/kernel.h>
14120 +#include <linux/sched.h>
14121 +#include <linux/serial_reg.h>
14122 +#include <linux/interrupt.h>
14123 +#include <asm/addrspace.h>
14124 +#include <asm/io.h>
14125 +#include <asm/time.h>
14126 +
14127 +#include <typedefs.h>
14128 +#include <osl.h>
14129 +#include <sbutils.h>
14130 +#include <bcmnvram.h>
14131 +#include <sbconfig.h>
14132 +#include <sbextif.h>
14133 +#include <sbmips.h>
14134 +
14135 +/* Global SB handle */
14136 +extern void *bcm947xx_sbh;
14137 +extern spinlock_t bcm947xx_sbh_lock;
14138 +
14139 +/* Convenience */
14140 +#define sbh bcm947xx_sbh
14141 +#define sbh_lock bcm947xx_sbh_lock
14142 +
14143 +extern int panic_timeout;
14144 +static int watchdog = 0;
14145 +static u8 *mcr = NULL;
14146 +
14147 +void __init
14148 +bcm947xx_time_init(void)
14149 +{
14150 + unsigned int hz;
14151 + extifregs_t *eir;
14152 +
14153 + /*
14154 + * Use deterministic values for initial counter interrupt
14155 + * so that calibrate delay avoids encountering a counter wrap.
14156 + */
14157 + write_c0_count(0);
14158 + write_c0_compare(0xffff);
14159 +
14160 + if (!(hz = sb_mips_clock(sbh)))
14161 + hz = 100000000;
14162 +
14163 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
14164 + (hz + 500000) / 1000000);
14165 +
14166 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
14167 + mips_hpt_frequency = hz / 2;
14168 +
14169 + /* Set watchdog interval in ms */
14170 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
14171 +
14172 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
14173 + if (watchdog > 0) {
14174 + if (watchdog < 3000)
14175 + watchdog = 3000;
14176 + }
14177 +
14178 +
14179 + /* Set panic timeout in seconds */
14180 + panic_timeout = watchdog / 1000;
14181 +
14182 + /* Setup blink */
14183 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
14184 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
14185 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
14186 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
14187 + }
14188 +}
14189 +
14190 +static void
14191 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
14192 +{
14193 + /* Generic MIPS timer code */
14194 + timer_interrupt(irq, dev_id, regs);
14195 +
14196 + /* Set the watchdog timer to reset after the specified number of ms */
14197 + if (watchdog > 0)
14198 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
14199 +
14200 +#ifdef CONFIG_HWSIM
14201 + (*((int *)0xa0000f1c))++;
14202 +#else
14203 + /* Blink one of the LEDs in the external UART */
14204 + if (mcr && !(jiffies % (HZ/2)))
14205 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
14206 +#endif
14207 +}
14208 +
14209 +static struct irqaction bcm947xx_timer_irqaction = {
14210 + bcm947xx_timer_interrupt,
14211 + SA_INTERRUPT,
14212 + 0,
14213 + "timer",
14214 + NULL,
14215 + NULL
14216 +};
14217 +
14218 +void __init
14219 +bcm947xx_timer_setup(struct irqaction *irq)
14220 +{
14221 + /* Enable the timer interrupt */
14222 + setup_irq(7, &bcm947xx_timer_irqaction);
14223 +}
14224 diff -Nur linux-2.4.32/arch/mips/config-shared.in linux-2.4.32-brcm/arch/mips/config-shared.in
14225 --- linux-2.4.32/arch/mips/config-shared.in 2005-01-19 15:09:27.000000000 +0100
14226 +++ linux-2.4.32-brcm/arch/mips/config-shared.in 2005-12-16 23:39:11.080845250 +0100
14227 @@ -205,6 +205,14 @@
14228 fi
14229 define_bool CONFIG_MIPS_RTC y
14230 fi
14231 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
14232 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
14233 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14234 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
14235 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
14236 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
14237 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
14238 +fi
14239 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
14240 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
14241 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
14242 @@ -226,6 +234,11 @@
14243 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
14244
14245 #
14246 +# Provide an option for a default kernel command line
14247 +#
14248 +string 'Default kernel command string' CONFIG_CMDLINE ""
14249 +
14250 +#
14251 # Select some configuration options automatically based on user selections.
14252 #
14253 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
14254 @@ -533,6 +546,13 @@
14255 define_bool CONFIG_SWAP_IO_SPACE_L y
14256 define_bool CONFIG_BOOT_ELF32 y
14257 fi
14258 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14259 + define_bool CONFIG_PCI y
14260 + define_bool CONFIG_NONCOHERENT_IO y
14261 + define_bool CONFIG_NEW_TIME_C y
14262 + define_bool CONFIG_NEW_IRQ y
14263 + define_bool CONFIG_HND y
14264 +fi
14265 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
14266 define_bool CONFIG_ARC32 y
14267 define_bool CONFIG_ARC_MEMORY y
14268 @@ -1011,7 +1031,11 @@
14269
14270 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
14271 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
14272 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
14273 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14274 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
14275 +else
14276 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
14277 +fi
14278 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
14279 if [ "$CONFIG_KGDB" = "y" ]; then
14280 define_bool CONFIG_DEBUG_INFO y
14281 diff -Nur linux-2.4.32/arch/mips/kernel/cpu-probe.c linux-2.4.32-brcm/arch/mips/kernel/cpu-probe.c
14282 --- linux-2.4.32/arch/mips/kernel/cpu-probe.c 2005-01-19 15:09:29.000000000 +0100
14283 +++ linux-2.4.32-brcm/arch/mips/kernel/cpu-probe.c 2005-12-16 23:39:11.084845500 +0100
14284 @@ -174,7 +174,7 @@
14285
14286 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
14287 {
14288 - switch (c->processor_id & 0xff00) {
14289 + switch (c->processor_id & PRID_IMP_MASK) {
14290 case PRID_IMP_R2000:
14291 c->cputype = CPU_R2000;
14292 c->isa_level = MIPS_CPU_ISA_I;
14293 @@ -184,7 +184,7 @@
14294 c->tlbsize = 64;
14295 break;
14296 case PRID_IMP_R3000:
14297 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
14298 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
14299 if (cpu_has_confreg())
14300 c->cputype = CPU_R3081E;
14301 else
14302 @@ -199,12 +199,12 @@
14303 break;
14304 case PRID_IMP_R4000:
14305 if (read_c0_config() & CONF_SC) {
14306 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14307 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14308 c->cputype = CPU_R4400PC;
14309 else
14310 c->cputype = CPU_R4000PC;
14311 } else {
14312 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14313 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14314 c->cputype = CPU_R4400SC;
14315 else
14316 c->cputype = CPU_R4000SC;
14317 @@ -450,7 +450,7 @@
14318 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
14319 {
14320 decode_config1(c);
14321 - switch (c->processor_id & 0xff00) {
14322 + switch (c->processor_id & PRID_IMP_MASK) {
14323 case PRID_IMP_4KC:
14324 c->cputype = CPU_4KC;
14325 c->isa_level = MIPS_CPU_ISA_M32;
14326 @@ -491,10 +491,10 @@
14327 {
14328 decode_config1(c);
14329 c->options |= MIPS_CPU_PREFETCH;
14330 - switch (c->processor_id & 0xff00) {
14331 + switch (c->processor_id & PRID_IMP_MASK) {
14332 case PRID_IMP_AU1_REV1:
14333 case PRID_IMP_AU1_REV2:
14334 - switch ((c->processor_id >> 24) & 0xff) {
14335 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
14336 case 0:
14337 c->cputype = CPU_AU1000;
14338 break;
14339 @@ -522,10 +522,34 @@
14340 }
14341 }
14342
14343 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
14344 +{
14345 + decode_config1(c);
14346 + c->options |= MIPS_CPU_PREFETCH;
14347 + switch (c->processor_id & PRID_IMP_MASK) {
14348 + case PRID_IMP_BCM4710:
14349 + c->cputype = CPU_BCM4710;
14350 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14351 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14352 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14353 + break;
14354 + case PRID_IMP_4KC:
14355 + case PRID_IMP_BCM3302:
14356 + c->cputype = CPU_BCM3302;
14357 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14358 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14359 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14360 + break;
14361 + default:
14362 + c->cputype = CPU_UNKNOWN;
14363 + break;
14364 + }
14365 +}
14366 +
14367 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
14368 {
14369 decode_config1(c);
14370 - switch (c->processor_id & 0xff00) {
14371 + switch (c->processor_id & PRID_IMP_MASK) {
14372 case PRID_IMP_SB1:
14373 c->cputype = CPU_SB1;
14374 c->isa_level = MIPS_CPU_ISA_M64;
14375 @@ -547,7 +571,7 @@
14376 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
14377 {
14378 decode_config1(c);
14379 - switch (c->processor_id & 0xff00) {
14380 + switch (c->processor_id & PRID_IMP_MASK) {
14381 case PRID_IMP_SR71000:
14382 c->cputype = CPU_SR71000;
14383 c->isa_level = MIPS_CPU_ISA_M64;
14384 @@ -572,7 +596,7 @@
14385 c->cputype = CPU_UNKNOWN;
14386
14387 c->processor_id = read_c0_prid();
14388 - switch (c->processor_id & 0xff0000) {
14389 + switch (c->processor_id & PRID_COMP_MASK) {
14390
14391 case PRID_COMP_LEGACY:
14392 cpu_probe_legacy(c);
14393 @@ -583,6 +607,9 @@
14394 case PRID_COMP_ALCHEMY:
14395 cpu_probe_alchemy(c);
14396 break;
14397 + case PRID_COMP_BROADCOM:
14398 + cpu_probe_broadcom(c);
14399 + break;
14400 case PRID_COMP_SIBYTE:
14401 cpu_probe_sibyte(c);
14402 break;
14403 diff -Nur linux-2.4.32/arch/mips/kernel/head.S linux-2.4.32-brcm/arch/mips/kernel/head.S
14404 --- linux-2.4.32/arch/mips/kernel/head.S 2005-01-19 15:09:29.000000000 +0100
14405 +++ linux-2.4.32-brcm/arch/mips/kernel/head.S 2005-12-16 23:39:11.084845500 +0100
14406 @@ -28,12 +28,20 @@
14407 #include <asm/mipsregs.h>
14408 #include <asm/stackframe.h>
14409
14410 +#ifdef CONFIG_BCM4710
14411 +#undef eret
14412 +#define eret nop; nop; eret
14413 +#endif
14414 +
14415 .text
14416 + j kernel_entry
14417 + nop
14418 +
14419 /*
14420 * Reserved space for exception handlers.
14421 * Necessary for machines which link their kernels at KSEG0.
14422 */
14423 - .fill 0x400
14424 + .fill 0x3f4
14425
14426 /* The following two symbols are used for kernel profiling. */
14427 EXPORT(stext)
14428 diff -Nur linux-2.4.32/arch/mips/kernel/proc.c linux-2.4.32-brcm/arch/mips/kernel/proc.c
14429 --- linux-2.4.32/arch/mips/kernel/proc.c 2005-01-19 15:09:29.000000000 +0100
14430 +++ linux-2.4.32-brcm/arch/mips/kernel/proc.c 2005-12-16 23:39:11.084845500 +0100
14431 @@ -78,9 +78,10 @@
14432 [CPU_AU1550] "Au1550",
14433 [CPU_24K] "MIPS 24K",
14434 [CPU_AU1200] "Au1200",
14435 + [CPU_BCM4710] "BCM4710",
14436 + [CPU_BCM3302] "BCM3302",
14437 };
14438
14439 -
14440 static int show_cpuinfo(struct seq_file *m, void *v)
14441 {
14442 unsigned int version = current_cpu_data.processor_id;
14443 diff -Nur linux-2.4.32/arch/mips/kernel/setup.c linux-2.4.32-brcm/arch/mips/kernel/setup.c
14444 --- linux-2.4.32/arch/mips/kernel/setup.c 2005-01-19 15:09:29.000000000 +0100
14445 +++ linux-2.4.32-brcm/arch/mips/kernel/setup.c 2005-12-16 23:39:11.140849000 +0100
14446 @@ -495,6 +495,7 @@
14447 void swarm_setup(void);
14448 void hp_setup(void);
14449 void au1x00_setup(void);
14450 + void brcm_setup(void);
14451 void frame_info_init(void);
14452
14453 frame_info_init();
14454 @@ -693,6 +694,11 @@
14455 pmc_yosemite_setup();
14456 break;
14457 #endif
14458 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
14459 + case MACH_GROUP_BRCM:
14460 + brcm_setup();
14461 + break;
14462 +#endif
14463 default:
14464 panic("Unsupported architecture");
14465 }
14466 diff -Nur linux-2.4.32/arch/mips/kernel/traps.c linux-2.4.32-brcm/arch/mips/kernel/traps.c
14467 --- linux-2.4.32/arch/mips/kernel/traps.c 2005-01-19 15:09:29.000000000 +0100
14468 +++ linux-2.4.32-brcm/arch/mips/kernel/traps.c 2005-12-16 23:39:11.140849000 +0100
14469 @@ -913,6 +913,7 @@
14470 void __init trap_init(void)
14471 {
14472 extern char except_vec1_generic;
14473 + extern char except_vec2_generic;
14474 extern char except_vec3_generic, except_vec3_r4000;
14475 extern char except_vec_ejtag_debug;
14476 extern char except_vec4;
14477 @@ -922,6 +923,7 @@
14478
14479 /* Copy the generic exception handler code to it's final destination. */
14480 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
14481 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
14482
14483 /*
14484 * Setup default vectors
14485 @@ -980,6 +982,12 @@
14486 set_except_vector(13, handle_tr);
14487 set_except_vector(22, handle_mdmx);
14488
14489 + if (current_cpu_data.cputype == CPU_SB1) {
14490 + /* Enable timer interrupt and scd mapped interrupt */
14491 + clear_c0_status(0xf000);
14492 + set_c0_status(0xc00);
14493 + }
14494 +
14495 if (cpu_has_fpu && !cpu_has_nofpuex)
14496 set_except_vector(15, handle_fpe);
14497
14498 diff -Nur linux-2.4.32/arch/mips/Makefile linux-2.4.32-brcm/arch/mips/Makefile
14499 --- linux-2.4.32/arch/mips/Makefile 2005-01-19 15:09:26.000000000 +0100
14500 +++ linux-2.4.32-brcm/arch/mips/Makefile 2005-12-16 23:39:10.668819500 +0100
14501 @@ -715,6 +715,19 @@
14502 endif
14503
14504 #
14505 +# Broadcom BCM947XX variants
14506 +#
14507 +ifdef CONFIG_BCM947XX
14508 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
14509 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
14510 +LOADADDR := 0x80001000
14511 +
14512 +zImage: vmlinux
14513 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
14514 +export LOADADDR
14515 +endif
14516 +
14517 +#
14518 # Choosing incompatible machines durings configuration will result in
14519 # error messages during linking. Select a default linkscript if
14520 # none has been choosen above.
14521 @@ -767,6 +780,7 @@
14522 $(MAKE) -C arch/$(ARCH)/tools clean
14523 $(MAKE) -C arch/mips/baget clean
14524 $(MAKE) -C arch/mips/lasat clean
14525 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
14526
14527 archmrproper:
14528 @$(MAKEBOOT) mrproper
14529 diff -Nur linux-2.4.32/arch/mips/mm/c-r4k.c linux-2.4.32-brcm/arch/mips/mm/c-r4k.c
14530 --- linux-2.4.32/arch/mips/mm/c-r4k.c 2005-01-19 15:09:29.000000000 +0100
14531 +++ linux-2.4.32-brcm/arch/mips/mm/c-r4k.c 2005-12-16 23:39:11.144849250 +0100
14532 @@ -1114,3 +1114,47 @@
14533 build_clear_page();
14534 build_copy_page();
14535 }
14536 +
14537 +#ifdef CONFIG_BCM4704
14538 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
14539 +{
14540 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
14541 + int i;
14542 + for (i = 0; i < nbytes; i += ic_lsize)
14543 + fill_icache_line((addr + i));
14544 +}
14545 +
14546 +/*
14547 + * This must be run from the cache on 4704A0
14548 + * so there are no mips core BIU ops in progress
14549 + * when the PFC is enabled.
14550 + */
14551 +#define PFC_CR0 0xff400000 /* control reg 0 */
14552 +#define PFC_CR1 0xff400004 /* control reg 1 */
14553 +static void __init enable_pfc(u32 mode)
14554 +{
14555 + /* write range */
14556 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
14557 +
14558 + /* enable */
14559 + *(volatile u32 *)PFC_CR0 = mode;
14560 +}
14561 +#endif
14562 +
14563 +
14564 +void check_enable_mips_pfc(int val)
14565 +{
14566 +
14567 +#ifdef CONFIG_BCM4704
14568 + struct cpuinfo_mips *c = &current_cpu_data;
14569 +
14570 + /* enable prefetch cache */
14571 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
14572 + && (read_c0_diag() & (1 << 29))) {
14573 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
14574 + enable_pfc(val);
14575 + }
14576 +#endif
14577 +}
14578 +
14579 +
14580 diff -Nur linux-2.4.32/arch/mips/pci/Makefile linux-2.4.32-brcm/arch/mips/pci/Makefile
14581 --- linux-2.4.32/arch/mips/pci/Makefile 2005-01-19 15:09:29.000000000 +0100
14582 +++ linux-2.4.32-brcm/arch/mips/pci/Makefile 2005-12-16 23:39:11.144849250 +0100
14583 @@ -13,7 +13,9 @@
14584 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
14585 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
14586 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
14587 +ifndef CONFIG_BCM947XX
14588 obj-y += pci.o
14589 +endif
14590 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
14591
14592 include $(TOPDIR)/Rules.make
14593 diff -Nur linux-2.4.32/drivers/char/serial.c linux-2.4.32-brcm/drivers/char/serial.c
14594 --- linux-2.4.32/drivers/char/serial.c 2005-11-16 20:12:54.000000000 +0100
14595 +++ linux-2.4.32-brcm/drivers/char/serial.c 2005-12-16 23:39:11.200852750 +0100
14596 @@ -422,6 +422,10 @@
14597 return inb(info->port+1);
14598 #endif
14599 case SERIAL_IO_MEM:
14600 +#ifdef CONFIG_BCM4310
14601 + readb((unsigned long) info->iomem_base +
14602 + (UART_SCR<<info->iomem_reg_shift));
14603 +#endif
14604 return readb((unsigned long) info->iomem_base +
14605 (offset<<info->iomem_reg_shift));
14606 default:
14607 @@ -442,6 +446,9 @@
14608 case SERIAL_IO_MEM:
14609 writeb(value, (unsigned long) info->iomem_base +
14610 (offset<<info->iomem_reg_shift));
14611 +#ifdef CONFIG_BCM4704
14612 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
14613 +#endif
14614 break;
14615 default:
14616 outb(value, info->port+offset);
14617 @@ -1704,7 +1711,7 @@
14618 /* Special case since 134 is really 134.5 */
14619 quot = (2*baud_base / 269);
14620 else if (baud)
14621 - quot = baud_base / baud;
14622 + quot = (baud_base + (baud / 2)) / baud;
14623 }
14624 /* If the quotient is zero refuse the change */
14625 if (!quot && old_termios) {
14626 @@ -1721,12 +1728,12 @@
14627 /* Special case since 134 is really 134.5 */
14628 quot = (2*baud_base / 269);
14629 else if (baud)
14630 - quot = baud_base / baud;
14631 + quot = (baud_base + (baud / 2)) / baud;
14632 }
14633 }
14634 /* As a last resort, if the quotient is zero, default to 9600 bps */
14635 if (!quot)
14636 - quot = baud_base / 9600;
14637 + quot = (baud_base + 4800) / 9600;
14638 /*
14639 * Work around a bug in the Oxford Semiconductor 952 rev B
14640 * chip which causes it to seriously miscalculate baud rates
14641 @@ -5982,6 +5989,13 @@
14642 * Divisor, bytesize and parity
14643 */
14644 state = rs_table + co->index;
14645 + /*
14646 + * Safe guard: state structure must have been initialized
14647 + */
14648 + if (state->iomem_base == NULL) {
14649 + printk("!unable to setup serial console!\n");
14650 + return -1;
14651 + }
14652 if (doflow)
14653 state->flags |= ASYNC_CONS_FLOW;
14654 info = &async_sercons;
14655 @@ -5995,7 +6009,7 @@
14656 info->io_type = state->io_type;
14657 info->iomem_base = state->iomem_base;
14658 info->iomem_reg_shift = state->iomem_reg_shift;
14659 - quot = state->baud_base / baud;
14660 + quot = (state->baud_base + (baud / 2)) / baud;
14661 cval = cflag & (CSIZE | CSTOPB);
14662 #if defined(__powerpc__) || defined(__alpha__)
14663 cval >>= 8;
14664 diff -Nur linux-2.4.32/drivers/net/Config.in linux-2.4.32-brcm/drivers/net/Config.in
14665 --- linux-2.4.32/drivers/net/Config.in 2005-01-19 15:09:56.000000000 +0100
14666 +++ linux-2.4.32-brcm/drivers/net/Config.in 2005-12-16 23:39:11.232854750 +0100
14667 @@ -2,6 +2,8 @@
14668 # Network device configuration
14669 #
14670
14671 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
14672 +
14673 source drivers/net/arcnet/Config.in
14674
14675 tristate 'Dummy net driver support' CONFIG_DUMMY
14676 diff -Nur linux-2.4.32/drivers/net/hnd/bcmsrom.c linux-2.4.32-brcm/drivers/net/hnd/bcmsrom.c
14677 --- linux-2.4.32/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
14678 +++ linux-2.4.32-brcm/drivers/net/hnd/bcmsrom.c 2005-12-16 23:39:11.284858000 +0100
14679 @@ -0,0 +1,936 @@
14680 +/*
14681 + * Misc useful routines to access NIC SROM/OTP .
14682 + *
14683 + * Copyright 2005, Broadcom Corporation
14684 + * All Rights Reserved.
14685 + *
14686 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14687 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14688 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14689 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14690 + * $Id$
14691 + */
14692 +
14693 +#include <typedefs.h>
14694 +#include <osl.h>
14695 +#include <bcmutils.h>
14696 +#include <bcmsrom.h>
14697 +#include <bcmdevs.h>
14698 +#include <bcmendian.h>
14699 +#include <sbpcmcia.h>
14700 +#include <pcicfg.h>
14701 +#include <sbutils.h>
14702 +#include <bcmnvram.h>
14703 +
14704 +#include <proto/ethernet.h> /* for sprom content groking */
14705 +
14706 +#define VARS_MAX 4096 /* should be reduced */
14707 +
14708 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
14709 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
14710 +
14711 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
14712 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
14713 +static int initvars_flash_sb(void *sbh, char **vars, int *count);
14714 +static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
14715 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
14716 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
14717 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
14718 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
14719 +
14720 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
14721 +static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
14722 +
14723 +/*
14724 + * Initialize local vars from the right source for this platform.
14725 + * Return 0 on success, nonzero on error.
14726 + */
14727 +int
14728 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
14729 +{
14730 + ASSERT(bustype == BUSTYPE(bustype));
14731 + if (vars == NULL || count == NULL)
14732 + return (0);
14733 +
14734 + switch (BUSTYPE(bustype)) {
14735 + case SB_BUS:
14736 + case JTAG_BUS:
14737 + return initvars_flash_sb(sbh, vars, count);
14738 +
14739 + case PCI_BUS:
14740 + ASSERT(curmap); /* can not be NULL */
14741 + return initvars_srom_pci(sbh, curmap, vars, count);
14742 +
14743 + case PCMCIA_BUS:
14744 + return initvars_cis_pcmcia(sbh, osh, vars, count);
14745 +
14746 +
14747 + default:
14748 + ASSERT(0);
14749 + }
14750 + return (-1);
14751 +}
14752 +
14753 +/* support only 16-bit word read from srom */
14754 +int
14755 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
14756 +{
14757 + void *srom;
14758 + uint i, off, nw;
14759 +
14760 + ASSERT(bustype == BUSTYPE(bustype));
14761 +
14762 + /* check input - 16-bit access only */
14763 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
14764 + return 1;
14765 +
14766 + off = byteoff / 2;
14767 + nw = nbytes / 2;
14768 +
14769 + if (BUSTYPE(bustype) == PCI_BUS) {
14770 + if (!curmap)
14771 + return 1;
14772 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
14773 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
14774 + return 1;
14775 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
14776 + for (i = 0; i < nw; i++) {
14777 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
14778 + return 1;
14779 + }
14780 + } else {
14781 + return 1;
14782 + }
14783 +
14784 + return 0;
14785 +}
14786 +
14787 +/* support only 16-bit word write into srom */
14788 +int
14789 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
14790 +{
14791 + uint16 *srom;
14792 + uint i, off, nw, crc_range;
14793 + uint16 image[SPROM_SIZE], *p;
14794 + uint8 crc;
14795 + volatile uint32 val32;
14796 +
14797 + ASSERT(bustype == BUSTYPE(bustype));
14798 +
14799 + /* check input - 16-bit access only */
14800 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
14801 + return 1;
14802 +
14803 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
14804 +
14805 + /* if changes made inside crc cover range */
14806 + if (byteoff < crc_range) {
14807 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
14808 + /* read data including entire first 64 words from srom */
14809 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
14810 + return 1;
14811 + /* make changes */
14812 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
14813 + /* calculate crc */
14814 + htol16_buf(image, crc_range);
14815 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
14816 + ltoh16_buf(image, crc_range);
14817 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
14818 + p = image;
14819 + off = 0;
14820 + } else {
14821 + p = buf;
14822 + off = byteoff / 2;
14823 + nw = nbytes / 2;
14824 + }
14825 +
14826 + if (BUSTYPE(bustype) == PCI_BUS) {
14827 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
14828 + /* enable writes to the SPROM */
14829 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
14830 + val32 |= SPROM_WRITEEN;
14831 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
14832 + bcm_mdelay(WRITE_ENABLE_DELAY);
14833 + /* write srom */
14834 + for (i = 0; i < nw; i++) {
14835 + W_REG(&srom[off + i], p[i]);
14836 + bcm_mdelay(WRITE_WORD_DELAY);
14837 + }
14838 + /* disable writes to the SPROM */
14839 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
14840 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
14841 + /* enable writes to the SPROM */
14842 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
14843 + return 1;
14844 + bcm_mdelay(WRITE_ENABLE_DELAY);
14845 + /* write srom */
14846 + for (i = 0; i < nw; i++) {
14847 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
14848 + bcm_mdelay(WRITE_WORD_DELAY);
14849 + }
14850 + /* disable writes to the SPROM */
14851 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
14852 + return 1;
14853 + } else {
14854 + return 1;
14855 + }
14856 +
14857 + bcm_mdelay(WRITE_ENABLE_DELAY);
14858 + return 0;
14859 +}
14860 +
14861 +
14862 +static int
14863 +srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
14864 +{
14865 + char eabuf[32];
14866 + char *vp, *base;
14867 + uint8 tup, tlen, sromrev = 1;
14868 + int i, j;
14869 + uint varsize;
14870 + bool ag_init = FALSE;
14871 + uint32 w32;
14872 +
14873 + ASSERT(vars);
14874 + ASSERT(count);
14875 +
14876 + base = vp = MALLOC(osh, VARS_MAX);
14877 + ASSERT(vp);
14878 + if (!vp)
14879 + return -2;
14880 +
14881 + i = 0;
14882 + do {
14883 + tup = cis[i++];
14884 + tlen = cis[i++];
14885 + if ((i + tlen) >= CIS_SIZE)
14886 + break;
14887 +
14888 + switch (tup) {
14889 + case CISTPL_MANFID:
14890 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
14891 + vp++;
14892 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
14893 + vp++;
14894 + break;
14895 +
14896 + case CISTPL_FUNCE:
14897 + if (cis[i] == LAN_NID) {
14898 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
14899 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
14900 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
14901 + vp++;
14902 + }
14903 + break;
14904 +
14905 + case CISTPL_CFTABLE:
14906 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
14907 + vp++;
14908 + break;
14909 +
14910 + case CISTPL_BRCM_HNBU:
14911 + switch (cis[i]) {
14912 + case HNBU_SROMREV:
14913 + sromrev = cis[i + 1];
14914 + break;
14915 +
14916 + case HNBU_CHIPID:
14917 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
14918 + vp++;
14919 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
14920 + vp++;
14921 + if (tlen == 7) {
14922 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
14923 + vp++;
14924 + }
14925 + break;
14926 +
14927 + case HNBU_BOARDREV:
14928 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
14929 + vp++;
14930 + break;
14931 +
14932 + case HNBU_AA:
14933 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
14934 + vp++;
14935 + break;
14936 +
14937 + case HNBU_AG:
14938 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
14939 + vp++;
14940 + ag_init = TRUE;
14941 + break;
14942 +
14943 + case HNBU_CC:
14944 + ASSERT(sromrev > 1);
14945 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
14946 + vp++;
14947 + break;
14948 +
14949 + case HNBU_PAPARMS:
14950 + if (tlen == 2) {
14951 + ASSERT(sromrev == 1);
14952 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
14953 + vp++;
14954 + } else if (tlen >= 9) {
14955 + if (tlen == 10) {
14956 + ASSERT(sromrev == 2);
14957 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
14958 + vp++;
14959 + } else
14960 + ASSERT(tlen == 9);
14961 +
14962 + for (j = 0; j < 3; j++) {
14963 + vp += sprintf(vp, "pa0b%d=%d", j,
14964 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
14965 + vp++;
14966 + }
14967 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
14968 + vp++;
14969 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
14970 + vp++;
14971 + } else
14972 + ASSERT(tlen >= 9);
14973 + break;
14974 +
14975 + case HNBU_OEM:
14976 + ASSERT(sromrev == 1);
14977 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
14978 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
14979 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
14980 + vp++;
14981 + break;
14982 +
14983 + case HNBU_BOARDFLAGS:
14984 + w32 = (cis[i + 2] << 8) + cis[i + 1];
14985 + if (tlen == 5)
14986 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
14987 + vp += sprintf(vp, "boardflags=0x%x", w32);
14988 + vp++;
14989 + break;
14990 +
14991 + case HNBU_LEDS:
14992 + if (cis[i + 1] != 0xff) {
14993 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
14994 + vp++;
14995 + }
14996 + if (cis[i + 2] != 0xff) {
14997 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
14998 + vp++;
14999 + }
15000 + if (cis[i + 3] != 0xff) {
15001 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
15002 + vp++;
15003 + }
15004 + if (cis[i + 4] != 0xff) {
15005 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
15006 + vp++;
15007 + }
15008 + break;
15009 +
15010 + case HNBU_CCODE:
15011 + ASSERT(sromrev > 1);
15012 + vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
15013 + vp++;
15014 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
15015 + vp++;
15016 + break;
15017 +
15018 + case HNBU_CCKPO:
15019 + ASSERT(sromrev > 2);
15020 + vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
15021 + vp++;
15022 + break;
15023 +
15024 + case HNBU_OFDMPO:
15025 + ASSERT(sromrev > 2);
15026 + vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
15027 + (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
15028 + vp++;
15029 + break;
15030 + }
15031 + break;
15032 +
15033 + }
15034 + i += tlen;
15035 + } while (tup != 0xff);
15036 +
15037 + /* Set the srom version */
15038 + vp += sprintf(vp, "sromrev=%d", sromrev);
15039 + vp++;
15040 +
15041 + /* if there is no antenna gain field, set default */
15042 + if (ag_init == FALSE) {
15043 + ASSERT(sromrev == 1);
15044 + vp += sprintf(vp, "ag0=%d", 0xff);
15045 + vp++;
15046 + }
15047 +
15048 + /* final nullbyte terminator */
15049 + *vp++ = '\0';
15050 + varsize = (uint)(vp - base);
15051 +
15052 + ASSERT((vp - base) < VARS_MAX);
15053 +
15054 + if (varsize == VARS_MAX) {
15055 + *vars = base;
15056 + } else {
15057 + vp = MALLOC(osh, varsize);
15058 + ASSERT(vp);
15059 + if (vp)
15060 + bcopy(base, vp, varsize);
15061 + MFREE(osh, base, VARS_MAX);
15062 + *vars = vp;
15063 + if (!vp) {
15064 + *count = 0;
15065 + return -2;
15066 + }
15067 + }
15068 + *count = varsize;
15069 +
15070 + return (0);
15071 +}
15072 +
15073 +
15074 +/* set PCMCIA sprom command register */
15075 +static int
15076 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
15077 +{
15078 + uint8 status = 0;
15079 + uint wait_cnt = 1000;
15080 +
15081 + /* write sprom command register */
15082 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
15083 +
15084 + /* wait status */
15085 + while (wait_cnt--) {
15086 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
15087 + if (status & SROM_DONE)
15088 + return 0;
15089 + }
15090 +
15091 + return 1;
15092 +}
15093 +
15094 +/* read a word from the PCMCIA srom */
15095 +static int
15096 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
15097 +{
15098 + uint8 addr_l, addr_h, data_l, data_h;
15099 +
15100 + addr_l = (uint8)((addr * 2) & 0xff);
15101 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15102 +
15103 + /* set address */
15104 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15105 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15106 +
15107 + /* do read */
15108 + if (sprom_cmd_pcmcia(osh, SROM_READ))
15109 + return 1;
15110 +
15111 + /* read data */
15112 + data_h = data_l = 0;
15113 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
15114 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
15115 +
15116 + *data = (data_h << 8) | data_l;
15117 + return 0;
15118 +}
15119 +
15120 +/* write a word to the PCMCIA srom */
15121 +static int
15122 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
15123 +{
15124 + uint8 addr_l, addr_h, data_l, data_h;
15125 +
15126 + addr_l = (uint8)((addr * 2) & 0xff);
15127 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15128 + data_l = (uint8)(data & 0xff);
15129 + data_h = (uint8)((data >> 8) & 0xff);
15130 +
15131 + /* set address */
15132 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15133 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15134 +
15135 + /* write data */
15136 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
15137 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
15138 +
15139 + /* do write */
15140 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
15141 +}
15142 +
15143 +/*
15144 + * Read in and validate sprom.
15145 + * Return 0 on success, nonzero on error.
15146 + */
15147 +static int
15148 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
15149 +{
15150 + int err = 0;
15151 + uint i;
15152 +
15153 + /* read the sprom */
15154 + for (i = 0; i < nwords; i++)
15155 + buf[i] = R_REG(&sprom[wordoff + i]);
15156 +
15157 + if (check_crc) {
15158 + /* fixup the endianness so crc8 will pass */
15159 + htol16_buf(buf, nwords * 2);
15160 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
15161 + err = 1;
15162 + /* now correct the endianness of the byte array */
15163 + ltoh16_buf(buf, nwords * 2);
15164 + }
15165 +
15166 + return err;
15167 +}
15168 +
15169 +/*
15170 +* Create variable table from memory.
15171 +* Return 0 on success, nonzero on error.
15172 +*/
15173 +static int
15174 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
15175 +{
15176 + int c = (int)(end - start);
15177 +
15178 + /* do it only when there is more than just the null string */
15179 + if (c > 1) {
15180 + char *vp = MALLOC(osh, c);
15181 + ASSERT(vp);
15182 + if (!vp)
15183 + return BCME_NOMEM;
15184 + bcopy(start, vp, c);
15185 + *vars = vp;
15186 + *count = c;
15187 + }
15188 + else {
15189 + *vars = NULL;
15190 + *count = 0;
15191 + }
15192 +
15193 + return 0;
15194 +}
15195 +
15196 +/*
15197 +* Find variables with <devpath> from flash. 'base' points to the beginning
15198 +* of the table upon enter and to the end of the table upon exit when success.
15199 +* Return 0 on success, nonzero on error.
15200 +*/
15201 +static int
15202 +initvars_flash(osl_t *osh, char **base, int size, char *devpath)
15203 +{
15204 + char *vp = *base;
15205 + char *flash;
15206 + int err;
15207 + char *s;
15208 + uint l, dl, copy_len;
15209 +
15210 + /* allocate memory and read in flash */
15211 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
15212 + return BCME_NOMEM;
15213 + if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
15214 + goto exit;
15215 +
15216 + /* grab vars with the <devpath> prefix in name */
15217 + dl = strlen(devpath);
15218 + for (s = flash; s && *s; s += l + 1) {
15219 + l = strlen(s);
15220 +
15221 + /* skip non-matching variable */
15222 + if (strncmp(s, devpath, dl))
15223 + continue;
15224 +
15225 + /* is there enough room to copy? */
15226 + copy_len = l - dl + 1;
15227 + if (size < (int)copy_len) {
15228 + err = BCME_BUFTOOSHORT;
15229 + goto exit;
15230 + }
15231 +
15232 + /* no prefix, just the name=value */
15233 + strcpy(vp, &s[dl]);
15234 + vp += copy_len;
15235 + size -= copy_len;
15236 + }
15237 +
15238 + /* add null string as terminator */
15239 + if (size < 1) {
15240 + err = BCME_BUFTOOSHORT;
15241 + goto exit;
15242 + }
15243 + *vp++ = '\0';
15244 +
15245 + *base = vp;
15246 +
15247 +exit: MFREE(osh, flash, NVRAM_SPACE);
15248 + return err;
15249 +}
15250 +
15251 +/*
15252 + * Initialize nonvolatile variable table from flash.
15253 + * Return 0 on success, nonzero on error.
15254 + */
15255 +static int
15256 +initvars_flash_sb(void *sbh, char **vars, int *count)
15257 +{
15258 + osl_t *osh = sb_osh(sbh);
15259 + char devpath[SB_DEVPATH_BUFSZ];
15260 + char *vp, *base;
15261 + int err;
15262 +
15263 + ASSERT(vars);
15264 + ASSERT(count);
15265 +
15266 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15267 + return err;
15268 +
15269 + base = vp = MALLOC(osh, VARS_MAX);
15270 + ASSERT(vp);
15271 + if (!vp)
15272 + return BCME_NOMEM;
15273 +
15274 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15275 + goto err;
15276 +
15277 + err = initvars_table(osh, base, vp, vars, count);
15278 +
15279 +err: MFREE(osh, base, VARS_MAX);
15280 + return err;
15281 +}
15282 +
15283 +/*
15284 + * Initialize nonvolatile variable table from sprom.
15285 + * Return 0 on success, nonzero on error.
15286 + */
15287 +static int
15288 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
15289 +{
15290 + uint16 w, b[64];
15291 + uint8 sromrev;
15292 + struct ether_addr ea;
15293 + char eabuf[32];
15294 + uint32 w32;
15295 + int woff, i;
15296 + char *vp, *base;
15297 + osl_t *osh = sb_osh(sbh);
15298 + bool flash = FALSE;
15299 + char name[SB_DEVPATH_BUFSZ+16], *value;
15300 + char devpath[SB_DEVPATH_BUFSZ];
15301 + int err;
15302 +
15303 + /*
15304 + * Apply CRC over SROM content regardless SROM is present or not,
15305 + * and use variable <devpath>sromrev's existance in flash to decide
15306 + * if we should return an error when CRC fails or read SROM variables
15307 + * from flash.
15308 + */
15309 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
15310 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15311 + return err;
15312 + sprintf(name, "%ssromrev", devpath);
15313 + if (!(value = getvar(NULL, name)))
15314 + return (-1);
15315 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
15316 + flash = TRUE;
15317 + }
15318 + /* srom is good */
15319 + else {
15320 + /* top word of sprom contains version and crc8 */
15321 + sromrev = b[63] & 0xff;
15322 + /* bcm4401 sroms misprogrammed */
15323 + if (sromrev == 0x10)
15324 + sromrev = 1;
15325 + }
15326 +
15327 + /* srom version check */
15328 + if (sromrev > 3)
15329 + return (-2);
15330 +
15331 + ASSERT(vars);
15332 + ASSERT(count);
15333 +
15334 + base = vp = MALLOC(osh, VARS_MAX);
15335 + ASSERT(vp);
15336 + if (!vp)
15337 + return -2;
15338 +
15339 + /* read variables from flash */
15340 + if (flash) {
15341 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15342 + goto err;
15343 + goto done;
15344 + }
15345 +
15346 + vp += sprintf(vp, "sromrev=%d", sromrev);
15347 + vp++;
15348 +
15349 + if (sromrev >= 3) {
15350 + /* New section takes over the 3th hardware function space */
15351 +
15352 + /* Words 22+23 are 11a (mid) ofdm power offsets */
15353 + w32 = ((uint32)b[23] << 16) | b[22];
15354 + vp += sprintf(vp, "ofdmapo=%d", w32);
15355 + vp++;
15356 +
15357 + /* Words 24+25 are 11a (low) ofdm power offsets */
15358 + w32 = ((uint32)b[25] << 16) | b[24];
15359 + vp += sprintf(vp, "ofdmalpo=%d", w32);
15360 + vp++;
15361 +
15362 + /* Words 26+27 are 11a (high) ofdm power offsets */
15363 + w32 = ((uint32)b[27] << 16) | b[26];
15364 + vp += sprintf(vp, "ofdmahpo=%d", w32);
15365 + vp++;
15366 +
15367 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15368 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
15369 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15370 +
15371 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15372 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
15373 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
15374 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15375 +
15376 + vp++;
15377 + }
15378 +
15379 + if (sromrev >= 2) {
15380 + /* New section takes over the 4th hardware function space */
15381 +
15382 + /* Word 29 is max power 11a high/low */
15383 + w = b[29];
15384 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
15385 + vp++;
15386 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
15387 + vp++;
15388 +
15389 + /* Words 30-32 set the 11alow pa settings,
15390 + * 33-35 are the 11ahigh ones.
15391 + */
15392 + for (i = 0; i < 3; i++) {
15393 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
15394 + vp++;
15395 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
15396 + vp++;
15397 + }
15398 + w = b[59];
15399 + if (w == 0)
15400 + vp += sprintf(vp, "ccode=");
15401 + else
15402 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
15403 + vp++;
15404 +
15405 + }
15406 +
15407 + /* parameter section of sprom starts at byte offset 72 */
15408 + woff = 72/2;
15409 +
15410 + /* first 6 bytes are il0macaddr */
15411 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15412 + ea.octet[1] = b[woff] & 0xff;
15413 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15414 + ea.octet[3] = b[woff+1] & 0xff;
15415 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15416 + ea.octet[5] = b[woff+2] & 0xff;
15417 + woff += ETHER_ADDR_LEN/2 ;
15418 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15419 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15420 + vp++;
15421 +
15422 + /* next 6 bytes are et0macaddr */
15423 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15424 + ea.octet[1] = b[woff] & 0xff;
15425 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15426 + ea.octet[3] = b[woff+1] & 0xff;
15427 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15428 + ea.octet[5] = b[woff+2] & 0xff;
15429 + woff += ETHER_ADDR_LEN/2 ;
15430 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15431 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
15432 + vp++;
15433 +
15434 + /* next 6 bytes are et1macaddr */
15435 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15436 + ea.octet[1] = b[woff] & 0xff;
15437 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15438 + ea.octet[3] = b[woff+1] & 0xff;
15439 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15440 + ea.octet[5] = b[woff+2] & 0xff;
15441 + woff += ETHER_ADDR_LEN/2 ;
15442 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15443 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
15444 + vp++;
15445 +
15446 + /*
15447 + * Enet phy settings one or two singles or a dual
15448 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
15449 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
15450 + * Bit 14 : Mdio for enet0
15451 + * Bit 15 : Mdio for enet1
15452 + */
15453 + w = b[woff];
15454 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
15455 + vp++;
15456 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
15457 + vp++;
15458 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
15459 + vp++;
15460 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
15461 + vp++;
15462 +
15463 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
15464 + w = b[46];
15465 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
15466 + vp++;
15467 +
15468 + if (sromrev > 1)
15469 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
15470 + else
15471 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
15472 + vp++;
15473 +
15474 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
15475 + vp++;
15476 +
15477 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
15478 + vp++;
15479 +
15480 + /* Words 47-49 set the (wl) pa settings */
15481 + woff = 47;
15482 +
15483 + for (i = 0; i < 3; i++) {
15484 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
15485 + vp++;
15486 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
15487 + vp++;
15488 + }
15489 +
15490 + /*
15491 + * Words 50-51 set the customer-configured wl led behavior.
15492 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
15493 + * LED behavior values defined in wlioctl.h .
15494 + */
15495 + w = b[50];
15496 + if ((w != 0) && (w != 0xffff)) {
15497 + /* gpio0 */
15498 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
15499 + vp++;
15500 +
15501 + /* gpio1 */
15502 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
15503 + vp++;
15504 + }
15505 + w = b[51];
15506 + if ((w != 0) && (w != 0xffff)) {
15507 + /* gpio2 */
15508 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
15509 + vp++;
15510 +
15511 + /* gpio3 */
15512 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
15513 + vp++;
15514 + }
15515 +
15516 + /* Word 52 is max power 0/1 */
15517 + w = b[52];
15518 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
15519 + vp++;
15520 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
15521 + vp++;
15522 +
15523 + /* Word 56 is idle tssi target 0/1 */
15524 + w = b[56];
15525 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
15526 + vp++;
15527 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
15528 + vp++;
15529 +
15530 + /* Word 57 is boardflags, if not programmed make it zero */
15531 + w32 = (uint32)b[57];
15532 + if (w32 == 0xffff) w32 = 0;
15533 + if (sromrev > 1) {
15534 + /* Word 28 is the high bits of boardflags */
15535 + w32 |= (uint32)b[28] << 16;
15536 + }
15537 + vp += sprintf(vp, "boardflags=%d", w32);
15538 + vp++;
15539 +
15540 + /* Word 58 is antenna gain 0/1 */
15541 + w = b[58];
15542 + vp += sprintf(vp, "ag0=%d", w & 0xff);
15543 + vp++;
15544 +
15545 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
15546 + vp++;
15547 +
15548 + if (sromrev == 1) {
15549 + /* set the oem string */
15550 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15551 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
15552 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
15553 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
15554 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
15555 + vp++;
15556 + } else if (sromrev == 2) {
15557 + /* Word 60 OFDM tx power offset from CCK level */
15558 + /* OFDM Power Offset - opo */
15559 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
15560 + vp++;
15561 + } else {
15562 + /* Word 60: cck power offsets */
15563 + vp += sprintf(vp, "cckpo=%d", b[60]);
15564 + vp++;
15565 +
15566 + /* Words 61+62: 11g ofdm power offsets */
15567 + w32 = ((uint32)b[62] << 16) | b[61];
15568 + vp += sprintf(vp, "ofdmgpo=%d", w32);
15569 + vp++;
15570 + }
15571 +
15572 + /* final nullbyte terminator */
15573 + *vp++ = '\0';
15574 +
15575 + ASSERT((vp - base) <= VARS_MAX);
15576 +
15577 +done: err = initvars_table(osh, base, vp, vars, count);
15578 +
15579 +err: MFREE(osh, base, VARS_MAX);
15580 + return err;
15581 +}
15582 +
15583 +/*
15584 + * Read the cis and call parsecis to initialize the vars.
15585 + * Return 0 on success, nonzero on error.
15586 + */
15587 +static int
15588 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
15589 +{
15590 + uint8 *cis = NULL;
15591 + int rc;
15592 + uint data_sz;
15593 +
15594 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
15595 +
15596 + if ((cis = MALLOC(osh, data_sz)) == NULL)
15597 + return (-2);
15598 +
15599 + if (sb_pcmciarev(sbh) == 1) {
15600 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
15601 + MFREE(osh, cis, data_sz);
15602 + return (-1);
15603 + }
15604 + /* fix up endianess for 16-bit data vs 8-bit parsing */
15605 + ltoh16_buf((uint16 *)cis, data_sz);
15606 + } else
15607 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
15608 +
15609 + rc = srom_parsecis(osh, cis, vars, count);
15610 +
15611 + MFREE(osh, cis, data_sz);
15612 +
15613 + return (rc);
15614 +}
15615 +
15616 diff -Nur linux-2.4.32/drivers/net/hnd/bcmutils.c linux-2.4.32-brcm/drivers/net/hnd/bcmutils.c
15617 --- linux-2.4.32/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
15618 +++ linux-2.4.32-brcm/drivers/net/hnd/bcmutils.c 2005-12-16 23:39:11.288858250 +0100
15619 @@ -0,0 +1,1081 @@
15620 +/*
15621 + * Misc useful OS-independent routines.
15622 + *
15623 + * Copyright 2005, Broadcom Corporation
15624 + * All Rights Reserved.
15625 + *
15626 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15627 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15628 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15629 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15630 + * $Id$
15631 + */
15632 +
15633 +#include <typedefs.h>
15634 +#ifdef BCMDRIVER
15635 +#include <osl.h>
15636 +#include <sbutils.h>
15637 +#include <bcmnvram.h>
15638 +#else
15639 +#include <stdio.h>
15640 +#include <string.h>
15641 +#endif
15642 +#include <bcmutils.h>
15643 +#include <bcmendian.h>
15644 +#include <bcmdevs.h>
15645 +
15646 +#ifdef BCMDRIVER
15647 +/* copy a pkt buffer chain into a buffer */
15648 +uint
15649 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
15650 +{
15651 + uint n, ret = 0;
15652 +
15653 + if (len < 0)
15654 + len = 4096; /* "infinite" */
15655 +
15656 + /* skip 'offset' bytes */
15657 + for (; p && offset; p = PKTNEXT(osh, p)) {
15658 + if (offset < (uint)PKTLEN(osh, p))
15659 + break;
15660 + offset -= PKTLEN(osh, p);
15661 + }
15662 +
15663 + if (!p)
15664 + return 0;
15665 +
15666 + /* copy the data */
15667 + for (; p && len; p = PKTNEXT(osh, p)) {
15668 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
15669 + bcopy(PKTDATA(osh, p) + offset, buf, n);
15670 + buf += n;
15671 + len -= n;
15672 + ret += n;
15673 + offset = 0;
15674 + }
15675 +
15676 + return ret;
15677 +}
15678 +
15679 +/* return total length of buffer chain */
15680 +uint
15681 +pkttotlen(osl_t *osh, void *p)
15682 +{
15683 + uint total;
15684 +
15685 + total = 0;
15686 + for (; p; p = PKTNEXT(osh, p))
15687 + total += PKTLEN(osh, p);
15688 + return (total);
15689 +}
15690 +
15691 +void
15692 +pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
15693 +{
15694 + q->head = q->tail = NULL;
15695 + q->maxlen = maxlen;
15696 + q->len = 0;
15697 + if (prio_map) {
15698 + q->priority = TRUE;
15699 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
15700 + }
15701 + else
15702 + q->priority = FALSE;
15703 +}
15704 +
15705 +/* should always check pktq_full before calling pktenq */
15706 +void
15707 +pktenq(struct pktq *q, void *p, bool lifo)
15708 +{
15709 + void *next, *prev;
15710 +
15711 + /* allow 10 pkts slack */
15712 + ASSERT(q->len < (q->maxlen + 10));
15713 +
15714 + /* Queueing chains not allowed */
15715 + ASSERT(PKTLINK(p) == NULL);
15716 +
15717 + /* Queue is empty */
15718 + if (q->tail == NULL) {
15719 + ASSERT(q->head == NULL);
15720 + q->head = q->tail = p;
15721 + }
15722 +
15723 + /* Insert at head or tail */
15724 + else if (q->priority == FALSE) {
15725 + /* Insert at head (LIFO) */
15726 + if (lifo) {
15727 + PKTSETLINK(p, q->head);
15728 + q->head = p;
15729 + }
15730 + /* Insert at tail (FIFO) */
15731 + else {
15732 + ASSERT(PKTLINK(q->tail) == NULL);
15733 + PKTSETLINK(q->tail, p);
15734 + PKTSETLINK(p, NULL);
15735 + q->tail = p;
15736 + }
15737 + }
15738 +
15739 + /* Insert by priority */
15740 + else {
15741 + /* legal priorities 0-7 */
15742 + ASSERT(PKTPRIO(p) <= MAXPRIO);
15743 +
15744 + ASSERT(q->head);
15745 + ASSERT(q->tail);
15746 + /* Shortcut to insertion at tail */
15747 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
15748 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
15749 + prev = q->tail;
15750 + next = NULL;
15751 + }
15752 + /* Insert at head or in the middle */
15753 + else {
15754 + prev = NULL;
15755 + next = q->head;
15756 + }
15757 + /* Walk the queue */
15758 + for (; next; prev = next, next = PKTLINK(next)) {
15759 + /* Priority queue invariant */
15760 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
15761 + /* Insert at head of string of packets of same priority (LIFO) */
15762 + if (lifo) {
15763 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
15764 + break;
15765 + }
15766 + /* Insert at tail of string of packets of same priority (FIFO) */
15767 + else {
15768 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
15769 + break;
15770 + }
15771 + }
15772 + /* Insert at tail */
15773 + if (next == NULL) {
15774 + ASSERT(PKTLINK(q->tail) == NULL);
15775 + PKTSETLINK(q->tail, p);
15776 + PKTSETLINK(p, NULL);
15777 + q->tail = p;
15778 + }
15779 + /* Insert in the middle */
15780 + else if (prev) {
15781 + PKTSETLINK(prev, p);
15782 + PKTSETLINK(p, next);
15783 + }
15784 + /* Insert at head */
15785 + else {
15786 + PKTSETLINK(p, q->head);
15787 + q->head = p;
15788 + }
15789 + }
15790 +
15791 + /* List invariants after insertion */
15792 + ASSERT(q->head);
15793 + ASSERT(PKTLINK(q->tail) == NULL);
15794 +
15795 + q->len++;
15796 +}
15797 +
15798 +/* dequeue packet at head */
15799 +void*
15800 +pktdeq(struct pktq *q)
15801 +{
15802 + void *p;
15803 +
15804 + if ((p = q->head)) {
15805 + ASSERT(q->tail);
15806 + q->head = PKTLINK(p);
15807 + PKTSETLINK(p, NULL);
15808 + q->len--;
15809 + if (q->head == NULL)
15810 + q->tail = NULL;
15811 + }
15812 + else {
15813 + ASSERT(q->tail == NULL);
15814 + }
15815 +
15816 + return (p);
15817 +}
15818 +
15819 +/* dequeue packet at tail */
15820 +void*
15821 +pktdeqtail(struct pktq *q)
15822 +{
15823 + void *p;
15824 + void *next, *prev;
15825 +
15826 + if (q->head == q->tail) { /* last packet on queue or queue empty */
15827 + p = q->head;
15828 + q->head = q->tail = NULL;
15829 + q->len = 0;
15830 + return(p);
15831 + }
15832 +
15833 + /* start walk at head */
15834 + prev = NULL;
15835 + next = q->head;
15836 +
15837 + /* Walk the queue to find prev of q->tail */
15838 + for (; next; prev = next, next = PKTLINK(next)) {
15839 + if (next == q->tail)
15840 + break;
15841 + }
15842 +
15843 + ASSERT(prev);
15844 +
15845 + PKTSETLINK(prev, NULL);
15846 + q->tail = prev;
15847 + q->len--;
15848 + p = next;
15849 +
15850 + return (p);
15851 +}
15852 +
15853 +unsigned char bcm_ctype[] = {
15854 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
15855 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
15856 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
15857 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
15858 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
15859 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
15860 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
15861 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
15862 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
15863 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
15864 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
15865 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
15866 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
15867 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
15868 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
15869 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
15870 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
15871 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
15872 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
15873 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
15874 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
15875 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
15876 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
15877 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
15878 +};
15879 +
15880 +uchar
15881 +bcm_toupper(uchar c)
15882 +{
15883 + if (bcm_islower(c))
15884 + c -= 'a'-'A';
15885 + return (c);
15886 +}
15887 +
15888 +ulong
15889 +bcm_strtoul(char *cp, char **endp, uint base)
15890 +{
15891 + ulong result, value;
15892 + bool minus;
15893 +
15894 + minus = FALSE;
15895 +
15896 + while (bcm_isspace(*cp))
15897 + cp++;
15898 +
15899 + if (cp[0] == '+')
15900 + cp++;
15901 + else if (cp[0] == '-') {
15902 + minus = TRUE;
15903 + cp++;
15904 + }
15905 +
15906 + if (base == 0) {
15907 + if (cp[0] == '0') {
15908 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
15909 + base = 16;
15910 + cp = &cp[2];
15911 + } else {
15912 + base = 8;
15913 + cp = &cp[1];
15914 + }
15915 + } else
15916 + base = 10;
15917 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
15918 + cp = &cp[2];
15919 + }
15920 +
15921 + result = 0;
15922 +
15923 + while (bcm_isxdigit(*cp) &&
15924 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
15925 + result = result*base + value;
15926 + cp++;
15927 + }
15928 +
15929 + if (minus)
15930 + result = (ulong)(result * -1);
15931 +
15932 + if (endp)
15933 + *endp = (char *)cp;
15934 +
15935 + return (result);
15936 +}
15937 +
15938 +uint
15939 +bcm_atoi(char *s)
15940 +{
15941 + uint n;
15942 +
15943 + n = 0;
15944 +
15945 + while (bcm_isdigit(*s))
15946 + n = (n * 10) + *s++ - '0';
15947 + return (n);
15948 +}
15949 +
15950 +/* return pointer to location of substring 'needle' in 'haystack' */
15951 +char*
15952 +bcmstrstr(char *haystack, char *needle)
15953 +{
15954 + int len, nlen;
15955 + int i;
15956 +
15957 + if ((haystack == NULL) || (needle == NULL))
15958 + return (haystack);
15959 +
15960 + nlen = strlen(needle);
15961 + len = strlen(haystack) - nlen + 1;
15962 +
15963 + for (i = 0; i < len; i++)
15964 + if (bcmp(needle, &haystack[i], nlen) == 0)
15965 + return (&haystack[i]);
15966 + return (NULL);
15967 +}
15968 +
15969 +char*
15970 +bcmstrcat(char *dest, const char *src)
15971 +{
15972 + strcpy(&dest[strlen(dest)], src);
15973 + return (dest);
15974 +}
15975 +
15976 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
15977 +/* registry routine buffer preparation utility functions:
15978 + * parameter order is like strncpy, but returns count
15979 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
15980 + */
15981 +ulong
15982 +wchar2ascii(
15983 + char *abuf,
15984 + ushort *wbuf,
15985 + ushort wbuflen,
15986 + ulong abuflen
15987 +)
15988 +{
15989 + ulong copyct = 1;
15990 + ushort i;
15991 +
15992 + if (abuflen == 0)
15993 + return 0;
15994 +
15995 + /* wbuflen is in bytes */
15996 + wbuflen /= sizeof(ushort);
15997 +
15998 + for (i = 0; i < wbuflen; ++i) {
15999 + if (--abuflen == 0)
16000 + break;
16001 + *abuf++ = (char) *wbuf++;
16002 + ++copyct;
16003 + }
16004 + *abuf = '\0';
16005 +
16006 + return copyct;
16007 +}
16008 +#endif
16009 +
16010 +char*
16011 +bcm_ether_ntoa(char *ea, char *buf)
16012 +{
16013 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
16014 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
16015 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
16016 + return (buf);
16017 +}
16018 +
16019 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
16020 +int
16021 +bcm_ether_atoe(char *p, char *ea)
16022 +{
16023 + int i = 0;
16024 +
16025 + for (;;) {
16026 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
16027 + if (!*p++ || i == 6)
16028 + break;
16029 + }
16030 +
16031 + return (i == 6);
16032 +}
16033 +
16034 +void
16035 +bcm_mdelay(uint ms)
16036 +{
16037 + uint i;
16038 +
16039 + for (i = 0; i < ms; i++) {
16040 + OSL_DELAY(1000);
16041 + }
16042 +}
16043 +
16044 +/*
16045 + * Search the name=value vars for a specific one and return its value.
16046 + * Returns NULL if not found.
16047 + */
16048 +char*
16049 +getvar(char *vars, char *name)
16050 +{
16051 + char *s;
16052 + int len;
16053 +
16054 + len = strlen(name);
16055 +
16056 + /* first look in vars[] */
16057 + for (s = vars; s && *s; ) {
16058 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
16059 + return (&s[len+1]);
16060 +
16061 + while (*s++)
16062 + ;
16063 + }
16064 +
16065 + /* then query nvram */
16066 + return (BCMINIT(nvram_get)(name));
16067 +}
16068 +
16069 +/*
16070 + * Search the vars for a specific one and return its value as
16071 + * an integer. Returns 0 if not found.
16072 + */
16073 +int
16074 +getintvar(char *vars, char *name)
16075 +{
16076 + char *val;
16077 +
16078 + if ((val = getvar(vars, name)) == NULL)
16079 + return (0);
16080 +
16081 + return (bcm_strtoul(val, NULL, 0));
16082 +}
16083 +
16084 +
16085 +/* Search for token in comma separated token-string */
16086 +static int
16087 +findmatch(char *string, char *name)
16088 +{
16089 + uint len;
16090 + char *c;
16091 +
16092 + len = strlen(name);
16093 + while ((c = strchr(string, ',')) != NULL) {
16094 + if (len == (uint)(c - string) && !strncmp(string, name, len))
16095 + return 1;
16096 + string = c + 1;
16097 + }
16098 +
16099 + return (!strcmp(string, name));
16100 +}
16101 +
16102 +/* Return gpio pin number assigned to the named pin */
16103 +/*
16104 +* Variable should be in format:
16105 +*
16106 +* gpio<N>=pin_name,pin_name
16107 +*
16108 +* This format allows multiple features to share the gpio with mutual
16109 +* understanding.
16110 +*
16111 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
16112 +* and if def_pin is not used by others.
16113 +*/
16114 +uint
16115 +getgpiopin(char *vars, char *pin_name, uint def_pin)
16116 +{
16117 + char name[] = "gpioXXXX";
16118 + char *val;
16119 + uint pin;
16120 +
16121 + /* Go thru all possibilities till a match in pin name */
16122 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
16123 + sprintf(name, "gpio%d", pin);
16124 + val = getvar(vars, name);
16125 + if (val && findmatch(val, pin_name))
16126 + return pin;
16127 + }
16128 +
16129 + if (def_pin != GPIO_PIN_NOTDEFINED) {
16130 + /* make sure the default pin is not used by someone else */
16131 + sprintf(name, "gpio%d", def_pin);
16132 + if (getvar(vars, name)) {
16133 + def_pin = GPIO_PIN_NOTDEFINED;
16134 + }
16135 + }
16136 +
16137 + return def_pin;
16138 +}
16139 +
16140 +
16141 +static char bcm_undeferrstr[BCME_STRLEN];
16142 +
16143 +static const char *bcmerrorstrtable[] = \
16144 +{ "OK", /* 0 */
16145 + "Undefined error", /* BCME_ERROR */
16146 + "Bad Argument", /* BCME_BADARG*/
16147 + "Bad Option", /* BCME_BADOPTION*/
16148 + "Not up", /* BCME_NOTUP */
16149 + "Not down", /* BCME_NOTDOWN */
16150 + "Not AP", /* BCME_NOTAP */
16151 + "Not STA", /* BCME_NOTSTA */
16152 + "Bad Key Index", /* BCME_BADKEYIDX */
16153 + "Radio Off", /* BCME_RADIOOFF */
16154 + "Not band locked", /* BCME_NOTBANDLOCKED */
16155 + "No clock", /* BCME_NOCLK */
16156 + "Bad Rate valueset", /* BCME_BADRATESET */
16157 + "Bad Band", /* BCME_BADBAND */
16158 + "Buffer too short", /* BCME_BUFTOOSHORT */
16159 + "Buffer too length", /* BCME_BUFTOOLONG */
16160 + "Busy", /* BCME_BUSY */
16161 + "Not Associated", /* BCME_NOTASSOCIATED */
16162 + "Bad SSID len", /* BCME_BADSSIDLEN */
16163 + "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
16164 + "Bad Channel", /* BCME_BADCHAN */
16165 + "Bad Address", /* BCME_BADADDR */
16166 + "Not Enough Resources", /* BCME_NORESOURCE */
16167 + "Unsupported", /* BCME_UNSUPPORTED */
16168 + "Bad length", /* BCME_BADLENGTH */
16169 + "Not Ready", /* BCME_NOTREADY */
16170 + "Not Permitted", /* BCME_EPERM */
16171 + "No Memory", /* BCME_NOMEM */
16172 + "Associated", /* BCME_ASSOCIATED */
16173 + "Not In Range", /* BCME_RANGE */
16174 + "Not Found" /* BCME_NOTFOUND */
16175 + };
16176 +
16177 +/* Convert the Error codes into related Error strings */
16178 +const char *
16179 +bcmerrorstr(int bcmerror)
16180 +{
16181 + int abs_bcmerror;
16182 +
16183 + abs_bcmerror = ABS(bcmerror);
16184 +
16185 + /* check if someone added a bcmerror code but forgot to add errorstring */
16186 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
16187 + if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
16188 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
16189 + return bcm_undeferrstr;
16190 + }
16191 +
16192 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
16193 +
16194 + return bcmerrorstrtable[abs_bcmerror];
16195 +}
16196 +#endif /* #ifdef BCMDRIVER */
16197 +
16198 +
16199 +/*******************************************************************************
16200 + * crc8
16201 + *
16202 + * Computes a crc8 over the input data using the polynomial:
16203 + *
16204 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
16205 + *
16206 + * The caller provides the initial value (either CRC8_INIT_VALUE
16207 + * or the previous returned value) to allow for processing of
16208 + * discontiguous blocks of data. When generating the CRC the
16209 + * caller is responsible for complementing the final return value
16210 + * and inserting it into the byte stream. When checking, a final
16211 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
16212 + *
16213 + * Reference: Dallas Semiconductor Application Note 27
16214 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16215 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16216 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16217 + *
16218 + ******************************************************************************/
16219 +
16220 +static uint8 crc8_table[256] = {
16221 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
16222 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
16223 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
16224 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
16225 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
16226 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
16227 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
16228 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
16229 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
16230 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
16231 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
16232 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
16233 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
16234 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
16235 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
16236 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
16237 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
16238 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
16239 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
16240 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
16241 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
16242 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
16243 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
16244 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
16245 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
16246 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
16247 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
16248 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
16249 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
16250 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
16251 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
16252 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
16253 +};
16254 +
16255 +#define CRC_INNER_LOOP(n, c, x) \
16256 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
16257 +
16258 +uint8
16259 +hndcrc8(
16260 + uint8 *pdata, /* pointer to array of data to process */
16261 + uint nbytes, /* number of input data bytes to process */
16262 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
16263 +)
16264 +{
16265 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
16266 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
16267 + while (nbytes-- > 0)
16268 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
16269 +
16270 + return crc;
16271 +}
16272 +
16273 +/*******************************************************************************
16274 + * crc16
16275 + *
16276 + * Computes a crc16 over the input data using the polynomial:
16277 + *
16278 + * x^16 + x^12 +x^5 + 1
16279 + *
16280 + * The caller provides the initial value (either CRC16_INIT_VALUE
16281 + * or the previous returned value) to allow for processing of
16282 + * discontiguous blocks of data. When generating the CRC the
16283 + * caller is responsible for complementing the final return value
16284 + * and inserting it into the byte stream. When checking, a final
16285 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
16286 + *
16287 + * Reference: Dallas Semiconductor Application Note 27
16288 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16289 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16290 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16291 + *
16292 + ******************************************************************************/
16293 +
16294 +static uint16 crc16_table[256] = {
16295 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
16296 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
16297 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
16298 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
16299 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
16300 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
16301 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
16302 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
16303 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
16304 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
16305 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
16306 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
16307 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
16308 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
16309 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
16310 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
16311 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
16312 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
16313 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
16314 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
16315 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
16316 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
16317 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
16318 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
16319 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
16320 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
16321 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
16322 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
16323 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
16324 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
16325 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
16326 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
16327 +};
16328 +
16329 +uint16
16330 +hndcrc16(
16331 + uint8 *pdata, /* pointer to array of data to process */
16332 + uint nbytes, /* number of input data bytes to process */
16333 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
16334 +)
16335 +{
16336 + while (nbytes-- > 0)
16337 + CRC_INNER_LOOP(16, crc, *pdata++);
16338 + return crc;
16339 +}
16340 +
16341 +static uint32 crc32_table[256] = {
16342 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
16343 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
16344 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
16345 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
16346 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
16347 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
16348 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
16349 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
16350 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
16351 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
16352 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
16353 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
16354 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
16355 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
16356 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
16357 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
16358 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
16359 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
16360 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
16361 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
16362 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
16363 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
16364 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
16365 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
16366 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
16367 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
16368 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
16369 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
16370 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
16371 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
16372 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
16373 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
16374 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
16375 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
16376 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
16377 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
16378 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
16379 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
16380 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
16381 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
16382 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
16383 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
16384 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
16385 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
16386 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
16387 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
16388 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
16389 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
16390 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
16391 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
16392 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
16393 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
16394 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
16395 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
16396 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
16397 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
16398 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
16399 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
16400 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
16401 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
16402 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
16403 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
16404 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
16405 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
16406 +};
16407 +
16408 +uint32
16409 +hndcrc32(
16410 + uint8 *pdata, /* pointer to array of data to process */
16411 + uint nbytes, /* number of input data bytes to process */
16412 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
16413 +)
16414 +{
16415 + uint8 *pend;
16416 +#ifdef __mips__
16417 + uint8 tmp[4];
16418 + ulong *tptr = (ulong *)tmp;
16419 +
16420 + /* in case the beginning of the buffer isn't aligned */
16421 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
16422 + nbytes -= (pend - pdata);
16423 + while (pdata < pend)
16424 + CRC_INNER_LOOP(32, crc, *pdata++);
16425 +
16426 + /* handle bulk of data as 32-bit words */
16427 + pend = pdata + (nbytes & 0xfffffffc);
16428 + while (pdata < pend) {
16429 + tptr = *((ulong *) pdata);
16430 + *((ulong *) pdata) += 1;
16431 + CRC_INNER_LOOP(32, crc, tmp[0]);
16432 + CRC_INNER_LOOP(32, crc, tmp[1]);
16433 + CRC_INNER_LOOP(32, crc, tmp[2]);
16434 + CRC_INNER_LOOP(32, crc, tmp[3]);
16435 + }
16436 +
16437 + /* 1-3 bytes at end of buffer */
16438 + pend = pdata + (nbytes & 0x03);
16439 + while (pdata < pend)
16440 + CRC_INNER_LOOP(32, crc, *pdata++);
16441 +#else
16442 + pend = pdata + nbytes;
16443 + while (pdata < pend)
16444 + CRC_INNER_LOOP(32, crc, *pdata++);
16445 +#endif
16446 +
16447 + return crc;
16448 +}
16449 +
16450 +#ifdef notdef
16451 +#define CLEN 1499
16452 +#define CBUFSIZ (CLEN+4)
16453 +#define CNBUFS 5
16454 +
16455 +void testcrc32(void)
16456 +{
16457 + uint j,k,l;
16458 + uint8 *buf;
16459 + uint len[CNBUFS];
16460 + uint32 crcr;
16461 + uint32 crc32tv[CNBUFS] =
16462 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
16463 +
16464 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
16465 +
16466 + /* step through all possible alignments */
16467 + for (l=0;l<=4;l++) {
16468 + for (j=0; j<CNBUFS; j++) {
16469 + len[j] = CLEN;
16470 + for (k=0; k<len[j]; k++)
16471 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
16472 + }
16473 +
16474 + for (j=0; j<CNBUFS; j++) {
16475 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
16476 + ASSERT(crcr == crc32tv[j]);
16477 + }
16478 + }
16479 +
16480 + MFREE(buf, CBUFSIZ*CNBUFS);
16481 + return;
16482 +}
16483 +#endif
16484 +
16485 +
16486 +/*
16487 + * Advance from the current 1-byte tag/1-byte length/variable-length value
16488 + * triple, to the next, returning a pointer to the next.
16489 + * If the current or next TLV is invalid (does not fit in given buffer length),
16490 + * NULL is returned.
16491 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
16492 + * by the TLV paramter's length if it is valid.
16493 + */
16494 +bcm_tlv_t *
16495 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
16496 +{
16497 + int len;
16498 +
16499 + /* validate current elt */
16500 + if (!bcm_valid_tlv(elt, *buflen))
16501 + return NULL;
16502 +
16503 + /* advance to next elt */
16504 + len = elt->len;
16505 + elt = (bcm_tlv_t*)(elt->data + len);
16506 + *buflen -= (2 + len);
16507 +
16508 + /* validate next elt */
16509 + if (!bcm_valid_tlv(elt, *buflen))
16510 + return NULL;
16511 +
16512 + return elt;
16513 +}
16514 +
16515 +/*
16516 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16517 + * triples, returning a pointer to the substring whose first element
16518 + * matches tag
16519 + */
16520 +bcm_tlv_t *
16521 +bcm_parse_tlvs(void *buf, int buflen, uint key)
16522 +{
16523 + bcm_tlv_t *elt;
16524 + int totlen;
16525 +
16526 + elt = (bcm_tlv_t*)buf;
16527 + totlen = buflen;
16528 +
16529 + /* find tagged parameter */
16530 + while (totlen >= 2) {
16531 + int len = elt->len;
16532 +
16533 + /* validate remaining totlen */
16534 + if ((elt->id == key) && (totlen >= (len + 2)))
16535 + return (elt);
16536 +
16537 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16538 + totlen -= (len + 2);
16539 + }
16540 +
16541 + return NULL;
16542 +}
16543 +
16544 +/*
16545 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16546 + * triples, returning a pointer to the substring whose first element
16547 + * matches tag. Stop parsing when we see an element whose ID is greater
16548 + * than the target key.
16549 + */
16550 +bcm_tlv_t *
16551 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
16552 +{
16553 + bcm_tlv_t *elt;
16554 + int totlen;
16555 +
16556 + elt = (bcm_tlv_t*)buf;
16557 + totlen = buflen;
16558 +
16559 + /* find tagged parameter */
16560 + while (totlen >= 2) {
16561 + uint id = elt->id;
16562 + int len = elt->len;
16563 +
16564 + /* Punt if we start seeing IDs > than target key */
16565 + if (id > key)
16566 + return(NULL);
16567 +
16568 + /* validate remaining totlen */
16569 + if ((id == key) && (totlen >= (len + 2)))
16570 + return (elt);
16571 +
16572 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16573 + totlen -= (len + 2);
16574 + }
16575 + return NULL;
16576 +}
16577 +/* routine to dump fields in a fileddesc structure */
16578 +
16579 +uint
16580 +bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
16581 +{
16582 + uint filled_len;
16583 + uint len;
16584 + struct fielddesc *cur_ptr;
16585 +
16586 + filled_len = 0;
16587 + cur_ptr = fielddesc_array;
16588 +
16589 + while (bufsize > (filled_len + 64)) {
16590 + if (cur_ptr->nameandfmt == NULL)
16591 + break;
16592 + len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
16593 + buf += len;
16594 + filled_len += len;
16595 + cur_ptr++;
16596 + }
16597 + return filled_len;
16598 +}
16599 +
16600 +uint
16601 +bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
16602 +{
16603 + uint len;
16604 +
16605 + len = strlen(name) + 1;
16606 +
16607 + if ((len + datalen) > buflen)
16608 + return 0;
16609 +
16610 + strcpy(buf, name);
16611 +
16612 + /* append data onto the end of the name string */
16613 + memcpy(&buf[len], data, datalen);
16614 + len += datalen;
16615 +
16616 + return len;
16617 +}
16618 +
16619 +/* Quarter dBm units to mW
16620 + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
16621 + * Table is offset so the last entry is largest mW value that fits in
16622 + * a uint16.
16623 + */
16624 +
16625 +#define QDBM_OFFSET 153
16626 +#define QDBM_TABLE_LEN 40
16627 +
16628 +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
16629 + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
16630 + */
16631 +#define QDBM_TABLE_LOW_BOUND 6493
16632 +
16633 +/* Largest mW value that will round down to the last table entry,
16634 + * QDBM_OFFSET + QDBM_TABLE_LEN-1.
16635 + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
16636 + */
16637 +#define QDBM_TABLE_HIGH_BOUND 64938
16638 +
16639 +static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
16640 +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
16641 +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
16642 +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
16643 +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
16644 +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
16645 +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
16646 +};
16647 +
16648 +uint16
16649 +bcm_qdbm_to_mw(uint8 qdbm)
16650 +{
16651 + uint factor = 1;
16652 + int idx = qdbm - QDBM_OFFSET;
16653 +
16654 + if (idx > QDBM_TABLE_LEN) {
16655 + /* clamp to max uint16 mW value */
16656 + return 0xFFFF;
16657 + }
16658 +
16659 + /* scale the qdBm index up to the range of the table 0-40
16660 + * where an offset of 40 qdBm equals a factor of 10 mW.
16661 + */
16662 + while (idx < 0) {
16663 + idx += 40;
16664 + factor *= 10;
16665 + }
16666 +
16667 + /* return the mW value scaled down to the correct factor of 10,
16668 + * adding in factor/2 to get proper rounding. */
16669 + return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
16670 +}
16671 +
16672 +uint8
16673 +bcm_mw_to_qdbm(uint16 mw)
16674 +{
16675 + uint8 qdbm;
16676 + int offset;
16677 + uint mw_uint = mw;
16678 + uint boundary;
16679 +
16680 + /* handle boundary case */
16681 + if (mw_uint <= 1)
16682 + return 0;
16683 +
16684 + offset = QDBM_OFFSET;
16685 +
16686 + /* move mw into the range of the table */
16687 + while (mw_uint < QDBM_TABLE_LOW_BOUND) {
16688 + mw_uint *= 10;
16689 + offset -= 40;
16690 + }
16691 +
16692 + for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
16693 + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
16694 + if (mw_uint < boundary) break;
16695 + }
16696 +
16697 + qdbm += (uint8)offset;
16698 +
16699 + return(qdbm);
16700 +}
16701 diff -Nur linux-2.4.32/drivers/net/hnd/hnddma.c linux-2.4.32-brcm/drivers/net/hnd/hnddma.c
16702 --- linux-2.4.32/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
16703 +++ linux-2.4.32-brcm/drivers/net/hnd/hnddma.c 2005-12-16 23:39:11.288858250 +0100
16704 @@ -0,0 +1,1527 @@
16705 +/*
16706 + * Generic Broadcom Home Networking Division (HND) DMA module.
16707 + * This supports the following chips: BCM42xx, 44xx, 47xx .
16708 + *
16709 + * Copyright 2005, Broadcom Corporation
16710 + * All Rights Reserved.
16711 + *
16712 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16713 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16714 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16715 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16716 + *
16717 + * $Id$
16718 + */
16719 +
16720 +#include <typedefs.h>
16721 +#include <osl.h>
16722 +#include <bcmendian.h>
16723 +#include <sbconfig.h>
16724 +#include <bcmutils.h>
16725 +#include <bcmdevs.h>
16726 +#include <sbutils.h>
16727 +
16728 +struct dma_info; /* forward declaration */
16729 +#define di_t struct dma_info
16730 +
16731 +#include <sbhnddma.h>
16732 +#include <hnddma.h>
16733 +
16734 +/* debug/trace */
16735 +#define DMA_ERROR(args)
16736 +#define DMA_TRACE(args)
16737 +
16738 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
16739 +static uint dma_msg_level =
16740 + 0;
16741 +
16742 +#define MAXNAMEL 8
16743 +
16744 +/* dma engine software state */
16745 +typedef struct dma_info {
16746 + hnddma_t hnddma; /* exported structure */
16747 + uint *msg_level; /* message level pointer */
16748 + char name[MAXNAMEL]; /* callers name for diag msgs */
16749 +
16750 + void *osh; /* os handle */
16751 + sb_t *sbh; /* sb handle */
16752 +
16753 + bool dma64; /* dma64 enabled */
16754 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
16755 +
16756 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
16757 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
16758 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
16759 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
16760 +
16761 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
16762 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
16763 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
16764 + uint ntxd; /* # tx descriptors tunable */
16765 + uint txin; /* index of next descriptor to reclaim */
16766 + uint txout; /* index of next descriptor to post */
16767 + uint txavail; /* # free tx descriptors */
16768 + void **txp; /* pointer to parallel array of pointers to packets */
16769 + ulong txdpa; /* physical address of descriptor ring */
16770 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
16771 + uint txdalloc; /* #bytes allocated for the ring */
16772 +
16773 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
16774 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
16775 + uint nrxd; /* # rx descriptors tunable */
16776 + uint rxin; /* index of next descriptor to reclaim */
16777 + uint rxout; /* index of next descriptor to post */
16778 + void **rxp; /* pointer to parallel array of pointers to packets */
16779 + ulong rxdpa; /* physical address of descriptor ring */
16780 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
16781 + uint rxdalloc; /* #bytes allocated for the ring */
16782 +
16783 + /* tunables */
16784 + uint rxbufsize; /* rx buffer size in bytes */
16785 + uint nrxpost; /* # rx buffers to keep posted */
16786 + uint rxoffset; /* rxcontrol offset */
16787 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
16788 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
16789 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
16790 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
16791 +} dma_info_t;
16792 +
16793 +#ifdef BCMDMA64
16794 +#define DMA64_ENAB(di) ((di)->dma64)
16795 +#else
16796 +#define DMA64_ENAB(di) (0)
16797 +#endif
16798 +
16799 +/* descriptor bumping macros */
16800 +#define XXD(x, n) ((x) & ((n) - 1))
16801 +#define TXD(x) XXD((x), di->ntxd)
16802 +#define RXD(x) XXD((x), di->nrxd)
16803 +#define NEXTTXD(i) TXD(i + 1)
16804 +#define PREVTXD(i) TXD(i - 1)
16805 +#define NEXTRXD(i) RXD(i + 1)
16806 +#define NTXDACTIVE(h, t) TXD(t - h)
16807 +#define NRXDACTIVE(h, t) RXD(t - h)
16808 +
16809 +/* macros to convert between byte offsets and indexes */
16810 +#define B2I(bytes, type) ((bytes) / sizeof(type))
16811 +#define I2B(index, type) ((index) * sizeof(type))
16812 +
16813 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
16814 +#define PCI32ADDR_HIGH_SHIFT 30
16815 +
16816 +
16817 +/* prototypes */
16818 +static bool dma_isaddrext(dma_info_t *di);
16819 +static bool dma_alloc(dma_info_t *di, uint direction);
16820 +
16821 +static bool dma32_alloc(dma_info_t *di, uint direction);
16822 +static void dma32_txreset(dma_info_t *di);
16823 +static void dma32_rxreset(dma_info_t *di);
16824 +static bool dma32_txsuspendedidle(dma_info_t *di);
16825 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16826 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
16827 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
16828 +static void dma32_txrotate(di_t *di);
16829 +
16830 +/* prototype or stubs */
16831 +#ifdef BCMDMA64
16832 +static bool dma64_alloc(dma_info_t *di, uint direction);
16833 +static void dma64_txreset(dma_info_t *di);
16834 +static void dma64_rxreset(dma_info_t *di);
16835 +static bool dma64_txsuspendedidle(dma_info_t *di);
16836 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
16837 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
16838 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
16839 +static void dma64_txrotate(di_t *di);
16840 +#else
16841 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
16842 +static void dma64_txreset(dma_info_t *di) {}
16843 +static void dma64_rxreset(dma_info_t *di) {}
16844 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
16845 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
16846 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
16847 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
16848 +static void dma64_txrotate(di_t *di) { return; }
16849 +#endif
16850 +
16851 +/* old dmaregs struct for compatibility */
16852 +typedef volatile struct {
16853 + /* transmit channel */
16854 + uint32 xmtcontrol; /* enable, et al */
16855 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
16856 + uint32 xmtptr; /* last descriptor posted to chip */
16857 + uint32 xmtstatus; /* current active descriptor, et al */
16858 +
16859 + /* receive channel */
16860 + uint32 rcvcontrol; /* enable, et al */
16861 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
16862 + uint32 rcvptr; /* last descriptor posted to chip */
16863 + uint32 rcvstatus; /* current active descriptor, et al */
16864 +} dmaregs_t;
16865 +
16866 +typedef struct {
16867 + uint ddoffset;
16868 + uint dataoffset;
16869 +} compat_data;
16870 +
16871 +static compat_data *ugly_hack = NULL;
16872 +
16873 +void*
16874 +dma_attold(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
16875 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
16876 +{
16877 + dma32regs_t *dtx = regs;
16878 + dma32regs_t *drx = dtx + 1;
16879 +
16880 + ugly_hack = kmalloc(sizeof(ugly_hack), GFP_KERNEL);
16881 + ugly_hack->ddoffset = ddoffset;
16882 + ugly_hack->dataoffset = dataoffset;
16883 + dma_attach((osl_t *) osh, name, NULL, dtx, drx, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, msg_level);
16884 + ugly_hack = NULL;
16885 +}
16886 +
16887 +
16888 +void*
16889 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
16890 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
16891 +{
16892 + dma_info_t *di;
16893 + uint size;
16894 +
16895 + /* allocate private info structure */
16896 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
16897 + return (NULL);
16898 + }
16899 + bzero((char*)di, sizeof (dma_info_t));
16900 +
16901 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
16902 +
16903 + if (sbh != NULL)
16904 + di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
16905 +
16906 +#ifndef BCMDMA64
16907 + if (di->dma64) {
16908 + DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
16909 + goto fail;
16910 + }
16911 +#endif
16912 +
16913 + /* check arguments */
16914 + ASSERT(ISPOWEROF2(ntxd));
16915 + ASSERT(ISPOWEROF2(nrxd));
16916 + if (nrxd == 0)
16917 + ASSERT(dmaregsrx == NULL);
16918 + if (ntxd == 0)
16919 + ASSERT(dmaregstx == NULL);
16920 +
16921 +
16922 + /* init dma reg pointer */
16923 + if (di->dma64) {
16924 + ASSERT(ntxd <= D64MAXDD);
16925 + ASSERT(nrxd <= D64MAXDD);
16926 + di->d64txregs = (dma64regs_t *)dmaregstx;
16927 + di->d64rxregs = (dma64regs_t *)dmaregsrx;
16928 +
16929 + di->dma64align = D64RINGALIGN;
16930 + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
16931 + /* for smaller dd table, HW relax the alignment requirement */
16932 + di->dma64align = D64RINGALIGN / 2;
16933 + }
16934 + } else {
16935 + ASSERT(ntxd <= D32MAXDD);
16936 + ASSERT(nrxd <= D32MAXDD);
16937 + di->d32txregs = (dma32regs_t *)dmaregstx;
16938 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
16939 + }
16940 +
16941 +
16942 + /* make a private copy of our callers name */
16943 + strncpy(di->name, name, MAXNAMEL);
16944 + di->name[MAXNAMEL-1] = '\0';
16945 +
16946 + di->osh = osh;
16947 + di->sbh = sbh;
16948 +
16949 + /* save tunables */
16950 + di->ntxd = ntxd;
16951 + di->nrxd = nrxd;
16952 + di->rxbufsize = rxbufsize;
16953 + di->nrxpost = nrxpost;
16954 + di->rxoffset = rxoffset;
16955 +
16956 + /*
16957 + * figure out the DMA physical address offset for dd and data
16958 + * for old chips w/o sb, use zero
16959 + * for new chips w sb,
16960 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
16961 + * Other bus: use zero
16962 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
16963 + */
16964 + di->ddoffsetlow = 0;
16965 + di->dataoffsetlow = 0;
16966 + if (ugly_hack != NULL) {
16967 + di->ddoffsetlow = ugly_hack->ddoffset;
16968 + di->dataoffsetlow = ugly_hack->dataoffset;
16969 + di->ddoffsethigh = 0;
16970 + di->dataoffsethigh = 0;
16971 + } else if (sbh != NULL) {
16972 + if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
16973 + if ((sbh->buscoretype == SB_PCIE) && di->dma64){
16974 + di->ddoffsetlow = 0;
16975 + di->ddoffsethigh = SB_PCIE_DMA_H32;
16976 + } else {
16977 + di->ddoffsetlow = SB_PCI_DMA;
16978 + di->ddoffsethigh = 0;
16979 + }
16980 + di->dataoffsetlow = di->ddoffsetlow;
16981 + di->dataoffsethigh = di->ddoffsethigh;
16982 + }
16983 +#if defined(__mips__) && defined(IL_BIGENDIAN)
16984 + /* use sdram swapped region for data buffers but not dma descriptors */
16985 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
16986 +#endif
16987 + }
16988 +
16989 + di->addrext = ((ugly_hack == NULL) ? dma_isaddrext(di) : 0);
16990 +
16991 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
16992 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
16993 +
16994 + /* allocate tx packet pointer vector */
16995 + if (ntxd) {
16996 + size = ntxd * sizeof (void*);
16997 + if ((di->txp = MALLOC(osh, size)) == NULL) {
16998 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
16999 + goto fail;
17000 + }
17001 + bzero((char*)di->txp, size);
17002 + }
17003 +
17004 + /* allocate rx packet pointer vector */
17005 + if (nrxd) {
17006 + size = nrxd * sizeof (void*);
17007 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
17008 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17009 + goto fail;
17010 + }
17011 + bzero((char*)di->rxp, size);
17012 + }
17013 +
17014 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
17015 + if (ntxd) {
17016 + if (!dma_alloc(di, DMA_TX))
17017 + goto fail;
17018 + }
17019 +
17020 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
17021 + if (nrxd) {
17022 + if (!dma_alloc(di, DMA_RX))
17023 + goto fail;
17024 + }
17025 +
17026 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17027 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
17028 + goto fail;
17029 + }
17030 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17031 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
17032 + goto fail;
17033 + }
17034 +
17035 + return ((void*)di);
17036 +
17037 +fail:
17038 + dma_detach((void*)di);
17039 + return (NULL);
17040 +}
17041 +
17042 +static bool
17043 +dma_alloc(dma_info_t *di, uint direction)
17044 +{
17045 + if (DMA64_ENAB(di)) {
17046 + return dma64_alloc(di, direction);
17047 + } else {
17048 + return dma32_alloc(di, direction);
17049 + }
17050 +}
17051 +
17052 +/* may be called with core in reset */
17053 +void
17054 +dma_detach(dma_info_t *di)
17055 +{
17056 + if (di == NULL)
17057 + return;
17058 +
17059 + DMA_TRACE(("%s: dma_detach\n", di->name));
17060 +
17061 + /* shouldn't be here if descriptors are unreclaimed */
17062 + ASSERT(di->txin == di->txout);
17063 + ASSERT(di->rxin == di->rxout);
17064 +
17065 + /* free dma descriptor rings */
17066 + if (di->txd32)
17067 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
17068 + if (di->rxd32)
17069 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
17070 +
17071 + /* free packet pointer vectors */
17072 + if (di->txp)
17073 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
17074 + if (di->rxp)
17075 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
17076 +
17077 + /* free our private info structure */
17078 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
17079 +}
17080 +
17081 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
17082 +static bool
17083 +dma_isaddrext(dma_info_t *di)
17084 +{
17085 + uint32 w;
17086 +
17087 + if (DMA64_ENAB(di)) {
17088 + OR_REG(&di->d64txregs->control, D64_XC_AE);
17089 + w = R_REG(&di->d32txregs->control);
17090 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
17091 + return ((w & XC_AE) == D64_XC_AE);
17092 + } else {
17093 + OR_REG(&di->d32txregs->control, XC_AE);
17094 + w = R_REG(&di->d32txregs->control);
17095 + AND_REG(&di->d32txregs->control, ~XC_AE);
17096 + return ((w & XC_AE) == XC_AE);
17097 + }
17098 +}
17099 +
17100 +void
17101 +dma_txreset(dma_info_t *di)
17102 +{
17103 + DMA_TRACE(("%s: dma_txreset\n", di->name));
17104 +
17105 + if (DMA64_ENAB(di))
17106 + dma64_txreset(di);
17107 + else
17108 + dma32_txreset(di);
17109 +}
17110 +
17111 +void
17112 +dma_rxreset(dma_info_t *di)
17113 +{
17114 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
17115 +
17116 + if (DMA64_ENAB(di))
17117 + dma64_rxreset(di);
17118 + else
17119 + dma32_rxreset(di);
17120 +}
17121 +
17122 +/* initialize descriptor table base address */
17123 +static void
17124 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
17125 +{
17126 + if (DMA64_ENAB(di)) {
17127 + if (direction == DMA_TX) {
17128 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
17129 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
17130 + } else {
17131 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
17132 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
17133 + }
17134 + } else {
17135 + uint32 offset = di->ddoffsetlow;
17136 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17137 + if (direction == DMA_TX)
17138 + W_REG(&di->d32txregs->addr, (pa + offset));
17139 + else
17140 + W_REG(&di->d32rxregs->addr, (pa + offset));
17141 + } else {
17142 + /* dma32 address extension */
17143 + uint32 ae;
17144 + ASSERT(di->addrext);
17145 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17146 +
17147 + if (direction == DMA_TX) {
17148 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17149 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
17150 + } else {
17151 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17152 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
17153 + }
17154 + }
17155 + }
17156 +}
17157 +
17158 +/* init the tx or rx descriptor */
17159 +static INLINE void
17160 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
17161 +{
17162 + uint offset = di->dataoffsetlow;
17163 +
17164 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17165 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
17166 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17167 + } else {
17168 + /* address extension */
17169 + uint32 ae;
17170 + ASSERT(di->addrext);
17171 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17172 +
17173 + *ctrl |= (ae << CTRL_AE_SHIFT);
17174 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
17175 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17176 + }
17177 +}
17178 +
17179 +/* init the tx or rx descriptor */
17180 +static INLINE void
17181 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
17182 +{
17183 + uint32 bufaddr_low = pa + di->dataoffsetlow;
17184 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
17185 +
17186 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
17187 +
17188 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
17189 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
17190 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
17191 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
17192 +}
17193 +
17194 +void
17195 +dma_txinit(dma_info_t *di)
17196 +{
17197 + DMA_TRACE(("%s: dma_txinit\n", di->name));
17198 +
17199 + di->txin = di->txout = 0;
17200 + di->txavail = di->ntxd - 1;
17201 +
17202 + /* clear tx descriptor ring */
17203 + if (DMA64_ENAB(di)) {
17204 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
17205 + W_REG(&di->d64txregs->control, XC_XE);
17206 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17207 + } else {
17208 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
17209 + W_REG(&di->d32txregs->control, XC_XE);
17210 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17211 + }
17212 +}
17213 +
17214 +bool
17215 +dma_txenabled(dma_info_t *di)
17216 +{
17217 + uint32 xc;
17218 +
17219 + /* If the chip is dead, it is not enabled :-) */
17220 + if (DMA64_ENAB(di)) {
17221 + xc = R_REG(&di->d64txregs->control);
17222 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
17223 + } else {
17224 + xc = R_REG(&di->d32txregs->control);
17225 + return ((xc != 0xffffffff) && (xc & XC_XE));
17226 + }
17227 +}
17228 +
17229 +void
17230 +dma_txsuspend(dma_info_t *di)
17231 +{
17232 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
17233 + if (DMA64_ENAB(di))
17234 + OR_REG(&di->d64txregs->control, D64_XC_SE);
17235 + else
17236 + OR_REG(&di->d32txregs->control, XC_SE);
17237 +}
17238 +
17239 +void
17240 +dma_txresume(dma_info_t *di)
17241 +{
17242 + DMA_TRACE(("%s: dma_txresume\n", di->name));
17243 + if (DMA64_ENAB(di))
17244 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
17245 + else
17246 + AND_REG(&di->d32txregs->control, ~XC_SE);
17247 +}
17248 +
17249 +bool
17250 +dma_txsuspendedidle(dma_info_t *di)
17251 +{
17252 + if (DMA64_ENAB(di))
17253 + return dma64_txsuspendedidle(di);
17254 + else
17255 + return dma32_txsuspendedidle(di);
17256 +}
17257 +
17258 +bool
17259 +dma_txsuspended(dma_info_t *di)
17260 +{
17261 + if (DMA64_ENAB(di))
17262 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
17263 + else
17264 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
17265 +}
17266 +
17267 +bool
17268 +dma_txstopped(dma_info_t *di)
17269 +{
17270 + if (DMA64_ENAB(di))
17271 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
17272 + else
17273 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
17274 +}
17275 +
17276 +bool
17277 +dma_rxstopped(dma_info_t *di)
17278 +{
17279 + if (DMA64_ENAB(di))
17280 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
17281 + else
17282 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
17283 +}
17284 +
17285 +void
17286 +dma_fifoloopbackenable(dma_info_t *di)
17287 +{
17288 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
17289 + if (DMA64_ENAB(di))
17290 + OR_REG(&di->d64txregs->control, D64_XC_LE);
17291 + else
17292 + OR_REG(&di->d32txregs->control, XC_LE);
17293 +}
17294 +
17295 +void
17296 +dma_rxinit(dma_info_t *di)
17297 +{
17298 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
17299 +
17300 + di->rxin = di->rxout = 0;
17301 +
17302 + /* clear rx descriptor ring */
17303 + if (DMA64_ENAB(di)) {
17304 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
17305 + dma_rxenable(di);
17306 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17307 + } else {
17308 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
17309 + dma_rxenable(di);
17310 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17311 + }
17312 +}
17313 +
17314 +void
17315 +dma_rxenable(dma_info_t *di)
17316 +{
17317 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
17318 + if (DMA64_ENAB(di))
17319 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
17320 + else
17321 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
17322 +}
17323 +
17324 +bool
17325 +dma_rxenabled(dma_info_t *di)
17326 +{
17327 + uint32 rc;
17328 +
17329 + if (DMA64_ENAB(di)) {
17330 + rc = R_REG(&di->d64rxregs->control);
17331 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
17332 + } else {
17333 + rc = R_REG(&di->d32rxregs->control);
17334 + return ((rc != 0xffffffff) && (rc & RC_RE));
17335 + }
17336 +}
17337 +
17338 +
17339 +/* !! tx entry routine */
17340 +int
17341 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17342 +{
17343 + if (DMA64_ENAB(di)) {
17344 + return dma64_txfast(di, p0, coreflags);
17345 + } else {
17346 + return dma32_txfast(di, p0, coreflags);
17347 + }
17348 +}
17349 +
17350 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
17351 +void*
17352 +dma_rx(dma_info_t *di)
17353 +{
17354 + void *p;
17355 + uint len;
17356 + int skiplen = 0;
17357 +
17358 + while ((p = dma_getnextrxp(di, FALSE))) {
17359 + /* skip giant packets which span multiple rx descriptors */
17360 + if (skiplen > 0) {
17361 + skiplen -= di->rxbufsize;
17362 + if (skiplen < 0)
17363 + skiplen = 0;
17364 + PKTFREE(di->osh, p, FALSE);
17365 + continue;
17366 + }
17367 +
17368 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
17369 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
17370 +
17371 + /* bad frame length check */
17372 + if (len > (di->rxbufsize - di->rxoffset)) {
17373 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
17374 + if (len > 0)
17375 + skiplen = len - (di->rxbufsize - di->rxoffset);
17376 + PKTFREE(di->osh, p, FALSE);
17377 + di->hnddma.rxgiants++;
17378 + continue;
17379 + }
17380 +
17381 + /* set actual length */
17382 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
17383 +
17384 + break;
17385 + }
17386 +
17387 + return (p);
17388 +}
17389 +
17390 +/* post receive buffers */
17391 +void
17392 +dma_rxfill(dma_info_t *di)
17393 +{
17394 + void *p;
17395 + uint rxin, rxout;
17396 + uint32 ctrl;
17397 + uint n;
17398 + uint i;
17399 + uint32 pa;
17400 + uint rxbufsize;
17401 +
17402 + /*
17403 + * Determine how many receive buffers we're lacking
17404 + * from the full complement, allocate, initialize,
17405 + * and post them, then update the chip rx lastdscr.
17406 + */
17407 +
17408 + rxin = di->rxin;
17409 + rxout = di->rxout;
17410 + rxbufsize = di->rxbufsize;
17411 +
17412 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
17413 +
17414 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
17415 +
17416 + for (i = 0; i < n; i++) {
17417 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
17418 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
17419 + di->hnddma.rxnobuf++;
17420 + break;
17421 + }
17422 +
17423 + /* Do a cached write instead of uncached write since DMA_MAP
17424 + * will flush the cache. */
17425 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
17426 +
17427 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
17428 + ASSERT(ISALIGNED(pa, 4));
17429 +
17430 + /* save the free packet pointer */
17431 + ASSERT(di->rxp[rxout] == NULL);
17432 + di->rxp[rxout] = p;
17433 +
17434 + if (DMA64_ENAB(di)) {
17435 + /* prep the descriptor control value */
17436 + if (rxout == (di->nrxd - 1))
17437 + ctrl = CTRL_EOT;
17438 +
17439 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
17440 + } else {
17441 + /* prep the descriptor control value */
17442 + ctrl = rxbufsize;
17443 + if (rxout == (di->nrxd - 1))
17444 + ctrl |= CTRL_EOT;
17445 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
17446 + }
17447 +
17448 + rxout = NEXTRXD(rxout);
17449 + }
17450 +
17451 + di->rxout = rxout;
17452 +
17453 + /* update the chip lastdscr pointer */
17454 + if (DMA64_ENAB(di)) {
17455 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
17456 + } else {
17457 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
17458 + }
17459 +}
17460 +
17461 +void
17462 +dma_txreclaim(dma_info_t *di, bool forceall)
17463 +{
17464 + void *p;
17465 +
17466 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
17467 +
17468 + while ((p = dma_getnexttxp(di, forceall)))
17469 + PKTFREE(di->osh, p, TRUE);
17470 +}
17471 +
17472 +/*
17473 + * Reclaim next completed txd (txds if using chained buffers) and
17474 + * return associated packet.
17475 + * If 'force' is true, reclaim txd(s) and return associated packet
17476 + * regardless of the value of the hardware "curr" pointer.
17477 + */
17478 +void*
17479 +dma_getnexttxp(dma_info_t *di, bool forceall)
17480 +{
17481 + if (DMA64_ENAB(di)) {
17482 + return dma64_getnexttxp(di, forceall);
17483 + } else {
17484 + return dma32_getnexttxp(di, forceall);
17485 + }
17486 +}
17487 +
17488 +/* like getnexttxp but no reclaim */
17489 +void*
17490 +dma_peeknexttxp(dma_info_t *di)
17491 +{
17492 + uint end, i;
17493 +
17494 + if (DMA64_ENAB(di)) {
17495 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
17496 + } else {
17497 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17498 + }
17499 +
17500 + for (i = di->txin; i != end; i = NEXTTXD(i))
17501 + if (di->txp[i])
17502 + return (di->txp[i]);
17503 +
17504 + return (NULL);
17505 +}
17506 +
17507 +/*
17508 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
17509 + */
17510 +void
17511 +dma_txrotate(di_t *di)
17512 +{
17513 + if (DMA64_ENAB(di)) {
17514 + dma64_txrotate(di);
17515 + } else {
17516 + dma32_txrotate(di);
17517 + }
17518 +}
17519 +
17520 +void
17521 +dma_rxreclaim(dma_info_t *di)
17522 +{
17523 + void *p;
17524 +
17525 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
17526 +
17527 + while ((p = dma_getnextrxp(di, TRUE)))
17528 + PKTFREE(di->osh, p, FALSE);
17529 +}
17530 +
17531 +void *
17532 +dma_getnextrxp(dma_info_t *di, bool forceall)
17533 +{
17534 + if (DMA64_ENAB(di)) {
17535 + return dma64_getnextrxp(di, forceall);
17536 + } else {
17537 + return dma32_getnextrxp(di, forceall);
17538 + }
17539 +}
17540 +
17541 +uintptr
17542 +dma_getvar(dma_info_t *di, char *name)
17543 +{
17544 + if (!strcmp(name, "&txavail"))
17545 + return ((uintptr) &di->txavail);
17546 + else {
17547 + ASSERT(0);
17548 + }
17549 + return (0);
17550 +}
17551 +
17552 +void
17553 +dma_txblock(dma_info_t *di)
17554 +{
17555 + di->txavail = 0;
17556 +}
17557 +
17558 +void
17559 +dma_txunblock(dma_info_t *di)
17560 +{
17561 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17562 +}
17563 +
17564 +uint
17565 +dma_txactive(dma_info_t *di)
17566 +{
17567 + return (NTXDACTIVE(di->txin, di->txout));
17568 +}
17569 +
17570 +void
17571 +dma_rxpiomode(dma32regs_t *regs)
17572 +{
17573 + W_REG(&regs->control, RC_FM);
17574 +}
17575 +
17576 +void
17577 +dma_txpioloopback(dma32regs_t *regs)
17578 +{
17579 + OR_REG(&regs->control, XC_LE);
17580 +}
17581 +
17582 +
17583 +
17584 +
17585 +/*** 32 bits DMA non-inline functions ***/
17586 +static bool
17587 +dma32_alloc(dma_info_t *di, uint direction)
17588 +{
17589 + uint size;
17590 + uint ddlen;
17591 + void *va;
17592 +
17593 + ddlen = sizeof (dma32dd_t);
17594 +
17595 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17596 +
17597 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
17598 + size += D32RINGALIGN;
17599 +
17600 +
17601 + if (direction == DMA_TX) {
17602 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17603 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17604 + return FALSE;
17605 + }
17606 +
17607 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17608 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
17609 + di->txdpa += di->txdalign;
17610 + di->txdalloc = size;
17611 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
17612 + } else {
17613 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17614 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17615 + return FALSE;
17616 + }
17617 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17618 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
17619 + di->rxdpa += di->rxdalign;
17620 + di->rxdalloc = size;
17621 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
17622 + }
17623 +
17624 + return TRUE;
17625 +}
17626 +
17627 +static void
17628 +dma32_txreset(dma_info_t *di)
17629 +{
17630 + uint32 status;
17631 +
17632 + /* suspend tx DMA first */
17633 + W_REG(&di->d32txregs->control, XC_SE);
17634 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
17635 + status != XS_XS_IDLE &&
17636 + status != XS_XS_STOPPED,
17637 + 10000);
17638 +
17639 + W_REG(&di->d32txregs->control, 0);
17640 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
17641 + 10000);
17642 +
17643 + if (status != XS_XS_DISABLED) {
17644 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17645 + }
17646 +
17647 + /* wait for the last transaction to complete */
17648 + OSL_DELAY(300);
17649 +}
17650 +
17651 +static void
17652 +dma32_rxreset(dma_info_t *di)
17653 +{
17654 + uint32 status;
17655 +
17656 + W_REG(&di->d32rxregs->control, 0);
17657 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
17658 + 10000);
17659 +
17660 + if (status != RS_RS_DISABLED) {
17661 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17662 + }
17663 +}
17664 +
17665 +static bool
17666 +dma32_txsuspendedidle(dma_info_t *di)
17667 +{
17668 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
17669 + return 0;
17670 +
17671 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
17672 + return 0;
17673 +
17674 + OSL_DELAY(2);
17675 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
17676 +}
17677 +
17678 +/*
17679 + * supports full 32bit dma engine buffer addressing so
17680 + * dma buffers can cross 4 Kbyte page boundaries.
17681 + */
17682 +static int
17683 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17684 +{
17685 + void *p, *next;
17686 + uchar *data;
17687 + uint len;
17688 + uint txout;
17689 + uint32 ctrl;
17690 + uint32 pa;
17691 +
17692 + DMA_TRACE(("%s: dma_txfast\n", di->name));
17693 +
17694 + txout = di->txout;
17695 + ctrl = 0;
17696 +
17697 + /*
17698 + * Walk the chain of packet buffers
17699 + * allocating and initializing transmit descriptor entries.
17700 + */
17701 + for (p = p0; p; p = next) {
17702 + data = PKTDATA(di->osh, p);
17703 + len = PKTLEN(di->osh, p);
17704 + next = PKTNEXT(di->osh, p);
17705 +
17706 + /* return nonzero if out of tx descriptors */
17707 + if (NEXTTXD(txout) == di->txin)
17708 + goto outoftxd;
17709 +
17710 + if (len == 0)
17711 + continue;
17712 +
17713 + /* get physical address of buffer start */
17714 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
17715 +
17716 + /* build the descriptor control value */
17717 + ctrl = len & CTRL_BC_MASK;
17718 +
17719 + ctrl |= coreflags;
17720 +
17721 + if (p == p0)
17722 + ctrl |= CTRL_SOF;
17723 + if (next == NULL)
17724 + ctrl |= (CTRL_IOC | CTRL_EOF);
17725 + if (txout == (di->ntxd - 1))
17726 + ctrl |= CTRL_EOT;
17727 +
17728 + if (DMA64_ENAB(di)) {
17729 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
17730 + } else {
17731 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
17732 + }
17733 +
17734 + ASSERT(di->txp[txout] == NULL);
17735 +
17736 + txout = NEXTTXD(txout);
17737 + }
17738 +
17739 + /* if last txd eof not set, fix it */
17740 + if (!(ctrl & CTRL_EOF))
17741 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
17742 +
17743 + /* save the packet */
17744 + di->txp[PREVTXD(txout)] = p0;
17745 +
17746 + /* bump the tx descriptor index */
17747 + di->txout = txout;
17748 +
17749 + /* kick the chip */
17750 + if (DMA64_ENAB(di)) {
17751 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
17752 + } else {
17753 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
17754 + }
17755 +
17756 + /* tx flow control */
17757 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17758 +
17759 + return (0);
17760 +
17761 + outoftxd:
17762 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
17763 + PKTFREE(di->osh, p0, TRUE);
17764 + di->txavail = 0;
17765 + di->hnddma.txnobuf++;
17766 + return (-1);
17767 +}
17768 +
17769 +static void*
17770 +dma32_getnexttxp(dma_info_t *di, bool forceall)
17771 +{
17772 + uint start, end, i;
17773 + void *txp;
17774 +
17775 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
17776 +
17777 + txp = NULL;
17778 +
17779 + start = di->txin;
17780 + if (forceall)
17781 + end = di->txout;
17782 + else
17783 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17784 +
17785 + if ((start == 0) && (end > di->txout))
17786 + goto bogus;
17787 +
17788 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
17789 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
17790 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
17791 +
17792 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
17793 + txp = di->txp[i];
17794 + di->txp[i] = NULL;
17795 + }
17796 +
17797 + di->txin = i;
17798 +
17799 + /* tx flow control */
17800 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17801 +
17802 + return (txp);
17803 +
17804 +bogus:
17805 +/*
17806 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
17807 + start, end, di->txout, forceall));
17808 +*/
17809 + return (NULL);
17810 +}
17811 +
17812 +static void *
17813 +dma32_getnextrxp(dma_info_t *di, bool forceall)
17814 +{
17815 + uint i;
17816 + void *rxp;
17817 +
17818 + /* if forcing, dma engine must be disabled */
17819 + ASSERT(!forceall || !dma_rxenabled(di));
17820 +
17821 + i = di->rxin;
17822 +
17823 + /* return if no packets posted */
17824 + if (i == di->rxout)
17825 + return (NULL);
17826 +
17827 + /* ignore curr if forceall */
17828 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
17829 + return (NULL);
17830 +
17831 + /* get the packet pointer that corresponds to the rx descriptor */
17832 + rxp = di->rxp[i];
17833 + ASSERT(rxp);
17834 + di->rxp[i] = NULL;
17835 +
17836 + /* clear this packet from the descriptor ring */
17837 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
17838 + di->rxbufsize, DMA_RX, rxp);
17839 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
17840 +
17841 + di->rxin = NEXTRXD(i);
17842 +
17843 + return (rxp);
17844 +}
17845 +
17846 +static void
17847 +dma32_txrotate(di_t *di)
17848 +{
17849 + uint ad;
17850 + uint nactive;
17851 + uint rot;
17852 + uint old, new;
17853 + uint32 w;
17854 + uint first, last;
17855 +
17856 + ASSERT(dma_txsuspendedidle(di));
17857 +
17858 + nactive = dma_txactive(di);
17859 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
17860 + rot = TXD(ad - di->txin);
17861 +
17862 + ASSERT(rot < di->ntxd);
17863 +
17864 + /* full-ring case is a lot harder - don't worry about this */
17865 + if (rot >= (di->ntxd - nactive)) {
17866 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
17867 + return;
17868 + }
17869 +
17870 + first = di->txin;
17871 + last = PREVTXD(di->txout);
17872 +
17873 + /* move entries starting at last and moving backwards to first */
17874 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
17875 + new = TXD(old + rot);
17876 +
17877 + /*
17878 + * Move the tx dma descriptor.
17879 + * EOT is set only in the last entry in the ring.
17880 + */
17881 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
17882 + if (new == (di->ntxd - 1))
17883 + w |= CTRL_EOT;
17884 + W_SM(&di->txd32[new].ctrl, w);
17885 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
17886 +
17887 + /* zap the old tx dma descriptor address field */
17888 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
17889 +
17890 + /* move the corresponding txp[] entry */
17891 + ASSERT(di->txp[new] == NULL);
17892 + di->txp[new] = di->txp[old];
17893 + di->txp[old] = NULL;
17894 + }
17895 +
17896 + /* update txin and txout */
17897 + di->txin = ad;
17898 + di->txout = TXD(di->txout + rot);
17899 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17900 +
17901 + /* kick the chip */
17902 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
17903 +}
17904 +
17905 +/*** 64 bits DMA non-inline functions ***/
17906 +
17907 +#ifdef BCMDMA64
17908 +
17909 +static bool
17910 +dma64_alloc(dma_info_t *di, uint direction)
17911 +{
17912 + uint size;
17913 + uint ddlen;
17914 + uint32 alignbytes;
17915 + void *va;
17916 +
17917 + ddlen = sizeof (dma64dd_t);
17918 +
17919 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17920 +
17921 + alignbytes = di->dma64align;
17922 +
17923 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
17924 + size += alignbytes;
17925 +
17926 +
17927 + if (direction == DMA_TX) {
17928 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17929 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17930 + return FALSE;
17931 + }
17932 +
17933 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
17934 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
17935 + di->txdpa += di->txdalign;
17936 + di->txdalloc = size;
17937 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
17938 + } else {
17939 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17940 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17941 + return FALSE;
17942 + }
17943 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
17944 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
17945 + di->rxdpa += di->rxdalign;
17946 + di->rxdalloc = size;
17947 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
17948 + }
17949 +
17950 + return TRUE;
17951 +}
17952 +
17953 +static void
17954 +dma64_txreset(dma_info_t *di)
17955 +{
17956 + uint32 status;
17957 +
17958 + /* suspend tx DMA first */
17959 + W_REG(&di->d64txregs->control, D64_XC_SE);
17960 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
17961 + status != D64_XS0_XS_IDLE &&
17962 + status != D64_XS0_XS_STOPPED,
17963 + 10000);
17964 +
17965 + W_REG(&di->d64txregs->control, 0);
17966 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
17967 + 10000);
17968 +
17969 + if (status != D64_XS0_XS_DISABLED) {
17970 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17971 + }
17972 +
17973 + /* wait for the last transaction to complete */
17974 + OSL_DELAY(300);
17975 +}
17976 +
17977 +static void
17978 +dma64_rxreset(dma_info_t *di)
17979 +{
17980 + uint32 status;
17981 +
17982 + W_REG(&di->d64rxregs->control, 0);
17983 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
17984 + 10000);
17985 +
17986 + if (status != D64_RS0_RS_DISABLED) {
17987 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17988 + }
17989 +}
17990 +
17991 +static bool
17992 +dma64_txsuspendedidle(dma_info_t *di)
17993 +{
17994 +
17995 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
17996 + return 0;
17997 +
17998 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
17999 + return 1;
18000 +
18001 + return 0;
18002 +}
18003 +
18004 +/*
18005 + * supports full 32bit dma engine buffer addressing so
18006 + * dma buffers can cross 4 Kbyte page boundaries.
18007 + */
18008 +static int
18009 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
18010 +{
18011 + void *p, *next;
18012 + uchar *data;
18013 + uint len;
18014 + uint txout;
18015 + uint32 flags;
18016 + uint32 pa;
18017 +
18018 + DMA_TRACE(("%s: dma_txfast\n", di->name));
18019 +
18020 + txout = di->txout;
18021 + flags = 0;
18022 +
18023 + /*
18024 + * Walk the chain of packet buffers
18025 + * allocating and initializing transmit descriptor entries.
18026 + */
18027 + for (p = p0; p; p = next) {
18028 + data = PKTDATA(di->osh, p);
18029 + len = PKTLEN(di->osh, p);
18030 + next = PKTNEXT(di->osh, p);
18031 +
18032 + /* return nonzero if out of tx descriptors */
18033 + if (NEXTTXD(txout) == di->txin)
18034 + goto outoftxd;
18035 +
18036 + if (len == 0)
18037 + continue;
18038 +
18039 + /* get physical address of buffer start */
18040 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
18041 +
18042 + flags = coreflags;
18043 +
18044 + if (p == p0)
18045 + flags |= D64_CTRL1_SOF;
18046 + if (next == NULL)
18047 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
18048 + if (txout == (di->ntxd - 1))
18049 + flags |= D64_CTRL1_EOT;
18050 +
18051 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
18052 +
18053 + ASSERT(di->txp[txout] == NULL);
18054 +
18055 + txout = NEXTTXD(txout);
18056 + }
18057 +
18058 + /* if last txd eof not set, fix it */
18059 + if (!(flags & D64_CTRL1_EOF))
18060 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
18061 +
18062 + /* save the packet */
18063 + di->txp[PREVTXD(txout)] = p0;
18064 +
18065 + /* bump the tx descriptor index */
18066 + di->txout = txout;
18067 +
18068 + /* kick the chip */
18069 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18070 +
18071 + /* tx flow control */
18072 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18073 +
18074 + return (0);
18075 +
18076 +outoftxd:
18077 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18078 + PKTFREE(di->osh, p0, TRUE);
18079 + di->txavail = 0;
18080 + di->hnddma.txnobuf++;
18081 + return (-1);
18082 +}
18083 +
18084 +static void*
18085 +dma64_getnexttxp(dma_info_t *di, bool forceall)
18086 +{
18087 + uint start, end, i;
18088 + void *txp;
18089 +
18090 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18091 +
18092 + txp = NULL;
18093 +
18094 + start = di->txin;
18095 + if (forceall)
18096 + end = di->txout;
18097 + else
18098 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
18099 +
18100 + if ((start == 0) && (end > di->txout))
18101 + goto bogus;
18102 +
18103 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18104 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
18105 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
18106 +
18107 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
18108 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
18109 +
18110 + txp = di->txp[i];
18111 + di->txp[i] = NULL;
18112 + }
18113 +
18114 + di->txin = i;
18115 +
18116 + /* tx flow control */
18117 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18118 +
18119 + return (txp);
18120 +
18121 +bogus:
18122 +/*
18123 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18124 + start, end, di->txout, forceall));
18125 +*/
18126 + return (NULL);
18127 +}
18128 +
18129 +static void *
18130 +dma64_getnextrxp(dma_info_t *di, bool forceall)
18131 +{
18132 + uint i;
18133 + void *rxp;
18134 +
18135 + /* if forcing, dma engine must be disabled */
18136 + ASSERT(!forceall || !dma_rxenabled(di));
18137 +
18138 + i = di->rxin;
18139 +
18140 + /* return if no packets posted */
18141 + if (i == di->rxout)
18142 + return (NULL);
18143 +
18144 + /* ignore curr if forceall */
18145 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
18146 + return (NULL);
18147 +
18148 + /* get the packet pointer that corresponds to the rx descriptor */
18149 + rxp = di->rxp[i];
18150 + ASSERT(rxp);
18151 + di->rxp[i] = NULL;
18152 +
18153 + /* clear this packet from the descriptor ring */
18154 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
18155 + di->rxbufsize, DMA_RX, rxp);
18156 +
18157 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
18158 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
18159 +
18160 + di->rxin = NEXTRXD(i);
18161 +
18162 + return (rxp);
18163 +}
18164 +
18165 +static void
18166 +dma64_txrotate(di_t *di)
18167 +{
18168 + uint ad;
18169 + uint nactive;
18170 + uint rot;
18171 + uint old, new;
18172 + uint32 w;
18173 + uint first, last;
18174 +
18175 + ASSERT(dma_txsuspendedidle(di));
18176 +
18177 + nactive = dma_txactive(di);
18178 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
18179 + rot = TXD(ad - di->txin);
18180 +
18181 + ASSERT(rot < di->ntxd);
18182 +
18183 + /* full-ring case is a lot harder - don't worry about this */
18184 + if (rot >= (di->ntxd - nactive)) {
18185 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18186 + return;
18187 + }
18188 +
18189 + first = di->txin;
18190 + last = PREVTXD(di->txout);
18191 +
18192 + /* move entries starting at last and moving backwards to first */
18193 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18194 + new = TXD(old + rot);
18195 +
18196 + /*
18197 + * Move the tx dma descriptor.
18198 + * EOT is set only in the last entry in the ring.
18199 + */
18200 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
18201 + if (new == (di->ntxd - 1))
18202 + w |= D64_CTRL1_EOT;
18203 + W_SM(&di->txd64[new].ctrl1, w);
18204 +
18205 + w = R_SM(&di->txd64[old].ctrl2);
18206 + W_SM(&di->txd64[new].ctrl2, w);
18207 +
18208 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
18209 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
18210 +
18211 + /* zap the old tx dma descriptor address field */
18212 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
18213 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
18214 +
18215 + /* move the corresponding txp[] entry */
18216 + ASSERT(di->txp[new] == NULL);
18217 + di->txp[new] = di->txp[old];
18218 + di->txp[old] = NULL;
18219 + }
18220 +
18221 + /* update txin and txout */
18222 + di->txin = ad;
18223 + di->txout = TXD(di->txout + rot);
18224 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18225 +
18226 + /* kick the chip */
18227 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
18228 +}
18229 +
18230 +#endif
18231 +
18232 diff -Nur linux-2.4.32/drivers/net/hnd/linux_osl.c linux-2.4.32-brcm/drivers/net/hnd/linux_osl.c
18233 --- linux-2.4.32/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
18234 +++ linux-2.4.32-brcm/drivers/net/hnd/linux_osl.c 2005-12-16 23:39:11.292858500 +0100
18235 @@ -0,0 +1,708 @@
18236 +/*
18237 + * Linux OS Independent Layer
18238 + *
18239 + * Copyright 2005, Broadcom Corporation
18240 + * All Rights Reserved.
18241 + *
18242 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18243 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18244 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18245 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18246 + *
18247 + * $Id$
18248 + */
18249 +
18250 +#define LINUX_OSL
18251 +
18252 +#include <typedefs.h>
18253 +#include <bcmendian.h>
18254 +#include <linux/module.h>
18255 +#include <linuxver.h>
18256 +#include <osl.h>
18257 +#include <bcmutils.h>
18258 +#include <linux/delay.h>
18259 +#ifdef mips
18260 +#include <asm/paccess.h>
18261 +#endif
18262 +#include <pcicfg.h>
18263 +
18264 +#define PCI_CFG_RETRY 10
18265 +
18266 +#define OS_HANDLE_MAGIC 0x1234abcd
18267 +#define BCM_MEM_FILENAME_LEN 24
18268 +
18269 +typedef struct bcm_mem_link {
18270 + struct bcm_mem_link *prev;
18271 + struct bcm_mem_link *next;
18272 + uint size;
18273 + int line;
18274 + char file[BCM_MEM_FILENAME_LEN];
18275 +} bcm_mem_link_t;
18276 +
18277 +struct os_handle {
18278 + uint magic;
18279 + void *pdev;
18280 + uint malloced;
18281 + uint failed;
18282 + bcm_mem_link_t *dbgmem_list;
18283 +};
18284 +
18285 +static int16 linuxbcmerrormap[] = \
18286 +{ 0, /* 0 */
18287 + -EINVAL, /* BCME_ERROR */
18288 + -EINVAL, /* BCME_BADARG*/
18289 + -EINVAL, /* BCME_BADOPTION*/
18290 + -EINVAL, /* BCME_NOTUP */
18291 + -EINVAL, /* BCME_NOTDOWN */
18292 + -EINVAL, /* BCME_NOTAP */
18293 + -EINVAL, /* BCME_NOTSTA */
18294 + -EINVAL, /* BCME_BADKEYIDX */
18295 + -EINVAL, /* BCME_RADIOOFF */
18296 + -EINVAL, /* BCME_NOTBANDLOCKED */
18297 + -EINVAL, /* BCME_NOCLK */
18298 + -EINVAL, /* BCME_BADRATESET */
18299 + -EINVAL, /* BCME_BADBAND */
18300 + -E2BIG, /* BCME_BUFTOOSHORT */
18301 + -E2BIG, /* BCME_BUFTOOLONG */
18302 + -EBUSY, /* BCME_BUSY */
18303 + -EINVAL, /* BCME_NOTASSOCIATED */
18304 + -EINVAL, /* BCME_BADSSIDLEN */
18305 + -EINVAL, /* BCME_OUTOFRANGECHAN */
18306 + -EINVAL, /* BCME_BADCHAN */
18307 + -EFAULT, /* BCME_BADADDR */
18308 + -ENOMEM, /* BCME_NORESOURCE */
18309 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
18310 + -EMSGSIZE, /* BCME_BADLENGTH */
18311 + -EINVAL, /* BCME_NOTREADY */
18312 + -EPERM, /* BCME_NOTPERMITTED */
18313 + -ENOMEM, /* BCME_NOMEM */
18314 + -EINVAL, /* BCME_ASSOCIATED */
18315 + -ERANGE, /* BCME_RANGE */
18316 + -EINVAL /* BCME_NOTFOUND */
18317 +};
18318 +
18319 +/* translate bcmerrors into linux errors*/
18320 +int
18321 +osl_error(int bcmerror)
18322 +{
18323 + int abs_bcmerror;
18324 + int array_size = ARRAYSIZE(linuxbcmerrormap);
18325 +
18326 + abs_bcmerror = ABS(bcmerror);
18327 +
18328 + if (bcmerror > 0)
18329 + abs_bcmerror = 0;
18330 +
18331 + else if (abs_bcmerror >= array_size)
18332 + abs_bcmerror = BCME_ERROR;
18333 +
18334 + return linuxbcmerrormap[abs_bcmerror];
18335 +}
18336 +
18337 +osl_t *
18338 +osl_attach(void *pdev)
18339 +{
18340 + osl_t *osh;
18341 +
18342 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
18343 + ASSERT(osh);
18344 +
18345 + /*
18346 + * check the cases where
18347 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
18348 + * dependent error code
18349 + * 2. Error code is added to the bcmerror table, but forgot to add the
18350 + * corresponding errorstring(dummy call to bcmerrorstr)
18351 + */
18352 + bcmerrorstr(0);
18353 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
18354 +
18355 + osh->magic = OS_HANDLE_MAGIC;
18356 + osh->malloced = 0;
18357 + osh->failed = 0;
18358 + osh->dbgmem_list = NULL;
18359 + osh->pdev = pdev;
18360 +
18361 + return osh;
18362 +}
18363 +
18364 +void
18365 +osl_detach(osl_t *osh)
18366 +{
18367 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
18368 + kfree(osh);
18369 +}
18370 +
18371 +void*
18372 +osl_pktget(osl_t *osh, uint len, bool send)
18373 +{
18374 + struct sk_buff *skb;
18375 +
18376 + if ((skb = dev_alloc_skb(len)) == NULL)
18377 + return (NULL);
18378 +
18379 + skb_put(skb, len);
18380 +
18381 + /* ensure the cookie field is cleared */
18382 + PKTSETCOOKIE(skb, NULL);
18383 +
18384 + return ((void*) skb);
18385 +}
18386 +
18387 +void
18388 +osl_pktfree(void *p)
18389 +{
18390 + struct sk_buff *skb, *nskb;
18391 +
18392 + skb = (struct sk_buff*) p;
18393 +
18394 + /* perversion: we use skb->next to chain multi-skb packets */
18395 + while (skb) {
18396 + nskb = skb->next;
18397 + skb->next = NULL;
18398 + if (skb->destructor) {
18399 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
18400 + dev_kfree_skb_any(skb);
18401 + } else {
18402 + /* can free immediately (even in_irq()) if destructor does not exist */
18403 + dev_kfree_skb(skb);
18404 + }
18405 + skb = nskb;
18406 + }
18407 +}
18408 +
18409 +uint32
18410 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
18411 +{
18412 + uint val;
18413 + uint retry=PCI_CFG_RETRY;
18414 +
18415 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18416 +
18417 + /* only 4byte access supported */
18418 + ASSERT(size == 4);
18419 +
18420 + do {
18421 + pci_read_config_dword(osh->pdev, offset, &val);
18422 + if (val != 0xffffffff)
18423 + break;
18424 + } while (retry--);
18425 +
18426 +
18427 + return (val);
18428 +}
18429 +
18430 +void
18431 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
18432 +{
18433 + uint retry=PCI_CFG_RETRY;
18434 +
18435 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18436 +
18437 + /* only 4byte access supported */
18438 + ASSERT(size == 4);
18439 +
18440 + do {
18441 + pci_write_config_dword(osh->pdev, offset, val);
18442 + if (offset!=PCI_BAR0_WIN)
18443 + break;
18444 + if (osl_pci_read_config(osh,offset,size) == val)
18445 + break;
18446 + } while (retry--);
18447 +
18448 +}
18449 +
18450 +/* return bus # for the pci device pointed by osh->pdev */
18451 +uint
18452 +osl_pci_bus(osl_t *osh)
18453 +{
18454 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18455 +
18456 + return ((struct pci_dev *)osh->pdev)->bus->number;
18457 +}
18458 +
18459 +/* return slot # for the pci device pointed by osh->pdev */
18460 +uint
18461 +osl_pci_slot(osl_t *osh)
18462 +{
18463 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18464 +
18465 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
18466 +}
18467 +
18468 +static void
18469 +osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
18470 +{
18471 +}
18472 +
18473 +void
18474 +osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
18475 +{
18476 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
18477 +}
18478 +
18479 +void
18480 +osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
18481 +{
18482 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
18483 +}
18484 +
18485 +
18486 +#ifdef BCMDBG_MEM
18487 +
18488 +void*
18489 +osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
18490 +{
18491 + bcm_mem_link_t *p;
18492 + char* basename;
18493 +
18494 + ASSERT(size);
18495 +
18496 + if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
18497 + return (NULL);
18498 +
18499 + p->size = size;
18500 + p->line = line;
18501 +
18502 + basename = strrchr(file, '/');
18503 + /* skip the '/' */
18504 + if (basename)
18505 + basename++;
18506 +
18507 + if (!basename)
18508 + basename = file;
18509 +
18510 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
18511 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
18512 +
18513 + /* link this block */
18514 + p->prev = NULL;
18515 + p->next = osh->dbgmem_list;
18516 + if (p->next)
18517 + p->next->prev = p;
18518 + osh->dbgmem_list = p;
18519 +
18520 + return p + 1;
18521 +}
18522 +
18523 +void
18524 +osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
18525 +{
18526 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
18527 +
18528 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18529 +
18530 + if (p->size == 0) {
18531 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
18532 + (uint)addr, size, line, file);
18533 + ASSERT(p->size);
18534 + return;
18535 + }
18536 +
18537 + if (p->size != size) {
18538 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
18539 + size, p->size, (uint)addr, line, file);
18540 + ASSERT(p->size == size);
18541 + return;
18542 + }
18543 +
18544 + /* unlink this block */
18545 + if (p->prev)
18546 + p->prev->next = p->next;
18547 + if (p->next)
18548 + p->next->prev = p->prev;
18549 + if (osh->dbgmem_list == p)
18550 + osh->dbgmem_list = p->next;
18551 + p->next = p->prev = NULL;
18552 +
18553 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
18554 +}
18555 +
18556 +char*
18557 +osl_debug_memdump(osl_t *osh, char *buf, uint sz)
18558 +{
18559 + bcm_mem_link_t *p;
18560 + char *obuf;
18561 +
18562 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18563 + obuf = buf;
18564 +
18565 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
18566 + for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
18567 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
18568 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
18569 +
18570 + return (obuf);
18571 +}
18572 +
18573 +#endif /* BCMDBG_MEM */
18574 +
18575 +void*
18576 +osl_malloc(osl_t *osh, uint size)
18577 +{
18578 + void *addr;
18579 +
18580 + /* only ASSERT if osh is defined */
18581 + if (osh)
18582 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18583 +
18584 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
18585 + if(osh)
18586 + osh->failed++;
18587 + return (NULL);
18588 + }
18589 + if (osh)
18590 + osh->malloced += size;
18591 +
18592 + return (addr);
18593 +}
18594 +
18595 +void
18596 +osl_mfree(osl_t *osh, void *addr, uint size)
18597 +{
18598 + if (osh) {
18599 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18600 + osh->malloced -= size;
18601 + }
18602 + kfree(addr);
18603 +}
18604 +
18605 +uint
18606 +osl_malloced(osl_t *osh)
18607 +{
18608 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18609 + return (osh->malloced);
18610 +}
18611 +
18612 +uint osl_malloc_failed(osl_t *osh)
18613 +{
18614 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18615 + return (osh->failed);
18616 +}
18617 +
18618 +void*
18619 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
18620 +{
18621 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18622 +
18623 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
18624 +}
18625 +
18626 +void
18627 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
18628 +{
18629 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18630 +
18631 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
18632 +}
18633 +
18634 +uint
18635 +osl_dma_map(osl_t *osh, void *va, uint size, int direction)
18636 +{
18637 + int dir;
18638 +
18639 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18640 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18641 + return (pci_map_single(osh->pdev, va, size, dir));
18642 +}
18643 +
18644 +void
18645 +osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
18646 +{
18647 + int dir;
18648 +
18649 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18650 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18651 + pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
18652 +}
18653 +
18654 +#if defined(BINOSL)
18655 +void
18656 +osl_assert(char *exp, char *file, int line)
18657 +{
18658 + char tempbuf[255];
18659 +
18660 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
18661 + panic(tempbuf);
18662 +}
18663 +#endif /* BCMDBG || BINOSL */
18664 +
18665 +void
18666 +osl_delay(uint usec)
18667 +{
18668 + uint d;
18669 +
18670 + while (usec > 0) {
18671 + d = MIN(usec, 1000);
18672 + udelay(d);
18673 + usec -= d;
18674 + }
18675 +}
18676 +
18677 +/*
18678 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
18679 + */
18680 +#ifdef BINOSL
18681 +
18682 +int
18683 +osl_printf(const char *format, ...)
18684 +{
18685 + va_list args;
18686 + char buf[1024];
18687 + int len;
18688 +
18689 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
18690 + va_start(args, format);
18691 + len = vsprintf(buf, format, args);
18692 + va_end(args);
18693 +
18694 + if (len > sizeof (buf)) {
18695 + printk("osl_printf: buffer overrun\n");
18696 + return (0);
18697 + }
18698 +
18699 + return (printk(buf));
18700 +}
18701 +
18702 +int
18703 +osl_sprintf(char *buf, const char *format, ...)
18704 +{
18705 + va_list args;
18706 + int rc;
18707 +
18708 + va_start(args, format);
18709 + rc = vsprintf(buf, format, args);
18710 + va_end(args);
18711 + return (rc);
18712 +}
18713 +
18714 +int
18715 +osl_strcmp(const char *s1, const char *s2)
18716 +{
18717 + return (strcmp(s1, s2));
18718 +}
18719 +
18720 +int
18721 +osl_strncmp(const char *s1, const char *s2, uint n)
18722 +{
18723 + return (strncmp(s1, s2, n));
18724 +}
18725 +
18726 +int
18727 +osl_strlen(const char *s)
18728 +{
18729 + return (strlen(s));
18730 +}
18731 +
18732 +char*
18733 +osl_strcpy(char *d, const char *s)
18734 +{
18735 + return (strcpy(d, s));
18736 +}
18737 +
18738 +char*
18739 +osl_strncpy(char *d, const char *s, uint n)
18740 +{
18741 + return (strncpy(d, s, n));
18742 +}
18743 +
18744 +void
18745 +bcopy(const void *src, void *dst, int len)
18746 +{
18747 + memcpy(dst, src, len);
18748 +}
18749 +
18750 +int
18751 +bcmp(const void *b1, const void *b2, int len)
18752 +{
18753 + return (memcmp(b1, b2, len));
18754 +}
18755 +
18756 +void
18757 +bzero(void *b, int len)
18758 +{
18759 + memset(b, '\0', len);
18760 +}
18761 +
18762 +uint32
18763 +osl_readl(volatile uint32 *r)
18764 +{
18765 + return (readl(r));
18766 +}
18767 +
18768 +uint16
18769 +osl_readw(volatile uint16 *r)
18770 +{
18771 + return (readw(r));
18772 +}
18773 +
18774 +uint8
18775 +osl_readb(volatile uint8 *r)
18776 +{
18777 + return (readb(r));
18778 +}
18779 +
18780 +void
18781 +osl_writel(uint32 v, volatile uint32 *r)
18782 +{
18783 + writel(v, r);
18784 +}
18785 +
18786 +void
18787 +osl_writew(uint16 v, volatile uint16 *r)
18788 +{
18789 + writew(v, r);
18790 +}
18791 +
18792 +void
18793 +osl_writeb(uint8 v, volatile uint8 *r)
18794 +{
18795 + writeb(v, r);
18796 +}
18797 +
18798 +void *
18799 +osl_uncached(void *va)
18800 +{
18801 +#ifdef mips
18802 + return ((void*)KSEG1ADDR(va));
18803 +#else
18804 + return ((void*)va);
18805 +#endif
18806 +}
18807 +
18808 +uint
18809 +osl_getcycles(void)
18810 +{
18811 + uint cycles;
18812 +
18813 +#if defined(mips)
18814 + cycles = read_c0_count() * 2;
18815 +#elif defined(__i386__)
18816 + rdtscl(cycles);
18817 +#else
18818 + cycles = 0;
18819 +#endif
18820 + return cycles;
18821 +}
18822 +
18823 +void *
18824 +osl_reg_map(uint32 pa, uint size)
18825 +{
18826 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
18827 +}
18828 +
18829 +void
18830 +osl_reg_unmap(void *va)
18831 +{
18832 + iounmap(va);
18833 +}
18834 +
18835 +int
18836 +osl_busprobe(uint32 *val, uint32 addr)
18837 +{
18838 +#ifdef mips
18839 + return get_dbe(*val, (uint32*)addr);
18840 +#else
18841 + *val = readl(addr);
18842 + return 0;
18843 +#endif
18844 +}
18845 +
18846 +uchar*
18847 +osl_pktdata(osl_t *osh, void *skb)
18848 +{
18849 + return (((struct sk_buff*)skb)->data);
18850 +}
18851 +
18852 +uint
18853 +osl_pktlen(osl_t *osh, void *skb)
18854 +{
18855 + return (((struct sk_buff*)skb)->len);
18856 +}
18857 +
18858 +uint
18859 +osl_pktheadroom(osl_t *osh, void *skb)
18860 +{
18861 + return (uint) skb_headroom((struct sk_buff *) skb);
18862 +}
18863 +
18864 +uint
18865 +osl_pkttailroom(osl_t *osh, void *skb)
18866 +{
18867 + return (uint) skb_tailroom((struct sk_buff *) skb);
18868 +}
18869 +
18870 +void*
18871 +osl_pktnext(osl_t *osh, void *skb)
18872 +{
18873 + return (((struct sk_buff*)skb)->next);
18874 +}
18875 +
18876 +void
18877 +osl_pktsetnext(void *skb, void *x)
18878 +{
18879 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
18880 +}
18881 +
18882 +void
18883 +osl_pktsetlen(osl_t *osh, void *skb, uint len)
18884 +{
18885 + __skb_trim((struct sk_buff*)skb, len);
18886 +}
18887 +
18888 +uchar*
18889 +osl_pktpush(osl_t *osh, void *skb, int bytes)
18890 +{
18891 + return (skb_push((struct sk_buff*)skb, bytes));
18892 +}
18893 +
18894 +uchar*
18895 +osl_pktpull(osl_t *osh, void *skb, int bytes)
18896 +{
18897 + return (skb_pull((struct sk_buff*)skb, bytes));
18898 +}
18899 +
18900 +void*
18901 +osl_pktdup(osl_t *osh, void *skb)
18902 +{
18903 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
18904 +}
18905 +
18906 +void*
18907 +osl_pktcookie(void *skb)
18908 +{
18909 + return ((void*)((struct sk_buff*)skb)->csum);
18910 +}
18911 +
18912 +void
18913 +osl_pktsetcookie(void *skb, void *x)
18914 +{
18915 + ((struct sk_buff*)skb)->csum = (uint)x;
18916 +}
18917 +
18918 +void*
18919 +osl_pktlink(void *skb)
18920 +{
18921 + return (((struct sk_buff*)skb)->prev);
18922 +}
18923 +
18924 +void
18925 +osl_pktsetlink(void *skb, void *x)
18926 +{
18927 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
18928 +}
18929 +
18930 +uint
18931 +osl_pktprio(void *skb)
18932 +{
18933 + return (((struct sk_buff*)skb)->priority);
18934 +}
18935 +
18936 +void
18937 +osl_pktsetprio(void *skb, uint x)
18938 +{
18939 + ((struct sk_buff*)skb)->priority = x;
18940 +}
18941 +
18942 +
18943 +#endif /* BINOSL */
18944 diff -Nur linux-2.4.32/drivers/net/hnd/Makefile linux-2.4.32-brcm/drivers/net/hnd/Makefile
18945 --- linux-2.4.32/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
18946 +++ linux-2.4.32-brcm/drivers/net/hnd/Makefile 2005-12-16 23:39:11.284858000 +0100
18947 @@ -0,0 +1,19 @@
18948 +#
18949 +# Makefile for the BCM47xx specific kernel interface routines
18950 +# under Linux.
18951 +#
18952 +
18953 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
18954 +
18955 +O_TARGET := hnd.o
18956 +
18957 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
18958 +
18959 +export-objs := shared_ksyms.o
18960 +obj-y := shared_ksyms.o $(HND_OBJS)
18961 +obj-m := $(O_TARGET)
18962 +
18963 +include $(TOPDIR)/Rules.make
18964 +
18965 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
18966 + sh -e $< $(HND_OBJS) > $@
18967 diff -Nur linux-2.4.32/drivers/net/hnd/sbutils.c linux-2.4.32-brcm/drivers/net/hnd/sbutils.c
18968 --- linux-2.4.32/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
18969 +++ linux-2.4.32-brcm/drivers/net/hnd/sbutils.c 2005-12-16 23:39:11.316860000 +0100
18970 @@ -0,0 +1,2837 @@
18971 +/*
18972 + * Misc utility routines for accessing chip-specific features
18973 + * of the SiliconBackplane-based Broadcom chips.
18974 + *
18975 + * Copyright 2005, Broadcom Corporation
18976 + * All Rights Reserved.
18977 + *
18978 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18979 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18980 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18981 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18982 + * $Id$
18983 + */
18984 +
18985 +#include <typedefs.h>
18986 +#include <osl.h>
18987 +#include <sbutils.h>
18988 +#include <bcmutils.h>
18989 +#include <bcmdevs.h>
18990 +#include <sbconfig.h>
18991 +#include <sbchipc.h>
18992 +#include <sbpci.h>
18993 +#include <sbpcie.h>
18994 +#include <pcicfg.h>
18995 +#include <sbpcmcia.h>
18996 +#include <sbextif.h>
18997 +#include <bcmsrom.h>
18998 +
18999 +/* debug/trace */
19000 +#define SB_ERROR(args)
19001 +
19002 +
19003 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
19004 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
19005 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
19006 +
19007 +/* misc sb info needed by some of the routines */
19008 +typedef struct sb_info {
19009 +
19010 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
19011 +
19012 + void *osh; /* osl os handle */
19013 + void *sdh; /* bcmsdh handle */
19014 +
19015 + void *curmap; /* current regs va */
19016 + void *regs[SB_MAXCORES]; /* other regs va */
19017 +
19018 + uint curidx; /* current core index */
19019 + uint dev_coreid; /* the core provides driver functions */
19020 +
19021 + bool memseg; /* flag to toggle MEM_SEG register */
19022 +
19023 + uint gpioidx; /* gpio control core index */
19024 + uint gpioid; /* gpio control coretype */
19025 +
19026 + uint numcores; /* # discovered cores */
19027 + uint coreid[SB_MAXCORES]; /* id of each core */
19028 +
19029 + void *intr_arg; /* interrupt callback function arg */
19030 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
19031 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
19032 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
19033 +
19034 +} sb_info_t;
19035 +
19036 +/* local prototypes */
19037 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19038 + uint bustype, void *sdh, char **vars, int *varsz);
19039 +static void BCMINIT(sb_scan)(sb_info_t *si);
19040 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
19041 +static uint _sb_coreidx(sb_info_t *si);
19042 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
19043 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
19044 +static uint BCMINIT(sb_chip2numcores)(uint chip);
19045 +static bool sb_ispcie(sb_info_t *si);
19046 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
19047 +static int sb_pci_fixcfg(sb_info_t *si);
19048 +
19049 +/* routines to access mdio slave device registers */
19050 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
19051 +static void BCMINIT(sb_war30841)(sb_info_t *si);
19052 +
19053 +/* delay needed between the mdio control/ mdiodata register data access */
19054 +#define PR28829_DELAY() OSL_DELAY(10)
19055 +
19056 +
19057 +/* global variable to indicate reservation/release of gpio's*/
19058 +static uint32 sb_gpioreservation = 0;
19059 +
19060 +#define SB_INFO(sbh) (sb_info_t*)sbh
19061 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
19062 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
19063 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
19064 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
19065 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
19066 +#define BADIDX (SB_MAXCORES+1)
19067 +#define NOREV -1
19068 +
19069 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
19070 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
19071 +
19072 +/* sonicsrev */
19073 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
19074 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
19075 +
19076 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
19077 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
19078 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
19079 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
19080 +
19081 +/*
19082 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
19083 + * after core switching to avoid invalid register accesss inside ISR.
19084 + */
19085 +#define INTR_OFF(si, intr_val) \
19086 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19087 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
19088 +#define INTR_RESTORE(si, intr_val) \
19089 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19090 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
19091 +
19092 +/* dynamic clock control defines */
19093 +#define LPOMINFREQ 25000 /* low power oscillator min */
19094 +#define LPOMAXFREQ 43000 /* low power oscillator max */
19095 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
19096 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
19097 +#define PCIMINFREQ 25000000 /* 25 MHz */
19098 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
19099 +
19100 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
19101 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
19102 +
19103 +#define MIN_DUMPBUFLEN 32 /* debug */
19104 +
19105 +/* different register spaces to access thr'u pcie indirect access*/
19106 +#define PCIE_CONFIGREGS 1
19107 +#define PCIE_PCIEREGS 2
19108 +
19109 +/* GPIO Based LED powersave defines */
19110 +#define DEFAULT_GPIO_ONTIME 10
19111 +#define DEFAULT_GPIO_OFFTIME 90
19112 +
19113 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
19114 +
19115 +static uint32
19116 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
19117 +{
19118 + uint8 tmp;
19119 + uint32 val, intr_val = 0;
19120 +
19121 +
19122 + /*
19123 + * compact flash only has 11 bits address, while we needs 12 bits address.
19124 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19125 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19126 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19127 + */
19128 + if(si->memseg) {
19129 + INTR_OFF(si, intr_val);
19130 + tmp = 1;
19131 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19132 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19133 + }
19134 +
19135 + val = R_REG(sbr);
19136 +
19137 + if(si->memseg) {
19138 + tmp = 0;
19139 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19140 + INTR_RESTORE(si, intr_val);
19141 + }
19142 +
19143 + return (val);
19144 +}
19145 +
19146 +static void
19147 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
19148 +{
19149 + uint8 tmp;
19150 + volatile uint32 dummy;
19151 + uint32 intr_val = 0;
19152 +
19153 +
19154 + /*
19155 + * compact flash only has 11 bits address, while we needs 12 bits address.
19156 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19157 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19158 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19159 + */
19160 + if(si->memseg) {
19161 + INTR_OFF(si, intr_val);
19162 + tmp = 1;
19163 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19164 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19165 + }
19166 +
19167 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19168 +#ifdef IL_BIGENDIAN
19169 + dummy = R_REG(sbr);
19170 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19171 + dummy = R_REG(sbr);
19172 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19173 +#else
19174 + dummy = R_REG(sbr);
19175 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19176 + dummy = R_REG(sbr);
19177 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19178 +#endif
19179 + } else
19180 + W_REG(sbr, v);
19181 +
19182 + if(si->memseg) {
19183 + tmp = 0;
19184 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19185 + INTR_RESTORE(si, intr_val);
19186 + }
19187 +}
19188 +
19189 +/*
19190 + * Allocate a sb handle.
19191 + * devid - pci device id (used to determine chip#)
19192 + * osh - opaque OS handle
19193 + * regs - virtual address of initial core registers
19194 + * bustype - pci/pcmcia/sb/sdio/etc
19195 + * vars - pointer to a pointer area for "environment" variables
19196 + * varsz - pointer to int to return the size of the vars
19197 + */
19198 +sb_t *
19199 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
19200 + uint bustype, void *sdh, char **vars, int *varsz)
19201 +{
19202 + sb_info_t *si;
19203 +
19204 + /* alloc sb_info_t */
19205 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
19206 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
19207 + return (NULL);
19208 + }
19209 +
19210 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
19211 + MFREE(osh, si, sizeof (sb_info_t));
19212 + return (NULL);
19213 + }
19214 + return (sb_t *)si;
19215 +}
19216 +
19217 +/* Using sb_kattach depends on SB_BUS support, either implicit */
19218 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
19219 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
19220 +
19221 +/* global kernel resource */
19222 +static sb_info_t ksi;
19223 +
19224 +/* generic kernel variant of sb_attach() */
19225 +sb_t *
19226 +BCMINITFN(sb_kattach)()
19227 +{
19228 + uint32 *regs;
19229 +
19230 + if (ksi.curmap == NULL) {
19231 + uint32 cid;
19232 +
19233 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
19234 + cid = R_REG((uint32 *)regs);
19235 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
19236 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
19237 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
19238 + uint32 *scc, val;
19239 +
19240 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
19241 + val = R_REG(scc);
19242 + SB_ERROR((" initial scc = 0x%x\n", val));
19243 + val |= SCC_SS_XTAL;
19244 + W_REG(scc, val);
19245 + }
19246 +
19247 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
19248 + SB_BUS, NULL, NULL, NULL) == NULL) {
19249 + return NULL;
19250 + }
19251 + }
19252 +
19253 + return (sb_t *)&ksi;
19254 +}
19255 +#endif
19256 +
19257 +static sb_info_t *
19258 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19259 + uint bustype, void *sdh, char **vars, int *varsz)
19260 +{
19261 + uint origidx;
19262 + chipcregs_t *cc;
19263 + sbconfig_t *sb;
19264 + uint32 w;
19265 +
19266 + ASSERT(GOODREGS(regs));
19267 +
19268 + bzero((uchar*)si, sizeof (sb_info_t));
19269 +
19270 + si->sb.buscoreidx = si->gpioidx = BADIDX;
19271 +
19272 + si->osh = osh;
19273 + si->curmap = regs;
19274 + si->sdh = sdh;
19275 +
19276 + /* check to see if we are a sb core mimic'ing a pci core */
19277 + if (bustype == PCI_BUS) {
19278 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
19279 + bustype = SB_BUS;
19280 + else
19281 + bustype = PCI_BUS;
19282 + }
19283 +
19284 + si->sb.bustype = bustype;
19285 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
19286 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
19287 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
19288 + return NULL;
19289 + }
19290 +
19291 + /* need to set memseg flag for CF card first before any sb registers access */
19292 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19293 + si->memseg = TRUE;
19294 +
19295 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
19296 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
19297 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
19298 +
19299 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19300 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
19301 + if (!GOODCOREADDR(w))
19302 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
19303 + }
19304 +
19305 + /* initialize current core index value */
19306 + si->curidx = _sb_coreidx(si);
19307 +
19308 + if (si->curidx == BADIDX) {
19309 + SB_ERROR(("sb_doattach: bad core index\n"));
19310 + return NULL;
19311 + }
19312 +
19313 + /* get sonics backplane revision */
19314 + sb = REGS2SB(si->curmap);
19315 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
19316 +
19317 + /* keep and reuse the initial register mapping */
19318 + origidx = si->curidx;
19319 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
19320 + si->regs[origidx] = regs;
19321 +
19322 + /* is core-0 a chipcommon core? */
19323 + si->numcores = 1;
19324 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
19325 + if (sb_coreid(&si->sb) != SB_CC)
19326 + cc = NULL;
19327 +
19328 + /* determine chip id and rev */
19329 + if (cc) {
19330 + /* chip common core found! */
19331 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
19332 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
19333 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
19334 + } else {
19335 + /* The only pcmcia chip without a chipcommon core is a 4301 */
19336 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19337 + devid = BCM4301_DEVICE_ID;
19338 +
19339 + /* no chip common core -- must convert device id to chip id */
19340 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
19341 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
19342 + sb_setcoreidx(&si->sb, origidx);
19343 + return NULL;
19344 + }
19345 + }
19346 +
19347 + /* get chipcommon rev */
19348 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
19349 +
19350 + /* determine numcores */
19351 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
19352 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
19353 + else
19354 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
19355 +
19356 + /* return to original core */
19357 + sb_setcoreidx(&si->sb, origidx);
19358 +
19359 + /* sanity checks */
19360 + ASSERT(si->sb.chip);
19361 +
19362 + /* scan for cores */
19363 + BCMINIT(sb_scan)(si);
19364 +
19365 + /* fixup necessary chip/core configurations */
19366 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19367 + if (sb_pci_fixcfg(si)) {
19368 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
19369 + return NULL;
19370 + }
19371 + }
19372 +
19373 + /* srom_var_init() depends on sb_scan() info */
19374 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
19375 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
19376 + return (NULL);
19377 + }
19378 +
19379 + if (cc == NULL) {
19380 + /*
19381 + * The chip revision number is hardwired into all
19382 + * of the pci function config rev fields and is
19383 + * independent from the individual core revision numbers.
19384 + * For example, the "A0" silicon of each chip is chip rev 0.
19385 + * For PCMCIA we get it from the CIS instead.
19386 + */
19387 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19388 + ASSERT(vars);
19389 + si->sb.chiprev = getintvar(*vars, "chiprev");
19390 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19391 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
19392 + si->sb.chiprev = w & 0xff;
19393 + } else
19394 + si->sb.chiprev = 0;
19395 + }
19396 +
19397 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19398 + w = getintvar(*vars, "regwindowsz");
19399 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
19400 + }
19401 +
19402 + /* gpio control core is required */
19403 + if (!GOODIDX(si->gpioidx)) {
19404 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
19405 + return NULL;
19406 + }
19407 +
19408 + /* get boardtype and boardrev */
19409 + switch (BUSTYPE(si->sb.bustype)) {
19410 + case PCI_BUS:
19411 + /* do a pci config read to get subsystem id and subvendor id */
19412 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
19413 + si->sb.boardvendor = w & 0xffff;
19414 + si->sb.boardtype = (w >> 16) & 0xffff;
19415 + break;
19416 +
19417 + case PCMCIA_BUS:
19418 + case SDIO_BUS:
19419 + si->sb.boardvendor = getintvar(*vars, "manfid");
19420 + si->sb.boardtype = getintvar(*vars, "prodid");
19421 + break;
19422 +
19423 + case SB_BUS:
19424 + case JTAG_BUS:
19425 + si->sb.boardvendor = VENDOR_BROADCOM;
19426 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
19427 + si->sb.boardtype = 0xffff;
19428 + break;
19429 + }
19430 +
19431 + if (si->sb.boardtype == 0) {
19432 + SB_ERROR(("sb_doattach: unknown board type\n"));
19433 + ASSERT(si->sb.boardtype);
19434 + }
19435 +
19436 + /* setup the GPIO based LED powersave register */
19437 + if (si->sb.ccrev >= 16) {
19438 + w = getintvar(*vars, "gpiotimerval");
19439 + if (!w)
19440 + w = DEFAULT_GPIOTIMERVAL;
19441 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
19442 + }
19443 +
19444 +
19445 + return (si);
19446 +}
19447 +
19448 +uint
19449 +sb_coreid(sb_t *sbh)
19450 +{
19451 + sb_info_t *si;
19452 + sbconfig_t *sb;
19453 +
19454 + si = SB_INFO(sbh);
19455 + sb = REGS2SB(si->curmap);
19456 +
19457 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
19458 +}
19459 +
19460 +uint
19461 +sb_coreidx(sb_t *sbh)
19462 +{
19463 + sb_info_t *si;
19464 +
19465 + si = SB_INFO(sbh);
19466 + return (si->curidx);
19467 +}
19468 +
19469 +/* return current index of core */
19470 +static uint
19471 +_sb_coreidx(sb_info_t *si)
19472 +{
19473 + sbconfig_t *sb;
19474 + uint32 sbaddr = 0;
19475 +
19476 + ASSERT(si);
19477 +
19478 + switch (BUSTYPE(si->sb.bustype)) {
19479 + case SB_BUS:
19480 + sb = REGS2SB(si->curmap);
19481 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
19482 + break;
19483 +
19484 + case PCI_BUS:
19485 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
19486 + break;
19487 +
19488 + case PCMCIA_BUS: {
19489 + uint8 tmp = 0;
19490 +
19491 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
19492 + sbaddr = (uint)tmp << 12;
19493 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
19494 + sbaddr |= (uint)tmp << 16;
19495 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
19496 + sbaddr |= (uint)tmp << 24;
19497 + break;
19498 + }
19499 +
19500 +#ifdef BCMJTAG
19501 + case JTAG_BUS:
19502 + sbaddr = (uint32)si->curmap;
19503 + break;
19504 +#endif /* BCMJTAG */
19505 +
19506 + default:
19507 + ASSERT(0);
19508 + }
19509 +
19510 + if (!GOODCOREADDR(sbaddr))
19511 + return BADIDX;
19512 +
19513 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
19514 +}
19515 +
19516 +uint
19517 +sb_corevendor(sb_t *sbh)
19518 +{
19519 + sb_info_t *si;
19520 + sbconfig_t *sb;
19521 +
19522 + si = SB_INFO(sbh);
19523 + sb = REGS2SB(si->curmap);
19524 +
19525 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
19526 +}
19527 +
19528 +uint
19529 +sb_corerev(sb_t *sbh)
19530 +{
19531 + sb_info_t *si;
19532 + sbconfig_t *sb;
19533 + uint sbidh;
19534 +
19535 + si = SB_INFO(sbh);
19536 + sb = REGS2SB(si->curmap);
19537 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
19538 +
19539 + return (SBCOREREV(sbidh));
19540 +}
19541 +
19542 +void *
19543 +sb_osh(sb_t *sbh)
19544 +{
19545 + sb_info_t *si;
19546 +
19547 + si = SB_INFO(sbh);
19548 + return si->osh;
19549 +}
19550 +
19551 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
19552 +
19553 +/* set/clear sbtmstatelow core-specific flags */
19554 +uint32
19555 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
19556 +{
19557 + sb_info_t *si;
19558 + sbconfig_t *sb;
19559 + uint32 w;
19560 +
19561 + si = SB_INFO(sbh);
19562 + sb = REGS2SB(si->curmap);
19563 +
19564 + ASSERT((val & ~mask) == 0);
19565 + ASSERT((mask & ~SBTML_ALLOW) == 0);
19566 +
19567 + /* mask and set */
19568 + if (mask || val) {
19569 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
19570 + W_SBREG(si, &sb->sbtmstatelow, w);
19571 + }
19572 +
19573 + /* return the new value */
19574 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
19575 +}
19576 +
19577 +/* set/clear sbtmstatehigh core-specific flags */
19578 +uint32
19579 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
19580 +{
19581 + sb_info_t *si;
19582 + sbconfig_t *sb;
19583 + uint32 w;
19584 +
19585 + si = SB_INFO(sbh);
19586 + sb = REGS2SB(si->curmap);
19587 +
19588 + ASSERT((val & ~mask) == 0);
19589 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
19590 +
19591 + /* mask and set */
19592 + if (mask || val) {
19593 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
19594 + W_SBREG(si, &sb->sbtmstatehigh, w);
19595 + }
19596 +
19597 + /* return the new value */
19598 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
19599 +}
19600 +
19601 +/* caller needs to take care of core-specific bist hazards */
19602 +int
19603 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
19604 +{
19605 + uint32 sblo;
19606 + uint coreidx;
19607 + sb_info_t *si;
19608 + int result = 0;
19609 +
19610 + si = SB_INFO(sbh);
19611 +
19612 + coreidx = sb_findcoreidx(si, coreid, coreunit);
19613 + if (!GOODIDX(coreidx))
19614 + result = BCME_ERROR;
19615 + else {
19616 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
19617 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
19618 +
19619 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
19620 +
19621 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
19622 + result = BCME_ERROR;
19623 +
19624 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
19625 + }
19626 +
19627 + return result;
19628 +}
19629 +
19630 +bool
19631 +sb_iscoreup(sb_t *sbh)
19632 +{
19633 + sb_info_t *si;
19634 + sbconfig_t *sb;
19635 +
19636 + si = SB_INFO(sbh);
19637 + sb = REGS2SB(si->curmap);
19638 +
19639 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
19640 +}
19641 +
19642 +/*
19643 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
19644 + * switch back to the original core, and return the new value.
19645 + */
19646 +static uint
19647 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
19648 +{
19649 + uint origidx;
19650 + uint32 *r;
19651 + uint w;
19652 + uint intr_val = 0;
19653 +
19654 + ASSERT(GOODIDX(coreidx));
19655 + ASSERT(regoff < SB_CORE_SIZE);
19656 + ASSERT((val & ~mask) == 0);
19657 +
19658 + INTR_OFF(si, intr_val);
19659 +
19660 + /* save current core index */
19661 + origidx = sb_coreidx(&si->sb);
19662 +
19663 + /* switch core */
19664 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
19665 +
19666 + /* mask and set */
19667 + if (mask || val) {
19668 + if (regoff >= SBCONFIGOFF) {
19669 + w = (R_SBREG(si, r) & ~mask) | val;
19670 + W_SBREG(si, r, w);
19671 + } else {
19672 + w = (R_REG(r) & ~mask) | val;
19673 + W_REG(r, w);
19674 + }
19675 + }
19676 +
19677 + /* readback */
19678 + if (regoff >= SBCONFIGOFF)
19679 + w = R_SBREG(si, r);
19680 + else
19681 + w = R_REG(r);
19682 +
19683 + /* restore core index */
19684 + if (origidx != coreidx)
19685 + sb_setcoreidx(&si->sb, origidx);
19686 +
19687 + INTR_RESTORE(si, intr_val);
19688 + return (w);
19689 +}
19690 +
19691 +#define DWORD_ALIGN(x) (x & ~(0x03))
19692 +#define BYTE_POS(x) (x & 0x3)
19693 +#define WORD_POS(x) (x & 0x1)
19694 +
19695 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
19696 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
19697 +
19698 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
19699 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
19700 +
19701 +#define read_pci_cfg_byte(a) \
19702 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
19703 +
19704 +#define read_pci_cfg_write(a) \
19705 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
19706 +
19707 +
19708 +/* return TRUE if requested capability exists in the PCI config space */
19709 +static bool
19710 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
19711 +{
19712 + uint8 cap_id;
19713 + uint8 cap_ptr;
19714 + uint32 bufsize;
19715 + uint8 byte_val;
19716 +
19717 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
19718 + return FALSE;
19719 +
19720 + /* check for Header type 0*/
19721 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
19722 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
19723 + return FALSE;
19724 +
19725 + /* check if the capability pointer field exists */
19726 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
19727 + if (!(byte_val & PCI_CAPPTR_PRESENT))
19728 + return FALSE;
19729 +
19730 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
19731 + /* check if the capability pointer is 0x00 */
19732 + if (cap_ptr == 0x00)
19733 + return FALSE;
19734 +
19735 +
19736 + /* loop thr'u the capability list and see if the pcie capabilty exists */
19737 +
19738 + cap_id = read_pci_cfg_byte(cap_ptr);
19739 +
19740 + while (cap_id != req_cap_id) {
19741 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
19742 + if (cap_ptr == 0x00) break;
19743 + cap_id = read_pci_cfg_byte(cap_ptr);
19744 + }
19745 + if (cap_id != req_cap_id) {
19746 + return FALSE;
19747 + }
19748 + /* found the caller requested capability */
19749 + if ((buf != NULL) && (buflen != NULL)) {
19750 + bufsize = *buflen;
19751 + if (!bufsize) goto end;
19752 + *buflen = 0;
19753 + /* copy the cpability data excluding cap ID and next ptr */
19754 + cap_ptr += 2;
19755 + if ((bufsize + cap_ptr) > SZPCR)
19756 + bufsize = SZPCR - cap_ptr;
19757 + *buflen = bufsize;
19758 + while (bufsize--) {
19759 + *buf = read_pci_cfg_byte(cap_ptr);
19760 + cap_ptr++;
19761 + buf++;
19762 + }
19763 + }
19764 +end:
19765 + return TRUE;
19766 +}
19767 +
19768 +/* return TRUE if PCIE capability exists the pci config space */
19769 +static bool
19770 +sb_ispcie(sb_info_t *si)
19771 +{
19772 + return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
19773 +}
19774 +
19775 +/* scan the sb enumerated space to identify all cores */
19776 +static void
19777 +BCMINITFN(sb_scan)(sb_info_t *si)
19778 +{
19779 + uint origidx;
19780 + uint i;
19781 + bool pci;
19782 + bool pcie;
19783 + uint pciidx;
19784 + uint pcieidx;
19785 + uint pcirev;
19786 + uint pcierev;
19787 +
19788 +
19789 +
19790 + /* numcores should already be set */
19791 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
19792 +
19793 + /* save current core index */
19794 + origidx = sb_coreidx(&si->sb);
19795 +
19796 + si->sb.buscorerev = NOREV;
19797 + si->sb.buscoreidx = BADIDX;
19798 +
19799 + si->gpioidx = BADIDX;
19800 +
19801 + pci = pcie = FALSE;
19802 + pcirev = pcierev = NOREV;
19803 + pciidx = pcieidx = BADIDX;
19804 +
19805 + for (i = 0; i < si->numcores; i++) {
19806 + sb_setcoreidx(&si->sb, i);
19807 + si->coreid[i] = sb_coreid(&si->sb);
19808 +
19809 + if (si->coreid[i] == SB_PCI) {
19810 + pciidx = i;
19811 + pcirev = sb_corerev(&si->sb);
19812 + pci = TRUE;
19813 + } else if (si->coreid[i] == SB_PCIE) {
19814 + pcieidx = i;
19815 + pcierev = sb_corerev(&si->sb);
19816 + pcie = TRUE;
19817 + } else if (si->coreid[i] == SB_PCMCIA) {
19818 + si->sb.buscorerev = sb_corerev(&si->sb);
19819 + si->sb.buscoretype = si->coreid[i];
19820 + si->sb.buscoreidx = i;
19821 + }
19822 + }
19823 + if (pci && pcie) {
19824 + if (sb_ispcie(si))
19825 + pci = FALSE;
19826 + else
19827 + pcie = FALSE;
19828 + }
19829 + if (pci) {
19830 + si->sb.buscoretype = SB_PCI;
19831 + si->sb.buscorerev = pcirev;
19832 + si->sb.buscoreidx = pciidx;
19833 + }
19834 + else if (pcie) {
19835 + si->sb.buscoretype = SB_PCIE;
19836 + si->sb.buscorerev = pcierev;
19837 + si->sb.buscoreidx = pcieidx;
19838 + }
19839 +
19840 + /*
19841 + * Find the gpio "controlling core" type and index.
19842 + * Precedence:
19843 + * - if there's a chip common core - use that
19844 + * - else if there's a pci core (rev >= 2) - use that
19845 + * - else there had better be an extif core (4710 only)
19846 + */
19847 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
19848 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
19849 + si->gpioid = SB_CC;
19850 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
19851 + si->gpioidx = si->sb.buscoreidx;
19852 + si->gpioid = SB_PCI;
19853 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
19854 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
19855 + si->gpioid = SB_EXTIF;
19856 + } else
19857 + ASSERT(si->gpioidx != BADIDX);
19858 +
19859 + /* return to original core index */
19860 + sb_setcoreidx(&si->sb, origidx);
19861 +}
19862 +
19863 +/* may be called with core in reset */
19864 +void
19865 +sb_detach(sb_t *sbh)
19866 +{
19867 + sb_info_t *si;
19868 + uint idx;
19869 +
19870 + si = SB_INFO(sbh);
19871 +
19872 + if (si == NULL)
19873 + return;
19874 +
19875 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
19876 + for (idx = 0; idx < SB_MAXCORES; idx++)
19877 + if (si->regs[idx]) {
19878 + REG_UNMAP(si->regs[idx]);
19879 + si->regs[idx] = NULL;
19880 + }
19881 +
19882 + if (si != &ksi)
19883 + MFREE(si->osh, si, sizeof (sb_info_t));
19884 +}
19885 +
19886 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
19887 +static uint
19888 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
19889 +{
19890 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
19891 + return (BCM4710_DEVICE_ID);
19892 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
19893 + return (BCM4402_DEVICE_ID);
19894 + if (pcidev == BCM4401_ENET_ID)
19895 + return (BCM4402_DEVICE_ID);
19896 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
19897 + return (BCM4307_DEVICE_ID);
19898 + if (pcidev == BCM4301_DEVICE_ID)
19899 + return (BCM4301_DEVICE_ID);
19900 +
19901 + return (0);
19902 +}
19903 +
19904 +/* convert chip number to number of i/o cores */
19905 +static uint
19906 +BCMINITFN(sb_chip2numcores)(uint chip)
19907 +{
19908 + if (chip == BCM4710_DEVICE_ID)
19909 + return (9);
19910 + if (chip == BCM4402_DEVICE_ID)
19911 + return (3);
19912 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
19913 + return (5);
19914 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
19915 + return (6);
19916 + if (chip == BCM4704_DEVICE_ID)
19917 + return (9);
19918 + if (chip == BCM5365_DEVICE_ID)
19919 + return (7);
19920 +
19921 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
19922 + ASSERT(0);
19923 + return (1);
19924 +}
19925 +
19926 +/* return index of coreid or BADIDX if not found */
19927 +static uint
19928 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
19929 +{
19930 + uint found;
19931 + uint i;
19932 +
19933 + found = 0;
19934 +
19935 + for (i = 0; i < si->numcores; i++)
19936 + if (si->coreid[i] == coreid) {
19937 + if (found == coreunit)
19938 + return (i);
19939 + found++;
19940 + }
19941 +
19942 + return (BADIDX);
19943 +}
19944 +
19945 +/*
19946 + * this function changes logical "focus" to the indiciated core,
19947 + * must be called with interrupt off.
19948 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
19949 + */
19950 +void*
19951 +sb_setcoreidx(sb_t *sbh, uint coreidx)
19952 +{
19953 + sb_info_t *si;
19954 + uint32 sbaddr;
19955 + uint8 tmp;
19956 +
19957 + si = SB_INFO(sbh);
19958 +
19959 + if (coreidx >= si->numcores)
19960 + return (NULL);
19961 +
19962 + /*
19963 + * If the user has provided an interrupt mask enabled function,
19964 + * then assert interrupts are disabled before switching the core.
19965 + */
19966 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
19967 +
19968 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
19969 +
19970 + switch (BUSTYPE(si->sb.bustype)) {
19971 + case SB_BUS:
19972 + /* map new one */
19973 + if (!si->regs[coreidx]) {
19974 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
19975 + ASSERT(GOODREGS(si->regs[coreidx]));
19976 + }
19977 + si->curmap = si->regs[coreidx];
19978 + break;
19979 +
19980 + case PCI_BUS:
19981 + /* point bar0 window */
19982 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
19983 + break;
19984 +
19985 + case PCMCIA_BUS:
19986 + tmp = (sbaddr >> 12) & 0x0f;
19987 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
19988 + tmp = (sbaddr >> 16) & 0xff;
19989 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
19990 + tmp = (sbaddr >> 24) & 0xff;
19991 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
19992 + break;
19993 +#ifdef BCMJTAG
19994 + case JTAG_BUS:
19995 + /* map new one */
19996 + if (!si->regs[coreidx]) {
19997 + si->regs[coreidx] = (void *)sbaddr;
19998 + ASSERT(GOODREGS(si->regs[coreidx]));
19999 + }
20000 + si->curmap = si->regs[coreidx];
20001 + break;
20002 +#endif /* BCMJTAG */
20003 + }
20004 +
20005 + si->curidx = coreidx;
20006 +
20007 + return (si->curmap);
20008 +}
20009 +
20010 +/*
20011 + * this function changes logical "focus" to the indiciated core,
20012 + * must be called with interrupt off.
20013 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20014 + */
20015 +void*
20016 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
20017 +{
20018 + sb_info_t *si;
20019 + uint idx;
20020 +
20021 + si = SB_INFO(sbh);
20022 + idx = sb_findcoreidx(si, coreid, coreunit);
20023 + if (!GOODIDX(idx))
20024 + return (NULL);
20025 +
20026 + return (sb_setcoreidx(sbh, idx));
20027 +}
20028 +
20029 +/* return chip number */
20030 +uint
20031 +BCMINITFN(sb_chip)(sb_t *sbh)
20032 +{
20033 + sb_info_t *si;
20034 +
20035 + si = SB_INFO(sbh);
20036 + return (si->sb.chip);
20037 +}
20038 +
20039 +/* return chip revision number */
20040 +uint
20041 +BCMINITFN(sb_chiprev)(sb_t *sbh)
20042 +{
20043 + sb_info_t *si;
20044 +
20045 + si = SB_INFO(sbh);
20046 + return (si->sb.chiprev);
20047 +}
20048 +
20049 +/* return chip common revision number */
20050 +uint
20051 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
20052 +{
20053 + sb_info_t *si;
20054 +
20055 + si = SB_INFO(sbh);
20056 + return (si->sb.ccrev);
20057 +}
20058 +
20059 +/* return chip package option */
20060 +uint
20061 +BCMINITFN(sb_chippkg)(sb_t *sbh)
20062 +{
20063 + sb_info_t *si;
20064 +
20065 + si = SB_INFO(sbh);
20066 + return (si->sb.chippkg);
20067 +}
20068 +
20069 +/* return PCI core rev. */
20070 +uint
20071 +BCMINITFN(sb_pcirev)(sb_t *sbh)
20072 +{
20073 + sb_info_t *si;
20074 +
20075 + si = SB_INFO(sbh);
20076 + return (si->sb.buscorerev);
20077 +}
20078 +
20079 +bool
20080 +BCMINITFN(sb_war16165)(sb_t *sbh)
20081 +{
20082 + sb_info_t *si;
20083 +
20084 + si = SB_INFO(sbh);
20085 +
20086 + return (PCI(si) && (si->sb.buscorerev <= 10));
20087 +}
20088 +
20089 +static void
20090 +BCMINITFN(sb_war30841)(sb_info_t *si)
20091 +{
20092 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
20093 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
20094 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
20095 +}
20096 +
20097 +/* return PCMCIA core rev. */
20098 +uint
20099 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
20100 +{
20101 + sb_info_t *si;
20102 +
20103 + si = SB_INFO(sbh);
20104 + return (si->sb.buscorerev);
20105 +}
20106 +
20107 +/* return board vendor id */
20108 +uint
20109 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
20110 +{
20111 + sb_info_t *si;
20112 +
20113 + si = SB_INFO(sbh);
20114 + return (si->sb.boardvendor);
20115 +}
20116 +
20117 +/* return boardtype */
20118 +uint
20119 +BCMINITFN(sb_boardtype)(sb_t *sbh)
20120 +{
20121 + sb_info_t *si;
20122 + char *var;
20123 +
20124 + si = SB_INFO(sbh);
20125 +
20126 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
20127 + /* boardtype format is a hex string */
20128 + si->sb.boardtype = getintvar(NULL, "boardtype");
20129 +
20130 + /* backward compatibility for older boardtype string format */
20131 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
20132 + if (!strcmp(var, "bcm94710dev"))
20133 + si->sb.boardtype = BCM94710D_BOARD;
20134 + else if (!strcmp(var, "bcm94710ap"))
20135 + si->sb.boardtype = BCM94710AP_BOARD;
20136 + else if (!strcmp(var, "bu4710"))
20137 + si->sb.boardtype = BU4710_BOARD;
20138 + else if (!strcmp(var, "bcm94702mn"))
20139 + si->sb.boardtype = BCM94702MN_BOARD;
20140 + else if (!strcmp(var, "bcm94710r1"))
20141 + si->sb.boardtype = BCM94710R1_BOARD;
20142 + else if (!strcmp(var, "bcm94710r4"))
20143 + si->sb.boardtype = BCM94710R4_BOARD;
20144 + else if (!strcmp(var, "bcm94702cpci"))
20145 + si->sb.boardtype = BCM94702CPCI_BOARD;
20146 + else if (!strcmp(var, "bcm95380_rr"))
20147 + si->sb.boardtype = BCM95380RR_BOARD;
20148 + }
20149 + }
20150 +
20151 + return (si->sb.boardtype);
20152 +}
20153 +
20154 +/* return bus type of sbh device */
20155 +uint
20156 +sb_bus(sb_t *sbh)
20157 +{
20158 + sb_info_t *si;
20159 +
20160 + si = SB_INFO(sbh);
20161 + return (si->sb.bustype);
20162 +}
20163 +
20164 +/* return bus core type */
20165 +uint
20166 +sb_buscoretype(sb_t *sbh)
20167 +{
20168 + sb_info_t *si;
20169 +
20170 + si = SB_INFO(sbh);
20171 +
20172 + return (si->sb.buscoretype);
20173 +}
20174 +
20175 +/* return bus core revision */
20176 +uint
20177 +sb_buscorerev(sb_t *sbh)
20178 +{
20179 + sb_info_t *si;
20180 + si = SB_INFO(sbh);
20181 +
20182 + return (si->sb.buscorerev);
20183 +}
20184 +
20185 +/* return list of found cores */
20186 +uint
20187 +sb_corelist(sb_t *sbh, uint coreid[])
20188 +{
20189 + sb_info_t *si;
20190 +
20191 + si = SB_INFO(sbh);
20192 +
20193 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
20194 + return (si->numcores);
20195 +}
20196 +
20197 +/* return current register mapping */
20198 +void *
20199 +sb_coreregs(sb_t *sbh)
20200 +{
20201 + sb_info_t *si;
20202 +
20203 + si = SB_INFO(sbh);
20204 + ASSERT(GOODREGS(si->curmap));
20205 +
20206 + return (si->curmap);
20207 +}
20208 +
20209 +
20210 +/* do buffered registers update */
20211 +void
20212 +sb_commit(sb_t *sbh)
20213 +{
20214 + sb_info_t *si;
20215 + uint origidx;
20216 + uint intr_val = 0;
20217 +
20218 + si = SB_INFO(sbh);
20219 +
20220 + origidx = si->curidx;
20221 + ASSERT(GOODIDX(origidx));
20222 +
20223 + INTR_OFF(si, intr_val);
20224 +
20225 + /* switch over to chipcommon core if there is one, else use pci */
20226 + if (si->sb.ccrev != NOREV) {
20227 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
20228 +
20229 + /* do the buffer registers update */
20230 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
20231 + W_REG(&ccregs->broadcastdata, 0x0);
20232 + } else if (PCI(si)) {
20233 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
20234 +
20235 + /* do the buffer registers update */
20236 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
20237 + W_REG(&pciregs->bcastdata, 0x0);
20238 + } else
20239 + ASSERT(0);
20240 +
20241 + /* restore core index */
20242 + sb_setcoreidx(sbh, origidx);
20243 + INTR_RESTORE(si, intr_val);
20244 +}
20245 +
20246 +/* reset and re-enable a core */
20247 +void
20248 +sb_core_reset(sb_t *sbh, uint32 bits)
20249 +{
20250 + sb_info_t *si;
20251 + sbconfig_t *sb;
20252 + volatile uint32 dummy;
20253 +
20254 + si = SB_INFO(sbh);
20255 + ASSERT(GOODREGS(si->curmap));
20256 + sb = REGS2SB(si->curmap);
20257 +
20258 + /*
20259 + * Must do the disable sequence first to work for arbitrary current core state.
20260 + */
20261 + sb_core_disable(sbh, bits);
20262 +
20263 + /*
20264 + * Now do the initialization sequence.
20265 + */
20266 +
20267 + /* set reset while enabling the clock and forcing them on throughout the core */
20268 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
20269 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20270 + OSL_DELAY(1);
20271 +
20272 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
20273 + W_SBREG(si, &sb->sbtmstatehigh, 0);
20274 + }
20275 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
20276 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
20277 + }
20278 +
20279 + /* clear reset and allow it to propagate throughout the core */
20280 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
20281 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20282 + OSL_DELAY(1);
20283 +
20284 + /* leave clock enabled */
20285 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
20286 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20287 + OSL_DELAY(1);
20288 +}
20289 +
20290 +void
20291 +sb_core_tofixup(sb_t *sbh)
20292 +{
20293 + sb_info_t *si;
20294 + sbconfig_t *sb;
20295 +
20296 + si = SB_INFO(sbh);
20297 +
20298 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
20299 + return;
20300 +
20301 + ASSERT(GOODREGS(si->curmap));
20302 + sb = REGS2SB(si->curmap);
20303 +
20304 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
20305 + SET_SBREG(si, &sb->sbimconfiglow,
20306 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20307 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
20308 + } else {
20309 + if (sb_coreid(sbh) == SB_PCI) {
20310 + SET_SBREG(si, &sb->sbimconfiglow,
20311 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20312 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20313 + } else {
20314 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
20315 + }
20316 + }
20317 +
20318 + sb_commit(sbh);
20319 +}
20320 +
20321 +/*
20322 + * Set the initiator timeout for the "master core".
20323 + * The master core is defined to be the core in control
20324 + * of the chip and so it issues accesses to non-memory
20325 + * locations (Because of dma *any* core can access memeory).
20326 + *
20327 + * The routine uses the bus to decide who is the master:
20328 + * SB_BUS => mips
20329 + * JTAG_BUS => chipc
20330 + * PCI_BUS => pci or pcie
20331 + * PCMCIA_BUS => pcmcia
20332 + * SDIO_BUS => pcmcia
20333 + *
20334 + * This routine exists so callers can disable initiator
20335 + * timeouts so accesses to very slow devices like otp
20336 + * won't cause an abort. The routine allows arbitrary
20337 + * settings of the service and request timeouts, though.
20338 + *
20339 + * Returns the timeout state before changing it or -1
20340 + * on error.
20341 + */
20342 +
20343 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
20344 +
20345 +uint32
20346 +sb_set_initiator_to(sb_t *sbh, uint32 to)
20347 +{
20348 + sb_info_t *si;
20349 + uint origidx, idx;
20350 + uint intr_val = 0;
20351 + uint32 tmp, ret = 0xffffffff;
20352 + sbconfig_t *sb;
20353 +
20354 + si = SB_INFO(sbh);
20355 +
20356 + if ((to & ~TO_MASK) != 0)
20357 + return ret;
20358 +
20359 + /* Figure out the master core */
20360 + idx = BADIDX;
20361 + switch (BUSTYPE(si->sb.bustype)) {
20362 + case PCI_BUS:
20363 + idx = si->sb.buscoreidx;
20364 + break;
20365 + case JTAG_BUS:
20366 + idx = SB_CC_IDX;
20367 + break;
20368 + case PCMCIA_BUS:
20369 + case SDIO_BUS:
20370 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
20371 + break;
20372 + case SB_BUS:
20373 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
20374 + idx = sb_findcoreidx(si, SB_MIPS, 0);
20375 + break;
20376 + default:
20377 + ASSERT(0);
20378 + }
20379 + if (idx == BADIDX)
20380 + return ret;
20381 +
20382 + INTR_OFF(si, intr_val);
20383 + origidx = sb_coreidx(sbh);
20384 +
20385 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
20386 +
20387 + tmp = R_SBREG(si, &sb->sbimconfiglow);
20388 + ret = tmp & TO_MASK;
20389 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
20390 +
20391 + sb_commit(sbh);
20392 + sb_setcoreidx(sbh, origidx);
20393 + INTR_RESTORE(si, intr_val);
20394 + return ret;
20395 +}
20396 +
20397 +void
20398 +sb_core_disable(sb_t *sbh, uint32 bits)
20399 +{
20400 + sb_info_t *si;
20401 + volatile uint32 dummy;
20402 + uint32 rej;
20403 + sbconfig_t *sb;
20404 +
20405 + si = SB_INFO(sbh);
20406 +
20407 + ASSERT(GOODREGS(si->curmap));
20408 + sb = REGS2SB(si->curmap);
20409 +
20410 + /* if core is already in reset, just return */
20411 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
20412 + return;
20413 +
20414 + /* reject value changed between sonics 2.2 and 2.3 */
20415 + if (si->sb.sonicsrev == SONICS_2_2)
20416 + rej = (1 << SBTML_REJ_SHIFT);
20417 + else
20418 + rej = (2 << SBTML_REJ_SHIFT);
20419 +
20420 + /* if clocks are not enabled, put into reset and return */
20421 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
20422 + goto disable;
20423 +
20424 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
20425 + OR_SBREG(si, &sb->sbtmstatelow, rej);
20426 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20427 + OSL_DELAY(1);
20428 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
20429 +
20430 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
20431 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
20432 + dummy = R_SBREG(si, &sb->sbimstate);
20433 + OSL_DELAY(1);
20434 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
20435 + }
20436 +
20437 + /* set reset and reject while enabling the clocks */
20438 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
20439 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20440 + OSL_DELAY(10);
20441 +
20442 + /* don't forget to clear the initiator reject bit */
20443 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
20444 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
20445 +
20446 +disable:
20447 + /* leave reset and reject asserted */
20448 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
20449 + OSL_DELAY(1);
20450 +}
20451 +
20452 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
20453 +void
20454 +sb_watchdog(sb_t *sbh, uint ticks)
20455 +{
20456 + sb_info_t *si = SB_INFO(sbh);
20457 +
20458 + /* instant NMI */
20459 + switch (si->gpioid) {
20460 + case SB_CC:
20461 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
20462 + break;
20463 + case SB_EXTIF:
20464 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
20465 + break;
20466 + }
20467 +}
20468 +
20469 +/* initialize the pcmcia core */
20470 +void
20471 +sb_pcmcia_init(sb_t *sbh)
20472 +{
20473 + sb_info_t *si;
20474 + uint8 cor;
20475 +
20476 + si = SB_INFO(sbh);
20477 +
20478 + /* enable d11 mac interrupts */
20479 + if (si->sb.chip == BCM4301_DEVICE_ID) {
20480 + /* Have to use FCR2 in 4301 */
20481 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20482 + cor |= COR_IRQEN | COR_FUNEN;
20483 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20484 + } else {
20485 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20486 + cor |= COR_IRQEN | COR_FUNEN;
20487 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20488 + }
20489 +
20490 +}
20491 +
20492 +
20493 +/*
20494 + * Configure the pci core for pci client (NIC) action
20495 + * coremask is the bitvec of cores by index to be enabled.
20496 + */
20497 +void
20498 +sb_pci_setup(sb_t *sbh, uint coremask)
20499 +{
20500 + sb_info_t *si;
20501 + sbconfig_t *sb;
20502 + sbpciregs_t *pciregs;
20503 + uint32 sbflag;
20504 + uint32 w;
20505 + uint idx;
20506 + int reg_val;
20507 +
20508 + si = SB_INFO(sbh);
20509 +
20510 + /* if not pci bus, we're done */
20511 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
20512 + return;
20513 +
20514 + ASSERT(PCI(si) || PCIE(si));
20515 + ASSERT(si->sb.buscoreidx != BADIDX);
20516 +
20517 + /* get current core index */
20518 + idx = si->curidx;
20519 +
20520 + /* we interrupt on this backplane flag number */
20521 + ASSERT(GOODREGS(si->curmap));
20522 + sb = REGS2SB(si->curmap);
20523 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
20524 +
20525 + /* switch over to pci core */
20526 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
20527 + sb = REGS2SB(pciregs);
20528 +
20529 + /*
20530 + * Enable sb->pci interrupts. Assume
20531 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
20532 + */
20533 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
20534 + /* pci config write to set this core bit in PCIIntMask */
20535 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
20536 + w |= (coremask << PCI_SBIM_SHIFT);
20537 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
20538 + } else {
20539 + /* set sbintvec bit for our flag number */
20540 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
20541 + }
20542 +
20543 + if (PCI(si)) {
20544 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
20545 + if (si->sb.buscorerev >= 11)
20546 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
20547 + if (si->sb.buscorerev < 5) {
20548 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20549 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20550 + sb_commit(sbh);
20551 + }
20552 + }
20553 +
20554 + if (PCIE(si) && (si->sb.buscorerev == 0)) {
20555 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
20556 + reg_val |= 0x8;
20557 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
20558 +
20559 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
20560 + reg_val &= ~(0x40);
20561 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
20562 +
20563 + BCMINIT(sb_war30841)(si);
20564 + }
20565 +
20566 + /* switch back to previous core */
20567 + sb_setcoreidx(sbh, idx);
20568 +}
20569 +
20570 +uint32
20571 +sb_base(uint32 admatch)
20572 +{
20573 + uint32 base;
20574 + uint type;
20575 +
20576 + type = admatch & SBAM_TYPE_MASK;
20577 + ASSERT(type < 3);
20578 +
20579 + base = 0;
20580 +
20581 + if (type == 0) {
20582 + base = admatch & SBAM_BASE0_MASK;
20583 + } else if (type == 1) {
20584 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20585 + base = admatch & SBAM_BASE1_MASK;
20586 + } else if (type == 2) {
20587 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20588 + base = admatch & SBAM_BASE2_MASK;
20589 + }
20590 +
20591 + return (base);
20592 +}
20593 +
20594 +uint32
20595 +sb_size(uint32 admatch)
20596 +{
20597 + uint32 size;
20598 + uint type;
20599 +
20600 + type = admatch & SBAM_TYPE_MASK;
20601 + ASSERT(type < 3);
20602 +
20603 + size = 0;
20604 +
20605 + if (type == 0) {
20606 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
20607 + } else if (type == 1) {
20608 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20609 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
20610 + } else if (type == 2) {
20611 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20612 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
20613 + }
20614 +
20615 + return (size);
20616 +}
20617 +
20618 +/* return the core-type instantiation # of the current core */
20619 +uint
20620 +sb_coreunit(sb_t *sbh)
20621 +{
20622 + sb_info_t *si;
20623 + uint idx;
20624 + uint coreid;
20625 + uint coreunit;
20626 + uint i;
20627 +
20628 + si = SB_INFO(sbh);
20629 + coreunit = 0;
20630 +
20631 + idx = si->curidx;
20632 +
20633 + ASSERT(GOODREGS(si->curmap));
20634 + coreid = sb_coreid(sbh);
20635 +
20636 + /* count the cores of our type */
20637 + for (i = 0; i < idx; i++)
20638 + if (si->coreid[i] == coreid)
20639 + coreunit++;
20640 +
20641 + return (coreunit);
20642 +}
20643 +
20644 +static INLINE uint32
20645 +factor6(uint32 x)
20646 +{
20647 + switch (x) {
20648 + case CC_F6_2: return 2;
20649 + case CC_F6_3: return 3;
20650 + case CC_F6_4: return 4;
20651 + case CC_F6_5: return 5;
20652 + case CC_F6_6: return 6;
20653 + case CC_F6_7: return 7;
20654 + default: return 0;
20655 + }
20656 +}
20657 +
20658 +/* calculate the speed the SB would run at given a set of clockcontrol values */
20659 +uint32
20660 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
20661 +{
20662 + uint32 n1, n2, clock, m1, m2, m3, mc;
20663 +
20664 + n1 = n & CN_N1_MASK;
20665 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
20666 +
20667 + if (pll_type == PLL_TYPE6) {
20668 + if (m & CC_T6_MMASK)
20669 + return CC_T6_M1;
20670 + else
20671 + return CC_T6_M0;
20672 + } else if ((pll_type == PLL_TYPE1) ||
20673 + (pll_type == PLL_TYPE3) ||
20674 + (pll_type == PLL_TYPE4) ||
20675 + (pll_type == PLL_TYPE7)) {
20676 + n1 = factor6(n1);
20677 + n2 += CC_F5_BIAS;
20678 + } else if (pll_type == PLL_TYPE2) {
20679 + n1 += CC_T2_BIAS;
20680 + n2 += CC_T2_BIAS;
20681 + ASSERT((n1 >= 2) && (n1 <= 7));
20682 + ASSERT((n2 >= 5) && (n2 <= 23));
20683 + } else if (pll_type == PLL_TYPE5) {
20684 + return (100000000);
20685 + } else
20686 + ASSERT(0);
20687 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
20688 + if ((pll_type == PLL_TYPE3) ||
20689 + (pll_type == PLL_TYPE7)) {
20690 + clock = CC_CLOCK_BASE2 * n1 * n2;
20691 + }
20692 + else
20693 + clock = CC_CLOCK_BASE1 * n1 * n2;
20694 +
20695 + if (clock == 0)
20696 + return 0;
20697 +
20698 + m1 = m & CC_M1_MASK;
20699 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
20700 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
20701 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
20702 +
20703 + if ((pll_type == PLL_TYPE1) ||
20704 + (pll_type == PLL_TYPE3) ||
20705 + (pll_type == PLL_TYPE4) ||
20706 + (pll_type == PLL_TYPE7)) {
20707 + m1 = factor6(m1);
20708 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
20709 + m2 += CC_F5_BIAS;
20710 + else
20711 + m2 = factor6(m2);
20712 + m3 = factor6(m3);
20713 +
20714 + switch (mc) {
20715 + case CC_MC_BYPASS: return (clock);
20716 + case CC_MC_M1: return (clock / m1);
20717 + case CC_MC_M1M2: return (clock / (m1 * m2));
20718 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
20719 + case CC_MC_M1M3: return (clock / (m1 * m3));
20720 + default: return (0);
20721 + }
20722 + } else {
20723 + ASSERT(pll_type == PLL_TYPE2);
20724 +
20725 + m1 += CC_T2_BIAS;
20726 + m2 += CC_T2M2_BIAS;
20727 + m3 += CC_T2_BIAS;
20728 + ASSERT((m1 >= 2) && (m1 <= 7));
20729 + ASSERT((m2 >= 3) && (m2 <= 10));
20730 + ASSERT((m3 >= 2) && (m3 <= 7));
20731 +
20732 + if ((mc & CC_T2MC_M1BYP) == 0)
20733 + clock /= m1;
20734 + if ((mc & CC_T2MC_M2BYP) == 0)
20735 + clock /= m2;
20736 + if ((mc & CC_T2MC_M3BYP) == 0)
20737 + clock /= m3;
20738 +
20739 + return(clock);
20740 + }
20741 +}
20742 +
20743 +/* returns the current speed the SB is running at */
20744 +uint32
20745 +sb_clock(sb_t *sbh)
20746 +{
20747 + sb_info_t *si;
20748 + extifregs_t *eir;
20749 + chipcregs_t *cc;
20750 + uint32 n, m;
20751 + uint idx;
20752 + uint32 pll_type, rate;
20753 + uint intr_val = 0;
20754 +
20755 + si = SB_INFO(sbh);
20756 + idx = si->curidx;
20757 + pll_type = PLL_TYPE1;
20758 +
20759 + INTR_OFF(si, intr_val);
20760 +
20761 + /* switch to extif or chipc core */
20762 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
20763 + n = R_REG(&eir->clockcontrol_n);
20764 + m = R_REG(&eir->clockcontrol_sb);
20765 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
20766 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
20767 + n = R_REG(&cc->clockcontrol_n);
20768 + if (pll_type == PLL_TYPE6)
20769 + m = R_REG(&cc->clockcontrol_mips);
20770 + else if (pll_type == PLL_TYPE3)
20771 + {
20772 + // Added by Chen-I for 5365
20773 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
20774 + m = R_REG(&cc->clockcontrol_sb);
20775 + else
20776 + m = R_REG(&cc->clockcontrol_m2);
20777 + }
20778 + else
20779 + m = R_REG(&cc->clockcontrol_sb);
20780 + } else {
20781 + INTR_RESTORE(si, intr_val);
20782 + return 0;
20783 + }
20784 +
20785 + // Added by Chen-I for 5365
20786 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
20787 + {
20788 + rate = 100000000;
20789 + }
20790 + else
20791 + {
20792 + /* calculate rate */
20793 + rate = sb_clock_rate(pll_type, n, m);
20794 + if (pll_type == PLL_TYPE3)
20795 + rate = rate / 2;
20796 + }
20797 +
20798 + /* switch back to previous core */
20799 + sb_setcoreidx(sbh, idx);
20800 +
20801 + INTR_RESTORE(si, intr_val);
20802 +
20803 + return rate;
20804 +}
20805 +
20806 +/* change logical "focus" to the gpio core for optimized access */
20807 +void*
20808 +sb_gpiosetcore(sb_t *sbh)
20809 +{
20810 + sb_info_t *si;
20811 +
20812 + si = SB_INFO(sbh);
20813 +
20814 + return (sb_setcoreidx(sbh, si->gpioidx));
20815 +}
20816 +
20817 +/* mask&set gpiocontrol bits */
20818 +uint32
20819 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
20820 +{
20821 + sb_info_t *si;
20822 + uint regoff;
20823 +
20824 + si = SB_INFO(sbh);
20825 + regoff = 0;
20826 +
20827 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20828 +
20829 + /* gpios could be shared on router platforms */
20830 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
20831 + mask = priority ? (sb_gpioreservation & mask) :
20832 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
20833 + val &= mask;
20834 + }
20835 +
20836 + switch (si->gpioid) {
20837 + case SB_CC:
20838 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
20839 + break;
20840 +
20841 + case SB_PCI:
20842 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
20843 + break;
20844 +
20845 + case SB_EXTIF:
20846 + return (0);
20847 + }
20848 +
20849 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
20850 +}
20851 +
20852 +/* mask&set gpio output enable bits */
20853 +uint32
20854 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
20855 +{
20856 + sb_info_t *si;
20857 + uint regoff;
20858 +
20859 + si = SB_INFO(sbh);
20860 + regoff = 0;
20861 +
20862 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20863 +
20864 + /* gpios could be shared on router platforms */
20865 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
20866 + mask = priority ? (sb_gpioreservation & mask) :
20867 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
20868 + val &= mask;
20869 + }
20870 +
20871 + switch (si->gpioid) {
20872 + case SB_CC:
20873 + regoff = OFFSETOF(chipcregs_t, gpioouten);
20874 + break;
20875 +
20876 + case SB_PCI:
20877 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
20878 + break;
20879 +
20880 + case SB_EXTIF:
20881 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
20882 + break;
20883 + }
20884 +
20885 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
20886 +}
20887 +
20888 +/* mask&set gpio output bits */
20889 +uint32
20890 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
20891 +{
20892 + sb_info_t *si;
20893 + uint regoff;
20894 +
20895 + si = SB_INFO(sbh);
20896 + regoff = 0;
20897 +
20898 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20899 +
20900 + /* gpios could be shared on router platforms */
20901 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
20902 + mask = priority ? (sb_gpioreservation & mask) :
20903 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
20904 + val &= mask;
20905 + }
20906 +
20907 + switch (si->gpioid) {
20908 + case SB_CC:
20909 + regoff = OFFSETOF(chipcregs_t, gpioout);
20910 + break;
20911 +
20912 + case SB_PCI:
20913 + regoff = OFFSETOF(sbpciregs_t, gpioout);
20914 + break;
20915 +
20916 + case SB_EXTIF:
20917 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
20918 + break;
20919 + }
20920 +
20921 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
20922 +}
20923 +
20924 +/* reserve one gpio */
20925 +uint32
20926 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
20927 +{
20928 + sb_info_t *si;
20929 +
20930 + si = SB_INFO(sbh);
20931 +
20932 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20933 +
20934 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
20935 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
20936 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
20937 + return -1;
20938 + }
20939 + /* make sure only one bit is set */
20940 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
20941 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
20942 + return -1;
20943 + }
20944 +
20945 + /* already reserved */
20946 + if (sb_gpioreservation & gpio_bitmask)
20947 + return -1;
20948 + /* set reservation */
20949 + sb_gpioreservation |= gpio_bitmask;
20950 +
20951 + return sb_gpioreservation;
20952 +}
20953 +
20954 +/* release one gpio */
20955 +/*
20956 + * releasing the gpio doesn't change the current value on the GPIO last write value
20957 + * persists till some one overwrites it
20958 +*/
20959 +
20960 +uint32
20961 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
20962 +{
20963 + sb_info_t *si;
20964 +
20965 + si = SB_INFO(sbh);
20966 +
20967 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
20968 +
20969 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
20970 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
20971 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
20972 + return -1;
20973 + }
20974 + /* make sure only one bit is set */
20975 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
20976 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
20977 + return -1;
20978 + }
20979 +
20980 + /* already released */
20981 + if (!(sb_gpioreservation & gpio_bitmask))
20982 + return -1;
20983 +
20984 + /* clear reservation */
20985 + sb_gpioreservation &= ~gpio_bitmask;
20986 +
20987 + return sb_gpioreservation;
20988 +}
20989 +
20990 +/* return the current gpioin register value */
20991 +uint32
20992 +sb_gpioin(sb_t *sbh)
20993 +{
20994 + sb_info_t *si;
20995 + uint regoff;
20996 +
20997 + si = SB_INFO(sbh);
20998 + regoff = 0;
20999 +
21000 + switch (si->gpioid) {
21001 + case SB_CC:
21002 + regoff = OFFSETOF(chipcregs_t, gpioin);
21003 + break;
21004 +
21005 + case SB_PCI:
21006 + regoff = OFFSETOF(sbpciregs_t, gpioin);
21007 + break;
21008 +
21009 + case SB_EXTIF:
21010 + regoff = OFFSETOF(extifregs_t, gpioin);
21011 + break;
21012 + }
21013 +
21014 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
21015 +}
21016 +
21017 +/* mask&set gpio interrupt polarity bits */
21018 +uint32
21019 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21020 +{
21021 + sb_info_t *si;
21022 + uint regoff;
21023 +
21024 + si = SB_INFO(sbh);
21025 + regoff = 0;
21026 +
21027 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21028 +
21029 + /* gpios could be shared on router platforms */
21030 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21031 + mask = priority ? (sb_gpioreservation & mask) :
21032 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21033 + val &= mask;
21034 + }
21035 +
21036 + switch (si->gpioid) {
21037 + case SB_CC:
21038 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
21039 + break;
21040 +
21041 + case SB_PCI:
21042 + /* pci gpio implementation does not support interrupt polarity */
21043 + ASSERT(0);
21044 + break;
21045 +
21046 + case SB_EXTIF:
21047 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
21048 + break;
21049 + }
21050 +
21051 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21052 +}
21053 +
21054 +/* mask&set gpio interrupt mask bits */
21055 +uint32
21056 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21057 +{
21058 + sb_info_t *si;
21059 + uint regoff;
21060 +
21061 + si = SB_INFO(sbh);
21062 + regoff = 0;
21063 +
21064 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
21065 +
21066 + /* gpios could be shared on router platforms */
21067 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21068 + mask = priority ? (sb_gpioreservation & mask) :
21069 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21070 + val &= mask;
21071 + }
21072 +
21073 + switch (si->gpioid) {
21074 + case SB_CC:
21075 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
21076 + break;
21077 +
21078 + case SB_PCI:
21079 + /* pci gpio implementation does not support interrupt mask */
21080 + ASSERT(0);
21081 + break;
21082 +
21083 + case SB_EXTIF:
21084 + regoff = OFFSETOF(extifregs_t, gpiointmask);
21085 + break;
21086 + }
21087 +
21088 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21089 +}
21090 +
21091 +/* assign the gpio to an led */
21092 +uint32
21093 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
21094 +{
21095 + sb_info_t *si;
21096 +
21097 + si = SB_INFO(sbh);
21098 + if (si->sb.ccrev < 16)
21099 + return -1;
21100 +
21101 + /* gpio led powersave reg */
21102 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
21103 +}
21104 +
21105 +/* mask&set gpio timer val */
21106 +uint32
21107 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
21108 +{
21109 + sb_info_t *si;
21110 + si = SB_INFO(sbh);
21111 +
21112 + if (si->sb.ccrev < 16)
21113 + return -1;
21114 +
21115 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
21116 +}
21117 +
21118 +
21119 +/* return the slow clock source - LPO, XTAL, or PCI */
21120 +static uint
21121 +sb_slowclk_src(sb_info_t *si)
21122 +{
21123 + chipcregs_t *cc;
21124 +
21125 +
21126 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21127 +
21128 + if (si->sb.ccrev < 6) {
21129 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
21130 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
21131 + return (SCC_SS_PCI);
21132 + else
21133 + return (SCC_SS_XTAL);
21134 + } else if (si->sb.ccrev < 10) {
21135 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21136 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
21137 + } else /* Insta-clock */
21138 + return (SCC_SS_XTAL);
21139 +}
21140 +
21141 +/* return the ILP (slowclock) min or max frequency */
21142 +static uint
21143 +sb_slowclk_freq(sb_info_t *si, bool max)
21144 +{
21145 + chipcregs_t *cc;
21146 + uint32 slowclk;
21147 + uint div;
21148 +
21149 +
21150 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21151 +
21152 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21153 +
21154 + /* shouldn't be here unless we've established the chip has dynamic clk control */
21155 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
21156 +
21157 + slowclk = sb_slowclk_src(si);
21158 + if (si->sb.ccrev < 6) {
21159 + if (slowclk == SCC_SS_PCI)
21160 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
21161 + else
21162 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
21163 + } else if (si->sb.ccrev < 10) {
21164 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21165 + if (slowclk == SCC_SS_LPO)
21166 + return (max? LPOMAXFREQ : LPOMINFREQ);
21167 + else if (slowclk == SCC_SS_XTAL)
21168 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
21169 + else if (slowclk == SCC_SS_PCI)
21170 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
21171 + else
21172 + ASSERT(0);
21173 + } else {
21174 + /* Chipc rev 10 is InstaClock */
21175 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
21176 + div = 4 * (div + 1);
21177 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
21178 + }
21179 + return (0);
21180 +}
21181 +
21182 +static void
21183 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
21184 +{
21185 + chipcregs_t * cc;
21186 + uint slowmaxfreq, pll_delay, slowclk;
21187 + uint pll_on_delay, fref_sel_delay;
21188 +
21189 + pll_delay = PLL_DELAY;
21190 +
21191 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
21192 + * since the xtal will also be powered down by dynamic clk control logic.
21193 + */
21194 + slowclk = sb_slowclk_src(si);
21195 + if (slowclk != SCC_SS_XTAL)
21196 + pll_delay += XTAL_ON_DELAY;
21197 +
21198 + /* Starting with 4318 it is ILP that is used for the delays */
21199 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
21200 +
21201 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
21202 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
21203 +
21204 + cc = (chipcregs_t *)chipcregs;
21205 + W_REG(&cc->pll_on_delay, pll_on_delay);
21206 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
21207 +}
21208 +
21209 +int
21210 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
21211 +{
21212 + sb_info_t *si;
21213 + uint origidx;
21214 + chipcregs_t *cc;
21215 + uint intr_val = 0;
21216 + uint err = 0;
21217 +
21218 + si = SB_INFO(sbh);
21219 +
21220 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
21221 + if (si->sb.ccrev < 6)
21222 + return 1;
21223 +
21224 + /* chipcommon cores rev10 are a whole new ball game */
21225 + if (si->sb.ccrev >= 10)
21226 + return 1;
21227 +
21228 + if (set && ((*div % 4) || (*div < 4)))
21229 + return 2;
21230 +
21231 + INTR_OFF(si, intr_val);
21232 + origidx = si->curidx;
21233 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21234 + ASSERT(cc != NULL);
21235 +
21236 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
21237 + err = 3;
21238 + goto done;
21239 + }
21240 +
21241 + if (set) {
21242 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
21243 + sb_clkctl_setdelay(sbh, (void *)cc);
21244 + } else
21245 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21246 +
21247 +done:
21248 + sb_setcoreidx(sbh, origidx);
21249 + INTR_RESTORE(si, intr_val);
21250 + return err;
21251 +}
21252 +
21253 +/* initialize power control delay registers */
21254 +void sb_clkctl_init(sb_t *sbh)
21255 +{
21256 + sb_info_t *si;
21257 + uint origidx;
21258 + chipcregs_t *cc;
21259 +
21260 + si = SB_INFO(sbh);
21261 +
21262 + origidx = si->curidx;
21263 +
21264 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21265 + return;
21266 +
21267 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21268 + goto done;
21269 +
21270 + /* 4317pc does not work with SlowClock less than 5 MHz */
21271 + if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
21272 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
21273 +
21274 + /* set all Instaclk chip ILP to 1 MHz */
21275 + else if (si->sb.ccrev >= 10)
21276 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
21277 +
21278 + sb_clkctl_setdelay(si, (void *)cc);
21279 +
21280 +done:
21281 + sb_setcoreidx(sbh, origidx);
21282 +}
21283 +void sb_pwrctl_init(sb_t *sbh)
21284 +{
21285 +sb_clkctl_init(sbh);
21286 +}
21287 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
21288 +uint16
21289 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
21290 +{
21291 + sb_info_t *si;
21292 + uint origidx;
21293 + chipcregs_t *cc;
21294 + uint slowminfreq;
21295 + uint16 fpdelay;
21296 + uint intr_val = 0;
21297 +
21298 + si = SB_INFO(sbh);
21299 + fpdelay = 0;
21300 + origidx = si->curidx;
21301 +
21302 + INTR_OFF(si, intr_val);
21303 +
21304 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21305 + goto done;
21306 +
21307 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21308 + goto done;
21309 +
21310 + slowminfreq = sb_slowclk_freq(si, FALSE);
21311 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
21312 +
21313 +done:
21314 + sb_setcoreidx(sbh, origidx);
21315 + INTR_RESTORE(si, intr_val);
21316 + return (fpdelay);
21317 +}
21318 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
21319 +{
21320 +return sb_clkctl_fast_pwrup_delay(sbh);
21321 +}
21322 +/* turn primary xtal and/or pll off/on */
21323 +int
21324 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
21325 +{
21326 + sb_info_t *si;
21327 + uint32 in, out, outen;
21328 +
21329 + si = SB_INFO(sbh);
21330 +
21331 + switch (BUSTYPE(si->sb.bustype)) {
21332 +
21333 +
21334 + case PCMCIA_BUS:
21335 + return (0);
21336 +
21337 +
21338 + case PCI_BUS:
21339 +
21340 + /* pcie core doesn't have any mapping to control the xtal pu */
21341 + if (PCIE(si))
21342 + return -1;
21343 +
21344 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
21345 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
21346 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
21347 +
21348 + /*
21349 + * Avoid glitching the clock if GPRS is already using it.
21350 + * We can't actually read the state of the PLLPD so we infer it
21351 + * by the value of XTAL_PU which *is* readable via gpioin.
21352 + */
21353 + if (on && (in & PCI_CFG_GPIO_XTAL))
21354 + return (0);
21355 +
21356 + if (what & XTAL)
21357 + outen |= PCI_CFG_GPIO_XTAL;
21358 + if (what & PLL)
21359 + outen |= PCI_CFG_GPIO_PLL;
21360 +
21361 + if (on) {
21362 + /* turn primary xtal on */
21363 + if (what & XTAL) {
21364 + out |= PCI_CFG_GPIO_XTAL;
21365 + if (what & PLL)
21366 + out |= PCI_CFG_GPIO_PLL;
21367 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21368 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21369 + OSL_DELAY(XTAL_ON_DELAY);
21370 + }
21371 +
21372 + /* turn pll on */
21373 + if (what & PLL) {
21374 + out &= ~PCI_CFG_GPIO_PLL;
21375 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21376 + OSL_DELAY(2000);
21377 + }
21378 + } else {
21379 + if (what & XTAL)
21380 + out &= ~PCI_CFG_GPIO_XTAL;
21381 + if (what & PLL)
21382 + out |= PCI_CFG_GPIO_PLL;
21383 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21384 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21385 + }
21386 +
21387 + default:
21388 + return (-1);
21389 + }
21390 +
21391 + return (0);
21392 +}
21393 +
21394 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
21395 +{
21396 +return sb_clkctl_xtal(sbh,what,on);
21397 +}
21398 +
21399 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
21400 +/* returns true if ignore pll off is set and false if it is not */
21401 +bool
21402 +sb_clkctl_clk(sb_t *sbh, uint mode)
21403 +{
21404 + sb_info_t *si;
21405 + uint origidx;
21406 + chipcregs_t *cc;
21407 + uint32 scc;
21408 + bool forcefastclk=FALSE;
21409 + uint intr_val = 0;
21410 +
21411 + si = SB_INFO(sbh);
21412 +
21413 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
21414 + if (si->sb.ccrev < 6)
21415 + return (FALSE);
21416 +
21417 + /* chipcommon cores rev10 are a whole new ball game */
21418 + if (si->sb.ccrev >= 10)
21419 + return (FALSE);
21420 +
21421 + INTR_OFF(si, intr_val);
21422 +
21423 + origidx = si->curidx;
21424 +
21425 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21426 + ASSERT(cc != NULL);
21427 +
21428 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21429 + goto done;
21430 +
21431 + switch (mode) {
21432 + case CLK_FAST: /* force fast (pll) clock */
21433 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
21434 + sb_clkctl_xtal(&si->sb, XTAL, ON);
21435 +
21436 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
21437 + break;
21438 +
21439 + case CLK_DYNAMIC: /* enable dynamic clock control */
21440 + scc = R_REG(&cc->slow_clk_ctl);
21441 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
21442 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
21443 + scc |= SCC_XC;
21444 + W_REG(&cc->slow_clk_ctl, scc);
21445 +
21446 + /* for dynamic control, we have to release our xtal_pu "force on" */
21447 + if (scc & SCC_XC)
21448 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
21449 + break;
21450 +
21451 + default:
21452 + ASSERT(0);
21453 + }
21454 +
21455 + /* Is the h/w forcing the use of the fast clk */
21456 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
21457 +
21458 +done:
21459 + sb_setcoreidx(sbh, origidx);
21460 + INTR_RESTORE(si, intr_val);
21461 + return (forcefastclk);
21462 +}
21463 +
21464 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
21465 +{
21466 +return sb_clkctl_clk(sbh, mode);
21467 +}
21468 +/* register driver interrupt disabling and restoring callback functions */
21469 +void
21470 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
21471 +{
21472 + sb_info_t *si;
21473 +
21474 + si = SB_INFO(sbh);
21475 + si->intr_arg = intr_arg;
21476 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
21477 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
21478 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
21479 + /* save current core id. when this function called, the current core
21480 + * must be the core which provides driver functions(il, et, wl, etc.)
21481 + */
21482 + si->dev_coreid = si->coreid[si->curidx];
21483 +}
21484 +
21485 +
21486 +void
21487 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
21488 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
21489 +{
21490 + uint vendor, core, unit;
21491 + uint chip, chippkg;
21492 + char varname[8];
21493 + uint8 class, subclass, progif;
21494 +
21495 + vendor = sb_corevendor(sbh);
21496 + core = sb_coreid(sbh);
21497 + unit = sb_coreunit(sbh);
21498 +
21499 + chip = BCMINIT(sb_chip)(sbh);
21500 + chippkg = BCMINIT(sb_chippkg)(sbh);
21501 +
21502 + progif = 0;
21503 +
21504 + /* Known vendor translations */
21505 + switch (vendor) {
21506 + case SB_VEND_BCM:
21507 + vendor = VENDOR_BROADCOM;
21508 + break;
21509 + }
21510 +
21511 + /* Determine class based on known core codes */
21512 + switch (core) {
21513 + case SB_ILINE20:
21514 + class = PCI_CLASS_NET;
21515 + subclass = PCI_NET_ETHER;
21516 + core = BCM47XX_ILINE_ID;
21517 + break;
21518 + case SB_ENET:
21519 + class = PCI_CLASS_NET;
21520 + subclass = PCI_NET_ETHER;
21521 + core = BCM47XX_ENET_ID;
21522 + break;
21523 + case SB_SDRAM:
21524 + case SB_MEMC:
21525 + class = PCI_CLASS_MEMORY;
21526 + subclass = PCI_MEMORY_RAM;
21527 + break;
21528 + case SB_PCI:
21529 + case SB_PCIE:
21530 + class = PCI_CLASS_BRIDGE;
21531 + subclass = PCI_BRIDGE_PCI;
21532 + break;
21533 + case SB_MIPS:
21534 + case SB_MIPS33:
21535 + class = PCI_CLASS_CPU;
21536 + subclass = PCI_CPU_MIPS;
21537 + break;
21538 + case SB_CODEC:
21539 + class = PCI_CLASS_COMM;
21540 + subclass = PCI_COMM_MODEM;
21541 + core = BCM47XX_V90_ID;
21542 + break;
21543 + case SB_USB:
21544 + class = PCI_CLASS_SERIAL;
21545 + subclass = PCI_SERIAL_USB;
21546 + progif = 0x10; /* OHCI */
21547 + core = BCM47XX_USB_ID;
21548 + break;
21549 + case SB_USB11H:
21550 + class = PCI_CLASS_SERIAL;
21551 + subclass = PCI_SERIAL_USB;
21552 + progif = 0x10; /* OHCI */
21553 + core = BCM47XX_USBH_ID;
21554 + break;
21555 + case SB_USB11D:
21556 + class = PCI_CLASS_SERIAL;
21557 + subclass = PCI_SERIAL_USB;
21558 + core = BCM47XX_USBD_ID;
21559 + break;
21560 + case SB_IPSEC:
21561 + class = PCI_CLASS_CRYPT;
21562 + subclass = PCI_CRYPT_NETWORK;
21563 + core = BCM47XX_IPSEC_ID;
21564 + break;
21565 + case SB_ROBO:
21566 + class = PCI_CLASS_NET;
21567 + subclass = PCI_NET_OTHER;
21568 + core = BCM47XX_ROBO_ID;
21569 + break;
21570 + case SB_EXTIF:
21571 + case SB_CC:
21572 + class = PCI_CLASS_MEMORY;
21573 + subclass = PCI_MEMORY_FLASH;
21574 + break;
21575 + case SB_D11:
21576 + class = PCI_CLASS_NET;
21577 + subclass = PCI_NET_OTHER;
21578 + /* Let an nvram variable override this */
21579 + sprintf(varname, "wl%did", unit);
21580 + if ((core = getintvar(NULL, varname)) == 0) {
21581 + if (chip == BCM4712_DEVICE_ID) {
21582 + if (chippkg == BCM4712SMALL_PKG_ID)
21583 + core = BCM4306_D11G_ID;
21584 + else
21585 + core = BCM4306_D11DUAL_ID;
21586 + }
21587 + }
21588 + break;
21589 +
21590 + default:
21591 + class = subclass = progif = 0xff;
21592 + break;
21593 + }
21594 +
21595 + *pcivendor = (uint16)vendor;
21596 + *pcidevice = (uint16)core;
21597 + *pciclass = class;
21598 + *pcisubclass = subclass;
21599 + *pciprogif = progif;
21600 +}
21601 +
21602 +
21603 +
21604 +
21605 +/* use the mdio interface to write to mdio slaves */
21606 +static int
21607 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
21608 +{
21609 + uint mdiodata;
21610 + uint i = 0;
21611 + sbpcieregs_t *pcieregs;
21612 +
21613 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
21614 + ASSERT (pcieregs);
21615 +
21616 + /* enable mdio access to SERDES */
21617 + W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
21618 +
21619 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
21620 + (physmedia << MDIODATA_DEVADDR_SHF) |
21621 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
21622 +
21623 + W_REG((&pcieregs->mdiodata), mdiodata);
21624 +
21625 + PR28829_DELAY();
21626 +
21627 + /* retry till the transaction is complete */
21628 + while ( i < 10 ) {
21629 + if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
21630 + /* Disable mdio access to SERDES */
21631 + W_REG((&pcieregs->mdiocontrol), 0);
21632 + return 0;
21633 + }
21634 + OSL_DELAY(1000);
21635 + i++;
21636 + }
21637 +
21638 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
21639 + /* Disable mdio access to SERDES */
21640 + W_REG((&pcieregs->mdiocontrol), 0);
21641 + ASSERT(0);
21642 + return 1;
21643 +
21644 +}
21645 +
21646 +/* indirect way to read pcie config regs*/
21647 +uint
21648 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
21649 +{
21650 + sb_info_t *si;
21651 + sb_t *sbh;
21652 + uint retval = 0xFFFFFFFF;
21653 + sbpcieregs_t *pcieregs;
21654 + uint addrtype;
21655 +
21656 + sbh = (sb_t *)sb;
21657 + si = SB_INFO(sbh);
21658 + ASSERT (PCIE(si));
21659 +
21660 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21661 + ASSERT (pcieregs);
21662 +
21663 + addrtype = (uint)((uintptr)arg1);
21664 + switch(addrtype) {
21665 + case PCIE_CONFIGREGS:
21666 + W_REG((&pcieregs->configaddr),offset);
21667 + retval = R_REG(&(pcieregs->configdata));
21668 + break;
21669 + case PCIE_PCIEREGS:
21670 + W_REG(&(pcieregs->pcieaddr),offset);
21671 + retval = R_REG(&(pcieregs->pciedata));
21672 + break;
21673 + default:
21674 + ASSERT(0);
21675 + break;
21676 + }
21677 + return retval;
21678 +}
21679 +
21680 +/* indirect way to write pcie config/mdio/pciecore regs*/
21681 +uint
21682 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
21683 +{
21684 + sb_info_t *si;
21685 + sbpcieregs_t *pcieregs;
21686 + uint addrtype;
21687 +
21688 + si = SB_INFO(sbh);
21689 + ASSERT (PCIE(si));
21690 +
21691 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21692 + ASSERT (pcieregs);
21693 +
21694 + addrtype = (uint)((uintptr)arg1);
21695 +
21696 + switch(addrtype) {
21697 + case PCIE_CONFIGREGS:
21698 + W_REG((&pcieregs->configaddr),offset);
21699 + W_REG((&pcieregs->configdata),val);
21700 + break;
21701 + case PCIE_PCIEREGS:
21702 + W_REG((&pcieregs->pcieaddr),offset);
21703 + W_REG((&pcieregs->pciedata),val);
21704 + break;
21705 + default:
21706 + ASSERT(0);
21707 + break;
21708 + }
21709 + return 0;
21710 +}
21711 +
21712 +
21713 +/* Build device path. Support SB, PCI, and JTAG for now. */
21714 +int
21715 +sb_devpath(sb_t *sbh, char *path, int size)
21716 +{
21717 + ASSERT(path);
21718 + ASSERT(size >= SB_DEVPATH_BUFSZ);
21719 +
21720 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
21721 + case SB_BUS:
21722 + case JTAG_BUS:
21723 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
21724 + break;
21725 + case PCI_BUS:
21726 + ASSERT((SB_INFO(sbh))->osh);
21727 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
21728 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
21729 + break;
21730 + case PCMCIA_BUS:
21731 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
21732 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
21733 + sprintf(path, "pc/%u/%u/", 1, 1);
21734 + break;
21735 + case SDIO_BUS:
21736 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
21737 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
21738 + break;
21739 + default:
21740 + ASSERT(0);
21741 + break;
21742 + }
21743 +
21744 + return 0;
21745 +}
21746 +
21747 +/* Fix chip's configuration. The current core may be changed upon return */
21748 +static int
21749 +sb_pci_fixcfg(sb_info_t *si)
21750 +{
21751 + uint origidx, pciidx;
21752 + sbpciregs_t *pciregs;
21753 + sbpcieregs_t *pcieregs;
21754 + uint16 val16, *reg16;
21755 + char name[SB_DEVPATH_BUFSZ+16], *value;
21756 + char devpath[SB_DEVPATH_BUFSZ];
21757 +
21758 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
21759 +
21760 + /* Fix PCI(e) SROM shadow area */
21761 + /* save the current index */
21762 + origidx = sb_coreidx(&si->sb);
21763 +
21764 + /* check 'pi' is correct and fix it if not */
21765 + if (si->sb.buscoretype == SB_PCIE) {
21766 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
21767 + ASSERT(pcieregs);
21768 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
21769 + }
21770 + else if (si->sb.buscoretype == SB_PCI) {
21771 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
21772 + ASSERT(pciregs);
21773 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
21774 + }
21775 + else {
21776 + ASSERT(0);
21777 + return -1;
21778 + }
21779 + pciidx = sb_coreidx(&si->sb);
21780 + val16 = R_REG(reg16);
21781 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
21782 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
21783 + W_REG(reg16, val16);
21784 + }
21785 +
21786 + /* restore the original index */
21787 + sb_setcoreidx(&si->sb, origidx);
21788 +
21789 + /* Fix bar0window */
21790 + /* !do it last, it changes the current core! */
21791 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
21792 + return -1;
21793 + sprintf(name, "%sb0w", devpath);
21794 + if ((value = getvar(NULL, name))) {
21795 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
21796 + bcm_strtoul(value, NULL, 16));
21797 + /* update curidx since the current core is changed */
21798 + si->curidx = _sb_coreidx(si);
21799 + if (si->curidx == BADIDX) {
21800 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
21801 + return -1;
21802 + }
21803 + }
21804 +
21805 + return 0;
21806 +}
21807 +
21808 diff -Nur linux-2.4.32/drivers/net/hnd/shared_ksyms.sh linux-2.4.32-brcm/drivers/net/hnd/shared_ksyms.sh
21809 --- linux-2.4.32/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
21810 +++ linux-2.4.32-brcm/drivers/net/hnd/shared_ksyms.sh 2005-12-16 23:39:11.316860000 +0100
21811 @@ -0,0 +1,21 @@
21812 +#!/bin/sh
21813 +#
21814 +# Copyright 2004, Broadcom Corporation
21815 +# All Rights Reserved.
21816 +#
21817 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21818 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21819 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21820 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21821 +#
21822 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
21823 +#
21824 +
21825 +cat <<EOF
21826 +#include <linux/config.h>
21827 +#include <linux/module.h>
21828 +EOF
21829 +
21830 +for file in $* ; do
21831 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
21832 +done
21833 diff -Nur linux-2.4.32/drivers/net/Makefile linux-2.4.32-brcm/drivers/net/Makefile
21834 --- linux-2.4.32/drivers/net/Makefile 2005-01-19 15:09:56.000000000 +0100
21835 +++ linux-2.4.32-brcm/drivers/net/Makefile 2005-12-16 23:39:11.284858000 +0100
21836 @@ -3,6 +3,8 @@
21837 # Makefile for the Linux network (ethercard) device drivers.
21838 #
21839
21840 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
21841 +
21842 obj-y :=
21843 obj-m :=
21844 obj-n :=
21845 @@ -39,6 +41,8 @@
21846 obj-$(CONFIG_ISDN) += slhc.o
21847 endif
21848
21849 +subdir-$(CONFIG_HND) += hnd
21850 +subdir-$(CONFIG_WL) += wl
21851 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
21852 subdir-$(CONFIG_NET_WIRELESS) += wireless
21853 subdir-$(CONFIG_TULIP) += tulip
21854 @@ -69,6 +74,13 @@
21855 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
21856 obj-$(CONFIG_SUNGEM) += sungem.o
21857
21858 +ifeq ($(CONFIG_HND),y)
21859 + obj-y += hnd/hnd.o
21860 +endif
21861 +ifeq ($(CONFIG_WL),y)
21862 + obj-y += wl/wl.o
21863 +endif
21864 +
21865 obj-$(CONFIG_MACE) += mace.o
21866 obj-$(CONFIG_BMAC) += bmac.o
21867 obj-$(CONFIG_GMAC) += gmac.o
21868 diff -Nur linux-2.4.32/drivers/net/wireless/Config.in linux-2.4.32-brcm/drivers/net/wireless/Config.in
21869 --- linux-2.4.32/drivers/net/wireless/Config.in 2004-11-17 12:54:21.000000000 +0100
21870 +++ linux-2.4.32-brcm/drivers/net/wireless/Config.in 2005-12-16 23:39:11.364863000 +0100
21871 @@ -13,6 +13,7 @@
21872 fi
21873
21874 if [ "$CONFIG_PCI" = "y" ]; then
21875 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
21876 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21877 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21878 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
21879 diff -Nur linux-2.4.32/drivers/net/wl/Makefile linux-2.4.32-brcm/drivers/net/wl/Makefile
21880 --- linux-2.4.32/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
21881 +++ linux-2.4.32-brcm/drivers/net/wl/Makefile 2005-12-16 23:39:11.364863000 +0100
21882 @@ -0,0 +1,26 @@
21883 +#
21884 +# Makefile for the Broadcom wl driver
21885 +#
21886 +# Copyright 2004, Broadcom Corporation
21887 +# All Rights Reserved.
21888 +#
21889 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
21890 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
21891 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21892 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
21893 +#
21894 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
21895 +
21896 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
21897 +
21898 +O_TARGET := wl.o
21899 +
21900 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
21901 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
21902 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
21903 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
21904 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
21905 +
21906 +obj-m := $(O_TARGET)
21907 +
21908 +include $(TOPDIR)/Rules.make
21909 diff -Nur linux-2.4.32/drivers/parport/Config.in linux-2.4.32-brcm/drivers/parport/Config.in
21910 --- linux-2.4.32/drivers/parport/Config.in 2004-02-18 14:36:31.000000000 +0100
21911 +++ linux-2.4.32-brcm/drivers/parport/Config.in 2005-12-16 23:39:11.364863000 +0100
21912 @@ -11,6 +11,7 @@
21913 tristate 'Parallel port support' CONFIG_PARPORT
21914 if [ "$CONFIG_PARPORT" != "n" ]; then
21915 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
21916 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
21917 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
21918 if [ "$CONFIG_SERIAL" = "m" ]; then
21919 define_tristate CONFIG_PARPORT_PC_CML1 m
21920 diff -Nur linux-2.4.32/drivers/parport/Makefile linux-2.4.32-brcm/drivers/parport/Makefile
21921 --- linux-2.4.32/drivers/parport/Makefile 2004-08-08 01:26:05.000000000 +0200
21922 +++ linux-2.4.32-brcm/drivers/parport/Makefile 2005-12-16 23:39:11.364863000 +0100
21923 @@ -22,6 +22,7 @@
21924
21925 obj-$(CONFIG_PARPORT) += parport.o
21926 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
21927 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
21928 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
21929 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
21930 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
21931 diff -Nur linux-2.4.32/drivers/parport/parport_splink.c linux-2.4.32-brcm/drivers/parport/parport_splink.c
21932 --- linux-2.4.32/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
21933 +++ linux-2.4.32-brcm/drivers/parport/parport_splink.c 2005-12-16 23:39:11.364863000 +0100
21934 @@ -0,0 +1,345 @@
21935 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
21936 + *
21937 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
21938 + * Based on parport_pc source
21939 + */
21940 +
21941 +#include <linux/config.h>
21942 +#include <linux/module.h>
21943 +#include <linux/init.h>
21944 +#include <linux/ioport.h>
21945 +#include <linux/kernel.h>
21946 +#include <linux/slab.h>
21947 +#include <linux/parport.h>
21948 +#include <linux/parport_pc.h>
21949 +
21950 +#define SPLINK_ADDRESS 0xBF800010
21951 +
21952 +#undef DEBUG
21953 +
21954 +#ifdef DEBUG
21955 +#define DPRINTK printk
21956 +#else
21957 +#define DPRINTK(stuff...)
21958 +#endif
21959 +
21960 +
21961 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
21962 + * it doesn't do any extra masking. */
21963 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
21964 + unsigned char mask,
21965 + unsigned char val)
21966 +{
21967 + struct parport_pc_private *priv = p->physport->private_data;
21968 + unsigned char *io = (unsigned char *) p->base;
21969 + unsigned char ctr = priv->ctr;
21970 +#ifdef DEBUG_PARPORT
21971 + printk (KERN_DEBUG
21972 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
21973 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
21974 +#endif
21975 + ctr = (ctr & ~mask) ^ val;
21976 + ctr &= priv->ctr_writable; /* only write writable bits. */
21977 + *(io+2) = ctr;
21978 + priv->ctr = ctr; /* Update soft copy */
21979 + return ctr;
21980 +}
21981 +
21982 +
21983 +
21984 +static void parport_splink_data_forward (struct parport *p)
21985 +{
21986 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
21987 + __parport_splink_frob_control (p, 0x20, 0);
21988 +}
21989 +
21990 +static void parport_splink_data_reverse (struct parport *p)
21991 +{
21992 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
21993 + __parport_splink_frob_control (p, 0x20, 0x20);
21994 +}
21995 +
21996 +/*
21997 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
21998 +{
21999 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
22000 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
22001 +}
22002 +*/
22003 +
22004 +static void parport_splink_enable_irq(struct parport *p)
22005 +{
22006 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
22007 + __parport_splink_frob_control (p, 0x10, 0x10);
22008 +}
22009 +
22010 +static void parport_splink_disable_irq(struct parport *p)
22011 +{
22012 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
22013 + __parport_splink_frob_control (p, 0x10, 0);
22014 +}
22015 +
22016 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
22017 +{
22018 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
22019 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
22020 + if (dev->irq_func &&
22021 + dev->port->irq != PARPORT_IRQ_NONE)
22022 + /* Set ackIntEn */
22023 + s->u.pc.ctr |= 0x10;
22024 +}
22025 +
22026 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
22027 +{
22028 + const struct parport_pc_private *priv = p->physport->private_data;
22029 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
22030 + s->u.pc.ctr = priv->ctr;
22031 +}
22032 +
22033 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
22034 +{
22035 + struct parport_pc_private *priv = p->physport->private_data;
22036 + unsigned char *io = (unsigned char *) p->base;
22037 + unsigned char ctr = s->u.pc.ctr;
22038 +
22039 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
22040 + *(io+2) = ctr;
22041 + priv->ctr = ctr;
22042 +}
22043 +
22044 +static void parport_splink_setup_interrupt(void) {
22045 + return;
22046 +}
22047 +
22048 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
22049 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
22050 + unsigned char *io = (unsigned char *) p->base;
22051 + *io = d;
22052 +}
22053 +
22054 +static unsigned char parport_splink_read_data(struct parport *p) {
22055 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
22056 + unsigned char *io = (unsigned char *) p->base;
22057 + return *io;
22058 +}
22059 +
22060 +static void parport_splink_write_control(struct parport *p, unsigned char d)
22061 +{
22062 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22063 + PARPORT_CONTROL_AUTOFD |
22064 + PARPORT_CONTROL_INIT |
22065 + PARPORT_CONTROL_SELECT);
22066 +
22067 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
22068 + /* Take this out when drivers have adapted to the newer interface. */
22069 + if (d & 0x20) {
22070 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
22071 + p->name, p->cad->name);
22072 + parport_splink_data_reverse (p);
22073 + }
22074 +
22075 + __parport_splink_frob_control (p, wm, d & wm);
22076 +}
22077 +
22078 +static unsigned char parport_splink_read_control(struct parport *p)
22079 +{
22080 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22081 + PARPORT_CONTROL_AUTOFD |
22082 + PARPORT_CONTROL_INIT |
22083 + PARPORT_CONTROL_SELECT);
22084 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
22085 + const struct parport_pc_private *priv = p->physport->private_data;
22086 + return priv->ctr & wm; /* Use soft copy */
22087 +}
22088 +
22089 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
22090 + unsigned char val)
22091 +{
22092 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22093 + PARPORT_CONTROL_AUTOFD |
22094 + PARPORT_CONTROL_INIT |
22095 + PARPORT_CONTROL_SELECT);
22096 +
22097 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
22098 + /* Take this out when drivers have adapted to the newer interface. */
22099 + if (mask & 0x20) {
22100 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
22101 + p->name, p->cad->name,
22102 + (val & 0x20) ? "reverse" : "forward");
22103 + if (val & 0x20)
22104 + parport_splink_data_reverse (p);
22105 + else
22106 + parport_splink_data_forward (p);
22107 + }
22108 +
22109 + /* Restrict mask and val to control lines. */
22110 + mask &= wm;
22111 + val &= wm;
22112 +
22113 + return __parport_splink_frob_control (p, mask, val);
22114 +}
22115 +
22116 +static unsigned char parport_splink_read_status(struct parport *p)
22117 +{
22118 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
22119 + unsigned char *io = (unsigned char *) p->base;
22120 + return *(io+1);
22121 +}
22122 +
22123 +static void parport_splink_inc_use_count(void)
22124 +{
22125 +#ifdef MODULE
22126 + MOD_INC_USE_COUNT;
22127 +#endif
22128 +}
22129 +
22130 +static void parport_splink_dec_use_count(void)
22131 +{
22132 +#ifdef MODULE
22133 + MOD_DEC_USE_COUNT;
22134 +#endif
22135 +}
22136 +
22137 +static struct parport_operations parport_splink_ops =
22138 +{
22139 + parport_splink_write_data,
22140 + parport_splink_read_data,
22141 +
22142 + parport_splink_write_control,
22143 + parport_splink_read_control,
22144 + parport_splink_frob_control,
22145 +
22146 + parport_splink_read_status,
22147 +
22148 + parport_splink_enable_irq,
22149 + parport_splink_disable_irq,
22150 +
22151 + parport_splink_data_forward,
22152 + parport_splink_data_reverse,
22153 +
22154 + parport_splink_init_state,
22155 + parport_splink_save_state,
22156 + parport_splink_restore_state,
22157 +
22158 + parport_splink_inc_use_count,
22159 + parport_splink_dec_use_count,
22160 +
22161 + parport_ieee1284_epp_write_data,
22162 + parport_ieee1284_epp_read_data,
22163 + parport_ieee1284_epp_write_addr,
22164 + parport_ieee1284_epp_read_addr,
22165 +
22166 + parport_ieee1284_ecp_write_data,
22167 + parport_ieee1284_ecp_read_data,
22168 + parport_ieee1284_ecp_write_addr,
22169 +
22170 + parport_ieee1284_write_compat,
22171 + parport_ieee1284_read_nibble,
22172 + parport_ieee1284_read_byte,
22173 +};
22174 +
22175 +/* --- Initialisation code -------------------------------- */
22176 +
22177 +static struct parport *parport_splink_probe_port (unsigned long int base)
22178 +{
22179 + struct parport_pc_private *priv;
22180 + struct parport_operations *ops;
22181 + struct parport *p;
22182 +
22183 + if (check_mem_region(base, 3)) {
22184 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
22185 + return NULL;
22186 + }
22187 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
22188 + if (!priv) {
22189 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
22190 + return NULL;
22191 + }
22192 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
22193 + if (!ops) {
22194 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
22195 + base);
22196 + kfree (priv);
22197 + return NULL;
22198 + }
22199 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
22200 + priv->ctr = 0xc;
22201 + priv->ctr_writable = 0xff;
22202 +
22203 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
22204 + PARPORT_DMA_NONE, ops))) {
22205 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
22206 + base);
22207 + kfree (priv);
22208 + kfree (ops);
22209 + return NULL;
22210 + }
22211 +
22212 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
22213 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
22214 + p->private_data = priv;
22215 +
22216 + parport_proc_register(p);
22217 + request_mem_region (p->base, 3, p->name);
22218 +
22219 + /* Done probing. Now put the port into a sensible start-up state. */
22220 + parport_splink_write_data(p, 0);
22221 + parport_splink_data_forward (p);
22222 +
22223 + /* Now that we've told the sharing engine about the port, and
22224 + found out its characteristics, let the high-level drivers
22225 + know about it. */
22226 + parport_announce_port (p);
22227 +
22228 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
22229 + base);
22230 + return p;
22231 +}
22232 +
22233 +static void parport_splink_unregister_port(struct parport *p) {
22234 + struct parport_pc_private *priv = p->private_data;
22235 + struct parport_operations *ops = p->ops;
22236 +
22237 + if (p->irq != PARPORT_IRQ_NONE)
22238 + free_irq(p->irq, p);
22239 + release_mem_region(p->base, 3);
22240 + parport_proc_unregister(p);
22241 + kfree (priv);
22242 + parport_unregister_port(p);
22243 + kfree (ops);
22244 +}
22245 +
22246 +
22247 +int parport_splink_init(void)
22248 +{
22249 + int ret;
22250 +
22251 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
22252 + parport_splink_setup_interrupt();
22253 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
22254 +
22255 + return ret;
22256 +}
22257 +
22258 +void parport_splink_cleanup(void) {
22259 + struct parport *p = parport_enumerate(), *tmp;
22260 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
22261 + if (p->size) {
22262 + if (p->modes & PARPORT_MODE_PCSPP) {
22263 + while(p) {
22264 + tmp = p->next;
22265 + parport_splink_unregister_port(p);
22266 + p = tmp;
22267 + }
22268 + }
22269 + }
22270 +}
22271 +
22272 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
22273 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
22274 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
22275 +MODULE_LICENSE("GPL");
22276 +
22277 +module_init(parport_splink_init)
22278 +module_exit(parport_splink_cleanup)
22279 +
22280 diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710_generic.c linux-2.4.32-brcm/drivers/pcmcia/bcm4710_generic.c
22281 --- linux-2.4.32/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
22282 +++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710_generic.c 2005-12-16 23:39:11.368863250 +0100
22283 @@ -0,0 +1,912 @@
22284 +/*
22285 + *
22286 + * bcm47xx pcmcia driver
22287 + *
22288 + * Copyright 2004, Broadcom Corporation
22289 + * All Rights Reserved.
22290 + *
22291 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22292 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22293 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22294 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22295 + *
22296 + * Based on sa1100_generic.c from www.handhelds.org,
22297 + * and au1000_generic.c from oss.sgi.com.
22298 + *
22299 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
22300 + */
22301 +#include <linux/module.h>
22302 +#include <linux/init.h>
22303 +#include <linux/config.h>
22304 +#include <linux/delay.h>
22305 +#include <linux/ioport.h>
22306 +#include <linux/kernel.h>
22307 +#include <linux/tqueue.h>
22308 +#include <linux/timer.h>
22309 +#include <linux/mm.h>
22310 +#include <linux/proc_fs.h>
22311 +#include <linux/version.h>
22312 +#include <linux/types.h>
22313 +#include <linux/vmalloc.h>
22314 +
22315 +#include <pcmcia/version.h>
22316 +#include <pcmcia/cs_types.h>
22317 +#include <pcmcia/cs.h>
22318 +#include <pcmcia/ss.h>
22319 +#include <pcmcia/bulkmem.h>
22320 +#include <pcmcia/cistpl.h>
22321 +#include <pcmcia/bus_ops.h>
22322 +#include "cs_internal.h"
22323 +
22324 +#include <asm/io.h>
22325 +#include <asm/irq.h>
22326 +#include <asm/system.h>
22327 +
22328 +#include <typedefs.h>
22329 +#include <bcm4710.h>
22330 +#include <sbextif.h>
22331 +
22332 +#include "bcm4710pcmcia.h"
22333 +
22334 +#ifdef PCMCIA_DEBUG
22335 +static int pc_debug = PCMCIA_DEBUG;
22336 +#endif
22337 +
22338 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
22339 +
22340 +/* This structure maintains housekeeping state for each socket, such
22341 + * as the last known values of the card detect pins, or the Card Services
22342 + * callback value associated with the socket:
22343 + */
22344 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
22345 +static int socket_count;
22346 +
22347 +
22348 +/* Returned by the low-level PCMCIA interface: */
22349 +static struct pcmcia_low_level *pcmcia_low_level;
22350 +
22351 +/* Event poll timer structure */
22352 +static struct timer_list poll_timer;
22353 +
22354 +
22355 +/* Prototypes for routines which are used internally: */
22356 +
22357 +static int bcm47xx_pcmcia_driver_init(void);
22358 +static void bcm47xx_pcmcia_driver_shutdown(void);
22359 +static void bcm47xx_pcmcia_task_handler(void *data);
22360 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
22361 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
22362 +static struct tq_struct bcm47xx_pcmcia_task;
22363 +
22364 +#ifdef CONFIG_PROC_FS
22365 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
22366 + off_t pos, int count, int *eof, void *data);
22367 +#endif
22368 +
22369 +
22370 +/* Prototypes for operations which are exported to the
22371 + * in-kernel PCMCIA core:
22372 + */
22373 +
22374 +static int bcm47xx_pcmcia_init(unsigned int sock);
22375 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
22376 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
22377 + void (*handler)(void *, unsigned int), void *info);
22378 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
22379 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
22380 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
22381 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
22382 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
22383 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
22384 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22385 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22386 +#ifdef CONFIG_PROC_FS
22387 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
22388 +#endif
22389 +
22390 +static struct pccard_operations bcm47xx_pcmcia_operations = {
22391 + bcm47xx_pcmcia_init,
22392 + bcm47xx_pcmcia_suspend,
22393 + bcm47xx_pcmcia_register_callback,
22394 + bcm47xx_pcmcia_inquire_socket,
22395 + bcm47xx_pcmcia_get_status,
22396 + bcm47xx_pcmcia_get_socket,
22397 + bcm47xx_pcmcia_set_socket,
22398 + bcm47xx_pcmcia_get_io_map,
22399 + bcm47xx_pcmcia_set_io_map,
22400 + bcm47xx_pcmcia_get_mem_map,
22401 + bcm47xx_pcmcia_set_mem_map,
22402 +#ifdef CONFIG_PROC_FS
22403 + bcm47xx_pcmcia_proc_setup
22404 +#endif
22405 +};
22406 +
22407 +
22408 +/*
22409 + * bcm47xx_pcmcia_driver_init()
22410 + *
22411 + * This routine performs a basic sanity check to ensure that this
22412 + * kernel has been built with the appropriate board-specific low-level
22413 + * PCMCIA support, performs low-level PCMCIA initialization, registers
22414 + * this socket driver with Card Services, and then spawns the daemon
22415 + * thread which is the real workhorse of the socket driver.
22416 + *
22417 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
22418 + * on the low-level kernel interface.
22419 + *
22420 + * Returns: 0 on success, -1 on error
22421 + */
22422 +static int __init bcm47xx_pcmcia_driver_init(void)
22423 +{
22424 + servinfo_t info;
22425 + struct pcmcia_init pcmcia_init;
22426 + struct pcmcia_state state;
22427 + unsigned int i;
22428 + unsigned long tmp;
22429 +
22430 +
22431 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
22432 +
22433 + CardServices(GetCardServicesInfo, &info);
22434 +
22435 + if (info.Revision != CS_RELEASE_CODE) {
22436 + printk(KERN_ERR "Card Services release codes do not match\n");
22437 + return -1;
22438 + }
22439 +
22440 +#ifdef CONFIG_BCM4710
22441 + pcmcia_low_level=&bcm4710_pcmcia_ops;
22442 +#else
22443 +#error Unsupported Broadcom BCM47XX board.
22444 +#endif
22445 +
22446 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
22447 +
22448 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
22449 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
22450 + return -EIO;
22451 + } else {
22452 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
22453 + }
22454 +
22455 + pcmcia_socket =
22456 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
22457 + GFP_KERNEL);
22458 + memset(pcmcia_socket, 0,
22459 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
22460 + if (!pcmcia_socket) {
22461 + printk(KERN_ERR "Card Services can't get memory \n");
22462 + return -1;
22463 + }
22464 +
22465 + for (i = 0; i < socket_count; i++) {
22466 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
22467 + printk(KERN_ERR "Unable to get PCMCIA status\n");
22468 + return -EIO;
22469 + }
22470 + pcmcia_socket[i].k_state = state;
22471 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
22472 +
22473 + if (i == 0) {
22474 + pcmcia_socket[i].virt_io =
22475 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
22476 + /* Substract ioport base which gets added by in/out */
22477 + pcmcia_socket[i].virt_io -= mips_io_port_base;
22478 + pcmcia_socket[i].phys_attr =
22479 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
22480 + pcmcia_socket[i].phys_mem =
22481 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
22482 + } else {
22483 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
22484 + return 1;
22485 + }
22486 + }
22487 +
22488 + /* Only advertise as many sockets as we can detect: */
22489 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
22490 + printk(KERN_ERR "Unable to register socket service routine\n");
22491 + return -ENXIO;
22492 + }
22493 +
22494 + /* Start the event poll timer.
22495 + * It will reschedule by itself afterwards.
22496 + */
22497 + bcm47xx_pcmcia_poll_event(0);
22498 +
22499 + DEBUG(1, "bcm4710: initialization complete\n");
22500 + return 0;
22501 +
22502 +}
22503 +
22504 +module_init(bcm47xx_pcmcia_driver_init);
22505 +
22506 +
22507 +/*
22508 + * bcm47xx_pcmcia_driver_shutdown()
22509 + *
22510 + * Invokes the low-level kernel service to free IRQs associated with this
22511 + * socket controller and reset GPIO edge detection.
22512 + */
22513 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
22514 +{
22515 + int i;
22516 +
22517 + del_timer_sync(&poll_timer);
22518 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
22519 + pcmcia_low_level->shutdown();
22520 + flush_scheduled_tasks();
22521 + for (i = 0; i < socket_count; i++) {
22522 + if (pcmcia_socket[i].virt_io)
22523 + iounmap((void *)pcmcia_socket[i].virt_io);
22524 + if (pcmcia_socket[i].phys_attr)
22525 + iounmap((void *)pcmcia_socket[i].phys_attr);
22526 + if (pcmcia_socket[i].phys_mem)
22527 + iounmap((void *)pcmcia_socket[i].phys_mem);
22528 + }
22529 + DEBUG(1, "bcm4710: shutdown complete\n");
22530 +}
22531 +
22532 +module_exit(bcm47xx_pcmcia_driver_shutdown);
22533 +
22534 +/*
22535 + * bcm47xx_pcmcia_init()
22536 + * We perform all of the interesting initialization tasks in
22537 + * bcm47xx_pcmcia_driver_init().
22538 + *
22539 + * Returns: 0
22540 + */
22541 +static int bcm47xx_pcmcia_init(unsigned int sock)
22542 +{
22543 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
22544 +
22545 + return 0;
22546 +}
22547 +
22548 +/*
22549 + * bcm47xx_pcmcia_suspend()
22550 + *
22551 + * We don't currently perform any actions on a suspend.
22552 + *
22553 + * Returns: 0
22554 + */
22555 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
22556 +{
22557 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
22558 +
22559 + return 0;
22560 +}
22561 +
22562 +
22563 +/*
22564 + * bcm47xx_pcmcia_events()
22565 + *
22566 + * Helper routine to generate a Card Services event mask based on
22567 + * state information obtained from the kernel low-level PCMCIA layer
22568 + * in a recent (and previous) sampling. Updates `prev_state'.
22569 + *
22570 + * Returns: an event mask for the given socket state.
22571 + */
22572 +static inline unsigned
22573 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
22574 + struct pcmcia_state *prev_state,
22575 + unsigned int mask, unsigned int flags)
22576 +{
22577 + unsigned int events=0;
22578 +
22579 + if (state->bvd1 != prev_state->bvd1) {
22580 +
22581 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
22582 +
22583 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
22584 + }
22585 +
22586 + if (state->bvd2 != prev_state->bvd2) {
22587 +
22588 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
22589 +
22590 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
22591 + }
22592 +
22593 + if (state->detect != prev_state->detect) {
22594 +
22595 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
22596 +
22597 + events |= mask & SS_DETECT;
22598 + }
22599 +
22600 +
22601 + if (state->ready != prev_state->ready) {
22602 +
22603 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
22604 +
22605 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
22606 + }
22607 +
22608 + if (events != 0) {
22609 + DEBUG(2, "events: %s%s%s%s%s\n",
22610 + (events & SS_DETECT) ? "DETECT " : "",
22611 + (events & SS_READY) ? "READY " : "",
22612 + (events & SS_BATDEAD) ? "BATDEAD " : "",
22613 + (events & SS_BATWARN) ? "BATWARN " : "",
22614 + (events & SS_STSCHG) ? "STSCHG " : "");
22615 + }
22616 +
22617 + *prev_state=*state;
22618 + return events;
22619 +}
22620 +
22621 +
22622 +/*
22623 + * bcm47xx_pcmcia_task_handler()
22624 + *
22625 + * Processes serviceable socket events using the "eventd" thread context.
22626 + *
22627 + * Event processing (specifically, the invocation of the Card Services event
22628 + * callback) occurs in this thread rather than in the actual interrupt
22629 + * handler due to the use of scheduling operations in the PCMCIA core.
22630 + */
22631 +static void bcm47xx_pcmcia_task_handler(void *data)
22632 +{
22633 + struct pcmcia_state state;
22634 + int i, events, irq_status;
22635 +
22636 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
22637 +
22638 + for (i = 0; i < socket_count; i++) {
22639 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
22640 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
22641 +
22642 + events = bcm47xx_pcmcia_events(&state,
22643 + &pcmcia_socket[i].k_state,
22644 + pcmcia_socket[i].cs_state.csc_mask,
22645 + pcmcia_socket[i].cs_state.flags);
22646 +
22647 + if (pcmcia_socket[i].handler != NULL) {
22648 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
22649 + events);
22650 + }
22651 + }
22652 +}
22653 +
22654 +static struct tq_struct bcm47xx_pcmcia_task = {
22655 + routine: bcm47xx_pcmcia_task_handler
22656 +};
22657 +
22658 +
22659 +/*
22660 + * bcm47xx_pcmcia_poll_event()
22661 + *
22662 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
22663 + */
22664 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
22665 +{
22666 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
22667 +
22668 + poll_timer.function = bcm47xx_pcmcia_poll_event;
22669 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
22670 + add_timer(&poll_timer);
22671 + schedule_task(&bcm47xx_pcmcia_task);
22672 +}
22673 +
22674 +
22675 +/*
22676 + * bcm47xx_pcmcia_interrupt()
22677 + *
22678 + * Service routine for socket driver interrupts (requested by the
22679 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
22680 + *
22681 + * The actual interrupt-servicing work is performed by
22682 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
22683 + * handling code performs scheduling operations which cannot be
22684 + * executed from within an interrupt context.
22685 + */
22686 +static void
22687 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
22688 +{
22689 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
22690 + schedule_task(&bcm47xx_pcmcia_task);
22691 +}
22692 +
22693 +
22694 +/*
22695 + * bcm47xx_pcmcia_register_callback()
22696 + *
22697 + * Implements the register_callback() operation for the in-kernel
22698 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
22699 + * the function pointer `handler' is not NULL, remember the callback
22700 + * location in the state for `sock', and increment the usage counter
22701 + * for the driver module. (The callback is invoked from the interrupt
22702 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
22703 + * of interesting events.) Otherwise, clear the callback pointer in the
22704 + * socket state and decrement the module usage count.
22705 + *
22706 + * Returns: 0
22707 + */
22708 +static int
22709 +bcm47xx_pcmcia_register_callback(unsigned int sock,
22710 + void (*handler)(void *, unsigned int), void *info)
22711 +{
22712 + if (handler == NULL) {
22713 + pcmcia_socket[sock].handler = NULL;
22714 + MOD_DEC_USE_COUNT;
22715 + } else {
22716 + MOD_INC_USE_COUNT;
22717 + pcmcia_socket[sock].handler = handler;
22718 + pcmcia_socket[sock].handler_info = info;
22719 + }
22720 + return 0;
22721 +}
22722 +
22723 +
22724 +/*
22725 + * bcm47xx_pcmcia_inquire_socket()
22726 + *
22727 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
22728 + * service (formerly SS_InquireSocket in Card Services). Of note is
22729 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
22730 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
22731 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
22732 + * resource database check. (Mapped memory is set up within the socket
22733 + * driver itself.)
22734 + *
22735 + * In conjunction with the STATIC_MAP capability is a new field,
22736 + * `io_offset', recommended by David Hinds. Rather than go through
22737 + * the SetIOMap interface (which is not quite suited for communicating
22738 + * window locations up from the socket driver), we just pass up
22739 + * an offset which is applied to client-requested base I/O addresses
22740 + * in alloc_io_space().
22741 + *
22742 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
22743 + */
22744 +static int
22745 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
22746 +{
22747 + struct pcmcia_irq_info irq_info;
22748 +
22749 + if (sock >= socket_count) {
22750 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
22751 + return -1;
22752 + }
22753 +
22754 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
22755 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
22756 + * general, the mapped * addresses of the PCMCIA memory regions
22757 + * will not be within 0xffff, setting force_low would be
22758 + * undesirable.
22759 + *
22760 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
22761 + * resource database; we instead pass up physical address ranges
22762 + * and allow other parts of Card Services to deal with remapping.
22763 + *
22764 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
22765 + * not 32-bit CardBus devices.
22766 + */
22767 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
22768 +
22769 + irq_info.sock = sock;
22770 + irq_info.irq = -1;
22771 +
22772 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
22773 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
22774 + return -1;
22775 + }
22776 +
22777 + cap->irq_mask = 0;
22778 + cap->map_size = PAGE_SIZE;
22779 + cap->pci_irq = irq_info.irq;
22780 + cap->io_offset = pcmcia_socket[sock].virt_io;
22781 +
22782 + return 0;
22783 +}
22784 +
22785 +
22786 +/*
22787 + * bcm47xx_pcmcia_get_status()
22788 + *
22789 + * Implements the get_status() operation for the in-kernel PCMCIA
22790 + * service (formerly SS_GetStatus in Card Services). Essentially just
22791 + * fills in bits in `status' according to internal driver state or
22792 + * the value of the voltage detect chipselect register.
22793 + *
22794 + * As a debugging note, during card startup, the PCMCIA core issues
22795 + * three set_socket() commands in a row the first with RESET deasserted,
22796 + * the second with RESET asserted, and the last with RESET deasserted
22797 + * again. Following the third set_socket(), a get_status() command will
22798 + * be issued. The kernel is looking for the SS_READY flag (see
22799 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
22800 + *
22801 + * Returns: 0
22802 + */
22803 +static int
22804 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
22805 +{
22806 + struct pcmcia_state state;
22807 +
22808 +
22809 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
22810 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
22811 + return -1;
22812 + }
22813 +
22814 + pcmcia_socket[sock].k_state = state;
22815 +
22816 + *status = state.detect ? SS_DETECT : 0;
22817 +
22818 + *status |= state.ready ? SS_READY : 0;
22819 +
22820 + /* The power status of individual sockets is not available
22821 + * explicitly from the hardware, so we just remember the state
22822 + * and regurgitate it upon request:
22823 + */
22824 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
22825 +
22826 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
22827 + *status |= state.bvd1 ? SS_STSCHG : 0;
22828 + else {
22829 + if (state.bvd1 == 0)
22830 + *status |= SS_BATDEAD;
22831 + else if (state.bvd2 == 0)
22832 + *status |= SS_BATWARN;
22833 + }
22834 +
22835 + *status |= state.vs_3v ? SS_3VCARD : 0;
22836 +
22837 + *status |= state.vs_Xv ? SS_XVCARD : 0;
22838 +
22839 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
22840 + (*status&SS_DETECT)?"DETECT ":"",
22841 + (*status&SS_READY)?"READY ":"",
22842 + (*status&SS_BATDEAD)?"BATDEAD ":"",
22843 + (*status&SS_BATWARN)?"BATWARN ":"",
22844 + (*status&SS_POWERON)?"POWERON ":"",
22845 + (*status&SS_STSCHG)?"STSCHG ":"",
22846 + (*status&SS_3VCARD)?"3VCARD ":"",
22847 + (*status&SS_XVCARD)?"XVCARD ":"");
22848 +
22849 + return 0;
22850 +}
22851 +
22852 +
22853 +/*
22854 + * bcm47xx_pcmcia_get_socket()
22855 + *
22856 + * Implements the get_socket() operation for the in-kernel PCMCIA
22857 + * service (formerly SS_GetSocket in Card Services). Not a very
22858 + * exciting routine.
22859 + *
22860 + * Returns: 0
22861 + */
22862 +static int
22863 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
22864 +{
22865 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
22866 +
22867 + /* This information was given to us in an earlier call to set_socket(),
22868 + * so we're just regurgitating it here:
22869 + */
22870 + *state = pcmcia_socket[sock].cs_state;
22871 + return 0;
22872 +}
22873 +
22874 +
22875 +/*
22876 + * bcm47xx_pcmcia_set_socket()
22877 + *
22878 + * Implements the set_socket() operation for the in-kernel PCMCIA
22879 + * service (formerly SS_SetSocket in Card Services). We more or
22880 + * less punt all of this work and let the kernel handle the details
22881 + * of power configuration, reset, &c. We also record the value of
22882 + * `state' in order to regurgitate it to the PCMCIA core later.
22883 + *
22884 + * Returns: 0
22885 + */
22886 +static int
22887 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
22888 +{
22889 + struct pcmcia_configure configure;
22890 +
22891 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
22892 + "\tVcc %d Vpp %d irq %d\n",
22893 + (state->csc_mask == 0) ? "<NONE>" : "",
22894 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
22895 + (state->csc_mask & SS_READY) ? "READY " : "",
22896 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
22897 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
22898 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
22899 + (state->flags == 0) ? "<NONE>" : "",
22900 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
22901 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
22902 + (state->flags & SS_RESET) ? "RESET " : "",
22903 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
22904 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
22905 + state->Vcc, state->Vpp, state->io_irq);
22906 +
22907 + configure.sock = sock;
22908 + configure.vcc = state->Vcc;
22909 + configure.vpp = state->Vpp;
22910 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
22911 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
22912 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
22913 +
22914 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
22915 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
22916 + return -1;
22917 + }
22918 +
22919 + pcmcia_socket[sock].cs_state = *state;
22920 + return 0;
22921 +}
22922 +
22923 +
22924 +/*
22925 + * bcm47xx_pcmcia_get_io_map()
22926 + *
22927 + * Implements the get_io_map() operation for the in-kernel PCMCIA
22928 + * service (formerly SS_GetIOMap in Card Services). Just returns an
22929 + * I/O map descriptor which was assigned earlier by a set_io_map().
22930 + *
22931 + * Returns: 0 on success, -1 if the map index was out of range
22932 + */
22933 +static int
22934 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
22935 +{
22936 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
22937 +
22938 + if (map->map >= MAX_IO_WIN) {
22939 + printk(KERN_ERR "%s(): map (%d) out of range\n",
22940 + __FUNCTION__, map->map);
22941 + return -1;
22942 + }
22943 +
22944 + *map = pcmcia_socket[sock].io_map[map->map];
22945 + return 0;
22946 +}
22947 +
22948 +
22949 +/*
22950 + * bcm47xx_pcmcia_set_io_map()
22951 + *
22952 + * Implements the set_io_map() operation for the in-kernel PCMCIA
22953 + * service (formerly SS_SetIOMap in Card Services). We configure
22954 + * the map speed as requested, but override the address ranges
22955 + * supplied by Card Services.
22956 + *
22957 + * Returns: 0 on success, -1 on error
22958 + */
22959 +int
22960 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
22961 +{
22962 + unsigned int speed;
22963 + unsigned long start;
22964 +
22965 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
22966 + "\tflags: %s%s%s%s%s%s%s%s\n",
22967 + map->map, map->speed, map->start, map->stop,
22968 + (map->flags == 0) ? "<NONE>" : "",
22969 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
22970 + (map->flags & MAP_16BIT) ? "16BIT " : "",
22971 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
22972 + (map->flags & MAP_0WS) ? "0WS " : "",
22973 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
22974 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
22975 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
22976 +
22977 + if (map->map >= MAX_IO_WIN) {
22978 + printk(KERN_ERR "%s(): map (%d) out of range\n",
22979 + __FUNCTION__, map->map);
22980 + return -1;
22981 + }
22982 +
22983 + if (map->flags & MAP_ACTIVE) {
22984 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
22985 + pcmcia_socket[sock].speed_io = speed;
22986 + }
22987 +
22988 + start = map->start;
22989 +
22990 + if (map->stop == 1) {
22991 + map->stop = PAGE_SIZE - 1;
22992 + }
22993 +
22994 + map->start = pcmcia_socket[sock].virt_io;
22995 + map->stop = map->start + (map->stop - start);
22996 + pcmcia_socket[sock].io_map[map->map] = *map;
22997 + DEBUG(2, "set_io_map %d start %x stop %x\n",
22998 + map->map, map->start, map->stop);
22999 + return 0;
23000 +}
23001 +
23002 +
23003 +/*
23004 + * bcm47xx_pcmcia_get_mem_map()
23005 + *
23006 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
23007 + * service (formerly SS_GetMemMap in Card Services). Just returns a
23008 + * memory map descriptor which was assigned earlier by a
23009 + * set_mem_map() request.
23010 + *
23011 + * Returns: 0 on success, -1 if the map index was out of range
23012 + */
23013 +static int
23014 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
23015 +{
23016 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23017 +
23018 + if (map->map >= MAX_WIN) {
23019 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23020 + __FUNCTION__, map->map);
23021 + return -1;
23022 + }
23023 +
23024 + *map = pcmcia_socket[sock].mem_map[map->map];
23025 + return 0;
23026 +}
23027 +
23028 +
23029 +/*
23030 + * bcm47xx_pcmcia_set_mem_map()
23031 + *
23032 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
23033 + * service (formerly SS_SetMemMap in Card Services). We configure
23034 + * the map speed as requested, but override the address ranges
23035 + * supplied by Card Services.
23036 + *
23037 + * Returns: 0 on success, -1 on error
23038 + */
23039 +static int
23040 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
23041 +{
23042 + unsigned int speed;
23043 + unsigned long start;
23044 + u_long flags;
23045 +
23046 + if (map->map >= MAX_WIN) {
23047 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23048 + __FUNCTION__, map->map);
23049 + return -1;
23050 + }
23051 +
23052 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
23053 + "\tsys_stop %#lx\n\tcard_start %#x\n"
23054 + "\tflags: %s%s%s%s%s%s%s%s\n",
23055 + map->map, map->speed, map->sys_start, map->sys_stop,
23056 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
23057 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23058 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23059 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23060 + (map->flags & MAP_0WS) ? "0WS " : "",
23061 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23062 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
23063 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
23064 +
23065 + if (map->flags & MAP_ACTIVE) {
23066 + /* When clients issue RequestMap, the access speed is not always
23067 + * properly configured:
23068 + */
23069 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
23070 +
23071 + /* TBD */
23072 + if (map->flags & MAP_ATTRIB) {
23073 + pcmcia_socket[sock].speed_attr = speed;
23074 + } else {
23075 + pcmcia_socket[sock].speed_mem = speed;
23076 + }
23077 + }
23078 +
23079 + save_flags(flags);
23080 + cli();
23081 + start = map->sys_start;
23082 +
23083 + if (map->sys_stop == 0)
23084 + map->sys_stop = PAGE_SIZE - 1;
23085 +
23086 + if (map->flags & MAP_ATTRIB) {
23087 + map->sys_start = pcmcia_socket[sock].phys_attr +
23088 + map->card_start;
23089 + } else {
23090 + map->sys_start = pcmcia_socket[sock].phys_mem +
23091 + map->card_start;
23092 + }
23093 +
23094 + map->sys_stop = map->sys_start + (map->sys_stop - start);
23095 + pcmcia_socket[sock].mem_map[map->map] = *map;
23096 + restore_flags(flags);
23097 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
23098 + map->map, map->sys_start, map->sys_stop,
23099 + map->card_start);
23100 + return 0;
23101 +}
23102 +
23103 +
23104 +#if defined(CONFIG_PROC_FS)
23105 +
23106 +/*
23107 + * bcm47xx_pcmcia_proc_setup()
23108 + *
23109 + * Implements the proc_setup() operation for the in-kernel PCMCIA
23110 + * service (formerly SS_ProcSetup in Card Services).
23111 + *
23112 + * Returns: 0 on success, -1 on error
23113 + */
23114 +static void
23115 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
23116 +{
23117 + struct proc_dir_entry *entry;
23118 +
23119 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
23120 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
23121 + return;
23122 + }
23123 +
23124 + entry->read_proc = bcm47xx_pcmcia_proc_status;
23125 + entry->data = (void *)sock;
23126 +}
23127 +
23128 +
23129 +/*
23130 + * bcm47xx_pcmcia_proc_status()
23131 + *
23132 + * Implements the /proc/bus/pccard/??/status file.
23133 + *
23134 + * Returns: the number of characters added to the buffer
23135 + */
23136 +static int
23137 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
23138 + int count, int *eof, void *data)
23139 +{
23140 + char *p = buf;
23141 + unsigned int sock = (unsigned int)data;
23142 +
23143 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
23144 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
23145 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
23146 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
23147 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
23148 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
23149 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
23150 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
23151 +
23152 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
23153 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
23154 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
23155 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
23156 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
23157 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
23158 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
23159 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23160 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
23161 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23162 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
23163 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
23164 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
23165 +
23166 + p += sprintf(p, "mask : %s%s%s%s%s\n",
23167 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
23168 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
23169 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
23170 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
23171 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
23172 +
23173 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
23174 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
23175 + "SS_PWR_AUTO " : "",
23176 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
23177 + "SS_IOCARD " : "",
23178 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
23179 + "SS_RESET " : "",
23180 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
23181 + "SS_SPKR_ENA " : "",
23182 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
23183 + "SS_OUTPUT_ENA " : "");
23184 +
23185 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
23186 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
23187 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
23188 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
23189 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
23190 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
23191 + return p-buf;
23192 +}
23193 +
23194 +
23195 +#endif /* defined(CONFIG_PROC_FS) */
23196 diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710_pcmcia.c linux-2.4.32-brcm/drivers/pcmcia/bcm4710_pcmcia.c
23197 --- linux-2.4.32/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
23198 +++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710_pcmcia.c 2005-12-16 23:39:11.368863250 +0100
23199 @@ -0,0 +1,266 @@
23200 +/*
23201 + * BCM4710 specific pcmcia routines.
23202 + *
23203 + * Copyright 2004, Broadcom Corporation
23204 + * All Rights Reserved.
23205 + *
23206 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23207 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23208 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23209 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23210 + *
23211 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
23212 + */
23213 +#include <linux/module.h>
23214 +#include <linux/init.h>
23215 +#include <linux/config.h>
23216 +#include <linux/delay.h>
23217 +#include <linux/ioport.h>
23218 +#include <linux/kernel.h>
23219 +#include <linux/tqueue.h>
23220 +#include <linux/timer.h>
23221 +#include <linux/mm.h>
23222 +#include <linux/proc_fs.h>
23223 +#include <linux/version.h>
23224 +#include <linux/types.h>
23225 +#include <linux/pci.h>
23226 +
23227 +#include <pcmcia/version.h>
23228 +#include <pcmcia/cs_types.h>
23229 +#include <pcmcia/cs.h>
23230 +#include <pcmcia/ss.h>
23231 +#include <pcmcia/bulkmem.h>
23232 +#include <pcmcia/cistpl.h>
23233 +#include <pcmcia/bus_ops.h>
23234 +#include "cs_internal.h"
23235 +
23236 +#include <asm/io.h>
23237 +#include <asm/irq.h>
23238 +#include <asm/system.h>
23239 +
23240 +
23241 +#include <typedefs.h>
23242 +#include <bcmdevs.h>
23243 +#include <bcm4710.h>
23244 +#include <sbconfig.h>
23245 +#include <sbextif.h>
23246 +
23247 +#include "bcm4710pcmcia.h"
23248 +
23249 +/* Use a static var for irq dev_id */
23250 +static int bcm47xx_pcmcia_dev_id;
23251 +
23252 +/* Do we think we have a card or not? */
23253 +static int bcm47xx_pcmcia_present = 0;
23254 +
23255 +
23256 +static void bcm4710_pcmcia_reset(void)
23257 +{
23258 + extifregs_t *eir;
23259 + unsigned long s;
23260 + uint32 out0, out1, outen;
23261 +
23262 +
23263 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23264 +
23265 + save_and_cli(s);
23266 +
23267 + /* Use gpio7 to reset the pcmcia slot */
23268 + outen = readl(&eir->gpio[0].outen);
23269 + outen |= BCM47XX_PCMCIA_RESET;
23270 + out0 = readl(&eir->gpio[0].out);
23271 + out0 &= ~(BCM47XX_PCMCIA_RESET);
23272 + out1 = out0 | BCM47XX_PCMCIA_RESET;
23273 +
23274 + writel(out0, &eir->gpio[0].out);
23275 + writel(outen, &eir->gpio[0].outen);
23276 + mdelay(1);
23277 + writel(out1, &eir->gpio[0].out);
23278 + mdelay(1);
23279 + writel(out0, &eir->gpio[0].out);
23280 +
23281 + restore_flags(s);
23282 +}
23283 +
23284 +
23285 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
23286 +{
23287 + struct pci_dev *pdev;
23288 + extifregs_t *eir;
23289 + uint32 outen, intp, intm, tmp;
23290 + uint16 *attrsp;
23291 + int rc = 0, i;
23292 + extern unsigned long bcm4710_cpu_cycle;
23293 +
23294 +
23295 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
23296 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
23297 + return -ENODEV;
23298 + }
23299 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
23300 +
23301 + /* Initialize the pcmcia i/f: 16bit no swap */
23302 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
23303 +
23304 +#ifdef notYet
23305 +
23306 + /* Set the timing for memory accesses */
23307 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23308 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23309 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23310 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23311 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
23312 +
23313 + /* Set the timing for I/O accesses */
23314 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23315 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23316 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23317 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23318 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
23319 +
23320 + /* Set the timing for attribute accesses */
23321 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23322 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23323 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23324 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23325 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
23326 +
23327 +#endif
23328 + /* Make sure gpio0 and gpio5 are inputs */
23329 + outen = readl(&eir->gpio[0].outen);
23330 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
23331 + writel(outen, &eir->gpio[0].outen);
23332 +
23333 + /* Issue a reset to the pcmcia socket */
23334 + bcm4710_pcmcia_reset();
23335 +
23336 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23337 + /* Setup gpio5 to be the STSCHG interrupt */
23338 + intp = readl(&eir->gpiointpolarity);
23339 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
23340 + intm = readl(&eir->gpiointmask);
23341 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
23342 +#endif
23343 +
23344 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
23345 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
23346 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
23347 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
23348 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
23349 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
23350 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
23351 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
23352 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
23353 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
23354 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
23355 +
23356 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23357 + /* Request pcmcia interrupt */
23358 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
23359 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
23360 +#endif
23361 +
23362 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
23363 + tmp = readw(&attrsp[0]);
23364 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
23365 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
23366 + bcm47xx_pcmcia_present = 0;
23367 + } else {
23368 + bcm47xx_pcmcia_present = 1;
23369 + }
23370 +
23371 + /* There's only one socket */
23372 + return 1;
23373 +}
23374 +
23375 +static int bcm4710_pcmcia_shutdown(void)
23376 +{
23377 + extifregs_t *eir;
23378 + uint32 intm;
23379 +
23380 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23381 +
23382 + /* Disable the pcmcia i/f */
23383 + writel(0, &eir->pcmcia_config);
23384 +
23385 + /* Reset gpio's */
23386 + intm = readl(&eir->gpiointmask);
23387 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
23388 +
23389 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
23390 +
23391 + return 0;
23392 +}
23393 +
23394 +static int
23395 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
23396 +{
23397 + extifregs_t *eir;
23398 +
23399 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23400 +
23401 +
23402 + if (sock != 0) {
23403 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
23404 + return -1;
23405 + }
23406 +
23407 + if (bcm47xx_pcmcia_present) {
23408 + state->detect = 1;
23409 + state->ready = 1;
23410 + state->bvd1 = 1;
23411 + state->bvd2 = 1;
23412 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
23413 + state->vs_3v = 0;
23414 + state->vs_Xv = 0;
23415 + } else {
23416 + state->detect = 0;
23417 + state->ready = 0;
23418 + }
23419 +
23420 + return 1;
23421 +}
23422 +
23423 +
23424 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
23425 +{
23426 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23427 +
23428 + info->irq = BCM47XX_PCMCIA_IRQ;
23429 +
23430 + return 0;
23431 +}
23432 +
23433 +
23434 +static int
23435 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
23436 +{
23437 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23438 +
23439 +
23440 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
23441 + configure->vpp, configure->output, configure->speaker, configure->reset);
23442 +
23443 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
23444 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
23445 + configure->vpp);
23446 + }
23447 +
23448 + if (configure->reset) {
23449 + /* Issue a reset to the pcmcia socket */
23450 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
23451 + bcm4710_pcmcia_reset();
23452 + }
23453 +
23454 +
23455 + return 0;
23456 +}
23457 +
23458 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
23459 + bcm4710_pcmcia_init,
23460 + bcm4710_pcmcia_shutdown,
23461 + bcm4710_pcmcia_socket_state,
23462 + bcm4710_pcmcia_get_irq_info,
23463 + bcm4710_pcmcia_configure_socket
23464 +};
23465 +
23466 diff -Nur linux-2.4.32/drivers/pcmcia/bcm4710pcmcia.h linux-2.4.32-brcm/drivers/pcmcia/bcm4710pcmcia.h
23467 --- linux-2.4.32/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
23468 +++ linux-2.4.32-brcm/drivers/pcmcia/bcm4710pcmcia.h 2005-12-16 23:39:11.368863250 +0100
23469 @@ -0,0 +1,118 @@
23470 +/*
23471 + *
23472 + * bcm47xx pcmcia driver
23473 + *
23474 + * Copyright 2004, Broadcom Corporation
23475 + * All Rights Reserved.
23476 + *
23477 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23478 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23479 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23480 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23481 + *
23482 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
23483 + * from www.handhelds.org,
23484 + * and au1000_generic.c from oss.sgi.com.
23485 + *
23486 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
23487 + */
23488 +
23489 +#if !defined(_BCM4710PCMCIA_H)
23490 +#define _BCM4710PCMCIA_H
23491 +
23492 +#include <pcmcia/cs_types.h>
23493 +#include <pcmcia/ss.h>
23494 +#include <pcmcia/bulkmem.h>
23495 +#include <pcmcia/cistpl.h>
23496 +#include "cs_internal.h"
23497 +
23498 +
23499 +/* The 47xx can only support one socket */
23500 +#define BCM47XX_PCMCIA_MAX_SOCK 1
23501 +
23502 +/* In the bcm947xx gpio's are used for some pcmcia functions */
23503 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
23504 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
23505 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
23506 +
23507 +#define BCM47XX_PCMCIA_IRQ 2
23508 +
23509 +/* The socket driver actually works nicely in interrupt-driven form,
23510 + * so the (relatively infrequent) polling is "just to be sure."
23511 + */
23512 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
23513 +
23514 +#define BCM47XX_PCMCIA_IO_SPEED (255)
23515 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
23516 +
23517 +
23518 +struct pcmcia_state {
23519 + unsigned detect: 1,
23520 + ready: 1,
23521 + bvd1: 1,
23522 + bvd2: 1,
23523 + wrprot: 1,
23524 + vs_3v: 1,
23525 + vs_Xv: 1;
23526 +};
23527 +
23528 +
23529 +struct pcmcia_configure {
23530 + unsigned sock: 8,
23531 + vcc: 8,
23532 + vpp: 8,
23533 + output: 1,
23534 + speaker: 1,
23535 + reset: 1;
23536 +};
23537 +
23538 +struct pcmcia_irq_info {
23539 + unsigned int sock;
23540 + unsigned int irq;
23541 +};
23542 +
23543 +/* This structure encapsulates per-socket state which we might need to
23544 + * use when responding to a Card Services query of some kind.
23545 + */
23546 +struct bcm47xx_pcmcia_socket {
23547 + socket_state_t cs_state;
23548 + struct pcmcia_state k_state;
23549 + unsigned int irq;
23550 + void (*handler)(void *, unsigned int);
23551 + void *handler_info;
23552 + pccard_io_map io_map[MAX_IO_WIN];
23553 + pccard_mem_map mem_map[MAX_WIN];
23554 + ioaddr_t virt_io, phys_attr, phys_mem;
23555 + unsigned short speed_io, speed_attr, speed_mem;
23556 +};
23557 +
23558 +struct pcmcia_init {
23559 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
23560 +};
23561 +
23562 +struct pcmcia_low_level {
23563 + int (*init)(struct pcmcia_init *);
23564 + int (*shutdown)(void);
23565 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
23566 + int (*get_irq_info)(struct pcmcia_irq_info *);
23567 + int (*configure_socket)(const struct pcmcia_configure *);
23568 +};
23569 +
23570 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
23571 +
23572 +/* I/O pins replacing memory pins
23573 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
23574 + *
23575 + * These signals change meaning when going from memory-only to
23576 + * memory-or-I/O interface:
23577 + */
23578 +#define iostschg bvd1
23579 +#define iospkr bvd2
23580 +
23581 +
23582 +/*
23583 + * Declaration for implementation specific low_level operations.
23584 + */
23585 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
23586 +
23587 +#endif /* !defined(_BCM4710PCMCIA_H) */
23588 diff -Nur linux-2.4.32/drivers/pcmcia/Makefile linux-2.4.32-brcm/drivers/pcmcia/Makefile
23589 --- linux-2.4.32/drivers/pcmcia/Makefile 2004-02-18 14:36:31.000000000 +0100
23590 +++ linux-2.4.32-brcm/drivers/pcmcia/Makefile 2005-12-16 23:39:11.364863000 +0100
23591 @@ -65,6 +65,10 @@
23592 au1000_ss-objs-$(CONFIG_PCMCIA_DB1X00) += au1000_db1x00.o
23593 au1000_ss-objs-$(CONFIG_PCMCIA_XXS1500) += au1000_xxs1500.o
23594
23595 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
23596 +bcm4710_ss-objs := bcm4710_generic.o
23597 +bcm4710_ss-objs += bcm4710_pcmcia.o
23598 +
23599 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
23600 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
23601 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
23602 @@ -102,5 +106,8 @@
23603 au1x00_ss.o: $(au1000_ss-objs-y)
23604 $(LD) -r -o $@ $(au1000_ss-objs-y)
23605
23606 +bcm4710_ss.o: $(bcm4710_ss-objs)
23607 + $(LD) -r -o $@ $(bcm4710_ss-objs)
23608 +
23609 yenta_socket.o: $(yenta_socket-objs)
23610 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
23611 diff -Nur linux-2.4.32/include/asm-mips/bootinfo.h linux-2.4.32-brcm/include/asm-mips/bootinfo.h
23612 --- linux-2.4.32/include/asm-mips/bootinfo.h 2004-02-18 14:36:32.000000000 +0100
23613 +++ linux-2.4.32-brcm/include/asm-mips/bootinfo.h 2005-12-16 23:39:11.400865250 +0100
23614 @@ -37,6 +37,7 @@
23615 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
23616 #define MACH_GROUP_LASAT 21
23617 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
23618 +#define MACH_GROUP_BRCM 23 /* Broadcom */
23619
23620 /*
23621 * Valid machtype values for group unknown (low order halfword of mips_machtype)
23622 @@ -194,6 +195,15 @@
23623 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
23624
23625 /*
23626 + * Valid machtypes for group Broadcom
23627 + */
23628 +#define MACH_BCM93725 0
23629 +#define MACH_BCM93725_VJ 1
23630 +#define MACH_BCM93730 2
23631 +#define MACH_BCM947XX 3
23632 +#define MACH_BCM933XX 4
23633 +
23634 +/*
23635 * Valid machtype for group TITAN
23636 */
23637 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
23638 diff -Nur linux-2.4.32/include/asm-mips/cpu.h linux-2.4.32-brcm/include/asm-mips/cpu.h
23639 --- linux-2.4.32/include/asm-mips/cpu.h 2005-01-19 15:10:11.000000000 +0100
23640 +++ linux-2.4.32-brcm/include/asm-mips/cpu.h 2005-12-16 23:39:11.412866000 +0100
23641 @@ -22,6 +22,11 @@
23642 spec.
23643 */
23644
23645 +#define PRID_COPT_MASK 0xff000000
23646 +#define PRID_COMP_MASK 0x00ff0000
23647 +#define PRID_IMP_MASK 0x0000ff00
23648 +#define PRID_REV_MASK 0x000000ff
23649 +
23650 #define PRID_COMP_LEGACY 0x000000
23651 #define PRID_COMP_MIPS 0x010000
23652 #define PRID_COMP_BROADCOM 0x020000
23653 @@ -58,6 +63,7 @@
23654 #define PRID_IMP_RM7000 0x2700
23655 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
23656 #define PRID_IMP_RM9000 0x3400
23657 +#define PRID_IMP_BCM4710 0x4000
23658 #define PRID_IMP_R5432 0x5400
23659 #define PRID_IMP_R5500 0x5500
23660 #define PRID_IMP_4KC 0x8000
23661 @@ -66,10 +72,16 @@
23662 #define PRID_IMP_4KEC 0x8400
23663 #define PRID_IMP_4KSC 0x8600
23664 #define PRID_IMP_25KF 0x8800
23665 +#define PRID_IMP_BCM3302 0x9000
23666 +#define PRID_IMP_BCM3303 0x9100
23667 #define PRID_IMP_24K 0x9300
23668
23669 #define PRID_IMP_UNKNOWN 0xff00
23670
23671 +#define BCM330X(id) \
23672 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
23673 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
23674 +
23675 /*
23676 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
23677 */
23678 @@ -174,7 +186,9 @@
23679 #define CPU_AU1550 57
23680 #define CPU_24K 58
23681 #define CPU_AU1200 59
23682 -#define CPU_LAST 59
23683 +#define CPU_BCM4710 60
23684 +#define CPU_BCM3302 61
23685 +#define CPU_LAST 61
23686
23687 /*
23688 * ISA Level encodings
23689 diff -Nur linux-2.4.32/include/asm-mips/r4kcache.h linux-2.4.32-brcm/include/asm-mips/r4kcache.h
23690 --- linux-2.4.32/include/asm-mips/r4kcache.h 2004-02-18 14:36:32.000000000 +0100
23691 +++ linux-2.4.32-brcm/include/asm-mips/r4kcache.h 2005-12-16 23:39:11.416866250 +0100
23692 @@ -567,4 +567,17 @@
23693 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
23694 }
23695
23696 +extern inline void fill_icache_line(unsigned long addr)
23697 +{
23698 + __asm__ __volatile__(
23699 + ".set noreorder\n\t"
23700 + ".set mips3\n\t"
23701 + "cache %1, (%0)\n\t"
23702 + ".set mips0\n\t"
23703 + ".set reorder"
23704 + :
23705 + : "r" (addr),
23706 + "i" (Fill));
23707 +}
23708 +
23709 #endif /* __ASM_R4KCACHE_H */
23710 diff -Nur linux-2.4.32/include/asm-mips/serial.h linux-2.4.32-brcm/include/asm-mips/serial.h
23711 --- linux-2.4.32/include/asm-mips/serial.h 2005-01-19 15:10:12.000000000 +0100
23712 +++ linux-2.4.32-brcm/include/asm-mips/serial.h 2005-12-16 23:39:11.428867000 +0100
23713 @@ -223,6 +223,13 @@
23714 #define TXX927_SERIAL_PORT_DEFNS
23715 #endif
23716
23717 +#ifdef CONFIG_BCM947XX
23718 +/* reserve 4 ports to be configured at runtime */
23719 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
23720 +#else
23721 +#define BCM947XX_SERIAL_PORT_DEFNS
23722 +#endif
23723 +
23724 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
23725 #define STD_SERIAL_PORT_DEFNS \
23726 /* UART CLK PORT IRQ FLAGS */ \
23727 @@ -470,6 +477,7 @@
23728 #define SERIAL_PORT_DFNS \
23729 ATLAS_SERIAL_PORT_DEFNS \
23730 AU1000_SERIAL_PORT_DEFNS \
23731 + BCM947XX_SERIAL_PORT_DEFNS \
23732 COBALT_SERIAL_PORT_DEFNS \
23733 DDB5477_SERIAL_PORT_DEFNS \
23734 EV96100_SERIAL_PORT_DEFNS \
23735 diff -Nur linux-2.4.32/init/do_mounts.c linux-2.4.32-brcm/init/do_mounts.c
23736 --- linux-2.4.32/init/do_mounts.c 2003-11-28 19:26:21.000000000 +0100
23737 +++ linux-2.4.32-brcm/init/do_mounts.c 2005-12-16 23:39:11.504871750 +0100
23738 @@ -253,7 +253,13 @@
23739 { "ftlb", 0x2c08 },
23740 { "ftlc", 0x2c10 },
23741 { "ftld", 0x2c18 },
23742 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
23743 { "mtdblock", 0x1f00 },
23744 + { "mtdblock0",0x1f00 },
23745 + { "mtdblock1",0x1f01 },
23746 + { "mtdblock2",0x1f02 },
23747 + { "mtdblock3",0x1f03 },
23748 +#endif
23749 { "nb", 0x2b00 },
23750 { NULL, 0 }
23751 };
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