1 Index: linux-2.6.22-rc6/drivers/ssb/driver_mipscore.c
2 ===================================================================
3 --- linux-2.6.22-rc6.orig/drivers/ssb/driver_mipscore.c 2007-06-28 11:35:29.077307472 +0200
4 +++ linux-2.6.22-rc6/drivers/ssb/driver_mipscore.c 2007-06-28 12:11:01.433140112 +0200
6 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
9 -/* XXX: leave here or move into separate extif driver? */
10 +static inline bool serial_exists(u8 *regs)
12 + u8 save_mcr, status1 = 0;
15 + save_mcr = regs[UART_MCR];
16 + regs[UART_MCR] = (UART_MCR_LOOP | 0x0a);
17 + // Fixme UART_MSR_DSR appears in status1
18 + status1 = regs[UART_MSR] & 0xd0;
19 + regs[UART_MCR] = save_mcr;
21 + return (status1 == (UART_MSR_DCD | UART_MSR_CTS));
24 static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
27 + u32 i, nr_ports = 0;
29 + /* Disable GPIO interrupt initially */
30 + extif_write32(dev, SSB_EXTIF_GPIO_INTPOL, 0);
31 + extif_write32(dev, SSB_EXTIF_GPIO_INTMASK, 0);
33 + for (i = 0; i < 2; i++) {
34 + void __iomem *uart_regs;
36 + uart_regs = ioremap_nocache(SSB_EUART, 16);
37 + uart_regs += (i * 8);
39 + if (serial_exists(uart_regs) && ports) {
40 + extif_write32(dev, SSB_EXTIF_GPIO_INTMASK, 2);
43 + ports[i].regs = uart_regs;
45 + ports[i].baud_base = 13500000;
46 + ports[i].reg_shift = 0;
56 struct ssb_bus *bus = mcore->dev->bus;
58 - //TODO if (EXTIF available
60 - extifregs_t *eir = (extifregs_t *) regs;
63 - /* Determine external UART register base */
64 - sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
65 - base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
70 - /* Disable GPIO interrupt initially */
71 - W_REG(&eir->gpiointpolarity, 0);
72 - W_REG(&eir->gpiointmask, 0);
74 - /* Search for external UARTs */
76 - for (i = 0; i < 2; i++) {
77 - regs = (void *) REG_MAP(base + (i * 8), 8);
78 - if (BCMINIT(serial_exists)(regs)) {
79 - /* Set GPIO 1 to be the external UART IRQ */
80 - W_REG(&eir->gpiointmask, 2);
82 - add(regs, irq, 13500000, 0);
86 - /* Add internal UART if enabled */
87 - if (R_REG(&eir->corecontrol) & CC_UE)
89 - add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
93 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
94 else if (bus->chipco.dev)
96 extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
99 -static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
100 +void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
101 u32 *pll_type, u32 *n, u32 *m)
103 *pll_type = SSB_PLLTYPE_1;
104 Index: linux-2.6.22-rc6/drivers/ssb/main.c
105 ===================================================================
106 --- linux-2.6.22-rc6.orig/drivers/ssb/main.c 2007-06-28 11:23:38.418344056 +0200
107 +++ linux-2.6.22-rc6/drivers/ssb/main.c 2007-06-28 12:07:50.346189744 +0200
108 @@ -774,12 +774,12 @@
110 u32 clkctl_n, clkctl_m;
112 - //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
114 - if (bus->chipco.dev) {
115 + if (bus->extif.dev)
116 + ssb_extif_get_clockcontrol(&bus->extif, &plltype, &clkctl_n, &clkctl_m);
117 + else if (bus->chipco.dev)
118 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
119 &clkctl_n, &clkctl_m);
124 if (bus->chip_id == 0x5365) {
125 Index: linux-2.6.22-rc6/include/linux/ssb/ssb_driver_extif.h
126 ===================================================================
127 --- linux-2.6.22-rc6.orig/include/linux/ssb/ssb_driver_extif.h 2007-06-28 11:27:47.099538768 +0200
128 +++ linux-2.6.22-rc6/include/linux/ssb/ssb_driver_extif.h 2007-06-28 11:28:03.482048248 +0200
131 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
133 +extern void ssb_extif_get_clockcontrol(struct ssb_extif *, u32 *, u32 *, u32 *);
136 static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
138 Index: linux-2.6.22-rc6/include/linux/ssb/ssb_regs.h
139 ===================================================================
140 --- linux-2.6.22-rc6.orig/include/linux/ssb/ssb_regs.h 2007-06-28 12:09:24.943808720 +0200
141 +++ linux-2.6.22-rc6/include/linux/ssb/ssb_regs.h 2007-06-28 12:09:34.606339792 +0200
143 #define SSB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
144 #define SSB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
145 #define SSB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
146 -#define SSB_EUART (SB_EXTIF_BASE + 0x00800000)
147 -#define SSB_LED (SB_EXTIF_BASE + 0x00900000)
148 +#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
149 +#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
152 /* Enumeration space constants */