GPIO code updates, make the cf-mips driver compile against this gpio version
[openwrt.git] / target / linux / rb532 / files / arch / mips / rb500 / gpio.c
1 /*
2 * Miscellaneous functions for IDT EB434 board
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Phil Sutter <n0-1@freewrt.org>
6 * Copyright 2007 Florian Fainelli <florian@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/init.h>
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/spinlock.h>
34 #include <linux/io.h>
35 #include <linux/platform_device.h>
36
37 #include <asm/addrspace.h>
38 #include <asm/gpio.h>
39
40 #include <asm/rc32434/rb.h>
41
42 #define GPIO_BADDR 0x18050000
43
44 static volatile unsigned char *devCtl3Base;
45 static unsigned char latchU5State;
46 static spinlock_t clu5Lock;
47
48 struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
49 EXPORT_SYMBOL(rb500_gpio_reg0);
50
51 static struct resource rb500_gpio_reg0_res[] = {
52 {
53 .name = "gpio_reg0",
54 .start = GPIO_BADDR,
55 .end = GPIO_BADDR + sizeof(struct rb500_gpio_reg),
56 .flags = IORESOURCE_MEM,
57 }
58 };
59
60 void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val)
61 {
62 unsigned flags, data;
63 unsigned i = 0;
64
65 spin_lock_irqsave(&clu5Lock, flags);
66 data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
67 for (i = 0; i != len; ++i) {
68 if (val & (1 << i))
69 data |= (1 << (i + bit));
70 else
71 data &= ~(1 << (i + bit));
72 }
73 *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
74 spin_unlock_irqrestore(&clu5Lock, flags);
75 }
76 EXPORT_SYMBOL(set434Reg);
77
78 void changeLatchU5(unsigned char orMask, unsigned char nandMask)
79 {
80 unsigned flags;
81
82 spin_lock_irqsave(&clu5Lock, flags);
83 latchU5State = (latchU5State | orMask) & ~nandMask;
84 if (!devCtl3Base)
85 devCtl3Base = (volatile unsigned char *)
86 KSEG1ADDR(*(volatile unsigned *)
87 KSEG1ADDR(0x18010030));
88 *devCtl3Base = latchU5State;
89 spin_unlock_irqrestore(&clu5Lock, flags);
90 }
91 EXPORT_SYMBOL(changeLatchU5);
92
93 unsigned char getLatchU5State(void)
94 {
95 return latchU5State;
96 }
97 EXPORT_SYMBOL(getLatchU5State);
98
99 int rb500_gpio_get_value(unsigned gpio)
100 {
101 return readl(&rb500_gpio_reg0->gpiod) & (1 << gpio);
102 }
103 EXPORT_SYMBOL(rb500_gpio_get_value);
104
105 void rb500_gpio_set_value(unsigned gpio, int value)
106 {
107 unsigned tmp;
108
109 tmp = readl(&rb500_gpio_reg0->gpiod) & ~(1 << gpio);
110 if (value)
111 tmp |= 1 << gpio;
112
113 writel(tmp, (void *)&rb500_gpio_reg0->gpiod);
114 }
115 EXPORT_SYMBOL(rb500_gpio_set_value);
116
117 int rb500_gpio_direction_input(unsigned gpio)
118 {
119 writel(readl(&rb500_gpio_reg0->gpiocfg) | (1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
120
121 return 0;
122 }
123 EXPORT_SYMBOL(rb500_gpio_direction_input);
124
125 int rb500_gpio_direction_output(unsigned gpio, int value)
126 {
127 gpio_set_value(gpio, value);
128 writel(readl(&rb500_gpio_reg0->gpiocfg) & ~(1 << gpio), (void *)&rb500_gpio_reg0->gpiocfg);
129
130 return 0;
131 }
132 EXPORT_SYMBOL(rb500_gpio_direction_output);
133
134 void rb500_gpio_set_int_level(unsigned gpio, int value)
135 {
136 unsigned tmp;
137
138 tmp = readl(&rb500_gpio_reg0->gpioilevel) & ~(1 << gpio);
139 if (value)
140 tmp |= 1 << gpio;
141 writel(tmp, (void *)&rb500_gpio_reg0->gpioilevel);
142 }
143 EXPORT_SYMBOL(rb500_gpio_set_int_level);
144
145 int rb500_gpio_get_int_level(unsigned gpio)
146 {
147 return readl(&rb500_gpio_reg0->gpioilevel) & (1 << gpio);
148 }
149 EXPORT_SYMBOL(rb500_gpio_get_int_level);
150
151 void rb500_gpio_set_int_status(unsigned gpio, int value)
152 {
153 unsigned tmp;
154
155 tmp = readl(&rb500_gpio_reg0->gpioistat);
156 if (value)
157 tmp |= 1 << gpio;
158 writel(tmp, (void *)&rb500_gpio_reg0->gpioistat);
159 }
160 EXPORT_SYMBOL(rb500_gpio_set_int_status);
161
162 int rb500_gpio_get_int_status(unsigned gpio)
163 {
164 return readl(&rb500_gpio_reg0->gpioistat) & (1 << gpio);
165 }
166 EXPORT_SYMBOL(rb500_gpio_get_int_status);
167
168 void rb500_gpio_set_func(unsigned gpio, int value)
169 {
170 unsigned tmp;
171
172 tmp = readl(&rb500_gpio_reg0->gpiofunc);
173 if (value)
174 tmp |= 1 << gpio;
175 writel(tmp, (void *)&rb500_gpio_reg0->gpiofunc);
176 }
177 EXPORT_SYMBOL(rb500_gpio_set_func);
178
179 int rb500_gpio_get_func(unsigned gpio)
180 {
181 return readl(&rb500_gpio_reg0->gpiofunc) & (1 << gpio);
182 }
183 EXPORT_SYMBOL(rb500_gpio_get_func);
184
185 int __init rb500_gpio_init(void)
186 {
187 rb500_gpio_reg0 = ioremap_nocache(rb500_gpio_reg0_res[0].start,
188 rb500_gpio_reg0_res[0].end -
189 rb500_gpio_reg0_res[0].start);
190
191 if (!rb500_gpio_reg0) {
192 printk(KERN_ERR "rb500: cannot remap GPIO register 0\n");
193 return -ENXIO;
194 }
195
196 return 0;
197 }
198 arch_initcall(rb500_gpio_init);
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