target/linux/adm8668/files/arch/mips/include/asm/mach-adm8668/adm8668.h

   1 /************************************************************************
   2  *
   3  *    Copyright (c) 2005
   4  *    Infineon Technologies AG
   5  *    St. Martin Strasse 53; 81669 Muenchen; Germany
   6  *
   7  ************************************************************************/
   8
   9 #ifndef  __ADM8668_H__
  10 #define  __ADM8668_H__
  11
  12 #define SYS_CLOCK               175000000
  13
  14 /*=======================  Physical Memory Map  ============================*/
  15 #define ADM8668_SDRAM_BASE      0
  16 #define ADM8668_SMEM1_BASE      0x10000000
  17 #define ADM8668_MPMC_BASE       0x11000000
  18 #define ADM8668_USB_BASE        0x11200000
  19 #define ADM8668_CONFIG_BASE     0x11400000
  20 #define ADM8668_WAN_BASE        0x11600000
  21 #define ADM8668_WLAN_BASE       0x11800000
  22 #define ADM8668_LAN_BASE        0x11A00000
  23 #define ADM8668_INTC_BASE       0x1E000000
  24 #define ADM8668_TMR_BASE        0x1E200000
  25 #define ADM8668_UART0_BASE      0x1E400000
  26 #define ADM8668_SMEM0_BASE      0x1FC00000
  27 #define ADM8668_NAND_BASE       0x1FFFFF00
  28
  29 #define PCICFG_BASE             0x12200000
  30 #define PCIDAT_BASE             0x12400000
  31
  32 /** onboard uart **/
  33 #define ADM8668_UARTCLK_FREQ    62500000
  34 /* registers */
  35 #define UART_DR_REG             0x00
  36 #define UART_RSR_REG            0x04
  37 #define UART_CR_REG             0x14
  38 #define UART_FR_REG             0x18
  39 #define UART_IIR_REG            0x1C
  40
  41 /* rsr reg */
  42 #define UART_FRAMING_ERR        0x01
  43 #define UART_PARITY_ERR         0x02
  44 #define UART_BREAK_ERR          0x04
  45 #define UART_OVERRUN_ERR        0x08
  46 #define UART_RX_STATUS_MASK     0x0F
  47
  48 /* cr reg */
  49 #define UART_RX_INT_EN          0x10
  50 #define UART_TX_INT_EN          0x20
  51 #define UART_RX_TIMEOUT_INT_EN  0x40
  52
  53 /* fr reg */
  54 #define UART_RX_FIFO_EMPTY      0x10
  55 #define UART_TX_FIFO_FULL       0x20
  56
  57 /* iir reg */
  58 #define UART_RX_INT             0x02
  59 #define UART_TX_INT             0x04
  60 #define UART_RX_TIMEOUT_INT     0x08
  61
  62 /* interrupt controller */
  63 #define IRQ_STATUS_REG          0x00    /* Read */
  64 #define IRQ_ENABLE_REG          0x08    /* Read/Write */
  65 #define IRQ_DISABLE_REG         0x0C    /* Write */
  66
  67 /* interrupt levels */
  68 #define INT_LVL_SWI             1
  69 #define INT_LVL_COMMS_RX        2
  70 #define INT_LVL_COMMS_TX        3
  71 #define INT_LVL_TIMERINT0       4
  72 #define INT_LVL_TIMERINT1       5
  73 #define INT_LVL_UART0           6
  74 #define INT_LVL_LAN             7
  75 #define INT_LVL_WAN             8
  76 #define INT_LVL_WLAN            9
  77 #define INT_LVL_GPIO            10
  78 #define INT_LVL_IDE             11
  79 #define INT_LVL_PCI2            12
  80 #define INT_LVL_PCI1            13
  81 #define INT_LVL_PCI0            14
  82 #define INT_LVL_USB             15
  83 #define INT_LVL_MAX             INT_LVL_USB
  84
  85 /* register access macros */
  86 #define ADM8668_INTC_REG(_reg)  \
  87         (*((volatile unsigned long *)(KSEG1ADDR(ADM8668_INTC_BASE + (_reg)))))
  88 #define ADM8668_LAN_REG(_reg)           \
  89         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
  90 #define ADM8668_WAN_REG(_reg)           \
  91         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WAN_BASE + (_reg)))))
  92 #define ADM8668_WLAN_REG(_reg)          \
  93         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WLAN_BASE + (_reg)))))
  94 #define ADM8668_CONFIG_REG(_reg)        \
  95         (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg)))))
  96
  97 /* lan registers */
  98 #define NETCSR6                 0x30
  99 #define NETCSR7                 0x38
 100 #define NETCSR37                0xF8
 101
 102 /* known/used CPU configuration registers */
 103 #define ADM8668_CR0             0x00
 104 #define ADM8668_CR1             0x04
 105 #define ADM8668_CR3             0x0C
 106
 107 /** For GPIO control **/
 108 #define GPIO_REG                0x5C    /* on WLAN */
 109 #define CRGPIO_REG              0x20    /* on CPU */
 110 #define GPIO0_OUTPUT_ENABLE     0x1000
 111 #define GPIO1_OUTPUT_ENABLE     0x2000
 112 #define GPIO2_OUTPUT_ENABLE     0x4000
 113 #define GPIO_OUTPUT_ENABLE_ALL  0x7000
 114 #define GPIO0_OUTPUT_1          0x40
 115 #define GPIO1_OUTPUT_1          0x80
 116 #define GPIO2_OUTPUT_1          0x100
 117 #define GPIO0_INPUT_1           0x1
 118 #define GPIO1_INPUT_1           0x2
 119 #define GPIO2_INPUT_1           0x4
 120
 121 #define GPIO_SET_HI(num)        \
 122         ADM8668_WLAN_REG(GPIO_REG) |= (1 << (6 + num))
 123
 124 #define GPIO_SET_LOW(num)       \
 125         ADM8668_WLAN_REG(GPIO_REG) &= ~(1 << (6 + num))
 126
 127 #define GPIO_TOGGLE(num)        \
 128         ADM8668_WLAN_REG(GPIO_REG) ^= (1 << (6 + num))
 129
 130 #define CRGPIO_SET_HI(num)      \
 131         ADM8668_CONFIG_REG(CRGPIO_REG) |= (1 << (6 + num))
 132
 133 #define CRGPIO_SET_LOW(num)     \
 134         ADM8668_CONFIG_REG(CRGPIO_REG) &= ~(1 << (6 + num))
 135
 136 #define CRGPIO_TOGGLE(num)      \
 137         ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
 138
 139 #endif /* __ADM8668_H__ */