target/linux/aruba-2.6/files/include/asm-mips/idt-boards/rc32434/rc32434_dma.h

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *   DMA register definition
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  *
  28  *
  29  **************************************************************************
  30  * May 2004 rkt, neb
  31  *
  32  * Initial Release
  33  *
  34  *
  35  *
  36  **************************************************************************
  37  */
  38
  39 #ifndef __IDT_DMA_H__
  40 #define __IDT_DMA_H__
  41
  42 enum
  43 {
  44         DMA0_PhysicalAddress    = 0x18040000,
  45         DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
  46
  47         DMA0_VirtualAddress     = 0xb8040000,
  48         DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
  49 } ;
  50
  51 /*
  52  * DMA descriptor (in physical memory).
  53  */
  54
  55 typedef struct DMAD_s
  56 {
  57         u32                     control ;       // Control. use DMAD_*
  58         u32                     ca ;            // Current Address.
  59         u32                     devcs ;         // Device control and status.
  60         u32                     link ;          // Next descriptor in chain.
  61 } volatile *DMAD_t ;
  62
  63 enum
  64 {
  65         DMAD_size               = sizeof (struct DMAD_s),
  66         DMAD_count_b            = 0,            // in DMAD_t -> control
  67         DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
  68         DMAD_ds_b               = 20,           // in DMAD_t -> control
  69         DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
  70                 DMAD_ds_ethRcv0_v       = 0,
  71                 DMAD_ds_ethXmt0_v       = 0,
  72                 DMAD_ds_memToFifo_v     = 0,
  73                 DMAD_ds_fifoToMem_v     = 0,
  74                 DMAD_ds_pciToMem_v      = 0,
  75                 DMAD_ds_memToPci_v      = 0,
  76
  77         DMAD_devcmd_b           = 22,           // in DMAD_t -> control
  78         DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
  79                 DMAD_devcmd_byte_v      = 0,    //memory-to-memory
  80                 DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
  81                 DMAD_devcmd_word_v      = 2,    //memory-to-memory
  82                 DMAD_devcmd_2words_v    = 3,    //memory-to-memory
  83                 DMAD_devcmd_4words_v    = 4,    //memory-to-memory
  84                 DMAD_devcmd_6words_v    = 5,    //memory-to-memory
  85                 DMAD_devcmd_8words_v    = 6,    //memory-to-memory
  86                 DMAD_devcmd_16words_v   = 7,    //memory-to-memory
  87         DMAD_cof_b              = 25,           // chain on finished
  88         DMAD_cof_m              = 0x02000000,   //
  89         DMAD_cod_b              = 26,           // chain on done
  90         DMAD_cod_m              = 0x04000000,   //
  91         DMAD_iof_b              = 27,           // interrupt on finished
  92         DMAD_iof_m              = 0x08000000,   //
  93         DMAD_iod_b              = 28,           // interrupt on done
  94         DMAD_iod_m              = 0x10000000,   //
  95         DMAD_t_b                = 29,           // terminated
  96         DMAD_t_m                = 0x20000000,   //
  97         DMAD_d_b                = 30,           // done
  98         DMAD_d_m                = 0x40000000,   //
  99         DMAD_f_b                = 31,           // finished
 100         DMAD_f_m                = 0x80000000,   //
 101 } ;
 102
 103 /*
 104  * DMA register (within Internal Register Map).
 105  */
 106
 107 struct DMA_Chan_s
 108 {
 109         u32             dmac ;          // Control.
 110         u32             dmas ;          // Status.
 111         u32             dmasm ;         // Mask.
 112         u32             dmadptr ;       // Descriptor pointer.
 113         u32             dmandptr ;      // Next descriptor pointer.
 114 };
 115
 116 typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
 117
 118 //DMA_Channels    use DMACH_count instead
 119
 120 enum
 121 {
 122         DMAC_run_b      = 0,            //
 123         DMAC_run_m      = 0x00000001,   //
 124         DMAC_dm_b       = 1,            // done mask
 125         DMAC_dm_m       = 0x00000002,   //
 126         DMAC_mode_b     = 2,            //
 127         DMAC_mode_m     = 0x0000000c,   //
 128                 DMAC_mode_auto_v        = 0,
 129                 DMAC_mode_burst_v       = 1,
 130                 DMAC_mode_transfer_v    = 2, //usually used
 131                 DMAC_mode_reserved_v    = 3,
 132         DMAC_a_b        = 4,            //
 133         DMAC_a_m        = 0x00000010,   //
 134
 135         DMAS_f_b        = 0,            // finished (sticky)
 136         DMAS_f_m        = 0x00000001,   //
 137         DMAS_d_b        = 1,            // done (sticky)
 138         DMAS_d_m        = 0x00000002,   //
 139         DMAS_c_b        = 2,            // chain (sticky)
 140         DMAS_c_m        = 0x00000004,   //
 141         DMAS_e_b        = 3,            // error (sticky)
 142         DMAS_e_m        = 0x00000008,   //
 143         DMAS_h_b        = 4,            // halt (sticky)
 144         DMAS_h_m        = 0x00000010,   //
 145
 146         DMASM_f_b       = 0,            // finished (1=mask)
 147         DMASM_f_m       = 0x00000001,   //
 148         DMASM_d_b       = 1,            // done (1=mask)
 149         DMASM_d_m       = 0x00000002,   //
 150         DMASM_c_b       = 2,            // chain (1=mask)
 151         DMASM_c_m       = 0x00000004,   //
 152         DMASM_e_b       = 3,            // error (1=mask)
 153         DMASM_e_m       = 0x00000008,   //
 154         DMASM_h_b       = 4,            // halt (1=mask)
 155         DMASM_h_m       = 0x00000010,   //
 156 } ;
 157
 158 /*
 159  * DMA channel definitions
 160  */
 161
 162 enum
 163 {
 164         DMACH_ethRcv0 = 0,
 165         DMACH_ethXmt0 = 1,
 166         DMACH_memToFifo = 2,
 167         DMACH_fifoToMem = 3,
 168         DMACH_pciToMem = 4,
 169         DMACH_memToPci = 5,
 170
 171         DMACH_count //must be last
 172 };
 173
 174
 175 typedef struct DMAC_s
 176 {
 177         struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
 178 } volatile *DMA_t ;
 179
 180
 181 /*
 182  * External DMA parameters
 183 */
 184
 185 enum
 186 {
 187         DMADEVCMD_ts_b  = 0,            // ts field in devcmd
 188         DMADEVCMD_ts_m  = 0x00000007,   // ts field in devcmd
 189                 DMADEVCMD_ts_byte_v     = 0,
 190                 DMADEVCMD_ts_halfword_v = 1,
 191                 DMADEVCMD_ts_word_v     = 2,
 192                 DMADEVCMD_ts_2word_v    = 3,
 193                 DMADEVCMD_ts_4word_v    = 4,
 194                 DMADEVCMD_ts_6word_v    = 5,
 195                 DMADEVCMD_ts_8word_v    = 6,
 196                 DMADEVCMD_ts_16word_v   = 7
 197 };
 198
 199
 200 #endif  // __IDT_DMA_H__
 201
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 205