2 * Hardware-specific definitions for
3 * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
5 * Copyright 2004, Broadcom Corporation
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 #ifndef _bcmenet_47xx_h_
16 #define _bcmenet_47xx_h_
21 #define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
22 #define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
23 #define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
24 #define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
26 /* power management event wakeup pattern constants */
27 #define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
28 #define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
29 #define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
30 #define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
31 #define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
33 /* cpp contortions to concatenate w/arg prescan */
35 #define _PADLINE(line) pad ## line
36 #define _XSTR(line) _PADLINE(line)
37 #define PAD _XSTR(__LINE__)
40 /* sometimes you just need the enet mib definitions */
41 #include <bcmenetmib.h>
44 * Host Interface Registers
46 typedef volatile struct _bcmenettregs
{
47 /* Device and Power Control */
54 /* Interrupt Control */
60 /* Ethernet MAC Address Filtering Control */
66 /* Ethernet MAC Control */
67 uint32 emactxmaxburstlen
;
68 uint32 emacrxmaxburstlen
;
70 uint32 emacflowcontrol
;
74 /* DMA Lazy Interrupt Control */
101 /* EMAC MIB counters */
106 /* Sonics SiliconBackplane config registers */
111 #define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
112 #define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
113 #define DC_ER ((uint32)1 << 15) /* ephy reset */
114 #define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
115 #define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
116 #define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
117 #define DC_PA_SHIFT 18
120 #define WL_P0_MASK 0x7f /* pattern 0 */
121 #define WL_D0 ((uint32)1 << 7)
122 #define WL_P1_MASK 0x7f00 /* pattern 1 */
123 #define WL_P1_SHIFT 8
124 #define WL_D1 ((uint32)1 << 15)
125 #define WL_P2_MASK 0x7f0000 /* pattern 2 */
126 #define WL_P2_SHIFT 16
127 #define WL_D2 ((uint32)1 << 23)
128 #define WL_P3_MASK 0x7f000000 /* pattern 3 */
129 #define WL_P3_SHIFT 24
130 #define WL_D3 ((uint32)1 << 31)
132 /* intstatus and intmask */
133 #define I_PME ((uint32)1 << 6) /* power management event */
134 #define I_TO ((uint32)1 << 7) /* general purpose timeout */
135 #define I_PC ((uint32)1 << 10) /* descriptor error */
136 #define I_PD ((uint32)1 << 11) /* data error */
137 #define I_DE ((uint32)1 << 12) /* descriptor protocol error */
138 #define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
139 #define I_RO ((uint32)1 << 14) /* receive fifo overflow */
140 #define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
141 #define I_RI ((uint32)1 << 16) /* receive interrupt */
142 #define I_XI ((uint32)1 << 24) /* transmit interrupt */
143 #define I_EM ((uint32)1 << 26) /* emac interrupt */
144 #define I_MW ((uint32)1 << 27) /* mii write */
145 #define I_MR ((uint32)1 << 28) /* mii read */
148 #define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
149 #define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
150 #define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
151 #define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
152 #define EMC_LC_SHIFT 5
154 /* emacflowcontrol */
155 #define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
156 #define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
158 /* interrupt receive lazy */
159 #define IRL_TO_MASK 0x00ffffff /* timeout */
160 #define IRL_FC_MASK 0xff000000 /* frame count */
161 #define IRL_FC_SHIFT 24 /* frame count */
163 /* emac receive config */
164 #define ERC_DB ((uint32)1 << 0) /* disable broadcast */
165 #define ERC_AM ((uint32)1 << 1) /* accept all multicast */
166 #define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
167 #define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
168 #define ERC_LE ((uint32)1 << 4) /* loopback enable */
169 #define ERC_FE ((uint32)1 << 5) /* enable flow control */
170 #define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
171 #define ERC_RF ((uint32)1 << 7) /* reject filter */
173 /* emac mdio control */
174 #define MC_MF_MASK 0x7f /* mdc frequency */
175 #define MC_PE ((uint32)1 << 7) /* mii preamble enable */
178 #define MD_DATA_MASK 0xffff /* r/w data */
179 #define MD_TA_MASK 0x30000 /* turnaround value */
180 #define MD_TA_SHIFT 16
181 #define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
182 #define MD_RA_MASK 0x7c0000 /* register address */
183 #define MD_RA_SHIFT 18
184 #define MD_PMD_MASK 0xf800000 /* physical media device */
185 #define MD_PMD_SHIFT 23
186 #define MD_OP_MASK 0x30000000 /* opcode */
187 #define MD_OP_SHIFT 28
188 #define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
189 #define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
190 #define MD_SB_MASK 0xc0000000 /* start bits */
191 #define MD_SB_SHIFT 30
192 #define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
194 /* emac intstatus and intmask */
195 #define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
196 #define EI_MIB ((uint32)1 << 1) /* mib interrupt */
197 #define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
199 /* emac cam data high */
200 #define CD_V ((uint32)1 << 16) /* valid bit */
202 /* emac cam control */
203 #define CC_CE ((uint32)1 << 0) /* cam enable */
204 #define CC_MS ((uint32)1 << 1) /* mask select */
205 #define CC_RD ((uint32)1 << 2) /* read */
206 #define CC_WR ((uint32)1 << 3) /* write */
207 #define CC_INDEX_MASK 0x3f0000 /* index */
208 #define CC_INDEX_SHIFT 16
209 #define CC_CB ((uint32)1 << 31) /* cam busy */
211 /* emac ethernet control */
212 #define EC_EE ((uint32)1 << 0) /* emac enable */
213 #define EC_ED ((uint32)1 << 1) /* emac disable */
214 #define EC_ES ((uint32)1 << 2) /* emac soft reset */
215 #define EC_EP ((uint32)1 << 3) /* external phy select */
217 /* emac transmit control */
218 #define EXC_FD ((uint32)1 << 0) /* full duplex */
219 #define EXC_FM ((uint32)1 << 1) /* flowmode */
220 #define EXC_SB ((uint32)1 << 2) /* single backoff enable */
221 #define EXC_SS ((uint32)1 << 3) /* small slottime */
223 /* emac mib control */
224 #define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
226 /* sometimes you just need the enet rxheader definitions */
227 #include <bcmenetrxh.h>
229 #endif /* _bcmenet_47xx_h_ */
This page took 0.05878 seconds and 5 git commands to generate.