2 * Generic Broadcom Home Networking Division (HND) DMA engine definitions.
3 * This supports the following chips: BCM42xx, 44xx, 47xx .
5 * Copyright 2004, Broadcom Corporation
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19 * Each DMA processor consists of a transmit channel and a receive channel.
21 typedef volatile struct {
22 /* transmit channel */
23 uint32 xmtcontrol
; /* enable, et al */
24 uint32 xmtaddr
; /* descriptor ring base address (4K aligned) */
25 uint32 xmtptr
; /* last descriptor posted to chip */
26 uint32 xmtstatus
; /* current active descriptor, et al */
29 uint32 rcvcontrol
; /* enable, et al */
30 uint32 rcvaddr
; /* descriptor ring base address (4K aligned) */
31 uint32 rcvptr
; /* last descriptor posted to chip */
32 uint32 rcvstatus
; /* current active descriptor, et al */
35 typedef volatile struct {
37 uint32 fifoaddr
; /* diag address */
38 uint32 fifodatalow
; /* low 32bits of data */
39 uint32 fifodatahigh
; /* high 32bits of data */
40 uint32 pad
; /* reserved */
43 /* transmit channel control */
44 #define XC_XE ((uint32)1 << 0) /* transmit enable */
45 #define XC_SE ((uint32)1 << 1) /* transmit suspend request */
46 #define XC_LE ((uint32)1 << 2) /* loopback enable */
47 #define XC_FL ((uint32)1 << 4) /* flush request */
49 /* transmit descriptor table pointer */
50 #define XP_LD_MASK 0xfff /* last valid descriptor */
52 /* transmit channel status */
53 #define XS_CD_MASK 0x0fff /* current descriptor pointer */
54 #define XS_XS_MASK 0xf000 /* transmit state */
55 #define XS_XS_SHIFT 12
56 #define XS_XS_DISABLED 0x0000 /* disabled */
57 #define XS_XS_ACTIVE 0x1000 /* active */
58 #define XS_XS_IDLE 0x2000 /* idle wait */
59 #define XS_XS_STOPPED 0x3000 /* stopped */
60 #define XS_XS_SUSP 0x4000 /* suspend pending */
61 #define XS_XE_MASK 0xf0000 /* transmit errors */
62 #define XS_XE_SHIFT 16
63 #define XS_XE_NOERR 0x00000 /* no error */
64 #define XS_XE_DPE 0x10000 /* descriptor protocol error */
65 #define XS_XE_DFU 0x20000 /* data fifo underrun */
66 #define XS_XE_BEBR 0x30000 /* bus error on buffer read */
67 #define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
68 #define XS_AD_MASK 0xfff00000 /* active descriptor */
69 #define XS_AD_SHIFT 20
71 /* receive channel control */
72 #define RC_RE ((uint32)1 << 0) /* receive enable */
73 #define RC_RO_MASK 0xfe /* receive frame offset */
75 #define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
77 /* receive descriptor table pointer */
78 #define RP_LD_MASK 0xfff /* last valid descriptor */
80 /* receive channel status */
81 #define RS_CD_MASK 0x0fff /* current descriptor pointer */
82 #define RS_RS_MASK 0xf000 /* receive state */
83 #define RS_RS_SHIFT 12
84 #define RS_RS_DISABLED 0x0000 /* disabled */
85 #define RS_RS_ACTIVE 0x1000 /* active */
86 #define RS_RS_IDLE 0x2000 /* idle wait */
87 #define RS_RS_STOPPED 0x3000 /* reserved */
88 #define RS_RE_MASK 0xf0000 /* receive errors */
89 #define RS_RE_SHIFT 16
90 #define RS_RE_NOERR 0x00000 /* no error */
91 #define RS_RE_DPE 0x10000 /* descriptor protocol error */
92 #define RS_RE_DFO 0x20000 /* data fifo overflow */
93 #define RS_RE_BEBW 0x30000 /* bus error on buffer write */
94 #define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
95 #define RS_AD_MASK 0xfff00000 /* active descriptor */
96 #define RS_AD_SHIFT 20
99 #define FA_OFF_MASK 0xffff /* offset */
100 #define FA_SEL_MASK 0xf0000 /* select */
101 #define FA_SEL_SHIFT 16
102 #define FA_SEL_XDD 0x00000 /* transmit dma data */
103 #define FA_SEL_XDP 0x10000 /* transmit dma pointers */
104 #define FA_SEL_RDD 0x40000 /* receive dma data */
105 #define FA_SEL_RDP 0x50000 /* receive dma pointers */
106 #define FA_SEL_XFD 0x80000 /* transmit fifo data */
107 #define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
108 #define FA_SEL_RFD 0xc0000 /* receive fifo data */
109 #define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
113 * Descriptors are only read by the hardware, never written back.
115 typedef volatile struct {
116 uint32 ctrl
; /* misc control bits & bufcount */
117 uint32 addr
; /* data buffer address */
121 * Each descriptor ring must be 4096byte aligned
122 * and fit within a single 4096byte page.
124 #define DMAMAXRINGSZ 4096
125 #define DMARINGALIGN 4096
128 #define CTRL_BC_MASK 0x1fff /* buffer byte count */
129 #define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
130 #define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
131 #define CTRL_EOF ((uint32)1 << 30) /* end of frame */
132 #define CTRL_SOF ((uint32)1 << 31) /* start of frame */
134 /* control flags in the range [27:20] are core-specific and not defined here */
135 #define CTRL_CORE_MASK 0x0ff00000
137 /* export structure */
138 typedef volatile struct {
139 /* rx error counters */
140 uint rxgiants
; /* rx giant frames */
141 uint rxnobuf
; /* rx out of dma descriptors */
142 /* tx error counters */
143 uint txnobuf
; /* tx out of dma descriptors */
151 extern void *dma_attach(void *drv
, void *dev
, char *name
, dmaregs_t
*dmaregs
,
152 uint ntxd
, uint nrxd
, uint rxbufsize
, uint nrxpost
, uint rxoffset
,
153 uint ddoffset
, uint dataoffset
, uint
*msg_level
);
154 extern void dma_detach(di_t
*di
);
155 extern void dma_txreset(di_t
*di
);
156 extern void dma_rxreset(di_t
*di
);
157 extern void dma_txinit(di_t
*di
);
158 extern bool dma_txenabled(di_t
*di
);
159 extern void dma_rxinit(di_t
*di
);
160 extern void dma_rxenable(di_t
*di
);
161 extern bool dma_rxenabled(di_t
*di
);
162 extern void dma_txsuspend(di_t
*di
);
163 extern void dma_txresume(di_t
*di
);
164 extern bool dma_txsuspended(di_t
*di
);
165 extern bool dma_txstopped(di_t
*di
);
166 extern bool dma_rxstopped(di_t
*di
);
167 extern int dma_txfast(di_t
*di
, void *p
, uint32 coreflags
);
168 extern int dma_tx(di_t
*di
, void *p
, uint32 coreflags
);
169 extern void dma_fifoloopbackenable(di_t
*di
);
170 extern void *dma_rx(di_t
*di
);
171 extern void dma_rxfill(di_t
*di
);
172 extern void dma_txreclaim(di_t
*di
, bool forceall
);
173 extern void dma_rxreclaim(di_t
*di
);
174 extern char *dma_dump(di_t
*di
, char *buf
);
175 extern char *dma_dumptx(di_t
*di
, char *buf
);
176 extern char *dma_dumprx(di_t
*di
, char *buf
);
177 extern uint
dma_getvar(di_t
*di
, char *name
);
178 extern void *dma_getnexttxp(di_t
*di
, bool forceall
);
179 extern void *dma_peeknexttxp(di_t
*di
);
180 extern void *dma_getnextrxp(di_t
*di
, bool forceall
);
181 extern void dma_txblock(di_t
*di
);
182 extern void dma_txunblock(di_t
*di
);
183 extern uint
dma_txactive(di_t
*di
);
184 extern void dma_txrotate(di_t
*di
);
186 #endif /* _hnddma_h_ */
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