2 * Hardware-specific External Interface I/O core definitions
3 * for the BCM47xx family of SiliconBackplane-based chips.
5 * The External Interface core supports a total of three external chip selects
6 * supporting external interfaces. One of the external chip selects is
7 * used for Flash, one is used for PCMCIA, and the other may be
8 * programmed to support either a synchronous interface or an
9 * asynchronous interface. The asynchronous interface can be used to
10 * support external devices such as UARTs and the BCM2019 Bluetooth
12 * The external interface core also contains 2 on-chip 16550 UARTs, clock
13 * frequency control, a watchdog interrupt timer, and a GPIO interface.
15 * Copyright 2004, Broadcom Corporation
16 * All Rights Reserved.
18 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
20 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
28 /* external interface address space */
29 #define EXTIF_PCMCIA_MEMBASE(x) (x)
30 #define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
31 #define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
32 #define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
33 #define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
35 /* cpp contortions to concatenate w/arg prescan */
37 #define _PADLINE(line) pad ## line
38 #define _XSTR(line) _PADLINE(line)
39 #define PAD _XSTR(__LINE__)
43 * The multiple instances of output and output enable registers
44 * are present to allow driver software for multiple cores to control
45 * gpio outputs without needing to share a single register pair.
53 typedef volatile struct {
58 /* pcmcia control registers */
60 uint32 pcmcia_memwait
;
61 uint32 pcmcia_attrwait
;
64 /* programmable interface control registers */
66 uint32 prog_waitcount
;
68 /* flash control registers */
70 uint32 flash_waitcount
;
76 uint32 clockcontrol_n
;
77 uint32 clockcontrol_sb
;
78 uint32 clockcontrol_pci
;
79 uint32 clockcontrol_mii
;
84 struct gpiouser gpio
[NGPIOUSER
];
87 uint32 gpiointpolarity
;
110 #define CC_UE (1 << 0) /* uart enable */
113 #define ES_EM (1 << 0) /* endian mode (ro) */
114 #define ES_EI (1 << 1) /* external interrupt pin (ro) */
115 #define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
118 #define GPIO_BIT0 (1 << 0)
119 #define GPIO_BIT1 (1 << 1)
120 #define GPIO_BIT2 (1 << 2)
121 #define GPIO_BIT3 (1 << 3)
122 #define GPIO_BIT4 (1 << 4)
123 #define GPIO_BIT5 (1 << 5)
124 #define GPIO_BIT6 (1 << 6)
125 #define GPIO_BIT7 (1 << 7)
128 /* pcmcia/prog/flash_config */
129 #define CF_EN (1 << 0) /* enable */
130 #define CF_EM_MASK 0xe /* mode */
131 #define CF_EM_SHIFT 1
132 #define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
133 #define CF_EM_SYNC 0x2 /* synchronous mode */
134 #define CF_EM_PCMCIA 0x4 /* pcmcia mode */
135 #define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
136 #define CF_BS (1 << 5) /* byteswap */
137 #define CF_CD_MASK 0xc0 /* clock divider */
138 #define CF_CD_SHIFT 6
139 #define CF_CD_DIV2 0x0 /* backplane/2 */
140 #define CF_CD_DIV3 0x40 /* backplane/3 */
141 #define CF_CD_DIV4 0x80 /* backplane/4 */
142 #define CF_CE (1 << 8) /* clock enable */
143 #define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
146 #define PM_W0_MASK 0x3f /* waitcount0 */
147 #define PM_W1_MASK 0x1f00 /* waitcount1 */
148 #define PM_W1_SHIFT 8
149 #define PM_W2_MASK 0x1f0000 /* waitcount2 */
150 #define PM_W2_SHIFT 16
151 #define PM_W3_MASK 0x1f000000 /* waitcount3 */
152 #define PM_W3_SHIFT 24
154 /* pcmcia_attrwait */
155 #define PA_W0_MASK 0x3f /* waitcount0 */
156 #define PA_W1_MASK 0x1f00 /* waitcount1 */
157 #define PA_W1_SHIFT 8
158 #define PA_W2_MASK 0x1f0000 /* waitcount2 */
159 #define PA_W2_SHIFT 16
160 #define PA_W3_MASK 0x1f000000 /* waitcount3 */
161 #define PA_W3_SHIFT 24
164 #define PI_W0_MASK 0x3f /* waitcount0 */
165 #define PI_W1_MASK 0x1f00 /* waitcount1 */
166 #define PI_W1_SHIFT 8
167 #define PI_W2_MASK 0x1f0000 /* waitcount2 */
168 #define PI_W2_SHIFT 16
169 #define PI_W3_MASK 0x1f000000 /* waitcount3 */
170 #define PI_W3_SHIFT 24
173 #define PW_W0_MASK 0x0000001f /* waitcount0 */
174 #define PW_W1_MASK 0x00001f00 /* waitcount1 */
175 #define PW_W1_SHIFT 8
176 #define PW_W2_MASK 0x001f0000 /* waitcount2 */
177 #define PW_W2_SHIFT 16
178 #define PW_W3_MASK 0x1f000000 /* waitcount3 */
179 #define PW_W3_SHIFT 24
181 #define PW_W0 0x0000000c
182 #define PW_W1 0x00000a00
183 #define PW_W2 0x00020000
184 #define PW_W3 0x01000000
186 /* flash_waitcount */
187 #define FW_W0_MASK 0x1f /* waitcount0 */
188 #define FW_W1_MASK 0x1f00 /* waitcount1 */
189 #define FW_W1_SHIFT 8
190 #define FW_W2_MASK 0x1f0000 /* waitcount2 */
191 #define FW_W2_SHIFT 16
192 #define FW_W3_MASK 0x1f000000 /* waitcount3 */
193 #define FW_W3_SHIFT 24
196 #define WATCHDOG_CLOCK 48000000 /* Hz */
199 #define CN_N1_MASK 0x3f /* n1 control */
200 #define CN_N2_MASK 0x3f00 /* n2 control */
201 #define CN_N2_SHIFT 8
203 /* clockcontrol_sb/pci/mii */
204 #define CC_M1_MASK 0x3f /* m1 control */
205 #define CC_M2_MASK 0x3f00 /* m2 control */
206 #define CC_M2_SHIFT 8
207 #define CC_M3_MASK 0x3f0000 /* m3 control */
208 #define CC_M3_SHIFT 16
209 #define CC_MC_MASK 0x1f000000 /* mux control */
210 #define CC_MC_SHIFT 24
212 /* Clock control default values */
213 #define CC_DEF_N 0x0009 /* Default values for bcm4710 */
214 #define CC_DEF_100 0x04020011
215 #define CC_DEF_33 0x11030011
216 #define CC_DEF_25 0x11050011
218 /* Clock control values for 125Mhz */
219 #define CC_125_N 0x0802
220 #define CC_125_M 0x04020009
221 #define CC_125_M25 0x11090009
222 #define CC_125_M33 0x11090005
224 /* Clock control magic field values */
225 #define CC_F6_2 0x02 /* A factor of 2 in */
226 #define CC_F6_3 0x03 /* 6-bit fields like */
227 #define CC_F6_4 0x05 /* N1, M1 or M3 */
232 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
234 #define CC_MC_BYPASS 0x08
235 #define CC_MC_M1 0x04
236 #define CC_MC_M1M2 0x02
237 #define CC_MC_M1M2M3 0x01
238 #define CC_MC_M1M3 0x11
240 #define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
242 #endif /* _SBEXTIF_H */
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