2 * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
4 * Copyright 2004, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18 #ifdef _LANGUAGE_ASSEMBLY
20 #define MEMC_CONTROL 0x00
21 #define MEMC_CONFIG 0x04
22 #define MEMC_REFRESH 0x08
23 #define MEMC_BISTSTAT 0x0c
24 #define MEMC_MODEBUF 0x10
25 #define MEMC_BKCLS 0x14
26 #define MEMC_PRIORINV 0x18
27 #define MEMC_DRAMTIM 0x1c
28 #define MEMC_INTSTAT 0x20
29 #define MEMC_INTMASK 0x24
30 #define MEMC_INTINFO 0x28
31 #define MEMC_NCDLCTL 0x30
32 #define MEMC_RDNCDLCOR 0x34
33 #define MEMC_WRNCDLCOR 0x38
34 #define MEMC_MISCDLYCTL 0x3c
35 #define MEMC_DQSGATENCDL 0x40
36 #define MEMC_SPARE 0x44
37 #define MEMC_TPADDR 0x48
38 #define MEMC_TPDATA 0x4c
39 #define MEMC_BARRIER 0x50
40 #define MEMC_CORE 0x54
45 /* Sonics side: MEMC core registers */
46 typedef volatile struct sbmemcregs
{
73 /* MEMC Core Init values (OCP ID 0x80f) */
76 #define MEMC_SD_CONFIG_INIT 0x00048000
77 #define MEMC_SD_DRAMTIM2_INIT 0x000754d8
78 #define MEMC_SD_DRAMTIM3_INIT 0x000754da
79 #define MEMC_SD_RDNCDLCOR_INIT 0x00000000
80 #define MEMC_SD_WRNCDLCOR_INIT 0x49351200
81 #define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
82 #define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
83 #define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
84 #define MEMC_SD_CONTROL_INIT0 0x00000002
85 #define MEMC_SD_CONTROL_INIT1 0x00000008
86 #define MEMC_SD_CONTROL_INIT2 0x00000004
87 #define MEMC_SD_CONTROL_INIT3 0x00000010
88 #define MEMC_SD_CONTROL_INIT4 0x00000001
89 #define MEMC_SD_MODEBUF_INIT 0x00000000
90 #define MEMC_SD_REFRESH_INIT 0x0000840f
93 /* This is for SDRM8X8X4 */
94 #define MEMC_SDR_INIT 0x0008
95 #define MEMC_SDR_MODE 0x32
96 #define MEMC_SDR_NCDL 0x00020032
97 #define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
100 #define MEMC_CONFIG_INIT 0x00048000
101 #define MEMC_DRAMTIM2_INIT 0x000754d8
102 #define MEMC_DRAMTIM25_INIT 0x000754d9
103 #define MEMC_RDNCDLCOR_INIT 0x00000000
104 #define MEMC_WRNCDLCOR_INIT 0x49351200
105 #define MEMC_1_WRNCDLCOR_INIT 0x14500200
106 #define MEMC_DQSGATENCDL_INIT 0x00030000
107 #define MEMC_MISCDLYCTL_INIT 0x21061c1b
108 #define MEMC_1_MISCDLYCTL_INIT 0x21021400
109 #define MEMC_NCDLCTL_INIT 0x00002001
110 #define MEMC_CONTROL_INIT0 0x00000002
111 #define MEMC_CONTROL_INIT1 0x00000008
112 #define MEMC_MODEBUF_INIT0 0x00004000
113 #define MEMC_CONTROL_INIT2 0x00000010
114 #define MEMC_MODEBUF_INIT1 0x00000100
115 #define MEMC_CONTROL_INIT3 0x00000010
116 #define MEMC_CONTROL_INIT4 0x00000008
117 #define MEMC_REFRESH_INIT 0x0000840f
118 #define MEMC_CONTROL_INIT5 0x00000004
119 #define MEMC_MODEBUF_INIT2 0x00000000
120 #define MEMC_CONTROL_INIT6 0x00000010
121 #define MEMC_CONTROL_INIT7 0x00000001
124 /* This is for DDRM16X16X2 */
125 #define MEMC_DDR_INIT 0x0009
126 #define MEMC_DDR_MODE 0x62
127 #define MEMC_DDR_NCDL 0x0005050a
128 #define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
130 /* mask for sdr/ddr calibration registers */
131 #define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
132 #define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
133 #define MEMC_DQSGATENCDL_G_MASK 0x000000ff
135 /* masks for miscdlyctl registers */
136 #define MEMC_MISC_SM_MASK 0x30000000
137 #define MEMC_MISC_SM_SHIFT 28
138 #define MEMC_MISC_SD_MASK 0x0f000000
139 #define MEMC_MISC_SD_SHIFT 24
141 /* hw threshhold for calculating wr/rd for sdr memc */
142 #define MEMC_CD_THRESHOLD 128
144 /* Low bit of init register says if memc is ddr or sdr */
145 #define MEMC_CONFIG_DDR 0x00000001
147 #endif /* _SBMEMC_H */
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