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[adm5120] more USB driver fixes, now it passes usbtests 1-14
[openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-q.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10 #include <linux/irq.h>
11
12 /*-------------------------------------------------------------------------*/
13
14 /*
15 * URB goes back to driver, and isn't reissued.
16 * It's completely gone from HC data structures.
17 * PRECONDITION: ahcd lock held, irqs blocked.
18 */
19 static void
20 finish_urb(struct admhcd *ahcd, struct urb *urb)
21 __releases(ahcd->lock)
22 __acquires(ahcd->lock)
23 {
24 urb_priv_free(ahcd, urb->hcpriv);
25 urb->hcpriv = NULL;
26
27 spin_lock(&urb->lock);
28 if (likely(urb->status == -EINPROGRESS))
29 urb->status = 0;
30
31 /* report short control reads right even though the data TD always
32 * has TD_R set. (much simpler, but creates the 1-td limit.)
33 */
34 if (unlikely(urb->transfer_flags & URB_SHORT_NOT_OK)
35 && unlikely(usb_pipecontrol(urb->pipe))
36 && urb->actual_length < urb->transfer_buffer_length
37 && usb_pipein(urb->pipe)
38 && urb->status == 0) {
39 urb->status = -EREMOTEIO;
40 #ifdef ADMHC_VERBOSE_DEBUG
41 urb_print(ahcd, urb, "SHORT", usb_pipeout(urb->pipe));
42 #endif
43 }
44 spin_unlock(&urb->lock);
45
46 switch (usb_pipetype(urb->pipe)) {
47 case PIPE_ISOCHRONOUS:
48 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
49 break;
50 case PIPE_INTERRUPT:
51 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
52 break;
53 }
54
55 #ifdef ADMHC_VERBOSE_DEBUG
56 urb_print(ahcd, urb, "RET", usb_pipeout (urb->pipe));
57 #endif
58
59 /* urb->complete() can reenter this HCD */
60 spin_unlock(&ahcd->lock);
61 usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb);
62 spin_lock(&ahcd->lock);
63 }
64
65
66 /*-------------------------------------------------------------------------*
67 * ED handling functions
68 *-------------------------------------------------------------------------*/
69
70 #if 0 /* FIXME */
71 /* search for the right schedule branch to use for a periodic ed.
72 * does some load balancing; returns the branch, or negative errno.
73 */
74 static int balance(struct admhcd *ahcd, int interval, int load)
75 {
76 int i, branch = -ENOSPC;
77
78 /* iso periods can be huge; iso tds specify frame numbers */
79 if (interval > NUM_INTS)
80 interval = NUM_INTS;
81
82 /* search for the least loaded schedule branch of that period
83 * that has enough bandwidth left unreserved.
84 */
85 for (i = 0; i < interval ; i++) {
86 if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
87 int j;
88
89 /* usb 1.1 says 90% of one frame */
90 for (j = i; j < NUM_INTS; j += interval) {
91 if ((ahcd->load [j] + load) > 900)
92 break;
93 }
94 if (j < NUM_INTS)
95 continue;
96 branch = i;
97 }
98 }
99 return branch;
100 }
101 #endif
102
103 /*-------------------------------------------------------------------------*/
104
105 #if 0 /* FIXME */
106 /* both iso and interrupt requests have periods; this routine puts them
107 * into the schedule tree in the apppropriate place. most iso devices use
108 * 1msec periods, but that's not required.
109 */
110 static void periodic_link (struct admhcd *ahcd, struct ed *ed)
111 {
112 unsigned i;
113
114 admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
115 (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
116 ed, ed->branch, ed->load, ed->interval);
117
118 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
119 struct ed **prev = &ahcd->periodic [i];
120 __hc32 *prev_p = &ahcd->hcca->int_table [i];
121 struct ed *here = *prev;
122
123 /* sorting each branch by period (slow before fast)
124 * lets us share the faster parts of the tree.
125 * (plus maybe: put interrupt eds before iso)
126 */
127 while (here && ed != here) {
128 if (ed->interval > here->interval)
129 break;
130 prev = &here->ed_next;
131 prev_p = &here->hwNextED;
132 here = *prev;
133 }
134 if (ed != here) {
135 ed->ed_next = here;
136 if (here)
137 ed->hwNextED = *prev_p;
138 wmb ();
139 *prev = ed;
140 *prev_p = cpu_to_hc32(ahcd, ed->dma);
141 wmb();
142 }
143 ahcd->load [i] += ed->load;
144 }
145 admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
146 }
147 #endif
148
149 /* link an ed into the HC chain */
150
151 static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
152 {
153 struct ed *old_tail;
154
155 if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
156 return -EAGAIN;
157
158 ed->state = ED_OPER;
159
160 old_tail = ahcd->ed_tails[ed->type];
161
162 ed->ed_next = old_tail->ed_next;
163 if (ed->ed_next) {
164 ed->ed_next->ed_prev = ed;
165 ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
166 }
167 ed->ed_prev = old_tail;
168
169 old_tail->ed_next = ed;
170 old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
171
172 ahcd->ed_tails[ed->type] = ed;
173
174 admhc_dma_enable(ahcd);
175
176 return 0;
177 }
178
179 /*-------------------------------------------------------------------------*/
180
181 #if 0 /* FIXME */
182 /* scan the periodic table to find and unlink this ED */
183 static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
184 {
185 int i;
186
187 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
188 struct ed *temp;
189 struct ed **prev = &ahcd->periodic [i];
190 __hc32 *prev_p = &ahcd->hcca->int_table [i];
191
192 while (*prev && (temp = *prev) != ed) {
193 prev_p = &temp->hwNextED;
194 prev = &temp->ed_next;
195 }
196 if (*prev) {
197 *prev_p = ed->hwNextED;
198 *prev = ed->ed_next;
199 }
200 ahcd->load [i] -= ed->load;
201 }
202
203 admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
204 admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
205 (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
206 ed, ed->branch, ed->load, ed->interval);
207 }
208 #endif
209
210 /* unlink an ed from the HC chain.
211 * just the link to the ed is unlinked.
212 * the link from the ed still points to another operational ed or 0
213 * so the HC can eventually finish the processing of the unlinked ed
214 * (assuming it already started that, which needn't be true).
215 *
216 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
217 * it won't. ED_SKIP means the HC will finish its current transaction,
218 * but won't start anything new. The TD queue may still grow; device
219 * drivers don't know about this HCD-internal state.
220 *
221 * When the HC can't see the ED, something changes ED_UNLINK to one of:
222 *
223 * - ED_OPER: when there's any request queued, the ED gets rescheduled
224 * immediately. HC should be working on them.
225 *
226 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
227 * to care about this ED; safe to disable the endpoint.
228 *
229 * When finish_unlinks() runs later, after SOF interrupt, it will often
230 * complete one or more URB unlinks before making that state change.
231 */
232 static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
233 {
234
235 #ifdef ADMHC_VERBOSE_DEBUG
236 admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
237 #endif
238
239 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
240 wmb();
241 ed->state = ED_UNLINK;
242
243 /* remove this ED from the HC list */
244 ed->ed_prev->hwNextED = ed->hwNextED;
245
246 /* and remove it from our list also */
247 ed->ed_prev->ed_next = ed->ed_next;
248
249 if (ed->ed_next)
250 ed->ed_next->ed_prev = ed->ed_prev;
251
252 if (ahcd->ed_tails[ed->type] == ed)
253 ahcd->ed_tails[ed->type] = ed->ed_prev;
254 }
255
256 /*-------------------------------------------------------------------------*/
257
258 static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
259 {
260 struct ed *ed;
261 struct td *td;
262
263 ed = ed_alloc(ahcd, GFP_ATOMIC);
264 if (!ed)
265 goto err;
266
267 /* dummy td; end of td list for this ed */
268 td = td_alloc(ahcd, GFP_ATOMIC);
269 if (!td)
270 goto err_free_ed;
271
272 switch (type) {
273 case PIPE_INTERRUPT:
274 info |= ED_INT;
275 break;
276 case PIPE_ISOCHRONOUS:
277 info |= ED_ISO;
278 break;
279 }
280
281 ed->dummy = td;
282 ed->state = ED_IDLE;
283 ed->type = type;
284
285 ed->hwINFO = cpu_to_hc32(ahcd, info);
286 ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
287 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
288
289 return ed;
290
291 err_free_ed:
292 ed_free(ahcd, ed);
293 err:
294 return NULL;
295 }
296
297 /* get and maybe (re)init an endpoint. init _should_ be done only as part
298 * of enumeration, usb_set_configuration() or usb_set_interface().
299 */
300 static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
301 struct usb_device *udev, unsigned int pipe, int interval)
302 {
303 struct ed *ed;
304 unsigned long flags;
305
306 spin_lock_irqsave(&ahcd->lock, flags);
307
308 ed = ep->hcpriv;
309 if (!ed) {
310 u32 info;
311
312 /* FIXME: usbcore changes dev->devnum before SET_ADDRESS
313 * suceeds ... otherwise we wouldn't need "pipe".
314 */
315 info = usb_pipedevice(pipe);
316 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
317 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
318 if (udev->speed == USB_SPEED_FULL)
319 info |= ED_SPEED_FULL;
320
321 ed = ed_create(ahcd, usb_pipetype(pipe), info);
322 if (ed)
323 ep->hcpriv = ed;
324 }
325
326 spin_unlock_irqrestore(&ahcd->lock, flags);
327
328 return ed;
329 }
330
331 /*-------------------------------------------------------------------------*/
332
333 /* request unlinking of an endpoint from an operational HC.
334 * put the ep on the rm_list
335 * real work is done at the next start frame (SOFI) hardware interrupt
336 * caller guarantees HCD is running, so hardware access is safe,
337 * and that ed->state is ED_OPER
338 */
339 static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
340 {
341
342 #ifdef ADMHC_VERBOSE_DEBUG
343 admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
344 #endif
345
346 ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
347 ed_deschedule(ahcd, ed);
348
349 /* add this ED into the remove list */
350 ed->ed_rm_next = ahcd->ed_rm_list;
351 ahcd->ed_rm_list = ed;
352
353 /* enable SOF interrupt */
354 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
355 admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
356 /* flush those writes */
357 admhc_writel_flush(ahcd);
358
359 /* SOF interrupt might get delayed; record the frame counter value that
360 * indicates when the HC isn't looking at it, so concurrent unlinks
361 * behave. frame_no wraps every 2^16 msec, and changes right before
362 * SOF is triggered.
363 */
364 ed->tick = admhc_frame_no(ahcd) + 1;
365 }
366
367 /*-------------------------------------------------------------------------*
368 * TD handling functions
369 *-------------------------------------------------------------------------*/
370
371 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
372
373 static void
374 td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
375 struct urb *urb, int index)
376 {
377 struct td *td, *td_pt;
378 struct urb_priv *urb_priv = urb->hcpriv;
379 int hash;
380 u32 cbl = 0;
381
382 #if 1
383 if (index == (urb_priv->td_cnt - 1) &&
384 ((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
385 cbl |= TD_IE;
386 #else
387 if (index == (urb_priv->td_cnt - 1))
388 cbl |= TD_IE;
389 #endif
390
391 /* use this td as the next dummy */
392 td_pt = urb_priv->td[index];
393
394 /* fill the old dummy TD */
395 td = urb_priv->td[index] = urb_priv->ed->dummy;
396 urb_priv->ed->dummy = td_pt;
397
398 td->ed = urb_priv->ed;
399 td->next_dl_td = NULL;
400 td->index = index;
401 td->urb = urb;
402 td->data_dma = data;
403 if (!len)
404 data = 0;
405
406 if (data)
407 cbl |= (len & TD_BL_MASK);
408
409 info |= TD_OWN;
410
411 /* setup hardware specific fields */
412 td->hwINFO = cpu_to_hc32(ahcd, info);
413 td->hwDBP = cpu_to_hc32(ahcd, data);
414 td->hwCBL = cpu_to_hc32(ahcd, cbl);
415 td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
416
417 /* append to queue */
418 list_add_tail(&td->td_list, &td->ed->td_list);
419
420 /* hash it for later reverse mapping */
421 hash = TD_HASH_FUNC(td->td_dma);
422 td->td_hash = ahcd->td_hash[hash];
423 ahcd->td_hash[hash] = td;
424
425 /* HC might read the TD (or cachelines) right away ... */
426 wmb();
427 td->ed->hwTailP = td->hwNextTD;
428 }
429
430 /*-------------------------------------------------------------------------*/
431
432 /* Prepare all TDs of a transfer, and queue them onto the ED.
433 * Caller guarantees HC is active.
434 * Usually the ED is already on the schedule, so TDs might be
435 * processed as soon as they're queued.
436 */
437 static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
438 {
439 struct urb_priv *urb_priv = urb->hcpriv;
440 dma_addr_t data;
441 int data_len = urb->transfer_buffer_length;
442 int cnt = 0;
443 u32 info = 0;
444 int is_out = usb_pipeout(urb->pipe);
445 u32 toggle = 0;
446
447 /* OHCI handles the bulk/interrupt data toggles itself. We just
448 * use the device toggle bits for resetting, and rely on the fact
449 * that resetting toggle is meaningless if the endpoint is active.
450 */
451
452 if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
453 toggle = TD_T_CARRY;
454 } else {
455 toggle = TD_T_DATA0;
456 usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
457 is_out, 1);
458 }
459
460 urb_priv->td_idx = 0;
461 list_add(&urb_priv->pending, &ahcd->pending);
462
463 if (data_len)
464 data = urb->transfer_dma;
465 else
466 data = 0;
467
468 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
469 * using TD_CC_GET, as well as by seeing them on the done list.
470 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
471 */
472 switch (urb_priv->ed->type) {
473 case PIPE_INTERRUPT:
474 info = is_out
475 ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
476 : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
477
478 /* setup service interval and starting frame number */
479 info |= (urb->start_frame & TD_FN_MASK);
480 info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
481
482 td_fill(ahcd, info, data, data_len, urb, cnt);
483 cnt++;
484
485 admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
486 break;
487
488 case PIPE_BULK:
489 info = is_out
490 ? TD_SCC_NOTACCESSED | TD_DP_OUT
491 : TD_SCC_NOTACCESSED | TD_DP_IN;
492
493 /* TDs _could_ transfer up to 8K each */
494 while (data_len > TD_DATALEN_MAX) {
495 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
496 data, TD_DATALEN_MAX, urb, cnt);
497 data += TD_DATALEN_MAX;
498 data_len -= TD_DATALEN_MAX;
499 cnt++;
500 }
501
502 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
503 data_len, urb, cnt);
504 cnt++;
505
506 if ((urb->transfer_flags & URB_ZERO_PACKET)
507 && (cnt < urb_priv->td_cnt)) {
508 td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
509 0, 0, urb, cnt);
510 cnt++;
511 }
512 break;
513
514 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
515 * any DATA phase works normally, and the STATUS ack is special.
516 */
517 case PIPE_CONTROL:
518 /* fill a TD for the setup */
519 info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
520 td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
521
522 if (data_len > 0) {
523 /* fill a TD for the data */
524 info = TD_SCC_NOTACCESSED | TD_T_DATA1;
525 info |= is_out ? TD_DP_OUT : TD_DP_IN;
526 /* NOTE: mishandles transfers >8K, some >4K */
527 td_fill(ahcd, info, data, data_len, urb, cnt++);
528 }
529
530 /* fill a TD for the ACK */
531 info = (is_out || data_len == 0)
532 ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
533 : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
534 td_fill(ahcd, info, data, 0, urb, cnt++);
535
536 break;
537
538 /* ISO has no retransmit, so no toggle;
539 * Each TD could handle multiple consecutive frames (interval 1);
540 * we could often reduce the number of TDs here.
541 */
542 case PIPE_ISOCHRONOUS:
543 info = TD_SCC_NOTACCESSED;
544 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
545 int frame = urb->start_frame;
546
547 frame += cnt * urb->interval;
548 frame &= TD_FN_MASK;
549 td_fill(ahcd, info | frame,
550 data + urb->iso_frame_desc[cnt].offset,
551 urb->iso_frame_desc[cnt].length, urb, cnt);
552 }
553 admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
554 break;
555 }
556
557 if (urb_priv->td_cnt != cnt)
558 admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
559 }
560
561 /*-------------------------------------------------------------------------*
562 * Done List handling functions
563 *-------------------------------------------------------------------------*/
564
565 /* calculate transfer length/status and update the urb
566 * PRECONDITION: irqsafe (only for urb->status locking)
567 */
568 static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
569 {
570 struct urb_priv *urb_priv = urb->hcpriv;
571 u32 info = hc32_to_cpup(ahcd, &td->hwINFO);
572 int type = usb_pipetype(urb->pipe);
573 int cc;
574
575 cc = TD_CC_GET(info);
576
577 /* ISO ... drivers see per-TD length/status */
578 if (type == PIPE_ISOCHRONOUS) {
579 #if 0
580 /* TODO */
581 int dlen = 0;
582
583 /* NOTE: assumes FC in tdINFO == 0, and that
584 * only the first of 0..MAXPSW psws is used.
585 */
586
587 cc = TD_CC_GET(td);
588 if (tdINFO & TD_CC) /* hc didn't touch? */
589 return;
590
591 if (usb_pipeout (urb->pipe))
592 dlen = urb->iso_frame_desc [td->index].length;
593 else {
594 /* short reads are always OK for ISO */
595 if (cc == TD_DATAUNDERRUN)
596 cc = TD_CC_NOERROR;
597 dlen = tdPSW & 0x3ff;
598 }
599 urb->actual_length += dlen;
600 urb->iso_frame_desc [td->index].actual_length = dlen;
601 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
602
603 if (cc != TD_CC_NOERROR)
604 admhc_vdbg (ahcd,
605 "urb %p iso td %p (%d) len %d cc %d\n",
606 urb, td, 1 + td->index, dlen, cc);
607 #endif
608 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
609 * except that "setup" bytes aren't counted and "short" transfers
610 * might not be reported as errors.
611 */
612 } else {
613 u32 bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
614 u32 tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
615
616 /* update packet status if needed (short is normally ok) */
617 if (cc == TD_CC_DATAUNDERRUN
618 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
619 cc = TD_CC_NOERROR;
620
621 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) {
622 spin_lock(&urb->lock);
623 if (urb->status == -EINPROGRESS)
624 urb->status = cc_to_error[cc];
625 spin_unlock(&urb->lock);
626 }
627
628 /* count all non-empty packets except control SETUP packet */
629 if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
630 urb->actual_length += tdDBP - td->data_dma + bl;
631 }
632
633 if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
634 admhc_vdbg(ahcd,
635 "urb %p td %p (%d) cc %d, len=%d/%d\n",
636 urb, td, td->index, cc,
637 urb->actual_length,
638 urb->transfer_buffer_length);
639 }
640
641 list_del(&td->td_list);
642 urb_priv->td_idx++;
643
644 return cc;
645 }
646
647 /*-------------------------------------------------------------------------*/
648
649 static inline struct td *
650 ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
651 {
652 struct urb *urb = td->urb;
653 struct ed *ed = td->ed;
654 struct list_head *tmp = td->td_list.next;
655 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
656
657 admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
658 /* clear ed halt; this is the td that caused it, but keep it inactive
659 * until its urb->complete() has a chance to clean up.
660 */
661 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
662 wmb();
663 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
664
665 /* put any later tds from this urb onto the donelist, after 'td',
666 * order won't matter here: no errors, and nothing was transferred.
667 * also patch the ed so it looks as if those tds completed normally.
668 */
669 while (tmp != &ed->td_list) {
670 struct td *next;
671 __hc32 info;
672
673 next = list_entry(tmp, struct td, td_list);
674 tmp = next->td_list.next;
675
676 if (next->urb != urb)
677 break;
678
679 /* NOTE: if multi-td control DATA segments get supported,
680 * this urb had one of them, this td wasn't the last td
681 * in that segment (TD_R clear), this ed halted because
682 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
683 * then we need to leave the control STATUS packet queued
684 * and clear ED_SKIP.
685 */
686 info = next->hwINFO;
687 #if 0 /* FIXME */
688 info |= cpu_to_hc32(ahcd, TD_DONE);
689 #endif
690 info &= ~cpu_to_hc32(ahcd, TD_CC);
691 next->hwINFO = info;
692
693 next->next_dl_td = rev;
694 rev = next;
695
696 ed->hwHeadP = next->hwNextTD | toggle;
697 }
698
699 /* help for troubleshooting: report anything that
700 * looks odd ... that doesn't include protocol stalls
701 * (or maybe some other things)
702 */
703 switch (cc) {
704 case TD_CC_DATAUNDERRUN:
705 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
706 break;
707 /* fallthrough */
708 case TD_CC_STALL:
709 if (usb_pipecontrol(urb->pipe))
710 break;
711 /* fallthrough */
712 default:
713 admhc_dbg (ahcd,
714 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
715 urb, urb->dev->devpath,
716 usb_pipeendpoint (urb->pipe),
717 usb_pipein (urb->pipe) ? "in" : "out",
718 hc32_to_cpu(ahcd, td->hwINFO),
719 cc, cc_to_error [cc]);
720 }
721
722 return rev;
723 }
724
725 /*-------------------------------------------------------------------------*/
726
727 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
728 static void
729 finish_unlinks(struct admhcd *ahcd, u16 tick)
730 {
731 struct ed *ed, **last;
732
733 rescan_all:
734 for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
735 struct list_head *entry, *tmp;
736 int completed, modified;
737 __hc32 *prev;
738
739 /* only take off EDs that the HC isn't using, accounting for
740 * frame counter wraps and EDs with partially retired TDs
741 */
742 if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
743 if (tick_before (tick, ed->tick)) {
744 skip_ed:
745 last = &ed->ed_rm_next;
746 continue;
747 }
748 #if 0
749 if (!list_empty(&ed->td_list)) {
750 struct td *td;
751 u32 head;
752
753 td = list_entry(ed->td_list.next, struct td,
754 td_list);
755 head = hc32_to_cpu(ahcd, ed->hwHeadP) &
756 TD_MASK;
757
758 /* INTR_WDH may need to clean up first */
759 if (td->td_dma != head)
760 goto skip_ed;
761 }
762 #endif
763 }
764
765 /* reentrancy: if we drop the schedule lock, someone might
766 * have modified this list. normally it's just prepending
767 * entries (which we'd ignore), but paranoia won't hurt.
768 */
769 *last = ed->ed_rm_next;
770 ed->ed_rm_next = NULL;
771 modified = 0;
772
773 /* unlink urbs as requested, but rescan the list after
774 * we call a completion since it might have unlinked
775 * another (earlier) urb
776 *
777 * When we get here, the HC doesn't see this ed. But it
778 * must not be rescheduled until all completed URBs have
779 * been given back to the driver.
780 */
781 rescan_this:
782 completed = 0;
783 prev = &ed->hwHeadP;
784 list_for_each_safe(entry, tmp, &ed->td_list) {
785 struct td *td;
786 struct urb *urb;
787 struct urb_priv *urb_priv;
788 __hc32 savebits;
789
790 td = list_entry(entry, struct td, td_list);
791 urb = td->urb;
792 urb_priv = td->urb->hcpriv;
793
794 if (urb->status == -EINPROGRESS) {
795 prev = &td->hwNextTD;
796 continue;
797 }
798
799 if ((urb_priv) == NULL)
800 continue;
801
802 /* patch pointer hc uses */
803 savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
804 *prev = td->hwNextTD | savebits;
805
806 /* HC may have partly processed this TD */
807 #ifdef ADMHC_VERBOSE_DEBUG
808 urb_print(ahcd, urb, "PARTIAL", 0);
809 #endif
810 td_done(ahcd, urb, td);
811
812 /* if URB is done, clean up */
813 if (urb_priv->td_idx == urb_priv->td_cnt) {
814 modified = completed = 1;
815 finish_urb(ahcd, urb);
816 }
817 }
818 if (completed && !list_empty(&ed->td_list))
819 goto rescan_this;
820
821 /* ED's now officially unlinked, hc doesn't see */
822 ed->state = ED_IDLE;
823 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
824 ed->hwNextED = 0;
825 wmb();
826 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
827
828 /* but if there's work queued, reschedule */
829 if (!list_empty(&ed->td_list)) {
830 if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
831 ed_schedule(ahcd, ed);
832 }
833
834 if (modified)
835 goto rescan_all;
836 }
837 }
838
839 /*-------------------------------------------------------------------------*/
840
841 /*
842 * Process normal completions (error or success) and clean the schedules.
843 *
844 * This is the main path for handing urbs back to drivers. The only other
845 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
846 * scanning the (re-reversed) donelist as this does.
847 */
848
849 static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
850 {
851 struct list_head *entry,*tmp;
852 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
853
854 #ifdef ADMHC_VERBOSE_DEBUG
855 admhc_dump_ed(ahcd, "UNHALT", ed, 0);
856 #endif
857 /* clear ed halt; this is the td that caused it, but keep it inactive
858 * until its urb->complete() has a chance to clean up.
859 */
860 ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
861 wmb();
862 ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
863
864 list_for_each_safe(entry, tmp, &ed->td_list) {
865 struct td *td = list_entry(entry, struct td, td_list);
866 __hc32 info;
867
868 if (td->urb != urb)
869 break;
870
871 info = td->hwINFO;
872 info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
873 td->hwINFO = info;
874
875 ed->hwHeadP = td->hwNextTD | toggle;
876 wmb();
877 }
878
879 }
880
881 static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
882 {
883 __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
884
885 ed->hwHeadP = ed->hwTailP | toggle;
886 }
887
888
889 static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
890 {
891 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
892 }
893
894 static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
895 struct td *td)
896 {
897 return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
898 (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
899 }
900
901 static void ed_update(struct admhcd *ahcd, struct ed *ed)
902 {
903 struct list_head *entry,*tmp;
904
905 #ifdef ADMHC_VERBOSE_DEBUG
906 admhc_dump_ed(ahcd, "UPDATE", ed, 1);
907 #endif
908
909 list_for_each_safe(entry, tmp, &ed->td_list) {
910 struct td *td = list_entry(entry, struct td, td_list);
911 struct urb *urb = td->urb;
912 struct urb_priv *urb_priv = urb->hcpriv;
913 int cc;
914
915 if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
916 break;
917
918 /* update URB's length and status from TD */
919 cc = td_done(ahcd, urb, td);
920 if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
921 ed_unhalt(ahcd, ed, urb);
922
923 if (ed->type == PIPE_INTERRUPT)
924 ed_intr_refill(ahcd,ed);
925
926 /* If all this urb's TDs are done, call complete() */
927 if (urb_priv->td_idx == urb_priv->td_cnt)
928 finish_urb(ahcd, urb);
929
930 /* clean schedule: unlink EDs that are no longer busy */
931 if (list_empty(&ed->td_list)) {
932 if (ed->state == ED_OPER)
933 start_ed_unlink(ahcd, ed);
934
935 /* ... reenabling halted EDs only after fault cleanup */
936 } else if ((ed->hwINFO & cpu_to_hc32(ahcd,
937 ED_SKIP | ED_DEQUEUE))
938 == cpu_to_hc32(ahcd, ED_SKIP)) {
939 td = list_entry(ed->td_list.next, struct td, td_list);
940 #if 0
941 if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
942 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
943 /* ... hc may need waking-up */
944 switch (ed->type) {
945 case PIPE_CONTROL:
946 admhc_writel (ahcd, OHCI_CLF,
947 &ahcd->regs->cmdstatus);
948 break;
949 case PIPE_BULK:
950 admhc_writel (ahcd, OHCI_BLF,
951 &ahcd->regs->cmdstatus);
952 break;
953 }
954 }
955 #else
956 if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
957 ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
958 #endif
959 }
960
961 }
962 }
963
964 /* there are some tds completed; called in_irq(), with HCD locked */
965 static void admhc_td_complete(struct admhcd *ahcd)
966 {
967 struct ed *ed;
968
969 for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
970 if (ed->state != ED_OPER)
971 continue;
972
973 ed_update(ahcd, ed);
974 }
975 }
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