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add support for wgt634u nvram, change the order of the serial ports on the wgt (will...
[openwrt.git] / openwrt / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2005-12-15 13:26:49.758027500 +0100
3 +++ linux.dev/arch/mips/Kconfig 2005-12-15 12:57:27.889182500 +0100
4 @@ -244,6 +244,17 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SYS_SUPPORTS_LITTLE_ENDIAN
16 + help
17 + Support for BCM947xx based boards
18 +
19 config LASAT
20 bool "Support for LASAT Networks platforms"
21 select DMA_NONCOHERENT
22 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
23 --- linux.old/arch/mips/Makefile 2005-12-15 13:26:49.766024000 +0100
24 +++ linux.dev/arch/mips/Makefile 2005-12-15 12:57:27.921168500 +0100
25 @@ -689,6 +689,13 @@
26 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
27
28 #
29 +# Broadcom BCM47XX boards
30 +#
31 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
32 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
33 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
34 +
35 +#
36 # SNI RM200 PCI
37 #
38 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
39 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
40 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-12-15 14:32:03.580639500 +0100
42 @@ -0,0 +1,6 @@
43 +#
44 +# Makefile for the BCM47xx specific kernel interface routines
45 +# under Linux.
46 +#
47 +
48 +obj-y := irq.o int-handler.o prom.o setup.o time.o pci.o
49 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
50 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2005-12-17 20:51:17.749271000 +0100
52 @@ -0,0 +1,6 @@
53 +#
54 +# Makefile for the BCM47xx specific kernel interface routines
55 +# under Linux.
56 +#
57 +
58 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
59 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
60 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
61 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-12-17 01:21:23.007883000 +0100
62 @@ -0,0 +1,481 @@
63 +/*
64 + * Misc useful routines to access NIC SROM/OTP .
65 + *
66 + * Copyright 2005, Broadcom Corporation
67 + * All Rights Reserved.
68 + *
69 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
70 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
71 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
72 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
73 + * $Id$
74 + */
75 +
76 +#include <typedefs.h>
77 +#include <osl.h>
78 +#include <bcmutils.h>
79 +#include <bcmsrom.h>
80 +#include <bcmdevs.h>
81 +#include <bcmendian.h>
82 +#include <pcicfg.h>
83 +#include <sbutils.h>
84 +
85 +#include <proto/ethernet.h> /* for sprom content groking */
86 +
87 +#define VARS_MAX 4096 /* should be reduced */
88 +
89 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
90 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
91 +
92 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
93 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
94 +
95 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
96 +
97 +/*
98 + * Initialize local vars from the right source for this platform.
99 + * Return 0 on success, nonzero on error.
100 + */
101 +int
102 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
103 +{
104 + ASSERT(bustype == BUSTYPE(bustype));
105 + if (vars == NULL || count == NULL)
106 + return (0);
107 +
108 + switch (BUSTYPE(bustype)) {
109 +
110 + case PCI_BUS:
111 + ASSERT(curmap); /* can not be NULL */
112 + return initvars_srom_pci(sbh, curmap, vars, count);
113 +
114 + default:
115 + return 0;
116 + }
117 + return (-1);
118 +}
119 +
120 +/* support only 16-bit word read from srom */
121 +int
122 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
123 +{
124 + void *srom;
125 + uint off, nw;
126 +
127 + ASSERT(bustype == BUSTYPE(bustype));
128 +
129 + /* check input - 16-bit access only */
130 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
131 + return 1;
132 +
133 + off = byteoff / 2;
134 + nw = nbytes / 2;
135 +
136 + if (BUSTYPE(bustype) == PCI_BUS) {
137 + if (!curmap)
138 + return 1;
139 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
140 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
141 + return 1;
142 + } else {
143 + return 1;
144 + }
145 +
146 + return 0;
147 +}
148 +
149 +/* support only 16-bit word write into srom */
150 +int
151 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
152 +{
153 + uint16 *srom;
154 + uint i, off, nw, crc_range;
155 + uint16 image[SPROM_SIZE], *p;
156 + uint8 crc;
157 + volatile uint32 val32;
158 +
159 + ASSERT(bustype == BUSTYPE(bustype));
160 +
161 + /* check input - 16-bit access only */
162 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
163 + return 1;
164 +
165 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
166 +
167 + /* if changes made inside crc cover range */
168 + if (byteoff < crc_range) {
169 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
170 + /* read data including entire first 64 words from srom */
171 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
172 + return 1;
173 + /* make changes */
174 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
175 + /* calculate crc */
176 + htol16_buf(image, crc_range);
177 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
178 + ltoh16_buf(image, crc_range);
179 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
180 + p = image;
181 + off = 0;
182 + } else {
183 + p = buf;
184 + off = byteoff / 2;
185 + nw = nbytes / 2;
186 + }
187 +
188 + if (BUSTYPE(bustype) == PCI_BUS) {
189 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
190 + /* enable writes to the SPROM */
191 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
192 + val32 |= SPROM_WRITEEN;
193 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
194 + bcm_mdelay(WRITE_ENABLE_DELAY);
195 + /* write srom */
196 + for (i = 0; i < nw; i++) {
197 + W_REG(&srom[off + i], p[i]);
198 + bcm_mdelay(WRITE_WORD_DELAY);
199 + }
200 + /* disable writes to the SPROM */
201 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
202 + } else {
203 + return 1;
204 + }
205 +
206 + bcm_mdelay(WRITE_ENABLE_DELAY);
207 + return 0;
208 +}
209 +
210 +
211 +/*
212 + * Read in and validate sprom.
213 + * Return 0 on success, nonzero on error.
214 + */
215 +static int
216 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
217 +{
218 + int err = 0;
219 + uint i;
220 +
221 + /* read the sprom */
222 + for (i = 0; i < nwords; i++)
223 + buf[i] = R_REG(&sprom[wordoff + i]);
224 +
225 + if (check_crc) {
226 + /* fixup the endianness so crc8 will pass */
227 + htol16_buf(buf, nwords * 2);
228 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
229 + err = 1;
230 + /* now correct the endianness of the byte array */
231 + ltoh16_buf(buf, nwords * 2);
232 + }
233 +
234 + return err;
235 +}
236 +
237 +/*
238 +* Create variable table from memory.
239 +* Return 0 on success, nonzero on error.
240 +*/
241 +static int
242 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
243 +{
244 + int c = (int)(end - start);
245 +
246 + /* do it only when there is more than just the null string */
247 + if (c > 1) {
248 + char *vp = MALLOC(osh, c);
249 + ASSERT(vp);
250 + if (!vp)
251 + return BCME_NOMEM;
252 + bcopy(start, vp, c);
253 + *vars = vp;
254 + *count = c;
255 + }
256 + else {
257 + *vars = NULL;
258 + *count = 0;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +/*
265 + * Initialize nonvolatile variable table from sprom.
266 + * Return 0 on success, nonzero on error.
267 + */
268 +static int
269 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
270 +{
271 + uint16 w, b[64];
272 + uint8 sromrev;
273 + struct ether_addr ea;
274 + char eabuf[32];
275 + uint32 w32;
276 + int woff, i;
277 + char *vp, *base;
278 + osl_t *osh = sb_osh(sbh);
279 + int err;
280 +
281 + /*
282 + * Apply CRC over SROM content regardless SROM is present or not,
283 + * and use variable <devpath>sromrev's existance in flash to decide
284 + * if we should return an error when CRC fails or read SROM variables
285 + * from flash.
286 + */
287 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
288 +
289 + /* top word of sprom contains version and crc8 */
290 + sromrev = b[63] & 0xff;
291 + /* bcm4401 sroms misprogrammed */
292 + if (sromrev == 0x10)
293 + sromrev = 1;
294 +
295 + /* srom version check */
296 + if (sromrev > 3)
297 + return (-2);
298 +
299 + ASSERT(vars);
300 + ASSERT(count);
301 +
302 + base = vp = MALLOC(osh, VARS_MAX);
303 + ASSERT(vp);
304 + if (!vp)
305 + return -2;
306 +
307 + vp += sprintf(vp, "sromrev=%d", sromrev);
308 + vp++;
309 +
310 + if (sromrev >= 3) {
311 + /* New section takes over the 3th hardware function space */
312 +
313 + /* Words 22+23 are 11a (mid) ofdm power offsets */
314 + w32 = ((uint32)b[23] << 16) | b[22];
315 + vp += sprintf(vp, "ofdmapo=%d", w32);
316 + vp++;
317 +
318 + /* Words 24+25 are 11a (low) ofdm power offsets */
319 + w32 = ((uint32)b[25] << 16) | b[24];
320 + vp += sprintf(vp, "ofdmalpo=%d", w32);
321 + vp++;
322 +
323 + /* Words 26+27 are 11a (high) ofdm power offsets */
324 + w32 = ((uint32)b[27] << 16) | b[26];
325 + vp += sprintf(vp, "ofdmahpo=%d", w32);
326 + vp++;
327 +
328 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
329 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
330 + vp += sprintf(vp, "gpiotimerval=%d", w32);
331 +
332 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
333 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
334 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
335 + vp += sprintf(vp, "gpiotimerval=%d", w32);
336 +
337 + vp++;
338 + }
339 +
340 + if (sromrev >= 2) {
341 + /* New section takes over the 4th hardware function space */
342 +
343 + /* Word 29 is max power 11a high/low */
344 + w = b[29];
345 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
346 + vp++;
347 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
348 + vp++;
349 +
350 + /* Words 30-32 set the 11alow pa settings,
351 + * 33-35 are the 11ahigh ones.
352 + */
353 + for (i = 0; i < 3; i++) {
354 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
355 + vp++;
356 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
357 + vp++;
358 + }
359 + w = b[59];
360 + if (w == 0)
361 + vp += sprintf(vp, "ccode=");
362 + else
363 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
364 + vp++;
365 +
366 + }
367 +
368 + /* parameter section of sprom starts at byte offset 72 */
369 + woff = 72/2;
370 +
371 + /* first 6 bytes are il0macaddr */
372 + ea.octet[0] = (b[woff] >> 8) & 0xff;
373 + ea.octet[1] = b[woff] & 0xff;
374 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
375 + ea.octet[3] = b[woff+1] & 0xff;
376 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
377 + ea.octet[5] = b[woff+2] & 0xff;
378 + woff += ETHER_ADDR_LEN/2 ;
379 + bcm_ether_ntoa((uchar*)&ea, eabuf);
380 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
381 + vp++;
382 +
383 + /* next 6 bytes are et0macaddr */
384 + ea.octet[0] = (b[woff] >> 8) & 0xff;
385 + ea.octet[1] = b[woff] & 0xff;
386 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
387 + ea.octet[3] = b[woff+1] & 0xff;
388 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
389 + ea.octet[5] = b[woff+2] & 0xff;
390 + woff += ETHER_ADDR_LEN/2 ;
391 + bcm_ether_ntoa((uchar*)&ea, eabuf);
392 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
393 + vp++;
394 +
395 + /* next 6 bytes are et1macaddr */
396 + ea.octet[0] = (b[woff] >> 8) & 0xff;
397 + ea.octet[1] = b[woff] & 0xff;
398 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
399 + ea.octet[3] = b[woff+1] & 0xff;
400 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
401 + ea.octet[5] = b[woff+2] & 0xff;
402 + woff += ETHER_ADDR_LEN/2 ;
403 + bcm_ether_ntoa((uchar*)&ea, eabuf);
404 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
405 + vp++;
406 +
407 + /*
408 + * Enet phy settings one or two singles or a dual
409 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
410 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
411 + * Bit 14 : Mdio for enet0
412 + * Bit 15 : Mdio for enet1
413 + */
414 + w = b[woff];
415 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
416 + vp++;
417 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
418 + vp++;
419 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
420 + vp++;
421 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
422 + vp++;
423 +
424 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
425 + w = b[46];
426 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
427 + vp++;
428 +
429 + if (sromrev > 1)
430 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
431 + else
432 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
433 + vp++;
434 +
435 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
436 + vp++;
437 +
438 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
439 + vp++;
440 +
441 + /* Words 47-49 set the (wl) pa settings */
442 + woff = 47;
443 +
444 + for (i = 0; i < 3; i++) {
445 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
446 + vp++;
447 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
448 + vp++;
449 + }
450 +
451 + /*
452 + * Words 50-51 set the customer-configured wl led behavior.
453 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
454 + * LED behavior values defined in wlioctl.h .
455 + */
456 + w = b[50];
457 + if ((w != 0) && (w != 0xffff)) {
458 + /* gpio0 */
459 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
460 + vp++;
461 +
462 + /* gpio1 */
463 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
464 + vp++;
465 + }
466 + w = b[51];
467 + if ((w != 0) && (w != 0xffff)) {
468 + /* gpio2 */
469 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
470 + vp++;
471 +
472 + /* gpio3 */
473 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
474 + vp++;
475 + }
476 +
477 + /* Word 52 is max power 0/1 */
478 + w = b[52];
479 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
480 + vp++;
481 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
482 + vp++;
483 +
484 + /* Word 56 is idle tssi target 0/1 */
485 + w = b[56];
486 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
487 + vp++;
488 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
489 + vp++;
490 +
491 + /* Word 57 is boardflags, if not programmed make it zero */
492 + w32 = (uint32)b[57];
493 + if (w32 == 0xffff) w32 = 0;
494 + if (sromrev > 1) {
495 + /* Word 28 is the high bits of boardflags */
496 + w32 |= (uint32)b[28] << 16;
497 + }
498 + vp += sprintf(vp, "boardflags=%d", w32);
499 + vp++;
500 +
501 + /* Word 58 is antenna gain 0/1 */
502 + w = b[58];
503 + vp += sprintf(vp, "ag0=%d", w & 0xff);
504 + vp++;
505 +
506 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
507 + vp++;
508 +
509 + if (sromrev == 1) {
510 + /* set the oem string */
511 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
512 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
513 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
514 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
515 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
516 + vp++;
517 + } else if (sromrev == 2) {
518 + /* Word 60 OFDM tx power offset from CCK level */
519 + /* OFDM Power Offset - opo */
520 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
521 + vp++;
522 + } else {
523 + /* Word 60: cck power offsets */
524 + vp += sprintf(vp, "cckpo=%d", b[60]);
525 + vp++;
526 +
527 + /* Words 61+62: 11g ofdm power offsets */
528 + w32 = ((uint32)b[62] << 16) | b[61];
529 + vp += sprintf(vp, "ofdmgpo=%d", w32);
530 + vp++;
531 + }
532 +
533 + /* final nullbyte terminator */
534 + *vp++ = '\0';
535 +
536 + ASSERT((vp - base) <= VARS_MAX);
537 +
538 + err = initvars_table(osh, base, vp, vars, count);
539 +
540 + MFREE(osh, base, VARS_MAX);
541 + return err;
542 +}
543 +
544 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
545 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
546 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-12-17 17:53:52.387365000 +0100
547 @@ -0,0 +1,356 @@
548 +/*
549 + * Misc useful OS-independent routines.
550 + *
551 + * Copyright 2005, Broadcom Corporation
552 + * All Rights Reserved.
553 + *
554 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
555 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
556 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
557 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
558 + * $Id$
559 + */
560 +
561 +#include <typedefs.h>
562 +#include <osl.h>
563 +#include <sbutils.h>
564 +#include <bcmnvram.h>
565 +#include <bcmutils.h>
566 +#include <bcmendian.h>
567 +#include <bcmdevs.h>
568 +
569 +unsigned char bcm_ctype[] = {
570 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
571 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
572 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
573 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
574 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
575 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
576 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
577 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
578 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
579 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
580 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
581 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
582 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
583 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
584 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
585 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
586 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
587 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
588 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
589 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
590 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
591 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
592 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
593 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
594 +};
595 +
596 +uchar
597 +bcm_toupper(uchar c)
598 +{
599 + if (bcm_islower(c))
600 + c -= 'a'-'A';
601 + return (c);
602 +}
603 +
604 +ulong
605 +bcm_strtoul(char *cp, char **endp, uint base)
606 +{
607 + ulong result, value;
608 + bool minus;
609 +
610 + minus = FALSE;
611 +
612 + while (bcm_isspace(*cp))
613 + cp++;
614 +
615 + if (cp[0] == '+')
616 + cp++;
617 + else if (cp[0] == '-') {
618 + minus = TRUE;
619 + cp++;
620 + }
621 +
622 + if (base == 0) {
623 + if (cp[0] == '0') {
624 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
625 + base = 16;
626 + cp = &cp[2];
627 + } else {
628 + base = 8;
629 + cp = &cp[1];
630 + }
631 + } else
632 + base = 10;
633 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
634 + cp = &cp[2];
635 + }
636 +
637 + result = 0;
638 +
639 + while (bcm_isxdigit(*cp) &&
640 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
641 + result = result*base + value;
642 + cp++;
643 + }
644 +
645 + if (minus)
646 + result = (ulong)(result * -1);
647 +
648 + if (endp)
649 + *endp = (char *)cp;
650 +
651 + return (result);
652 +}
653 +
654 +uint
655 +bcm_atoi(char *s)
656 +{
657 + uint n;
658 +
659 + n = 0;
660 +
661 + while (bcm_isdigit(*s))
662 + n = (n * 10) + *s++ - '0';
663 + return (n);
664 +}
665 +
666 +/* return pointer to location of substring 'needle' in 'haystack' */
667 +char*
668 +bcmstrstr(char *haystack, char *needle)
669 +{
670 + int len, nlen;
671 + int i;
672 +
673 + if ((haystack == NULL) || (needle == NULL))
674 + return (haystack);
675 +
676 + nlen = strlen(needle);
677 + len = strlen(haystack) - nlen + 1;
678 +
679 + for (i = 0; i < len; i++)
680 + if (bcmp(needle, &haystack[i], nlen) == 0)
681 + return (&haystack[i]);
682 + return (NULL);
683 +}
684 +
685 +char*
686 +bcmstrcat(char *dest, const char *src)
687 +{
688 + strcpy(&dest[strlen(dest)], src);
689 + return (dest);
690 +}
691 +
692 +
693 +char*
694 +bcm_ether_ntoa(char *ea, char *buf)
695 +{
696 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
697 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
698 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
699 + return (buf);
700 +}
701 +
702 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
703 +int
704 +bcm_ether_atoe(char *p, char *ea)
705 +{
706 + int i = 0;
707 +
708 + for (;;) {
709 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
710 + if (!*p++ || i == 6)
711 + break;
712 + }
713 +
714 + return (i == 6);
715 +}
716 +
717 +void
718 +bcm_mdelay(uint ms)
719 +{
720 + uint i;
721 +
722 + for (i = 0; i < ms; i++) {
723 + OSL_DELAY(1000);
724 + }
725 +}
726 +
727 +/*
728 + * Search the name=value vars for a specific one and return its value.
729 + * Returns NULL if not found.
730 + */
731 +char*
732 +getvar(char *vars, char *name)
733 +{
734 + char *s;
735 + int len;
736 +
737 + len = strlen(name);
738 +
739 + /* first look in vars[] */
740 + for (s = vars; s && *s; ) {
741 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
742 + return (&s[len+1]);
743 +
744 + while (*s++)
745 + ;
746 + }
747 +
748 + /* then query nvram */
749 + return (BCMINIT(nvram_get)(name));
750 +}
751 +
752 +/*
753 + * Search the vars for a specific one and return its value as
754 + * an integer. Returns 0 if not found.
755 + */
756 +int
757 +getintvar(char *vars, char *name)
758 +{
759 + char *val;
760 +
761 + if ((val = getvar(vars, name)) == NULL)
762 + return (0);
763 +
764 + return (bcm_strtoul(val, NULL, 0));
765 +}
766 +
767 +
768 +/* Search for token in comma separated token-string */
769 +static int
770 +findmatch(char *string, char *name)
771 +{
772 + uint len;
773 + char *c;
774 +
775 + len = strlen(name);
776 + while ((c = strchr(string, ',')) != NULL) {
777 + if (len == (uint)(c - string) && !strncmp(string, name, len))
778 + return 1;
779 + string = c + 1;
780 + }
781 +
782 + return (!strcmp(string, name));
783 +}
784 +
785 +/* Return gpio pin number assigned to the named pin */
786 +/*
787 +* Variable should be in format:
788 +*
789 +* gpio<N>=pin_name,pin_name
790 +*
791 +* This format allows multiple features to share the gpio with mutual
792 +* understanding.
793 +*
794 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
795 +* and if def_pin is not used by others.
796 +*/
797 +uint
798 +getgpiopin(char *vars, char *pin_name, uint def_pin)
799 +{
800 + char name[] = "gpioXXXX";
801 + char *val;
802 + uint pin;
803 +
804 + /* Go thru all possibilities till a match in pin name */
805 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
806 + sprintf(name, "gpio%d", pin);
807 + val = getvar(vars, name);
808 + if (val && findmatch(val, pin_name))
809 + return pin;
810 + }
811 +
812 + if (def_pin != GPIO_PIN_NOTDEFINED) {
813 + /* make sure the default pin is not used by someone else */
814 + sprintf(name, "gpio%d", def_pin);
815 + if (getvar(vars, name)) {
816 + def_pin = GPIO_PIN_NOTDEFINED;
817 + }
818 + }
819 +
820 + return def_pin;
821 +}
822 +
823 +
824 +/*******************************************************************************
825 + * crc8
826 + *
827 + * Computes a crc8 over the input data using the polynomial:
828 + *
829 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
830 + *
831 + * The caller provides the initial value (either CRC8_INIT_VALUE
832 + * or the previous returned value) to allow for processing of
833 + * discontiguous blocks of data. When generating the CRC the
834 + * caller is responsible for complementing the final return value
835 + * and inserting it into the byte stream. When checking, a final
836 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
837 + *
838 + * Reference: Dallas Semiconductor Application Note 27
839 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
840 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
841 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
842 + *
843 + ******************************************************************************/
844 +
845 +static uint8 crc8_table[256] = {
846 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
847 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
848 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
849 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
850 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
851 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
852 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
853 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
854 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
855 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
856 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
857 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
858 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
859 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
860 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
861 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
862 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
863 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
864 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
865 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
866 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
867 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
868 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
869 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
870 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
871 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
872 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
873 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
874 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
875 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
876 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
877 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
878 +};
879 +
880 +#define CRC_INNER_LOOP(n, c, x) \
881 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
882 +
883 +uint8
884 +hndcrc8(
885 + uint8 *pdata, /* pointer to array of data to process */
886 + uint nbytes, /* number of input data bytes to process */
887 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
888 +)
889 +{
890 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
891 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
892 + while (nbytes-- > 0)
893 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
894 +
895 + return crc;
896 +}
897 +
898 +#ifdef notdef
899 +#define CLEN 1499
900 +#define CBUFSIZ (CLEN+4)
901 +#define CNBUFS 5
902 +
903 +#endif
904 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
905 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
906 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2005-12-17 21:40:08.166726750 +0100
907 @@ -0,0 +1,234 @@
908 +/*
909 + * NVRAM variable manipulation (Linux kernel half)
910 + *
911 + * Copyright 2001-2003, Broadcom Corporation
912 + * All Rights Reserved.
913 + *
914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
918 + *
919 + * $Id$
920 + */
921 +
922 +#include <linux/config.h>
923 +#include <linux/init.h>
924 +#include <linux/module.h>
925 +#include <linux/kernel.h>
926 +#include <linux/string.h>
927 +#include <asm/io.h>
928 +#include <asm/uaccess.h>
929 +
930 +#include <typedefs.h>
931 +#include <osl.h>
932 +#include <bcmendian.h>
933 +#include <bcmutils.h>
934 +
935 +#define NVRAM_SIZE (0x1ff0)
936 +static char _nvdata[NVRAM_SIZE] __initdata;
937 +static char _valuestr[256] __initdata;
938 +
939 +/*
940 + * TLV types. These codes are used in the "type-length-value"
941 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
942 + *
943 + * The layout of the flash/nvram is as follows:
944 + *
945 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
946 + *
947 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
948 + * The "length" field marks the length of the data section, not
949 + * including the type and length fields.
950 + *
951 + * Environment variables are stored as follows:
952 + *
953 + * <type_env> <length> <flags> <name> = <value>
954 + *
955 + * If bit 0 (low bit) is set, the length is an 8-bit value.
956 + * If bit 0 (low bit) is clear, the length is a 16-bit value
957 + *
958 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
959 + * indicates the size of the length field.
960 + *
961 + * Flags are from the constants below:
962 + *
963 + */
964 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
965 +#define ENV_LENGTH_8BITS 0x01
966 +
967 +#define ENV_TYPE_USER 0x80
968 +
969 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
970 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
971 +
972 +/*
973 + * The actual TLV types we support
974 + */
975 +
976 +#define ENV_TLV_TYPE_END 0x00
977 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
978 +
979 +/*
980 + * Environment variable flags
981 + */
982 +
983 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
984 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
985 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
986 +
987 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
988 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
989 +
990 +
991 +/* *********************************************************************
992 + * _nvram_read(buffer,offset,length)
993 + *
994 + * Read data from the NVRAM device
995 + *
996 + * Input parameters:
997 + * buffer - destination buffer
998 + * offset - offset of data to read
999 + * length - number of bytes to read
1000 + *
1001 + * Return value:
1002 + * number of bytes read, or <0 if error occured
1003 + ********************************************************************* */
1004 +static int
1005 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1006 +{
1007 + int i;
1008 + if (offset > NVRAM_SIZE)
1009 + return -1;
1010 +
1011 + for ( i = 0; i < length; i++) {
1012 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1013 + }
1014 + return length;
1015 +}
1016 +
1017 +
1018 +static char*
1019 +_strnchr(const char *dest,int c,size_t cnt)
1020 +{
1021 + while (*dest && (cnt > 0)) {
1022 + if (*dest == c) return (char *) dest;
1023 + dest++;
1024 + cnt--;
1025 + }
1026 + return NULL;
1027 +}
1028 +
1029 +
1030 +
1031 +/*
1032 + * Core support API: Externally visible.
1033 + */
1034 +
1035 +/*
1036 + * Get the value of an NVRAM variable
1037 + * @param name name of variable to get
1038 + * @return value of variable or NULL if undefined
1039 + */
1040 +
1041 +char*
1042 +cfe_env_get(unsigned char *nv_buf, char* name)
1043 +{
1044 + int size;
1045 + unsigned char *buffer;
1046 + unsigned char *ptr;
1047 + unsigned char *envval;
1048 + unsigned int reclen;
1049 + unsigned int rectype;
1050 + int offset;
1051 + int flg;
1052 +
1053 + size = NVRAM_SIZE;
1054 + buffer = &_nvdata[0];
1055 +
1056 + ptr = buffer;
1057 + offset = 0;
1058 +
1059 + /* Read the record type and length */
1060 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1061 + goto error;
1062 + }
1063 +
1064 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1065 +
1066 + /* Adjust pointer for TLV type */
1067 + rectype = *(ptr);
1068 + offset++;
1069 + size--;
1070 +
1071 + /*
1072 + * Read the length. It can be either 1 or 2 bytes
1073 + * depending on the code
1074 + */
1075 + if (rectype & ENV_LENGTH_8BITS) {
1076 + /* Read the record type and length - 8 bits */
1077 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1078 + goto error;
1079 + }
1080 + reclen = *(ptr);
1081 + size--;
1082 + offset++;
1083 + }
1084 + else {
1085 + /* Read the record type and length - 16 bits, MSB first */
1086 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1087 + goto error;
1088 + }
1089 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1090 + size -= 2;
1091 + offset += 2;
1092 + }
1093 +
1094 + if (reclen > size)
1095 + break; /* should not happen, bad NVRAM */
1096 +
1097 + switch (rectype) {
1098 + case ENV_TLV_TYPE_ENV:
1099 + /* Read the TLV data */
1100 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1101 + goto error;
1102 + flg = *ptr++;
1103 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1104 + if (envval) {
1105 + *envval++ = '\0';
1106 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1107 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1108 +#if 0
1109 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1110 +#endif
1111 + if(!strcmp(ptr, name)){
1112 + return _valuestr;
1113 + }
1114 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1115 + return _valuestr;
1116 + }
1117 + break;
1118 +
1119 + default:
1120 + /* Unknown TLV type, skip it. */
1121 + break;
1122 + }
1123 +
1124 + /*
1125 + * Advance to next TLV
1126 + */
1127 +
1128 + size -= (int)reclen;
1129 + offset += reclen;
1130 +
1131 + /* Read the next record type */
1132 + ptr = buffer;
1133 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1134 + goto error;
1135 + }
1136 +
1137 +error:
1138 + return NULL;
1139 +
1140 +}
1141 +
1142 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1143 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1144 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-12-15 17:11:05.818041750 +0100
1145 @@ -0,0 +1,102 @@
1146 +/*
1147 + * Linux OS Independent Layer
1148 + *
1149 + * Copyright 2005, Broadcom Corporation
1150 + * All Rights Reserved.
1151 + *
1152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1156 + *
1157 + * $Id$
1158 + */
1159 +
1160 +#define LINUX_OSL
1161 +
1162 +#include <typedefs.h>
1163 +#include <bcmendian.h>
1164 +#include <linux/module.h>
1165 +#include <linuxver.h>
1166 +#include <osl.h>
1167 +#include <bcmutils.h>
1168 +#include <linux/delay.h>
1169 +#ifdef mips
1170 +#include <asm/paccess.h>
1171 +#endif
1172 +#include <pcicfg.h>
1173 +
1174 +#define PCI_CFG_RETRY 10
1175 +
1176 +#define OS_HANDLE_MAGIC 0x1234abcd
1177 +#define BCM_MEM_FILENAME_LEN 24
1178 +
1179 +typedef struct bcm_mem_link {
1180 + struct bcm_mem_link *prev;
1181 + struct bcm_mem_link *next;
1182 + uint size;
1183 + int line;
1184 + char file[BCM_MEM_FILENAME_LEN];
1185 +} bcm_mem_link_t;
1186 +
1187 +struct os_handle {
1188 + uint magic;
1189 + void *pdev;
1190 + uint malloced;
1191 + uint failed;
1192 + bcm_mem_link_t *dbgmem_list;
1193 +};
1194 +
1195 +uint32
1196 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1197 +{
1198 + uint val;
1199 + uint retry=PCI_CFG_RETRY;
1200 +
1201 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1202 +
1203 + /* only 4byte access supported */
1204 + ASSERT(size == 4);
1205 +
1206 + do {
1207 + pci_read_config_dword(osh->pdev, offset, &val);
1208 + if (val != 0xffffffff)
1209 + break;
1210 + } while (retry--);
1211 +
1212 +
1213 + return (val);
1214 +}
1215 +
1216 +void
1217 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1218 +{
1219 + uint retry=PCI_CFG_RETRY;
1220 +
1221 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1222 +
1223 + /* only 4byte access supported */
1224 + ASSERT(size == 4);
1225 +
1226 + do {
1227 + pci_write_config_dword(osh->pdev, offset, val);
1228 + if (offset!=PCI_BAR0_WIN)
1229 + break;
1230 + if (osl_pci_read_config(osh,offset,size) == val)
1231 + break;
1232 + } while (retry--);
1233 +
1234 +}
1235 +
1236 +void
1237 +osl_delay(uint usec)
1238 +{
1239 + uint d;
1240 +
1241 + while (usec > 0) {
1242 + d = MIN(usec, 1000);
1243 + udelay(d);
1244 + usec -= d;
1245 + }
1246 +}
1247 +
1248 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1249 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1250 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2005-12-17 21:41:45.656819500 +0100
1251 @@ -0,0 +1,165 @@
1252 +/*
1253 + * NVRAM variable manipulation (Linux kernel half)
1254 + *
1255 + * Copyright 2005, Broadcom Corporation
1256 + * All Rights Reserved.
1257 + *
1258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1262 + *
1263 + * $Id$
1264 + */
1265 +
1266 +#include <linux/config.h>
1267 +#include <linux/init.h>
1268 +#include <linux/module.h>
1269 +#include <linux/kernel.h>
1270 +#include <linux/string.h>
1271 +#include <linux/interrupt.h>
1272 +#include <linux/spinlock.h>
1273 +#include <linux/slab.h>
1274 +#include <asm/bootinfo.h>
1275 +#include <asm/addrspace.h>
1276 +#include <asm/io.h>
1277 +#include <asm/uaccess.h>
1278 +
1279 +#include <typedefs.h>
1280 +#include <bcmendian.h>
1281 +#include <bcmnvram.h>
1282 +#include <bcmutils.h>
1283 +#include <sbconfig.h>
1284 +#include <sbchipc.h>
1285 +#include <sbutils.h>
1286 +#include <sbmips.h>
1287 +#include <sflash.h>
1288 +
1289 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1290 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1291 +
1292 +/* Global SB handle */
1293 +extern void *sbh;
1294 +extern spinlock_t bcm947xx_sbh_lock;
1295 +static int cfe_env;
1296 +
1297 +extern char *cfe_env_get(unsigned char *nv_buf, char *name);
1298 +
1299 +
1300 +/* Convenience */
1301 +#define sbh_lock bcm947xx_sbh_lock
1302 +#define KB * 1024
1303 +#define MB * 1024 * 1024
1304 +
1305 +/* Probe for NVRAM header */
1306 +static void __init
1307 +early_nvram_init(void)
1308 +{
1309 + struct nvram_header *header;
1310 + chipcregs_t *cc;
1311 + struct sflash *info = NULL;
1312 + int i;
1313 + uint32 base, off, lim;
1314 + u32 *src, *dst;
1315 +
1316 + cfe_env = 0;
1317 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1318 + base = KSEG1ADDR(SB_FLASH2);
1319 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1320 + case PFLASH:
1321 + lim = SB_FLASH2_SZ;
1322 + break;
1323 +
1324 + case SFLASH_ST:
1325 + case SFLASH_AT:
1326 + if ((info = sflash_init(cc)) == NULL)
1327 + return;
1328 + lim = info->size;
1329 + break;
1330 +
1331 + case FLASH_NONE:
1332 + default:
1333 + return;
1334 + }
1335 + } else {
1336 + /* extif assumed, Stop at 4 MB */
1337 + base = KSEG1ADDR(SB_FLASH1);
1338 + lim = SB_FLASH1_SZ;
1339 + }
1340 +
1341 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1342 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1343 + dst = (u32 *) nvram_buf;
1344 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1345 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1346 +
1347 + for (i = 0; i < 0x1ff0; i++) {
1348 + if (*src == 0xFFFFFFFF)
1349 + break;
1350 + *dst++ = *src++;
1351 + }
1352 + cfe_env = 1;
1353 + return;
1354 + }
1355 +
1356 + off = FLASH_MIN;
1357 + while (off <= lim) {
1358 + /* Windowed flash access */
1359 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1360 + if (header->magic == NVRAM_MAGIC)
1361 + goto found;
1362 + off <<= 1;
1363 + }
1364 +
1365 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1366 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1367 + if (header->magic == NVRAM_MAGIC)
1368 + goto found;
1369 +
1370 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1371 + if (header->magic == NVRAM_MAGIC)
1372 + goto found;
1373 +
1374 + return;
1375 +
1376 +found:
1377 + src = (u32 *) header;
1378 + dst = (u32 *) nvram_buf;
1379 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1380 + *dst++ = *src++;
1381 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1382 + *dst++ = ltoh32(*src++);
1383 +}
1384 +
1385 +/* Early (before mm or mtd) read-only access to NVRAM */
1386 +char * __init nvram_get(const char *name)
1387 +{
1388 + char *var, *value, *end, *eq;
1389 +
1390 + if (!name)
1391 + return NULL;
1392 +
1393 + /* Too early? */
1394 + if (sbh == NULL)
1395 + return NULL;
1396 +
1397 + if (!nvram_buf[0])
1398 + early_nvram_init();
1399 +
1400 + if (cfe_env)
1401 + return cfe_env_get(nvram_buf, name);
1402 +
1403 + /* Look for name=value and return value */
1404 + var = &nvram_buf[sizeof(struct nvram_header)];
1405 + end = nvram_buf + sizeof(nvram_buf) - 2;
1406 + end[0] = end[1] = '\0';
1407 + for (; *var; var = value + strlen(value) + 1) {
1408 + if (!(eq = strchr(var, '=')))
1409 + break;
1410 + value = eq + 1;
1411 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1412 + return value;
1413 + }
1414 +
1415 + return NULL;
1416 +}
1417 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1418 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1419 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2005-12-15 16:46:31.122961250 +0100
1420 @@ -0,0 +1,1038 @@
1421 +/*
1422 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1423 + *
1424 + * Copyright 2005, Broadcom Corporation
1425 + * All Rights Reserved.
1426 + *
1427 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1428 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1429 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1430 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1431 + *
1432 + * $Id$
1433 + */
1434 +
1435 +#include <typedefs.h>
1436 +#include <osl.h>
1437 +#include <sbutils.h>
1438 +#include <bcmdevs.h>
1439 +#include <bcmnvram.h>
1440 +#include <bcmutils.h>
1441 +#include <hndmips.h>
1442 +#include <sbconfig.h>
1443 +#include <sbextif.h>
1444 +#include <sbchipc.h>
1445 +#include <sbmemc.h>
1446 +#include <mipsinc.h>
1447 +#include <sbutils.h>
1448 +
1449 +/*
1450 + * Returns TRUE if an external UART exists at the given base
1451 + * register.
1452 + */
1453 +static bool
1454 +BCMINITFN(serial_exists)(uint8 *regs)
1455 +{
1456 + uint8 save_mcr, status1;
1457 +
1458 + save_mcr = R_REG(&regs[UART_MCR]);
1459 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1460 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1461 + W_REG(&regs[UART_MCR], save_mcr);
1462 +
1463 + return (status1 == 0x90);
1464 +}
1465 +
1466 +/*
1467 + * Initializes UART access. The callback function will be called once
1468 + * per found UART.
1469 + */
1470 +void
1471 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1472 +{
1473 + void *regs;
1474 + ulong base;
1475 + uint irq;
1476 + int i, n;
1477 +
1478 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1479 + extifregs_t *eir = (extifregs_t *) regs;
1480 + sbconfig_t *sb;
1481 +
1482 + /* Determine external UART register base */
1483 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1484 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1485 +
1486 + /* Determine IRQ */
1487 + irq = sb_irq(sbh);
1488 +
1489 + /* Disable GPIO interrupt initially */
1490 + W_REG(&eir->gpiointpolarity, 0);
1491 + W_REG(&eir->gpiointmask, 0);
1492 +
1493 + /* Search for external UARTs */
1494 + n = 2;
1495 + for (i = 0; i < 2; i++) {
1496 + regs = (void *) REG_MAP(base + (i * 8), 8);
1497 + if (BCMINIT(serial_exists)(regs)) {
1498 + /* Set GPIO 1 to be the external UART IRQ */
1499 + W_REG(&eir->gpiointmask, 2);
1500 + if (add)
1501 + add(regs, irq, 13500000, 0);
1502 + }
1503 + }
1504 +
1505 + /* Add internal UART if enabled */
1506 + if (R_REG(&eir->corecontrol) & CC_UE)
1507 + if (add)
1508 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1509 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1510 + chipcregs_t *cc = (chipcregs_t *) regs;
1511 + uint32 rev, cap, pll, baud_base, div;
1512 +
1513 + /* Determine core revision and capabilities */
1514 + rev = sb_corerev(sbh);
1515 + cap = R_REG(&cc->capabilities);
1516 + pll = cap & CAP_PLL_MASK;
1517 +
1518 + /* Determine IRQ */
1519 + irq = sb_irq(sbh);
1520 +
1521 + if (pll == PLL_TYPE1) {
1522 + /* PLL clock */
1523 + baud_base = sb_clock_rate(pll,
1524 + R_REG(&cc->clockcontrol_n),
1525 + R_REG(&cc->clockcontrol_m2));
1526 + div = 1;
1527 + } else {
1528 + if (rev >= 11) {
1529 + /* Fixed ALP clock */
1530 + baud_base = 20000000;
1531 + div = 1;
1532 + /* Set the override bit so we don't divide it */
1533 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1534 + } else if (rev >= 3) {
1535 + /* Internal backplane clock */
1536 + baud_base = sb_clock(sbh);
1537 + div = 2; /* Minimum divisor */
1538 + W_REG(&cc->clkdiv,
1539 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1540 + } else {
1541 + /* Fixed internal backplane clock */
1542 + baud_base = 88000000;
1543 + div = 48;
1544 + }
1545 +
1546 + /* Clock source depends on strapping if UartClkOverride is unset */
1547 + if ((rev > 0) &&
1548 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1549 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1550 + /* Internal divided backplane clock */
1551 + baud_base /= div;
1552 + } else {
1553 + /* Assume external clock of 1.8432 MHz */
1554 + baud_base = 1843200;
1555 + }
1556 + }
1557 + }
1558 +
1559 + /* Add internal UARTs */
1560 + n = cap & CAP_UARTS_MASK;
1561 + for (i = 0; i < n; i++) {
1562 + /* Register offset changed after revision 0 */
1563 + if (rev)
1564 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1565 + else
1566 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1567 +
1568 + if (add)
1569 + add(regs, irq, baud_base, 0);
1570 + }
1571 + }
1572 +}
1573 +
1574 +/*
1575 + * Initialize jtag master and return handle for
1576 + * jtag_rwreg. Returns NULL on failure.
1577 + */
1578 +void *
1579 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1580 +{
1581 + void *regs;
1582 +
1583 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1584 + chipcregs_t *cc = (chipcregs_t *) regs;
1585 + uint32 tmp;
1586 +
1587 + /*
1588 + * Determine jtagm availability from
1589 + * core revision and capabilities.
1590 + */
1591 + tmp = sb_corerev(sbh);
1592 + /*
1593 + * Corerev 10 has jtagm, but the only chip
1594 + * with it does not have a mips, and
1595 + * the layout of the jtagcmd register is
1596 + * different. We'll only accept >= 11.
1597 + */
1598 + if (tmp < 11)
1599 + return (NULL);
1600 +
1601 + tmp = R_REG(&cc->capabilities);
1602 + if ((tmp & CAP_JTAGP) == 0)
1603 + return (NULL);
1604 +
1605 + /* Set clock divider if requested */
1606 + if (clkd != 0) {
1607 + tmp = R_REG(&cc->clkdiv);
1608 + tmp = (tmp & ~CLKD_JTAG) |
1609 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1610 + W_REG(&cc->clkdiv, tmp);
1611 + }
1612 +
1613 + /* Enable jtagm */
1614 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1615 + W_REG(&cc->jtagctrl, tmp);
1616 + }
1617 +
1618 + return (regs);
1619 +}
1620 +
1621 +void
1622 +sb_jtagm_disable(void *h)
1623 +{
1624 + chipcregs_t *cc = (chipcregs_t *)h;
1625 +
1626 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1627 +}
1628 +
1629 +/*
1630 + * Read/write a jtag register. Assumes a target with
1631 + * 8 bit IR and 32 bit DR.
1632 + */
1633 +#define IRWIDTH 8
1634 +#define DRWIDTH 32
1635 +uint32
1636 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1637 +{
1638 + chipcregs_t *cc = (chipcregs_t *) h;
1639 + uint32 tmp;
1640 +
1641 + W_REG(&cc->jtagir, ir);
1642 + W_REG(&cc->jtagdr, dr);
1643 + tmp = JCMD_START | JCMD_ACC_IRDR |
1644 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1645 + (DRWIDTH - 1);
1646 + W_REG(&cc->jtagcmd, tmp);
1647 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1648 + /* OSL_DELAY(1); */
1649 + }
1650 +
1651 + tmp = R_REG(&cc->jtagdr);
1652 + return (tmp);
1653 +}
1654 +
1655 +/* Returns the SB interrupt flag of the current core. */
1656 +uint32
1657 +sb_flag(sb_t *sbh)
1658 +{
1659 + void *regs;
1660 + sbconfig_t *sb;
1661 +
1662 + regs = sb_coreregs(sbh);
1663 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1664 +
1665 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1666 +}
1667 +
1668 +static const uint32 sbips_int_mask[] = {
1669 + 0,
1670 + SBIPS_INT1_MASK,
1671 + SBIPS_INT2_MASK,
1672 + SBIPS_INT3_MASK,
1673 + SBIPS_INT4_MASK
1674 +};
1675 +
1676 +static const uint32 sbips_int_shift[] = {
1677 + 0,
1678 + 0,
1679 + SBIPS_INT2_SHIFT,
1680 + SBIPS_INT3_SHIFT,
1681 + SBIPS_INT4_SHIFT
1682 +};
1683 +
1684 +/*
1685 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1686 + * 0 is returned.
1687 + */
1688 +uint
1689 +sb_irq(sb_t *sbh)
1690 +{
1691 + uint idx;
1692 + void *regs;
1693 + sbconfig_t *sb;
1694 + uint32 flag, sbipsflag;
1695 + uint irq = 0;
1696 +
1697 + flag = sb_flag(sbh);
1698 +
1699 + idx = sb_coreidx(sbh);
1700 +
1701 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1702 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1703 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1704 +
1705 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1706 + sbipsflag = R_REG(&sb->sbipsflag);
1707 + for (irq = 1; irq <= 4; irq++) {
1708 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1709 + break;
1710 + }
1711 + if (irq == 5)
1712 + irq = 0;
1713 + }
1714 +
1715 + sb_setcoreidx(sbh, idx);
1716 +
1717 + return irq;
1718 +}
1719 +
1720 +/* Clears the specified MIPS IRQ. */
1721 +static void
1722 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 +
1727 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1728 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1729 + ASSERT(regs);
1730 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1731 +
1732 + if (irq == 0)
1733 + W_REG(&sb->sbintvec, 0);
1734 + else
1735 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1736 +}
1737 +
1738 +/*
1739 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1740 + * IRQ 0 may be assigned more than once.
1741 + */
1742 +static void
1743 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1744 +{
1745 + void *regs;
1746 + sbconfig_t *sb;
1747 + uint32 flag;
1748 +
1749 + regs = sb_setcore(sbh, coreid, coreunit);
1750 + ASSERT(regs);
1751 + flag = sb_flag(sbh);
1752 +
1753 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1754 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1755 + ASSERT(regs);
1756 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1757 +
1758 + if (irq == 0)
1759 + OR_REG(&sb->sbintvec, 1 << flag);
1760 + else {
1761 + flag <<= sbips_int_shift[irq];
1762 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1763 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1764 + W_REG(&sb->sbipsflag, flag);
1765 + }
1766 +}
1767 +
1768 +/*
1769 + * Initializes clocks and interrupts. SB and NVRAM access must be
1770 + * initialized prior to calling.
1771 + */
1772 +void
1773 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1774 +{
1775 + ulong hz, ns, tmp;
1776 + extifregs_t *eir;
1777 + chipcregs_t *cc;
1778 + char *value;
1779 + uint irq;
1780 +
1781 + /* Figure out current SB clock speed */
1782 + if ((hz = sb_clock(sbh)) == 0)
1783 + hz = 100000000;
1784 + ns = 1000000000 / hz;
1785 +
1786 + /* Setup external interface timing */
1787 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1788 + /* Initialize extif so we can get to the LEDs and external UART */
1789 + W_REG(&eir->prog_config, CF_EN);
1790 +
1791 + /* Set timing for the flash */
1792 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1793 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1794 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1795 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1796 +
1797 + /* Set programmable interface timing for external uart */
1798 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1799 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1800 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1801 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1802 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1803 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1804 + /* Set timing for the flash */
1805 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1806 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1807 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1808 +
1809 + // Added by Chen-I for 5365
1810 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1811 + {
1812 + W_REG(&cc->flash_waitcount, tmp);
1813 + W_REG(&cc->pcmcia_memwait, tmp);
1814 + }
1815 + else
1816 + {
1817 + if (sb_corerev(sbh) < 9)
1818 + W_REG(&cc->flash_waitcount, tmp);
1819 +
1820 + if ((sb_corerev(sbh) < 9) ||
1821 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1822 + W_REG(&cc->pcmcia_memwait, tmp);
1823 + }
1824 + }
1825 + }
1826 +
1827 + /* Chip specific initialization */
1828 + switch (BCMINIT(sb_chip)(sbh)) {
1829 + case BCM4710_DEVICE_ID:
1830 + /* Clear interrupt map */
1831 + for (irq = 0; irq <= 4; irq++)
1832 + BCMINIT(sb_clearirq)(sbh, irq);
1833 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1834 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1835 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1836 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1837 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1838 + ASSERT(eir);
1839 + value = BCMINIT(nvram_get)("et0phyaddr");
1840 + if (value && !strcmp(value, "31")) {
1841 + /* Enable internal UART */
1842 + W_REG(&eir->corecontrol, CC_UE);
1843 + /* Give USB its own interrupt */
1844 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1845 + } else {
1846 + /* Disable internal UART */
1847 + W_REG(&eir->corecontrol, 0);
1848 + /* Give Ethernet its own interrupt */
1849 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1850 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1851 + }
1852 + break;
1853 + case BCM5350_DEVICE_ID:
1854 + /* Clear interrupt map */
1855 + for (irq = 0; irq <= 4; irq++)
1856 + BCMINIT(sb_clearirq)(sbh, irq);
1857 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1858 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1859 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1860 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1861 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1862 + break;
1863 + }
1864 +}
1865 +
1866 +uint32
1867 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1868 +{
1869 + extifregs_t *eir;
1870 + chipcregs_t *cc;
1871 + uint32 n, m;
1872 + uint idx;
1873 + uint32 pll_type, rate = 0;
1874 +
1875 + /* get index of the current core */
1876 + idx = sb_coreidx(sbh);
1877 + pll_type = PLL_TYPE1;
1878 +
1879 + /* switch to extif or chipc core */
1880 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1881 + n = R_REG(&eir->clockcontrol_n);
1882 + m = R_REG(&eir->clockcontrol_sb);
1883 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1884 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1885 + n = R_REG(&cc->clockcontrol_n);
1886 + if ((pll_type == PLL_TYPE2) ||
1887 + (pll_type == PLL_TYPE4) ||
1888 + (pll_type == PLL_TYPE6) ||
1889 + (pll_type == PLL_TYPE7))
1890 + m = R_REG(&cc->clockcontrol_mips);
1891 + else if (pll_type == PLL_TYPE5) {
1892 + rate = 200000000;
1893 + goto out;
1894 + }
1895 + else if (pll_type == PLL_TYPE3) {
1896 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1897 + rate = 200000000;
1898 + goto out;
1899 + } else
1900 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1901 + } else
1902 + m = R_REG(&cc->clockcontrol_sb);
1903 + } else
1904 + goto out;
1905 +
1906 + // Added by Chen-I for 5365
1907 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1908 + rate = 100000000;
1909 + else
1910 + /* calculate rate */
1911 + rate = sb_clock_rate(pll_type, n, m);
1912 +
1913 + if (pll_type == PLL_TYPE6)
1914 + rate = SB2MIPS_T6(rate);
1915 +
1916 +out:
1917 + /* switch back to previous core */
1918 + sb_setcoreidx(sbh, idx);
1919 +
1920 + return rate;
1921 +}
1922 +
1923 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1924 +
1925 +static void
1926 +BCMINITFN(handler)(void)
1927 +{
1928 + /* Step 11 */
1929 + __asm__ (
1930 + ".set\tmips32\n\t"
1931 + "ssnop\n\t"
1932 + "ssnop\n\t"
1933 + /* Disable interrupts */
1934 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1935 + "mfc0 $15, $12\n\t"
1936 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1937 + "li $14, -31746\n\t"
1938 + "and $15, $15, $14\n\t"
1939 + "mtc0 $15, $12\n\t"
1940 + "eret\n\t"
1941 + "nop\n\t"
1942 + "nop\n\t"
1943 + ".set\tmips0"
1944 + );
1945 +}
1946 +
1947 +/* The following MUST come right after handler() */
1948 +static void
1949 +BCMINITFN(afterhandler)(void)
1950 +{
1951 +}
1952 +
1953 +/*
1954 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1955 + */
1956 +bool
1957 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1958 +{
1959 + extifregs_t *eir = NULL;
1960 + chipcregs_t *cc = NULL;
1961 + mipsregs_t *mipsr = NULL;
1962 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1963 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1964 + uint32 pll_type, sync_mode;
1965 + uint ic_size, ic_lsize;
1966 + uint idx, i;
1967 + typedef struct {
1968 + uint32 mipsclock;
1969 + uint16 n;
1970 + uint32 sb;
1971 + uint32 pci33;
1972 + uint32 pci25;
1973 + } n3m_table_t;
1974 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1975 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1976 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1977 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1978 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1979 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1980 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1981 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1982 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1983 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1984 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1985 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1986 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1987 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1988 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1989 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1990 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1991 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1992 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1993 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1994 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1995 + };
1996 + typedef struct {
1997 + uint32 mipsclock;
1998 + uint16 n;
1999 + uint32 m2; /* that is the clockcontrol_m2 */
2000 + } type3_table_t;
2001 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
2002 + { 150000000, 0x311, 0x4020005 },
2003 + { 200000000, 0x311, 0x4020003 },
2004 + };
2005 + typedef struct {
2006 + uint32 mipsclock;
2007 + uint32 sbclock;
2008 + uint16 n;
2009 + uint32 sb;
2010 + uint32 pci33;
2011 + uint32 m2;
2012 + uint32 m3;
2013 + uint32 ratio_cfg;
2014 + uint32 ratio_parm;
2015 + } n4m_table_t;
2016 +
2017 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2018 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2019 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2020 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2021 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2023 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2026 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2027 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2028 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2029 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2031 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2032 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2033 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2034 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2035 + };
2036 +
2037 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2038 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2039 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2041 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2042 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2043 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2045 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2047 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2048 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2049 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2050 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2051 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2052 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2053 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2054 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2055 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2056 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2057 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2058 + };
2059 +
2060 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2061 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2062 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2063 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2065 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2066 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2067 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2068 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2070 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2071 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2072 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2073 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2074 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2075 + };
2076 +
2077 + ulong start, end, dst;
2078 + bool ret = FALSE;
2079 +
2080 + /* get index of the current core */
2081 + idx = sb_coreidx(sbh);
2082 + clockcontrol_m2 = NULL;
2083 +
2084 + /* switch to extif or chipc core */
2085 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2086 + pll_type = PLL_TYPE1;
2087 + clockcontrol_n = &eir->clockcontrol_n;
2088 + clockcontrol_sb = &eir->clockcontrol_sb;
2089 + clockcontrol_pci = &eir->clockcontrol_pci;
2090 + clockcontrol_m2 = &cc->clockcontrol_m2;
2091 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2092 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2093 + if (pll_type == PLL_TYPE6) {
2094 + clockcontrol_n = NULL;
2095 + clockcontrol_sb = NULL;
2096 + clockcontrol_pci = NULL;
2097 + } else {
2098 + clockcontrol_n = &cc->clockcontrol_n;
2099 + clockcontrol_sb = &cc->clockcontrol_sb;
2100 + clockcontrol_pci = &cc->clockcontrol_pci;
2101 + clockcontrol_m2 = &cc->clockcontrol_m2;
2102 + }
2103 + } else
2104 + goto done;
2105 +
2106 + if (pll_type == PLL_TYPE6) {
2107 + /* Silence compilers */
2108 + orig_n = orig_sb = orig_pci = 0;
2109 + } else {
2110 + /* Store the current clock register values */
2111 + orig_n = R_REG(clockcontrol_n);
2112 + orig_sb = R_REG(clockcontrol_sb);
2113 + orig_pci = R_REG(clockcontrol_pci);
2114 + }
2115 +
2116 + if (pll_type == PLL_TYPE1) {
2117 + /* Keep the current PCI clock if not specified */
2118 + if (pciclock == 0) {
2119 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2120 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2121 + }
2122 +
2123 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2124 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2125 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2126 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2127 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2128 + break;
2129 + }
2130 + if (i == 0) {
2131 + ret = FALSE;
2132 + goto done;
2133 + } else {
2134 + ret = TRUE;
2135 + i--;
2136 + }
2137 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2138 +
2139 + /* No PLL change */
2140 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2141 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2142 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2143 + goto done;
2144 +
2145 + /* Set the PLL controls */
2146 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2147 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2148 + if (pciclock == 25000000)
2149 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2150 + else
2151 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2152 +
2153 + /* Reset */
2154 + sb_watchdog(sbh, 1);
2155 +
2156 + while (1);
2157 + } else if ((pll_type == PLL_TYPE3) &&
2158 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2159 + /* 5350 */
2160 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2161 +
2162 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2163 + if (type3_table[i].mipsclock > mipsclock)
2164 + break;
2165 + }
2166 + if (i == 0) {
2167 + ret = FALSE;
2168 + goto done;
2169 + } else {
2170 + ret = TRUE;
2171 + i--;
2172 + }
2173 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2174 +
2175 + /* No PLL change */
2176 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2177 + if ((orig_n == type3_table[i].n) &&
2178 + (orig_m2 == type3_table[i].m2)) {
2179 + goto done;
2180 + }
2181 +
2182 + /* Set the PLL controls */
2183 + W_REG(clockcontrol_n, type3_table[i].n);
2184 + W_REG(clockcontrol_m2, type3_table[i].m2);
2185 +
2186 + /* Reset */
2187 + sb_watchdog(sbh, 1);
2188 + while (1);
2189 + } else if ((pll_type == PLL_TYPE2) ||
2190 + (pll_type == PLL_TYPE4) ||
2191 + (pll_type == PLL_TYPE6) ||
2192 + (pll_type == PLL_TYPE7)) {
2193 + n4m_table_t *table = NULL, *te;
2194 + uint tabsz = 0;
2195 +
2196 + ASSERT(cc);
2197 +
2198 + orig_mips = R_REG(&cc->clockcontrol_mips);
2199 +
2200 + if (pll_type == PLL_TYPE6) {
2201 + uint32 new_mips = 0;
2202 +
2203 + ret = TRUE;
2204 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2205 + new_mips = CC_T6_MMASK;
2206 +
2207 + if (orig_mips == new_mips)
2208 + goto done;
2209 +
2210 + W_REG(&cc->clockcontrol_mips, new_mips);
2211 + goto end_fill;
2212 + }
2213 +
2214 + if (pll_type == PLL_TYPE2) {
2215 + table = BCMINIT(type2_table);
2216 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2217 + } else if (pll_type == PLL_TYPE4) {
2218 + table = BCMINIT(type4_table);
2219 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2220 + } else if (pll_type == PLL_TYPE7) {
2221 + table = BCMINIT(type7_table);
2222 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2223 + } else
2224 + ASSERT("No table for plltype" == NULL);
2225 +
2226 + /* Store the current clock register values */
2227 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2228 + orig_ratio_parm = 0;
2229 + orig_ratio_cfg = 0;
2230 +
2231 + /* Look up current ratio */
2232 + for (i = 0; i < tabsz; i++) {
2233 + if ((orig_n == table[i].n) &&
2234 + (orig_sb == table[i].sb) &&
2235 + (orig_pci == table[i].pci33) &&
2236 + (orig_m2 == table[i].m2) &&
2237 + (orig_mips == table[i].m3)) {
2238 + orig_ratio_parm = table[i].ratio_parm;
2239 + orig_ratio_cfg = table[i].ratio_cfg;
2240 + break;
2241 + }
2242 + }
2243 +
2244 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2245 + for (i = 0; i < tabsz; i++) {
2246 + ASSERT(table[i].mipsclock ==
2247 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2248 + if ((mipsclock <= table[i].mipsclock) &&
2249 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2250 + break;
2251 + }
2252 + if (i == tabsz) {
2253 + ret = FALSE;
2254 + goto done;
2255 + } else {
2256 + te = &table[i];
2257 + ret = TRUE;
2258 + }
2259 +
2260 + /* No PLL change */
2261 + if ((orig_n == te->n) &&
2262 + (orig_sb == te->sb) &&
2263 + (orig_pci == te->pci33) &&
2264 + (orig_m2 == te->m2) &&
2265 + (orig_mips == te->m3))
2266 + goto done;
2267 +
2268 + /* Set the PLL controls */
2269 + W_REG(clockcontrol_n, te->n);
2270 + W_REG(clockcontrol_sb, te->sb);
2271 + W_REG(clockcontrol_pci, te->pci33);
2272 + W_REG(&cc->clockcontrol_m2, te->m2);
2273 + W_REG(&cc->clockcontrol_mips, te->m3);
2274 +
2275 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2276 + if ((pll_type == PLL_TYPE7) &&
2277 + (te->sb != te->m2) &&
2278 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2279 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2280 +
2281 + /* No ratio change */
2282 + if (orig_ratio_parm == te->ratio_parm)
2283 + goto end_fill;
2284 +
2285 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2286 +
2287 + /* Preload the code into the cache */
2288 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2289 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2290 + while (start < end) {
2291 + cache_op(start, Fill_I);
2292 + start += ic_lsize;
2293 + }
2294 +
2295 + /* Copy the handler */
2296 + start = (ulong) &BCMINIT(handler);
2297 + end = (ulong) &BCMINIT(afterhandler);
2298 + dst = KSEG1ADDR(0x180);
2299 + for (i = 0; i < (end - start); i += 4)
2300 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2301 +
2302 + /* Preload handler into the cache one line at a time */
2303 + for (i = 0; i < (end - start); i += 4)
2304 + cache_op(dst + i, Fill_I);
2305 +
2306 + /* Clear BEV bit */
2307 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2308 +
2309 + /* Enable interrupts */
2310 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2311 +
2312 + /* Enable MIPS timer interrupt */
2313 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2314 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2315 + ASSERT(mipsr);
2316 + W_REG(&mipsr->intmask, 1);
2317 +
2318 + start_fill:
2319 + /* step 1, set clock ratios */
2320 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2321 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2322 +
2323 + /* step 2: program timer intr */
2324 + W_REG(&mipsr->timer, 100);
2325 + (void) R_REG(&mipsr->timer);
2326 +
2327 + /* step 3, switch to async */
2328 + sync_mode = MFC0(C0_BROADCOM, 4);
2329 + MTC0(C0_BROADCOM, 4, 1 << 22);
2330 +
2331 + /* step 4, set cfg active */
2332 + MTC0(C0_BROADCOM, 2, 0x9);
2333 +
2334 +
2335 + /* steps 5 & 6 */
2336 + __asm__ __volatile__ (
2337 + ".set\tmips3\n\t"
2338 + "wait\n\t"
2339 + ".set\tmips0"
2340 + );
2341 +
2342 + /* step 7, clear cfg_active */
2343 + MTC0(C0_BROADCOM, 2, 0);
2344 +
2345 + /* Additional Step: set back to orig sync mode */
2346 + MTC0(C0_BROADCOM, 4, sync_mode);
2347 +
2348 + /* step 8, fake soft reset */
2349 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2350 +
2351 + end_fill:
2352 + /* step 9 set watchdog timer */
2353 + sb_watchdog(sbh, 20);
2354 + (void) R_REG(&cc->chipid);
2355 +
2356 + /* step 11 */
2357 + __asm__ __volatile__ (
2358 + ".set\tmips3\n\t"
2359 + "sync\n\t"
2360 + "wait\n\t"
2361 + ".set\tmips0"
2362 + );
2363 + while (1);
2364 + }
2365 +
2366 +done:
2367 + /* switch back to previous core */
2368 + sb_setcoreidx(sbh, idx);
2369 +
2370 + return ret;
2371 +}
2372 +
2373 +/*
2374 + * This also must be run from the cache on 47xx
2375 + * so there are no mips core BIU ops in progress
2376 + * when the PFC is enabled.
2377 + */
2378 +
2379 +static void
2380 +BCMINITFN(_enable_pfc)(uint32 mode)
2381 +{
2382 + /* write range */
2383 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2384 +
2385 + /* enable */
2386 + *(volatile uint32 *)PFC_CR0 = mode;
2387 +}
2388 +
2389 +void
2390 +BCMINITFN(enable_pfc)(uint32 mode)
2391 +{
2392 + ulong start, end;
2393 + int i;
2394 +
2395 + /* If auto then choose the correct mode for this
2396 + platform, currently we only ever select one mode */
2397 + if (mode == PFC_AUTO)
2398 + mode = PFC_INST;
2399 +
2400 + /* enable prefetch cache if available */
2401 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2402 + start = (ulong) &BCMINIT(_enable_pfc);
2403 + end = (ulong) &BCMINIT(enable_pfc);
2404 +
2405 + /* Preload handler into the cache one line at a time */
2406 + for (i = 0; i < (end - start); i += 4)
2407 + cache_op(start + i, Fill_I);
2408 +
2409 + BCMINIT(_enable_pfc)(mode);
2410 + }
2411 +}
2412 +
2413 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2414 +uint32
2415 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2416 +{
2417 + sbmemcregs_t *memc;
2418 + uint32 ret = 0;
2419 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2420 + uint idx, rev;
2421 +
2422 + idx = sb_coreidx(sbh);
2423 +
2424 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2425 + if (memc == 0)
2426 + goto out;
2427 +
2428 + rev = sb_corerev(sbh);
2429 +
2430 + config = R_REG(&memc->config);
2431 + wr = R_REG(&memc->wrncdlcor);
2432 + rd = R_REG(&memc->rdncdlcor);
2433 + misc = R_REG(&memc->miscdlyctl);
2434 + dqsg = R_REG(&memc->dqsgatencdl);
2435 +
2436 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2437 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2438 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2439 +
2440 + if (config & MEMC_CONFIG_DDR) {
2441 + ret = (wr << 16) | (rd << 8) | dqsg;
2442 + } else {
2443 + if (rev > 0)
2444 + cd = rd;
2445 + else
2446 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2447 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2448 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2449 + ret = (sm << 16) | (sd << 8) | cd;
2450 + }
2451 +
2452 +out:
2453 + /* switch back to previous core */
2454 + sb_setcoreidx(sbh, idx);
2455 +
2456 + return ret;
2457 +}
2458 +
2459 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2460 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2461 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2005-12-15 23:50:31.846688500 +0100
2462 @@ -0,0 +1,531 @@
2463 +/*
2464 + * Low-Level PCI and SB support for BCM47xx
2465 + *
2466 + * Copyright 2005, Broadcom Corporation
2467 + * All Rights Reserved.
2468 + *
2469 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2470 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2471 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2472 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2473 + *
2474 + * $Id$
2475 + */
2476 +
2477 +#include <typedefs.h>
2478 +#include <pcicfg.h>
2479 +#include <bcmdevs.h>
2480 +#include <sbconfig.h>
2481 +#include <osl.h>
2482 +#include <sbutils.h>
2483 +#include <sbpci.h>
2484 +#include <bcmendian.h>
2485 +#include <bcmutils.h>
2486 +#include <bcmnvram.h>
2487 +#include <hndmips.h>
2488 +
2489 +/* Can free sbpci_init() memory after boot */
2490 +#ifndef linux
2491 +#define __init
2492 +#endif
2493 +
2494 +/* Emulated configuration space */
2495 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2496 +
2497 +/* Banned cores */
2498 +static uint16 pci_ban[32] = { 0 };
2499 +static uint pci_banned = 0;
2500 +
2501 +/* CardBus mode */
2502 +static bool cardbus = FALSE;
2503 +
2504 +/* Disable PCI host core */
2505 +static bool pci_disabled = FALSE;
2506 +
2507 +/*
2508 + * Functions for accessing external PCI configuration space
2509 + */
2510 +
2511 +/* Assume one-hot slot wiring */
2512 +#define PCI_SLOT_MAX 16
2513 +
2514 +static uint32
2515 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2516 +{
2517 + uint coreidx;
2518 + sbpciregs_t *regs;
2519 + uint32 addr = 0;
2520 +
2521 + /* CardBusMode supports only one device */
2522 + if (cardbus && dev > 1)
2523 + return 0;
2524 +
2525 + coreidx = sb_coreidx(sbh);
2526 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2527 +
2528 + /* Type 0 transaction */
2529 + if (bus == 1) {
2530 + /* Skip unwired slots */
2531 + if (dev < PCI_SLOT_MAX) {
2532 + /* Slide the PCI window to the appropriate slot */
2533 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2534 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2535 + (func << 8) | (off & ~3);
2536 + }
2537 + }
2538 +
2539 + /* Type 1 transaction */
2540 + else {
2541 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2542 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2543 + }
2544 +
2545 + sb_setcoreidx(sbh, coreidx);
2546 +
2547 + return addr;
2548 +}
2549 +
2550 +static int
2551 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2552 +{
2553 + uint32 addr, *reg = NULL, val;
2554 + int ret = 0;
2555 +
2556 + if (pci_disabled ||
2557 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2558 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2559 + BUSPROBE(val, reg))
2560 + val = 0xffffffff;
2561 +
2562 + val >>= 8 * (off & 3);
2563 + if (len == 4)
2564 + *((uint32 *) buf) = val;
2565 + else if (len == 2)
2566 + *((uint16 *) buf) = (uint16) val;
2567 + else if (len == 1)
2568 + *((uint8 *) buf) = (uint8) val;
2569 + else
2570 + ret = -1;
2571 +
2572 + if (reg)
2573 + REG_UNMAP(reg);
2574 +
2575 + return ret;
2576 +}
2577 +
2578 +static int
2579 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2580 +{
2581 + uint32 addr, *reg = NULL, val;
2582 + int ret = 0;
2583 +
2584 + if (pci_disabled ||
2585 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2586 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2587 + BUSPROBE(val, reg))
2588 + goto done;
2589 +
2590 + if (len == 4)
2591 + val = *((uint32 *) buf);
2592 + else if (len == 2) {
2593 + val &= ~(0xffff << (8 * (off & 3)));
2594 + val |= *((uint16 *) buf) << (8 * (off & 3));
2595 + } else if (len == 1) {
2596 + val &= ~(0xff << (8 * (off & 3)));
2597 + val |= *((uint8 *) buf) << (8 * (off & 3));
2598 + } else
2599 + ret = -1;
2600 +
2601 + W_REG(reg, val);
2602 +
2603 + done:
2604 + if (reg)
2605 + REG_UNMAP(reg);
2606 +
2607 + return ret;
2608 +}
2609 +
2610 +/*
2611 + * Functions for accessing translated SB configuration space
2612 + */
2613 +
2614 +static int
2615 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2616 +{
2617 + pci_config_regs *cfg;
2618 +
2619 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2620 + return -1;
2621 + cfg = &sb_config_regs[dev];
2622 +
2623 + ASSERT(ISALIGNED(off, len));
2624 + ASSERT(ISALIGNED((uintptr)buf, len));
2625 +
2626 + if (len == 4)
2627 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2628 + else if (len == 2)
2629 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2630 + else if (len == 1)
2631 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2632 + else
2633 + return -1;
2634 +
2635 + return 0;
2636 +}
2637 +
2638 +static int
2639 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2640 +{
2641 + uint coreidx, n;
2642 + void *regs;
2643 + sbconfig_t *sb;
2644 + pci_config_regs *cfg;
2645 +
2646 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2647 + return -1;
2648 + cfg = &sb_config_regs[dev];
2649 +
2650 + ASSERT(ISALIGNED(off, len));
2651 + ASSERT(ISALIGNED((uintptr)buf, len));
2652 +
2653 + /* Emulate BAR sizing */
2654 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2655 + len == 4 && *((uint32 *) buf) == ~0) {
2656 + coreidx = sb_coreidx(sbh);
2657 + if ((regs = sb_setcoreidx(sbh, dev))) {
2658 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2659 + /* Highest numbered address match register */
2660 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2661 + if (off == OFFSETOF(pci_config_regs, base[0]))
2662 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2663 +#if 0
2664 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2665 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2666 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2667 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2668 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2669 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2670 +#endif
2671 + }
2672 + sb_setcoreidx(sbh, coreidx);
2673 + return 0;
2674 + }
2675 +
2676 + if (len == 4)
2677 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2678 + else if (len == 2)
2679 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2680 + else if (len == 1)
2681 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2682 + else
2683 + return -1;
2684 +
2685 + return 0;
2686 +}
2687 +
2688 +int
2689 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2690 +{
2691 + if (bus == 0)
2692 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2693 + else
2694 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2695 +}
2696 +
2697 +int
2698 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2699 +{
2700 + if (bus == 0)
2701 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2702 + else
2703 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2704 +}
2705 +
2706 +void
2707 +sbpci_ban(uint16 core)
2708 +{
2709 + if (pci_banned < ARRAYSIZE(pci_ban))
2710 + pci_ban[pci_banned++] = core;
2711 +}
2712 +
2713 +static int
2714 +sbpci_init_pci(sb_t *sbh)
2715 +{
2716 + uint chip, chiprev, chippkg, host;
2717 + uint32 boardflags;
2718 + sbpciregs_t *pci;
2719 + sbconfig_t *sb;
2720 + uint32 val;
2721 +
2722 + chip = sb_chip(sbh);
2723 + chiprev = sb_chiprev(sbh);
2724 + chippkg = sb_chippkg(sbh);
2725 +
2726 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2727 + printf("PCI: no core\n");
2728 + pci_disabled = TRUE;
2729 + return -1;
2730 + }
2731 + sb_core_reset(sbh, 0);
2732 +
2733 + boardflags = (uint32) getintvar(NULL, "boardflags");
2734 +
2735 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2736 + pci_disabled = TRUE;
2737 +
2738 + /*
2739 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2740 + * PCI is bonded out, some boards may leave the pins
2741 + * floating.
2742 + */
2743 + if (((chip == BCM4712_DEVICE_ID) &&
2744 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2745 + (chippkg == BCM4712MID_PKG_ID))) ||
2746 + (boardflags & BFL_NOPCI))
2747 + pci_disabled = TRUE;
2748 +
2749 + /*
2750 + * If the PCI core should not be touched (disabled, not bonded
2751 + * out, or pins floating), do not even attempt to access core
2752 + * registers. Otherwise, try to determine if it is in host
2753 + * mode.
2754 + */
2755 + if (pci_disabled)
2756 + host = 0;
2757 + else
2758 + host = !BUSPROBE(val, &pci->control);
2759 +
2760 + if (!host) {
2761 + /* Disable PCI interrupts in client mode */
2762 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2763 + W_REG(&sb->sbintvec, 0);
2764 +
2765 + /* Disable the PCI bridge in client mode */
2766 + sbpci_ban(SB_PCI);
2767 + printf("PCI: Disabled\n");
2768 + } else {
2769 + /* Reset the external PCI bus and enable the clock */
2770 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2771 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2772 + OSL_DELAY(150); /* delay > 100 us */
2773 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2774 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2775 + OSL_DELAY(1); /* delay 1 us */
2776 +
2777 + /* Enable CardBusMode */
2778 + cardbus = nvram_match("cardbus", "1");
2779 + if (cardbus) {
2780 + printf("PCI: Enabling CardBus\n");
2781 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2782 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2783 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2784 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2785 + }
2786 +
2787 + /* 64 MB I/O access window */
2788 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2789 + /* 64 MB configuration access window */
2790 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2791 + /* 1 GB memory access window */
2792 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2793 +
2794 + /* Enable PCI bridge BAR0 prefetch and burst */
2795 + val = 6;
2796 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2797 +
2798 + /* Enable PCI interrupts */
2799 + W_REG(&pci->intmask, PCI_INTA);
2800 + }
2801 +
2802 + return 0;
2803 +}
2804 +
2805 +static int
2806 +sbpci_init_cores(sb_t *sbh)
2807 +{
2808 + uint chip, chiprev, chippkg, coreidx, i;
2809 + sbconfig_t *sb;
2810 + pci_config_regs *cfg;
2811 + void *regs;
2812 + char varname[8];
2813 + uint wlidx = 0;
2814 + uint16 vendor, core;
2815 + uint8 class, subclass, progif;
2816 + uint32 val;
2817 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2818 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2819 +
2820 + chip = sb_chip(sbh);
2821 + chiprev = sb_chiprev(sbh);
2822 + chippkg = sb_chippkg(sbh);
2823 + coreidx = sb_coreidx(sbh);
2824 +
2825 + /* Scan the SB bus */
2826 + bzero(sb_config_regs, sizeof(sb_config_regs));
2827 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2828 + cfg->vendor = 0xffff;
2829 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2830 + continue;
2831 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2832 +
2833 + /* Read ID register and parse vendor and core */
2834 + val = R_REG(&sb->sbidhigh);
2835 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2836 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2837 + progif = 0;
2838 +
2839 + /* Check if this core is banned */
2840 + for (i = 0; i < pci_banned; i++)
2841 + if (core == pci_ban[i])
2842 + break;
2843 + if (i < pci_banned)
2844 + continue;
2845 +
2846 + /* Known vendor translations */
2847 + switch (vendor) {
2848 + case SB_VEND_BCM:
2849 + vendor = VENDOR_BROADCOM;
2850 + break;
2851 + }
2852 +
2853 + /* Determine class based on known core codes */
2854 + switch (core) {
2855 + case SB_ILINE20:
2856 + class = PCI_CLASS_NET;
2857 + subclass = PCI_NET_ETHER;
2858 + core = BCM47XX_ILINE_ID;
2859 + break;
2860 + case SB_ILINE100:
2861 + class = PCI_CLASS_NET;
2862 + subclass = PCI_NET_ETHER;
2863 + core = BCM4610_ILINE_ID;
2864 + break;
2865 + case SB_ENET:
2866 + class = PCI_CLASS_NET;
2867 + subclass = PCI_NET_ETHER;
2868 + core = BCM47XX_ENET_ID;
2869 + break;
2870 + case SB_SDRAM:
2871 + case SB_MEMC:
2872 + class = PCI_CLASS_MEMORY;
2873 + subclass = PCI_MEMORY_RAM;
2874 + break;
2875 + case SB_PCI:
2876 + class = PCI_CLASS_BRIDGE;
2877 + subclass = PCI_BRIDGE_PCI;
2878 + break;
2879 + case SB_MIPS:
2880 + case SB_MIPS33:
2881 + class = PCI_CLASS_CPU;
2882 + subclass = PCI_CPU_MIPS;
2883 + break;
2884 + case SB_CODEC:
2885 + class = PCI_CLASS_COMM;
2886 + subclass = PCI_COMM_MODEM;
2887 + core = BCM47XX_V90_ID;
2888 + break;
2889 + case SB_USB:
2890 + class = PCI_CLASS_SERIAL;
2891 + subclass = PCI_SERIAL_USB;
2892 + progif = 0x10; /* OHCI */
2893 + core = BCM47XX_USB_ID;
2894 + break;
2895 + case SB_USB11H:
2896 + class = PCI_CLASS_SERIAL;
2897 + subclass = PCI_SERIAL_USB;
2898 + progif = 0x10; /* OHCI */
2899 + core = BCM47XX_USBH_ID;
2900 + break;
2901 + case SB_USB11D:
2902 + class = PCI_CLASS_SERIAL;
2903 + subclass = PCI_SERIAL_USB;
2904 + core = BCM47XX_USBD_ID;
2905 + break;
2906 + case SB_IPSEC:
2907 + class = PCI_CLASS_CRYPT;
2908 + subclass = PCI_CRYPT_NETWORK;
2909 + core = BCM47XX_IPSEC_ID;
2910 + break;
2911 + case SB_ROBO:
2912 + class = PCI_CLASS_NET;
2913 + subclass = PCI_NET_OTHER;
2914 + core = BCM47XX_ROBO_ID;
2915 + break;
2916 + case SB_EXTIF:
2917 + case SB_CC:
2918 + class = PCI_CLASS_MEMORY;
2919 + subclass = PCI_MEMORY_FLASH;
2920 + break;
2921 + case SB_D11:
2922 + class = PCI_CLASS_NET;
2923 + subclass = PCI_NET_OTHER;
2924 + /* Let an nvram variable override this */
2925 + sprintf(varname, "wl%did", wlidx);
2926 + wlidx++;
2927 + if ((core = getintvar(NULL, varname)) == 0) {
2928 + if (chip == BCM4712_DEVICE_ID) {
2929 + if (chippkg == BCM4712SMALL_PKG_ID)
2930 + core = BCM4306_D11G_ID;
2931 + else
2932 + core = BCM4306_D11DUAL_ID;
2933 + } else {
2934 + /* 4310 */
2935 + core = BCM4310_D11B_ID;
2936 + }
2937 + }
2938 + break;
2939 +
2940 + default:
2941 + class = subclass = progif = 0xff;
2942 + break;
2943 + }
2944 +
2945 + /* Supported translations */
2946 + cfg->vendor = htol16(vendor);
2947 + cfg->device = htol16(core);
2948 + cfg->rev_id = chiprev;
2949 + cfg->prog_if = progif;
2950 + cfg->sub_class = subclass;
2951 + cfg->base_class = class;
2952 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2953 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
2954 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
2955 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
2956 + cfg->base[4] = 0;
2957 + cfg->base[5] = 0;
2958 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2959 + cfg->header_type = PCI_HEADER_BRIDGE;
2960 + else
2961 + cfg->header_type = PCI_HEADER_NORMAL;
2962 + /* Save core interrupt flag */
2963 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2964 + /* Default to MIPS shared interrupt 0 */
2965 + cfg->int_line = 0;
2966 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2967 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2968 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2969 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2970 + val = R_REG(&sb->sbipsflag);
2971 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
2972 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
2973 + break;
2974 + }
2975 + if (cfg->int_line > 4)
2976 + cfg->int_line = 0;
2977 + }
2978 + /* Emulated core */
2979 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
2980 + }
2981 +
2982 + sb_setcoreidx(sbh, coreidx);
2983 + return 0;
2984 +}
2985 +
2986 +int __init
2987 +sbpci_init(sb_t *sbh)
2988 +{
2989 + sbpci_init_pci(sbh);
2990 + sbpci_init_cores(sbh);
2991 + return 0;
2992 +}
2993 +
2994 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
2995 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
2996 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2005-12-17 01:21:12.951254500 +0100
2997 @@ -0,0 +1,2370 @@
2998 +/*
2999 + * Misc utility routines for accessing chip-specific features
3000 + * of the SiliconBackplane-based Broadcom chips.
3001 + *
3002 + * Copyright 2005, Broadcom Corporation
3003 + * All Rights Reserved.
3004 + *
3005 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3006 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3007 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3008 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3009 + * $Id$
3010 + */
3011 +
3012 +#include <typedefs.h>
3013 +#include <osl.h>
3014 +#include <sbutils.h>
3015 +#include <bcmutils.h>
3016 +#include <bcmdevs.h>
3017 +#include <sbconfig.h>
3018 +#include <sbchipc.h>
3019 +#include <sbpci.h>
3020 +#include <pcicfg.h>
3021 +#include <sbextif.h>
3022 +#include <bcmsrom.h>
3023 +
3024 +/* debug/trace */
3025 +#define SB_ERROR(args)
3026 +
3027 +
3028 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3029 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3030 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3031 +
3032 +/* misc sb info needed by some of the routines */
3033 +typedef struct sb_info {
3034 +
3035 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3036 +
3037 + void *osh; /* osl os handle */
3038 + void *sdh; /* bcmsdh handle */
3039 +
3040 + void *curmap; /* current regs va */
3041 + void *regs[SB_MAXCORES]; /* other regs va */
3042 +
3043 + uint curidx; /* current core index */
3044 + uint dev_coreid; /* the core provides driver functions */
3045 +
3046 + uint gpioidx; /* gpio control core index */
3047 + uint gpioid; /* gpio control coretype */
3048 +
3049 + uint numcores; /* # discovered cores */
3050 + uint coreid[SB_MAXCORES]; /* id of each core */
3051 +
3052 + void *intr_arg; /* interrupt callback function arg */
3053 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3054 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3055 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3056 +
3057 +} sb_info_t;
3058 +
3059 +/* local prototypes */
3060 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3061 + uint bustype, void *sdh, char **vars, int *varsz);
3062 +static void BCMINIT(sb_scan)(sb_info_t *si);
3063 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3064 +static uint _sb_coreidx(sb_info_t *si);
3065 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3066 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3067 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3068 +static int sb_pci_fixcfg(sb_info_t *si);
3069 +
3070 +/* delay needed between the mdio control/ mdiodata register data access */
3071 +#define PR28829_DELAY() OSL_DELAY(10)
3072 +
3073 +
3074 +/* global variable to indicate reservation/release of gpio's*/
3075 +static uint32 sb_gpioreservation = 0;
3076 +
3077 +#define SB_INFO(sbh) (sb_info_t*)sbh
3078 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3079 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3080 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3081 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3082 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3083 +#define BADIDX (SB_MAXCORES+1)
3084 +#define NOREV -1
3085 +
3086 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3087 +
3088 +/* sonicsrev */
3089 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3090 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3091 +
3092 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3093 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3094 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3095 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3096 +
3097 +/*
3098 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3099 + * after core switching to avoid invalid register accesss inside ISR.
3100 + */
3101 +#define INTR_OFF(si, intr_val) \
3102 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3103 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3104 +#define INTR_RESTORE(si, intr_val) \
3105 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3106 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3107 +
3108 +/* dynamic clock control defines */
3109 +#define LPOMINFREQ 25000 /* low power oscillator min */
3110 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3111 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3112 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3113 +#define PCIMINFREQ 25000000 /* 25 MHz */
3114 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3115 +
3116 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3117 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3118 +
3119 +#define MIN_DUMPBUFLEN 32 /* debug */
3120 +
3121 +/* GPIO Based LED powersave defines */
3122 +#define DEFAULT_GPIO_ONTIME 10
3123 +#define DEFAULT_GPIO_OFFTIME 90
3124 +
3125 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3126 +
3127 +static uint32
3128 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3129 +{
3130 + uint32 val = R_REG(sbr);
3131 +
3132 + return (val);
3133 +}
3134 +
3135 +static void
3136 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3137 +{
3138 + W_REG(sbr, v);
3139 +}
3140 +
3141 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3142 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3143 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3144 +
3145 +/* global kernel resource */
3146 +static sb_info_t ksi;
3147 +
3148 +/* generic kernel variant of sb_attach() */
3149 +sb_t *
3150 +BCMINITFN(sb_kattach)()
3151 +{
3152 + uint32 *regs;
3153 +
3154 + if (ksi.curmap == NULL) {
3155 + uint32 cid;
3156 +
3157 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3158 + cid = R_REG((uint32 *)regs);
3159 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3160 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3161 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3162 + uint32 *scc, val;
3163 +
3164 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3165 + val = R_REG(scc);
3166 + SB_ERROR((" initial scc = 0x%x\n", val));
3167 + val |= SCC_SS_XTAL;
3168 + W_REG(scc, val);
3169 + }
3170 +
3171 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3172 + SB_BUS, NULL, NULL, NULL) == NULL) {
3173 + return NULL;
3174 + }
3175 + }
3176 +
3177 + return (sb_t *)&ksi;
3178 +}
3179 +#endif
3180 +
3181 +static sb_info_t *
3182 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3183 + uint bustype, void *sdh, char **vars, int *varsz)
3184 +{
3185 + uint origidx;
3186 + chipcregs_t *cc;
3187 + sbconfig_t *sb;
3188 + uint32 w;
3189 +
3190 + ASSERT(GOODREGS(regs));
3191 +
3192 + bzero((uchar*)si, sizeof (sb_info_t));
3193 +
3194 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3195 +
3196 + si->osh = osh;
3197 + si->curmap = regs;
3198 + si->sdh = sdh;
3199 +
3200 + /* check to see if we are a sb core mimic'ing a pci core */
3201 + if (bustype == PCI_BUS) {
3202 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3203 + bustype = SB_BUS;
3204 + else
3205 + bustype = PCI_BUS;
3206 + }
3207 +
3208 + si->sb.bustype = bustype;
3209 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3210 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3211 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3212 + return NULL;
3213 + }
3214 +
3215 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3216 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3217 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3218 +
3219 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3220 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3221 + if (!GOODCOREADDR(w))
3222 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3223 + }
3224 +
3225 + /* initialize current core index value */
3226 + si->curidx = _sb_coreidx(si);
3227 +
3228 + if (si->curidx == BADIDX) {
3229 + SB_ERROR(("sb_doattach: bad core index\n"));
3230 + return NULL;
3231 + }
3232 +
3233 + /* get sonics backplane revision */
3234 + sb = REGS2SB(si->curmap);
3235 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3236 +
3237 + /* keep and reuse the initial register mapping */
3238 + origidx = si->curidx;
3239 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3240 + si->regs[origidx] = regs;
3241 +
3242 + /* is core-0 a chipcommon core? */
3243 + si->numcores = 1;
3244 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3245 + if (sb_coreid(&si->sb) != SB_CC)
3246 + cc = NULL;
3247 +
3248 + /* determine chip id and rev */
3249 + if (cc) {
3250 + /* chip common core found! */
3251 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3252 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3253 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3254 + } else {
3255 + /* no chip common core -- must convert device id to chip id */
3256 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3257 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3258 + sb_setcoreidx(&si->sb, origidx);
3259 + return NULL;
3260 + }
3261 + }
3262 +
3263 + /* get chipcommon rev */
3264 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3265 +
3266 + /* determine numcores */
3267 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3268 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3269 + else
3270 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3271 +
3272 + /* return to original core */
3273 + sb_setcoreidx(&si->sb, origidx);
3274 +
3275 + /* sanity checks */
3276 + ASSERT(si->sb.chip);
3277 +
3278 + /* scan for cores */
3279 + BCMINIT(sb_scan)(si);
3280 +
3281 + /* fixup necessary chip/core configurations */
3282 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3283 + if (sb_pci_fixcfg(si)) {
3284 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3285 + return NULL;
3286 + }
3287 + }
3288 +
3289 + /* srom_var_init() depends on sb_scan() info */
3290 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3291 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3292 + return (NULL);
3293 + }
3294 +
3295 + if (cc == NULL) {
3296 + /*
3297 + * The chip revision number is hardwired into all
3298 + * of the pci function config rev fields and is
3299 + * independent from the individual core revision numbers.
3300 + * For example, the "A0" silicon of each chip is chip rev 0.
3301 + */
3302 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3303 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3304 + si->sb.chiprev = w & 0xff;
3305 + } else
3306 + si->sb.chiprev = 0;
3307 + }
3308 +
3309 + /* gpio control core is required */
3310 + if (!GOODIDX(si->gpioidx)) {
3311 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3312 + return NULL;
3313 + }
3314 +
3315 + /* get boardtype and boardrev */
3316 + switch (BUSTYPE(si->sb.bustype)) {
3317 + case PCI_BUS:
3318 + /* do a pci config read to get subsystem id and subvendor id */
3319 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3320 + si->sb.boardvendor = w & 0xffff;
3321 + si->sb.boardtype = (w >> 16) & 0xffff;
3322 + break;
3323 +
3324 + case SB_BUS:
3325 + case JTAG_BUS:
3326 + si->sb.boardvendor = VENDOR_BROADCOM;
3327 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3328 + si->sb.boardtype = 0xffff;
3329 + break;
3330 + }
3331 +
3332 + if (si->sb.boardtype == 0) {
3333 + SB_ERROR(("sb_doattach: unknown board type\n"));
3334 + ASSERT(si->sb.boardtype);
3335 + }
3336 +
3337 + /* setup the GPIO based LED powersave register */
3338 + if (si->sb.ccrev >= 16) {
3339 + w = getintvar(*vars, "gpiotimerval");
3340 + if (!w)
3341 + w = DEFAULT_GPIOTIMERVAL;
3342 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3343 + }
3344 +
3345 +
3346 + return (si);
3347 +}
3348 +
3349 +uint
3350 +sb_coreid(sb_t *sbh)
3351 +{
3352 + sb_info_t *si;
3353 + sbconfig_t *sb;
3354 +
3355 + si = SB_INFO(sbh);
3356 + sb = REGS2SB(si->curmap);
3357 +
3358 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3359 +}
3360 +
3361 +uint
3362 +sb_coreidx(sb_t *sbh)
3363 +{
3364 + sb_info_t *si;
3365 +
3366 + si = SB_INFO(sbh);
3367 + return (si->curidx);
3368 +}
3369 +
3370 +/* return current index of core */
3371 +static uint
3372 +_sb_coreidx(sb_info_t *si)
3373 +{
3374 + sbconfig_t *sb;
3375 + uint32 sbaddr = 0;
3376 +
3377 + ASSERT(si);
3378 +
3379 + switch (BUSTYPE(si->sb.bustype)) {
3380 + case SB_BUS:
3381 + sb = REGS2SB(si->curmap);
3382 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3383 + break;
3384 +
3385 + case PCI_BUS:
3386 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3387 + break;
3388 +
3389 +#ifdef BCMJTAG
3390 + case JTAG_BUS:
3391 + sbaddr = (uint32)si->curmap;
3392 + break;
3393 +#endif /* BCMJTAG */
3394 +
3395 + default:
3396 + ASSERT(0);
3397 + }
3398 +
3399 + if (!GOODCOREADDR(sbaddr))
3400 + return BADIDX;
3401 +
3402 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3403 +}
3404 +
3405 +uint
3406 +sb_corevendor(sb_t *sbh)
3407 +{
3408 + sb_info_t *si;
3409 + sbconfig_t *sb;
3410 +
3411 + si = SB_INFO(sbh);
3412 + sb = REGS2SB(si->curmap);
3413 +
3414 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3415 +}
3416 +
3417 +uint
3418 +sb_corerev(sb_t *sbh)
3419 +{
3420 + sb_info_t *si;
3421 + sbconfig_t *sb;
3422 + uint sbidh;
3423 +
3424 + si = SB_INFO(sbh);
3425 + sb = REGS2SB(si->curmap);
3426 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3427 +
3428 + return (SBCOREREV(sbidh));
3429 +}
3430 +
3431 +void *
3432 +sb_osh(sb_t *sbh)
3433 +{
3434 + sb_info_t *si;
3435 +
3436 + si = SB_INFO(sbh);
3437 + return si->osh;
3438 +}
3439 +
3440 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3441 +
3442 +/* set/clear sbtmstatelow core-specific flags */
3443 +uint32
3444 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3445 +{
3446 + sb_info_t *si;
3447 + sbconfig_t *sb;
3448 + uint32 w;
3449 +
3450 + si = SB_INFO(sbh);
3451 + sb = REGS2SB(si->curmap);
3452 +
3453 + ASSERT((val & ~mask) == 0);
3454 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3455 +
3456 + /* mask and set */
3457 + if (mask || val) {
3458 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3459 + W_SBREG(si, &sb->sbtmstatelow, w);
3460 + }
3461 +
3462 + /* return the new value */
3463 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3464 +}
3465 +
3466 +/* set/clear sbtmstatehigh core-specific flags */
3467 +uint32
3468 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3469 +{
3470 + sb_info_t *si;
3471 + sbconfig_t *sb;
3472 + uint32 w;
3473 +
3474 + si = SB_INFO(sbh);
3475 + sb = REGS2SB(si->curmap);
3476 +
3477 + ASSERT((val & ~mask) == 0);
3478 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3479 +
3480 + /* mask and set */
3481 + if (mask || val) {
3482 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3483 + W_SBREG(si, &sb->sbtmstatehigh, w);
3484 + }
3485 +
3486 + /* return the new value */
3487 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3488 +}
3489 +
3490 +/* caller needs to take care of core-specific bist hazards */
3491 +int
3492 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3493 +{
3494 + uint32 sblo;
3495 + uint coreidx;
3496 + sb_info_t *si;
3497 + int result = 0;
3498 +
3499 + si = SB_INFO(sbh);
3500 +
3501 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3502 + if (!GOODIDX(coreidx))
3503 + result = BCME_ERROR;
3504 + else {
3505 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3506 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3507 +
3508 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3509 +
3510 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3511 + result = BCME_ERROR;
3512 +
3513 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3514 + }
3515 +
3516 + return result;
3517 +}
3518 +
3519 +bool
3520 +sb_iscoreup(sb_t *sbh)
3521 +{
3522 + sb_info_t *si;
3523 + sbconfig_t *sb;
3524 +
3525 + si = SB_INFO(sbh);
3526 + sb = REGS2SB(si->curmap);
3527 +
3528 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3529 +}
3530 +
3531 +/*
3532 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3533 + * switch back to the original core, and return the new value.
3534 + */
3535 +static uint
3536 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3537 +{
3538 + uint origidx;
3539 + uint32 *r;
3540 + uint w;
3541 + uint intr_val = 0;
3542 +
3543 + ASSERT(GOODIDX(coreidx));
3544 + ASSERT(regoff < SB_CORE_SIZE);
3545 + ASSERT((val & ~mask) == 0);
3546 +
3547 + INTR_OFF(si, intr_val);
3548 +
3549 + /* save current core index */
3550 + origidx = sb_coreidx(&si->sb);
3551 +
3552 + /* switch core */
3553 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3554 +
3555 + /* mask and set */
3556 + if (mask || val) {
3557 + if (regoff >= SBCONFIGOFF) {
3558 + w = (R_SBREG(si, r) & ~mask) | val;
3559 + W_SBREG(si, r, w);
3560 + } else {
3561 + w = (R_REG(r) & ~mask) | val;
3562 + W_REG(r, w);
3563 + }
3564 + }
3565 +
3566 + /* readback */
3567 + if (regoff >= SBCONFIGOFF)
3568 + w = R_SBREG(si, r);
3569 + else
3570 + w = R_REG(r);
3571 +
3572 + /* restore core index */
3573 + if (origidx != coreidx)
3574 + sb_setcoreidx(&si->sb, origidx);
3575 +
3576 + INTR_RESTORE(si, intr_val);
3577 + return (w);
3578 +}
3579 +
3580 +#define DWORD_ALIGN(x) (x & ~(0x03))
3581 +#define BYTE_POS(x) (x & 0x3)
3582 +#define WORD_POS(x) (x & 0x1)
3583 +
3584 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3585 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3586 +
3587 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3588 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3589 +
3590 +#define read_pci_cfg_byte(a) \
3591 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3592 +
3593 +#define read_pci_cfg_write(a) \
3594 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3595 +
3596 +
3597 +/* scan the sb enumerated space to identify all cores */
3598 +static void
3599 +BCMINITFN(sb_scan)(sb_info_t *si)
3600 +{
3601 + uint origidx;
3602 + uint i;
3603 + bool pci;
3604 + uint pciidx;
3605 + uint pcirev;
3606 +
3607 +
3608 +
3609 + /* numcores should already be set */
3610 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3611 +
3612 + /* save current core index */
3613 + origidx = sb_coreidx(&si->sb);
3614 +
3615 + si->sb.buscorerev = NOREV;
3616 + si->sb.buscoreidx = BADIDX;
3617 +
3618 + si->gpioidx = BADIDX;
3619 +
3620 + pci = FALSE;
3621 + pcirev = NOREV;
3622 + pciidx = BADIDX;
3623 +
3624 + for (i = 0; i < si->numcores; i++) {
3625 + sb_setcoreidx(&si->sb, i);
3626 + si->coreid[i] = sb_coreid(&si->sb);
3627 +
3628 + if (si->coreid[i] == SB_PCI) {
3629 + pciidx = i;
3630 + pcirev = sb_corerev(&si->sb);
3631 + pci = TRUE;
3632 + }
3633 + }
3634 + if (pci) {
3635 + si->sb.buscoretype = SB_PCI;
3636 + si->sb.buscorerev = pcirev;
3637 + si->sb.buscoreidx = pciidx;
3638 + }
3639 +
3640 + /*
3641 + * Find the gpio "controlling core" type and index.
3642 + * Precedence:
3643 + * - if there's a chip common core - use that
3644 + * - else if there's a pci core (rev >= 2) - use that
3645 + * - else there had better be an extif core (4710 only)
3646 + */
3647 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3648 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3649 + si->gpioid = SB_CC;
3650 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3651 + si->gpioidx = si->sb.buscoreidx;
3652 + si->gpioid = SB_PCI;
3653 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3654 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3655 + si->gpioid = SB_EXTIF;
3656 + } else
3657 + ASSERT(si->gpioidx != BADIDX);
3658 +
3659 + /* return to original core index */
3660 + sb_setcoreidx(&si->sb, origidx);
3661 +}
3662 +
3663 +/* may be called with core in reset */
3664 +void
3665 +sb_detach(sb_t *sbh)
3666 +{
3667 + sb_info_t *si;
3668 + uint idx;
3669 +
3670 + si = SB_INFO(sbh);
3671 +
3672 + if (si == NULL)
3673 + return;
3674 +
3675 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3676 + for (idx = 0; idx < SB_MAXCORES; idx++)
3677 + if (si->regs[idx]) {
3678 + REG_UNMAP(si->regs[idx]);
3679 + si->regs[idx] = NULL;
3680 + }
3681 +
3682 + if (si != &ksi)
3683 + MFREE(si->osh, si, sizeof (sb_info_t));
3684 +}
3685 +
3686 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3687 +static uint
3688 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3689 +{
3690 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3691 + return (BCM4710_DEVICE_ID);
3692 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3693 + return (BCM4402_DEVICE_ID);
3694 + if (pcidev == BCM4401_ENET_ID)
3695 + return (BCM4402_DEVICE_ID);
3696 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3697 + return (BCM4307_DEVICE_ID);
3698 + if (pcidev == BCM4301_DEVICE_ID)
3699 + return (BCM4301_DEVICE_ID);
3700 +
3701 + return (0);
3702 +}
3703 +
3704 +/* convert chip number to number of i/o cores */
3705 +static uint
3706 +BCMINITFN(sb_chip2numcores)(uint chip)
3707 +{
3708 + if (chip == BCM4710_DEVICE_ID)
3709 + return (9);
3710 + if (chip == BCM4402_DEVICE_ID)
3711 + return (3);
3712 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3713 + return (5);
3714 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3715 + return (6);
3716 + if (chip == BCM4704_DEVICE_ID)
3717 + return (9);
3718 + if (chip == BCM5365_DEVICE_ID)
3719 + return (7);
3720 +
3721 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3722 + ASSERT(0);
3723 + return (1);
3724 +}
3725 +
3726 +/* return index of coreid or BADIDX if not found */
3727 +static uint
3728 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3729 +{
3730 + uint found;
3731 + uint i;
3732 +
3733 + found = 0;
3734 +
3735 + for (i = 0; i < si->numcores; i++)
3736 + if (si->coreid[i] == coreid) {
3737 + if (found == coreunit)
3738 + return (i);
3739 + found++;
3740 + }
3741 +
3742 + return (BADIDX);
3743 +}
3744 +
3745 +/*
3746 + * this function changes logical "focus" to the indiciated core,
3747 + * must be called with interrupt off.
3748 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3749 + */
3750 +void*
3751 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3752 +{
3753 + sb_info_t *si;
3754 + uint32 sbaddr;
3755 +
3756 + si = SB_INFO(sbh);
3757 +
3758 + if (coreidx >= si->numcores)
3759 + return (NULL);
3760 +
3761 + /*
3762 + * If the user has provided an interrupt mask enabled function,
3763 + * then assert interrupts are disabled before switching the core.
3764 + */
3765 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3766 +
3767 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3768 +
3769 + switch (BUSTYPE(si->sb.bustype)) {
3770 + case SB_BUS:
3771 + /* map new one */
3772 + if (!si->regs[coreidx]) {
3773 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3774 + ASSERT(GOODREGS(si->regs[coreidx]));
3775 + }
3776 + si->curmap = si->regs[coreidx];
3777 + break;
3778 +
3779 + case PCI_BUS:
3780 + /* point bar0 window */
3781 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3782 + break;
3783 +
3784 +#ifdef BCMJTAG
3785 + case JTAG_BUS:
3786 + /* map new one */
3787 + if (!si->regs[coreidx]) {
3788 + si->regs[coreidx] = (void *)sbaddr;
3789 + ASSERT(GOODREGS(si->regs[coreidx]));
3790 + }
3791 + si->curmap = si->regs[coreidx];
3792 + break;
3793 +#endif /* BCMJTAG */
3794 + }
3795 +
3796 + si->curidx = coreidx;
3797 +
3798 + return (si->curmap);
3799 +}
3800 +
3801 +/*
3802 + * this function changes logical "focus" to the indiciated core,
3803 + * must be called with interrupt off.
3804 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3805 + */
3806 +void*
3807 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3808 +{
3809 + sb_info_t *si;
3810 + uint idx;
3811 +
3812 + si = SB_INFO(sbh);
3813 + idx = sb_findcoreidx(si, coreid, coreunit);
3814 + if (!GOODIDX(idx))
3815 + return (NULL);
3816 +
3817 + return (sb_setcoreidx(sbh, idx));
3818 +}
3819 +
3820 +/* return chip number */
3821 +uint
3822 +BCMINITFN(sb_chip)(sb_t *sbh)
3823 +{
3824 + sb_info_t *si;
3825 +
3826 + si = SB_INFO(sbh);
3827 + return (si->sb.chip);
3828 +}
3829 +
3830 +/* return chip revision number */
3831 +uint
3832 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3833 +{
3834 + sb_info_t *si;
3835 +
3836 + si = SB_INFO(sbh);
3837 + return (si->sb.chiprev);
3838 +}
3839 +
3840 +/* return chip common revision number */
3841 +uint
3842 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3843 +{
3844 + sb_info_t *si;
3845 +
3846 + si = SB_INFO(sbh);
3847 + return (si->sb.ccrev);
3848 +}
3849 +
3850 +/* return chip package option */
3851 +uint
3852 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3853 +{
3854 + sb_info_t *si;
3855 +
3856 + si = SB_INFO(sbh);
3857 + return (si->sb.chippkg);
3858 +}
3859 +
3860 +/* return PCI core rev. */
3861 +uint
3862 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3863 +{
3864 + sb_info_t *si;
3865 +
3866 + si = SB_INFO(sbh);
3867 + return (si->sb.buscorerev);
3868 +}
3869 +
3870 +bool
3871 +BCMINITFN(sb_war16165)(sb_t *sbh)
3872 +{
3873 + sb_info_t *si;
3874 +
3875 + si = SB_INFO(sbh);
3876 +
3877 + return (PCI(si) && (si->sb.buscorerev <= 10));
3878 +}
3879 +
3880 +/* return board vendor id */
3881 +uint
3882 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3883 +{
3884 + sb_info_t *si;
3885 +
3886 + si = SB_INFO(sbh);
3887 + return (si->sb.boardvendor);
3888 +}
3889 +
3890 +/* return boardtype */
3891 +uint
3892 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3893 +{
3894 + sb_info_t *si;
3895 + char *var;
3896 +
3897 + si = SB_INFO(sbh);
3898 +
3899 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3900 + /* boardtype format is a hex string */
3901 + si->sb.boardtype = getintvar(NULL, "boardtype");
3902 +
3903 + /* backward compatibility for older boardtype string format */
3904 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3905 + if (!strcmp(var, "bcm94710dev"))
3906 + si->sb.boardtype = BCM94710D_BOARD;
3907 + else if (!strcmp(var, "bcm94710ap"))
3908 + si->sb.boardtype = BCM94710AP_BOARD;
3909 + else if (!strcmp(var, "bu4710"))
3910 + si->sb.boardtype = BU4710_BOARD;
3911 + else if (!strcmp(var, "bcm94702mn"))
3912 + si->sb.boardtype = BCM94702MN_BOARD;
3913 + else if (!strcmp(var, "bcm94710r1"))
3914 + si->sb.boardtype = BCM94710R1_BOARD;
3915 + else if (!strcmp(var, "bcm94710r4"))
3916 + si->sb.boardtype = BCM94710R4_BOARD;
3917 + else if (!strcmp(var, "bcm94702cpci"))
3918 + si->sb.boardtype = BCM94702CPCI_BOARD;
3919 + else if (!strcmp(var, "bcm95380_rr"))
3920 + si->sb.boardtype = BCM95380RR_BOARD;
3921 + }
3922 + }
3923 +
3924 + return (si->sb.boardtype);
3925 +}
3926 +
3927 +/* return bus type of sbh device */
3928 +uint
3929 +sb_bus(sb_t *sbh)
3930 +{
3931 + sb_info_t *si;
3932 +
3933 + si = SB_INFO(sbh);
3934 + return (si->sb.bustype);
3935 +}
3936 +
3937 +/* return bus core type */
3938 +uint
3939 +sb_buscoretype(sb_t *sbh)
3940 +{
3941 + sb_info_t *si;
3942 +
3943 + si = SB_INFO(sbh);
3944 +
3945 + return (si->sb.buscoretype);
3946 +}
3947 +
3948 +/* return bus core revision */
3949 +uint
3950 +sb_buscorerev(sb_t *sbh)
3951 +{
3952 + sb_info_t *si;
3953 + si = SB_INFO(sbh);
3954 +
3955 + return (si->sb.buscorerev);
3956 +}
3957 +
3958 +/* return list of found cores */
3959 +uint
3960 +sb_corelist(sb_t *sbh, uint coreid[])
3961 +{
3962 + sb_info_t *si;
3963 +
3964 + si = SB_INFO(sbh);
3965 +
3966 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
3967 + return (si->numcores);
3968 +}
3969 +
3970 +/* return current register mapping */
3971 +void *
3972 +sb_coreregs(sb_t *sbh)
3973 +{
3974 + sb_info_t *si;
3975 +
3976 + si = SB_INFO(sbh);
3977 + ASSERT(GOODREGS(si->curmap));
3978 +
3979 + return (si->curmap);
3980 +}
3981 +
3982 +
3983 +/* do buffered registers update */
3984 +void
3985 +sb_commit(sb_t *sbh)
3986 +{
3987 + sb_info_t *si;
3988 + uint origidx;
3989 + uint intr_val = 0;
3990 +
3991 + si = SB_INFO(sbh);
3992 +
3993 + origidx = si->curidx;
3994 + ASSERT(GOODIDX(origidx));
3995 +
3996 + INTR_OFF(si, intr_val);
3997 +
3998 + /* switch over to chipcommon core if there is one, else use pci */
3999 + if (si->sb.ccrev != NOREV) {
4000 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4001 +
4002 + /* do the buffer registers update */
4003 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4004 + W_REG(&ccregs->broadcastdata, 0x0);
4005 + } else if (PCI(si)) {
4006 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4007 +
4008 + /* do the buffer registers update */
4009 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4010 + W_REG(&pciregs->bcastdata, 0x0);
4011 + } else
4012 + ASSERT(0);
4013 +
4014 + /* restore core index */
4015 + sb_setcoreidx(sbh, origidx);
4016 + INTR_RESTORE(si, intr_val);
4017 +}
4018 +
4019 +/* reset and re-enable a core */
4020 +void
4021 +sb_core_reset(sb_t *sbh, uint32 bits)
4022 +{
4023 + sb_info_t *si;
4024 + sbconfig_t *sb;
4025 + volatile uint32 dummy;
4026 +
4027 + si = SB_INFO(sbh);
4028 + ASSERT(GOODREGS(si->curmap));
4029 + sb = REGS2SB(si->curmap);
4030 +
4031 + /*
4032 + * Must do the disable sequence first to work for arbitrary current core state.
4033 + */
4034 + sb_core_disable(sbh, bits);
4035 +
4036 + /*
4037 + * Now do the initialization sequence.
4038 + */
4039 +
4040 + /* set reset while enabling the clock and forcing them on throughout the core */
4041 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4042 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4043 + OSL_DELAY(1);
4044 +
4045 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4046 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4047 + }
4048 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4049 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4050 + }
4051 +
4052 + /* clear reset and allow it to propagate throughout the core */
4053 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4054 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4055 + OSL_DELAY(1);
4056 +
4057 + /* leave clock enabled */
4058 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4059 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4060 + OSL_DELAY(1);
4061 +}
4062 +
4063 +void
4064 +sb_core_tofixup(sb_t *sbh)
4065 +{
4066 + sb_info_t *si;
4067 + sbconfig_t *sb;
4068 +
4069 + si = SB_INFO(sbh);
4070 +
4071 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4072 + return;
4073 +
4074 + ASSERT(GOODREGS(si->curmap));
4075 + sb = REGS2SB(si->curmap);
4076 +
4077 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4078 + SET_SBREG(si, &sb->sbimconfiglow,
4079 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4080 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4081 + } else {
4082 + if (sb_coreid(sbh) == SB_PCI) {
4083 + SET_SBREG(si, &sb->sbimconfiglow,
4084 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4085 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4086 + } else {
4087 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4088 + }
4089 + }
4090 +
4091 + sb_commit(sbh);
4092 +}
4093 +
4094 +/*
4095 + * Set the initiator timeout for the "master core".
4096 + * The master core is defined to be the core in control
4097 + * of the chip and so it issues accesses to non-memory
4098 + * locations (Because of dma *any* core can access memeory).
4099 + *
4100 + * The routine uses the bus to decide who is the master:
4101 + * SB_BUS => mips
4102 + * JTAG_BUS => chipc
4103 + * PCI_BUS => pci
4104 + *
4105 + * This routine exists so callers can disable initiator
4106 + * timeouts so accesses to very slow devices like otp
4107 + * won't cause an abort. The routine allows arbitrary
4108 + * settings of the service and request timeouts, though.
4109 + *
4110 + * Returns the timeout state before changing it or -1
4111 + * on error.
4112 + */
4113 +
4114 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4115 +
4116 +uint32
4117 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4118 +{
4119 + sb_info_t *si;
4120 + uint origidx, idx;
4121 + uint intr_val = 0;
4122 + uint32 tmp, ret = 0xffffffff;
4123 + sbconfig_t *sb;
4124 +
4125 + si = SB_INFO(sbh);
4126 +
4127 + if ((to & ~TO_MASK) != 0)
4128 + return ret;
4129 +
4130 + /* Figure out the master core */
4131 + idx = BADIDX;
4132 + switch (BUSTYPE(si->sb.bustype)) {
4133 + case PCI_BUS:
4134 + idx = si->sb.buscoreidx;
4135 + break;
4136 + case JTAG_BUS:
4137 + idx = SB_CC_IDX;
4138 + break;
4139 + case SB_BUS:
4140 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4141 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4142 + break;
4143 + default:
4144 + ASSERT(0);
4145 + }
4146 + if (idx == BADIDX)
4147 + return ret;
4148 +
4149 + INTR_OFF(si, intr_val);
4150 + origidx = sb_coreidx(sbh);
4151 +
4152 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4153 +
4154 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4155 + ret = tmp & TO_MASK;
4156 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4157 +
4158 + sb_commit(sbh);
4159 + sb_setcoreidx(sbh, origidx);
4160 + INTR_RESTORE(si, intr_val);
4161 + return ret;
4162 +}
4163 +
4164 +void
4165 +sb_core_disable(sb_t *sbh, uint32 bits)
4166 +{
4167 + sb_info_t *si;
4168 + volatile uint32 dummy;
4169 + uint32 rej;
4170 + sbconfig_t *sb;
4171 +
4172 + si = SB_INFO(sbh);
4173 +
4174 + ASSERT(GOODREGS(si->curmap));
4175 + sb = REGS2SB(si->curmap);
4176 +
4177 + /* if core is already in reset, just return */
4178 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4179 + return;
4180 +
4181 + /* reject value changed between sonics 2.2 and 2.3 */
4182 + if (si->sb.sonicsrev == SONICS_2_2)
4183 + rej = (1 << SBTML_REJ_SHIFT);
4184 + else
4185 + rej = (2 << SBTML_REJ_SHIFT);
4186 +
4187 + /* if clocks are not enabled, put into reset and return */
4188 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4189 + goto disable;
4190 +
4191 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4192 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4193 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4194 + OSL_DELAY(1);
4195 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4196 +
4197 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4198 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4199 + dummy = R_SBREG(si, &sb->sbimstate);
4200 + OSL_DELAY(1);
4201 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4202 + }
4203 +
4204 + /* set reset and reject while enabling the clocks */
4205 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4206 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4207 + OSL_DELAY(10);
4208 +
4209 + /* don't forget to clear the initiator reject bit */
4210 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4211 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4212 +
4213 +disable:
4214 + /* leave reset and reject asserted */
4215 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4216 + OSL_DELAY(1);
4217 +}
4218 +
4219 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4220 +void
4221 +sb_watchdog(sb_t *sbh, uint ticks)
4222 +{
4223 + sb_info_t *si = SB_INFO(sbh);
4224 +
4225 + /* instant NMI */
4226 + switch (si->gpioid) {
4227 + case SB_CC:
4228 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4229 + break;
4230 + case SB_EXTIF:
4231 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4232 + break;
4233 + }
4234 +}
4235 +
4236 +
4237 +/*
4238 + * Configure the pci core for pci client (NIC) action
4239 + * coremask is the bitvec of cores by index to be enabled.
4240 + */
4241 +void
4242 +sb_pci_setup(sb_t *sbh, uint coremask)
4243 +{
4244 + sb_info_t *si;
4245 + sbconfig_t *sb;
4246 + sbpciregs_t *pciregs;
4247 + uint32 sbflag;
4248 + uint32 w;
4249 + uint idx;
4250 +
4251 + si = SB_INFO(sbh);
4252 +
4253 + /* if not pci bus, we're done */
4254 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4255 + return;
4256 +
4257 + ASSERT(PCI(si));
4258 + ASSERT(si->sb.buscoreidx != BADIDX);
4259 +
4260 + /* get current core index */
4261 + idx = si->curidx;
4262 +
4263 + /* we interrupt on this backplane flag number */
4264 + ASSERT(GOODREGS(si->curmap));
4265 + sb = REGS2SB(si->curmap);
4266 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4267 +
4268 + /* switch over to pci core */
4269 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4270 + sb = REGS2SB(pciregs);
4271 +
4272 + /*
4273 + * Enable sb->pci interrupts. Assume
4274 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4275 + */
4276 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4277 + /* pci config write to set this core bit in PCIIntMask */
4278 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4279 + w |= (coremask << PCI_SBIM_SHIFT);
4280 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4281 + } else {
4282 + /* set sbintvec bit for our flag number */
4283 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4284 + }
4285 +
4286 + if (PCI(si)) {
4287 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4288 + if (si->sb.buscorerev >= 11)
4289 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4290 + if (si->sb.buscorerev < 5) {
4291 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4292 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4293 + sb_commit(sbh);
4294 + }
4295 + }
4296 +
4297 + /* switch back to previous core */
4298 + sb_setcoreidx(sbh, idx);
4299 +}
4300 +
4301 +uint32
4302 +sb_base(uint32 admatch)
4303 +{
4304 + uint32 base;
4305 + uint type;
4306 +
4307 + type = admatch & SBAM_TYPE_MASK;
4308 + ASSERT(type < 3);
4309 +
4310 + base = 0;
4311 +
4312 + if (type == 0) {
4313 + base = admatch & SBAM_BASE0_MASK;
4314 + } else if (type == 1) {
4315 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4316 + base = admatch & SBAM_BASE1_MASK;
4317 + } else if (type == 2) {
4318 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4319 + base = admatch & SBAM_BASE2_MASK;
4320 + }
4321 +
4322 + return (base);
4323 +}
4324 +
4325 +uint32
4326 +sb_size(uint32 admatch)
4327 +{
4328 + uint32 size;
4329 + uint type;
4330 +
4331 + type = admatch & SBAM_TYPE_MASK;
4332 + ASSERT(type < 3);
4333 +
4334 + size = 0;
4335 +
4336 + if (type == 0) {
4337 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4338 + } else if (type == 1) {
4339 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4340 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4341 + } else if (type == 2) {
4342 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4343 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4344 + }
4345 +
4346 + return (size);
4347 +}
4348 +
4349 +/* return the core-type instantiation # of the current core */
4350 +uint
4351 +sb_coreunit(sb_t *sbh)
4352 +{
4353 + sb_info_t *si;
4354 + uint idx;
4355 + uint coreid;
4356 + uint coreunit;
4357 + uint i;
4358 +
4359 + si = SB_INFO(sbh);
4360 + coreunit = 0;
4361 +
4362 + idx = si->curidx;
4363 +
4364 + ASSERT(GOODREGS(si->curmap));
4365 + coreid = sb_coreid(sbh);
4366 +
4367 + /* count the cores of our type */
4368 + for (i = 0; i < idx; i++)
4369 + if (si->coreid[i] == coreid)
4370 + coreunit++;
4371 +
4372 + return (coreunit);
4373 +}
4374 +
4375 +static INLINE uint32
4376 +factor6(uint32 x)
4377 +{
4378 + switch (x) {
4379 + case CC_F6_2: return 2;
4380 + case CC_F6_3: return 3;
4381 + case CC_F6_4: return 4;
4382 + case CC_F6_5: return 5;
4383 + case CC_F6_6: return 6;
4384 + case CC_F6_7: return 7;
4385 + default: return 0;
4386 + }
4387 +}
4388 +
4389 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4390 +uint32
4391 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4392 +{
4393 + uint32 n1, n2, clock, m1, m2, m3, mc;
4394 +
4395 + n1 = n & CN_N1_MASK;
4396 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4397 +
4398 + if (pll_type == PLL_TYPE6) {
4399 + if (m & CC_T6_MMASK)
4400 + return CC_T6_M1;
4401 + else
4402 + return CC_T6_M0;
4403 + } else if ((pll_type == PLL_TYPE1) ||
4404 + (pll_type == PLL_TYPE3) ||
4405 + (pll_type == PLL_TYPE4) ||
4406 + (pll_type == PLL_TYPE7)) {
4407 + n1 = factor6(n1);
4408 + n2 += CC_F5_BIAS;
4409 + } else if (pll_type == PLL_TYPE2) {
4410 + n1 += CC_T2_BIAS;
4411 + n2 += CC_T2_BIAS;
4412 + ASSERT((n1 >= 2) && (n1 <= 7));
4413 + ASSERT((n2 >= 5) && (n2 <= 23));
4414 + } else if (pll_type == PLL_TYPE5) {
4415 + return (100000000);
4416 + } else
4417 + ASSERT(0);
4418 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4419 + if ((pll_type == PLL_TYPE3) ||
4420 + (pll_type == PLL_TYPE7)) {
4421 + clock = CC_CLOCK_BASE2 * n1 * n2;
4422 + }
4423 + else
4424 + clock = CC_CLOCK_BASE1 * n1 * n2;
4425 +
4426 + if (clock == 0)
4427 + return 0;
4428 +
4429 + m1 = m & CC_M1_MASK;
4430 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4431 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4432 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4433 +
4434 + if ((pll_type == PLL_TYPE1) ||
4435 + (pll_type == PLL_TYPE3) ||
4436 + (pll_type == PLL_TYPE4) ||
4437 + (pll_type == PLL_TYPE7)) {
4438 + m1 = factor6(m1);
4439 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4440 + m2 += CC_F5_BIAS;
4441 + else
4442 + m2 = factor6(m2);
4443 + m3 = factor6(m3);
4444 +
4445 + switch (mc) {
4446 + case CC_MC_BYPASS: return (clock);
4447 + case CC_MC_M1: return (clock / m1);
4448 + case CC_MC_M1M2: return (clock / (m1 * m2));
4449 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4450 + case CC_MC_M1M3: return (clock / (m1 * m3));
4451 + default: return (0);
4452 + }
4453 + } else {
4454 + ASSERT(pll_type == PLL_TYPE2);
4455 +
4456 + m1 += CC_T2_BIAS;
4457 + m2 += CC_T2M2_BIAS;
4458 + m3 += CC_T2_BIAS;
4459 + ASSERT((m1 >= 2) && (m1 <= 7));
4460 + ASSERT((m2 >= 3) && (m2 <= 10));
4461 + ASSERT((m3 >= 2) && (m3 <= 7));
4462 +
4463 + if ((mc & CC_T2MC_M1BYP) == 0)
4464 + clock /= m1;
4465 + if ((mc & CC_T2MC_M2BYP) == 0)
4466 + clock /= m2;
4467 + if ((mc & CC_T2MC_M3BYP) == 0)
4468 + clock /= m3;
4469 +
4470 + return(clock);
4471 + }
4472 +}
4473 +
4474 +/* returns the current speed the SB is running at */
4475 +uint32
4476 +sb_clock(sb_t *sbh)
4477 +{
4478 + sb_info_t *si;
4479 + extifregs_t *eir;
4480 + chipcregs_t *cc;
4481 + uint32 n, m;
4482 + uint idx;
4483 + uint32 pll_type, rate;
4484 + uint intr_val = 0;
4485 +
4486 + si = SB_INFO(sbh);
4487 + idx = si->curidx;
4488 + pll_type = PLL_TYPE1;
4489 +
4490 + INTR_OFF(si, intr_val);
4491 +
4492 + /* switch to extif or chipc core */
4493 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4494 + n = R_REG(&eir->clockcontrol_n);
4495 + m = R_REG(&eir->clockcontrol_sb);
4496 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4497 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4498 + n = R_REG(&cc->clockcontrol_n);
4499 + if (pll_type == PLL_TYPE6)
4500 + m = R_REG(&cc->clockcontrol_mips);
4501 + else if (pll_type == PLL_TYPE3)
4502 + {
4503 + // Added by Chen-I for 5365
4504 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4505 + m = R_REG(&cc->clockcontrol_sb);
4506 + else
4507 + m = R_REG(&cc->clockcontrol_m2);
4508 + }
4509 + else
4510 + m = R_REG(&cc->clockcontrol_sb);
4511 + } else {
4512 + INTR_RESTORE(si, intr_val);
4513 + return 0;
4514 + }
4515 +
4516 + // Added by Chen-I for 5365
4517 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4518 + {
4519 + rate = 100000000;
4520 + }
4521 + else
4522 + {
4523 + /* calculate rate */
4524 + rate = sb_clock_rate(pll_type, n, m);
4525 + if (pll_type == PLL_TYPE3)
4526 + rate = rate / 2;
4527 + }
4528 +
4529 + /* switch back to previous core */
4530 + sb_setcoreidx(sbh, idx);
4531 +
4532 + INTR_RESTORE(si, intr_val);
4533 +
4534 + return rate;
4535 +}
4536 +
4537 +/* change logical "focus" to the gpio core for optimized access */
4538 +void*
4539 +sb_gpiosetcore(sb_t *sbh)
4540 +{
4541 + sb_info_t *si;
4542 +
4543 + si = SB_INFO(sbh);
4544 +
4545 + return (sb_setcoreidx(sbh, si->gpioidx));
4546 +}
4547 +
4548 +/* mask&set gpiocontrol bits */
4549 +uint32
4550 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4551 +{
4552 + sb_info_t *si;
4553 + uint regoff;
4554 +
4555 + si = SB_INFO(sbh);
4556 + regoff = 0;
4557 +
4558 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4559 +
4560 + /* gpios could be shared on router platforms */
4561 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4562 + mask = priority ? (sb_gpioreservation & mask) :
4563 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4564 + val &= mask;
4565 + }
4566 +
4567 + switch (si->gpioid) {
4568 + case SB_CC:
4569 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4570 + break;
4571 +
4572 + case SB_PCI:
4573 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4574 + break;
4575 +
4576 + case SB_EXTIF:
4577 + return (0);
4578 + }
4579 +
4580 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4581 +}
4582 +
4583 +/* mask&set gpio output enable bits */
4584 +uint32
4585 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4586 +{
4587 + sb_info_t *si;
4588 + uint regoff;
4589 +
4590 + si = SB_INFO(sbh);
4591 + regoff = 0;
4592 +
4593 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4594 +
4595 + /* gpios could be shared on router platforms */
4596 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4597 + mask = priority ? (sb_gpioreservation & mask) :
4598 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4599 + val &= mask;
4600 + }
4601 +
4602 + switch (si->gpioid) {
4603 + case SB_CC:
4604 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4605 + break;
4606 +
4607 + case SB_PCI:
4608 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4609 + break;
4610 +
4611 + case SB_EXTIF:
4612 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4613 + break;
4614 + }
4615 +
4616 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4617 +}
4618 +
4619 +/* mask&set gpio output bits */
4620 +uint32
4621 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4622 +{
4623 + sb_info_t *si;
4624 + uint regoff;
4625 +
4626 + si = SB_INFO(sbh);
4627 + regoff = 0;
4628 +
4629 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4630 +
4631 + /* gpios could be shared on router platforms */
4632 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4633 + mask = priority ? (sb_gpioreservation & mask) :
4634 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4635 + val &= mask;
4636 + }
4637 +
4638 + switch (si->gpioid) {
4639 + case SB_CC:
4640 + regoff = OFFSETOF(chipcregs_t, gpioout);
4641 + break;
4642 +
4643 + case SB_PCI:
4644 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4645 + break;
4646 +
4647 + case SB_EXTIF:
4648 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4649 + break;
4650 + }
4651 +
4652 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4653 +}
4654 +
4655 +/* reserve one gpio */
4656 +uint32
4657 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4658 +{
4659 + sb_info_t *si;
4660 +
4661 + si = SB_INFO(sbh);
4662 +
4663 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4664 +
4665 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4666 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4667 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4668 + return -1;
4669 + }
4670 + /* make sure only one bit is set */
4671 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4672 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4673 + return -1;
4674 + }
4675 +
4676 + /* already reserved */
4677 + if (sb_gpioreservation & gpio_bitmask)
4678 + return -1;
4679 + /* set reservation */
4680 + sb_gpioreservation |= gpio_bitmask;
4681 +
4682 + return sb_gpioreservation;
4683 +}
4684 +
4685 +/* release one gpio */
4686 +/*
4687 + * releasing the gpio doesn't change the current value on the GPIO last write value
4688 + * persists till some one overwrites it
4689 +*/
4690 +
4691 +uint32
4692 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4693 +{
4694 + sb_info_t *si;
4695 +
4696 + si = SB_INFO(sbh);
4697 +
4698 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4699 +
4700 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4701 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4702 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4703 + return -1;
4704 + }
4705 + /* make sure only one bit is set */
4706 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4707 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4708 + return -1;
4709 + }
4710 +
4711 + /* already released */
4712 + if (!(sb_gpioreservation & gpio_bitmask))
4713 + return -1;
4714 +
4715 + /* clear reservation */
4716 + sb_gpioreservation &= ~gpio_bitmask;
4717 +
4718 + return sb_gpioreservation;
4719 +}
4720 +
4721 +/* return the current gpioin register value */
4722 +uint32
4723 +sb_gpioin(sb_t *sbh)
4724 +{
4725 + sb_info_t *si;
4726 + uint regoff;
4727 +
4728 + si = SB_INFO(sbh);
4729 + regoff = 0;
4730 +
4731 + switch (si->gpioid) {
4732 + case SB_CC:
4733 + regoff = OFFSETOF(chipcregs_t, gpioin);
4734 + break;
4735 +
4736 + case SB_PCI:
4737 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4738 + break;
4739 +
4740 + case SB_EXTIF:
4741 + regoff = OFFSETOF(extifregs_t, gpioin);
4742 + break;
4743 + }
4744 +
4745 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4746 +}
4747 +
4748 +/* mask&set gpio interrupt polarity bits */
4749 +uint32
4750 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4751 +{
4752 + sb_info_t *si;
4753 + uint regoff;
4754 +
4755 + si = SB_INFO(sbh);
4756 + regoff = 0;
4757 +
4758 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4759 +
4760 + /* gpios could be shared on router platforms */
4761 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4762 + mask = priority ? (sb_gpioreservation & mask) :
4763 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4764 + val &= mask;
4765 + }
4766 +
4767 + switch (si->gpioid) {
4768 + case SB_CC:
4769 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4770 + break;
4771 +
4772 + case SB_PCI:
4773 + /* pci gpio implementation does not support interrupt polarity */
4774 + ASSERT(0);
4775 + break;
4776 +
4777 + case SB_EXTIF:
4778 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4779 + break;
4780 + }
4781 +
4782 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4783 +}
4784 +
4785 +/* mask&set gpio interrupt mask bits */
4786 +uint32
4787 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4788 +{
4789 + sb_info_t *si;
4790 + uint regoff;
4791 +
4792 + si = SB_INFO(sbh);
4793 + regoff = 0;
4794 +
4795 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4796 +
4797 + /* gpios could be shared on router platforms */
4798 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4799 + mask = priority ? (sb_gpioreservation & mask) :
4800 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4801 + val &= mask;
4802 + }
4803 +
4804 + switch (si->gpioid) {
4805 + case SB_CC:
4806 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4807 + break;
4808 +
4809 + case SB_PCI:
4810 + /* pci gpio implementation does not support interrupt mask */
4811 + ASSERT(0);
4812 + break;
4813 +
4814 + case SB_EXTIF:
4815 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4816 + break;
4817 + }
4818 +
4819 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4820 +}
4821 +
4822 +/* assign the gpio to an led */
4823 +uint32
4824 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4825 +{
4826 + sb_info_t *si;
4827 +
4828 + si = SB_INFO(sbh);
4829 + if (si->sb.ccrev < 16)
4830 + return -1;
4831 +
4832 + /* gpio led powersave reg */
4833 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4834 +}
4835 +
4836 +/* mask&set gpio timer val */
4837 +uint32
4838 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4839 +{
4840 + sb_info_t *si;
4841 + si = SB_INFO(sbh);
4842 +
4843 + if (si->sb.ccrev < 16)
4844 + return -1;
4845 +
4846 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4847 +}
4848 +
4849 +
4850 +/* return the slow clock source - LPO, XTAL, or PCI */
4851 +static uint
4852 +sb_slowclk_src(sb_info_t *si)
4853 +{
4854 + chipcregs_t *cc;
4855 +
4856 +
4857 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4858 +
4859 + if (si->sb.ccrev < 6) {
4860 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4861 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4862 + return (SCC_SS_PCI);
4863 + else
4864 + return (SCC_SS_XTAL);
4865 + } else if (si->sb.ccrev < 10) {
4866 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4867 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4868 + } else /* Insta-clock */
4869 + return (SCC_SS_XTAL);
4870 +}
4871 +
4872 +/* return the ILP (slowclock) min or max frequency */
4873 +static uint
4874 +sb_slowclk_freq(sb_info_t *si, bool max)
4875 +{
4876 + chipcregs_t *cc;
4877 + uint32 slowclk;
4878 + uint div;
4879 +
4880 +
4881 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4882 +
4883 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4884 +
4885 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4886 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4887 +
4888 + slowclk = sb_slowclk_src(si);
4889 + if (si->sb.ccrev < 6) {
4890 + if (slowclk == SCC_SS_PCI)
4891 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4892 + else
4893 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4894 + } else if (si->sb.ccrev < 10) {
4895 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4896 + if (slowclk == SCC_SS_LPO)
4897 + return (max? LPOMAXFREQ : LPOMINFREQ);
4898 + else if (slowclk == SCC_SS_XTAL)
4899 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4900 + else if (slowclk == SCC_SS_PCI)
4901 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4902 + else
4903 + ASSERT(0);
4904 + } else {
4905 + /* Chipc rev 10 is InstaClock */
4906 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4907 + div = 4 * (div + 1);
4908 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4909 + }
4910 + return (0);
4911 +}
4912 +
4913 +static void
4914 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4915 +{
4916 + chipcregs_t * cc;
4917 + uint slowmaxfreq, pll_delay, slowclk;
4918 + uint pll_on_delay, fref_sel_delay;
4919 +
4920 + pll_delay = PLL_DELAY;
4921 +
4922 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4923 + * since the xtal will also be powered down by dynamic clk control logic.
4924 + */
4925 + slowclk = sb_slowclk_src(si);
4926 + if (slowclk != SCC_SS_XTAL)
4927 + pll_delay += XTAL_ON_DELAY;
4928 +
4929 + /* Starting with 4318 it is ILP that is used for the delays */
4930 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4931 +
4932 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4933 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4934 +
4935 + cc = (chipcregs_t *)chipcregs;
4936 + W_REG(&cc->pll_on_delay, pll_on_delay);
4937 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4938 +}
4939 +
4940 +int
4941 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4942 +{
4943 + sb_info_t *si;
4944 + uint origidx;
4945 + chipcregs_t *cc;
4946 + uint intr_val = 0;
4947 + uint err = 0;
4948 +
4949 + si = SB_INFO(sbh);
4950 +
4951 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4952 + if (si->sb.ccrev < 6)
4953 + return 1;
4954 +
4955 + /* chipcommon cores rev10 are a whole new ball game */
4956 + if (si->sb.ccrev >= 10)
4957 + return 1;
4958 +
4959 + if (set && ((*div % 4) || (*div < 4)))
4960 + return 2;
4961 +
4962 + INTR_OFF(si, intr_val);
4963 + origidx = si->curidx;
4964 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4965 + ASSERT(cc != NULL);
4966 +
4967 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
4968 + err = 3;
4969 + goto done;
4970 + }
4971 +
4972 + if (set) {
4973 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
4974 + sb_clkctl_setdelay(sbh, (void *)cc);
4975 + } else
4976 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4977 +
4978 +done:
4979 + sb_setcoreidx(sbh, origidx);
4980 + INTR_RESTORE(si, intr_val);
4981 + return err;
4982 +}
4983 +
4984 +/* initialize power control delay registers */
4985 +void sb_clkctl_init(sb_t *sbh)
4986 +{
4987 + sb_info_t *si;
4988 + uint origidx;
4989 + chipcregs_t *cc;
4990 +
4991 + si = SB_INFO(sbh);
4992 +
4993 + origidx = si->curidx;
4994 +
4995 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
4996 + return;
4997 +
4998 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
4999 + goto done;
5000 +
5001 + /* set all Instaclk chip ILP to 1 MHz */
5002 + if (si->sb.ccrev >= 10)
5003 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5004 +
5005 + sb_clkctl_setdelay(si, (void *)cc);
5006 +
5007 +done:
5008 + sb_setcoreidx(sbh, origidx);
5009 +}
5010 +void sb_pwrctl_init(sb_t *sbh)
5011 +{
5012 +sb_clkctl_init(sbh);
5013 +}
5014 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5015 +uint16
5016 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5017 +{
5018 + sb_info_t *si;
5019 + uint origidx;
5020 + chipcregs_t *cc;
5021 + uint slowminfreq;
5022 + uint16 fpdelay;
5023 + uint intr_val = 0;
5024 +
5025 + si = SB_INFO(sbh);
5026 + fpdelay = 0;
5027 + origidx = si->curidx;
5028 +
5029 + INTR_OFF(si, intr_val);
5030 +
5031 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5032 + goto done;
5033 +
5034 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5035 + goto done;
5036 +
5037 + slowminfreq = sb_slowclk_freq(si, FALSE);
5038 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5039 +
5040 +done:
5041 + sb_setcoreidx(sbh, origidx);
5042 + INTR_RESTORE(si, intr_val);
5043 + return (fpdelay);
5044 +}
5045 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5046 +{
5047 +return sb_clkctl_fast_pwrup_delay(sbh);
5048 +}
5049 +/* turn primary xtal and/or pll off/on */
5050 +int
5051 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5052 +{
5053 + sb_info_t *si;
5054 + uint32 in, out, outen;
5055 +
5056 + si = SB_INFO(sbh);
5057 +
5058 + switch (BUSTYPE(si->sb.bustype)) {
5059 + case PCI_BUS:
5060 +
5061 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5062 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5063 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5064 +
5065 + /*
5066 + * Avoid glitching the clock if GPRS is already using it.
5067 + * We can't actually read the state of the PLLPD so we infer it
5068 + * by the value of XTAL_PU which *is* readable via gpioin.
5069 + */
5070 + if (on && (in & PCI_CFG_GPIO_XTAL))
5071 + return (0);
5072 +
5073 + if (what & XTAL)
5074 + outen |= PCI_CFG_GPIO_XTAL;
5075 + if (what & PLL)
5076 + outen |= PCI_CFG_GPIO_PLL;
5077 +
5078 + if (on) {
5079 + /* turn primary xtal on */
5080 + if (what & XTAL) {
5081 + out |= PCI_CFG_GPIO_XTAL;
5082 + if (what & PLL)
5083 + out |= PCI_CFG_GPIO_PLL;
5084 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5085 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5086 + OSL_DELAY(XTAL_ON_DELAY);
5087 + }
5088 +
5089 + /* turn pll on */
5090 + if (what & PLL) {
5091 + out &= ~PCI_CFG_GPIO_PLL;
5092 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5093 + OSL_DELAY(2000);
5094 + }
5095 + } else {
5096 + if (what & XTAL)
5097 + out &= ~PCI_CFG_GPIO_XTAL;
5098 + if (what & PLL)
5099 + out |= PCI_CFG_GPIO_PLL;
5100 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5101 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5102 + }
5103 +
5104 + default:
5105 + return (-1);
5106 + }
5107 +
5108 + return (0);
5109 +}
5110 +
5111 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5112 +{
5113 +return sb_clkctl_xtal(sbh,what,on);
5114 +}
5115 +
5116 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5117 +/* returns true if ignore pll off is set and false if it is not */
5118 +bool
5119 +sb_clkctl_clk(sb_t *sbh, uint mode)
5120 +{
5121 + sb_info_t *si;
5122 + uint origidx;
5123 + chipcregs_t *cc;
5124 + uint32 scc;
5125 + bool forcefastclk=FALSE;
5126 + uint intr_val = 0;
5127 +
5128 + si = SB_INFO(sbh);
5129 +
5130 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5131 + if (si->sb.ccrev < 6)
5132 + return (FALSE);
5133 +
5134 + /* chipcommon cores rev10 are a whole new ball game */
5135 + if (si->sb.ccrev >= 10)
5136 + return (FALSE);
5137 +
5138 + INTR_OFF(si, intr_val);
5139 +
5140 + origidx = si->curidx;
5141 +
5142 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5143 + ASSERT(cc != NULL);
5144 +
5145 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5146 + goto done;
5147 +
5148 + switch (mode) {
5149 + case CLK_FAST: /* force fast (pll) clock */
5150 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5151 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5152 +
5153 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5154 + break;
5155 +
5156 + case CLK_DYNAMIC: /* enable dynamic clock control */
5157 + scc = R_REG(&cc->slow_clk_ctl);
5158 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5159 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5160 + scc |= SCC_XC;
5161 + W_REG(&cc->slow_clk_ctl, scc);
5162 +
5163 + /* for dynamic control, we have to release our xtal_pu "force on" */
5164 + if (scc & SCC_XC)
5165 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5166 + break;
5167 +
5168 + default:
5169 + ASSERT(0);
5170 + }
5171 +
5172 + /* Is the h/w forcing the use of the fast clk */
5173 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5174 +
5175 +done:
5176 + sb_setcoreidx(sbh, origidx);
5177 + INTR_RESTORE(si, intr_val);
5178 + return (forcefastclk);
5179 +}
5180 +
5181 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5182 +{
5183 +return sb_clkctl_clk(sbh, mode);
5184 +}
5185 +/* register driver interrupt disabling and restoring callback functions */
5186 +void
5187 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5188 +{
5189 + sb_info_t *si;
5190 +
5191 + si = SB_INFO(sbh);
5192 + si->intr_arg = intr_arg;
5193 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5194 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5195 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5196 + /* save current core id. when this function called, the current core
5197 + * must be the core which provides driver functions(il, et, wl, etc.)
5198 + */
5199 + si->dev_coreid = si->coreid[si->curidx];
5200 +}
5201 +
5202 +
5203 +void
5204 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5205 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5206 +{
5207 + uint vendor, core, unit;
5208 + uint chip, chippkg;
5209 + char varname[8];
5210 + uint8 class, subclass, progif;
5211 +
5212 + vendor = sb_corevendor(sbh);
5213 + core = sb_coreid(sbh);
5214 + unit = sb_coreunit(sbh);
5215 +
5216 + chip = BCMINIT(sb_chip)(sbh);
5217 + chippkg = BCMINIT(sb_chippkg)(sbh);
5218 +
5219 + progif = 0;
5220 +
5221 + /* Known vendor translations */
5222 + switch (vendor) {
5223 + case SB_VEND_BCM:
5224 + vendor = VENDOR_BROADCOM;
5225 + break;
5226 + }
5227 +
5228 + /* Determine class based on known core codes */
5229 + switch (core) {
5230 + case SB_ILINE20:
5231 + class = PCI_CLASS_NET;
5232 + subclass = PCI_NET_ETHER;
5233 + core = BCM47XX_ILINE_ID;
5234 + break;
5235 + case SB_ENET:
5236 + class = PCI_CLASS_NET;
5237 + subclass = PCI_NET_ETHER;
5238 + core = BCM47XX_ENET_ID;
5239 + break;
5240 + case SB_SDRAM:
5241 + case SB_MEMC:
5242 + class = PCI_CLASS_MEMORY;
5243 + subclass = PCI_MEMORY_RAM;
5244 + break;
5245 + case SB_PCI:
5246 + class = PCI_CLASS_BRIDGE;
5247 + subclass = PCI_BRIDGE_PCI;
5248 + break;
5249 + case SB_MIPS:
5250 + case SB_MIPS33:
5251 + class = PCI_CLASS_CPU;
5252 + subclass = PCI_CPU_MIPS;
5253 + break;
5254 + case SB_CODEC:
5255 + class = PCI_CLASS_COMM;
5256 + subclass = PCI_COMM_MODEM;
5257 + core = BCM47XX_V90_ID;
5258 + break;
5259 + case SB_USB:
5260 + class = PCI_CLASS_SERIAL;
5261 + subclass = PCI_SERIAL_USB;
5262 + progif = 0x10; /* OHCI */
5263 + core = BCM47XX_USB_ID;
5264 + break;
5265 + case SB_USB11H:
5266 + class = PCI_CLASS_SERIAL;
5267 + subclass = PCI_SERIAL_USB;
5268 + progif = 0x10; /* OHCI */
5269 + core = BCM47XX_USBH_ID;
5270 + break;
5271 + case SB_USB11D:
5272 + class = PCI_CLASS_SERIAL;
5273 + subclass = PCI_SERIAL_USB;
5274 + core = BCM47XX_USBD_ID;
5275 + break;
5276 + case SB_IPSEC:
5277 + class = PCI_CLASS_CRYPT;
5278 + subclass = PCI_CRYPT_NETWORK;
5279 + core = BCM47XX_IPSEC_ID;
5280 + break;
5281 + case SB_ROBO:
5282 + class = PCI_CLASS_NET;
5283 + subclass = PCI_NET_OTHER;
5284 + core = BCM47XX_ROBO_ID;
5285 + break;
5286 + case SB_EXTIF:
5287 + case SB_CC:
5288 + class = PCI_CLASS_MEMORY;
5289 + subclass = PCI_MEMORY_FLASH;
5290 + break;
5291 + case SB_D11:
5292 + class = PCI_CLASS_NET;
5293 + subclass = PCI_NET_OTHER;
5294 + /* Let an nvram variable override this */
5295 + sprintf(varname, "wl%did", unit);
5296 + if ((core = getintvar(NULL, varname)) == 0) {
5297 + if (chip == BCM4712_DEVICE_ID) {
5298 + if (chippkg == BCM4712SMALL_PKG_ID)
5299 + core = BCM4306_D11G_ID;
5300 + else
5301 + core = BCM4306_D11DUAL_ID;
5302 + }
5303 + }
5304 + break;
5305 +
5306 + default:
5307 + class = subclass = progif = 0xff;
5308 + break;
5309 + }
5310 +
5311 + *pcivendor = (uint16)vendor;
5312 + *pcidevice = (uint16)core;
5313 + *pciclass = class;
5314 + *pcisubclass = subclass;
5315 + *pciprogif = progif;
5316 +}
5317 +
5318 +/* Fix chip's configuration. The current core may be changed upon return */
5319 +static int
5320 +sb_pci_fixcfg(sb_info_t *si)
5321 +{
5322 + uint origidx, pciidx;
5323 + sbpciregs_t *pciregs;
5324 + uint16 val16, *reg16;
5325 +
5326 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5327 +
5328 + /* Fix PCI(e) SROM shadow area */
5329 + /* save the current index */
5330 + origidx = sb_coreidx(&si->sb);
5331 +
5332 + if (si->sb.buscoretype == SB_PCI) {
5333 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5334 + ASSERT(pciregs);
5335 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5336 + }
5337 + else {
5338 + ASSERT(0);
5339 + return -1;
5340 + }
5341 + pciidx = sb_coreidx(&si->sb);
5342 + val16 = R_REG(reg16);
5343 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5344 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5345 + W_REG(reg16, val16);
5346 + }
5347 +
5348 + /* restore the original index */
5349 + sb_setcoreidx(&si->sb, origidx);
5350 +
5351 + return 0;
5352 +}
5353 +
5354 +EXPORT_SYMBOL(sb_boardtype);
5355 +EXPORT_SYMBOL(sb_boardvendor);
5356 +EXPORT_SYMBOL(sb_gpiocontrol);
5357 +EXPORT_SYMBOL(sb_gpioin);
5358 +EXPORT_SYMBOL(sb_gpiointmask);
5359 +EXPORT_SYMBOL(sb_gpiointpolarity);
5360 +EXPORT_SYMBOL(sb_gpioled);
5361 +EXPORT_SYMBOL(sb_gpioout);
5362 +EXPORT_SYMBOL(sb_gpioouten);
5363 +EXPORT_SYMBOL(sb_gpiorelease);
5364 +EXPORT_SYMBOL(sb_gpioreserve);
5365 +EXPORT_SYMBOL(sb_gpiosetcore);
5366 +EXPORT_SYMBOL(sb_gpiotimerval);
5367 +EXPORT_SYMBOL(sb_watchdog);
5368 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5369 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5370 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2005-12-15 16:59:20.045933750 +0100
5371 @@ -0,0 +1,418 @@
5372 +/*
5373 + * Broadcom SiliconBackplane chipcommon serial flash interface
5374 + *
5375 + * Copyright 2005, Broadcom Corporation
5376 + * All Rights Reserved.
5377 + *
5378 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5379 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5380 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5381 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5382 + *
5383 + * $Id$
5384 + */
5385 +
5386 +#include <osl.h>
5387 +#include <typedefs.h>
5388 +#include <sbconfig.h>
5389 +#include <sbchipc.h>
5390 +#include <mipsinc.h>
5391 +#include <bcmutils.h>
5392 +#include <bcmdevs.h>
5393 +#include <sflash.h>
5394 +
5395 +/* Private global state */
5396 +static struct sflash sflash;
5397 +
5398 +/* Issue a serial flash command */
5399 +static INLINE void
5400 +sflash_cmd(chipcregs_t *cc, uint opcode)
5401 +{
5402 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5403 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5404 +}
5405 +
5406 +/* Initialize serial flash access */
5407 +struct sflash *
5408 +sflash_init(chipcregs_t *cc)
5409 +{
5410 + uint32 id, id2;
5411 +
5412 + bzero(&sflash, sizeof(sflash));
5413 +
5414 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5415 +
5416 + switch (sflash.type) {
5417 + case SFLASH_ST:
5418 + /* Probe for ST chips */
5419 + sflash_cmd(cc, SFLASH_ST_DP);
5420 + sflash_cmd(cc, SFLASH_ST_RES);
5421 + id = R_REG(&cc->flashdata);
5422 + switch (id) {
5423 + case 0x11:
5424 + /* ST M25P20 2 Mbit Serial Flash */
5425 + sflash.blocksize = 64 * 1024;
5426 + sflash.numblocks = 4;
5427 + break;
5428 + case 0x12:
5429 + /* ST M25P40 4 Mbit Serial Flash */
5430 + sflash.blocksize = 64 * 1024;
5431 + sflash.numblocks = 8;
5432 + break;
5433 + case 0x13:
5434 + /* ST M25P80 8 Mbit Serial Flash */
5435 + sflash.blocksize = 64 * 1024;
5436 + sflash.numblocks = 16;
5437 + break;
5438 + case 0x14:
5439 + /* ST M25P16 16 Mbit Serial Flash */
5440 + sflash.blocksize = 64 * 1024;
5441 + sflash.numblocks = 32;
5442 + break;
5443 + case 0x15:
5444 + /* ST M25P32 32 Mbit Serial Flash */
5445 + sflash.blocksize = 64 * 1024;
5446 + sflash.numblocks = 64;
5447 + break;
5448 + case 0xbf:
5449 + W_REG(&cc->flashaddress, 1);
5450 + sflash_cmd(cc, SFLASH_ST_RES);
5451 + id2 = R_REG(&cc->flashdata);
5452 + if (id2 == 0x44) {
5453 + /* SST M25VF80 4 Mbit Serial Flash */
5454 + sflash.blocksize = 64 * 1024;
5455 + sflash.numblocks = 8;
5456 + }
5457 + break;
5458 + }
5459 + break;
5460 +
5461 + case SFLASH_AT:
5462 + /* Probe for Atmel chips */
5463 + sflash_cmd(cc, SFLASH_AT_STATUS);
5464 + id = R_REG(&cc->flashdata) & 0x3c;
5465 + switch (id) {
5466 + case 0xc:
5467 + /* Atmel AT45DB011 1Mbit Serial Flash */
5468 + sflash.blocksize = 256;
5469 + sflash.numblocks = 512;
5470 + break;
5471 + case 0x14:
5472 + /* Atmel AT45DB021 2Mbit Serial Flash */
5473 + sflash.blocksize = 256;
5474 + sflash.numblocks = 1024;
5475 + break;
5476 + case 0x1c:
5477 + /* Atmel AT45DB041 4Mbit Serial Flash */
5478 + sflash.blocksize = 256;
5479 + sflash.numblocks = 2048;
5480 + break;
5481 + case 0x24:
5482 + /* Atmel AT45DB081 8Mbit Serial Flash */
5483 + sflash.blocksize = 256;
5484 + sflash.numblocks = 4096;
5485 + break;
5486 + case 0x2c:
5487 + /* Atmel AT45DB161 16Mbit Serial Flash */
5488 + sflash.blocksize = 512;
5489 + sflash.numblocks = 4096;
5490 + break;
5491 + case 0x34:
5492 + /* Atmel AT45DB321 32Mbit Serial Flash */
5493 + sflash.blocksize = 512;
5494 + sflash.numblocks = 8192;
5495 + break;
5496 + case 0x3c:
5497 + /* Atmel AT45DB642 64Mbit Serial Flash */
5498 + sflash.blocksize = 1024;
5499 + sflash.numblocks = 8192;
5500 + break;
5501 + }
5502 + break;
5503 + }
5504 +
5505 + sflash.size = sflash.blocksize * sflash.numblocks;
5506 + return sflash.size ? &sflash : NULL;
5507 +}
5508 +
5509 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5510 +int
5511 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5512 +{
5513 + int cnt;
5514 + uint32 *from, *to;
5515 +
5516 + if (!len)
5517 + return 0;
5518 +
5519 + if ((offset + len) > sflash.size)
5520 + return -22;
5521 +
5522 + if ((len >= 4) && (offset & 3))
5523 + cnt = 4 - (offset & 3);
5524 + else if ((len >= 4) && ((uint32)buf & 3))
5525 + cnt = 4 - ((uint32)buf & 3);
5526 + else
5527 + cnt = len;
5528 +
5529 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5530 + to = (uint32 *)buf;
5531 +
5532 + if (cnt < 4) {
5533 + bcopy(from, to, cnt);
5534 + return cnt;
5535 + }
5536 +
5537 + while (cnt >= 4) {
5538 + *to++ = *from++;
5539 + cnt -= 4;
5540 + }
5541 +
5542 + return (len - cnt);
5543 +}
5544 +
5545 +/* Poll for command completion. Returns zero when complete. */
5546 +int
5547 +sflash_poll(chipcregs_t *cc, uint offset)
5548 +{
5549 + if (offset >= sflash.size)
5550 + return -22;
5551 +
5552 + switch (sflash.type) {
5553 + case SFLASH_ST:
5554 + /* Check for ST Write In Progress bit */
5555 + sflash_cmd(cc, SFLASH_ST_RDSR);
5556 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5557 + case SFLASH_AT:
5558 + /* Check for Atmel Ready bit */
5559 + sflash_cmd(cc, SFLASH_AT_STATUS);
5560 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5561 + }
5562 +
5563 + return 0;
5564 +}
5565 +
5566 +/* Write len bytes starting at offset into buf. Returns number of bytes
5567 + * written. Caller should poll for completion.
5568 + */
5569 +int
5570 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5571 +{
5572 + struct sflash *sfl;
5573 + int ret = 0;
5574 + bool is4712b0;
5575 + uint32 page, byte, mask;
5576 +
5577 + if (!len)
5578 + return 0;
5579 +
5580 + if ((offset + len) > sflash.size)
5581 + return -22;
5582 +
5583 + sfl = &sflash;
5584 + switch (sfl->type) {
5585 + case SFLASH_ST:
5586 + mask = R_REG(&cc->chipid);
5587 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5588 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5589 + /* Enable writes */
5590 + sflash_cmd(cc, SFLASH_ST_WREN);
5591 + if (is4712b0) {
5592 + mask = 1 << 14;
5593 + W_REG(&cc->flashaddress, offset);
5594 + W_REG(&cc->flashdata, *buf++);
5595 + /* Set chip select */
5596 + OR_REG(&cc->gpioout, mask);
5597 + /* Issue a page program with the first byte */
5598 + sflash_cmd(cc, SFLASH_ST_PP);
5599 + ret = 1;
5600 + offset++;
5601 + len--;
5602 + while (len > 0) {
5603 + if ((offset & 255) == 0) {
5604 + /* Page boundary, drop cs and return */
5605 + AND_REG(&cc->gpioout, ~mask);
5606 + if (!sflash_poll(cc, offset)) {
5607 + /* Flash rejected command */
5608 + return -11;
5609 + }
5610 + return ret;
5611 + } else {
5612 + /* Write single byte */
5613 + sflash_cmd(cc, *buf++);
5614 + }
5615 + ret++;
5616 + offset++;
5617 + len--;
5618 + }
5619 + /* All done, drop cs if needed */
5620 + if ((offset & 255) != 1) {
5621 + /* Drop cs */
5622 + AND_REG(&cc->gpioout, ~mask);
5623 + if (!sflash_poll(cc, offset)) {
5624 + /* Flash rejected command */
5625 + return -12;
5626 + }
5627 + }
5628 + } else {
5629 + ret = 1;
5630 + W_REG(&cc->flashaddress, offset);
5631 + W_REG(&cc->flashdata, *buf);
5632 + /* Page program */
5633 + sflash_cmd(cc, SFLASH_ST_PP);
5634 + }
5635 + break;
5636 + case SFLASH_AT:
5637 + mask = sfl->blocksize - 1;
5638 + page = (offset & ~mask) << 1;
5639 + byte = offset & mask;
5640 + /* Read main memory page into buffer 1 */
5641 + if (byte || len < sfl->blocksize) {
5642 + W_REG(&cc->flashaddress, page);
5643 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5644 + /* 250 us for AT45DB321B */
5645 + SPINWAIT(sflash_poll(cc, offset), 1000);
5646 + ASSERT(!sflash_poll(cc, offset));
5647 + }
5648 + /* Write into buffer 1 */
5649 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5650 + W_REG(&cc->flashaddress, byte++);
5651 + W_REG(&cc->flashdata, *buf++);
5652 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5653 + }
5654 + /* Write buffer 1 into main memory page */
5655 + W_REG(&cc->flashaddress, page);
5656 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5657 + break;
5658 + }
5659 +
5660 + return ret;
5661 +}
5662 +
5663 +/* Erase a region. Returns number of bytes scheduled for erasure.
5664 + * Caller should poll for completion.
5665 + */
5666 +int
5667 +sflash_erase(chipcregs_t *cc, uint offset)
5668 +{
5669 + struct sflash *sfl;
5670 +
5671 + if (offset >= sflash.size)
5672 + return -22;
5673 +
5674 + sfl = &sflash;
5675 + switch (sfl->type) {
5676 + case SFLASH_ST:
5677 + sflash_cmd(cc, SFLASH_ST_WREN);
5678 + W_REG(&cc->flashaddress, offset);
5679 + sflash_cmd(cc, SFLASH_ST_SE);
5680 + return sfl->blocksize;
5681 + case SFLASH_AT:
5682 + W_REG(&cc->flashaddress, offset << 1);
5683 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5684 + return sfl->blocksize;
5685 + }
5686 +
5687 + return 0;
5688 +}
5689 +
5690 +/*
5691 + * writes the appropriate range of flash, a NULL buf simply erases
5692 + * the region of flash
5693 + */
5694 +int
5695 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5696 +{
5697 + struct sflash *sfl;
5698 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5699 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5700 + uint blk_offset, blk_len, copied;
5701 + int bytes, ret = 0;
5702 +
5703 + /* Check address range */
5704 + if (len <= 0)
5705 + return 0;
5706 +
5707 + sfl = &sflash;
5708 + if ((offset + len) > sfl->size)
5709 + return -1;
5710 +
5711 + blocksize = sfl->blocksize;
5712 + mask = blocksize - 1;
5713 +
5714 + /* Allocate a block of mem */
5715 + if (!(block = MALLOC(NULL, blocksize)))
5716 + return -1;
5717 +
5718 + while (len) {
5719 + /* Align offset */
5720 + cur_offset = offset & ~mask;
5721 + cur_length = blocksize;
5722 + cur_ptr = block;
5723 +
5724 + remainder = blocksize - (offset & mask);
5725 + if (len < remainder)
5726 + cur_retlen = len;
5727 + else
5728 + cur_retlen = remainder;
5729 +
5730 + /* buf == NULL means erase only */
5731 + if (buf) {
5732 + /* Copy existing data into holding block if necessary */
5733 + if ((offset & mask) || (len < blocksize)) {
5734 + blk_offset = cur_offset;
5735 + blk_len = cur_length;
5736 + blk_ptr = cur_ptr;
5737 +
5738 + /* Copy entire block */
5739 + while(blk_len) {
5740 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5741 + blk_offset += copied;
5742 + blk_len -= copied;
5743 + blk_ptr += copied;
5744 + }
5745 + }
5746 +
5747 + /* Copy input data into holding block */
5748 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5749 + }
5750 +
5751 + /* Erase block */
5752 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5753 + goto done;
5754 + while (sflash_poll(cc, (uint) cur_offset));
5755 +
5756 + /* buf == NULL means erase only */
5757 + if (!buf) {
5758 + offset += cur_retlen;
5759 + len -= cur_retlen;
5760 + continue;
5761 + }
5762 +
5763 + /* Write holding block */
5764 + while (cur_length > 0) {
5765 + if ((bytes = sflash_write(cc,
5766 + (uint) cur_offset,
5767 + (uint) cur_length,
5768 + (uchar *) cur_ptr)) < 0) {
5769 + ret = bytes;
5770 + goto done;
5771 + }
5772 + while (sflash_poll(cc, (uint) cur_offset));
5773 + cur_offset += bytes;
5774 + cur_length -= bytes;
5775 + cur_ptr += bytes;
5776 + }
5777 +
5778 + offset += cur_retlen;
5779 + len -= cur_retlen;
5780 + buf += cur_retlen;
5781 + }
5782 +
5783 + ret = len;
5784 +done:
5785 + if (block)
5786 + MFREE(NULL, block, blocksize);
5787 + return ret;
5788 +}
5789 +
5790 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5791 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5792 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-15 15:25:24.905340500 +0100
5793 @@ -0,0 +1,391 @@
5794 +/*
5795 + * Broadcom device-specific manifest constants.
5796 + *
5797 + * Copyright 2005, Broadcom Corporation
5798 + * All Rights Reserved.
5799 + *
5800 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5801 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5802 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5803 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5804 + * $Id$
5805 + */
5806 +
5807 +#ifndef _BCMDEVS_H
5808 +#define _BCMDEVS_H
5809 +
5810 +
5811 +/* Known PCI vendor Id's */
5812 +#define VENDOR_EPIGRAM 0xfeda
5813 +#define VENDOR_BROADCOM 0x14e4
5814 +#define VENDOR_3COM 0x10b7
5815 +#define VENDOR_NETGEAR 0x1385
5816 +#define VENDOR_DIAMOND 0x1092
5817 +#define VENDOR_DELL 0x1028
5818 +#define VENDOR_HP 0x0e11
5819 +#define VENDOR_APPLE 0x106b
5820 +
5821 +/* PCI Device Id's */
5822 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5823 +#define BCM4211_DEVICE_ID 0x4211
5824 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5825 +#define BCM4231_DEVICE_ID 0x4231
5826 +
5827 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5828 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5829 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5830 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5831 +
5832 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5833 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5834 +
5835 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5836 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5837 +
5838 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5839 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5840 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5841 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5842 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5843 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5844 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5845 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5846 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5847 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5848 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5849 +
5850 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5851 +
5852 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5853 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5854 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5855 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5856 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5857 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5858 +
5859 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5860 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5861 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5862 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5863 +
5864 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5865 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5866 +
5867 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5868 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5869 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5870 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5871 +
5872 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5873 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5874 +#define BCM4306_D11G_ID2 0x4325
5875 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5876 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5877 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5878 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5879 +
5880 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5881 +
5882 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5883 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5884 +
5885 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5886 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5887 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5888 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5889 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5890 +
5891 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5892 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5893 +
5894 +
5895 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5896 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5897 +
5898 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5899 +
5900 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5901 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5902 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5903 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5904 +
5905 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5906 +
5907 +/* Address map */
5908 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5909 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5910 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5911 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5912 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5913 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5914 +
5915 +/* Core register space */
5916 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5917 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5918 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5919 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5920 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5921 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5922 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5923 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5924 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5925 +
5926 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5927 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5928 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5929 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5930 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5931 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5932 +
5933 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5934 +
5935 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5936 +
5937 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5938 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5939 +
5940 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5941 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5942 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5943 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5944 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5945 +
5946 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5947 +
5948 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5949 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5950 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5951 +
5952 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
5953 +
5954 +/* PCMCIA vendor Id's */
5955 +
5956 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
5957 +
5958 +/* SDIO vendor Id's */
5959 +#define VENDOR_BROADCOM_SDIO 0x00BF
5960 +
5961 +
5962 +/* boardflags */
5963 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
5964 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
5965 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
5966 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
5967 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
5968 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
5969 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
5970 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
5971 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
5972 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
5973 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
5974 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
5975 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
5976 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
5977 +
5978 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
5979 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
5980 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
5981 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
5982 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
5983 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
5984 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
5985 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
5986 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
5987 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5988 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5989 +
5990 +/* Bus types */
5991 +#define SB_BUS 0 /* Silicon Backplane */
5992 +#define PCI_BUS 1 /* PCI target */
5993 +#define PCMCIA_BUS 2 /* PCMCIA target */
5994 +#define SDIO_BUS 3 /* SDIO target */
5995 +#define JTAG_BUS 4 /* JTAG */
5996 +
5997 +/* Allows optimization for single-bus support */
5998 +#ifdef BCMBUSTYPE
5999 +#define BUSTYPE(bus) (BCMBUSTYPE)
6000 +#else
6001 +#define BUSTYPE(bus) (bus)
6002 +#endif
6003 +
6004 +/* power control defines */
6005 +#define PLL_DELAY 150 /* us pll on delay */
6006 +#define FREF_DELAY 200 /* us fref change delay */
6007 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6008 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6009 +
6010 +/* Reference Board Types */
6011 +
6012 +#define BU4710_BOARD 0x0400
6013 +#define VSIM4710_BOARD 0x0401
6014 +#define QT4710_BOARD 0x0402
6015 +
6016 +#define BU4610_BOARD 0x0403
6017 +#define VSIM4610_BOARD 0x0404
6018 +
6019 +#define BU4307_BOARD 0x0405
6020 +#define BCM94301CB_BOARD 0x0406
6021 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6022 +#define BCM94301MP_BOARD 0x0407
6023 +#define BCM94307MP_BOARD 0x0408
6024 +#define BCMAP4307_BOARD 0x0409
6025 +
6026 +#define BU4309_BOARD 0x040a
6027 +#define BCM94309CB_BOARD 0x040b
6028 +#define BCM94309MP_BOARD 0x040c
6029 +#define BCM4309AP_BOARD 0x040d
6030 +
6031 +#define BCM94302MP_BOARD 0x040e
6032 +
6033 +#define VSIM4310_BOARD 0x040f
6034 +#define BU4711_BOARD 0x0410
6035 +#define BCM94310U_BOARD 0x0411
6036 +#define BCM94310AP_BOARD 0x0412
6037 +#define BCM94310MP_BOARD 0x0414
6038 +
6039 +#define BU4306_BOARD 0x0416
6040 +#define BCM94306CB_BOARD 0x0417
6041 +#define BCM94306MP_BOARD 0x0418
6042 +
6043 +#define BCM94710D_BOARD 0x041a
6044 +#define BCM94710R1_BOARD 0x041b
6045 +#define BCM94710R4_BOARD 0x041c
6046 +#define BCM94710AP_BOARD 0x041d
6047 +
6048 +
6049 +#define BU2050_BOARD 0x041f
6050 +
6051 +
6052 +#define BCM94309G_BOARD 0x0421
6053 +
6054 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6055 +
6056 +#define BU4704_BOARD 0x0423
6057 +#define BU4702_BOARD 0x0424
6058 +
6059 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6060 +
6061 +#define BU4317_BOARD 0x0426
6062 +
6063 +
6064 +#define BCM94702MN_BOARD 0x0428
6065 +
6066 +/* BCM4702 1U CompactPCI Board */
6067 +#define BCM94702CPCI_BOARD 0x0429
6068 +
6069 +/* BCM4702 with BCM95380 VLAN Router */
6070 +#define BCM95380RR_BOARD 0x042a
6071 +
6072 +/* cb4306 with SiGe PA */
6073 +#define BCM94306CBSG_BOARD 0x042b
6074 +
6075 +/* mp4301 with 2050 radio */
6076 +#define BCM94301MPL_BOARD 0x042c
6077 +
6078 +/* cb4306 with SiGe PA */
6079 +#define PCSG94306_BOARD 0x042d
6080 +
6081 +/* bu4704 with sdram */
6082 +#define BU4704SD_BOARD 0x042e
6083 +
6084 +/* Dual 11a/11g Router */
6085 +#define BCM94704AGR_BOARD 0x042f
6086 +
6087 +/* 11a-only minipci */
6088 +#define BCM94308MP_BOARD 0x0430
6089 +
6090 +
6091 +
6092 +/* BCM94317 boards */
6093 +#define BCM94317CB_BOARD 0x0440
6094 +#define BCM94317MP_BOARD 0x0441
6095 +#define BCM94317PCMCIA_BOARD 0x0442
6096 +#define BCM94317SDIO_BOARD 0x0443
6097 +
6098 +#define BU4712_BOARD 0x0444
6099 +#define BU4712SD_BOARD 0x045d
6100 +#define BU4712L_BOARD 0x045f
6101 +
6102 +/* BCM4712 boards */
6103 +#define BCM94712AP_BOARD 0x0445
6104 +#define BCM94712P_BOARD 0x0446
6105 +
6106 +/* BCM4318 boards */
6107 +#define BU4318_BOARD 0x0447
6108 +#define CB4318_BOARD 0x0448
6109 +#define MPG4318_BOARD 0x0449
6110 +#define MP4318_BOARD 0x044a
6111 +#define SD4318_BOARD 0x044b
6112 +
6113 +/* BCM63XX boards */
6114 +#define BCM96338_BOARD 0x6338
6115 +#define BCM96345_BOARD 0x6345
6116 +#define BCM96348_BOARD 0x6348
6117 +
6118 +/* Another mp4306 with SiGe */
6119 +#define BCM94306P_BOARD 0x044c
6120 +
6121 +/* CF-like 4317 modules */
6122 +#define BCM94317CF_BOARD 0x044d
6123 +
6124 +/* mp4303 */
6125 +#define BCM94303MP_BOARD 0x044e
6126 +
6127 +/* mpsgh4306 */
6128 +#define BCM94306MPSGH_BOARD 0x044f
6129 +
6130 +/* BRCM 4306 w/ Front End Modules */
6131 +#define BCM94306MPM 0x0450
6132 +#define BCM94306MPL 0x0453
6133 +
6134 +/* 4712agr */
6135 +#define BCM94712AGR_BOARD 0x0451
6136 +
6137 +/* The real CF 4317 board */
6138 +#define CFI4317_BOARD 0x0452
6139 +
6140 +/* pcmcia 4303 */
6141 +#define PC4303_BOARD 0x0454
6142 +
6143 +/* 5350K */
6144 +#define BCM95350K_BOARD 0x0455
6145 +
6146 +/* 5350R */
6147 +#define BCM95350R_BOARD 0x0456
6148 +
6149 +/* 4306mplna */
6150 +#define BCM94306MPLNA_BOARD 0x0457
6151 +
6152 +/* 4320 boards */
6153 +#define BU4320_BOARD 0x0458
6154 +#define BU4320S_BOARD 0x0459
6155 +#define BCM94320PH_BOARD 0x045a
6156 +
6157 +/* 4306mph */
6158 +#define BCM94306MPH_BOARD 0x045b
6159 +
6160 +/* 4306pciv */
6161 +#define BCM94306PCIV_BOARD 0x045c
6162 +
6163 +#define BU4712SD_BOARD 0x045d
6164 +
6165 +#define BCM94320PFLSH_BOARD 0x045e
6166 +
6167 +#define BU4712L_BOARD 0x045f
6168 +#define BCM94712LGR_BOARD 0x0460
6169 +#define BCM94320R_BOARD 0x0461
6170 +
6171 +#define BU5352_BOARD 0x0462
6172 +
6173 +#define BCM94318MPGH_BOARD 0x0463
6174 +
6175 +
6176 +#define BCM95352GR_BOARD 0x0467
6177 +
6178 +/* bcm95351agr */
6179 +#define BCM95351AGR_BOARD 0x0470
6180 +
6181 +/* # of GPIO pins */
6182 +#define GPIO_NUMPINS 16
6183 +
6184 +#endif /* _BCMDEVS_H */
6185 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6186 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6187 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-12-15 15:25:47.146730500 +0100
6188 @@ -0,0 +1,152 @@
6189 +/*
6190 + * local version of endian.h - byte order defines
6191 + *
6192 + * Copyright 2005, Broadcom Corporation
6193 + * All Rights Reserved.
6194 + *
6195 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6196 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6197 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6198 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6199 + *
6200 + * $Id$
6201 +*/
6202 +
6203 +#ifndef _BCMENDIAN_H_
6204 +#define _BCMENDIAN_H_
6205 +
6206 +#include <typedefs.h>
6207 +
6208 +/* Byte swap a 16 bit value */
6209 +#define BCMSWAP16(val) \
6210 + ((uint16)( \
6211 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6212 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6213 +
6214 +/* Byte swap a 32 bit value */
6215 +#define BCMSWAP32(val) \
6216 + ((uint32)( \
6217 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6218 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6219 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6220 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6221 +
6222 +/* 2 Byte swap a 32 bit value */
6223 +#define BCMSWAP32BY16(val) \
6224 + ((uint32)( \
6225 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6226 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6227 +
6228 +
6229 +static INLINE uint16
6230 +bcmswap16(uint16 val)
6231 +{
6232 + return BCMSWAP16(val);
6233 +}
6234 +
6235 +static INLINE uint32
6236 +bcmswap32(uint32 val)
6237 +{
6238 + return BCMSWAP32(val);
6239 +}
6240 +
6241 +static INLINE uint32
6242 +bcmswap32by16(uint32 val)
6243 +{
6244 + return BCMSWAP32BY16(val);
6245 +}
6246 +
6247 +/* buf - start of buffer of shorts to swap */
6248 +/* len - byte length of buffer */
6249 +static INLINE void
6250 +bcmswap16_buf(uint16 *buf, uint len)
6251 +{
6252 + len = len/2;
6253 +
6254 + while(len--){
6255 + *buf = bcmswap16(*buf);
6256 + buf++;
6257 + }
6258 +}
6259 +
6260 +#ifndef hton16
6261 +#ifndef IL_BIGENDIAN
6262 +#define HTON16(i) BCMSWAP16(i)
6263 +#define hton16(i) bcmswap16(i)
6264 +#define hton32(i) bcmswap32(i)
6265 +#define ntoh16(i) bcmswap16(i)
6266 +#define ntoh32(i) bcmswap32(i)
6267 +#define ltoh16(i) (i)
6268 +#define ltoh32(i) (i)
6269 +#define htol16(i) (i)
6270 +#define htol32(i) (i)
6271 +#else
6272 +#define HTON16(i) (i)
6273 +#define hton16(i) (i)
6274 +#define hton32(i) (i)
6275 +#define ntoh16(i) (i)
6276 +#define ntoh32(i) (i)
6277 +#define ltoh16(i) bcmswap16(i)
6278 +#define ltoh32(i) bcmswap32(i)
6279 +#define htol16(i) bcmswap16(i)
6280 +#define htol32(i) bcmswap32(i)
6281 +#endif
6282 +#endif
6283 +
6284 +#ifndef IL_BIGENDIAN
6285 +#define ltoh16_buf(buf, i)
6286 +#define htol16_buf(buf, i)
6287 +#else
6288 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6289 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6290 +#endif
6291 +
6292 +/*
6293 +* load 16-bit value from unaligned little endian byte array.
6294 +*/
6295 +static INLINE uint16
6296 +ltoh16_ua(uint8 *bytes)
6297 +{
6298 + return (bytes[1]<<8)+bytes[0];
6299 +}
6300 +
6301 +/*
6302 +* load 32-bit value from unaligned little endian byte array.
6303 +*/
6304 +static INLINE uint32
6305 +ltoh32_ua(uint8 *bytes)
6306 +{
6307 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6308 +}
6309 +
6310 +/*
6311 +* load 16-bit value from unaligned big(network) endian byte array.
6312 +*/
6313 +static INLINE uint16
6314 +ntoh16_ua(uint8 *bytes)
6315 +{
6316 + return (bytes[0]<<8)+bytes[1];
6317 +}
6318 +
6319 +/*
6320 +* load 32-bit value from unaligned big(network) endian byte array.
6321 +*/
6322 +static INLINE uint32
6323 +ntoh32_ua(uint8 *bytes)
6324 +{
6325 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6326 +}
6327 +
6328 +#define ltoh_ua(ptr) ( \
6329 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6330 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6331 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6332 +)
6333 +
6334 +#define ntoh_ua(ptr) ( \
6335 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6336 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6337 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6338 +)
6339 +
6340 +#endif /* _BCMENDIAN_H_ */
6341 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6342 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6343 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-15 16:04:35.850827500 +0100
6344 @@ -0,0 +1,87 @@
6345 +/*
6346 + * NVRAM variable manipulation
6347 + *
6348 + * Copyright 2005, Broadcom Corporation
6349 + * All Rights Reserved.
6350 + *
6351 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6352 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6353 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6354 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6355 + *
6356 + * $Id$
6357 + */
6358 +
6359 +#ifndef _bcmnvram_h_
6360 +#define _bcmnvram_h_
6361 +
6362 +#ifndef _LANGUAGE_ASSEMBLY
6363 +
6364 +#include <typedefs.h>
6365 +
6366 +struct nvram_header {
6367 + uint32 magic;
6368 + uint32 len;
6369 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6370 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6371 + uint32 config_ncdl; /* ncdl values for memc */
6372 +};
6373 +
6374 +struct nvram_tuple {
6375 + char *name;
6376 + char *value;
6377 + struct nvram_tuple *next;
6378 +};
6379 +
6380 +/*
6381 + * Get the value of an NVRAM variable. The pointer returned may be
6382 + * invalid after a set.
6383 + * @param name name of variable to get
6384 + * @return value of variable or NULL if undefined
6385 + */
6386 +extern char * __init nvram_get(const char *name);
6387 +
6388 +/*
6389 + * Get the value of an NVRAM variable.
6390 + * @param name name of variable to get
6391 + * @return value of variable or NUL if undefined
6392 + */
6393 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
6394 +
6395 +/*
6396 + * Match an NVRAM variable.
6397 + * @param name name of variable to match
6398 + * @param match value to compare against value of variable
6399 + * @return TRUE if variable is defined and its value is string equal
6400 + * to match or FALSE otherwise
6401 + */
6402 +static inline int
6403 +nvram_match(char *name, char *match) {
6404 + const char *value = BCMINIT(nvram_get)(name);
6405 + return (value && !strcmp(value, match));
6406 +}
6407 +
6408 +/*
6409 + * Inversely match an NVRAM variable.
6410 + * @param name name of variable to match
6411 + * @param match value to compare against value of variable
6412 + * @return TRUE if variable is defined and its value is not string
6413 + * equal to invmatch or FALSE otherwise
6414 + */
6415 +static inline int
6416 +nvram_invmatch(char *name, char *invmatch) {
6417 + const char *value = BCMINIT(nvram_get)(name);
6418 + return (value && strcmp(value, invmatch));
6419 +}
6420 +
6421 +#endif /* _LANGUAGE_ASSEMBLY */
6422 +
6423 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6424 +#define NVRAM_VERSION 1
6425 +#define NVRAM_HEADER_SIZE 20
6426 +#define NVRAM_SPACE 0x8000
6427 +
6428 +#define NVRAM_MAX_VALUE_LEN 255
6429 +#define NVRAM_MAX_PARAM_LEN 64
6430 +
6431 +#endif /* _bcmnvram_h_ */
6432 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6433 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6434 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-15 15:34:32.919589250 +0100
6435 @@ -0,0 +1,23 @@
6436 +/*
6437 + * Misc useful routines to access NIC local SROM/OTP .
6438 + *
6439 + * Copyright 2005, Broadcom Corporation
6440 + * All Rights Reserved.
6441 + *
6442 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6443 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6444 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6445 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6446 + *
6447 + * $Id$
6448 + */
6449 +
6450 +#ifndef _bcmsrom_h_
6451 +#define _bcmsrom_h_
6452 +
6453 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6454 +
6455 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6456 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6457 +
6458 +#endif /* _bcmsrom_h_ */
6459 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6460 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6461 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-12-15 16:44:25.619117750 +0100
6462 @@ -0,0 +1,308 @@
6463 +/*
6464 + * Misc useful os-independent macros and functions.
6465 + *
6466 + * Copyright 2005, Broadcom Corporation
6467 + * All Rights Reserved.
6468 + *
6469 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6470 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6471 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6472 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6473 + * $Id$
6474 + */
6475 +
6476 +#ifndef _bcmutils_h_
6477 +#define _bcmutils_h_
6478 +
6479 +/*** driver-only section ***/
6480 +#include <osl.h>
6481 +
6482 +#define _BCM_U 0x01 /* upper */
6483 +#define _BCM_L 0x02 /* lower */
6484 +#define _BCM_D 0x04 /* digit */
6485 +#define _BCM_C 0x08 /* cntrl */
6486 +#define _BCM_P 0x10 /* punct */
6487 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6488 +#define _BCM_X 0x40 /* hex digit */
6489 +#define _BCM_SP 0x80 /* hard space (0x20) */
6490 +
6491 +#define GPIO_PIN_NOTDEFINED 0x20
6492 +
6493 +extern unsigned char bcm_ctype[];
6494 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6495 +
6496 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6497 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6498 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6499 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6500 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6501 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6502 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6503 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6504 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6505 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6506 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6507 +
6508 +/*
6509 + * Spin at most 'us' microseconds while 'exp' is true.
6510 + * Caller should explicitly test 'exp' when this completes
6511 + * and take appropriate error action if 'exp' is still true.
6512 + */
6513 +#define SPINWAIT(exp, us) { \
6514 + uint countdown = (us) + 9; \
6515 + while ((exp) && (countdown >= 10)) {\
6516 + OSL_DELAY(10); \
6517 + countdown -= 10; \
6518 + } \
6519 +}
6520 +
6521 +/* generic osl packet queue */
6522 +struct pktq {
6523 + void *head; /* first packet to dequeue */
6524 + void *tail; /* last packet to dequeue */
6525 + uint len; /* number of queued packets */
6526 + uint maxlen; /* maximum number of queued packets */
6527 + bool priority; /* enqueue by packet priority */
6528 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6529 +};
6530 +#define DEFAULT_QLEN 128
6531 +
6532 +#define pktq_len(q) ((q)->len)
6533 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6534 +#define pktq_head(q) ((q)->head)
6535 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6536 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6537 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6538 +
6539 +/* externs */
6540 +/* packet */
6541 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6542 +extern uint pkttotlen(osl_t *osh, void *);
6543 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6544 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6545 +extern void *pktdeq(struct pktq *q);
6546 +extern void *pktdeqtail(struct pktq *q);
6547 +/* string */
6548 +extern uint bcm_atoi(char *s);
6549 +extern uchar bcm_toupper(uchar c);
6550 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6551 +extern char *bcmstrstr(char *haystack, char *needle);
6552 +extern char *bcmstrcat(char *dest, const char *src);
6553 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6554 +/* ethernet address */
6555 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6556 +extern int bcm_ether_atoe(char *p, char *ea);
6557 +/* delay */
6558 +extern void bcm_mdelay(uint ms);
6559 +/* variable access */
6560 +extern char *getvar(char *vars, char *name);
6561 +extern int getintvar(char *vars, char *name);
6562 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6563 +#define bcmlog(fmt, a1, a2)
6564 +#define bcmdumplog(buf, size) *buf = '\0'
6565 +#define bcmdumplogent(buf, idx) -1
6566 +
6567 +/*** driver/apps-shared section ***/
6568 +
6569 +#define BCME_STRLEN 64
6570 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6571 +
6572 +
6573 +/*
6574 + * error codes could be added but the defined ones shouldn't be changed/deleted
6575 + * these error codes are exposed to the user code
6576 + * when ever a new error code is added to this list
6577 + * please update errorstring table with the related error string and
6578 + * update osl files with os specific errorcode map
6579 +*/
6580 +
6581 +#define BCME_ERROR -1 /* Error generic */
6582 +#define BCME_BADARG -2 /* Bad Argument */
6583 +#define BCME_BADOPTION -3 /* Bad option */
6584 +#define BCME_NOTUP -4 /* Not up */
6585 +#define BCME_NOTDOWN -5 /* Not down */
6586 +#define BCME_NOTAP -6 /* Not AP */
6587 +#define BCME_NOTSTA -7 /* Not STA */
6588 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6589 +#define BCME_RADIOOFF -9 /* Radio Off */
6590 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6591 +#define BCME_NOCLK -11 /* No Clock*/
6592 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6593 +#define BCME_BADBAND -13 /* BAD Band */
6594 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6595 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6596 +#define BCME_BUSY -16 /* Busy*/
6597 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6598 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6599 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6600 +#define BCME_BADCHAN -20 /* BAD Channel */
6601 +#define BCME_BADADDR -21 /* BAD Address*/
6602 +#define BCME_NORESOURCE -22 /* No resources*/
6603 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6604 +#define BCME_BADLEN -24 /* Bad Length*/
6605 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6606 +#define BCME_EPERM -26 /* Not Permitted */
6607 +#define BCME_NOMEM -27 /* No Memory */
6608 +#define BCME_ASSOCIATED -28 /* Associated */
6609 +#define BCME_RANGE -29 /* Range Error*/
6610 +#define BCME_NOTFOUND -30 /* Not found */
6611 +#define BCME_LAST BCME_NOTFOUND
6612 +
6613 +#ifndef ABS
6614 +#define ABS(a) (((a)<0)?-(a):(a))
6615 +#endif
6616 +
6617 +#ifndef MIN
6618 +#define MIN(a, b) (((a)<(b))?(a):(b))
6619 +#endif
6620 +
6621 +#ifndef MAX
6622 +#define MAX(a, b) (((a)>(b))?(a):(b))
6623 +#endif
6624 +
6625 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6626 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6627 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6628 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6629 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6630 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6631 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6632 +
6633 +/* bit map related macros */
6634 +#ifndef setbit
6635 +#define NBBY 8 /* 8 bits per byte */
6636 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6637 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6638 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6639 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6640 +#endif
6641 +
6642 +#define NBITS(type) (sizeof(type) * 8)
6643 +#define NBITVAL(bits) (1 << (bits))
6644 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6645 +
6646 +/* crc defines */
6647 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6648 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6649 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6650 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6651 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6652 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6653 +
6654 +/* bcm_format_flags() bit description structure */
6655 +typedef struct bcm_bit_desc {
6656 + uint32 bit;
6657 + char* name;
6658 +} bcm_bit_desc_t;
6659 +
6660 +/* tag_ID/length/value_buffer tuple */
6661 +typedef struct bcm_tlv {
6662 + uint8 id;
6663 + uint8 len;
6664 + uint8 data[1];
6665 +} bcm_tlv_t;
6666 +
6667 +/* Check that bcm_tlv_t fits into the given buflen */
6668 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6669 +
6670 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6671 +#define ETHER_ADDR_STR_LEN 18
6672 +
6673 +/* unaligned load and store macros */
6674 +#ifdef IL_BIGENDIAN
6675 +static INLINE uint32
6676 +load32_ua(uint8 *a)
6677 +{
6678 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6679 +}
6680 +
6681 +static INLINE void
6682 +store32_ua(uint8 *a, uint32 v)
6683 +{
6684 + a[0] = (v >> 24) & 0xff;
6685 + a[1] = (v >> 16) & 0xff;
6686 + a[2] = (v >> 8) & 0xff;
6687 + a[3] = v & 0xff;
6688 +}
6689 +
6690 +static INLINE uint16
6691 +load16_ua(uint8 *a)
6692 +{
6693 + return ((a[0] << 8) | a[1]);
6694 +}
6695 +
6696 +static INLINE void
6697 +store16_ua(uint8 *a, uint16 v)
6698 +{
6699 + a[0] = (v >> 8) & 0xff;
6700 + a[1] = v & 0xff;
6701 +}
6702 +
6703 +#else
6704 +
6705 +static INLINE uint32
6706 +load32_ua(uint8 *a)
6707 +{
6708 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6709 +}
6710 +
6711 +static INLINE void
6712 +store32_ua(uint8 *a, uint32 v)
6713 +{
6714 + a[3] = (v >> 24) & 0xff;
6715 + a[2] = (v >> 16) & 0xff;
6716 + a[1] = (v >> 8) & 0xff;
6717 + a[0] = v & 0xff;
6718 +}
6719 +
6720 +static INLINE uint16
6721 +load16_ua(uint8 *a)
6722 +{
6723 + return ((a[1] << 8) | a[0]);
6724 +}
6725 +
6726 +static INLINE void
6727 +store16_ua(uint8 *a, uint16 v)
6728 +{
6729 + a[1] = (v >> 8) & 0xff;
6730 + a[0] = v & 0xff;
6731 +}
6732 +
6733 +#endif
6734 +
6735 +/* externs */
6736 +/* crc */
6737 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6738 +/* format/print */
6739 +/* IE parsing */
6740 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6741 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6742 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6743 +
6744 +/* bcmerror*/
6745 +extern const char *bcmerrorstr(int bcmerror);
6746 +
6747 +/* multi-bool data type: set of bools, mbool is true if any is set */
6748 +typedef uint32 mbool;
6749 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6750 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6751 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6752 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6753 +
6754 +/* power conversion */
6755 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6756 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6757 +
6758 +/* generic datastruct to help dump routines */
6759 +struct fielddesc {
6760 + char *nameandfmt;
6761 + uint32 offset;
6762 + uint32 len;
6763 +};
6764 +
6765 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6766 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6767 +
6768 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6769 +
6770 +#endif /* _bcmutils_h_ */
6771 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6772 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6773 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-15 15:34:40.268048500 +0100
6774 @@ -0,0 +1,85 @@
6775 +/*
6776 + * bit manipulation utility functions
6777 + *
6778 + * Copyright 2005, Broadcom Corporation
6779 + * All Rights Reserved.
6780 + *
6781 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6782 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6783 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6784 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6785 + * $Id$
6786 + */
6787 +
6788 +#ifndef _BITFUNCS_H
6789 +#define _BITFUNCS_H
6790 +
6791 +#include <typedefs.h>
6792 +
6793 +/* local prototypes */
6794 +static INLINE uint32 find_msbit(uint32 x);
6795 +
6796 +
6797 +/*
6798 + * find_msbit: returns index of most significant set bit in x, with index
6799 + * range defined as 0-31. NOTE: returns zero if input is zero.
6800 + */
6801 +
6802 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6803 +
6804 +/*
6805 + * Implementation for Pentium processors and gcc. Note that this
6806 + * instruction is actually very slow on some processors (e.g., family 5,
6807 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6808 + * implementation instead.
6809 + */
6810 +static INLINE uint32 find_msbit(uint32 x)
6811 +{
6812 + uint msbit;
6813 + __asm__("bsrl %1,%0"
6814 + :"=r" (msbit)
6815 + :"r" (x));
6816 + return msbit;
6817 +}
6818 +
6819 +#else
6820 +
6821 +/*
6822 + * Generic Implementation
6823 + */
6824 +
6825 +#define DB_POW_MASK16 0xffff0000
6826 +#define DB_POW_MASK8 0x0000ff00
6827 +#define DB_POW_MASK4 0x000000f0
6828 +#define DB_POW_MASK2 0x0000000c
6829 +#define DB_POW_MASK1 0x00000002
6830 +
6831 +static INLINE uint32 find_msbit(uint32 x)
6832 +{
6833 + uint32 temp_x = x;
6834 + uint msbit = 0;
6835 + if (temp_x & DB_POW_MASK16) {
6836 + temp_x >>= 16;
6837 + msbit = 16;
6838 + }
6839 + if (temp_x & DB_POW_MASK8) {
6840 + temp_x >>= 8;
6841 + msbit += 8;
6842 + }
6843 + if (temp_x & DB_POW_MASK4) {
6844 + temp_x >>= 4;
6845 + msbit += 4;
6846 + }
6847 + if (temp_x & DB_POW_MASK2) {
6848 + temp_x >>= 2;
6849 + msbit += 2;
6850 + }
6851 + if (temp_x & DB_POW_MASK1) {
6852 + msbit += 1;
6853 + }
6854 + return(msbit);
6855 +}
6856 +
6857 +#endif
6858 +
6859 +#endif /* _BITFUNCS_H */
6860 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6861 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6862 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-12-15 15:34:44.280299250 +0100
6863 @@ -0,0 +1,188 @@
6864 +/*
6865 + * flash.h: Common definitions for flash access.
6866 + *
6867 + * Copyright 2005, Broadcom Corporation
6868 + * All Rights Reserved.
6869 + *
6870 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6871 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6872 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6873 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6874 + *
6875 + * $Id$
6876 + */
6877 +
6878 +/* Types of flashes we know about */
6879 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6880 +
6881 +/* Commands to write/erase the flases */
6882 +typedef struct _flash_cmds{
6883 + flash_type_t type;
6884 + bool need_unlock;
6885 + uint16 pre_erase;
6886 + uint16 erase_block;
6887 + uint16 erase_chip;
6888 + uint16 write_word;
6889 + uint16 write_buf;
6890 + uint16 clear_csr;
6891 + uint16 read_csr;
6892 + uint16 read_id;
6893 + uint16 confirm;
6894 + uint16 read_array;
6895 +} flash_cmds_t;
6896 +
6897 +#define UNLOCK_CMD_WORDS 2
6898 +
6899 +typedef struct _unlock_cmd {
6900 + uint addr[UNLOCK_CMD_WORDS];
6901 + uint16 cmd[UNLOCK_CMD_WORDS];
6902 +} unlock_cmd_t;
6903 +
6904 +/* Flash descriptors */
6905 +typedef struct _flash_desc {
6906 + uint16 mfgid; /* Manufacturer Id */
6907 + uint16 devid; /* Device Id */
6908 + uint size; /* Total size in bytes */
6909 + uint width; /* Device width in bytes */
6910 + flash_type_t type; /* Device type old, S, J */
6911 + uint bsize; /* Block size */
6912 + uint nb; /* Number of blocks */
6913 + uint ff; /* First full block */
6914 + uint lf; /* Last full block */
6915 + uint nsub; /* Number of subblocks */
6916 + uint *subblocks; /* Offsets for subblocks */
6917 + char *desc; /* Description */
6918 +} flash_desc_t;
6919 +
6920 +
6921 +#ifdef DECLARE_FLASHES
6922 +flash_cmds_t sflash_cmd_t =
6923 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6924 +
6925 +flash_cmds_t flash_cmds[] = {
6926 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6927 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6928 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6929 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6930 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6931 + { 0 }
6932 +};
6933 +
6934 +unlock_cmd_t unlock_cmd_amd = {
6935 +#ifdef MIPSEB
6936 +/* addr: */ { 0x0aa8, 0x0556},
6937 +#else
6938 +/* addr: */ { 0x0aaa, 0x0554},
6939 +#endif
6940 +/* data: */ { 0xaa, 0x55}
6941 +};
6942 +
6943 +unlock_cmd_t unlock_cmd_sst = {
6944 +#ifdef MIPSEB
6945 +/* addr: */ { 0xaaa8, 0x5556},
6946 +#else
6947 +/* addr: */ { 0xaaaa, 0x5554},
6948 +#endif
6949 +/* data: */ { 0xaa, 0x55}
6950 +};
6951 +
6952 +#define AMD_CMD 0xaaa
6953 +#define SST_CMD 0xaaaa
6954 +
6955 +/* intel unlock block cmds */
6956 +#define INTEL_UNLOCK1 0x60
6957 +#define INTEL_UNLOCK2 0xD0
6958 +
6959 +/* Just eight blocks of 8KB byte each */
6960 +
6961 +uint blk8x8k[] = { 0x00000000,
6962 + 0x00002000,
6963 + 0x00004000,
6964 + 0x00006000,
6965 + 0x00008000,
6966 + 0x0000a000,
6967 + 0x0000c000,
6968 + 0x0000e000,
6969 + 0x00010000
6970 +};
6971 +
6972 +/* Funky AMD arrangement for 29xx800's */
6973 +uint amd800[] = { 0x00000000, /* 16KB */
6974 + 0x00004000, /* 32KB */
6975 + 0x0000c000, /* 8KB */
6976 + 0x0000e000, /* 8KB */
6977 + 0x00010000, /* 8KB */
6978 + 0x00012000, /* 8KB */
6979 + 0x00014000, /* 32KB */
6980 + 0x0001c000, /* 16KB */
6981 + 0x00020000
6982 +};
6983 +
6984 +/* AMD arrangement for 29xx160's */
6985 +uint amd4112[] = { 0x00000000, /* 32KB */
6986 + 0x00008000, /* 8KB */
6987 + 0x0000a000, /* 8KB */
6988 + 0x0000c000, /* 16KB */
6989 + 0x00010000
6990 +};
6991 +uint amd2114[] = { 0x00000000, /* 16KB */
6992 + 0x00004000, /* 8KB */
6993 + 0x00006000, /* 8KB */
6994 + 0x00008000, /* 32KB */
6995 + 0x00010000
6996 +};
6997 +
6998 +
6999 +flash_desc_t sflash_desc =
7000 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7001 +
7002 +flash_desc_t flashes[] = {
7003 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7004 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7005 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7006 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7007 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7008 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7009 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7010 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7011 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7012 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7013 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7014 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7015 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7016 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7017 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7018 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7019 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7020 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7021 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7022 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7023 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7024 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7025 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7026 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7027 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7028 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7029 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7030 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7031 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7032 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7033 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7034 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7035 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7036 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7037 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7038 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7039 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7040 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7041 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7042 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7043 +};
7044 +
7045 +#else
7046 +
7047 +extern flash_cmds_t flash_cmds[];
7048 +extern unlock_cmd_t unlock_cmd;
7049 +extern flash_desc_t flashes[];
7050 +
7051 +#endif
7052 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7053 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7054 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-12-15 15:34:48.160541750 +0100
7055 @@ -0,0 +1,27 @@
7056 +/*
7057 + * BCM47XX FLASH driver interface
7058 + *
7059 + * Copyright 2005, Broadcom Corporation
7060 + * All Rights Reserved.
7061 + *
7062 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7063 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7064 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7065 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7066 + * $Id$
7067 + */
7068 +
7069 +#ifndef _flashutl_h_
7070 +#define _flashutl_h_
7071 +
7072 +
7073 +#ifndef _LANGUAGE_ASSEMBLY
7074 +
7075 +int sysFlashInit(char *flash_str);
7076 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7077 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7078 +void nvWrite(unsigned short *data, unsigned int len);
7079 +
7080 +#endif /* _LANGUAGE_ASSEMBLY */
7081 +
7082 +#endif /* _flashutl_h_ */
7083 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7084 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7085 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-12-15 15:34:53.396869000 +0100
7086 @@ -0,0 +1,16 @@
7087 +/*
7088 + * Alternate include file for HND sbmips.h since CFE also ships with
7089 + * a sbmips.h.
7090 + *
7091 + * Copyright 2005, Broadcom Corporation
7092 + * All Rights Reserved.
7093 + *
7094 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7095 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7096 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7097 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7098 + *
7099 + * $Id$
7100 + */
7101 +
7102 +#include "sbmips.h"
7103 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7104 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7105 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-12-15 17:23:39.225126750 +0100
7106 @@ -0,0 +1,331 @@
7107 +/*
7108 + * Linux OS Independent Layer
7109 + *
7110 + * Copyright 2005, Broadcom Corporation
7111 + * All Rights Reserved.
7112 + *
7113 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7114 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7115 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7116 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7117 + *
7118 + * $Id$
7119 + */
7120 +
7121 +#ifndef _linux_osl_h_
7122 +#define _linux_osl_h_
7123 +
7124 +#include <typedefs.h>
7125 +
7126 +/* use current 2.4.x calling conventions */
7127 +#include <linuxver.h>
7128 +
7129 +/* assert and panic */
7130 +#ifdef __GNUC__
7131 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7132 +#if GCC_VERSION > 30100
7133 +#define ASSERT(exp) do {} while (0)
7134 +#else
7135 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7136 +#define ASSERT(exp)
7137 +#endif
7138 +#endif
7139 +
7140 +/* microsecond delay */
7141 +#define OSL_DELAY(usec) osl_delay(usec)
7142 +extern void osl_delay(uint usec);
7143 +
7144 +/* PCI configuration space access macros */
7145 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7146 + osl_pci_read_config((osh), (offset), (size))
7147 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7148 + osl_pci_write_config((osh), (offset), (size), (val))
7149 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7150 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7151 +
7152 +/* PCI device bus # and slot # */
7153 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7154 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7155 +extern uint osl_pci_bus(osl_t *osh);
7156 +extern uint osl_pci_slot(osl_t *osh);
7157 +
7158 +/* OSL initialization */
7159 +extern osl_t *osl_attach(void *pdev);
7160 +extern void osl_detach(osl_t *osh);
7161 +
7162 +/* host/bus architecture-specific byte swap */
7163 +#define BUS_SWAP32(v) (v)
7164 +
7165 +/* general purpose memory allocation */
7166 +
7167 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7168 +#define MFREE(osh, addr, size) kfree(addr);
7169 +
7170 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7171 +
7172 +extern void *osl_malloc(osl_t *osh, uint size);
7173 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7174 +extern uint osl_malloced(osl_t *osh);
7175 +extern uint osl_malloc_failed(osl_t *osh);
7176 +
7177 +/* allocate/free shared (dma-able) consistent memory */
7178 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7179 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7180 + osl_dma_alloc_consistent((osh), (size), (pap))
7181 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7182 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7183 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7184 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7185 +
7186 +/* map/unmap direction */
7187 +#define DMA_TX 1
7188 +#define DMA_RX 2
7189 +
7190 +/* register access macros */
7191 +#if defined(BCMJTAG)
7192 +#include <bcmjtag.h>
7193 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7194 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7195 +#endif
7196 +
7197 +/*
7198 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7199 + * Macros expand to calls to functions defined in linux_osl.c .
7200 + */
7201 +#ifndef BINOSL
7202 +
7203 +/* string library, kernel mode */
7204 +#define printf(fmt, args...) printk(fmt, ## args)
7205 +#include <linux/kernel.h>
7206 +#include <linux/string.h>
7207 +
7208 +/* register access macros */
7209 +#if !defined(BCMJTAG)
7210 +#ifndef IL_BIGENDIAN
7211 +#define R_REG(r) ( \
7212 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7213 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7214 + readl((volatile uint32*)(r)) \
7215 +)
7216 +#define W_REG(r, v) do { \
7217 + switch (sizeof(*(r))) { \
7218 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7219 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7220 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7221 + } \
7222 +} while (0)
7223 +#else /* IL_BIGENDIAN */
7224 +#define R_REG(r) ({ \
7225 + __typeof(*(r)) __osl_v; \
7226 + switch (sizeof(*(r))) { \
7227 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7228 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7229 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7230 + } \
7231 + __osl_v; \
7232 +})
7233 +#define W_REG(r, v) do { \
7234 + switch (sizeof(*(r))) { \
7235 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7236 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7237 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7238 + } \
7239 +} while (0)
7240 +#endif
7241 +#endif
7242 +
7243 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7244 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7245 +
7246 +/* bcopy, bcmp, and bzero */
7247 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7248 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7249 +#define bzero(b, len) memset((b), '\0', (len))
7250 +
7251 +/* uncached virtual address */
7252 +#ifdef mips
7253 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7254 +#include <asm/addrspace.h>
7255 +#else
7256 +#define OSL_UNCACHED(va) (va)
7257 +#endif
7258 +
7259 +/* get processor cycle count */
7260 +#if defined(mips)
7261 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7262 +#elif defined(__i386__)
7263 +#define OSL_GETCYCLES(x) rdtscl((x))
7264 +#else
7265 +#define OSL_GETCYCLES(x) ((x) = 0)
7266 +#endif
7267 +
7268 +/* dereference an address that may cause a bus exception */
7269 +#ifdef mips
7270 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7271 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7272 +#else
7273 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7274 +#include <asm/paccess.h>
7275 +#endif
7276 +#else
7277 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7278 +#endif
7279 +
7280 +/* map/unmap physical to virtual I/O */
7281 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7282 +#define REG_UNMAP(va) iounmap((void *)(va))
7283 +
7284 +/* shared (dma-able) memory access macros */
7285 +#define R_SM(r) *(r)
7286 +#define W_SM(r, v) (*(r) = (v))
7287 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7288 +
7289 +/* packet primitives */
7290 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7291 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7292 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7293 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7294 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7295 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7296 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7297 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7298 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7299 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7300 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7301 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7302 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7303 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7304 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7305 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7306 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7307 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7308 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7309 +extern void osl_pktfree(void *skb);
7310 +
7311 +#else /* BINOSL */
7312 +
7313 +/* string library */
7314 +#ifndef LINUX_OSL
7315 +#undef printf
7316 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7317 +#undef sprintf
7318 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7319 +#undef strcmp
7320 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7321 +#undef strncmp
7322 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7323 +#undef strlen
7324 +#define strlen(s) osl_strlen((s))
7325 +#undef strcpy
7326 +#define strcpy(d, s) osl_strcpy((d), (s))
7327 +#undef strncpy
7328 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7329 +#endif
7330 +extern int osl_printf(const char *format, ...);
7331 +extern int osl_sprintf(char *buf, const char *format, ...);
7332 +extern int osl_strcmp(const char *s1, const char *s2);
7333 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7334 +extern int osl_strlen(const char *s);
7335 +extern char* osl_strcpy(char *d, const char *s);
7336 +extern char* osl_strncpy(char *d, const char *s, uint n);
7337 +
7338 +/* register access macros */
7339 +#if !defined(BCMJTAG)
7340 +#define R_REG(r) ( \
7341 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7342 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7343 + osl_readl((volatile uint32*)(r)) \
7344 +)
7345 +#define W_REG(r, v) do { \
7346 + switch (sizeof(*(r))) { \
7347 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7348 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7349 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7350 + } \
7351 +} while (0)
7352 +#endif
7353 +
7354 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7355 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7356 +extern uint8 osl_readb(volatile uint8 *r);
7357 +extern uint16 osl_readw(volatile uint16 *r);
7358 +extern uint32 osl_readl(volatile uint32 *r);
7359 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7360 +extern void osl_writew(uint16 v, volatile uint16 *r);
7361 +extern void osl_writel(uint32 v, volatile uint32 *r);
7362 +
7363 +/* bcopy, bcmp, and bzero */
7364 +extern void bcopy(const void *src, void *dst, int len);
7365 +extern int bcmp(const void *b1, const void *b2, int len);
7366 +extern void bzero(void *b, int len);
7367 +
7368 +/* uncached virtual address */
7369 +#define OSL_UNCACHED(va) osl_uncached((va))
7370 +extern void *osl_uncached(void *va);
7371 +
7372 +/* get processor cycle count */
7373 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7374 +extern uint osl_getcycles(void);
7375 +
7376 +/* dereference an address that may target abort */
7377 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7378 +extern int osl_busprobe(uint32 *val, uint32 addr);
7379 +
7380 +/* map/unmap physical to virtual */
7381 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7382 +#define REG_UNMAP(va) osl_reg_unmap((va))
7383 +extern void *osl_reg_map(uint32 pa, uint size);
7384 +extern void osl_reg_unmap(void *va);
7385 +
7386 +/* shared (dma-able) memory access macros */
7387 +#define R_SM(r) *(r)
7388 +#define W_SM(r, v) (*(r) = (v))
7389 +#define BZERO_SM(r, len) bzero((r), (len))
7390 +
7391 +/* packet primitives */
7392 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7393 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7394 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7395 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7396 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7397 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7398 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7399 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7400 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7401 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7402 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7403 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7404 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7405 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7406 +#define PKTLINK(skb) osl_pktlink((skb))
7407 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7408 +#define PKTPRIO(skb) osl_pktprio((skb))
7409 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7410 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7411 +extern void osl_pktfree(void *skb);
7412 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7413 +extern uint osl_pktlen(osl_t *osh, void *skb);
7414 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7415 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7416 +extern void *osl_pktnext(osl_t *osh, void *skb);
7417 +extern void osl_pktsetnext(void *skb, void *x);
7418 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7419 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7420 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7421 +extern void *osl_pktdup(osl_t *osh, void *skb);
7422 +extern void *osl_pktcookie(void *skb);
7423 +extern void osl_pktsetcookie(void *skb, void *x);
7424 +extern void *osl_pktlink(void *skb);
7425 +extern void osl_pktsetlink(void *skb, void *x);
7426 +extern uint osl_pktprio(void *skb);
7427 +extern void osl_pktsetprio(void *skb, uint x);
7428 +
7429 +#endif /* BINOSL */
7430 +
7431 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7432 +extern int osl_error(int bcmerror);
7433 +
7434 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7435 +#define PKTBUFSZ 2048
7436 +
7437 +#endif /* _linux_osl_h_ */
7438 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7439 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7440 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-12-15 16:02:45.467929000 +0100
7441 @@ -0,0 +1,389 @@
7442 +/*
7443 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7444 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7445 + *
7446 + * Copyright 2005, Broadcom Corporation
7447 + * All Rights Reserved.
7448 + *
7449 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7450 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7451 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7452 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7453 + *
7454 + * $Id$
7455 + */
7456 +
7457 +#ifndef _linuxver_h_
7458 +#define _linuxver_h_
7459 +
7460 +#include <linux/config.h>
7461 +#include <linux/version.h>
7462 +
7463 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7464 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7465 +#ifdef __UNDEF_NO_VERSION__
7466 +#undef __NO_VERSION__
7467 +#else
7468 +#define __NO_VERSION__
7469 +#endif
7470 +#endif
7471 +
7472 +#if defined(MODULE) && defined(MODVERSIONS)
7473 +#include <linux/modversions.h>
7474 +#endif
7475 +
7476 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7477 +#include <linux/moduleparam.h>
7478 +#endif
7479 +
7480 +
7481 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7482 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7483 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7484 +#endif
7485 +
7486 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7487 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7488 +#include <linux/malloc.h>
7489 +#else
7490 +#include <linux/slab.h>
7491 +#endif
7492 +
7493 +#include <linux/types.h>
7494 +#include <linux/init.h>
7495 +#include <linux/mm.h>
7496 +#include <linux/string.h>
7497 +#include <linux/pci.h>
7498 +#include <linux/interrupt.h>
7499 +#include <linux/netdevice.h>
7500 +#include <asm/io.h>
7501 +
7502 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7503 +#include <linux/workqueue.h>
7504 +#else
7505 +#include <linux/tqueue.h>
7506 +#ifndef work_struct
7507 +#define work_struct tq_struct
7508 +#endif
7509 +#ifndef INIT_WORK
7510 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7511 +#endif
7512 +#ifndef schedule_work
7513 +#define schedule_work(_work) schedule_task((_work))
7514 +#endif
7515 +#ifndef flush_scheduled_work
7516 +#define flush_scheduled_work() flush_scheduled_tasks()
7517 +#endif
7518 +#endif
7519 +
7520 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7521 +/* Some distributions have their own 2.6.x compatibility layers */
7522 +#ifndef IRQ_NONE
7523 +typedef void irqreturn_t;
7524 +#define IRQ_NONE
7525 +#define IRQ_HANDLED
7526 +#define IRQ_RETVAL(x)
7527 +#endif
7528 +#else
7529 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7530 +#endif
7531 +
7532 +#ifndef __exit
7533 +#define __exit
7534 +#endif
7535 +#ifndef __devexit
7536 +#define __devexit
7537 +#endif
7538 +#ifndef __devinit
7539 +#define __devinit __init
7540 +#endif
7541 +#ifndef __devinitdata
7542 +#define __devinitdata
7543 +#endif
7544 +#ifndef __devexit_p
7545 +#define __devexit_p(x) x
7546 +#endif
7547 +
7548 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7549 +
7550 +#define pci_get_drvdata(dev) (dev)->sysdata
7551 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7552 +
7553 +/*
7554 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7555 + */
7556 +
7557 +struct pci_device_id {
7558 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7559 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7560 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7561 + unsigned long driver_data; /* Data private to the driver */
7562 +};
7563 +
7564 +struct pci_driver {
7565 + struct list_head node;
7566 + char *name;
7567 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7568 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7569 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7570 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7571 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7572 +};
7573 +
7574 +#define MODULE_DEVICE_TABLE(type, name)
7575 +#define PCI_ANY_ID (~0)
7576 +
7577 +/* compatpci.c */
7578 +#define pci_module_init pci_register_driver
7579 +extern int pci_register_driver(struct pci_driver *drv);
7580 +extern void pci_unregister_driver(struct pci_driver *drv);
7581 +
7582 +#endif /* PCI registration */
7583 +
7584 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7585 +#ifdef MODULE
7586 +#define module_init(x) int init_module(void) { return x(); }
7587 +#define module_exit(x) void cleanup_module(void) { x(); }
7588 +#else
7589 +#define module_init(x) __initcall(x);
7590 +#define module_exit(x) __exitcall(x);
7591 +#endif
7592 +#endif
7593 +
7594 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7595 +#define list_for_each(pos, head) \
7596 + for (pos = (head)->next; pos != (head); pos = pos->next)
7597 +#endif
7598 +
7599 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7600 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7601 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7602 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7603 +#endif
7604 +
7605 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7606 +#define pci_enable_device(dev) do { } while (0)
7607 +#endif
7608 +
7609 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7610 +#define net_device device
7611 +#endif
7612 +
7613 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7614 +
7615 +/*
7616 + * DMA mapping
7617 + *
7618 + * See linux/Documentation/DMA-mapping.txt
7619 + */
7620 +
7621 +#ifndef PCI_DMA_TODEVICE
7622 +#define PCI_DMA_TODEVICE 1
7623 +#define PCI_DMA_FROMDEVICE 2
7624 +#endif
7625 +
7626 +typedef u32 dma_addr_t;
7627 +
7628 +/* Pure 2^n version of get_order */
7629 +static inline int get_order(unsigned long size)
7630 +{
7631 + int order;
7632 +
7633 + size = (size-1) >> (PAGE_SHIFT-1);
7634 + order = -1;
7635 + do {
7636 + size >>= 1;
7637 + order++;
7638 + } while (size);
7639 + return order;
7640 +}
7641 +
7642 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7643 + dma_addr_t *dma_handle)
7644 +{
7645 + void *ret;
7646 + int gfp = GFP_ATOMIC | GFP_DMA;
7647 +
7648 + ret = (void *)__get_free_pages(gfp, get_order(size));
7649 +
7650 + if (ret != NULL) {
7651 + memset(ret, 0, size);
7652 + *dma_handle = virt_to_bus(ret);
7653 + }
7654 + return ret;
7655 +}
7656 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7657 + void *vaddr, dma_addr_t dma_handle)
7658 +{
7659 + free_pages((unsigned long)vaddr, get_order(size));
7660 +}
7661 +#ifdef ILSIM
7662 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7663 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7664 +#else
7665 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7666 +#define pci_unmap_single(cookie, address, size, dir)
7667 +#endif
7668 +
7669 +#endif /* DMA mapping */
7670 +
7671 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7672 +
7673 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7674 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7675 +
7676 +/* pcmcia-cs provides its own netdevice compatibility layer */
7677 +#ifndef _COMPAT_NETDEVICE_H
7678 +
7679 +/*
7680 + * SoftNet
7681 + *
7682 + * For pre-softnet kernels we need to tell the upper layer not to
7683 + * re-enter start_xmit() while we are in there. However softnet
7684 + * guarantees not to enter while we are in there so there is no need
7685 + * to do the netif_stop_queue() dance unless the transmit queue really
7686 + * gets stuck. This should also improve performance according to tests
7687 + * done by Aman Singla.
7688 + */
7689 +
7690 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7691 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7692 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7693 +
7694 +static inline void netif_start_queue(struct net_device *dev)
7695 +{
7696 + dev->tbusy = 0;
7697 + dev->interrupt = 0;
7698 + dev->start = 1;
7699 +}
7700 +
7701 +#define netif_queue_stopped(dev) (dev)->tbusy
7702 +#define netif_running(dev) (dev)->start
7703 +
7704 +#endif /* _COMPAT_NETDEVICE_H */
7705 +
7706 +#define netif_device_attach(dev) netif_start_queue(dev)
7707 +#define netif_device_detach(dev) netif_stop_queue(dev)
7708 +
7709 +/* 2.4.x renamed bottom halves to tasklets */
7710 +#define tasklet_struct tq_struct
7711 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7712 +{
7713 + queue_task(tasklet, &tq_immediate);
7714 + mark_bh(IMMEDIATE_BH);
7715 +}
7716 +
7717 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7718 + void (*func)(unsigned long),
7719 + unsigned long data)
7720 +{
7721 + tasklet->next = NULL;
7722 + tasklet->sync = 0;
7723 + tasklet->routine = (void (*)(void *))func;
7724 + tasklet->data = (void *)data;
7725 +}
7726 +#define tasklet_kill(tasklet) {do{} while(0);}
7727 +
7728 +/* 2.4.x introduced del_timer_sync() */
7729 +#define del_timer_sync(timer) del_timer(timer)
7730 +
7731 +#else
7732 +
7733 +#define netif_down(dev)
7734 +
7735 +#endif /* SoftNet */
7736 +
7737 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7738 +
7739 +/*
7740 + * Emit code to initialise a tq_struct's routine and data pointers
7741 + */
7742 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7743 + do { \
7744 + (_tq)->routine = _routine; \
7745 + (_tq)->data = _data; \
7746 + } while (0)
7747 +
7748 +/*
7749 + * Emit code to initialise all of a tq_struct
7750 + */
7751 +#define INIT_TQUEUE(_tq, _routine, _data) \
7752 + do { \
7753 + INIT_LIST_HEAD(&(_tq)->list); \
7754 + (_tq)->sync = 0; \
7755 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7756 + } while (0)
7757 +
7758 +#endif
7759 +
7760 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7761 +
7762 +/* Power management related routines */
7763 +
7764 +static inline int
7765 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7766 +{
7767 + int i;
7768 + if (buffer) {
7769 + for (i = 0; i < 16; i++)
7770 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7771 + }
7772 + return 0;
7773 +}
7774 +
7775 +static inline int
7776 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7777 +{
7778 + int i;
7779 +
7780 + if (buffer) {
7781 + for (i = 0; i < 16; i++)
7782 + pci_write_config_dword(dev,i * 4, buffer[i]);
7783 + }
7784 + /*
7785 + * otherwise, write the context information we know from bootup.
7786 + * This works around a problem where warm-booting from Windows
7787 + * combined with a D3(hot)->D0 transition causes PCI config
7788 + * header data to be forgotten.
7789 + */
7790 + else {
7791 + for (i = 0; i < 6; i ++)
7792 + pci_write_config_dword(dev,
7793 + PCI_BASE_ADDRESS_0 + (i * 4),
7794 + pci_resource_start(dev, i));
7795 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7796 + }
7797 + return 0;
7798 +}
7799 +
7800 +#endif /* PCI power management */
7801 +
7802 +/* Old cp0 access macros deprecated in 2.4.19 */
7803 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7804 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7805 +#endif
7806 +
7807 +/* Module refcount handled internally in 2.6.x */
7808 +#ifndef SET_MODULE_OWNER
7809 +#define SET_MODULE_OWNER(dev) do {} while (0)
7810 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7811 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7812 +#else
7813 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7814 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7815 +#endif
7816 +
7817 +#ifndef SET_NETDEV_DEV
7818 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7819 +#endif
7820 +
7821 +#ifndef HAVE_FREE_NETDEV
7822 +#define free_netdev(dev) kfree(dev)
7823 +#endif
7824 +
7825 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7826 +/* struct packet_type redefined in 2.6.x */
7827 +#define af_packet_priv data
7828 +#endif
7829 +
7830 +#endif /* _linuxver_h_ */
7831 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7832 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7833 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-12-15 16:47:29.886633750 +0100
7834 @@ -0,0 +1,552 @@
7835 +/*
7836 + * HND Run Time Environment for standalone MIPS programs.
7837 + *
7838 + * Copyright 2005, Broadcom Corporation
7839 + * All Rights Reserved.
7840 + *
7841 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7842 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7843 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7844 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7845 + *
7846 + * $Id$
7847 + */
7848 +
7849 +#ifndef _MISPINC_H
7850 +#define _MISPINC_H
7851 +
7852 +
7853 +/* MIPS defines */
7854 +
7855 +#ifdef _LANGUAGE_ASSEMBLY
7856 +
7857 +/*
7858 + * Symbolic register names for 32 bit ABI
7859 + */
7860 +#define zero $0 /* wired zero */
7861 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7862 +#define v0 $2 /* return value */
7863 +#define v1 $3
7864 +#define a0 $4 /* argument registers */
7865 +#define a1 $5
7866 +#define a2 $6
7867 +#define a3 $7
7868 +#define t0 $8 /* caller saved */
7869 +#define t1 $9
7870 +#define t2 $10
7871 +#define t3 $11
7872 +#define t4 $12
7873 +#define t5 $13
7874 +#define t6 $14
7875 +#define t7 $15
7876 +#define s0 $16 /* callee saved */
7877 +#define s1 $17
7878 +#define s2 $18
7879 +#define s3 $19
7880 +#define s4 $20
7881 +#define s5 $21
7882 +#define s6 $22
7883 +#define s7 $23
7884 +#define t8 $24 /* caller saved */
7885 +#define t9 $25
7886 +#define jp $25 /* PIC jump register */
7887 +#define k0 $26 /* kernel scratch */
7888 +#define k1 $27
7889 +#define gp $28 /* global pointer */
7890 +#define sp $29 /* stack pointer */
7891 +#define fp $30 /* frame pointer */
7892 +#define s8 $30 /* same like fp! */
7893 +#define ra $31 /* return address */
7894 +
7895 +
7896 +/*
7897 + * CP0 Registers
7898 + */
7899 +
7900 +#define C0_INX $0
7901 +#define C0_RAND $1
7902 +#define C0_TLBLO0 $2
7903 +#define C0_TLBLO C0_TLBLO0
7904 +#define C0_TLBLO1 $3
7905 +#define C0_CTEXT $4
7906 +#define C0_PGMASK $5
7907 +#define C0_WIRED $6
7908 +#define C0_BADVADDR $8
7909 +#define C0_COUNT $9
7910 +#define C0_TLBHI $10
7911 +#define C0_COMPARE $11
7912 +#define C0_SR $12
7913 +#define C0_STATUS C0_SR
7914 +#define C0_CAUSE $13
7915 +#define C0_EPC $14
7916 +#define C0_PRID $15
7917 +#define C0_CONFIG $16
7918 +#define C0_LLADDR $17
7919 +#define C0_WATCHLO $18
7920 +#define C0_WATCHHI $19
7921 +#define C0_XCTEXT $20
7922 +#define C0_DIAGNOSTIC $22
7923 +#define C0_BROADCOM C0_DIAGNOSTIC
7924 +#define C0_PERFORMANCE $25
7925 +#define C0_ECC $26
7926 +#define C0_CACHEERR $27
7927 +#define C0_TAGLO $28
7928 +#define C0_TAGHI $29
7929 +#define C0_ERREPC $30
7930 +#define C0_DESAVE $31
7931 +
7932 +/*
7933 + * LEAF - declare leaf routine
7934 + */
7935 +#define LEAF(symbol) \
7936 + .globl symbol; \
7937 + .align 2; \
7938 + .type symbol,@function; \
7939 + .ent symbol,0; \
7940 +symbol: .frame sp,0,ra
7941 +
7942 +/*
7943 + * END - mark end of function
7944 + */
7945 +#define END(function) \
7946 + .end function; \
7947 + .size function,.-function
7948 +
7949 +#define _ULCAST_
7950 +
7951 +#else
7952 +
7953 +/*
7954 + * The following macros are especially useful for __asm__
7955 + * inline assembler.
7956 + */
7957 +#ifndef __STR
7958 +#define __STR(x) #x
7959 +#endif
7960 +#ifndef STR
7961 +#define STR(x) __STR(x)
7962 +#endif
7963 +
7964 +#define _ULCAST_ (unsigned long)
7965 +
7966 +
7967 +/*
7968 + * CP0 Registers
7969 + */
7970 +
7971 +#define C0_INX 0 /* CP0: TLB Index */
7972 +#define C0_RAND 1 /* CP0: TLB Random */
7973 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
7974 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
7975 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
7976 +#define C0_CTEXT 4 /* CP0: Context */
7977 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
7978 +#define C0_WIRED 6 /* CP0: TLB Wired */
7979 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
7980 +#define C0_COUNT 9 /* CP0: Count */
7981 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
7982 +#define C0_COMPARE 11 /* CP0: Compare */
7983 +#define C0_SR 12 /* CP0: Processor Status */
7984 +#define C0_STATUS C0_SR /* CP0: Processor Status */
7985 +#define C0_CAUSE 13 /* CP0: Exception Cause */
7986 +#define C0_EPC 14 /* CP0: Exception PC */
7987 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
7988 +#define C0_CONFIG 16 /* CP0: Config */
7989 +#define C0_LLADDR 17 /* CP0: LLAddr */
7990 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
7991 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
7992 +#define C0_XCTEXT 20 /* CP0: XContext */
7993 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
7994 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
7995 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
7996 +#define C0_ECC 26 /* CP0: ECC */
7997 +#define C0_CACHEERR 27 /* CP0: CacheErr */
7998 +#define C0_TAGLO 28 /* CP0: TagLo */
7999 +#define C0_TAGHI 29 /* CP0: TagHi */
8000 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8001 +#define C0_DESAVE 31 /* CP0: DebugSave */
8002 +
8003 +#endif /* _LANGUAGE_ASSEMBLY */
8004 +
8005 +/*
8006 + * Memory segments (32bit kernel mode addresses)
8007 + */
8008 +#undef KUSEG
8009 +#undef KSEG0
8010 +#undef KSEG1
8011 +#undef KSEG2
8012 +#undef KSEG3
8013 +#define KUSEG 0x00000000
8014 +#define KSEG0 0x80000000
8015 +#define KSEG1 0xa0000000
8016 +#define KSEG2 0xc0000000
8017 +#define KSEG3 0xe0000000
8018 +#define PHYSADDR_MASK 0x1fffffff
8019 +
8020 +/*
8021 + * Map an address to a certain kernel segment
8022 + */
8023 +#undef PHYSADDR
8024 +#undef KSEG0ADDR
8025 +#undef KSEG1ADDR
8026 +#undef KSEG2ADDR
8027 +#undef KSEG3ADDR
8028 +
8029 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8030 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8031 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8032 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8033 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8034 +
8035 +
8036 +#ifndef Index_Invalidate_I
8037 +/*
8038 + * Cache Operations
8039 + */
8040 +#define Index_Invalidate_I 0x00
8041 +#define Index_Writeback_Inv_D 0x01
8042 +#define Index_Invalidate_SI 0x02
8043 +#define Index_Writeback_Inv_SD 0x03
8044 +#define Index_Load_Tag_I 0x04
8045 +#define Index_Load_Tag_D 0x05
8046 +#define Index_Load_Tag_SI 0x06
8047 +#define Index_Load_Tag_SD 0x07
8048 +#define Index_Store_Tag_I 0x08
8049 +#define Index_Store_Tag_D 0x09
8050 +#define Index_Store_Tag_SI 0x0A
8051 +#define Index_Store_Tag_SD 0x0B
8052 +#define Create_Dirty_Excl_D 0x0d
8053 +#define Create_Dirty_Excl_SD 0x0f
8054 +#define Hit_Invalidate_I 0x10
8055 +#define Hit_Invalidate_D 0x11
8056 +#define Hit_Invalidate_SI 0x12
8057 +#define Hit_Invalidate_SD 0x13
8058 +#define Fill_I 0x14
8059 +#define Hit_Writeback_Inv_D 0x15
8060 + /* 0x16 is unused */
8061 +#define Hit_Writeback_Inv_SD 0x17
8062 +#define R5K_Page_Invalidate_S 0x17
8063 +#define Hit_Writeback_I 0x18
8064 +#define Hit_Writeback_D 0x19
8065 + /* 0x1a is unused */
8066 +#define Hit_Writeback_SD 0x1b
8067 + /* 0x1c is unused */
8068 + /* 0x1e is unused */
8069 +#define Hit_Set_Virtual_SI 0x1e
8070 +#define Hit_Set_Virtual_SD 0x1f
8071 +#endif
8072 +
8073 +
8074 +/*
8075 + * R4x00 interrupt enable / cause bits
8076 + */
8077 +#define IE_SW0 (_ULCAST_(1) << 8)
8078 +#define IE_SW1 (_ULCAST_(1) << 9)
8079 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8080 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8081 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8082 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8083 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8084 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8085 +
8086 +#ifndef ST0_UM
8087 +/*
8088 + * Bitfields in the mips32 cp0 status register
8089 + */
8090 +#define ST0_IE 0x00000001
8091 +#define ST0_EXL 0x00000002
8092 +#define ST0_ERL 0x00000004
8093 +#define ST0_UM 0x00000010
8094 +#define ST0_SWINT0 0x00000100
8095 +#define ST0_SWINT1 0x00000200
8096 +#define ST0_HWINT0 0x00000400
8097 +#define ST0_HWINT1 0x00000800
8098 +#define ST0_HWINT2 0x00001000
8099 +#define ST0_HWINT3 0x00002000
8100 +#define ST0_HWINT4 0x00004000
8101 +#define ST0_HWINT5 0x00008000
8102 +#define ST0_IM 0x0000ff00
8103 +#define ST0_NMI 0x00080000
8104 +#define ST0_SR 0x00100000
8105 +#define ST0_TS 0x00200000
8106 +#define ST0_BEV 0x00400000
8107 +#define ST0_RE 0x02000000
8108 +#define ST0_RP 0x08000000
8109 +#define ST0_CU 0xf0000000
8110 +#define ST0_CU0 0x10000000
8111 +#define ST0_CU1 0x20000000
8112 +#define ST0_CU2 0x40000000
8113 +#define ST0_CU3 0x80000000
8114 +#endif
8115 +
8116 +
8117 +/*
8118 + * Bitfields in the mips32 cp0 cause register
8119 + */
8120 +#define C_EXC 0x0000007c
8121 +#define C_EXC_SHIFT 2
8122 +#define C_INT 0x0000ff00
8123 +#define C_INT_SHIFT 8
8124 +#define C_SW0 (_ULCAST_(1) << 8)
8125 +#define C_SW1 (_ULCAST_(1) << 9)
8126 +#define C_IRQ0 (_ULCAST_(1) << 10)
8127 +#define C_IRQ1 (_ULCAST_(1) << 11)
8128 +#define C_IRQ2 (_ULCAST_(1) << 12)
8129 +#define C_IRQ3 (_ULCAST_(1) << 13)
8130 +#define C_IRQ4 (_ULCAST_(1) << 14)
8131 +#define C_IRQ5 (_ULCAST_(1) << 15)
8132 +#define C_WP 0x00400000
8133 +#define C_IV 0x00800000
8134 +#define C_CE 0x30000000
8135 +#define C_CE_SHIFT 28
8136 +#define C_BD 0x80000000
8137 +
8138 +/* Values in C_EXC */
8139 +#define EXC_INT 0
8140 +#define EXC_TLBM 1
8141 +#define EXC_TLBL 2
8142 +#define EXC_TLBS 3
8143 +#define EXC_AEL 4
8144 +#define EXC_AES 5
8145 +#define EXC_IBE 6
8146 +#define EXC_DBE 7
8147 +#define EXC_SYS 8
8148 +#define EXC_BPT 9
8149 +#define EXC_RI 10
8150 +#define EXC_CU 11
8151 +#define EXC_OV 12
8152 +#define EXC_TR 13
8153 +#define EXC_WATCH 23
8154 +#define EXC_MCHK 24
8155 +
8156 +
8157 +/*
8158 + * Bits in the cp0 config register.
8159 + */
8160 +#define CONF_CM_CACHABLE_NO_WA 0
8161 +#define CONF_CM_CACHABLE_WA 1
8162 +#define CONF_CM_UNCACHED 2
8163 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8164 +#define CONF_CM_CACHABLE_CE 4
8165 +#define CONF_CM_CACHABLE_COW 5
8166 +#define CONF_CM_CACHABLE_CUW 6
8167 +#define CONF_CM_CACHABLE_ACCELERATED 7
8168 +#define CONF_CM_CMASK 7
8169 +#define CONF_CU (_ULCAST_(1) << 3)
8170 +#define CONF_DB (_ULCAST_(1) << 4)
8171 +#define CONF_IB (_ULCAST_(1) << 5)
8172 +#define CONF_SE (_ULCAST_(1) << 12)
8173 +#define CONF_SC (_ULCAST_(1) << 17)
8174 +#define CONF_AC (_ULCAST_(1) << 23)
8175 +#define CONF_HALT (_ULCAST_(1) << 25)
8176 +
8177 +
8178 +/*
8179 + * Bits in the cp0 config register select 1.
8180 + */
8181 +#define CONF1_FP 0x00000001 /* FPU present */
8182 +#define CONF1_EP 0x00000002 /* EJTAG present */
8183 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8184 +#define CONF1_WR 0x00000008 /* Watch registers present */
8185 +#define CONF1_PC 0x00000010 /* Performance counters present */
8186 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8187 +#define CONF1_DA_MASK 0x00000380
8188 +#define CONF1_DA_BASE 1
8189 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8190 +#define CONF1_DL_MASK 0x00001c00
8191 +#define CONF1_DL_BASE 2
8192 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8193 +#define CONF1_DS_MASK 0x0000e000
8194 +#define CONF1_DS_BASE 64
8195 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8196 +#define CONF1_IA_MASK 0x00070000
8197 +#define CONF1_IA_BASE 1
8198 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8199 +#define CONF1_IL_MASK 0x00380000
8200 +#define CONF1_IL_BASE 2
8201 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8202 +#define CONF1_IS_MASK 0x01c00000
8203 +#define CONF1_IS_BASE 64
8204 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8205 +#define CONF1_MS_SHIFT 25
8206 +
8207 +/* PRID register */
8208 +#define PRID_COPT_MASK 0xff000000
8209 +#define PRID_COMP_MASK 0x00ff0000
8210 +#define PRID_IMP_MASK 0x0000ff00
8211 +#define PRID_REV_MASK 0x000000ff
8212 +
8213 +#define PRID_COMP_LEGACY 0x000000
8214 +#define PRID_COMP_MIPS 0x010000
8215 +#define PRID_COMP_BROADCOM 0x020000
8216 +#define PRID_COMP_ALCHEMY 0x030000
8217 +#define PRID_COMP_SIBYTE 0x040000
8218 +#define PRID_IMP_BCM4710 0x4000
8219 +#define PRID_IMP_BCM3302 0x9000
8220 +#define PRID_IMP_BCM3303 0x9100
8221 +
8222 +#define PRID_IMP_UNKNOWN 0xff00
8223 +
8224 +#define BCM330X(id) \
8225 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8226 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8227 +
8228 +/* Bits in C0_BROADCOM */
8229 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8230 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8231 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8232 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8233 +
8234 +/* PreFetch Cache aka Read Ahead Cache */
8235 +
8236 +#define PFC_CR0 0xff400000 /* control reg 0 */
8237 +#define PFC_CR1 0xff400004 /* control reg 1 */
8238 +
8239 +/* PFC operations */
8240 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8241 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8242 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8243 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8244 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8245 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8246 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8247 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8248 +#define PFC_BRR 0x40000000 /* Bus error indication */
8249 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8250 +
8251 +/* Handy defaults */
8252 +#define PFC_DISABLED 0
8253 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8254 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8255 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8256 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8257 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8258 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8259 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8260 +
8261 +
8262 +/*
8263 + * These are the UART port assignments, expressed as offsets from the base
8264 + * register. These assignments should hold for any serial port based on
8265 + * a 8250, 16450, or 16550(A).
8266 + */
8267 +
8268 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8269 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8270 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8271 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8272 +#define UART_LCR 3 /* Out: Line Control Register */
8273 +#define UART_MCR 4 /* Out: Modem Control Register */
8274 +#define UART_LSR 5 /* In: Line Status Register */
8275 +#define UART_MSR 6 /* In: Modem Status Register */
8276 +#define UART_SCR 7 /* I/O: Scratch Register */
8277 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8278 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8279 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8280 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8281 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8282 +
8283 +
8284 +#ifndef _LANGUAGE_ASSEMBLY
8285 +
8286 +/*
8287 + * Macros to access the system control coprocessor
8288 + */
8289 +
8290 +#define MFC0(source, sel) \
8291 +({ \
8292 + int __res; \
8293 + __asm__ __volatile__( \
8294 + ".set\tnoreorder\n\t" \
8295 + ".set\tnoat\n\t" \
8296 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8297 + "move\t%0,$1\n\t" \
8298 + ".set\tat\n\t" \
8299 + ".set\treorder" \
8300 + :"=r" (__res) \
8301 + : \
8302 + :"$1"); \
8303 + __res; \
8304 +})
8305 +
8306 +#define MTC0(source, sel, value) \
8307 +do { \
8308 + __asm__ __volatile__( \
8309 + ".set\tnoreorder\n\t" \
8310 + ".set\tnoat\n\t" \
8311 + "move\t$1,%z0\n\t" \
8312 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8313 + ".set\tat\n\t" \
8314 + ".set\treorder" \
8315 + : \
8316 + :"jr" (value) \
8317 + :"$1"); \
8318 +} while (0)
8319 +
8320 +#define get_c0_count() \
8321 +({ \
8322 + int __res; \
8323 + __asm__ __volatile__( \
8324 + ".set\tnoreorder\n\t" \
8325 + ".set\tnoat\n\t" \
8326 + "mfc0\t%0,$9\n\t" \
8327 + ".set\tat\n\t" \
8328 + ".set\treorder" \
8329 + :"=r" (__res)); \
8330 + __res; \
8331 +})
8332 +
8333 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8334 +{
8335 + uint lsz, sets, ways;
8336 +
8337 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8338 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8339 + lsz = CONF1_IL_BASE << lsz;
8340 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8341 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8342 + *size = lsz * sets * ways;
8343 + *lsize = lsz;
8344 +}
8345 +
8346 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8347 +{
8348 + uint lsz, sets, ways;
8349 +
8350 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8351 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8352 + lsz = CONF1_DL_BASE << lsz;
8353 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8354 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8355 + *size = lsz * sets * ways;
8356 + *lsize = lsz;
8357 +}
8358 +
8359 +#define cache_op(base, op) \
8360 + __asm__ __volatile__(" \
8361 + .set noreorder; \
8362 + .set mips3; \
8363 + cache %1, (%0); \
8364 + .set mips0; \
8365 + .set reorder" \
8366 + : \
8367 + : "r" (base), \
8368 + "i" (op));
8369 +
8370 +#define cache_unroll4(base, delta, op) \
8371 + __asm__ __volatile__(" \
8372 + .set noreorder; \
8373 + .set mips3; \
8374 + cache %1,0(%0); \
8375 + cache %1,delta(%0); \
8376 + cache %1,(2 * delta)(%0); \
8377 + cache %1,(3 * delta)(%0); \
8378 + .set mips0; \
8379 + .set reorder" \
8380 + : \
8381 + : "r" (base), \
8382 + "i" (op));
8383 +
8384 +#endif /* !_LANGUAGE_ASSEMBLY */
8385 +
8386 +#endif /* _MISPINC_H */
8387 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8388 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8389 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-12-15 15:35:08.321801750 +0100
8390 @@ -0,0 +1,42 @@
8391 +/*
8392 + * OS Abstraction Layer
8393 + *
8394 + * Copyright 2005, Broadcom Corporation
8395 + * All Rights Reserved.
8396 + *
8397 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8398 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8399 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8400 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8401 + * $Id$
8402 + */
8403 +
8404 +#ifndef _osl_h_
8405 +#define _osl_h_
8406 +
8407 +/* osl handle type forward declaration */
8408 +typedef struct os_handle osl_t;
8409 +
8410 +#if defined(linux)
8411 +#include <linux_osl.h>
8412 +#elif defined(NDIS)
8413 +#include <ndis_osl.h>
8414 +#elif defined(_CFE_)
8415 +#include <cfe_osl.h>
8416 +#elif defined(_HNDRTE_)
8417 +#include <hndrte_osl.h>
8418 +#elif defined(_MINOSL_)
8419 +#include <min_osl.h>
8420 +#elif PMON
8421 +#include <pmon_osl.h>
8422 +#elif defined(MACOSX)
8423 +#include <macosx_osl.h>
8424 +#else
8425 +#error "Unsupported OSL requested"
8426 +#endif
8427 +
8428 +/* handy */
8429 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8430 +#define MAXPRIO 7 /* 0-7 */
8431 +
8432 +#endif /* _osl_h_ */
8433 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8434 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8435 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-12-15 15:36:31.719013750 +0100
8436 @@ -0,0 +1,398 @@
8437 +/*
8438 + * pcicfg.h: PCI configuration constants and structures.
8439 + *
8440 + * Copyright 2005, Broadcom Corporation
8441 + * All Rights Reserved.
8442 + *
8443 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8444 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8445 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8446 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8447 + *
8448 + * $Id$
8449 + */
8450 +
8451 +#ifndef _h_pci_
8452 +#define _h_pci_
8453 +
8454 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8455 +#ifndef PCI_MAX_BUS
8456 +#define PCI_MAX_BUS 0x100
8457 +#endif
8458 +#ifndef PCI_MAX_DEVICES
8459 +#define PCI_MAX_DEVICES 0x20
8460 +#endif
8461 +#ifndef PCI_MAX_FUNCTION
8462 +#define PCI_MAX_FUNCTION 0x8
8463 +#endif
8464 +
8465 +#ifndef PCI_INVALID_VENDORID
8466 +#define PCI_INVALID_VENDORID 0xffff
8467 +#endif
8468 +#ifndef PCI_INVALID_DEVICEID
8469 +#define PCI_INVALID_DEVICEID 0xffff
8470 +#endif
8471 +
8472 +
8473 +/* Convert between bus-slot-function-register and config addresses */
8474 +
8475 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8476 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8477 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8478 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8479 +
8480 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8481 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8482 +#define PCICFG_FUN_MASK 7 /* Function mask */
8483 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8484 +
8485 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8486 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8487 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8488 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8489 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8490 +
8491 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8492 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8493 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8494 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8495 +
8496 +/* The actual config space */
8497 +
8498 +#define PCI_BAR_MAX 6
8499 +
8500 +#define PCI_ROM_BAR 8
8501 +
8502 +#define PCR_RSVDA_MAX 2
8503 +
8504 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8505 +
8506 +#define PCI_CAPPTR_PRESENT 0x0010
8507 +
8508 +typedef struct _pci_config_regs {
8509 + unsigned short vendor;
8510 + unsigned short device;
8511 + unsigned short command;
8512 + unsigned short status;
8513 + unsigned char rev_id;
8514 + unsigned char prog_if;
8515 + unsigned char sub_class;
8516 + unsigned char base_class;
8517 + unsigned char cache_line_size;
8518 + unsigned char latency_timer;
8519 + unsigned char header_type;
8520 + unsigned char bist;
8521 + unsigned long base[PCI_BAR_MAX];
8522 + unsigned long cardbus_cis;
8523 + unsigned short subsys_vendor;
8524 + unsigned short subsys_id;
8525 + unsigned long baserom;
8526 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8527 + unsigned char int_line;
8528 + unsigned char int_pin;
8529 + unsigned char min_gnt;
8530 + unsigned char max_lat;
8531 + unsigned char dev_dep[192];
8532 +} pci_config_regs;
8533 +
8534 +#define SZPCR (sizeof (pci_config_regs))
8535 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8536 +
8537 +/* A structure for the config registers is nice, but in most
8538 + * systems the config space is not memory mapped, so we need
8539 + * filed offsetts. :-(
8540 + */
8541 +#define PCI_CFG_VID 0
8542 +#define PCI_CFG_DID 2
8543 +#define PCI_CFG_CMD 4
8544 +#define PCI_CFG_STAT 6
8545 +#define PCI_CFG_REV 8
8546 +#define PCI_CFG_PROGIF 9
8547 +#define PCI_CFG_SUBCL 0xa
8548 +#define PCI_CFG_BASECL 0xb
8549 +#define PCI_CFG_CLSZ 0xc
8550 +#define PCI_CFG_LATTIM 0xd
8551 +#define PCI_CFG_HDR 0xe
8552 +#define PCI_CFG_BIST 0xf
8553 +#define PCI_CFG_BAR0 0x10
8554 +#define PCI_CFG_BAR1 0x14
8555 +#define PCI_CFG_BAR2 0x18
8556 +#define PCI_CFG_BAR3 0x1c
8557 +#define PCI_CFG_BAR4 0x20
8558 +#define PCI_CFG_BAR5 0x24
8559 +#define PCI_CFG_CIS 0x28
8560 +#define PCI_CFG_SVID 0x2c
8561 +#define PCI_CFG_SSID 0x2e
8562 +#define PCI_CFG_ROMBAR 0x30
8563 +#define PCI_CFG_CAPPTR 0x34
8564 +#define PCI_CFG_INT 0x3c
8565 +#define PCI_CFG_PIN 0x3d
8566 +#define PCI_CFG_MINGNT 0x3e
8567 +#define PCI_CFG_MAXLAT 0x3f
8568 +
8569 +/* Classes and subclasses */
8570 +
8571 +typedef enum {
8572 + PCI_CLASS_OLD = 0,
8573 + PCI_CLASS_DASDI,
8574 + PCI_CLASS_NET,
8575 + PCI_CLASS_DISPLAY,
8576 + PCI_CLASS_MMEDIA,
8577 + PCI_CLASS_MEMORY,
8578 + PCI_CLASS_BRIDGE,
8579 + PCI_CLASS_COMM,
8580 + PCI_CLASS_BASE,
8581 + PCI_CLASS_INPUT,
8582 + PCI_CLASS_DOCK,
8583 + PCI_CLASS_CPU,
8584 + PCI_CLASS_SERIAL,
8585 + PCI_CLASS_INTELLIGENT = 0xe,
8586 + PCI_CLASS_SATELLITE,
8587 + PCI_CLASS_CRYPT,
8588 + PCI_CLASS_DSP,
8589 + PCI_CLASS_MAX
8590 +} pci_classes;
8591 +
8592 +typedef enum {
8593 + PCI_DASDI_SCSI,
8594 + PCI_DASDI_IDE,
8595 + PCI_DASDI_FLOPPY,
8596 + PCI_DASDI_IPI,
8597 + PCI_DASDI_RAID,
8598 + PCI_DASDI_OTHER = 0x80
8599 +} pci_dasdi_subclasses;
8600 +
8601 +typedef enum {
8602 + PCI_NET_ETHER,
8603 + PCI_NET_TOKEN,
8604 + PCI_NET_FDDI,
8605 + PCI_NET_ATM,
8606 + PCI_NET_OTHER = 0x80
8607 +} pci_net_subclasses;
8608 +
8609 +typedef enum {
8610 + PCI_DISPLAY_VGA,
8611 + PCI_DISPLAY_XGA,
8612 + PCI_DISPLAY_3D,
8613 + PCI_DISPLAY_OTHER = 0x80
8614 +} pci_display_subclasses;
8615 +
8616 +typedef enum {
8617 + PCI_MMEDIA_VIDEO,
8618 + PCI_MMEDIA_AUDIO,
8619 + PCI_MMEDIA_PHONE,
8620 + PCI_MEDIA_OTHER = 0x80
8621 +} pci_mmedia_subclasses;
8622 +
8623 +typedef enum {
8624 + PCI_MEMORY_RAM,
8625 + PCI_MEMORY_FLASH,
8626 + PCI_MEMORY_OTHER = 0x80
8627 +} pci_memory_subclasses;
8628 +
8629 +typedef enum {
8630 + PCI_BRIDGE_HOST,
8631 + PCI_BRIDGE_ISA,
8632 + PCI_BRIDGE_EISA,
8633 + PCI_BRIDGE_MC,
8634 + PCI_BRIDGE_PCI,
8635 + PCI_BRIDGE_PCMCIA,
8636 + PCI_BRIDGE_NUBUS,
8637 + PCI_BRIDGE_CARDBUS,
8638 + PCI_BRIDGE_RACEWAY,
8639 + PCI_BRIDGE_OTHER = 0x80
8640 +} pci_bridge_subclasses;
8641 +
8642 +typedef enum {
8643 + PCI_COMM_UART,
8644 + PCI_COMM_PARALLEL,
8645 + PCI_COMM_MULTIUART,
8646 + PCI_COMM_MODEM,
8647 + PCI_COMM_OTHER = 0x80
8648 +} pci_comm_subclasses;
8649 +
8650 +typedef enum {
8651 + PCI_BASE_PIC,
8652 + PCI_BASE_DMA,
8653 + PCI_BASE_TIMER,
8654 + PCI_BASE_RTC,
8655 + PCI_BASE_PCI_HOTPLUG,
8656 + PCI_BASE_OTHER = 0x80
8657 +} pci_base_subclasses;
8658 +
8659 +typedef enum {
8660 + PCI_INPUT_KBD,
8661 + PCI_INPUT_PEN,
8662 + PCI_INPUT_MOUSE,
8663 + PCI_INPUT_SCANNER,
8664 + PCI_INPUT_GAMEPORT,
8665 + PCI_INPUT_OTHER = 0x80
8666 +} pci_input_subclasses;
8667 +
8668 +typedef enum {
8669 + PCI_DOCK_GENERIC,
8670 + PCI_DOCK_OTHER = 0x80
8671 +} pci_dock_subclasses;
8672 +
8673 +typedef enum {
8674 + PCI_CPU_386,
8675 + PCI_CPU_486,
8676 + PCI_CPU_PENTIUM,
8677 + PCI_CPU_ALPHA = 0x10,
8678 + PCI_CPU_POWERPC = 0x20,
8679 + PCI_CPU_MIPS = 0x30,
8680 + PCI_CPU_COPROC = 0x40,
8681 + PCI_CPU_OTHER = 0x80
8682 +} pci_cpu_subclasses;
8683 +
8684 +typedef enum {
8685 + PCI_SERIAL_IEEE1394,
8686 + PCI_SERIAL_ACCESS,
8687 + PCI_SERIAL_SSA,
8688 + PCI_SERIAL_USB,
8689 + PCI_SERIAL_FIBER,
8690 + PCI_SERIAL_SMBUS,
8691 + PCI_SERIAL_OTHER = 0x80
8692 +} pci_serial_subclasses;
8693 +
8694 +typedef enum {
8695 + PCI_INTELLIGENT_I2O,
8696 +} pci_intelligent_subclasses;
8697 +
8698 +typedef enum {
8699 + PCI_SATELLITE_TV,
8700 + PCI_SATELLITE_AUDIO,
8701 + PCI_SATELLITE_VOICE,
8702 + PCI_SATELLITE_DATA,
8703 + PCI_SATELLITE_OTHER = 0x80
8704 +} pci_satellite_subclasses;
8705 +
8706 +typedef enum {
8707 + PCI_CRYPT_NETWORK,
8708 + PCI_CRYPT_ENTERTAINMENT,
8709 + PCI_CRYPT_OTHER = 0x80
8710 +} pci_crypt_subclasses;
8711 +
8712 +typedef enum {
8713 + PCI_DSP_DPIO,
8714 + PCI_DSP_OTHER = 0x80
8715 +} pci_dsp_subclasses;
8716 +
8717 +/* Header types */
8718 +typedef enum {
8719 + PCI_HEADER_NORMAL,
8720 + PCI_HEADER_BRIDGE,
8721 + PCI_HEADER_CARDBUS
8722 +} pci_header_types;
8723 +
8724 +
8725 +/* Overlay for a PCI-to-PCI bridge */
8726 +
8727 +#define PPB_RSVDA_MAX 2
8728 +#define PPB_RSVDD_MAX 8
8729 +
8730 +typedef struct _ppb_config_regs {
8731 + unsigned short vendor;
8732 + unsigned short device;
8733 + unsigned short command;
8734 + unsigned short status;
8735 + unsigned char rev_id;
8736 + unsigned char prog_if;
8737 + unsigned char sub_class;
8738 + unsigned char base_class;
8739 + unsigned char cache_line_size;
8740 + unsigned char latency_timer;
8741 + unsigned char header_type;
8742 + unsigned char bist;
8743 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8744 + unsigned char prim_bus;
8745 + unsigned char sec_bus;
8746 + unsigned char sub_bus;
8747 + unsigned char sec_lat;
8748 + unsigned char io_base;
8749 + unsigned char io_lim;
8750 + unsigned short sec_status;
8751 + unsigned short mem_base;
8752 + unsigned short mem_lim;
8753 + unsigned short pf_mem_base;
8754 + unsigned short pf_mem_lim;
8755 + unsigned long pf_mem_base_hi;
8756 + unsigned long pf_mem_lim_hi;
8757 + unsigned short io_base_hi;
8758 + unsigned short io_lim_hi;
8759 + unsigned short subsys_vendor;
8760 + unsigned short subsys_id;
8761 + unsigned long rsvd_b;
8762 + unsigned char rsvd_c;
8763 + unsigned char int_pin;
8764 + unsigned short bridge_ctrl;
8765 + unsigned char chip_ctrl;
8766 + unsigned char diag_ctrl;
8767 + unsigned short arb_ctrl;
8768 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8769 + unsigned char dev_dep[192];
8770 +} ppb_config_regs;
8771 +
8772 +
8773 +/* PCI CAPABILITY DEFINES */
8774 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8775 +#define PCI_CAP_MSICAP_ID 0x05
8776 +
8777 +/* Data structure to define the Message Signalled Interrupt facility
8778 + * Valid for PCI and PCIE configurations */
8779 +typedef struct _pciconfig_cap_msi {
8780 + unsigned char capID;
8781 + unsigned char nextptr;
8782 + unsigned short msgctrl;
8783 + unsigned int msgaddr;
8784 +} pciconfig_cap_msi;
8785 +
8786 +/* Data structure to define the Power managment facility
8787 + * Valid for PCI and PCIE configurations */
8788 +typedef struct _pciconfig_cap_pwrmgmt {
8789 + unsigned char capID;
8790 + unsigned char nextptr;
8791 + unsigned short pme_cap;
8792 + unsigned short pme_sts_ctrl;
8793 + unsigned char pme_bridge_ext;
8794 + unsigned char data;
8795 +} pciconfig_cap_pwrmgmt;
8796 +
8797 +/* Everything below is BRCM HND proprietary */
8798 +
8799 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8800 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8801 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8802 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8803 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8804 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8805 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8806 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8807 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8808 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8809 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8810 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8811 +
8812 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8813 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8814 +
8815 +/* PCI_INT_STATUS */
8816 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8817 +
8818 +/* PCI_INT_MASK */
8819 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8820 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8821 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8822 +
8823 +/* PCI_SPROM_CONTROL */
8824 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8825 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8826 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8827 +
8828 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8829 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8830 +
8831 +/* PCI_CFG_CMD_STAT */
8832 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8833 +
8834 +#endif
8835 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8836 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8837 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-15 12:57:27.869191250 +0100
8838 @@ -0,0 +1,145 @@
8839 +/*******************************************************************************
8840 + * $Id$
8841 + * Copyright 2001-2003, Broadcom Corporation
8842 + * All Rights Reserved.
8843 + *
8844 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8845 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8846 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8847 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8848 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8849 + ******************************************************************************/
8850 +
8851 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8852 +#define _NET_ETHERNET_H_
8853 +
8854 +#ifndef _TYPEDEFS_H_
8855 +#include "typedefs.h"
8856 +#endif
8857 +
8858 +#if defined(__GNUC__)
8859 +#define PACKED __attribute__((packed))
8860 +#else
8861 +#define PACKED
8862 +#endif
8863 +
8864 +/*
8865 + * The number of bytes in an ethernet (MAC) address.
8866 + */
8867 +#define ETHER_ADDR_LEN 6
8868 +
8869 +/*
8870 + * The number of bytes in the type field.
8871 + */
8872 +#define ETHER_TYPE_LEN 2
8873 +
8874 +/*
8875 + * The number of bytes in the trailing CRC field.
8876 + */
8877 +#define ETHER_CRC_LEN 4
8878 +
8879 +/*
8880 + * The length of the combined header.
8881 + */
8882 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8883 +
8884 +/*
8885 + * The minimum packet length.
8886 + */
8887 +#define ETHER_MIN_LEN 64
8888 +
8889 +/*
8890 + * The minimum packet user data length.
8891 + */
8892 +#define ETHER_MIN_DATA 46
8893 +
8894 +/*
8895 + * The maximum packet length.
8896 + */
8897 +#define ETHER_MAX_LEN 1518
8898 +
8899 +/*
8900 + * The maximum packet user data length.
8901 + */
8902 +#define ETHER_MAX_DATA 1500
8903 +
8904 +/*
8905 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8906 + */
8907 +#define VLAN_TAG 0x8100
8908 +
8909 +/*
8910 + * Located after dest & src address in ether header.
8911 + */
8912 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8913 +
8914 +/*
8915 + * 4 bytes of vlan field info.
8916 + */
8917 +#define VLAN_FIELDS_SIZE 4
8918 +
8919 +/* location of pri bits in 16-bit vlan fields */
8920 +#define VLAN_PRI_SHIFT 13
8921 +
8922 +/* 3 bits of priority */
8923 +#define VLAN_PRI_MASK 7
8924 +
8925 +/* 802.1X ethertype */
8926 +#define ETHER_TYPE_802_1X 0x888e
8927 +
8928 +/*
8929 + * A macro to validate a length with
8930 + */
8931 +#define ETHER_IS_VALID_LEN(foo) \
8932 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8933 +
8934 +
8935 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8936 +/*
8937 + * Structure of a 10Mb/s Ethernet header.
8938 + */
8939 +struct ether_header {
8940 + uint8 ether_dhost[ETHER_ADDR_LEN];
8941 + uint8 ether_shost[ETHER_ADDR_LEN];
8942 + uint16 ether_type;
8943 +} PACKED ;
8944 +
8945 +/*
8946 + * Structure of a 48-bit Ethernet address.
8947 + */
8948 +struct ether_addr {
8949 + uint8 octet[ETHER_ADDR_LEN];
8950 +} PACKED ;
8951 +#endif
8952 +
8953 +/*
8954 + * Takes a pointer, returns true if a 48-bit multicast address
8955 + * (including broadcast, since it is all ones)
8956 + */
8957 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
8958 +
8959 +/*
8960 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
8961 + */
8962 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
8963 + ((uint8 *)(ea))[1] & \
8964 + ((uint8 *)(ea))[2] & \
8965 + ((uint8 *)(ea))[3] & \
8966 + ((uint8 *)(ea))[4] & \
8967 + ((uint8 *)(ea))[5]) == 0xff)
8968 +
8969 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
8970 +
8971 +/*
8972 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
8973 + */
8974 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
8975 + ((uint8 *)(ea))[1] | \
8976 + ((uint8 *)(ea))[2] | \
8977 + ((uint8 *)(ea))[3] | \
8978 + ((uint8 *)(ea))[4] | \
8979 + ((uint8 *)(ea))[5]) == 0)
8980 +
8981 +#undef PACKED
8982 +
8983 +#endif /* _NET_ETHERNET_H_ */
8984 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
8985 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
8986 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2005-12-15 12:57:27.869191250 +0100
8987 @@ -0,0 +1,103 @@
8988 +#ifndef _S5_H_
8989 +#define _S5_H_
8990 +/*
8991 + * Copyright 2003, Broadcom Corporation
8992 + * All Rights Reserved.
8993 + *
8994 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
8995 + * and MIPS3301 (R4K) System Address Space
8996 + *
8997 + * This program is free software; you can redistribute it and/or
8998 + * modify it under the terms of the GNU General Public License as
8999 + * published by the Free Software Foundation, located in the file
9000 + * LICENSE.
9001 + *
9002 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9003 + *
9004 + */
9005 +
9006 +/* BCM5365 Address map */
9007 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9008 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9009 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9010 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9011 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9012 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9013 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9014 +
9015 +/* BCM5365 Core register space */
9016 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9017 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9018 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9019 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9020 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9021 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9022 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9023 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9024 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9025 +
9026 +/* COM Ports 1/2 */
9027 +#define BCM5365_UART (BCM5365_REG_UARTS)
9028 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9029 +
9030 +/* Registers common to MIPS33 Core used in 5365 */
9031 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9032 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9033 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9034 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9035 +
9036 +/* Internal Core Sonics Backplane Devices */
9037 +#define INTERNAL_UART_COM1 BCM5365_UART
9038 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9039 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9040 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9041 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9042 +#define SB_REG_USB BCM5365_REG_USB
9043 +#define SB_REG_PCI BCM5365_REG_PCI
9044 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9045 +#define SB_REG_MEMC BCM5365_REG_MEMC
9046 +#define SB_REG_MEMC_OFF 0x6000
9047 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9048 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9049 +
9050 +/*
9051 + * XXX
9052 + * 5365-specific backplane interrupt flag numbers. This should be done
9053 + * dynamically instead.
9054 + */
9055 +#define SBFLAG_PCI 0
9056 +#define SBFLAG_ENET0 1
9057 +#define SBFLAG_ILINE20 2
9058 +#define SBFLAG_CODEC 3
9059 +#define SBFLAG_USB 4
9060 +#define SBFLAG_EXTIF 5
9061 +#define SBFLAG_ENET1 6
9062 +
9063 +/* BCM95365 Local Bus devices */
9064 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9065 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9066 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9067 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9068 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9069 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9070 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9071 +
9072 +/* Write to DLR2416 VFD Display character RAM */
9073 +#define LED_REG(x) \
9074 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9075 +
9076 +#ifdef CONFIG_VSIM
9077 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9078 + } while (0)
9079 +#else
9080 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9081 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9082 + *((int *)0xa0002ff8) = (trval); } while (0)
9083 +#endif
9084 +
9085 +/* BCM9536R Local Bus devices */
9086 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9087 +
9088 +
9089 +
9090 +#endif /*!_S5_H_ */
9091 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9092 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9093 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-12-15 15:35:20.458560250 +0100
9094 @@ -0,0 +1,440 @@
9095 +/*
9096 + * SiliconBackplane Chipcommon core hardware definitions.
9097 + *
9098 + * The chipcommon core provides chip identification, SB control,
9099 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9100 + * gpio interface, extbus, and support for serial and parallel flashes.
9101 + *
9102 + * $Id$
9103 + * Copyright 2005, Broadcom Corporation
9104 + * All Rights Reserved.
9105 + *
9106 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9107 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9108 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9109 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9110 + *
9111 + */
9112 +
9113 +#ifndef _SBCHIPC_H
9114 +#define _SBCHIPC_H
9115 +
9116 +
9117 +#ifndef _LANGUAGE_ASSEMBLY
9118 +
9119 +/* cpp contortions to concatenate w/arg prescan */
9120 +#ifndef PAD
9121 +#define _PADLINE(line) pad ## line
9122 +#define _XSTR(line) _PADLINE(line)
9123 +#define PAD _XSTR(__LINE__)
9124 +#endif /* PAD */
9125 +
9126 +typedef volatile struct {
9127 + uint32 chipid; /* 0x0 */
9128 + uint32 capabilities;
9129 + uint32 corecontrol; /* corerev >= 1 */
9130 + uint32 bist;
9131 +
9132 + /* OTP */
9133 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9134 + uint32 otpcontrol;
9135 + uint32 otpprog;
9136 + uint32 PAD;
9137 +
9138 + /* Interrupt control */
9139 + uint32 intstatus; /* 0x20 */
9140 + uint32 intmask;
9141 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9142 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9143 +
9144 + /* Jtag Master */
9145 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9146 + uint32 jtagir;
9147 + uint32 jtagdr;
9148 + uint32 jtagctrl;
9149 +
9150 + /* serial flash interface registers */
9151 + uint32 flashcontrol; /* 0x40 */
9152 + uint32 flashaddress;
9153 + uint32 flashdata;
9154 + uint32 PAD[1];
9155 +
9156 + /* Silicon backplane configuration broadcast control */
9157 + uint32 broadcastaddress; /* 0x50 */
9158 + uint32 broadcastdata;
9159 + uint32 PAD[2];
9160 +
9161 + /* gpio - cleared only by power-on-reset */
9162 + uint32 gpioin; /* 0x60 */
9163 + uint32 gpioout;
9164 + uint32 gpioouten;
9165 + uint32 gpiocontrol;
9166 + uint32 gpiointpolarity;
9167 + uint32 gpiointmask;
9168 + uint32 PAD[2];
9169 +
9170 + /* Watchdog timer */
9171 + uint32 watchdog; /* 0x80 */
9172 + uint32 PAD[1];
9173 +
9174 + /*GPIO based LED powersave registers corerev >= 16*/
9175 + uint32 gpiotimerval; /*0x88 */
9176 + uint32 gpiotimeroutmask;
9177 +
9178 + /* clock control */
9179 + uint32 clockcontrol_n; /* 0x90 */
9180 + uint32 clockcontrol_sb; /* aka m0 */
9181 + uint32 clockcontrol_pci; /* aka m1 */
9182 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9183 + uint32 clockcontrol_mips; /* aka m3 */
9184 + uint32 clkdiv; /* corerev >= 3 */
9185 + uint32 PAD[2];
9186 +
9187 + /* pll delay registers (corerev >= 4) */
9188 + uint32 pll_on_delay; /* 0xb0 */
9189 + uint32 fref_sel_delay;
9190 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9191 + uint32 PAD[1];
9192 +
9193 + /* Instaclock registers (corerev >= 10) */
9194 + uint32 system_clk_ctl; /* 0xc0 */
9195 + uint32 clkstatestretch;
9196 + uint32 PAD[14];
9197 +
9198 + /* ExtBus control registers (corerev >= 3) */
9199 + uint32 pcmcia_config; /* 0x100 */
9200 + uint32 pcmcia_memwait;
9201 + uint32 pcmcia_attrwait;
9202 + uint32 pcmcia_iowait;
9203 + uint32 ide_config;
9204 + uint32 ide_memwait;
9205 + uint32 ide_attrwait;
9206 + uint32 ide_iowait;
9207 + uint32 prog_config;
9208 + uint32 prog_waitcount;
9209 + uint32 flash_config;
9210 + uint32 flash_waitcount;
9211 + uint32 PAD[116];
9212 +
9213 + /* uarts */
9214 + uint8 uart0data; /* 0x300 */
9215 + uint8 uart0imr;
9216 + uint8 uart0fcr;
9217 + uint8 uart0lcr;
9218 + uint8 uart0mcr;
9219 + uint8 uart0lsr;
9220 + uint8 uart0msr;
9221 + uint8 uart0scratch;
9222 + uint8 PAD[248]; /* corerev >= 1 */
9223 +
9224 + uint8 uart1data; /* 0x400 */
9225 + uint8 uart1imr;
9226 + uint8 uart1fcr;
9227 + uint8 uart1lcr;
9228 + uint8 uart1mcr;
9229 + uint8 uart1lsr;
9230 + uint8 uart1msr;
9231 + uint8 uart1scratch;
9232 +} chipcregs_t;
9233 +
9234 +#endif /* _LANGUAGE_ASSEMBLY */
9235 +
9236 +#define CC_CHIPID 0
9237 +#define CC_CAPABILITIES 4
9238 +#define CC_JTAGCMD 0x30
9239 +#define CC_JTAGIR 0x34
9240 +#define CC_JTAGDR 0x38
9241 +#define CC_JTAGCTRL 0x3c
9242 +#define CC_WATCHDOG 0x80
9243 +#define CC_CLKC_N 0x90
9244 +#define CC_CLKC_M0 0x94
9245 +#define CC_CLKC_M1 0x98
9246 +#define CC_CLKC_M2 0x9c
9247 +#define CC_CLKC_M3 0xa0
9248 +#define CC_CLKDIV 0xa4
9249 +#define CC_SYS_CLK_CTL 0xc0
9250 +#define CC_OTP 0x800
9251 +
9252 +/* chipid */
9253 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9254 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9255 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9256 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9257 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9258 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9259 +#define CID_CC_SHIFT 24
9260 +
9261 +/* capabilities */
9262 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9263 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9264 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9265 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9266 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9267 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9268 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9269 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9270 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9271 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9272 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9273 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9274 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9275 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9276 +
9277 +/* PLL type */
9278 +#define PLL_NONE 0x00000000
9279 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9280 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9281 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9282 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9283 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9284 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9285 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9286 +
9287 +/* corecontrol */
9288 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9289 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9290 +
9291 +/* Fields in the otpstatus register */
9292 +#define OTPS_PROGFAIL 0x80000000
9293 +#define OTPS_PROTECT 0x00000007
9294 +#define OTPS_HW_PROTECT 0x00000001
9295 +#define OTPS_SW_PROTECT 0x00000002
9296 +#define OTPS_CID_PROTECT 0x00000004
9297 +
9298 +/* Fields in the otpcontrol register */
9299 +#define OTPC_RECWAIT 0xff000000
9300 +#define OTPC_PROGWAIT 0x00ffff00
9301 +#define OTPC_PRW_SHIFT 8
9302 +#define OTPC_MAXFAIL 0x00000038
9303 +#define OTPC_VSEL 0x00000006
9304 +#define OTPC_SELVL 0x00000001
9305 +
9306 +/* Fields in otpprog */
9307 +#define OTPP_COL_MASK 0x000000ff
9308 +#define OTPP_ROW_MASK 0x0000ff00
9309 +#define OTPP_ROW_SHIFT 8
9310 +#define OTPP_READERR 0x10000000
9311 +#define OTPP_VALUE 0x20000000
9312 +#define OTPP_VALUE_SHIFT 29
9313 +#define OTPP_READ 0x40000000
9314 +#define OTPP_START 0x80000000
9315 +#define OTPP_BUSY 0x80000000
9316 +
9317 +/* jtagcmd */
9318 +#define JCMD_START 0x80000000
9319 +#define JCMD_BUSY 0x80000000
9320 +#define JCMD_PAUSE 0x40000000
9321 +#define JCMD0_ACC_MASK 0x0000f000
9322 +#define JCMD0_ACC_IRDR 0x00000000
9323 +#define JCMD0_ACC_DR 0x00001000
9324 +#define JCMD0_ACC_IR 0x00002000
9325 +#define JCMD0_ACC_RESET 0x00003000
9326 +#define JCMD0_ACC_IRPDR 0x00004000
9327 +#define JCMD0_ACC_PDR 0x00005000
9328 +#define JCMD0_IRW_MASK 0x00000f00
9329 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9330 +#define JCMD_ACC_IRDR 0x00000000
9331 +#define JCMD_ACC_DR 0x00010000
9332 +#define JCMD_ACC_IR 0x00020000
9333 +#define JCMD_ACC_RESET 0x00030000
9334 +#define JCMD_ACC_IRPDR 0x00040000
9335 +#define JCMD_ACC_PDR 0x00050000
9336 +#define JCMD_IRW_MASK 0x00001f00
9337 +#define JCMD_IRW_SHIFT 8
9338 +#define JCMD_DRW_MASK 0x0000003f
9339 +
9340 +/* jtagctrl */
9341 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9342 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9343 +#define JCTRL_EN 1 /* Enable Jtag master */
9344 +
9345 +/* Fields in clkdiv */
9346 +#define CLKD_SFLASH 0x0f000000
9347 +#define CLKD_SFLASH_SHIFT 24
9348 +#define CLKD_OTP 0x000f0000
9349 +#define CLKD_OTP_SHIFT 16
9350 +#define CLKD_JTAG 0x00000f00
9351 +#define CLKD_JTAG_SHIFT 8
9352 +#define CLKD_UART 0x000000ff
9353 +
9354 +/* intstatus/intmask */
9355 +#define CI_GPIO 0x00000001 /* gpio intr */
9356 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9357 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9358 +
9359 +/* slow_clk_ctl */
9360 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9361 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9362 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9363 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9364 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9365 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9366 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9367 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9368 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9369 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9370 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9371 +#define SCC_CD_SHIFT 16
9372 +
9373 +/* system_clk_ctl */
9374 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9375 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9376 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9377 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9378 +#define SYCC_HR 0x00000010 /* Force HT */
9379 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9380 +#define SYCC_CD_SHIFT 16
9381 +
9382 +/* gpiotimerval*/
9383 +#define GPIO_ONTIME_SHIFT 16
9384 +
9385 +/* clockcontrol_n */
9386 +#define CN_N1_MASK 0x3f /* n1 control */
9387 +#define CN_N2_MASK 0x3f00 /* n2 control */
9388 +#define CN_N2_SHIFT 8
9389 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9390 +#define CN_PLLC_SHIFT 16
9391 +
9392 +/* clockcontrol_sb/pci/uart */
9393 +#define CC_M1_MASK 0x3f /* m1 control */
9394 +#define CC_M2_MASK 0x3f00 /* m2 control */
9395 +#define CC_M2_SHIFT 8
9396 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9397 +#define CC_M3_SHIFT 16
9398 +#define CC_MC_MASK 0x1f000000 /* mux control */
9399 +#define CC_MC_SHIFT 24
9400 +
9401 +/* N3M Clock control magic field values */
9402 +#define CC_F6_2 0x02 /* A factor of 2 in */
9403 +#define CC_F6_3 0x03 /* 6-bit fields like */
9404 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9405 +#define CC_F6_5 0x09
9406 +#define CC_F6_6 0x11
9407 +#define CC_F6_7 0x21
9408 +
9409 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9410 +
9411 +#define CC_MC_BYPASS 0x08
9412 +#define CC_MC_M1 0x04
9413 +#define CC_MC_M1M2 0x02
9414 +#define CC_MC_M1M2M3 0x01
9415 +#define CC_MC_M1M3 0x11
9416 +
9417 +/* Type 2 Clock control magic field values */
9418 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9419 +#define CC_T2M2_BIAS 3 /* m2 bias */
9420 +
9421 +#define CC_T2MC_M1BYP 1
9422 +#define CC_T2MC_M2BYP 2
9423 +#define CC_T2MC_M3BYP 4
9424 +
9425 +/* Type 6 Clock control magic field values */
9426 +#define CC_T6_MMASK 1 /* bits of interest in m */
9427 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9428 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9429 +#define SB2MIPS_T6(sb) (2 * (sb))
9430 +
9431 +/* Common clock base */
9432 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9433 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9434 +
9435 +/* Clock control values for 200Mhz in 5350 */
9436 +#define CLKC_5350_N 0x0311
9437 +#define CLKC_5350_M 0x04020009
9438 +
9439 +/* Flash types in the chipcommon capabilities register */
9440 +#define FLASH_NONE 0x000 /* No flash */
9441 +#define SFLASH_ST 0x100 /* ST serial flash */
9442 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9443 +#define PFLASH 0x700 /* Parallel flash */
9444 +
9445 +/* Bits in the config registers */
9446 +#define CC_CFG_EN 0x0001 /* Enable */
9447 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9448 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9449 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9450 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9451 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9452 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9453 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9454 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9455 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9456 +
9457 +/* Start/busy bit in flashcontrol */
9458 +#define SFLASH_START 0x80000000
9459 +#define SFLASH_BUSY SFLASH_START
9460 +
9461 +/* flashcontrol opcodes for ST flashes */
9462 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9463 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9464 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9465 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9466 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9467 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9468 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9469 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9470 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9471 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9472 +
9473 +/* Status register bits for ST flashes */
9474 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9475 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9476 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9477 +#define SFLASH_ST_BP_SHIFT 2
9478 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9479 +
9480 +/* flashcontrol opcodes for Atmel flashes */
9481 +#define SFLASH_AT_READ 0x07e8
9482 +#define SFLASH_AT_PAGE_READ 0x07d2
9483 +#define SFLASH_AT_BUF1_READ
9484 +#define SFLASH_AT_BUF2_READ
9485 +#define SFLASH_AT_STATUS 0x01d7
9486 +#define SFLASH_AT_BUF1_WRITE 0x0384
9487 +#define SFLASH_AT_BUF2_WRITE 0x0387
9488 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9489 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9490 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9491 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9492 +#define SFLASH_AT_PAGE_ERASE 0x0281
9493 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9494 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9495 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9496 +#define SFLASH_AT_BUF1_LOAD 0x0253
9497 +#define SFLASH_AT_BUF2_LOAD 0x0255
9498 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9499 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9500 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9501 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9502 +
9503 +/* Status register bits for Atmel flashes */
9504 +#define SFLASH_AT_READY 0x80
9505 +#define SFLASH_AT_MISMATCH 0x40
9506 +#define SFLASH_AT_ID_MASK 0x38
9507 +#define SFLASH_AT_ID_SHIFT 3
9508 +
9509 +/* OTP regions */
9510 +#define OTP_HW_REGION OTPS_HW_PROTECT
9511 +#define OTP_SW_REGION OTPS_SW_PROTECT
9512 +#define OTP_CID_REGION OTPS_CID_PROTECT
9513 +
9514 +/* OTP regions (Byte offsets from otp size) */
9515 +#define OTP_SWLIM_OFF (-8)
9516 +#define OTP_CIDBASE_OFF 0
9517 +#define OTP_CIDLIM_OFF 8
9518 +
9519 +/* Predefined OTP words (Word offset from otp size) */
9520 +#define OTP_BOUNDARY_OFF (-4)
9521 +#define OTP_HWSIGN_OFF (-3)
9522 +#define OTP_SWSIGN_OFF (-2)
9523 +#define OTP_CIDSIGN_OFF (-1)
9524 +
9525 +#define OTP_CID_OFF 0
9526 +#define OTP_PKG_OFF 1
9527 +#define OTP_FID_OFF 2
9528 +#define OTP_RSV_OFF 3
9529 +#define OTP_LIM_OFF 4
9530 +
9531 +#define OTP_SIGNATURE 0x578a
9532 +#define OTP_MAGIC 0x4e56
9533 +
9534 +#endif /* _SBCHIPC_H */
9535 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9536 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9537 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-12-15 15:35:24.538815250 +0100
9538 @@ -0,0 +1,342 @@
9539 +/*
9540 + * Broadcom SiliconBackplane hardware register definitions.
9541 + *
9542 + * Copyright 2005, Broadcom Corporation
9543 + * All Rights Reserved.
9544 + *
9545 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9546 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9547 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9548 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9549 + * $Id$
9550 + */
9551 +
9552 +#ifndef _SBCONFIG_H
9553 +#define _SBCONFIG_H
9554 +
9555 +/* cpp contortions to concatenate w/arg prescan */
9556 +#ifndef PAD
9557 +#define _PADLINE(line) pad ## line
9558 +#define _XSTR(line) _PADLINE(line)
9559 +#define PAD _XSTR(__LINE__)
9560 +#endif
9561 +
9562 +/*
9563 + * SiliconBackplane Address Map.
9564 + * All regions may not exist on all chips.
9565 + */
9566 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9567 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9568 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9569 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9570 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9571 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9572 +
9573 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9574 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9575 +
9576 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9577 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9578 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9579 +
9580 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9581 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9582 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9583 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9584 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9585 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9586 +
9587 +
9588 +/* enumeration space related defs */
9589 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9590 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9591 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9592 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9593 +
9594 +/* mips address */
9595 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9596 +
9597 +/*
9598 + * Sonics Configuration Space Registers.
9599 + */
9600 +#define SBIPSFLAG 0x08
9601 +#define SBTPSFLAG 0x18
9602 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9603 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9604 +#define SBADMATCH3 0x60
9605 +#define SBADMATCH2 0x68
9606 +#define SBADMATCH1 0x70
9607 +#define SBIMSTATE 0x90
9608 +#define SBINTVEC 0x94
9609 +#define SBTMSTATELOW 0x98
9610 +#define SBTMSTATEHIGH 0x9c
9611 +#define SBBWA0 0xa0
9612 +#define SBIMCONFIGLOW 0xa8
9613 +#define SBIMCONFIGHIGH 0xac
9614 +#define SBADMATCH0 0xb0
9615 +#define SBTMCONFIGLOW 0xb8
9616 +#define SBTMCONFIGHIGH 0xbc
9617 +#define SBBCONFIG 0xc0
9618 +#define SBBSTATE 0xc8
9619 +#define SBACTCNFG 0xd8
9620 +#define SBFLAGST 0xe8
9621 +#define SBIDLOW 0xf8
9622 +#define SBIDHIGH 0xfc
9623 +
9624 +#ifndef _LANGUAGE_ASSEMBLY
9625 +
9626 +typedef volatile struct _sbconfig {
9627 + uint32 PAD[2];
9628 + uint32 sbipsflag; /* initiator port ocp slave flag */
9629 + uint32 PAD[3];
9630 + uint32 sbtpsflag; /* target port ocp slave flag */
9631 + uint32 PAD[11];
9632 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9633 + uint32 PAD;
9634 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9635 + uint32 PAD[3];
9636 + uint32 sbadmatch3; /* address match3 */
9637 + uint32 PAD;
9638 + uint32 sbadmatch2; /* address match2 */
9639 + uint32 PAD;
9640 + uint32 sbadmatch1; /* address match1 */
9641 + uint32 PAD[7];
9642 + uint32 sbimstate; /* initiator agent state */
9643 + uint32 sbintvec; /* interrupt mask */
9644 + uint32 sbtmstatelow; /* target state */
9645 + uint32 sbtmstatehigh; /* target state */
9646 + uint32 sbbwa0; /* bandwidth allocation table0 */
9647 + uint32 PAD;
9648 + uint32 sbimconfiglow; /* initiator configuration */
9649 + uint32 sbimconfighigh; /* initiator configuration */
9650 + uint32 sbadmatch0; /* address match0 */
9651 + uint32 PAD;
9652 + uint32 sbtmconfiglow; /* target configuration */
9653 + uint32 sbtmconfighigh; /* target configuration */
9654 + uint32 sbbconfig; /* broadcast configuration */
9655 + uint32 PAD;
9656 + uint32 sbbstate; /* broadcast state */
9657 + uint32 PAD[3];
9658 + uint32 sbactcnfg; /* activate configuration */
9659 + uint32 PAD[3];
9660 + uint32 sbflagst; /* current sbflags */
9661 + uint32 PAD[3];
9662 + uint32 sbidlow; /* identification */
9663 + uint32 sbidhigh; /* identification */
9664 +} sbconfig_t;
9665 +
9666 +#endif /* _LANGUAGE_ASSEMBLY */
9667 +
9668 +/* sbipsflag */
9669 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9670 +#define SBIPS_INT1_SHIFT 0
9671 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9672 +#define SBIPS_INT2_SHIFT 8
9673 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9674 +#define SBIPS_INT3_SHIFT 16
9675 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9676 +#define SBIPS_INT4_SHIFT 24
9677 +
9678 +/* sbtpsflag */
9679 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9680 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9681 +
9682 +/* sbtmerrlog */
9683 +#define SBTMEL_CM 0x00000007 /* command */
9684 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9685 +#define SBTMEL_EC 0x0f000000 /* error code */
9686 +#define SBTMEL_ME 0x80000000 /* multiple error */
9687 +
9688 +/* sbimstate */
9689 +#define SBIM_PC 0xf /* pipecount */
9690 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9691 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9692 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9693 +#define SBIM_AP_TK 0x20 /* use token only */
9694 +#define SBIM_AP_RSV 0x30 /* reserved */
9695 +#define SBIM_IBE 0x20000 /* inbanderror */
9696 +#define SBIM_TO 0x40000 /* timeout */
9697 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9698 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9699 +
9700 +/* sbtmstatelow */
9701 +#define SBTML_RESET 0x1 /* reset */
9702 +#define SBTML_REJ_MASK 0x6 /* reject */
9703 +#define SBTML_REJ_SHIFT 1
9704 +#define SBTML_CLK 0x10000 /* clock enable */
9705 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9706 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9707 +#define SBTML_PE 0x40000000 /* pme enable */
9708 +#define SBTML_BE 0x80000000 /* bist enable */
9709 +
9710 +/* sbtmstatehigh */
9711 +#define SBTMH_SERR 0x1 /* serror */
9712 +#define SBTMH_INT 0x2 /* interrupt */
9713 +#define SBTMH_BUSY 0x4 /* busy */
9714 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9715 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9716 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9717 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9718 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9719 +#define SBTMH_BISTD 0x80000000 /* bist done */
9720 +
9721 +
9722 +/* sbbwa0 */
9723 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9724 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9725 +#define SBBWA_TAB1_SHIFT 16
9726 +
9727 +/* sbimconfiglow */
9728 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9729 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9730 +#define SBIMCL_RTO_SHIFT 4
9731 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9732 +#define SBIMCL_CID_SHIFT 16
9733 +
9734 +/* sbimconfighigh */
9735 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9736 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9737 +#define SBIMCH_TEM_SHIFT 4
9738 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9739 +#define SBIMCH_BEM_SHIFT 6
9740 +
9741 +/* sbadmatch0 */
9742 +#define SBAM_TYPE_MASK 0x3 /* address type */
9743 +#define SBAM_AD64 0x4 /* reserved */
9744 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9745 +#define SBAM_ADINT0_SHIFT 3
9746 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9747 +#define SBAM_ADINT1_SHIFT 3
9748 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9749 +#define SBAM_ADINT2_SHIFT 3
9750 +#define SBAM_ADEN 0x400 /* enable */
9751 +#define SBAM_ADNEG 0x800 /* negative decode */
9752 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9753 +#define SBAM_BASE0_SHIFT 8
9754 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9755 +#define SBAM_BASE1_SHIFT 12
9756 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9757 +#define SBAM_BASE2_SHIFT 16
9758 +
9759 +/* sbtmconfiglow */
9760 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9761 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9762 +#define SBTMCL_CO_SHIFT 11
9763 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9764 +#define SBTMCL_IF_SHIFT 18
9765 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9766 +#define SBTMCL_IM_SHIFT 24
9767 +
9768 +/* sbtmconfighigh */
9769 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9770 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9771 +#define SBTMCH_RM_SHIFT 2
9772 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9773 +#define SBTMCH_SM_SHIFT 4
9774 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9775 +#define SBTMCH_EM_SHIFT 8
9776 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9777 +#define SBTMCH_IM_SHIFT 10
9778 +
9779 +/* sbbconfig */
9780 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9781 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9782 +#define SBBC_MAX0_SHIFT 16
9783 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9784 +#define SBBC_MAX1_SHIFT 20
9785 +
9786 +/* sbbstate */
9787 +#define SBBS_SRD 0x1 /* st reg disable */
9788 +#define SBBS_HRD 0x2 /* hold reg disable */
9789 +
9790 +/* sbidlow */
9791 +#define SBIDL_CS_MASK 0x3 /* config space */
9792 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9793 +#define SBIDL_AR_SHIFT 3
9794 +#define SBIDL_SYNCH 0x40 /* sync */
9795 +#define SBIDL_INIT 0x80 /* initiator */
9796 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9797 +#define SBIDL_MINLAT_SHIFT 8
9798 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9799 +#define SBIDL_MAXLAT_SHIFT 12
9800 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9801 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9802 +#define SBIDL_CW_SHIFT 18
9803 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9804 +#define SBIDL_TP_SHIFT 20
9805 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9806 +#define SBIDL_IP_SHIFT 24
9807 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9808 +#define SBIDL_RV_SHIFT 28
9809 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9810 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9811 +
9812 +/* sbidhigh */
9813 +#define SBIDH_RC_MASK 0x000f /* revision code */
9814 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9815 +#define SBIDH_RCE_SHIFT 8
9816 +#define SBCOREREV(sbidh) \
9817 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9818 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9819 +#define SBIDH_CC_SHIFT 4
9820 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9821 +#define SBIDH_VC_SHIFT 16
9822 +
9823 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9824 +
9825 +/* vendor codes */
9826 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9827 +
9828 +/* core codes */
9829 +#define SB_CC 0x800 /* chipcommon core */
9830 +#define SB_ILINE20 0x801 /* iline20 core */
9831 +#define SB_SDRAM 0x803 /* sdram core */
9832 +#define SB_PCI 0x804 /* pci core */
9833 +#define SB_MIPS 0x805 /* mips core */
9834 +#define SB_ENET 0x806 /* enet mac core */
9835 +#define SB_CODEC 0x807 /* v90 codec core */
9836 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9837 +#define SB_ADSL 0x809 /* ADSL core */
9838 +#define SB_ILINE100 0x80a /* iline100 core */
9839 +#define SB_IPSEC 0x80b /* ipsec core */
9840 +#define SB_PCMCIA 0x80d /* pcmcia core */
9841 +#define SB_SOCRAM 0x80e /* internal memory core */
9842 +#define SB_MEMC 0x80f /* memc sdram core */
9843 +#define SB_EXTIF 0x811 /* external interface core */
9844 +#define SB_D11 0x812 /* 802.11 MAC core */
9845 +#define SB_MIPS33 0x816 /* mips3302 core */
9846 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9847 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9848 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9849 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9850 +#define SB_SDIOH 0x81b /* sdio host core */
9851 +#define SB_ROBO 0x81c /* roboswitch core */
9852 +#define SB_ATA100 0x81d /* parallel ATA core */
9853 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9854 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9855 +#define SB_PCIE 0x820 /* pci express core */
9856 +#define SB_SRAMC 0x822 /* SRAM controller core */
9857 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9858 +
9859 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9860 +
9861 +/* Not really related to Silicon Backplane, but a couple of software
9862 + * conventions for the use the flash space:
9863 + */
9864 +
9865 +/* Minumum amount of flash we support */
9866 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9867 +
9868 +/* A boot/binary may have an embedded block that describes its size */
9869 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9870 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9871 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9872 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9873 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9874 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9875 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9876 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9877 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9878 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9879 +
9880 +#endif /* _SBCONFIG_H */
9881 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9882 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9883 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-12-15 16:48:55.651993750 +0100
9884 @@ -0,0 +1,242 @@
9885 +/*
9886 + * Hardware-specific External Interface I/O core definitions
9887 + * for the BCM47xx family of SiliconBackplane-based chips.
9888 + *
9889 + * The External Interface core supports a total of three external chip selects
9890 + * supporting external interfaces. One of the external chip selects is
9891 + * used for Flash, one is used for PCMCIA, and the other may be
9892 + * programmed to support either a synchronous interface or an
9893 + * asynchronous interface. The asynchronous interface can be used to
9894 + * support external devices such as UARTs and the BCM2019 Bluetooth
9895 + * baseband processor.
9896 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9897 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9898 + *
9899 + * Copyright 2005, Broadcom Corporation
9900 + * All Rights Reserved.
9901 + *
9902 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9903 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9904 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9905 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9906 + * $Id$
9907 + */
9908 +
9909 +#ifndef _SBEXTIF_H
9910 +#define _SBEXTIF_H
9911 +
9912 +/* external interface address space */
9913 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9914 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9915 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9916 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9917 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9918 +
9919 +/* cpp contortions to concatenate w/arg prescan */
9920 +#ifndef PAD
9921 +#define _PADLINE(line) pad ## line
9922 +#define _XSTR(line) _PADLINE(line)
9923 +#define PAD _XSTR(__LINE__)
9924 +#endif /* PAD */
9925 +
9926 +/*
9927 + * The multiple instances of output and output enable registers
9928 + * are present to allow driver software for multiple cores to control
9929 + * gpio outputs without needing to share a single register pair.
9930 + */
9931 +struct gpiouser {
9932 + uint32 out;
9933 + uint32 outen;
9934 +};
9935 +#define NGPIOUSER 5
9936 +
9937 +typedef volatile struct {
9938 + uint32 corecontrol;
9939 + uint32 extstatus;
9940 + uint32 PAD[2];
9941 +
9942 + /* pcmcia control registers */
9943 + uint32 pcmcia_config;
9944 + uint32 pcmcia_memwait;
9945 + uint32 pcmcia_attrwait;
9946 + uint32 pcmcia_iowait;
9947 +
9948 + /* programmable interface control registers */
9949 + uint32 prog_config;
9950 + uint32 prog_waitcount;
9951 +
9952 + /* flash control registers */
9953 + uint32 flash_config;
9954 + uint32 flash_waitcount;
9955 + uint32 PAD[4];
9956 +
9957 + uint32 watchdog;
9958 +
9959 + /* clock control */
9960 + uint32 clockcontrol_n;
9961 + uint32 clockcontrol_sb;
9962 + uint32 clockcontrol_pci;
9963 + uint32 clockcontrol_mii;
9964 + uint32 PAD[3];
9965 +
9966 + /* gpio */
9967 + uint32 gpioin;
9968 + struct gpiouser gpio[NGPIOUSER];
9969 + uint32 PAD;
9970 + uint32 ejtagouten;
9971 + uint32 gpiointpolarity;
9972 + uint32 gpiointmask;
9973 + uint32 PAD[153];
9974 +
9975 + uint8 uartdata;
9976 + uint8 PAD[3];
9977 + uint8 uartimer;
9978 + uint8 PAD[3];
9979 + uint8 uartfcr;
9980 + uint8 PAD[3];
9981 + uint8 uartlcr;
9982 + uint8 PAD[3];
9983 + uint8 uartmcr;
9984 + uint8 PAD[3];
9985 + uint8 uartlsr;
9986 + uint8 PAD[3];
9987 + uint8 uartmsr;
9988 + uint8 PAD[3];
9989 + uint8 uartscratch;
9990 + uint8 PAD[3];
9991 +} extifregs_t;
9992 +
9993 +/* corecontrol */
9994 +#define CC_UE (1 << 0) /* uart enable */
9995 +
9996 +/* extstatus */
9997 +#define ES_EM (1 << 0) /* endian mode (ro) */
9998 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
9999 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10000 +
10001 +/* gpio bit mask */
10002 +#define GPIO_BIT0 (1 << 0)
10003 +#define GPIO_BIT1 (1 << 1)
10004 +#define GPIO_BIT2 (1 << 2)
10005 +#define GPIO_BIT3 (1 << 3)
10006 +#define GPIO_BIT4 (1 << 4)
10007 +#define GPIO_BIT5 (1 << 5)
10008 +#define GPIO_BIT6 (1 << 6)
10009 +#define GPIO_BIT7 (1 << 7)
10010 +
10011 +
10012 +/* pcmcia/prog/flash_config */
10013 +#define CF_EN (1 << 0) /* enable */
10014 +#define CF_EM_MASK 0xe /* mode */
10015 +#define CF_EM_SHIFT 1
10016 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10017 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10018 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10019 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10020 +#define CF_BS (1 << 5) /* byteswap */
10021 +#define CF_CD_MASK 0xc0 /* clock divider */
10022 +#define CF_CD_SHIFT 6
10023 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10024 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10025 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10026 +#define CF_CE (1 << 8) /* clock enable */
10027 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10028 +
10029 +/* pcmcia_memwait */
10030 +#define PM_W0_MASK 0x3f /* waitcount0 */
10031 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10032 +#define PM_W1_SHIFT 8
10033 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10034 +#define PM_W2_SHIFT 16
10035 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10036 +#define PM_W3_SHIFT 24
10037 +
10038 +/* pcmcia_attrwait */
10039 +#define PA_W0_MASK 0x3f /* waitcount0 */
10040 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10041 +#define PA_W1_SHIFT 8
10042 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10043 +#define PA_W2_SHIFT 16
10044 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10045 +#define PA_W3_SHIFT 24
10046 +
10047 +/* pcmcia_iowait */
10048 +#define PI_W0_MASK 0x3f /* waitcount0 */
10049 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10050 +#define PI_W1_SHIFT 8
10051 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10052 +#define PI_W2_SHIFT 16
10053 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10054 +#define PI_W3_SHIFT 24
10055 +
10056 +/* prog_waitcount */
10057 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10058 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10059 +#define PW_W1_SHIFT 8
10060 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10061 +#define PW_W2_SHIFT 16
10062 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10063 +#define PW_W3_SHIFT 24
10064 +
10065 +#define PW_W0 0x0000000c
10066 +#define PW_W1 0x00000a00
10067 +#define PW_W2 0x00020000
10068 +#define PW_W3 0x01000000
10069 +
10070 +/* flash_waitcount */
10071 +#define FW_W0_MASK 0x1f /* waitcount0 */
10072 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10073 +#define FW_W1_SHIFT 8
10074 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10075 +#define FW_W2_SHIFT 16
10076 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10077 +#define FW_W3_SHIFT 24
10078 +
10079 +/* watchdog */
10080 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10081 +
10082 +/* clockcontrol_n */
10083 +#define CN_N1_MASK 0x3f /* n1 control */
10084 +#define CN_N2_MASK 0x3f00 /* n2 control */
10085 +#define CN_N2_SHIFT 8
10086 +
10087 +/* clockcontrol_sb/pci/mii */
10088 +#define CC_M1_MASK 0x3f /* m1 control */
10089 +#define CC_M2_MASK 0x3f00 /* m2 control */
10090 +#define CC_M2_SHIFT 8
10091 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10092 +#define CC_M3_SHIFT 16
10093 +#define CC_MC_MASK 0x1f000000 /* mux control */
10094 +#define CC_MC_SHIFT 24
10095 +
10096 +/* Clock control default values */
10097 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10098 +#define CC_DEF_100 0x04020011
10099 +#define CC_DEF_33 0x11030011
10100 +#define CC_DEF_25 0x11050011
10101 +
10102 +/* Clock control values for 125Mhz */
10103 +#define CC_125_N 0x0802
10104 +#define CC_125_M 0x04020009
10105 +#define CC_125_M25 0x11090009
10106 +#define CC_125_M33 0x11090005
10107 +
10108 +/* Clock control magic field values */
10109 +#define CC_F6_2 0x02 /* A factor of 2 in */
10110 +#define CC_F6_3 0x03 /* 6-bit fields like */
10111 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10112 +#define CC_F6_5 0x09
10113 +#define CC_F6_6 0x11
10114 +#define CC_F6_7 0x21
10115 +
10116 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10117 +
10118 +#define CC_MC_BYPASS 0x08
10119 +#define CC_MC_M1 0x04
10120 +#define CC_MC_M1M2 0x02
10121 +#define CC_MC_M1M2M3 0x01
10122 +#define CC_MC_M1M3 0x11
10123 +
10124 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10125 +
10126 +#endif /* _SBEXTIF_H */
10127 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10128 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10129 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-12-15 15:35:31.567254500 +0100
10130 @@ -0,0 +1,148 @@
10131 +/*
10132 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10133 + *
10134 + * Copyright 2005, Broadcom Corporation
10135 + * All Rights Reserved.
10136 + *
10137 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10138 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10139 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10140 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10141 + *
10142 + * $Id$
10143 + */
10144 +
10145 +#ifndef _SBMEMC_H
10146 +#define _SBMEMC_H
10147 +
10148 +#ifdef _LANGUAGE_ASSEMBLY
10149 +
10150 +#define MEMC_CONTROL 0x00
10151 +#define MEMC_CONFIG 0x04
10152 +#define MEMC_REFRESH 0x08
10153 +#define MEMC_BISTSTAT 0x0c
10154 +#define MEMC_MODEBUF 0x10
10155 +#define MEMC_BKCLS 0x14
10156 +#define MEMC_PRIORINV 0x18
10157 +#define MEMC_DRAMTIM 0x1c
10158 +#define MEMC_INTSTAT 0x20
10159 +#define MEMC_INTMASK 0x24
10160 +#define MEMC_INTINFO 0x28
10161 +#define MEMC_NCDLCTL 0x30
10162 +#define MEMC_RDNCDLCOR 0x34
10163 +#define MEMC_WRNCDLCOR 0x38
10164 +#define MEMC_MISCDLYCTL 0x3c
10165 +#define MEMC_DQSGATENCDL 0x40
10166 +#define MEMC_SPARE 0x44
10167 +#define MEMC_TPADDR 0x48
10168 +#define MEMC_TPDATA 0x4c
10169 +#define MEMC_BARRIER 0x50
10170 +#define MEMC_CORE 0x54
10171 +
10172 +
10173 +#else
10174 +
10175 +/* Sonics side: MEMC core registers */
10176 +typedef volatile struct sbmemcregs {
10177 + uint32 control;
10178 + uint32 config;
10179 + uint32 refresh;
10180 + uint32 biststat;
10181 + uint32 modebuf;
10182 + uint32 bkcls;
10183 + uint32 priorinv;
10184 + uint32 dramtim;
10185 + uint32 intstat;
10186 + uint32 intmask;
10187 + uint32 intinfo;
10188 + uint32 reserved1;
10189 + uint32 ncdlctl;
10190 + uint32 rdncdlcor;
10191 + uint32 wrncdlcor;
10192 + uint32 miscdlyctl;
10193 + uint32 dqsgatencdl;
10194 + uint32 spare;
10195 + uint32 tpaddr;
10196 + uint32 tpdata;
10197 + uint32 barrier;
10198 + uint32 core;
10199 +} sbmemcregs_t;
10200 +
10201 +#endif
10202 +
10203 +/* MEMC Core Init values (OCP ID 0x80f) */
10204 +
10205 +/* For sdr: */
10206 +#define MEMC_SD_CONFIG_INIT 0x00048000
10207 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10208 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10209 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10210 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10211 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10212 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10213 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10214 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10215 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10216 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10217 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10218 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10219 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10220 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10221 +
10222 +
10223 +/* This is for SDRM8X8X4 */
10224 +#define MEMC_SDR_INIT 0x0008
10225 +#define MEMC_SDR_MODE 0x32
10226 +#define MEMC_SDR_NCDL 0x00020032
10227 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10228 +
10229 +/* For ddr: */
10230 +#define MEMC_CONFIG_INIT 0x00048000
10231 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10232 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10233 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10234 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10235 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10236 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10237 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10238 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10239 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10240 +#define MEMC_NCDLCTL_INIT 0x00002001
10241 +#define MEMC_CONTROL_INIT0 0x00000002
10242 +#define MEMC_CONTROL_INIT1 0x00000008
10243 +#define MEMC_MODEBUF_INIT0 0x00004000
10244 +#define MEMC_CONTROL_INIT2 0x00000010
10245 +#define MEMC_MODEBUF_INIT1 0x00000100
10246 +#define MEMC_CONTROL_INIT3 0x00000010
10247 +#define MEMC_CONTROL_INIT4 0x00000008
10248 +#define MEMC_REFRESH_INIT 0x0000840f
10249 +#define MEMC_CONTROL_INIT5 0x00000004
10250 +#define MEMC_MODEBUF_INIT2 0x00000000
10251 +#define MEMC_CONTROL_INIT6 0x00000010
10252 +#define MEMC_CONTROL_INIT7 0x00000001
10253 +
10254 +
10255 +/* This is for DDRM16X16X2 */
10256 +#define MEMC_DDR_INIT 0x0009
10257 +#define MEMC_DDR_MODE 0x62
10258 +#define MEMC_DDR_NCDL 0x0005050a
10259 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10260 +
10261 +/* mask for sdr/ddr calibration registers */
10262 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10263 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10264 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10265 +
10266 +/* masks for miscdlyctl registers */
10267 +#define MEMC_MISC_SM_MASK 0x30000000
10268 +#define MEMC_MISC_SM_SHIFT 28
10269 +#define MEMC_MISC_SD_MASK 0x0f000000
10270 +#define MEMC_MISC_SD_SHIFT 24
10271 +
10272 +/* hw threshhold for calculating wr/rd for sdr memc */
10273 +#define MEMC_CD_THRESHOLD 128
10274 +
10275 +/* Low bit of init register says if memc is ddr or sdr */
10276 +#define MEMC_CONFIG_DDR 0x00000001
10277 +
10278 +#endif /* _SBMEMC_H */
10279 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10280 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10281 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-12-15 16:46:57.616617000 +0100
10282 @@ -0,0 +1,62 @@
10283 +/*
10284 + * Broadcom SiliconBackplane MIPS definitions
10285 + *
10286 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10287 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10288 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10289 + * interface. The core revision is stored in the SB ID register in SB
10290 + * configuration space.
10291 + *
10292 + * Copyright 2005, Broadcom Corporation
10293 + * All Rights Reserved.
10294 + *
10295 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10296 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10297 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10298 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10299 + *
10300 + * $Id$
10301 + */
10302 +
10303 +#ifndef _SBMIPS_H
10304 +#define _SBMIPS_H
10305 +
10306 +#include <mipsinc.h>
10307 +
10308 +#ifndef _LANGUAGE_ASSEMBLY
10309 +
10310 +/* cpp contortions to concatenate w/arg prescan */
10311 +#ifndef PAD
10312 +#define _PADLINE(line) pad ## line
10313 +#define _XSTR(line) _PADLINE(line)
10314 +#define PAD _XSTR(__LINE__)
10315 +#endif /* PAD */
10316 +
10317 +typedef volatile struct {
10318 + uint32 corecontrol;
10319 + uint32 PAD[2];
10320 + uint32 biststatus;
10321 + uint32 PAD[4];
10322 + uint32 intstatus;
10323 + uint32 intmask;
10324 + uint32 timer;
10325 +} mipsregs_t;
10326 +
10327 +extern uint32 sb_flag(sb_t *sbh);
10328 +extern uint sb_irq(sb_t *sbh);
10329 +
10330 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10331 +
10332 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10333 +extern void sb_jtagm_disable(void *h);
10334 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10335 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10336 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10337 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10338 +extern void BCMINIT(enable_pfc)(uint32 mode);
10339 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10340 +
10341 +
10342 +#endif /* _LANGUAGE_ASSEMBLY */
10343 +
10344 +#endif /* _SBMIPS_H */
10345 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10346 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10347 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-12-15 15:35:36.795581250 +0100
10348 @@ -0,0 +1,122 @@
10349 +/*
10350 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10351 + *
10352 + * $Id$
10353 + * Copyright 2005, Broadcom Corporation
10354 + * All Rights Reserved.
10355 + *
10356 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10357 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10358 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10359 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10360 + */
10361 +
10362 +#ifndef _SBPCI_H
10363 +#define _SBPCI_H
10364 +
10365 +/* cpp contortions to concatenate w/arg prescan */
10366 +#ifndef PAD
10367 +#define _PADLINE(line) pad ## line
10368 +#define _XSTR(line) _PADLINE(line)
10369 +#define PAD _XSTR(__LINE__)
10370 +#endif
10371 +
10372 +/* Sonics side: PCI core and host control registers */
10373 +typedef struct sbpciregs {
10374 + uint32 control; /* PCI control */
10375 + uint32 PAD[3];
10376 + uint32 arbcontrol; /* PCI arbiter control */
10377 + uint32 PAD[3];
10378 + uint32 intstatus; /* Interrupt status */
10379 + uint32 intmask; /* Interrupt mask */
10380 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10381 + uint32 PAD[9];
10382 + uint32 bcastaddr; /* Sonics broadcast address */
10383 + uint32 bcastdata; /* Sonics broadcast data */
10384 + uint32 PAD[2];
10385 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10386 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10387 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10388 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10389 + uint32 PAD[36];
10390 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10391 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10392 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10393 + uint32 PAD[445];
10394 + uint16 sprom[36]; /* SPROM shadow Area */
10395 + uint32 PAD[46];
10396 +} sbpciregs_t;
10397 +
10398 +/* PCI control */
10399 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10400 +#define PCI_RST 0x02 /* Value driven out to pin */
10401 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10402 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10403 +
10404 +/* PCI arbiter control */
10405 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10406 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10407 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10408 +#define PCI_PARKID_SHIFT 1
10409 +#define PCI_PARKID_LAST 0 /* Last requestor */
10410 +#define PCI_PARKID_4710 1 /* 4710 */
10411 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10412 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10413 +
10414 +/* Interrupt status/mask */
10415 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10416 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10417 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10418 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10419 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10420 +
10421 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10422 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10423 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10424 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10425 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10426 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10427 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10428 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10429 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10430 +
10431 +/* Sonics broadcast address */
10432 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10433 +
10434 +/* Sonics to PCI translation types */
10435 +#define SBTOPCI0_MASK 0xfc000000
10436 +#define SBTOPCI1_MASK 0xfc000000
10437 +#define SBTOPCI2_MASK 0xc0000000
10438 +#define SBTOPCI_MEM 0
10439 +#define SBTOPCI_IO 1
10440 +#define SBTOPCI_CFG0 2
10441 +#define SBTOPCI_CFG1 3
10442 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10443 +#define SBTOPCI_BURST 0x8 /* burst enable */
10444 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10445 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10446 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10447 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10448 +
10449 +/* PCI core index in SROM shadow area */
10450 +#define SRSH_PI_OFFSET 0 /* first word */
10451 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10452 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10453 +
10454 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10455 +#define cap_list rsvd_a[0]
10456 +#define bar0_window dev_dep[0x80 - 0x40]
10457 +#define bar1_window dev_dep[0x84 - 0x40]
10458 +#define sprom_control dev_dep[0x88 - 0x40]
10459 +
10460 +#ifndef _LANGUAGE_ASSEMBLY
10461 +
10462 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10463 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10464 +extern void sbpci_ban(uint16 core);
10465 +extern int sbpci_init(sb_t *sbh);
10466 +extern void sbpci_check(sb_t *sbh);
10467 +
10468 +#endif /* !_LANGUAGE_ASSEMBLY */
10469 +
10470 +#endif /* _SBPCI_H */
10471 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10472 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10473 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-12-15 15:35:40.175792500 +0100
10474 @@ -0,0 +1,75 @@
10475 +/*
10476 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10477 + *
10478 + * Copyright 2005, Broadcom Corporation
10479 + * All Rights Reserved.
10480 + *
10481 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10482 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10483 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10484 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10485 + * $Id$
10486 + */
10487 +
10488 +#ifndef _SBSDRAM_H
10489 +#define _SBSDRAM_H
10490 +
10491 +#ifndef _LANGUAGE_ASSEMBLY
10492 +
10493 +/* Sonics side: SDRAM core registers */
10494 +typedef volatile struct sbsdramregs {
10495 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10496 + uint32 config; /* Initializes external SDRAM mode register */
10497 + uint32 refresh; /* Controls external SDRAM refresh rate */
10498 + uint32 pad1;
10499 + uint32 pad2;
10500 +} sbsdramregs_t;
10501 +
10502 +#endif
10503 +
10504 +/* SDRAM initialization control (initcontrol) register bits */
10505 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10506 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10507 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10508 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10509 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10510 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10511 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10512 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10513 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10514 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10515 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10516 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10517 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10518 +
10519 +/* SDRAM configuration (config) register bits */
10520 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10521 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10522 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10523 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10524 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10525 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10526 +
10527 +/* SDRAM refresh control (refresh) register bits */
10528 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10529 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10530 +
10531 +/* SDRAM Core default Init values (OCP ID 0x803) */
10532 +#define SDRAM_INIT MEM4MX16X2
10533 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10534 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10535 +
10536 +#define MEM1MX16 0x009 /* 2 MB */
10537 +#define MEM1MX16X2 0x409 /* 4 MB */
10538 +#define MEM2MX8X2 0x809 /* 4 MB */
10539 +#define MEM2MX8X4 0xc09 /* 8 MB */
10540 +#define MEM2MX32 0x439 /* 8 MB */
10541 +#define MEM4MX16 0x019 /* 8 MB */
10542 +#define MEM4MX16X2 0x419 /* 16 MB */
10543 +#define MEM8MX8X2 0x819 /* 16 MB */
10544 +#define MEM8MX16 0x829 /* 16 MB */
10545 +#define MEM4MX32 0x429 /* 16 MB */
10546 +#define MEM8MX8X4 0xc19 /* 32 MB */
10547 +#define MEM8MX16X2 0xc29 /* 32 MB */
10548 +
10549 +#endif /* _SBSDRAM_H */
10550 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10551 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10552 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-12-15 16:00:47.404550500 +0100
10553 @@ -0,0 +1,136 @@
10554 +/*
10555 + * Misc utility routines for accessing chip-specific features
10556 + * of Broadcom HNBU SiliconBackplane-based chips.
10557 + *
10558 + * Copyright 2005, Broadcom Corporation
10559 + * All Rights Reserved.
10560 + *
10561 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10562 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10563 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10564 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10565 + *
10566 + * $Id$
10567 + */
10568 +
10569 +#ifndef _sbutils_h_
10570 +#define _sbutils_h_
10571 +
10572 +/*
10573 + * Datastructure to export all chip specific common variables
10574 + * public (read-only) portion of sbutils handle returned by
10575 + * sb_attach()/sb_kattach()
10576 +*/
10577 +
10578 +struct sb_pub {
10579 +
10580 + uint bustype; /* SB_BUS, PCI_BUS */
10581 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10582 + uint buscorerev; /* buscore rev */
10583 + uint buscoreidx; /* buscore index */
10584 + int ccrev; /* chip common core rev */
10585 + uint boardtype; /* board type */
10586 + uint boardvendor; /* board vendor */
10587 + uint chip; /* chip number */
10588 + uint chiprev; /* chip revision */
10589 + uint chippkg; /* chip package option */
10590 + uint sonicsrev; /* sonics backplane rev */
10591 +};
10592 +
10593 +typedef const struct sb_pub sb_t;
10594 +
10595 +/*
10596 + * Many of the routines below take an 'sbh' handle as their first arg.
10597 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10598 + * At any one time, the sbh is logically focused on one particular sb core
10599 + * (the "current core").
10600 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10601 + */
10602 +
10603 +/* exported externs */
10604 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10605 +extern sb_t * BCMINIT(sb_kattach)(void);
10606 +extern void sb_detach(sb_t *sbh);
10607 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10608 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10609 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10610 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10611 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10612 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10613 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10614 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10615 +extern uint sb_bus(sb_t *sbh);
10616 +extern uint sb_buscoretype(sb_t *sbh);
10617 +extern uint sb_buscorerev(sb_t *sbh);
10618 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10619 +extern uint sb_coreid(sb_t *sbh);
10620 +extern uint sb_coreidx(sb_t *sbh);
10621 +extern uint sb_coreunit(sb_t *sbh);
10622 +extern uint sb_corevendor(sb_t *sbh);
10623 +extern uint sb_corerev(sb_t *sbh);
10624 +extern void *sb_osh(sb_t *sbh);
10625 +extern void *sb_coreregs(sb_t *sbh);
10626 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10627 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10628 +extern bool sb_iscoreup(sb_t *sbh);
10629 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10630 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10631 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10632 +extern void sb_commit(sb_t *sbh);
10633 +extern uint32 sb_base(uint32 admatch);
10634 +extern uint32 sb_size(uint32 admatch);
10635 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10636 +extern void sb_core_tofixup(sb_t *sbh);
10637 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10638 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10639 +extern uint32 sb_clock(sb_t *sbh);
10640 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10641 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10642 +extern void *sb_gpiosetcore(sb_t *sbh);
10643 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10644 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10645 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10646 +extern uint32 sb_gpioin(sb_t *sbh);
10647 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10648 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10649 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10650 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10651 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10652 +
10653 +extern void sb_clkctl_init(sb_t *sbh);
10654 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10655 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10656 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10657 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10658 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10659 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10660 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10661 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10662 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10663 +
10664 +
10665 +
10666 +/*
10667 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10668 +* The returned path is NULL terminated and has trailing '/'.
10669 +* Return 0 on success, nonzero otherwise.
10670 +*/
10671 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10672 +
10673 +/* clkctl xtal what flags */
10674 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10675 +#define PLL 0x2 /* main chip pll */
10676 +
10677 +/* clkctl clk mode */
10678 +#define CLK_FAST 0 /* force fast (pll) clock */
10679 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10680 +
10681 +
10682 +/* GPIO usage priorities */
10683 +#define GPIO_DRV_PRIORITY 0
10684 +#define GPIO_APP_PRIORITY 1
10685 +
10686 +/* device path */
10687 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10688 +
10689 +#endif /* _sbutils_h_ */
10690 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10691 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10692 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-12-15 16:49:23.001703000 +0100
10693 @@ -0,0 +1,36 @@
10694 +/*
10695 + * Broadcom SiliconBackplane chipcommon serial flash interface
10696 + *
10697 + * Copyright 2005, Broadcom Corporation
10698 + * All Rights Reserved.
10699 + *
10700 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10701 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10702 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10703 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10704 + *
10705 + * $Id$
10706 + */
10707 +
10708 +#ifndef _sflash_h_
10709 +#define _sflash_h_
10710 +
10711 +#include <typedefs.h>
10712 +#include <sbchipc.h>
10713 +
10714 +struct sflash {
10715 + uint blocksize; /* Block size */
10716 + uint numblocks; /* Number of blocks */
10717 + uint32 type; /* Type */
10718 + uint size; /* Total size in bytes */
10719 +};
10720 +
10721 +/* Utility functions */
10722 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10723 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10724 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10725 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10726 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10727 +extern struct sflash * sflash_init(chipcregs_t *cc);
10728 +
10729 +#endif /* _sflash_h_ */
10730 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10731 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10732 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-12-15 15:35:49.220357750 +0100
10733 @@ -0,0 +1,33 @@
10734 +/*
10735 + * TRX image file header format.
10736 + *
10737 + * Copyright 2005, Broadcom Corporation
10738 + * All Rights Reserved.
10739 + *
10740 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10741 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10742 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10743 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10744 + *
10745 + * $Id$
10746 + */
10747 +
10748 +#include <typedefs.h>
10749 +
10750 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10751 +#define TRX_VERSION 1
10752 +#define TRX_MAX_LEN 0x3A0000
10753 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10754 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10755 +#define TRX_MAX_OFFSET 3
10756 +
10757 +struct trx_header {
10758 + uint32 magic; /* "HDR0" */
10759 + uint32 len; /* Length of file including header */
10760 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10761 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10762 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10763 +};
10764 +
10765 +/* Compatibility */
10766 +typedef struct trx_header TRXHDR, *PTRXHDR;
10767 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10768 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10769 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-12-15 15:35:52.436558750 +0100
10770 @@ -0,0 +1,326 @@
10771 +/*
10772 + * Copyright 2005, Broadcom Corporation
10773 + * All Rights Reserved.
10774 + *
10775 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10776 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10777 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10778 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10779 + * $Id$
10780 + */
10781 +
10782 +#ifndef _TYPEDEFS_H_
10783 +#define _TYPEDEFS_H_
10784 +
10785 +
10786 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10787 + * typedef file "site_typedefs.h".
10788 + *
10789 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10790 + * section of this file makes inferences about the compile environment
10791 + * based on defined symbols and possibly compiler pragmas.
10792 + *
10793 + * Following these two sections is the "Default Typedefs"
10794 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10795 + * defined. This section has a default set of typedefs and a few
10796 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10797 + */
10798 +
10799 +#ifdef SITE_TYPEDEFS
10800 +
10801 +/*******************************************************************************
10802 + * Site Specific Typedefs
10803 + *******************************************************************************/
10804 +
10805 +#include "site_typedefs.h"
10806 +
10807 +#else
10808 +
10809 +/*******************************************************************************
10810 + * Inferred Typedefs
10811 + *******************************************************************************/
10812 +
10813 +/* Infer the compile environment based on preprocessor symbols and pramas.
10814 + * Override type definitions as needed, and include configuration dependent
10815 + * header files to define types.
10816 + */
10817 +
10818 +#ifdef __cplusplus
10819 +
10820 +#define TYPEDEF_BOOL
10821 +#ifndef FALSE
10822 +#define FALSE false
10823 +#endif
10824 +#ifndef TRUE
10825 +#define TRUE true
10826 +#endif
10827 +
10828 +#else /* ! __cplusplus */
10829 +
10830 +#if defined(_WIN32)
10831 +
10832 +#define TYPEDEF_BOOL
10833 +typedef unsigned char bool; /* consistent w/BOOL */
10834 +
10835 +#endif /* _WIN32 */
10836 +
10837 +#endif /* ! __cplusplus */
10838 +
10839 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10840 +#if defined(_WIN64)
10841 +#include <basetsd.h>
10842 +#define TYPEDEF_UINTPTR
10843 +typedef ULONG_PTR uintptr;
10844 +#endif
10845 +
10846 +#ifdef _HNDRTE_
10847 +typedef long unsigned int size_t;
10848 +#endif
10849 +
10850 +#ifdef _MSC_VER /* Microsoft C */
10851 +#define TYPEDEF_INT64
10852 +#define TYPEDEF_UINT64
10853 +typedef signed __int64 int64;
10854 +typedef unsigned __int64 uint64;
10855 +#endif
10856 +
10857 +#if defined(MACOSX) && defined(KERNEL)
10858 +#define TYPEDEF_BOOL
10859 +#endif
10860 +
10861 +
10862 +#if defined(linux)
10863 +#define TYPEDEF_UINT
10864 +#define TYPEDEF_USHORT
10865 +#define TYPEDEF_ULONG
10866 +#endif
10867 +
10868 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10869 +#define TYPEDEF_UINT
10870 +#define TYPEDEF_USHORT
10871 +#endif
10872 +
10873 +
10874 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10875 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10876 +#define TYPEDEF_INT64
10877 +#define TYPEDEF_UINT64
10878 +#endif
10879 +
10880 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10881 + * for singned or unsigned */
10882 +#if defined(__ICL)
10883 +
10884 +#define TYPEDEF_INT64
10885 +
10886 +#if defined(__STDC__)
10887 +#define TYPEDEF_UINT64
10888 +#endif
10889 +
10890 +#endif /* __ICL */
10891 +
10892 +
10893 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10894 +
10895 +/* pick up ushort & uint from standard types.h */
10896 +#if defined(linux) && defined(__KERNEL__)
10897 +
10898 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10899 +
10900 +#else
10901 +
10902 +#include <sys/types.h>
10903 +
10904 +#endif
10905 +
10906 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10907 +
10908 +#if defined(MACOSX) && defined(KERNEL)
10909 +#include <IOKit/IOTypes.h>
10910 +#endif
10911 +
10912 +
10913 +/* use the default typedefs in the next section of this file */
10914 +#define USE_TYPEDEF_DEFAULTS
10915 +
10916 +#endif /* SITE_TYPEDEFS */
10917 +
10918 +
10919 +/*******************************************************************************
10920 + * Default Typedefs
10921 + *******************************************************************************/
10922 +
10923 +#ifdef USE_TYPEDEF_DEFAULTS
10924 +#undef USE_TYPEDEF_DEFAULTS
10925 +
10926 +#ifndef TYPEDEF_BOOL
10927 +typedef /*@abstract@*/ unsigned char bool;
10928 +#endif
10929 +
10930 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10931 +
10932 +#ifndef TYPEDEF_UCHAR
10933 +typedef unsigned char uchar;
10934 +#endif
10935 +
10936 +#ifndef TYPEDEF_USHORT
10937 +typedef unsigned short ushort;
10938 +#endif
10939 +
10940 +#ifndef TYPEDEF_UINT
10941 +typedef unsigned int uint;
10942 +#endif
10943 +
10944 +#ifndef TYPEDEF_ULONG
10945 +typedef unsigned long ulong;
10946 +#endif
10947 +
10948 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
10949 +
10950 +#ifndef TYPEDEF_UINT8
10951 +typedef unsigned char uint8;
10952 +#endif
10953 +
10954 +#ifndef TYPEDEF_UINT16
10955 +typedef unsigned short uint16;
10956 +#endif
10957 +
10958 +#ifndef TYPEDEF_UINT32
10959 +typedef unsigned int uint32;
10960 +#endif
10961 +
10962 +#ifndef TYPEDEF_UINT64
10963 +typedef unsigned long long uint64;
10964 +#endif
10965 +
10966 +#ifndef TYPEDEF_UINTPTR
10967 +typedef unsigned int uintptr;
10968 +#endif
10969 +
10970 +#ifndef TYPEDEF_INT8
10971 +typedef signed char int8;
10972 +#endif
10973 +
10974 +#ifndef TYPEDEF_INT16
10975 +typedef signed short int16;
10976 +#endif
10977 +
10978 +#ifndef TYPEDEF_INT32
10979 +typedef signed int int32;
10980 +#endif
10981 +
10982 +#ifndef TYPEDEF_INT64
10983 +typedef signed long long int64;
10984 +#endif
10985 +
10986 +/*----------------------- define float32/64, float_t -----------------------*/
10987 +
10988 +#ifndef TYPEDEF_FLOAT32
10989 +typedef float float32;
10990 +#endif
10991 +
10992 +#ifndef TYPEDEF_FLOAT64
10993 +typedef double float64;
10994 +#endif
10995 +
10996 +/*
10997 + * abstracted floating point type allows for compile time selection of
10998 + * single or double precision arithmetic. Compiling with -DFLOAT32
10999 + * selects single precision; the default is double precision.
11000 + */
11001 +
11002 +#ifndef TYPEDEF_FLOAT_T
11003 +
11004 +#if defined(FLOAT32)
11005 +typedef float32 float_t;
11006 +#else /* default to double precision floating point */
11007 +typedef float64 float_t;
11008 +#endif
11009 +
11010 +#endif /* TYPEDEF_FLOAT_T */
11011 +
11012 +/*----------------------- define macro values -----------------------------*/
11013 +
11014 +#ifndef FALSE
11015 +#define FALSE 0
11016 +#endif
11017 +
11018 +#ifndef TRUE
11019 +#define TRUE 1
11020 +#endif
11021 +
11022 +#ifndef NULL
11023 +#define NULL 0
11024 +#endif
11025 +
11026 +#ifndef OFF
11027 +#define OFF 0
11028 +#endif
11029 +
11030 +#ifndef ON
11031 +#define ON 1
11032 +#endif
11033 +
11034 +#define AUTO (-1)
11035 +
11036 +/* Reclaiming text and data :
11037 + The following macros specify special linker sections that can be reclaimed
11038 + after a system is considered 'up'.
11039 + */
11040 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11041 +extern bool bcmreclaimed;
11042 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11043 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11044 +#define BCMINIT(_id) _id##_ini
11045 +#else
11046 +#define BCMINITDATA(_data) _data
11047 +#define BCMINITFN(_fn) _fn
11048 +#define BCMINIT(_id) _id
11049 +#define bcmreclaimed 0
11050 +#endif
11051 +
11052 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11053 +
11054 +#ifndef PTRSZ
11055 +#define PTRSZ sizeof (char*)
11056 +#endif
11057 +
11058 +#ifndef INLINE
11059 +
11060 +#ifdef _MSC_VER
11061 +
11062 +#define INLINE __inline
11063 +
11064 +#elif __GNUC__
11065 +
11066 +#define INLINE __inline__
11067 +
11068 +#else
11069 +
11070 +#define INLINE
11071 +
11072 +#endif /* _MSC_VER */
11073 +
11074 +#endif /* INLINE */
11075 +
11076 +#undef TYPEDEF_BOOL
11077 +#undef TYPEDEF_UCHAR
11078 +#undef TYPEDEF_USHORT
11079 +#undef TYPEDEF_UINT
11080 +#undef TYPEDEF_ULONG
11081 +#undef TYPEDEF_UINT8
11082 +#undef TYPEDEF_UINT16
11083 +#undef TYPEDEF_UINT32
11084 +#undef TYPEDEF_UINT64
11085 +#undef TYPEDEF_UINTPTR
11086 +#undef TYPEDEF_INT8
11087 +#undef TYPEDEF_INT16
11088 +#undef TYPEDEF_INT32
11089 +#undef TYPEDEF_INT64
11090 +#undef TYPEDEF_FLOAT32
11091 +#undef TYPEDEF_FLOAT64
11092 +#undef TYPEDEF_FLOAT_T
11093 +
11094 +#endif /* USE_TYPEDEF_DEFAULTS */
11095 +
11096 +#endif /* _TYPEDEFS_H_ */
11097 diff -urN linux.old/arch/mips/bcm947xx/int-handler.S linux.dev/arch/mips/bcm947xx/int-handler.S
11098 --- linux.old/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
11099 +++ linux.dev/arch/mips/bcm947xx/int-handler.S 2005-12-15 12:57:27.877187750 +0100
11100 @@ -0,0 +1,48 @@
11101 +/*
11102 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11103 + *
11104 + * This program is free software; you can redistribute it and/or modify it
11105 + * under the terms of the GNU General Public License as published by the
11106 + * Free Software Foundation; either version 2 of the License, or (at your
11107 + * option) any later version.
11108 + *
11109 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11110 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11111 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11112 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11113 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11114 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11115 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11116 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11117 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11118 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11119 + *
11120 + * You should have received a copy of the GNU General Public License along
11121 + * with this program; if not, write to the Free Software Foundation, Inc.,
11122 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11123 + */
11124 +
11125 +#include <asm/asm.h>
11126 +#include <asm/mipsregs.h>
11127 +#include <asm/regdef.h>
11128 +#include <asm/stackframe.h>
11129 +
11130 + .text
11131 + .set noreorder
11132 + .set noat
11133 + .align 5
11134 +
11135 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
11136 + SAVE_ALL
11137 + CLI
11138 +
11139 + .set at
11140 + .set noreorder
11141 +
11142 + jal bcm47xx_irq_dispatch
11143 + move a0, sp
11144 +
11145 + j ret_from_irq
11146 + nop
11147 +
11148 + END(bcm47xx_irq_handler)
11149 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11150 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11151 +++ linux.dev/arch/mips/bcm947xx/irq.c 2005-12-15 12:57:27.877187750 +0100
11152 @@ -0,0 +1,67 @@
11153 +/*
11154 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11155 + *
11156 + * This program is free software; you can redistribute it and/or modify it
11157 + * under the terms of the GNU General Public License as published by the
11158 + * Free Software Foundation; either version 2 of the License, or (at your
11159 + * option) any later version.
11160 + *
11161 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11162 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11163 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11164 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11165 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11166 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11167 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11168 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11169 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11170 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11171 + *
11172 + * You should have received a copy of the GNU General Public License along
11173 + * with this program; if not, write to the Free Software Foundation, Inc.,
11174 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11175 + */
11176 +
11177 +#include <linux/config.h>
11178 +#include <linux/errno.h>
11179 +#include <linux/init.h>
11180 +#include <linux/interrupt.h>
11181 +#include <linux/irq.h>
11182 +#include <linux/module.h>
11183 +#include <linux/smp.h>
11184 +#include <linux/types.h>
11185 +
11186 +#include <asm/cpu.h>
11187 +#include <asm/io.h>
11188 +#include <asm/irq.h>
11189 +#include <asm/irq_cpu.h>
11190 +
11191 +extern asmlinkage void bcm47xx_irq_handler(void);
11192 +
11193 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
11194 +{
11195 + u32 cause;
11196 +
11197 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11198 +
11199 + clear_c0_status(cause);
11200 +
11201 + if (cause & CAUSEF_IP7)
11202 + do_IRQ(7, regs);
11203 + if (cause & CAUSEF_IP2)
11204 + do_IRQ(2, regs);
11205 + if (cause & CAUSEF_IP3)
11206 + do_IRQ(3, regs);
11207 + if (cause & CAUSEF_IP4)
11208 + do_IRQ(4, regs);
11209 + if (cause & CAUSEF_IP5)
11210 + do_IRQ(5, regs);
11211 + if (cause & CAUSEF_IP6)
11212 + do_IRQ(6, regs);
11213 +}
11214 +
11215 +void __init arch_init_irq(void)
11216 +{
11217 + set_except_vector(0, bcm47xx_irq_handler);
11218 + mips_cpu_irq_init(0);
11219 +}
11220 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11221 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11222 +++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-17 18:11:52.350836000 +0100
11223 @@ -0,0 +1,92 @@
11224 +#include <linux/kernel.h>
11225 +#include <linux/init.h>
11226 +#include <linux/pci.h>
11227 +#include <linux/types.h>
11228 +
11229 +#include <asm/cpu.h>
11230 +#include <asm/io.h>
11231 +
11232 +#include <typedefs.h>
11233 +#include <osl.h>
11234 +#include <sbutils.h>
11235 +#include <sbmips.h>
11236 +#include <sbconfig.h>
11237 +#include <sbpci.h>
11238 +
11239 +extern sb_t *sbh;
11240 +
11241 +
11242 +static int
11243 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11244 + int reg, int size, u32 *val)
11245 +{
11246 + int ret;
11247 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11248 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11249 +}
11250 +
11251 +static int
11252 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11253 + int reg, int size, u32 val)
11254 +{
11255 + int ret;
11256 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11257 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11258 +}
11259 +
11260 +
11261 +static struct pci_ops sb_pci_ops = {
11262 + .read = sb_pci_read_config,
11263 + .write = sb_pci_write_config,
11264 +};
11265 +
11266 +
11267 +static struct resource sb_pci_mem_resource = {
11268 + .name = "SB PCI Memory resources",
11269 + .start = SB_ENUM_BASE,
11270 + .end = SB_ENUM_LIM - 1,
11271 + .flags = IORESOURCE_MEM,
11272 +};
11273 +
11274 +static struct resource sb_pci_io_resource = {
11275 + .name = "SB PCI I/O resources",
11276 + .start = 0x100,
11277 + .end = 0x1FF,
11278 + .flags = IORESOURCE_IO,
11279 +};
11280 +
11281 +static struct pci_controller bcm47xx_sb_pci_controller = {
11282 + .pci_ops = &sb_pci_ops,
11283 + .mem_resource = &sb_pci_mem_resource,
11284 + .io_resource = &sb_pci_io_resource,
11285 +};
11286 +
11287 +static struct resource ext_pci_mem_resource = {
11288 + .name = "Ext PCI Memory resources",
11289 + .start = 0x40000000,
11290 + .end = 0x40ffffff,
11291 + .flags = IORESOURCE_MEM,
11292 +};
11293 +
11294 +static struct resource ext_pci_io_resource = {
11295 + .name = "Ext PCI I/O resources",
11296 + .start = 0x200,
11297 + .end = 0x2FF,
11298 + .flags = IORESOURCE_IO,
11299 +};
11300 +
11301 +static struct pci_controller bcm47xx_ext_pci_controller = {
11302 + .pci_ops = &sb_pci_ops,
11303 + .mem_resource = &ext_pci_mem_resource,
11304 + .io_resource = &ext_pci_io_resource,
11305 +};
11306 +
11307 +void bcm47xx_pci_init(void)
11308 +{
11309 + sbpci_init(sbh);
11310 +
11311 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11312 +
11313 + register_pci_controller(&bcm47xx_sb_pci_controller);
11314 + register_pci_controller(&bcm47xx_ext_pci_controller);
11315 +}
11316 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11317 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11318 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-12-15 12:57:27.877187750 +0100
11319 @@ -0,0 +1,59 @@
11320 +/*
11321 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11322 + *
11323 + * This program is free software; you can redistribute it and/or modify it
11324 + * under the terms of the GNU General Public License as published by the
11325 + * Free Software Foundation; either version 2 of the License, or (at your
11326 + * option) any later version.
11327 + *
11328 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11329 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11330 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11331 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11332 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11333 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11334 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11335 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11336 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11337 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11338 + *
11339 + * You should have received a copy of the GNU General Public License along
11340 + * with this program; if not, write to the Free Software Foundation, Inc.,
11341 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11342 + */
11343 +
11344 +#include <linux/init.h>
11345 +#include <linux/mm.h>
11346 +#include <linux/sched.h>
11347 +#include <linux/bootmem.h>
11348 +
11349 +#include <asm/addrspace.h>
11350 +#include <asm/bootinfo.h>
11351 +#include <asm/pmon.h>
11352 +
11353 +const char *get_system_type(void)
11354 +{
11355 + return "Broadcom BCM47xx";
11356 +}
11357 +
11358 +void __init prom_init(void)
11359 +{
11360 + unsigned long mem;
11361 +
11362 + mips_machgroup = MACH_GROUP_BRCM;
11363 + mips_machtype = MACH_BCM47XX;
11364 +
11365 + /* Figure out memory size by finding aliases */
11366 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11367 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11368 + *(unsigned long *)(prom_init))
11369 + break;
11370 + }
11371 +
11372 + add_memory_region(0, mem, BOOT_MEM_RAM);
11373 +}
11374 +
11375 +unsigned long __init prom_free_prom_memory(void)
11376 +{
11377 + return 0;
11378 +}
11379 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11380 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11381 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-17 22:14:27.619043750 +0100
11382 @@ -0,0 +1,155 @@
11383 +/*
11384 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11385 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11386 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11387 + *
11388 + * This program is free software; you can redistribute it and/or modify it
11389 + * under the terms of the GNU General Public License as published by the
11390 + * Free Software Foundation; either version 2 of the License, or (at your
11391 + * option) any later version.
11392 + *
11393 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11394 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11395 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11396 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11397 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11398 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11399 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11400 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11401 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11402 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11403 + *
11404 + * You should have received a copy of the GNU General Public License along
11405 + * with this program; if not, write to the Free Software Foundation, Inc.,
11406 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11407 + */
11408 +
11409 +#include <linux/init.h>
11410 +#include <linux/types.h>
11411 +#include <linux/tty.h>
11412 +#include <linux/serial.h>
11413 +#include <linux/serial_core.h>
11414 +#include <linux/serial_reg.h>
11415 +#include <asm/bootinfo.h>
11416 +#include <asm/time.h>
11417 +#include <asm/reboot.h>
11418 +
11419 +#include <typedefs.h>
11420 +#include <osl.h>
11421 +#include <sbutils.h>
11422 +#include <sbmips.h>
11423 +#include <sbpci.h>
11424 +#include <sbconfig.h>
11425 +#include <bcmdevs.h>
11426 +
11427 +extern void bcm47xx_pci_init(void);
11428 +extern void bcm47xx_time_init(void);
11429 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11430 +void *sbh;
11431 +int boardflags;
11432 +
11433 +static int ser_line = 0;
11434 +
11435 +typedef struct {
11436 + void *regs;
11437 + uint irq;
11438 + uint baud_base;
11439 + uint reg_shift;
11440 +} serial_port;
11441 +
11442 +static serial_port ports[4];
11443 +static int num_ports = 0;
11444 +
11445 +static void
11446 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11447 +{
11448 + ports[num_ports].regs = regs;
11449 + ports[num_ports].irq = irq;
11450 + ports[num_ports].baud_base = baud_base;
11451 + ports[num_ports].reg_shift = reg_shift;
11452 + num_ports++;
11453 +}
11454 +
11455 +static void
11456 +do_serial_add(serial_port *port)
11457 +{
11458 + void *regs;
11459 + uint irq;
11460 + uint baud_base;
11461 + uint reg_shift;
11462 + struct uart_port s;
11463 +
11464 + regs = port->regs;
11465 + irq = port->irq;
11466 + baud_base = port->baud_base;
11467 + reg_shift = port->reg_shift;
11468 +
11469 + memset(&s, 0, sizeof(s));
11470 +
11471 + s.line = ser_line++;
11472 + s.membase = regs;
11473 + s.irq = irq + 2;
11474 + s.uartclk = baud_base;
11475 + s.flags = ASYNC_BOOT_AUTOCONF;
11476 + s.iotype = SERIAL_IO_MEM;
11477 + s.regshift = reg_shift;
11478 +
11479 + if (early_serial_setup(&s) != 0) {
11480 + printk(KERN_ERR "Serial setup failed!\n");
11481 + }
11482 +}
11483 +
11484 +static void bcm47xx_machine_restart(char *command)
11485 +{
11486 + printk("Please stand by while rebooting the system...\n");
11487 +
11488 + /* Set the watchdog timer to reset immediately */
11489 + local_irq_disable();
11490 + sb_watchdog(sbh, 1);
11491 + while (1);
11492 +}
11493 +
11494 +static void bcm47xx_machine_halt(void)
11495 +{
11496 + /* Disable interrupts and watchdog and spin forever */
11497 + local_irq_disable();
11498 + sb_watchdog(sbh, 0);
11499 + while (1);
11500 +}
11501 +
11502 +void __init plat_setup(void)
11503 +{
11504 + char *s;
11505 + int i;
11506 +
11507 + sbh = sb_kattach();
11508 + sb_mips_init(sbh);
11509 +
11510 + bcm47xx_pci_init();
11511 +
11512 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11513 +
11514 + sb_serial_init(sbh, serial_add);
11515 + boardflags = getintvar(NULL, "boardflags");
11516 +
11517 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11518 + s = nvram_get("kernel_args");
11519 + if (!s) s = "";
11520 + if (!strncmp(s, "console=ttyS1", 13)) {
11521 + for (i = num_ports; i; i--)
11522 + do_serial_add(&ports[i - 1]);
11523 + } else {
11524 + for (i = 0; i < num_ports; i++)
11525 + do_serial_add(&ports[i]);
11526 + }
11527 +
11528 + _machine_restart = bcm47xx_machine_restart;
11529 + _machine_halt = bcm47xx_machine_halt;
11530 + _machine_power_off = bcm47xx_machine_halt;
11531 +
11532 + board_time_init = bcm47xx_time_init;
11533 + board_timer_setup = bcm47xx_timer_setup;
11534 +}
11535 +
11536 +EXPORT_SYMBOL(sbh);
11537 +EXPORT_SYMBOL(boardflags);
11538 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11539 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11540 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-12-15 12:57:27.877187750 +0100
11541 @@ -0,0 +1,59 @@
11542 +/*
11543 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11544 + *
11545 + * This program is free software; you can redistribute it and/or modify it
11546 + * under the terms of the GNU General Public License as published by the
11547 + * Free Software Foundation; either version 2 of the License, or (at your
11548 + * option) any later version.
11549 + *
11550 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11551 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11552 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11553 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11554 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11555 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11556 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11557 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11558 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11559 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11560 + *
11561 + * You should have received a copy of the GNU General Public License along
11562 + * with this program; if not, write to the Free Software Foundation, Inc.,
11563 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11564 + */
11565 +
11566 +#include <linux/config.h>
11567 +#include <linux/init.h>
11568 +#include <linux/kernel.h>
11569 +#include <linux/sched.h>
11570 +#include <linux/serial_reg.h>
11571 +#include <linux/interrupt.h>
11572 +#include <asm/addrspace.h>
11573 +#include <asm/io.h>
11574 +#include <asm/time.h>
11575 +
11576 +void __init
11577 +bcm47xx_time_init(void)
11578 +{
11579 + unsigned int hz;
11580 +
11581 + /*
11582 + * Use deterministic values for initial counter interrupt
11583 + * so that calibrate delay avoids encountering a counter wrap.
11584 + */
11585 + write_c0_count(0);
11586 + write_c0_compare(0xffff);
11587 +
11588 + hz = 200 * 1000 * 1000;
11589 +
11590 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11591 + mips_hpt_frequency = hz / 2;
11592 +
11593 +}
11594 +
11595 +void __init
11596 +bcm47xx_timer_setup(struct irqaction *irq)
11597 +{
11598 + /* Enable the timer interrupt */
11599 + setup_irq(7, irq);
11600 +}
11601 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11602 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-12-15 13:26:49.766024000 +0100
11603 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-12-15 12:57:27.901177250 +0100
11604 @@ -656,6 +656,28 @@
11605 }
11606
11607
11608 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11609 +{
11610 + decode_config1(c);
11611 + switch (c->processor_id & 0xff00) {
11612 + case PRID_IMP_BCM3302:
11613 + c->cputype = CPU_BCM3302;
11614 + c->isa_level = MIPS_CPU_ISA_M32;
11615 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11616 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11617 + break;
11618 + case PRID_IMP_BCM4710:
11619 + c->cputype = CPU_BCM4710;
11620 + c->isa_level = MIPS_CPU_ISA_M32;
11621 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11622 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11623 + break;
11624 + default:
11625 + c->cputype = CPU_UNKNOWN;
11626 + break;
11627 + }
11628 +}
11629 +
11630 __init void cpu_probe(void)
11631 {
11632 struct cpuinfo_mips *c = &current_cpu_data;
11633 @@ -678,6 +700,9 @@
11634 case PRID_COMP_SIBYTE:
11635 cpu_probe_sibyte(c);
11636 break;
11637 + case PRID_COMP_BROADCOM:
11638 + cpu_probe_broadcom(c);
11639 + break;
11640 case PRID_COMP_SANDCRAFT:
11641 cpu_probe_sandcraft(c);
11642 break;
11643 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11644 --- linux.old/arch/mips/kernel/head.S 2005-12-15 13:26:49.766024000 +0100
11645 +++ linux.dev/arch/mips/kernel/head.S 2005-12-15 12:57:27.901177250 +0100
11646 @@ -107,6 +107,14 @@
11647 #endif
11648 .endm
11649
11650 +#ifdef CONFIG_BCM4710
11651 +#undef eret
11652 +#define eret nop; nop; eret
11653 +#endif
11654 +
11655 + j kernel_entry
11656 + nop
11657 +
11658 /*
11659 * Reserved space for exception handlers.
11660 * Necessary for machines which link their kernels at KSEG0.
11661 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11662 --- linux.old/arch/mips/kernel/proc.c 2005-12-15 13:26:49.766024000 +0100
11663 +++ linux.dev/arch/mips/kernel/proc.c 2005-12-15 12:57:27.921168500 +0100
11664 @@ -82,6 +82,8 @@
11665 [CPU_VR4181] = "NEC VR4181",
11666 [CPU_VR4181A] = "NEC VR4181A",
11667 [CPU_SR71000] = "Sandcraft SR71000",
11668 + [CPU_BCM3302] = "Broadcom BCM3302",
11669 + [CPU_BCM4710] = "Broadcom BCM4710",
11670 [CPU_PR4450] = "Philips PR4450",
11671 };
11672
11673 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11674 --- linux.old/arch/mips/mm/tlbex.c 2005-12-15 13:26:49.794011750 +0100
11675 +++ linux.dev/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
11676 @@ -858,6 +858,8 @@
11677 case CPU_4KSC:
11678 case CPU_20KC:
11679 case CPU_25KF:
11680 + case CPU_BCM3302:
11681 + case CPU_BCM4710:
11682 tlbw(p);
11683 break;
11684
11685 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
11686 --- linux.old/arch/mips/pci/Makefile 2005-12-15 13:26:49.814003000 +0100
11687 +++ linux.dev/arch/mips/pci/Makefile 2005-12-15 14:27:26.439319250 +0100
11688 @@ -18,6 +18,7 @@
11689 obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
11690 obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
11691 obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
11692 +obj-$(CONFIG_BCM947XX) += fixup-bcm47xx.o
11693
11694 #
11695 # These are still pretty much in the old state, watch, go blind.
11696 diff -urN linux.old/arch/mips/pci/fixup-bcm47xx.c linux.dev/arch/mips/pci/fixup-bcm47xx.c
11697 --- linux.old/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
11698 +++ linux.dev/arch/mips/pci/fixup-bcm47xx.c 2005-12-15 12:57:27.945158000 +0100
11699 @@ -0,0 +1,23 @@
11700 +#include <linux/init.h>
11701 +#include <linux/pci.h>
11702 +
11703 +/* Do platform specific device initialization at pci_enable_device() time */
11704 +int pcibios_plat_dev_init(struct pci_dev *dev)
11705 +{
11706 + return 0;
11707 +}
11708 +
11709 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11710 +{
11711 + u8 irq;
11712 +
11713 + if (dev->bus->number == 1)
11714 + return 2;
11715 +
11716 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11717 + return irq + 2;
11718 +}
11719 +
11720 +struct pci_fixup pcibios_fixups[] = {
11721 + { 0 }
11722 +};
11723 diff -urN linux.old/arch/mips/pci/pci.c linux.dev/arch/mips/pci/pci.c
11724 --- linux.old/arch/mips/pci/pci.c 2005-12-15 13:26:49.814003000 +0100
11725 +++ linux.dev/arch/mips/pci/pci.c 2005-12-17 18:08:13.553162000 +0100
11726 @@ -307,7 +307,8 @@
11727 if (res->flags & IORESOURCE_IO)
11728 offset = hose->io_offset;
11729 else if (res->flags & IORESOURCE_MEM)
11730 - offset = hose->mem_offset;
11731 +// offset = hose->mem_offset;
11732 + offset = 0x24000000;
11733
11734 res->start = region->start + offset;
11735 res->end = region->end + offset;
11736 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11737 --- linux.old/include/asm-mips/bootinfo.h 2005-12-15 13:26:49.818001250 +0100
11738 +++ linux.dev/include/asm-mips/bootinfo.h 2005-12-15 12:57:27.969147500 +0100
11739 @@ -218,6 +218,12 @@
11740 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11741 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11742
11743 +/*
11744 + * Valid machtype for group Broadcom
11745 + */
11746 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11747 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11748 +
11749 #define CL_SIZE COMMAND_LINE_SIZE
11750
11751 const char *get_system_type(void);
11752 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11753 --- linux.old/include/asm-mips/cpu.h 2005-12-15 13:26:49.818001250 +0100
11754 +++ linux.dev/include/asm-mips/cpu.h 2005-12-15 12:57:27.969147500 +0100
11755 @@ -102,6 +102,13 @@
11756 #define PRID_IMP_SR71000 0x0400
11757
11758 /*
11759 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11760 + */
11761 +
11762 +#define PRID_IMP_BCM4710 0x4000
11763 +#define PRID_IMP_BCM3302 0x9000
11764 +
11765 +/*
11766 * Definitions for 7:0 on legacy processors
11767 */
11768
11769 @@ -196,7 +203,9 @@
11770 #define CPU_34K 60
11771 #define CPU_PR4450 61
11772 #define CPU_SB1A 62
11773 -#define CPU_LAST 62
11774 +#define CPU_BCM3302 63
11775 +#define CPU_BCM4710 64
11776 +#define CPU_LAST 64
11777
11778 /*
11779 * ISA Level encodings
11780 diff -urN linux.old/include/linux/init.h linux.dev/include/linux/init.h
11781 --- linux.old/include/linux/init.h 2005-12-15 13:26:49.818001250 +0100
11782 +++ linux.dev/include/linux/init.h 2005-12-15 12:57:27.973145750 +0100
11783 @@ -86,6 +86,8 @@
11784 static initcall_t __initcall_##fn __attribute_used__ \
11785 __attribute__((__section__(".initcall" level ".init"))) = fn
11786
11787 +#define early_initcall(fn) __define_initcall(".early1",fn)
11788 +
11789 #define core_initcall(fn) __define_initcall("1",fn)
11790 #define postcore_initcall(fn) __define_initcall("2",fn)
11791 #define arch_initcall(fn) __define_initcall("3",fn)
11792 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11793 --- linux.old/include/linux/pci_ids.h 2005-12-15 13:26:49.818001250 +0100
11794 +++ linux.dev/include/linux/pci_ids.h 2005-12-15 12:57:27.977144000 +0100
11795 @@ -1835,6 +1835,7 @@
11796 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11797 #define PCI_DEVICE_ID_BCM4401 0x4401
11798 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11799 +#define PCI_DEVICE_ID_BCM4713 0x4713
11800
11801 #define PCI_VENDOR_ID_TOPIC 0x151f
11802 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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