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rtl8366_smi: move memset into the rtl8366s_get_member_config function
[openwrt.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 #ifdef DEBUG
213 struct dentry *debugfs_root;
214 #endif
215 };
216
217 #ifdef DEBUG
218 u16 g_dbg_reg;
219 #endif
220
221 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
222
223 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
224 {
225 ndelay(RTL8366_SMI_CLK_DELAY);
226 }
227
228 static void rtl8366_smi_start(struct rtl8366_smi *smi)
229 {
230 unsigned int sda = smi->pdata->gpio_sda;
231 unsigned int sck = smi->pdata->gpio_sck;
232
233 /*
234 * Set GPIO pins to output mode, with initial state:
235 * SCK = 0, SDA = 1
236 */
237 gpio_direction_output(sck, 0);
238 gpio_direction_output(sda, 1);
239 rtl8366_smi_clk_delay(smi);
240
241 /* CLK 1: 0 -> 1, 1 -> 0 */
242 gpio_set_value(sck, 1);
243 rtl8366_smi_clk_delay(smi);
244 gpio_set_value(sck, 0);
245 rtl8366_smi_clk_delay(smi);
246
247 /* CLK 2: */
248 gpio_set_value(sck, 1);
249 rtl8366_smi_clk_delay(smi);
250 gpio_set_value(sda, 0);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 1);
255 }
256
257 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
258 {
259 unsigned int sda = smi->pdata->gpio_sda;
260 unsigned int sck = smi->pdata->gpio_sck;
261
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sda, 0);
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 0);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
273
274 /* add a click */
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 0);
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 1);
279
280 /* set GPIO pins to input mode */
281 gpio_direction_input(sda);
282 gpio_direction_input(sck);
283 }
284
285 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
286 {
287 unsigned int sda = smi->pdata->gpio_sda;
288 unsigned int sck = smi->pdata->gpio_sck;
289
290 for (; len > 0; len--) {
291 rtl8366_smi_clk_delay(smi);
292
293 /* prepare data */
294 if ( data & ( 1 << (len - 1)) )
295 gpio_set_value(sda, 1);
296 else
297 gpio_set_value(sda, 0);
298 rtl8366_smi_clk_delay(smi);
299
300 /* clocking */
301 gpio_set_value(sck, 1);
302 rtl8366_smi_clk_delay(smi);
303 gpio_set_value(sck, 0);
304 }
305 }
306
307 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
308 {
309 unsigned int sda = smi->pdata->gpio_sda;
310 unsigned int sck = smi->pdata->gpio_sck;
311
312 gpio_direction_input(sda);
313
314 for (*data = 0; len > 0; len--) {
315 u32 u;
316
317 rtl8366_smi_clk_delay(smi);
318
319 /* clocking */
320 gpio_set_value(sck, 1);
321 rtl8366_smi_clk_delay(smi);
322 u = gpio_get_value(sda);
323 gpio_set_value(sck, 0);
324
325 *data |= (u << (len - 1));
326 }
327
328 gpio_direction_output(sda, 0);
329 }
330
331 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
332 {
333 int retry_cnt;
334
335 retry_cnt = 0;
336 do {
337 u32 ack;
338
339 rtl8366_smi_read_bits(smi, 1, &ack);
340 if (ack == 0)
341 break;
342
343 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
344 return -EIO;
345 } while (1);
346
347 return 0;
348 }
349
350 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
351 {
352 rtl8366_smi_write_bits(smi, data, 8);
353 return rtl8366_smi_wait_for_ack(smi);
354 }
355
356 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
357 {
358 u32 t;
359
360 /* read data */
361 rtl8366_smi_read_bits(smi, 8, &t);
362 *data = (t & 0xff);
363
364 /* send an ACK */
365 rtl8366_smi_write_bits(smi, 0x00, 1);
366
367 return 0;
368 }
369
370 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
371 {
372 u32 t;
373
374 /* read data */
375 rtl8366_smi_read_bits(smi, 8, &t);
376 *data = (t & 0xff);
377
378 /* send an ACK */
379 rtl8366_smi_write_bits(smi, 0x01, 1);
380
381 return 0;
382 }
383
384 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
385 {
386 unsigned long flags;
387 u8 lo = 0;
388 u8 hi = 0;
389 int ret;
390
391 spin_lock_irqsave(&smi->lock, flags);
392
393 rtl8366_smi_start(smi);
394
395 /* send READ command */
396 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
397 if (ret)
398 goto out;
399
400 /* set ADDR[7:0] */
401 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
402 if (ret)
403 goto out;
404
405 /* set ADDR[15:8] */
406 ret = rtl8366_smi_write_byte(smi, addr >> 8);
407 if (ret)
408 goto out;
409
410 /* read DATA[7:0] */
411 rtl8366_smi_read_byte0(smi, &lo);
412 /* read DATA[15:8] */
413 rtl8366_smi_read_byte1(smi, &hi);
414
415 *data = ((u32) lo) | (((u32) hi) << 8);
416
417 ret = 0;
418
419 out:
420 rtl8366_smi_stop(smi);
421 spin_unlock_irqrestore(&smi->lock, flags);
422
423 return ret;
424 }
425
426 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
427 {
428 unsigned long flags;
429 int ret;
430
431 spin_lock_irqsave(&smi->lock, flags);
432
433 rtl8366_smi_start(smi);
434
435 /* send WRITE command */
436 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
437 if (ret)
438 goto out;
439
440 /* set ADDR[7:0] */
441 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
442 if (ret)
443 goto out;
444
445 /* set ADDR[15:8] */
446 ret = rtl8366_smi_write_byte(smi, addr >> 8);
447 if (ret)
448 goto out;
449
450 /* write DATA[7:0] */
451 ret = rtl8366_smi_write_byte(smi, data & 0xff);
452 if (ret)
453 goto out;
454
455 /* write DATA[15:8] */
456 ret = rtl8366_smi_write_byte(smi, data >> 8);
457 if (ret)
458 goto out;
459
460 ret = 0;
461
462 out:
463 rtl8366_smi_stop(smi);
464 spin_unlock_irqrestore(&smi->lock, flags);
465
466 return ret;
467 }
468
469 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
470 u32 phy_no, u32 page, u32 addr, u32 *data)
471 {
472 u32 reg;
473 int ret;
474
475 if (phy_no > RTL8366S_PHY_NO_MAX)
476 return -EINVAL;
477
478 if (page > RTL8366S_PHY_PAGE_MAX)
479 return -EINVAL;
480
481 if (addr > RTL8366S_PHY_ADDR_MAX)
482 return -EINVAL;
483
484 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
485 RTL8366S_PHY_CTRL_READ);
486 if (ret)
487 return ret;
488
489 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
490 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
491 (addr & RTL8366S_PHY_REG_MASK);
492
493 ret = rtl8366_smi_write_reg(smi, reg, 0);
494 if (ret)
495 return ret;
496
497 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
498 if (ret)
499 return ret;
500
501 return 0;
502 }
503
504 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
505 u32 phy_no, u32 page, u32 addr, u32 data)
506 {
507 u32 reg;
508 int ret;
509
510 if (phy_no > RTL8366S_PHY_NO_MAX)
511 return -EINVAL;
512
513 if (page > RTL8366S_PHY_PAGE_MAX)
514 return -EINVAL;
515
516 if (addr > RTL8366S_PHY_ADDR_MAX)
517 return -EINVAL;
518
519 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
520 RTL8366S_PHY_CTRL_WRITE);
521 if (ret)
522 return ret;
523
524 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
525 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
526 (addr & RTL8366S_PHY_REG_MASK);
527
528 ret = rtl8366_smi_write_reg(smi, reg, data);
529 if (ret)
530 return ret;
531
532 return 0;
533 }
534
535 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
536 int port, unsigned long long *val)
537 {
538 int i;
539 int err;
540 u32 addr, data, regoffset;
541 u64 mibvalue;
542
543 /* address offset to MIBs counter */
544 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
545 2, 2, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 4, 2, 2, 2, 2, 2, 2,
547 2, 2, 2, 2, 2, 2};
548
549 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
550 return -EINVAL;
551
552 i = 0;
553 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
554
555 while (i < counter) {
556 regoffset += mibLength[i];
557 i++;
558 }
559
560 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
561
562
563 /* writing access counter address first */
564 /* then ASIC will prepare 64bits counter wait for being retrived */
565 data = 0;/* writing data will be discard by ASIC */
566 err = rtl8366_smi_write_reg(smi, addr, data);
567 if (err)
568 return err;
569
570 /* read MIB control register */
571 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
572 if (err)
573 return err;
574
575 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
576 return -EBUSY;
577
578 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
579 return -EIO;
580
581 mibvalue = 0;
582 addr = addr + mibLength[counter] - 1;
583 i = mibLength[counter];
584
585 while (i) {
586 err = rtl8366_smi_read_reg(smi, addr, &data);
587 if (err)
588 return err;
589
590 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
591
592 addr--;
593 i--;
594 }
595
596 *val = mibvalue;
597 return 0;
598 }
599
600 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
601 struct rtl8366s_vlan4kentry *vlan4k)
602 {
603 int err;
604 u32 data;
605 u16 *tableaddr;
606
607 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
608 vlan4k->vid = vid;
609
610 if (vid >= RTL8366_NUM_VIDS)
611 return -EINVAL;
612
613 tableaddr = (u16 *)vlan4k;
614
615 /* write VID */
616 data = *tableaddr;
617 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
618 if (err)
619 return err;
620
621 /* write table access control word */
622 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
623 RTL8366S_TABLE_VLAN_READ_CTRL);
624 if (err)
625 return err;
626
627 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
628 if (err)
629 return err;
630
631 *tableaddr = data;
632 tableaddr++;
633
634 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
635 &data);
636 if (err)
637 return err;
638
639 *tableaddr = data;
640 vlan4k->vid = vid;
641
642 return 0;
643 }
644
645 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
646 const struct rtl8366s_vlan4kentry *vlan4k)
647 {
648 int err;
649 u32 data;
650 u16 *tableaddr;
651
652 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
653 vlan4k->member > RTL8366_PORT_ALL ||
654 vlan4k->untag > RTL8366_PORT_ALL ||
655 vlan4k->fid > RTL8366S_FIDMAX)
656 return -EINVAL;
657
658 tableaddr = (u16 *)vlan4k;
659
660 data = *tableaddr;
661
662 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
663 if (err)
664 return err;
665
666 tableaddr++;
667
668 data = *tableaddr;
669
670 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
671
672
673 /* write table access control word */
674 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
675 RTL8366S_TABLE_VLAN_WRITE_CTRL);
676 if (err)
677 return err;
678
679 return 0;
680 }
681
682 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
683 struct rtl8366s_vlanconfig
684 *vlanmconf)
685 {
686 int err;
687 u32 addr;
688 u32 data;
689 u16 *tableaddr;
690
691 memset(vlanmconf, '\0', sizeof(struct rtl8366s_vlanconfig));
692
693 if (index >= RTL8366_NUM_VLANS)
694 return -EINVAL;
695
696 tableaddr = (u16 *)vlanmconf;
697
698 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
699
700 err = rtl8366_smi_read_reg(smi, addr, &data);
701 if (err)
702 return err;
703
704 *tableaddr = data;
705 tableaddr++;
706
707 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
708
709 err = rtl8366_smi_read_reg(smi, addr, &data);
710 if (err)
711 return err;
712
713 *tableaddr = data;
714
715 return 0;
716 }
717
718 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
719 const struct rtl8366s_vlanconfig
720 *vlanmconf)
721 {
722 int err;
723 u32 addr;
724 u32 data;
725 u16 *tableaddr;
726
727 if (index >= RTL8366_NUM_VLANS ||
728 vlanmconf->vid >= RTL8366_NUM_VIDS ||
729 vlanmconf->priority > RTL8366S_PRIORITYMAX ||
730 vlanmconf->member > RTL8366_PORT_ALL ||
731 vlanmconf->untag > RTL8366_PORT_ALL ||
732 vlanmconf->fid > RTL8366S_FIDMAX)
733 return -EINVAL;
734
735 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
736
737
738 tableaddr = (u16 *)vlanmconf;
739 data = *tableaddr;
740
741 err = rtl8366_smi_write_reg(smi, addr, data);
742 if (err)
743 return err;
744
745 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
746
747 tableaddr++;
748 data = *tableaddr;
749
750 err = rtl8366_smi_write_reg(smi, addr, data);
751 if (err)
752 return err;
753
754 return 0;
755 }
756
757 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
758 int *val)
759 {
760 int err;
761 u32 addr;
762 u32 data;
763
764 /* bits mapping to port vlan control register of port n */
765 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
766 0xF000, 0x000F, 0x00F0 };
767 /* bits offset to port vlan control register of port n */
768 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
769 /* address offset to port vlan control register of port n */
770 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
771
772 if (port >= RTL8366_NUM_PORTS)
773 return -EINVAL;
774
775 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
776
777 err = rtl8366_smi_read_reg(smi, addr, &data);
778 if (err)
779 return err;
780
781 *val = (data & bits[port]) >> bitoffset[port];
782
783 return 0;
784
785 }
786
787 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
788 int *val)
789 {
790 int err;
791 int index;
792 struct rtl8366s_vlanconfig vlanMC;
793
794 err = rtl8366_get_port_vlan_index(smi, port, &index);
795 if (err)
796 return err;
797
798 err = rtl8366s_get_vlan_member_config(smi, index, &vlanMC);
799 if (err)
800 return err;
801
802 *val = vlanMC.vid;
803 return 0;
804 }
805
806 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
807 int index)
808 {
809 int err;
810 u32 addr;
811 u32 data;
812 u32 vlan_data;
813 u32 bits;
814
815 /* bits mapping to port vlan control register of port n */
816 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
817 0xF000, 0x000F, 0x00F0 };
818 /* bits offset to port vlan control register of port n */
819 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
820 /* address offset to port vlan control register of port n */
821 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
822
823 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
824 return -EINVAL;
825
826 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
827
828 bits = bitmasks[port];
829
830 data = (index << bitOff[port]) & bits;
831
832 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
833 if (err)
834 return err;
835
836 vlan_data &= ~(vlan_data & bits);
837 vlan_data |= data;
838
839 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
840 if (err)
841 return err;
842
843 return 0;
844 }
845
846 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
847 int val)
848 {
849 int i;
850 struct rtl8366s_vlanconfig vlanMC;
851 struct rtl8366s_vlan4kentry vlan4K;
852
853 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
854 return -EINVAL;
855
856
857
858 /* Updating the 4K entry; lookup it and change the port member set */
859 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4K);
860 vlan4K.member |= ((1 << port) | RTL8366_PORT_CPU);
861 vlan4K.untag = RTL8366_PORT_ALL_BUT_CPU;
862 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
863
864 /* For the 16 entries more work needs to be done. First see if such
865 VID is already there and change it */
866 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
867 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
868
869 /* Try to find an existing vid and update port member set */
870 if (val == vlanMC.vid) {
871 vlanMC.member |= ((1 << port) | RTL8366_PORT_CPU);
872 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
873
874 /* Now update PVID register settings */
875 rtl8366_set_port_vlan_index(smi, port, i);
876
877 return 0;
878 }
879 }
880
881 /* PVID could not be found from vlan table. Replace unused (one that
882 has no member ports) with new one */
883 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
884 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
885
886 /* See if this vlan member configuration is unused. It is
887 unused if member set contains no ports or CPU port only */
888 if (!vlanMC.member || vlanMC.member == RTL8366_PORT_CPU) {
889 vlanMC.vid = val;
890 vlanMC.priority = 0;
891 vlanMC.untag = RTL8366_PORT_ALL_BUT_CPU;
892 vlanMC.member = ((1 << port) | RTL8366_PORT_CPU);
893 vlanMC.fid = 0;
894
895 rtl8366s_set_vlan_member_config(smi, i, &vlanMC);
896
897 /* Now update PVID register settings */
898 rtl8366_set_port_vlan_index(smi, port, i);
899
900 return 0;
901 }
902 }
903
904 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
905 "use\n");
906 return -EINVAL;
907 }
908
909
910 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
911 {
912 u32 data = 0;
913 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
914
915 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
916 if (enable)
917 data |= RTL8366_CHIP_CTRL_VLAN;
918
919 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
920 }
921
922 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
923 {
924 u32 data = 0;
925 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
926
927 data &= ~(data & 1);
928 if (enable)
929 data |= 1;
930
931 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
932 }
933
934 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
935 {
936 int i;
937 struct rtl8366s_vlan4kentry vlan4K;
938 struct rtl8366s_vlanconfig vlanMC;
939
940 /* clear 16 VLAN member configuration */
941 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
942 vlanMC.vid = 0;
943 vlanMC.priority = 0;
944 vlanMC.member = 0;
945 vlanMC.untag = 0;
946 vlanMC.fid = 0;
947 if (rtl8366s_set_vlan_member_config(smi, i, &vlanMC) != 0)
948 return -EIO;
949 }
950
951 /* Set a default VLAN with vid 1 to 4K table for all ports */
952 vlan4K.vid = 1;
953 vlan4K.member = RTL8366_PORT_ALL;
954 vlan4K.untag = RTL8366_PORT_ALL;
955 vlan4K.fid = 0;
956 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4K) != 0)
957 return -EIO;
958
959 /* Set all ports PVID to default VLAN */
960 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
961 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
962 return -EIO;
963 }
964
965 return 0;
966 }
967
968 #ifdef DEBUG
969 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
970 {
971 file->private_data = inode->i_private;
972 return 0;
973 }
974
975 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
976 char __user *user_buf,
977 size_t count, loff_t *ppos)
978 {
979 char buf[4096];
980 int i, j, len = 0;
981 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
982
983 len += snprintf(buf + len, sizeof(buf) - len, "MIB Counters:\n");
984 len += snprintf(buf + len, sizeof(buf) - len, "Counter"
985 " "
986 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
987 "Port 4\n");
988
989 for (i = 0; i < 33; ++i) {
990
991 len += snprintf(buf + len, sizeof(buf) - len, "%d:%s ",
992 i, MIBCOUNTERS[i]);
993 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
994 unsigned long long counter = 0;
995
996 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
997 len += snprintf(buf + len, sizeof(buf) - len,
998 "[%llu]", counter);
999 else
1000 len += snprintf(buf + len, sizeof(buf) - len,
1001 "[error]");
1002
1003 if (j != RTL8366_NUM_PORTS - 1) {
1004 if (counter < 100000)
1005 len += snprintf(buf + len,
1006 sizeof(buf) - len,
1007 "\t");
1008
1009 len += snprintf(buf + len, sizeof(buf) - len,
1010 "\t");
1011 }
1012 }
1013 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1014 }
1015
1016 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1017
1018 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1019 }
1020
1021 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1022 char __user *user_buf,
1023 size_t count, loff_t *ppos)
1024 {
1025 char buf[4096];
1026 int i, j, len = 0;
1027 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1028
1029 len += snprintf(buf + len, sizeof(buf) - len, "VLAN Member Config:\n");
1030 len += snprintf(buf + len, sizeof(buf) - len,
1031 "\t id \t vid \t prio \t member \t untag \t fid "
1032 "\tports\n");
1033
1034 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1035 struct rtl8366s_vlanconfig vlanMC;
1036
1037 rtl8366s_get_vlan_member_config(smi, i, &vlanMC);
1038
1039 len += snprintf(buf + len, sizeof(buf) - len,
1040 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1041 "\t", i, vlanMC.vid, vlanMC.priority,
1042 vlanMC.member, vlanMC.untag, vlanMC.fid);
1043
1044 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1045 int index = 0;
1046 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1047 if (index == i)
1048 len += snprintf(buf + len,
1049 sizeof(buf) - len,
1050 "%d", j);
1051 }
1052 }
1053 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1054 }
1055
1056 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1057 }
1058
1059 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1060 char __user *user_buf,
1061 size_t count, loff_t *ppos)
1062 {
1063 u32 t, reg = g_dbg_reg;
1064 int err, len = 0;
1065 char buf[512];
1066 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1067
1068 memset(buf, '\0', sizeof(buf));
1069
1070 err = rtl8366_smi_read_reg(smi, reg, &t);
1071 if (err) {
1072 len += snprintf(buf, sizeof(buf),
1073 "Read failed (reg: 0x%04x)\n", reg);
1074 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1075 }
1076
1077 len += snprintf(buf, sizeof(buf), "reg = 0x%04x, val = 0x%04x\n",
1078 reg, t);
1079
1080 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1081 }
1082
1083 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1084 const char __user *user_buf,
1085 size_t count, loff_t *ppos)
1086 {
1087 unsigned long data;
1088 u32 reg = g_dbg_reg;
1089 int err;
1090 char buf[50];
1091 size_t len;
1092 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1093
1094 len = min(count, sizeof(buf) - 1);
1095 if (copy_from_user(buf, user_buf, len)) {
1096 dev_err(&smi->pdev->dev, "copy from user failed\n");
1097 return -EFAULT;
1098 }
1099
1100 buf[len] = '\0';
1101 if (len > 0 && buf[len - 1] == '\n')
1102 buf[len - 1] = '\0';
1103
1104
1105 if (strict_strtoul(buf, 16, &data)) {
1106 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1107 } else {
1108 err = rtl8366_smi_write_reg(smi, reg, data);
1109 if (err) {
1110 dev_err(&smi->pdev->dev,
1111 "writing reg 0x%04x val 0x%04lx failed\n",
1112 reg, data);
1113 }
1114 }
1115
1116 return count;
1117 }
1118
1119 static const struct file_operations fops_rtl8366_regs = {
1120 .read = rtl8366_read_debugfs_reg,
1121 .write = rtl8366_write_debugfs_reg,
1122 .open = rtl8366_debugfs_open,
1123 .owner = THIS_MODULE
1124 };
1125
1126 static const struct file_operations fops_rtl8366_vlan = {
1127 .read = rtl8366_read_debugfs_vlan,
1128 .open = rtl8366_debugfs_open,
1129 .owner = THIS_MODULE
1130 };
1131
1132 static const struct file_operations fops_rtl8366_mibs = {
1133 .read = rtl8366_read_debugfs_mibs,
1134 .open = rtl8366_debugfs_open,
1135 .owner = THIS_MODULE
1136 };
1137
1138 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1139 {
1140 struct dentry *node;
1141 struct dentry *root;
1142
1143 if (!smi->debugfs_root)
1144 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1145
1146 if (!smi->debugfs_root) {
1147 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1148 return;
1149 }
1150 root = smi->debugfs_root;
1151
1152 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1153 if (!node) {
1154 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1155 return;
1156 }
1157
1158 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1159 &fops_rtl8366_regs);
1160 if (!node) {
1161 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1162 return;
1163 }
1164
1165 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1166 &fops_rtl8366_vlan);
1167 if (!node) {
1168 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1169 "failed\n");
1170 return;
1171 }
1172
1173 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1174 &fops_rtl8366_mibs);
1175 if (!node) {
1176 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1177 "xfailed\n");
1178 return;
1179 }
1180 }
1181
1182 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1183 {
1184 if (smi->debugfs_root) {
1185 debugfs_remove_recursive(smi->debugfs_root);
1186 smi->debugfs_root = NULL;
1187 }
1188 }
1189
1190 #else
1191 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1192 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1193 #endif
1194
1195 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1196 const struct switch_attr *attr,
1197 struct switch_val *val)
1198 {
1199 u32 data = 0;
1200 struct rtl8366_smi *smi = to_rtl8366(dev);
1201
1202 if (val->value.i == 1) {
1203 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1204 data |= (1 << 2);
1205 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1206 }
1207
1208 return 0;
1209 }
1210
1211 static int rtl8366_get_vlan(struct switch_dev *dev,
1212 const struct switch_attr *attr,
1213 struct switch_val *val)
1214 {
1215 u32 data;
1216 struct rtl8366_smi *smi = to_rtl8366(dev);
1217
1218 if (attr->ofs == 1) {
1219 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1220
1221 if (data & RTL8366_CHIP_CTRL_VLAN)
1222 val->value.i = 1;
1223 else
1224 val->value.i = 0;
1225 } else if (attr->ofs == 2) {
1226 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1227
1228 if (data & 0x0001)
1229 val->value.i = 1;
1230 else
1231 val->value.i = 0;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1240 {
1241 u32 data;
1242 struct rtl8366_smi *smi = to_rtl8366(dev);
1243 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1244
1245 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1246
1247 return 0;
1248 }
1249
1250 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1251 const struct switch_attr *attr,
1252 struct switch_val *val)
1253 {
1254 u32 data;
1255 struct rtl8366_smi *smi = to_rtl8366(dev);
1256
1257 if (val->value.i >= 6)
1258 return -EINVAL;
1259
1260 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1261
1262 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1263 data |= val->value.i;
1264
1265 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1266
1267 return 0;
1268 }
1269
1270 static int rtl8366_set_vlan(struct switch_dev *dev,
1271 const struct switch_attr *attr,
1272 struct switch_val *val)
1273 {
1274 struct rtl8366_smi *smi = to_rtl8366(dev);
1275
1276 if (attr->ofs == 1)
1277 return rtl8366_vlan_set_vlan(smi, val->value.i);
1278 else
1279 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1280 }
1281
1282 static int rtl8366_init_vlan(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 struct rtl8366_smi *smi = to_rtl8366(dev);
1287 return rtl8366s_reset_vlan(smi);
1288 }
1289
1290 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1291 const struct switch_attr *attr,
1292 struct switch_val *val)
1293 {
1294 char buf[1024];
1295 u32 len = 0, data = 0;
1296 int speed, duplex, link, txpause, rxpause, nway;
1297 struct rtl8366_smi *smi = to_rtl8366(dev);
1298
1299 if (val->port_vlan >= RTL8366_NUM_PORTS)
1300 return -EINVAL;
1301
1302 memset(buf, '\0', sizeof(buf));
1303 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1304 (val->port_vlan >> 1),
1305 &data);
1306
1307 if (val->port_vlan & 0x1)
1308 data = data >> 8;
1309
1310 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1311 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1312 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1313 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1314 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1315 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1316
1317 len += snprintf(buf + len, sizeof(buf) - len, "Port %d: ",
1318 val->port_vlan);
1319
1320 if (link)
1321 len += snprintf(buf + len, sizeof(buf) - len,
1322 "Link UP, Speed: ");
1323 else
1324 len += snprintf(buf + len, sizeof(buf) - len,
1325 "Link DOWN, Speed: ");
1326
1327 if (speed == 0)
1328 len += snprintf(buf + len, sizeof(buf) - len, "10Base-TX ");
1329 else if (speed == 1)
1330 len += snprintf(buf + len, sizeof(buf) - len, "100Base-TX ");
1331 else if (speed == 2)
1332 len += snprintf(buf + len, sizeof(buf) - len, "1000Base-TX ");
1333
1334 if (duplex)
1335 len += snprintf(buf + len, sizeof(buf) - len, "Full-Duplex, ");
1336 else
1337 len += snprintf(buf + len, sizeof(buf) - len, "Half-Duplex, ");
1338
1339 if (txpause)
1340 len += snprintf(buf + len, sizeof(buf) - len, "TX-Pause ");
1341 if (rxpause)
1342 len += snprintf(buf + len, sizeof(buf) - len, "RX-Pause ");
1343 if (nway)
1344 len += snprintf(buf + len, sizeof(buf) - len, "nway ");
1345
1346 val->value.s = buf;
1347 val->len = len;
1348
1349 return 0;
1350 }
1351
1352 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1353 const struct switch_attr *attr,
1354 struct switch_val *val)
1355 {
1356 int i;
1357 char buf[1024];
1358 u32 len = 0;
1359 struct rtl8366s_vlanconfig vlanMC;
1360 struct rtl8366s_vlan4kentry vlan4K;
1361 struct rtl8366_smi *smi = to_rtl8366(dev);
1362
1363 if (val->port_vlan >= RTL8366_NUM_PORTS)
1364 return -EINVAL;
1365
1366 memset(buf, '\0', sizeof(buf));
1367
1368 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1369 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1370
1371 len += snprintf(buf + len, sizeof(buf) - len, "VLAN %d: Ports: ",
1372 val->port_vlan);
1373
1374 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1375 int index = 0;
1376 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1377 index == val->port_vlan)
1378 len += snprintf(buf + len, sizeof(buf) - len, "%d", i);
1379 }
1380 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1381
1382 len += snprintf(buf + len, sizeof(buf) - len,
1383 "\t\t vid \t prio \t member \t untag \t fid\n");
1384 len += snprintf(buf + len, sizeof(buf) - len, "\tMC:\t");
1385 len += snprintf(buf + len, sizeof(buf) - len,
1386 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1387 vlanMC.vid, vlanMC.priority, vlanMC.member,
1388 vlanMC.untag, vlanMC.fid);
1389 len += snprintf(buf + len, sizeof(buf) - len, "\t4K:\t");
1390 len += snprintf(buf + len, sizeof(buf) - len,
1391 "%d \t \t 0x%04x \t 0x%04x \t %d",
1392 vlan4K.vid, vlan4K.member, vlan4K.untag, vlan4K.fid);
1393
1394 val->value.s = buf;
1395 val->len = len;
1396
1397 return 0;
1398 }
1399
1400 static int rtl8366_set_port_led(struct switch_dev *dev,
1401 const struct switch_attr *attr,
1402 struct switch_val *val)
1403 {
1404 u32 data = 0;
1405 struct rtl8366_smi *smi = to_rtl8366(dev);
1406 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1407 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1408 return -EINVAL;
1409
1410 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1411 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1412 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1413 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1414 } else {
1415 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1416 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1417 (val->value.i << (val->port_vlan * 4));
1418 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1419 }
1420
1421 return 0;
1422 }
1423
1424 static int rtl8366_get_port_led(struct switch_dev *dev,
1425 const struct switch_attr *attr,
1426 struct switch_val *val)
1427 {
1428 u32 data = 0;
1429 struct rtl8366_smi *smi = to_rtl8366(dev);
1430 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1431 return -EINVAL;
1432
1433 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1434 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1435
1436 return 0;
1437 }
1438
1439 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1440 const struct switch_attr *attr,
1441 struct switch_val *val)
1442 {
1443 u32 data = 0;
1444 struct rtl8366_smi *smi = to_rtl8366(dev);
1445 if (val->port_vlan >= RTL8366_NUM_PORTS)
1446 return -EINVAL;
1447
1448 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1449 data |= (1 << (val->port_vlan + 3));
1450 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1451
1452 return 0;
1453 }
1454
1455 static int rtl8366_get_port_mib(struct switch_dev *dev,
1456 const struct switch_attr *attr,
1457 struct switch_val *val)
1458 {
1459 char buf[2048];
1460 int i, len = 0;
1461 unsigned long long counter = 0;
1462 struct rtl8366_smi *smi = to_rtl8366(dev);
1463 if (val->port_vlan >= RTL8366_NUM_PORTS)
1464 return -EINVAL;
1465
1466 len += snprintf(buf + len, sizeof(buf) - len, "Port %d MIB counters\n",
1467 val->port_vlan);
1468 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1469
1470 len += snprintf(buf + len, sizeof(buf) - len,
1471 "%d:%s\t", i, MIBCOUNTERS[i]);
1472 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1473 len += snprintf(buf + len, sizeof(buf) - len,
1474 "[%llu]\n", counter);
1475 else
1476 len += snprintf(buf + len, sizeof(buf) - len,
1477 "[error]\n");
1478 }
1479
1480 val->value.s = buf;
1481 val->len = len;
1482 return 0;
1483 }
1484
1485 static int rtl8366_set_member(struct switch_dev *dev,
1486 const struct switch_attr *attr,
1487 struct switch_val *val)
1488 {
1489 struct rtl8366s_vlanconfig vlanMC;
1490 struct rtl8366s_vlan4kentry vlan4K;
1491 struct rtl8366_smi *smi = to_rtl8366(dev);
1492
1493 if (val->port_vlan >= RTL8366_NUM_VLANS)
1494 return -EINVAL;
1495
1496 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1497
1498 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1499
1500 vlan4K.member = vlanMC.member = val->value.i;
1501 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1502 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1503
1504 return 0;
1505 }
1506
1507 static int rtl8366_get_member(struct switch_dev *dev,
1508 const struct switch_attr *attr,
1509 struct switch_val *val)
1510 {
1511 struct rtl8366s_vlanconfig vlanMC;
1512 struct rtl8366s_vlan4kentry vlan4K;
1513 struct rtl8366_smi *smi = to_rtl8366(dev);
1514
1515 if (val->port_vlan >= RTL8366_NUM_VLANS)
1516 return -EINVAL;
1517
1518 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1519
1520 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1521
1522 val->value.i = vlanMC.member;
1523
1524 return 0;
1525 }
1526
1527 static int rtl8366_set_untag(struct switch_dev *dev,
1528 const struct switch_attr *attr,
1529 struct switch_val *val)
1530 {
1531 struct rtl8366s_vlanconfig vlanMC;
1532 struct rtl8366s_vlan4kentry vlan4K;
1533 struct rtl8366_smi *smi = to_rtl8366(dev);
1534
1535 if (val->port_vlan >= RTL8366_NUM_VLANS)
1536 return -EINVAL;
1537
1538 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1539 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1540
1541 vlan4K.untag = vlanMC.untag = val->value.i;
1542 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanMC);
1543 rtl8366s_set_vlan_4k_entry(smi, &vlan4K);
1544
1545 return 0;
1546 }
1547
1548 static int rtl8366_get_untag(struct switch_dev *dev,
1549 const struct switch_attr *attr,
1550 struct switch_val *val)
1551 {
1552 struct rtl8366s_vlanconfig vlanMC;
1553 struct rtl8366s_vlan4kentry vlan4K;
1554 struct rtl8366_smi *smi = to_rtl8366(dev);
1555
1556 if (val->port_vlan >= RTL8366_NUM_VLANS)
1557 return -EINVAL;
1558
1559 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanMC);
1560 rtl8366s_get_vlan_4k_entry(smi, vlanMC.vid, &vlan4K);
1561
1562
1563 val->value.i = vlanMC.untag;
1564
1565 return 0;
1566 }
1567
1568 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1569 {
1570 struct rtl8366_smi *smi = to_rtl8366(dev);
1571 return rtl8366_get_vlan_port_pvid(smi, port, val);
1572 }
1573
1574 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1575 {
1576 struct rtl8366_smi *smi = to_rtl8366(dev);
1577 return rtl8366_set_vlan_port_pvid(smi, port, val);
1578 }
1579
1580 static int rtl8366_reset_switch(struct switch_dev *dev)
1581 {
1582 struct rtl8366_smi *smi = to_rtl8366(dev);
1583 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1584 RTL8366_CHIP_CTRL_RESET_HW);
1585 return 0;
1586 }
1587
1588 static struct switch_attr rtl8366_globals[] = {
1589 {
1590 .type = SWITCH_TYPE_INT,
1591 .name = "enable_vlan",
1592 .description = "Enable VLAN mode",
1593 .set = rtl8366_set_vlan,
1594 .get = rtl8366_get_vlan,
1595 .max = 1,
1596 .ofs = 1
1597 },
1598 {
1599 .type = SWITCH_TYPE_INT,
1600 .name = "enable_vlan4k",
1601 .description = "Enable VLAN 4K mode",
1602 .set = rtl8366_set_vlan,
1603 .get = rtl8366_get_vlan,
1604 .max = 1,
1605 .ofs = 2
1606 },
1607 {
1608 .type = SWITCH_TYPE_INT,
1609 .name = "init_vlan",
1610 .description = "Initialize VLAN tables to defaults",
1611 .set = rtl8366_init_vlan,
1612 .get = NULL,
1613 .max = 1
1614 },
1615
1616 {
1617 .type = SWITCH_TYPE_INT,
1618 .name = "reset_mibs",
1619 .description = "Reset all MIB counters",
1620 .set = rtl8366_global_reset_mibs,
1621 .get = NULL,
1622 .max = 1
1623 },
1624 {
1625 .type = SWITCH_TYPE_INT,
1626 .name = "blinkrate",
1627 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1628 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1629 .set = rtl8366_global_set_blinkrate,
1630 .get = rtl8366_global_get_blinkrate,
1631 .max = 5
1632 },
1633 };
1634
1635 static struct switch_attr rtl8366_port[] = {
1636 {
1637 .type = SWITCH_TYPE_STRING,
1638 .name = "link",
1639 .description = "Get port link information",
1640 .max = 1,
1641 .set = NULL,
1642 .get = rtl8366_attr_get_port_link
1643 },
1644 {
1645 .type = SWITCH_TYPE_INT,
1646 .name = "reset_mib",
1647 .description = "Reset single port MIB counters",
1648 .max = 1,
1649 .set = rtl8366_reset_port_mibs,
1650 .get = NULL
1651 },
1652 {
1653 .type = SWITCH_TYPE_STRING,
1654 .name = "mib",
1655 .description = "Get MIB counters for port",
1656 .max = 33,
1657 .set = NULL,
1658 .get = rtl8366_get_port_mib
1659 },
1660 {
1661 .type = SWITCH_TYPE_INT,
1662 .name = "led",
1663 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1664 .max = 15,
1665 .set = rtl8366_set_port_led,
1666 .get = rtl8366_get_port_led
1667 },
1668 };
1669
1670 static struct switch_attr rtl8366_vlan[] = {
1671 {
1672 .type = SWITCH_TYPE_INT,
1673 .name = "untag",
1674 .description = "Get/Set VLAN untag port set (bitmask)",
1675 .set = rtl8366_set_untag,
1676 .get = rtl8366_get_untag,
1677 .max = 63,
1678 },
1679 {
1680 .type = SWITCH_TYPE_INT,
1681 .name = "member",
1682 .description = "Get/Set VLAN member port set (bitmask)",
1683 .set = rtl8366_set_member,
1684 .get = rtl8366_get_member,
1685 .max = 63,
1686 },
1687 {
1688 .type = SWITCH_TYPE_STRING,
1689 .name = "info",
1690 .description = "Get vlan information",
1691 .max = 1,
1692 .set = NULL,
1693 .get = rtl8366_attr_get_vlan_info
1694 },
1695 };
1696
1697
1698 /* template */
1699 static struct switch_dev rtldev = {
1700 .name = "RTL8366S",
1701 .cpu_port = RTL8366_PORT_NUM_CPU,
1702 .ports = RTL8366_NUM_PORTS,
1703 .vlans = RTL8366_NUM_VLANS,
1704 .attr_global = {
1705 .attr = rtl8366_globals,
1706 .n_attr = ARRAY_SIZE(rtl8366_globals),
1707 },
1708 .attr_port = {
1709 .attr = rtl8366_port,
1710 .n_attr = ARRAY_SIZE(rtl8366_port),
1711 },
1712 .attr_vlan = {
1713 .attr = rtl8366_vlan,
1714 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1715 },
1716
1717 .get_port_pvid = rtl8366_get_port_pvid,
1718 .set_port_pvid = rtl8366_set_port_pvid,
1719 .reset_switch = rtl8366_reset_switch,
1720 };
1721
1722 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1723 {
1724 struct rtl8366_smi *smi = bus->priv;
1725 u32 val = 0;
1726 int err;
1727
1728 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1729 if (err)
1730 return 0xffff;
1731
1732 return val;
1733 }
1734
1735 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1736 u16 val)
1737 {
1738 struct rtl8366_smi *smi = bus->priv;
1739 u32 t;
1740 int err;
1741
1742 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1743 /* flush write */
1744 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1745
1746 return err;
1747 }
1748
1749 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1750 {
1751 int ret;
1752 int i;
1753
1754 smi->mii_bus = mdiobus_alloc();
1755 if (smi->mii_bus == NULL) {
1756 ret = -ENOMEM;
1757 goto err;
1758 }
1759
1760 spin_lock_init(&smi->lock);
1761 smi->mii_bus->priv = (void *) smi;
1762 smi->mii_bus->name = "rtl8366-smi";
1763 smi->mii_bus->read = rtl8366_smi_mii_read;
1764 smi->mii_bus->write = rtl8366_smi_mii_write;
1765 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1766 dev_name(&smi->pdev->dev));
1767 smi->mii_bus->parent = &smi->pdev->dev;
1768 smi->mii_bus->phy_mask = ~(0x1f);
1769 smi->mii_bus->irq = smi->mii_irq;
1770 for (i = 0; i < PHY_MAX_ADDR; i++)
1771 smi->mii_irq[i] = PHY_POLL;
1772
1773 ret = mdiobus_register(smi->mii_bus);
1774 if (ret)
1775 goto err_free;
1776
1777 return 0;
1778
1779 err_free:
1780 mdiobus_free(smi->mii_bus);
1781 err:
1782 return ret;
1783 }
1784
1785 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1786 {
1787 mdiobus_unregister(smi->mii_bus);
1788 mdiobus_free(smi->mii_bus);
1789 }
1790
1791 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1792 {
1793 u32 chip_id = 0;
1794 u32 chip_ver = 0;
1795 int ret;
1796
1797 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1798 if (ret) {
1799 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1800 return ret;
1801 }
1802
1803 switch (chip_id) {
1804 case RTL8366S_CHIP_ID_8366:
1805 break;
1806 default:
1807 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1808 return -ENODEV;
1809 }
1810
1811 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1812 &chip_ver);
1813 if (ret) {
1814 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1815 return ret;
1816 }
1817
1818 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1819 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1820
1821 rtl8366_debugfs_init(smi);
1822
1823 return 0;
1824 }
1825
1826 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1827 {
1828 static int rtl8366_smi_version_printed;
1829 struct rtl8366_smi_platform_data *pdata;
1830 struct rtl8366_smi *smi;
1831 int err;
1832
1833 if (!rtl8366_smi_version_printed++)
1834 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1835 " version " RTL8366_SMI_DRIVER_VER"\n");
1836
1837 pdata = pdev->dev.platform_data;
1838 if (!pdata) {
1839 dev_err(&pdev->dev, "no platform data specified\n");
1840 err = -EINVAL;
1841 goto err_out;
1842 }
1843
1844 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1845 if (!smi) {
1846 dev_err(&pdev->dev, "no memory for private data\n");
1847 err = -ENOMEM;
1848 goto err_out;
1849 }
1850
1851 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1852 if (err) {
1853 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1854 pdata->gpio_sda, err);
1855 goto err_free_smi;
1856 }
1857
1858 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1859 if (err) {
1860 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1861 pdata->gpio_sck, err);
1862 goto err_free_sda;
1863 }
1864
1865 smi->pdev = pdev;
1866 smi->pdata = pdata;
1867 spin_lock_init(&smi->lock);
1868
1869 platform_set_drvdata(pdev, smi);
1870
1871 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1872 pdata->gpio_sda, pdata->gpio_sck);
1873
1874 err = rtl8366_smi_setup(smi);
1875 if (err)
1876 goto err_clear_drvdata;
1877
1878 err = rtl8366_smi_mii_init(smi);
1879 if (err)
1880 goto err_clear_drvdata;
1881
1882 return 0;
1883
1884 err_clear_drvdata:
1885 platform_set_drvdata(pdev, NULL);
1886 gpio_free(pdata->gpio_sck);
1887 err_free_sda:
1888 gpio_free(pdata->gpio_sda);
1889 err_free_smi:
1890 kfree(smi);
1891 err_out:
1892 return err;
1893 }
1894
1895 int rtl8366_phy_config_init(struct phy_device *phydev)
1896 {
1897 int err;
1898 struct net_device *netdev = phydev->attached_dev;
1899 struct rtl8366_smi *smi = phydev->bus->priv;
1900 struct switch_dev *dev = &smi->dev;
1901
1902 /* Only init the switch for the primary PHY */
1903 if (phydev->addr != 4) {
1904 printk(KERN_INFO "Discarding address: %d\n", phydev->addr);
1905 return 0;
1906 }
1907
1908 memcpy(&smi->dev, &rtldev, sizeof(struct switch_dev));
1909 dev->priv = smi;
1910 dev->netdev = netdev;
1911
1912 err = register_switch(dev, netdev);
1913 if (err < 0) {
1914 printk(KERN_INFO "Switch registration failed\n");
1915 return err;
1916 }
1917
1918 return 0;
1919 }
1920
1921 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1922 {
1923 return 0;
1924 }
1925
1926 static struct phy_driver rtl8366_smi_phy_driver = {
1927 .phy_id = 0x001cc960,
1928 .name = "Realtek RTL8366",
1929 .phy_id_mask = 0x1ffffff0,
1930 .features = PHY_GBIT_FEATURES,
1931 .config_aneg = rtl8366_phy_config_aneg,
1932 .config_init = rtl8366_phy_config_init,
1933 .read_status = genphy_read_status,
1934 .driver = {
1935 .owner = THIS_MODULE,
1936 },
1937 };
1938
1939 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1940 {
1941 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1942
1943 if (smi) {
1944 struct rtl8366_smi_platform_data *pdata;
1945
1946 pdata = pdev->dev.platform_data;
1947
1948 rtl8366_debugfs_remove(smi);
1949 phy_driver_unregister(&rtl8366_smi_phy_driver);
1950 rtl8366_smi_mii_cleanup(smi);
1951 platform_set_drvdata(pdev, NULL);
1952 gpio_free(pdata->gpio_sck);
1953 gpio_free(pdata->gpio_sda);
1954 kfree(smi);
1955 }
1956
1957 return 0;
1958 }
1959
1960 static struct platform_driver rtl8366_smi_driver = {
1961 .driver = {
1962 .name = RTL8366_SMI_DRIVER_NAME,
1963 .owner = THIS_MODULE,
1964 },
1965 .probe = rtl8366_smi_probe,
1966 .remove = __devexit_p(rtl8366_smi_remove),
1967 };
1968
1969 static int __init rtl8366_smi_init(void)
1970 {
1971 int ret;
1972 ret = platform_driver_register(&rtl8366_smi_driver);
1973 if (ret)
1974 return ret;
1975
1976 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1977 if (ret)
1978 goto err_platform_unregister;
1979
1980 return 0;
1981
1982 err_platform_unregister:
1983 platform_driver_unregister(&rtl8366_smi_driver);
1984 return ret;
1985 }
1986 module_init(rtl8366_smi_init);
1987
1988 static void __exit rtl8366_smi_exit(void)
1989 {
1990 phy_driver_unregister(&rtl8366_smi_phy_driver);
1991 platform_driver_unregister(&rtl8366_smi_driver);
1992 }
1993 module_exit(rtl8366_smi_exit);
1994
1995 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1996 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1997 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1998 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1999 MODULE_LICENSE("GPL v2");
2000 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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