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[ixp4xx] enable switch support on Compex boards
[openwrt.git] / target / linux / ixp4xx / patches-2.6.24 / 200-npe_driver.patch
1 diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
2 index f9cc2b6..9274d3f 100644
3 --- a/drivers/net/arm/Kconfig
4 +++ b/drivers/net/arm/Kconfig
5 @@ -47,3 +47,13 @@ config EP93XX_ETH
6 help
7 This is a driver for the ethernet hardware included in EP93xx CPUs.
8 Say Y if you are building a kernel for EP93xx based devices.
9 +
10 +config IXP4XX_ETH
11 + tristate "IXP4xx Ethernet support"
12 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
13 + select IXP4XX_NPE
14 + select IXP4XX_QMGR
15 + select MII
16 + help
17 + Say Y here if you want to use built-in Ethernet ports
18 + on IXP4xx processor.
19 diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
20 index a4c8682..7c812ac 100644
21 --- a/drivers/net/arm/Makefile
22 +++ b/drivers/net/arm/Makefile
23 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
24 obj-$(CONFIG_ARM_ETHER1) += ether1.o
25 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
26 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
27 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
28 diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
29 new file mode 100644
30 index 0000000..98131a7
31 --- /dev/null
32 +++ b/drivers/net/arm/ixp4xx_eth.c
33 @@ -0,0 +1,1261 @@
34 +/*
35 + * Intel IXP4xx Ethernet driver for Linux
36 + *
37 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
38 + *
39 + * This program is free software; you can redistribute it and/or modify it
40 + * under the terms of version 2 of the GNU General Public License
41 + * as published by the Free Software Foundation.
42 + *
43 + * Ethernet port config (0x00 is not present on IXP42X):
44 + *
45 + * logical port 0x00 0x10 0x20
46 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
47 + * physical PortId 2 0 1
48 + * TX queue 23 24 25
49 + * RX-free queue 26 27 28
50 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
51 + *
52 + *
53 + * Queue entries:
54 + * bits 0 -> 1 - NPE ID (RX and TX-done)
55 + * bits 0 -> 2 - priority (TX, per 802.1D)
56 + * bits 3 -> 4 - port ID (user-set?)
57 + * bits 5 -> 31 - physical descriptor address
58 + */
59 +
60 +#include <linux/delay.h>
61 +#include <linux/dma-mapping.h>
62 +#include <linux/dmapool.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/io.h>
65 +#include <linux/kernel.h>
66 +#include <linux/mii.h>
67 +#include <linux/platform_device.h>
68 +#include <asm/arch/npe.h>
69 +#include <asm/arch/qmgr.h>
70 +
71 +#define DEBUG_QUEUES 0
72 +#define DEBUG_DESC 0
73 +#define DEBUG_RX 0
74 +#define DEBUG_TX 0
75 +#define DEBUG_PKT_BYTES 0
76 +#define DEBUG_MDIO 0
77 +#define DEBUG_CLOSE 0
78 +
79 +#define DRV_NAME "ixp4xx_eth"
80 +
81 +#define MAX_NPES 3
82 +
83 +#define RX_DESCS 64 /* also length of all RX queues */
84 +#define TX_DESCS 16 /* also length of all TX queues */
85 +#define TXDONE_QUEUE_LEN 64 /* dwords */
86 +
87 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
88 +#define REGS_SIZE 0x1000
89 +#define MAX_MRU 1536 /* 0x600 */
90 +
91 +#define MDIO_INTERVAL (3 * HZ)
92 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
93 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
94 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
95 +
96 +#define NPE_ID(port_id) ((port_id) >> 4)
97 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
98 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
99 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
100 +#define TXDONE_QUEUE 31
101 +
102 +#define ETH_NAPI_WEIGHT 16
103 +
104 +/* TX Control Registers */
105 +#define TX_CNTRL0_TX_EN 0x01
106 +#define TX_CNTRL0_HALFDUPLEX 0x02
107 +#define TX_CNTRL0_RETRY 0x04
108 +#define TX_CNTRL0_PAD_EN 0x08
109 +#define TX_CNTRL0_APPEND_FCS 0x10
110 +#define TX_CNTRL0_2DEFER 0x20
111 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
112 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
113 +
114 +/* RX Control Registers */
115 +#define RX_CNTRL0_RX_EN 0x01
116 +#define RX_CNTRL0_PADSTRIP_EN 0x02
117 +#define RX_CNTRL0_SEND_FCS 0x04
118 +#define RX_CNTRL0_PAUSE_EN 0x08
119 +#define RX_CNTRL0_LOOP_EN 0x10
120 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
121 +#define RX_CNTRL0_RX_RUNT_EN 0x40
122 +#define RX_CNTRL0_BCAST_DIS 0x80
123 +#define RX_CNTRL1_DEFER_EN 0x01
124 +
125 +/* Core Control Register */
126 +#define CORE_RESET 0x01
127 +#define CORE_RX_FIFO_FLUSH 0x02
128 +#define CORE_TX_FIFO_FLUSH 0x04
129 +#define CORE_SEND_JAM 0x08
130 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
131 +
132 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
133 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
134 + TX_CNTRL0_2DEFER)
135 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
136 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
137 +
138 +
139 +/* NPE message codes */
140 +#define NPE_GETSTATUS 0x00
141 +#define NPE_EDB_SETPORTADDRESS 0x01
142 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
143 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
144 +#define NPE_GETSTATS 0x04
145 +#define NPE_RESETSTATS 0x05
146 +#define NPE_SETMAXFRAMELENGTHS 0x06
147 +#define NPE_VLAN_SETRXTAGMODE 0x07
148 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
149 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
150 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
151 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
152 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
153 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
154 +#define NPE_FW_SETFIREWALLMODE 0x0E
155 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
156 +#define NPE_PC_SETAPMACTABLE 0x11
157 +#define NPE_SETLOOPBACK_MODE 0x12
158 +#define NPE_PC_SETBSSIDTABLE 0x13
159 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
160 +#define NPE_APPENDFCSCONFIG 0x15
161 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
162 +#define NPE_MAC_RECOVERY_START 0x17
163 +
164 +
165 +#ifdef __ARMEB__
166 +typedef struct sk_buff buffer_t;
167 +#define free_buffer dev_kfree_skb
168 +#define free_buffer_irq dev_kfree_skb_irq
169 +#else
170 +typedef void buffer_t;
171 +#define free_buffer kfree
172 +#define free_buffer_irq kfree
173 +#endif
174 +
175 +struct eth_regs {
176 + u32 tx_control[2], __res1[2]; /* 000 */
177 + u32 rx_control[2], __res2[2]; /* 010 */
178 + u32 random_seed, __res3[3]; /* 020 */
179 + u32 partial_empty_threshold, __res4; /* 030 */
180 + u32 partial_full_threshold, __res5; /* 038 */
181 + u32 tx_start_bytes, __res6[3]; /* 040 */
182 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
183 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
184 + u32 slot_time, __res9[3]; /* 070 */
185 + u32 mdio_command[4]; /* 080 */
186 + u32 mdio_status[4]; /* 090 */
187 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
188 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
189 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
190 + u32 hw_addr[6], __res13[61]; /* 0F0 */
191 + u32 core_control; /* 1FC */
192 +};
193 +
194 +struct port {
195 + struct resource *mem_res;
196 + struct eth_regs __iomem *regs;
197 + struct npe *npe;
198 + struct net_device *netdev;
199 + struct napi_struct napi;
200 + struct net_device_stats stat;
201 + struct mii_if_info mii;
202 + struct delayed_work mdio_thread;
203 + struct eth_plat_info *plat;
204 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
205 + struct desc *desc_tab; /* coherent */
206 + u32 desc_tab_phys;
207 + int id; /* logical port ID */
208 + u16 mii_bmcr;
209 +};
210 +
211 +/* NPE message structure */
212 +struct msg {
213 +#ifdef __ARMEB__
214 + u8 cmd, eth_id, byte2, byte3;
215 + u8 byte4, byte5, byte6, byte7;
216 +#else
217 + u8 byte3, byte2, eth_id, cmd;
218 + u8 byte7, byte6, byte5, byte4;
219 +#endif
220 +};
221 +
222 +/* Ethernet packet descriptor */
223 +struct desc {
224 + u32 next; /* pointer to next buffer, unused */
225 +
226 +#ifdef __ARMEB__
227 + u16 buf_len; /* buffer length */
228 + u16 pkt_len; /* packet length */
229 + u32 data; /* pointer to data buffer in RAM */
230 + u8 dest_id;
231 + u8 src_id;
232 + u16 flags;
233 + u8 qos;
234 + u8 padlen;
235 + u16 vlan_tci;
236 +#else
237 + u16 pkt_len; /* packet length */
238 + u16 buf_len; /* buffer length */
239 + u32 data; /* pointer to data buffer in RAM */
240 + u16 flags;
241 + u8 src_id;
242 + u8 dest_id;
243 + u16 vlan_tci;
244 + u8 padlen;
245 + u8 qos;
246 +#endif
247 +
248 +#ifdef __ARMEB__
249 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
250 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
251 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
252 +#else
253 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
254 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
255 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
256 +#endif
257 +};
258 +
259 +
260 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
261 + (n) * sizeof(struct desc))
262 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
263 +
264 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
265 + ((n) + RX_DESCS) * sizeof(struct desc))
266 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
267 +
268 +#ifndef __ARMEB__
269 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
270 +{
271 + int i;
272 + for (i = 0; i < cnt; i++)
273 + dest[i] = swab32(src[i]);
274 +}
275 +#endif
276 +
277 +static spinlock_t mdio_lock;
278 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
279 +static int ports_open;
280 +static struct port *npe_port_tab[MAX_NPES];
281 +static struct dma_pool *dma_pool;
282 +
283 +
284 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
285 + int write, u16 cmd)
286 +{
287 + int cycles = 0;
288 +
289 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
290 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
291 + return 0;
292 + }
293 +
294 + if (write) {
295 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
296 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
297 + }
298 + __raw_writel(((phy_id << 5) | location) & 0xFF,
299 + &mdio_regs->mdio_command[2]);
300 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
301 + &mdio_regs->mdio_command[3]);
302 +
303 + while ((cycles < MAX_MDIO_RETRIES) &&
304 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
305 + udelay(1);
306 + cycles++;
307 + }
308 +
309 + if (cycles == MAX_MDIO_RETRIES) {
310 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
311 + return 0;
312 + }
313 +
314 +#if DEBUG_MDIO
315 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
316 + cycles);
317 +#endif
318 +
319 + if (write)
320 + return 0;
321 +
322 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
323 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
324 + return 0;
325 + }
326 +
327 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
328 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
329 +}
330 +
331 +static int mdio_read(struct net_device *dev, int phy_id, int location)
332 +{
333 + unsigned long flags;
334 + u16 val;
335 +
336 + spin_lock_irqsave(&mdio_lock, flags);
337 + val = mdio_cmd(dev, phy_id, location, 0, 0);
338 + spin_unlock_irqrestore(&mdio_lock, flags);
339 + return val;
340 +}
341 +
342 +static void mdio_write(struct net_device *dev, int phy_id, int location,
343 + int val)
344 +{
345 + unsigned long flags;
346 +
347 + spin_lock_irqsave(&mdio_lock, flags);
348 + mdio_cmd(dev, phy_id, location, 1, val);
349 + spin_unlock_irqrestore(&mdio_lock, flags);
350 +}
351 +
352 +static void phy_reset(struct net_device *dev, int phy_id)
353 +{
354 + struct port *port = netdev_priv(dev);
355 + int cycles = 0;
356 +
357 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
358 +
359 + while (cycles < MAX_MII_RESET_RETRIES) {
360 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
361 +#if DEBUG_MDIO
362 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
363 + dev->name, cycles);
364 +#endif
365 + return;
366 + }
367 + udelay(1);
368 + cycles++;
369 + }
370 +
371 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
372 +}
373 +
374 +static void eth_set_duplex(struct port *port)
375 +{
376 + if (port->mii.full_duplex)
377 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
378 + &port->regs->tx_control[0]);
379 + else
380 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
381 + &port->regs->tx_control[0]);
382 +}
383 +
384 +
385 +static void phy_check_media(struct port *port, int init)
386 +{
387 + if (mii_check_media(&port->mii, 1, init))
388 + eth_set_duplex(port);
389 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
390 + struct net_device *dev = port->netdev;
391 + int cur_link = mii_link_ok(&port->mii);
392 + int prev_link = netif_carrier_ok(dev);
393 +
394 + if (!prev_link && cur_link) {
395 + printk(KERN_INFO "%s: link up\n", dev->name);
396 + netif_carrier_on(dev);
397 + } else if (prev_link && !cur_link) {
398 + printk(KERN_INFO "%s: link down\n", dev->name);
399 + netif_carrier_off(dev);
400 + }
401 + }
402 +}
403 +
404 +
405 +static void mdio_thread(struct work_struct *work)
406 +{
407 + struct port *port = container_of(work, struct port, mdio_thread.work);
408 +
409 + phy_check_media(port, 0);
410 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
411 +}
412 +
413 +
414 +static inline void debug_pkt(struct net_device *dev, const char *func,
415 + u8 *data, int len)
416 +{
417 +#if DEBUG_PKT_BYTES
418 + int i;
419 +
420 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
421 + for (i = 0; i < len; i++) {
422 + if (i >= DEBUG_PKT_BYTES)
423 + break;
424 + printk("%s%02X",
425 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
426 + data[i]);
427 + }
428 + printk("\n");
429 +#endif
430 +}
431 +
432 +
433 +static inline void debug_desc(u32 phys, struct desc *desc)
434 +{
435 +#if DEBUG_DESC
436 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
437 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
438 + phys, desc->next, desc->buf_len, desc->pkt_len,
439 + desc->data, desc->dest_id, desc->src_id, desc->flags,
440 + desc->qos, desc->padlen, desc->vlan_tci,
441 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
442 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
443 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
444 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
445 +#endif
446 +}
447 +
448 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
449 +{
450 +#if DEBUG_QUEUES
451 + static struct {
452 + int queue;
453 + char *name;
454 + } names[] = {
455 + { TX_QUEUE(0x10), "TX#0 " },
456 + { TX_QUEUE(0x20), "TX#1 " },
457 + { TX_QUEUE(0x00), "TX#2 " },
458 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
459 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
460 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
461 + { TXDONE_QUEUE, "TX-done " },
462 + };
463 + int i;
464 +
465 + for (i = 0; i < ARRAY_SIZE(names); i++)
466 + if (names[i].queue == queue)
467 + break;
468 +
469 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
470 + i < ARRAY_SIZE(names) ? names[i].name : "",
471 + is_get ? "->" : "<-", phys);
472 +#endif
473 +}
474 +
475 +static inline u32 queue_get_entry(unsigned int queue)
476 +{
477 + u32 phys = qmgr_get_entry(queue);
478 + debug_queue(queue, 1, phys);
479 + return phys;
480 +}
481 +
482 +static inline int queue_get_desc(unsigned int queue, struct port *port,
483 + int is_tx)
484 +{
485 + u32 phys, tab_phys, n_desc;
486 + struct desc *tab;
487 +
488 + if (!(phys = queue_get_entry(queue)))
489 + return -1;
490 +
491 + phys &= ~0x1F; /* mask out non-address bits */
492 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
493 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
494 + n_desc = (phys - tab_phys) / sizeof(struct desc);
495 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
496 + debug_desc(phys, &tab[n_desc]);
497 + BUG_ON(tab[n_desc].next);
498 + return n_desc;
499 +}
500 +
501 +static inline void queue_put_desc(unsigned int queue, u32 phys,
502 + struct desc *desc)
503 +{
504 + debug_queue(queue, 0, phys);
505 + debug_desc(phys, desc);
506 + BUG_ON(phys & 0x1F);
507 + qmgr_put_entry(queue, phys);
508 + BUG_ON(qmgr_stat_overflow(queue));
509 +}
510 +
511 +
512 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
513 +{
514 +#ifdef __ARMEB__
515 + dma_unmap_single(&port->netdev->dev, desc->data,
516 + desc->buf_len, DMA_TO_DEVICE);
517 +#else
518 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
519 + ALIGN((desc->data & 3) + desc->buf_len, 4),
520 + DMA_TO_DEVICE);
521 +#endif
522 +}
523 +
524 +
525 +static void eth_rx_irq(void *pdev)
526 +{
527 + struct net_device *dev = pdev;
528 + struct port *port = netdev_priv(dev);
529 +
530 +#if DEBUG_RX
531 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
532 +#endif
533 + qmgr_disable_irq(port->plat->rxq);
534 + netif_rx_schedule(dev, &port->napi);
535 +}
536 +
537 +static int eth_poll(struct napi_struct *napi, int budget)
538 +{
539 + struct port *port = container_of(napi, struct port, napi);
540 + struct net_device *dev = port->netdev;
541 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
542 + int received = 0;
543 +
544 +#if DEBUG_RX
545 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
546 +#endif
547 +
548 + while (received < budget) {
549 + struct sk_buff *skb;
550 + struct desc *desc;
551 + int n;
552 +#ifdef __ARMEB__
553 + struct sk_buff *temp;
554 + u32 phys;
555 +#endif
556 +
557 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
558 + received = 0; /* No packet received */
559 +#if DEBUG_RX
560 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
561 + dev->name);
562 +#endif
563 + netif_rx_complete(dev, &port->napi);
564 + qmgr_enable_irq(rxq);
565 + if (!qmgr_stat_empty(rxq) &&
566 + netif_rx_reschedule(dev, &port->napi)) {
567 +#if DEBUG_RX
568 + printk(KERN_DEBUG "%s: eth_poll"
569 + " netif_rx_reschedule successed\n",
570 + dev->name);
571 +#endif
572 + qmgr_disable_irq(rxq);
573 + continue;
574 + }
575 +#if DEBUG_RX
576 + printk(KERN_DEBUG "%s: eth_poll all done\n",
577 + dev->name);
578 +#endif
579 + return 0; /* all work done */
580 + }
581 +
582 + desc = rx_desc_ptr(port, n);
583 +
584 +#ifdef __ARMEB__
585 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
586 + phys = dma_map_single(&dev->dev, skb->data,
587 + MAX_MRU, DMA_FROM_DEVICE);
588 + if (dma_mapping_error(phys)) {
589 + dev_kfree_skb(skb);
590 + skb = NULL;
591 + }
592 + }
593 +#else
594 + skb = netdev_alloc_skb(dev, desc->pkt_len);
595 +#endif
596 +
597 + if (!skb) {
598 + port->stat.rx_dropped++;
599 + /* put the desc back on RX-ready queue */
600 + desc->buf_len = MAX_MRU;
601 + desc->pkt_len = 0;
602 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
603 + continue;
604 + }
605 +
606 + /* process received frame */
607 +#ifdef __ARMEB__
608 + temp = skb;
609 + skb = port->rx_buff_tab[n];
610 + dma_unmap_single(&dev->dev, desc->data,
611 + MAX_MRU, DMA_FROM_DEVICE);
612 +#else
613 + dma_sync_single(&dev->dev, desc->data,
614 + MAX_MRU, DMA_FROM_DEVICE);
615 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
616 + ALIGN(desc->pkt_len, 4) / 4);
617 +#endif
618 + skb_put(skb, desc->pkt_len);
619 +
620 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
621 +
622 + skb->protocol = eth_type_trans(skb, dev);
623 + dev->last_rx = jiffies;
624 + port->stat.rx_packets++;
625 + port->stat.rx_bytes += skb->len;
626 + netif_receive_skb(skb);
627 +
628 + /* put the new buffer on RX-free queue */
629 +#ifdef __ARMEB__
630 + port->rx_buff_tab[n] = temp;
631 + desc->data = phys;
632 +#endif
633 + desc->buf_len = MAX_MRU;
634 + desc->pkt_len = 0;
635 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
636 + received++;
637 + }
638 +
639 +#if DEBUG_RX
640 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
641 +#endif
642 + return received; /* not all work done */
643 +}
644 +
645 +
646 +static void eth_txdone_irq(void *unused)
647 +{
648 + u32 phys;
649 +
650 +#if DEBUG_TX
651 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
652 +#endif
653 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
654 + u32 npe_id, n_desc;
655 + struct port *port;
656 + struct desc *desc;
657 + int start;
658 +
659 + npe_id = phys & 3;
660 + BUG_ON(npe_id >= MAX_NPES);
661 + port = npe_port_tab[npe_id];
662 + BUG_ON(!port);
663 + phys &= ~0x1F; /* mask out non-address bits */
664 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
665 + BUG_ON(n_desc >= TX_DESCS);
666 + desc = tx_desc_ptr(port, n_desc);
667 + debug_desc(phys, desc);
668 +
669 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
670 + port->stat.tx_packets++;
671 + port->stat.tx_bytes += desc->pkt_len;
672 +
673 + dma_unmap_tx(port, desc);
674 +#if DEBUG_TX
675 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
676 + port->netdev->name, port->tx_buff_tab[n_desc]);
677 +#endif
678 + free_buffer_irq(port->tx_buff_tab[n_desc]);
679 + port->tx_buff_tab[n_desc] = NULL;
680 + }
681 +
682 + start = qmgr_stat_empty(port->plat->txreadyq);
683 + queue_put_desc(port->plat->txreadyq, phys, desc);
684 + if (start) {
685 +#if DEBUG_TX
686 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
687 + port->netdev->name);
688 +#endif
689 + netif_wake_queue(port->netdev);
690 + }
691 + }
692 +}
693 +
694 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
695 +{
696 + struct port *port = netdev_priv(dev);
697 + unsigned int txreadyq = port->plat->txreadyq;
698 + int len, offset, bytes, n;
699 + void *mem;
700 + u32 phys;
701 + struct desc *desc;
702 +
703 +#if DEBUG_TX
704 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
705 +#endif
706 +
707 + if (unlikely(skb->len > MAX_MRU)) {
708 + dev_kfree_skb(skb);
709 + port->stat.tx_errors++;
710 + return NETDEV_TX_OK;
711 + }
712 +
713 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
714 +
715 + len = skb->len;
716 +#ifdef __ARMEB__
717 + offset = 0; /* no need to keep alignment */
718 + bytes = len;
719 + mem = skb->data;
720 +#else
721 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
722 + bytes = ALIGN(offset + len, 4);
723 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
724 + dev_kfree_skb(skb);
725 + port->stat.tx_dropped++;
726 + return NETDEV_TX_OK;
727 + }
728 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
729 + dev_kfree_skb(skb);
730 +#endif
731 +
732 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
733 + if (dma_mapping_error(phys)) {
734 +#ifdef __ARMEB__
735 + dev_kfree_skb(skb);
736 +#else
737 + kfree(mem);
738 +#endif
739 + port->stat.tx_dropped++;
740 + return NETDEV_TX_OK;
741 + }
742 +
743 + n = queue_get_desc(txreadyq, port, 1);
744 + BUG_ON(n < 0);
745 + desc = tx_desc_ptr(port, n);
746 +
747 +#ifdef __ARMEB__
748 + port->tx_buff_tab[n] = skb;
749 +#else
750 + port->tx_buff_tab[n] = mem;
751 +#endif
752 + desc->data = phys + offset;
753 + desc->buf_len = desc->pkt_len = len;
754 +
755 + /* NPE firmware pads short frames with zeros internally */
756 + wmb();
757 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
758 + dev->trans_start = jiffies;
759 +
760 + if (qmgr_stat_empty(txreadyq)) {
761 +#if DEBUG_TX
762 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
763 +#endif
764 + netif_stop_queue(dev);
765 + /* we could miss TX ready interrupt */
766 + if (!qmgr_stat_empty(txreadyq)) {
767 +#if DEBUG_TX
768 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
769 + dev->name);
770 +#endif
771 + netif_wake_queue(dev);
772 + }
773 + }
774 +
775 +#if DEBUG_TX
776 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
777 +#endif
778 + return NETDEV_TX_OK;
779 +}
780 +
781 +
782 +static struct net_device_stats *eth_stats(struct net_device *dev)
783 +{
784 + struct port *port = netdev_priv(dev);
785 + return &port->stat;
786 +}
787 +
788 +static void eth_set_mcast_list(struct net_device *dev)
789 +{
790 + struct port *port = netdev_priv(dev);
791 + struct dev_mc_list *mclist = dev->mc_list;
792 + u8 diffs[ETH_ALEN], *addr;
793 + int cnt = dev->mc_count, i;
794 +
795 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
796 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
797 + &port->regs->rx_control[0]);
798 + return;
799 + }
800 +
801 + memset(diffs, 0, ETH_ALEN);
802 + addr = mclist->dmi_addr; /* first MAC address */
803 +
804 + while (--cnt && (mclist = mclist->next))
805 + for (i = 0; i < ETH_ALEN; i++)
806 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
807 +
808 + for (i = 0; i < ETH_ALEN; i++) {
809 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
810 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
811 + }
812 +
813 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
814 + &port->regs->rx_control[0]);
815 +}
816 +
817 +
818 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
819 +{
820 + struct port *port = netdev_priv(dev);
821 + unsigned int duplex_chg;
822 + int err;
823 +
824 + if (!netif_running(dev))
825 + return -EINVAL;
826 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
827 + if (duplex_chg)
828 + eth_set_duplex(port);
829 + return err;
830 +}
831 +
832 +
833 +static int request_queues(struct port *port)
834 +{
835 + int err;
836 +
837 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
838 + if (err)
839 + return err;
840 +
841 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
842 + if (err)
843 + goto rel_rxfree;
844 +
845 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
846 + if (err)
847 + goto rel_rx;
848 +
849 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
850 + if (err)
851 + goto rel_tx;
852 +
853 + /* TX-done queue handles skbs sent out by the NPEs */
854 + if (!ports_open) {
855 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
856 + if (err)
857 + goto rel_txready;
858 + }
859 + return 0;
860 +
861 +rel_txready:
862 + qmgr_release_queue(port->plat->txreadyq);
863 +rel_tx:
864 + qmgr_release_queue(TX_QUEUE(port->id));
865 +rel_rx:
866 + qmgr_release_queue(port->plat->rxq);
867 +rel_rxfree:
868 + qmgr_release_queue(RXFREE_QUEUE(port->id));
869 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
870 + port->netdev->name);
871 + return err;
872 +}
873 +
874 +static void release_queues(struct port *port)
875 +{
876 + qmgr_release_queue(RXFREE_QUEUE(port->id));
877 + qmgr_release_queue(port->plat->rxq);
878 + qmgr_release_queue(TX_QUEUE(port->id));
879 + qmgr_release_queue(port->plat->txreadyq);
880 +
881 + if (!ports_open)
882 + qmgr_release_queue(TXDONE_QUEUE);
883 +}
884 +
885 +static int init_queues(struct port *port)
886 +{
887 + int i;
888 +
889 + if (!ports_open)
890 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
891 + POOL_ALLOC_SIZE, 32, 0)))
892 + return -ENOMEM;
893 +
894 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
895 + &port->desc_tab_phys)))
896 + return -ENOMEM;
897 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
898 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
899 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
900 +
901 + /* Setup RX buffers */
902 + for (i = 0; i < RX_DESCS; i++) {
903 + struct desc *desc = rx_desc_ptr(port, i);
904 + buffer_t *buff;
905 + void *data;
906 +#ifdef __ARMEB__
907 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
908 + return -ENOMEM;
909 + data = buff->data;
910 +#else
911 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
912 + return -ENOMEM;
913 + data = buff;
914 +#endif
915 + desc->buf_len = MAX_MRU;
916 + desc->data = dma_map_single(&port->netdev->dev, data,
917 + MAX_MRU, DMA_FROM_DEVICE);
918 + if (dma_mapping_error(desc->data)) {
919 + free_buffer(buff);
920 + return -EIO;
921 + }
922 + port->rx_buff_tab[i] = buff;
923 + }
924 +
925 + return 0;
926 +}
927 +
928 +static void destroy_queues(struct port *port)
929 +{
930 + int i;
931 +
932 + if (port->desc_tab) {
933 + for (i = 0; i < RX_DESCS; i++) {
934 + struct desc *desc = rx_desc_ptr(port, i);
935 + buffer_t *buff = port->rx_buff_tab[i];
936 + if (buff) {
937 + dma_unmap_single(&port->netdev->dev,
938 + desc->data, MAX_MRU,
939 + DMA_FROM_DEVICE);
940 + free_buffer(buff);
941 + }
942 + }
943 + for (i = 0; i < TX_DESCS; i++) {
944 + struct desc *desc = tx_desc_ptr(port, i);
945 + buffer_t *buff = port->tx_buff_tab[i];
946 + if (buff) {
947 + dma_unmap_tx(port, desc);
948 + free_buffer(buff);
949 + }
950 + }
951 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
952 + port->desc_tab = NULL;
953 + }
954 +
955 + if (!ports_open && dma_pool) {
956 + dma_pool_destroy(dma_pool);
957 + dma_pool = NULL;
958 + }
959 +}
960 +
961 +static int eth_open(struct net_device *dev)
962 +{
963 + struct port *port = netdev_priv(dev);
964 + struct npe *npe = port->npe;
965 + struct msg msg;
966 + int i, err;
967 +
968 + if (!npe_running(npe)) {
969 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
970 + if (err)
971 + return err;
972 +
973 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
974 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
975 + npe_name(npe));
976 + return -EIO;
977 + }
978 + }
979 +
980 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
981 +
982 + memset(&msg, 0, sizeof(msg));
983 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
984 + msg.eth_id = port->id;
985 + msg.byte5 = port->plat->rxq | 0x80;
986 + msg.byte7 = port->plat->rxq << 4;
987 + for (i = 0; i < 8; i++) {
988 + msg.byte3 = i;
989 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
990 + return -EIO;
991 + }
992 +
993 + msg.cmd = NPE_EDB_SETPORTADDRESS;
994 + msg.eth_id = PHYSICAL_ID(port->id);
995 + msg.byte2 = dev->dev_addr[0];
996 + msg.byte3 = dev->dev_addr[1];
997 + msg.byte4 = dev->dev_addr[2];
998 + msg.byte5 = dev->dev_addr[3];
999 + msg.byte6 = dev->dev_addr[4];
1000 + msg.byte7 = dev->dev_addr[5];
1001 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1002 + return -EIO;
1003 +
1004 + memset(&msg, 0, sizeof(msg));
1005 + msg.cmd = NPE_FW_SETFIREWALLMODE;
1006 + msg.eth_id = port->id;
1007 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1008 + return -EIO;
1009 +
1010 + if ((err = request_queues(port)) != 0)
1011 + return err;
1012 +
1013 + if ((err = init_queues(port)) != 0) {
1014 + destroy_queues(port);
1015 + release_queues(port);
1016 + return err;
1017 + }
1018 +
1019 + for (i = 0; i < ETH_ALEN; i++)
1020 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1021 + __raw_writel(0x08, &port->regs->random_seed);
1022 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
1023 + __raw_writel(0x30, &port->regs->partial_full_threshold);
1024 + __raw_writel(0x08, &port->regs->tx_start_bytes);
1025 + __raw_writel(0x15, &port->regs->tx_deferral);
1026 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1027 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1028 + __raw_writel(0x80, &port->regs->slot_time);
1029 + __raw_writel(0x01, &port->regs->int_clock_threshold);
1030 +
1031 + /* Populate queues with buffers, no failure after this point */
1032 + for (i = 0; i < TX_DESCS; i++)
1033 + queue_put_desc(port->plat->txreadyq,
1034 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
1035 +
1036 + for (i = 0; i < RX_DESCS; i++)
1037 + queue_put_desc(RXFREE_QUEUE(port->id),
1038 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
1039 +
1040 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1041 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1042 + __raw_writel(0, &port->regs->rx_control[1]);
1043 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1044 +
1045 + napi_enable(&port->napi); /* check location of this call */
1046 +
1047 + phy_check_media(port, 1);
1048 + eth_set_mcast_list(dev);
1049 + netif_start_queue(dev);
1050 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1051 +
1052 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1053 + eth_rx_irq, dev);
1054 + if (!ports_open) {
1055 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1056 + eth_txdone_irq, NULL);
1057 + qmgr_enable_irq(TXDONE_QUEUE);
1058 + }
1059 + ports_open++;
1060 + netif_rx_schedule(dev, &port->napi); /* we may already have RX data, enables IRQ */
1061 + return 0;
1062 +}
1063 +
1064 +static int eth_close(struct net_device *dev)
1065 +{
1066 + struct port *port = netdev_priv(dev);
1067 + struct msg msg;
1068 + int buffs = RX_DESCS; /* allocated RX buffers */
1069 + int i;
1070 +
1071 + ports_open--;
1072 + qmgr_disable_irq(port->plat->rxq);
1073 + netif_stop_queue(dev);
1074 +
1075 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1076 + buffs--;
1077 +
1078 + memset(&msg, 0, sizeof(msg));
1079 + msg.cmd = NPE_SETLOOPBACK_MODE;
1080 + msg.eth_id = port->id;
1081 + msg.byte3 = 1;
1082 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1083 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1084 +
1085 + i = 0;
1086 + do { /* drain RX buffers */
1087 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1088 + buffs--;
1089 + if (!buffs)
1090 + break;
1091 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1092 + /* we have to inject some packet */
1093 + struct desc *desc;
1094 + u32 phys;
1095 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
1096 + BUG_ON(n < 0);
1097 + desc = tx_desc_ptr(port, n);
1098 + phys = tx_desc_phys(port, n);
1099 + desc->buf_len = desc->pkt_len = 1;
1100 + wmb();
1101 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
1102 + }
1103 + udelay(1);
1104 + } while (++i < MAX_CLOSE_WAIT);
1105 +
1106 + if (buffs)
1107 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1108 + " left in NPE\n", dev->name, buffs);
1109 +#if DEBUG_CLOSE
1110 + if (!buffs)
1111 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1112 +#endif
1113 +
1114 + buffs = TX_DESCS;
1115 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1116 + buffs--; /* cancel TX */
1117 +
1118 + i = 0;
1119 + do {
1120 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1121 + buffs--;
1122 + if (!buffs)
1123 + break;
1124 + } while (++i < MAX_CLOSE_WAIT);
1125 +
1126 + if (buffs)
1127 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1128 + "left in NPE\n", dev->name, buffs);
1129 +#if DEBUG_CLOSE
1130 + if (!buffs)
1131 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1132 +#endif
1133 +
1134 + msg.byte3 = 0;
1135 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1136 + printk(KERN_CRIT "%s: unable to disable loopback\n",
1137 + dev->name);
1138 +
1139 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
1140 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1141 + mdio_write(dev, port->plat->phy, MII_BMCR,
1142 + port->mii_bmcr | BMCR_PDOWN);
1143 +
1144 + if (!ports_open)
1145 + qmgr_disable_irq(TXDONE_QUEUE);
1146 + cancel_rearming_delayed_work(&port->mdio_thread);
1147 + napi_disable(&port->napi);
1148 + destroy_queues(port);
1149 + release_queues(port);
1150 + return 0;
1151 +}
1152 +
1153 +static int __devinit eth_init_one(struct platform_device *pdev)
1154 +{
1155 + struct port *port;
1156 + struct net_device *dev;
1157 + struct eth_plat_info *plat = pdev->dev.platform_data;
1158 + u32 regs_phys;
1159 + int err;
1160 +
1161 + if (!(dev = alloc_etherdev(sizeof(struct port))))
1162 + return -ENOMEM;
1163 +
1164 + SET_NETDEV_DEV(dev, &pdev->dev);
1165 + port = netdev_priv(dev);
1166 + port->netdev = dev;
1167 + port->id = pdev->id;
1168 +
1169 + switch (port->id) {
1170 + case IXP4XX_ETH_NPEA:
1171 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1172 + regs_phys = IXP4XX_EthA_BASE_PHYS;
1173 + break;
1174 + case IXP4XX_ETH_NPEB:
1175 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1176 + regs_phys = IXP4XX_EthB_BASE_PHYS;
1177 + break;
1178 + case IXP4XX_ETH_NPEC:
1179 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1180 + regs_phys = IXP4XX_EthC_BASE_PHYS;
1181 + break;
1182 + default:
1183 + err = -ENOSYS;
1184 + goto err_free;
1185 + }
1186 +
1187 + dev->open = eth_open;
1188 + dev->hard_start_xmit = eth_xmit;
1189 + dev->stop = eth_close;
1190 + dev->get_stats = eth_stats;
1191 + dev->do_ioctl = eth_ioctl;
1192 + dev->set_multicast_list = eth_set_mcast_list;
1193 + dev->tx_queue_len = 100;
1194 +
1195 + netif_napi_add(dev, &port->napi, eth_poll, ETH_NAPI_WEIGHT);
1196 +
1197 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1198 + err = -EIO;
1199 + goto err_free;
1200 + }
1201 +
1202 + if (register_netdev(dev)) {
1203 + err = -EIO;
1204 + goto err_npe_rel;
1205 + }
1206 +
1207 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1208 + if (!port->mem_res) {
1209 + err = -EBUSY;
1210 + goto err_unreg;
1211 + }
1212 +
1213 + port->plat = plat;
1214 + npe_port_tab[NPE_ID(port->id)] = port;
1215 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1216 +
1217 + platform_set_drvdata(pdev, dev);
1218 +
1219 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1220 + &port->regs->core_control);
1221 + udelay(50);
1222 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1223 + udelay(50);
1224 +
1225 + port->mii.dev = dev;
1226 + port->mii.mdio_read = mdio_read;
1227 + port->mii.mdio_write = mdio_write;
1228 + port->mii.phy_id = plat->phy;
1229 + port->mii.phy_id_mask = 0x1F;
1230 + port->mii.reg_num_mask = 0x1F;
1231 +
1232 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1233 + npe_name(port->npe));
1234 +
1235 + phy_reset(dev, plat->phy);
1236 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1237 + ~(BMCR_RESET | BMCR_PDOWN);
1238 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1239 +
1240 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1241 + return 0;
1242 +
1243 +err_unreg:
1244 + unregister_netdev(dev);
1245 +err_npe_rel:
1246 + npe_release(port->npe);
1247 +err_free:
1248 + free_netdev(dev);
1249 + return err;
1250 +}
1251 +
1252 +static int __devexit eth_remove_one(struct platform_device *pdev)
1253 +{
1254 + struct net_device *dev = platform_get_drvdata(pdev);
1255 + struct port *port = netdev_priv(dev);
1256 +
1257 + unregister_netdev(dev);
1258 + npe_port_tab[NPE_ID(port->id)] = NULL;
1259 + platform_set_drvdata(pdev, NULL);
1260 + npe_release(port->npe);
1261 + release_resource(port->mem_res);
1262 + free_netdev(dev);
1263 + return 0;
1264 +}
1265 +
1266 +static struct platform_driver drv = {
1267 + .driver.name = DRV_NAME,
1268 + .probe = eth_init_one,
1269 + .remove = eth_remove_one,
1270 +};
1271 +
1272 +static int __init eth_init_module(void)
1273 +{
1274 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1275 + return -ENOSYS;
1276 +
1277 + /* All MII PHY accesses use NPE-B Ethernet registers */
1278 + spin_lock_init(&mdio_lock);
1279 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1280 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1281 +
1282 + return platform_driver_register(&drv);
1283 +}
1284 +
1285 +static void __exit eth_cleanup_module(void)
1286 +{
1287 + platform_driver_unregister(&drv);
1288 +}
1289 +
1290 +MODULE_AUTHOR("Krzysztof Halasa");
1291 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1292 +MODULE_LICENSE("GPL v2");
1293 +module_init(eth_init_module);
1294 +module_exit(eth_cleanup_module);
1295 diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
1296 index a3df09e..94e7aa7 100644
1297 --- a/drivers/net/wan/Kconfig
1298 +++ b/drivers/net/wan/Kconfig
1299 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
1300
1301 Say Y if your card supports this feature.
1302
1303 +config IXP4XX_HSS
1304 + tristate "IXP4xx HSS (synchronous serial port) support"
1305 + depends on HDLC && ARM && ARCH_IXP4XX
1306 + select IXP4XX_NPE
1307 + select IXP4XX_QMGR
1308 + help
1309 + Say Y here if you want to use built-in HSS ports
1310 + on IXP4xx processor.
1311 +
1312 config DLCI
1313 tristate "Frame Relay DLCI support"
1314 ---help---
1315 diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
1316 index d61fef3..1b1d116 100644
1317 --- a/drivers/net/wan/Makefile
1318 +++ b/drivers/net/wan/Makefile
1319 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
1320 obj-$(CONFIG_WANXL) += wanxl.o
1321 obj-$(CONFIG_PCI200SYN) += pci200syn.o
1322 obj-$(CONFIG_PC300TOO) += pc300too.o
1323 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
1324
1325 clean-files := wanxlfw.inc
1326 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
1327 diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
1328 new file mode 100644
1329 index 0000000..c4cdace
1330 --- /dev/null
1331 +++ b/drivers/net/wan/ixp4xx_hss.c
1332 @@ -0,0 +1,1270 @@
1333 +/*
1334 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
1335 + *
1336 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1337 + *
1338 + * This program is free software; you can redistribute it and/or modify it
1339 + * under the terms of version 2 of the GNU General Public License
1340 + * as published by the Free Software Foundation.
1341 + */
1342 +
1343 +#include <linux/dma-mapping.h>
1344 +#include <linux/dmapool.h>
1345 +#include <linux/io.h>
1346 +#include <linux/kernel.h>
1347 +#include <linux/hdlc.h>
1348 +#include <linux/platform_device.h>
1349 +#include <asm/arch/npe.h>
1350 +#include <asm/arch/qmgr.h>
1351 +
1352 +#define DEBUG_QUEUES 0
1353 +#define DEBUG_DESC 0
1354 +#define DEBUG_RX 0
1355 +#define DEBUG_TX 0
1356 +#define DEBUG_PKT_BYTES 0
1357 +#define DEBUG_CLOSE 0
1358 +
1359 +#define DRV_NAME "ixp4xx_hss"
1360 +
1361 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
1362 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
1363 +#define FRAME_SYNC_SIZE 1024
1364 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
1365 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
1366 +
1367 +#define RX_DESCS 16 /* also length of all RX queues */
1368 +#define TX_DESCS 16 /* also length of all TX queues */
1369 +
1370 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1371 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
1372 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
1373 +
1374 +/* Queue IDs */
1375 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
1376 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
1377 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
1378 +#define HSS0_PKT_TX1_QUEUE 15
1379 +#define HSS0_PKT_TX2_QUEUE 16
1380 +#define HSS0_PKT_TX3_QUEUE 17
1381 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
1382 +#define HSS0_PKT_RXFREE1_QUEUE 19
1383 +#define HSS0_PKT_RXFREE2_QUEUE 20
1384 +#define HSS0_PKT_RXFREE3_QUEUE 21
1385 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
1386 +
1387 +#define HSS1_CHL_RXTRIG_QUEUE 10
1388 +#define HSS1_PKT_RX_QUEUE 0
1389 +#define HSS1_PKT_TX0_QUEUE 5
1390 +#define HSS1_PKT_TX1_QUEUE 6
1391 +#define HSS1_PKT_TX2_QUEUE 7
1392 +#define HSS1_PKT_TX3_QUEUE 8
1393 +#define HSS1_PKT_RXFREE0_QUEUE 1
1394 +#define HSS1_PKT_RXFREE1_QUEUE 2
1395 +#define HSS1_PKT_RXFREE2_QUEUE 3
1396 +#define HSS1_PKT_RXFREE3_QUEUE 4
1397 +#define HSS1_PKT_TXDONE_QUEUE 9
1398 +
1399 +#define NPE_PKT_MODE_HDLC 0
1400 +#define NPE_PKT_MODE_RAW 1
1401 +#define NPE_PKT_MODE_56KMODE 2
1402 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
1403 +
1404 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
1405 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
1406 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
1407 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
1408 +
1409 +
1410 +/* hss_config, PCRs */
1411 +/* Frame sync sampling, default = active low */
1412 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
1413 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
1414 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
1415 +
1416 +/* Frame sync pin: input (default) or output generated off a given clk edge */
1417 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
1418 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
1419 +
1420 +/* Frame and data clock sampling on edge, default = falling */
1421 +#define PCR_FCLK_EDGE_RISING 0x08000000
1422 +#define PCR_DCLK_EDGE_RISING 0x04000000
1423 +
1424 +/* Clock direction, default = input */
1425 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
1426 +
1427 +/* Generate/Receive frame pulses, default = enabled */
1428 +#define PCR_FRM_PULSE_DISABLED 0x01000000
1429 +
1430 + /* Data rate is full (default) or half the configured clk speed */
1431 +#define PCR_HALF_CLK_RATE 0x00200000
1432 +
1433 +/* Invert data between NPE and HSS FIFOs? (default = no) */
1434 +#define PCR_DATA_POLARITY_INVERT 0x00100000
1435 +
1436 +/* TX/RX endianness, default = LSB */
1437 +#define PCR_MSB_ENDIAN 0x00080000
1438 +
1439 +/* Normal (default) / open drain mode (TX only) */
1440 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
1441 +
1442 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
1443 +#define PCR_SOF_NO_FBIT 0x00020000
1444 +
1445 +/* Drive data pins? */
1446 +#define PCR_TX_DATA_ENABLE 0x00010000
1447 +
1448 +/* Voice 56k type: drive the data pins low (default), high, high Z */
1449 +#define PCR_TX_V56K_HIGH 0x00002000
1450 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
1451 +
1452 +/* Unassigned type: drive the data pins low (default), high, high Z */
1453 +#define PCR_TX_UNASS_HIGH 0x00000800
1454 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
1455 +
1456 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
1457 +#define PCR_TX_FB_HIGH_IMP 0x00000400
1458 +
1459 +/* 56k data endiannes - which bit unused: high (default) or low */
1460 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
1461 +
1462 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
1463 +#define PCR_TX_56KS_56K_DATA 0x00000100
1464 +
1465 +/* hss_config, cCR */
1466 +/* Number of packetized clients, default = 1 */
1467 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
1468 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
1469 +
1470 +/* default = no loopback */
1471 +#define CCR_LOOPBACK 0x02000000
1472 +
1473 +/* HSS number, default = 0 (first) */
1474 +#define CCR_SECOND_HSS 0x01000000
1475 +
1476 +
1477 +/* hss_config, clkCR: main:10, num:10, denom:12 */
1478 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
1479 +
1480 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
1481 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
1482 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
1483 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
1484 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
1485 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
1486 +
1487 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
1488 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
1489 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
1490 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
1491 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
1492 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
1493 +
1494 +
1495 +/* hss_config, LUT entries */
1496 +#define TDMMAP_UNASSIGNED 0
1497 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
1498 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
1499 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
1500 +
1501 +#define TIMESLOTS 128
1502 +#define LUT_BITS 2
1503 +
1504 +/* offsets into HSS config */
1505 +#define HSS_CONFIG_TX_PCR 0x00
1506 +#define HSS_CONFIG_RX_PCR 0x04
1507 +#define HSS_CONFIG_CORE_CR 0x08
1508 +#define HSS_CONFIG_CLOCK_CR 0x0C
1509 +#define HSS_CONFIG_TX_FCR 0x10
1510 +#define HSS_CONFIG_RX_FCR 0x14
1511 +#define HSS_CONFIG_TX_LUT 0x18
1512 +#define HSS_CONFIG_RX_LUT 0x38
1513 +
1514 +
1515 +/* NPE command codes */
1516 +/* writes the ConfigWord value to the location specified by offset */
1517 +#define PORT_CONFIG_WRITE 0x40
1518 +
1519 +/* triggers the NPE to load the contents of the configuration table */
1520 +#define PORT_CONFIG_LOAD 0x41
1521 +
1522 +/* triggers the NPE to return an HssErrorReadResponse message */
1523 +#define PORT_ERROR_READ 0x42
1524 +
1525 +/* reset NPE internal status and enable the HssChannelized operation */
1526 +#define CHAN_FLOW_ENABLE 0x43
1527 +#define CHAN_FLOW_DISABLE 0x44
1528 +#define CHAN_IDLE_PATTERN_WRITE 0x45
1529 +#define CHAN_NUM_CHANS_WRITE 0x46
1530 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
1531 +#define CHAN_RX_BUF_CFG_WRITE 0x48
1532 +#define CHAN_TX_BLK_CFG_WRITE 0x49
1533 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
1534 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
1535 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
1536 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
1537 +
1538 +/* downloads the gainWord value for a timeslot switching channel associated
1539 + with bypassNum */
1540 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
1541 +
1542 +/* triggers the NPE to reset internal status and enable the HssPacketized
1543 + operation for the flow specified by pPipe */
1544 +#define PKT_PIPE_FLOW_ENABLE 0x50
1545 +#define PKT_PIPE_FLOW_DISABLE 0x51
1546 +#define PKT_NUM_PIPES_WRITE 0x52
1547 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
1548 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
1549 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
1550 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
1551 +#define PKT_PIPE_MODE_WRITE 0x57
1552 +
1553 +/* HDLC packet status values - desc->status */
1554 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
1555 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
1556 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
1557 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
1558 + this packet (if buf_len < pkt_len) */
1559 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
1560 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
1561 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
1562 +
1563 +
1564 +#ifdef __ARMEB__
1565 +typedef struct sk_buff buffer_t;
1566 +#define free_buffer dev_kfree_skb
1567 +#define free_buffer_irq dev_kfree_skb_irq
1568 +#else
1569 +typedef void buffer_t;
1570 +#define free_buffer kfree
1571 +#define free_buffer_irq kfree
1572 +#endif
1573 +
1574 +struct port {
1575 + struct npe *npe;
1576 + struct net_device *netdev;
1577 + struct hss_plat_info *plat;
1578 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1579 + struct desc *desc_tab; /* coherent */
1580 + u32 desc_tab_phys;
1581 + int id;
1582 + unsigned int clock_type, clock_rate, loopback;
1583 + u8 hdlc_cfg;
1584 +};
1585 +
1586 +/* NPE message structure */
1587 +struct msg {
1588 +#ifdef __ARMEB__
1589 + u8 cmd, unused, hss_port, index;
1590 + union {
1591 + struct { u8 data8a, data8b, data8c, data8d; };
1592 + struct { u16 data16a, data16b; };
1593 + struct { u32 data32; };
1594 + };
1595 +#else
1596 + u8 index, hss_port, unused, cmd;
1597 + union {
1598 + struct { u8 data8d, data8c, data8b, data8a; };
1599 + struct { u16 data16b, data16a; };
1600 + struct { u32 data32; };
1601 + };
1602 +#endif
1603 +};
1604 +
1605 +/* HDLC packet descriptor */
1606 +struct desc {
1607 + u32 next; /* pointer to next buffer, unused */
1608 +
1609 +#ifdef __ARMEB__
1610 + u16 buf_len; /* buffer length */
1611 + u16 pkt_len; /* packet length */
1612 + u32 data; /* pointer to data buffer in RAM */
1613 + u8 status;
1614 + u8 error_count;
1615 + u16 __reserved;
1616 +#else
1617 + u16 pkt_len; /* packet length */
1618 + u16 buf_len; /* buffer length */
1619 + u32 data; /* pointer to data buffer in RAM */
1620 + u16 __reserved;
1621 + u8 error_count;
1622 + u8 status;
1623 +#endif
1624 + u32 __reserved1[4];
1625 +};
1626 +
1627 +
1628 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1629 + (n) * sizeof(struct desc))
1630 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1631 +
1632 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1633 + ((n) + RX_DESCS) * sizeof(struct desc))
1634 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1635 +
1636 +/*****************************************************************************
1637 + * global variables
1638 + ****************************************************************************/
1639 +
1640 +static int ports_open;
1641 +static struct dma_pool *dma_pool;
1642 +
1643 +static const struct {
1644 + int tx, txdone, rx, rxfree;
1645 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
1646 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
1647 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
1648 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
1649 +};
1650 +
1651 +/*****************************************************************************
1652 + * utility functions
1653 + ****************************************************************************/
1654 +
1655 +static inline struct port* dev_to_port(struct net_device *dev)
1656 +{
1657 + return dev_to_hdlc(dev)->priv;
1658 +}
1659 +
1660 +#ifndef __ARMEB__
1661 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1662 +{
1663 + int i;
1664 + for (i = 0; i < cnt; i++)
1665 + dest[i] = swab32(src[i]);
1666 +}
1667 +#endif
1668 +
1669 +static inline void debug_pkt(struct net_device *dev, const char *func,
1670 + u8 *data, int len)
1671 +{
1672 +#if DEBUG_PKT_BYTES
1673 + int i;
1674 +
1675 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1676 + for (i = 0; i < len; i++) {
1677 + if (i >= DEBUG_PKT_BYTES)
1678 + break;
1679 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
1680 + }
1681 + printk("\n");
1682 +#endif
1683 +}
1684 +
1685 +
1686 +static inline void debug_desc(u32 phys, struct desc *desc)
1687 +{
1688 +#if DEBUG_DESC
1689 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
1690 + phys, desc->next, desc->buf_len, desc->pkt_len,
1691 + desc->data, desc->status, desc->error_count);
1692 +#endif
1693 +}
1694 +
1695 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1696 +{
1697 +#if DEBUG_QUEUES
1698 + static struct {
1699 + int queue;
1700 + char *name;
1701 + } names[] = {
1702 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
1703 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
1704 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
1705 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
1706 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
1707 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
1708 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
1709 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
1710 + };
1711 + int i;
1712 +
1713 + for (i = 0; i < ARRAY_SIZE(names); i++)
1714 + if (names[i].queue == queue)
1715 + break;
1716 +
1717 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1718 + i < ARRAY_SIZE(names) ? names[i].name : "",
1719 + is_get ? "->" : "<-", phys);
1720 +#endif
1721 +}
1722 +
1723 +static inline u32 queue_get_entry(unsigned int queue)
1724 +{
1725 + u32 phys = qmgr_get_entry(queue);
1726 + debug_queue(queue, 1, phys);
1727 + return phys;
1728 +}
1729 +
1730 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1731 + int is_tx)
1732 +{
1733 + u32 phys, tab_phys, n_desc;
1734 + struct desc *tab;
1735 +
1736 + if (!(phys = queue_get_entry(queue)))
1737 + return -1;
1738 +
1739 + BUG_ON(phys & 0x1F);
1740 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1741 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1742 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1743 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1744 + debug_desc(phys, &tab[n_desc]);
1745 + BUG_ON(tab[n_desc].next);
1746 + return n_desc;
1747 +}
1748 +
1749 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1750 + struct desc *desc)
1751 +{
1752 + debug_queue(queue, 0, phys);
1753 + debug_desc(phys, desc);
1754 + BUG_ON(phys & 0x1F);
1755 + qmgr_put_entry(queue, phys);
1756 + BUG_ON(qmgr_stat_overflow(queue));
1757 +}
1758 +
1759 +
1760 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1761 +{
1762 +#ifdef __ARMEB__
1763 + dma_unmap_single(&port->netdev->dev, desc->data,
1764 + desc->buf_len, DMA_TO_DEVICE);
1765 +#else
1766 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1767 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1768 + DMA_TO_DEVICE);
1769 +#endif
1770 +}
1771 +
1772 +
1773 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
1774 +{
1775 + struct net_device *dev = pdev;
1776 + if (carrier)
1777 + netif_carrier_on(dev);
1778 + else
1779 + netif_carrier_off(dev);
1780 +}
1781 +
1782 +static void hss_hdlc_rx_irq(void *pdev)
1783 +{
1784 + struct net_device *dev = pdev;
1785 + struct port *port = dev_to_port(dev);
1786 +
1787 +#if DEBUG_RX
1788 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
1789 +#endif
1790 + qmgr_disable_irq(queue_ids[port->id].rx);
1791 + netif_rx_schedule(dev);
1792 +}
1793 +
1794 +static int hss_hdlc_poll(struct net_device *dev, int *budget)
1795 +{
1796 + struct port *port = dev_to_port(dev);
1797 + unsigned int rxq = queue_ids[port->id].rx;
1798 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
1799 + struct net_device_stats *stats = hdlc_stats(dev);
1800 + int quota = dev->quota, received = 0;
1801 +
1802 +#if DEBUG_RX
1803 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
1804 +#endif
1805 +
1806 + while (quota) {
1807 + struct sk_buff *skb;
1808 + struct desc *desc;
1809 + int n;
1810 +#ifdef __ARMEB__
1811 + struct sk_buff *temp;
1812 + u32 phys;
1813 +#endif
1814 +
1815 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1816 + dev->quota -= received; /* No packet received */
1817 + *budget -= received;
1818 + received = 0;
1819 +#if DEBUG_RX
1820 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1821 + " netif_rx_complete\n", dev->name);
1822 +#endif
1823 + netif_rx_complete(dev);
1824 + qmgr_enable_irq(rxq);
1825 + if (!qmgr_stat_empty(rxq) &&
1826 + netif_rx_reschedule(dev, 0)) {
1827 +#if DEBUG_RX
1828 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
1829 + " netif_rx_reschedule successed\n",
1830 + dev->name);
1831 +#endif
1832 + qmgr_disable_irq(rxq);
1833 + continue;
1834 + }
1835 +#if DEBUG_RX
1836 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
1837 + dev->name);
1838 +#endif
1839 + return 0; /* all work done */
1840 + }
1841 +
1842 + desc = rx_desc_ptr(port, n);
1843 +
1844 + if (desc->error_count) /* FIXME - remove printk */
1845 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
1846 + " errors %u\n", dev->name, desc->status,
1847 + desc->error_count);
1848 +
1849 + skb = NULL;
1850 + switch (desc->status) {
1851 + case 0:
1852 +#ifdef __ARMEB__
1853 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
1854 + phys = dma_map_single(&dev->dev, skb->data,
1855 + RX_SIZE,
1856 + DMA_FROM_DEVICE);
1857 + if (dma_mapping_error(phys)) {
1858 + dev_kfree_skb(skb);
1859 + skb = NULL;
1860 + }
1861 + }
1862 +#else
1863 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1864 +#endif
1865 + if (!skb)
1866 + stats->rx_dropped++;
1867 + break;
1868 + case ERR_HDLC_ALIGN:
1869 + case ERR_HDLC_ABORT:
1870 + stats->rx_frame_errors++;
1871 + stats->rx_errors++;
1872 + break;
1873 + case ERR_HDLC_FCS:
1874 + stats->rx_crc_errors++;
1875 + stats->rx_errors++;
1876 + break;
1877 + case ERR_HDLC_TOO_LONG:
1878 + stats->rx_length_errors++;
1879 + stats->rx_errors++;
1880 + break;
1881 + default: /* FIXME - remove printk */
1882 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
1883 + " errors %u\n", dev->name, desc->status,
1884 + desc->error_count);
1885 + stats->rx_errors++;
1886 + }
1887 +
1888 + if (!skb) {
1889 + /* put the desc back on RX-ready queue */
1890 + desc->buf_len = RX_SIZE;
1891 + desc->pkt_len = desc->status = 0;
1892 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1893 + continue;
1894 + }
1895 +
1896 + /* process received frame */
1897 +#ifdef __ARMEB__
1898 + temp = skb;
1899 + skb = port->rx_buff_tab[n];
1900 + dma_unmap_single(&dev->dev, desc->data,
1901 + RX_SIZE, DMA_FROM_DEVICE);
1902 +#else
1903 + dma_sync_single(&dev->dev, desc->data,
1904 + RX_SIZE, DMA_FROM_DEVICE);
1905 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1906 + ALIGN(desc->pkt_len, 4) / 4);
1907 +#endif
1908 + skb_put(skb, desc->pkt_len);
1909 +
1910 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
1911 +
1912 + skb->protocol = hdlc_type_trans(skb, dev);
1913 + dev->last_rx = jiffies;
1914 + stats->rx_packets++;
1915 + stats->rx_bytes += skb->len;
1916 + netif_receive_skb(skb);
1917 +
1918 + /* put the new buffer on RX-free queue */
1919 +#ifdef __ARMEB__
1920 + port->rx_buff_tab[n] = temp;
1921 + desc->data = phys;
1922 +#endif
1923 + desc->buf_len = RX_SIZE;
1924 + desc->pkt_len = 0;
1925 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1926 + quota--;
1927 + received++;
1928 + }
1929 + dev->quota -= received;
1930 + *budget -= received;
1931 +#if DEBUG_RX
1932 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
1933 +#endif
1934 + return 1; /* not all work done */
1935 +}
1936 +
1937 +
1938 +static void hss_hdlc_txdone_irq(void *pdev)
1939 +{
1940 + struct net_device *dev = pdev;
1941 + struct port *port = dev_to_port(dev);
1942 + struct net_device_stats *stats = hdlc_stats(dev);
1943 + int n_desc;
1944 +
1945 +#if DEBUG_TX
1946 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
1947 +#endif
1948 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
1949 + port, 1)) >= 0) {
1950 + struct desc *desc;
1951 + int start;
1952 +
1953 + desc = tx_desc_ptr(port, n_desc);
1954 +
1955 + stats->tx_packets++;
1956 + stats->tx_bytes += desc->pkt_len;
1957 +
1958 + dma_unmap_tx(port, desc);
1959 +#if DEBUG_TX
1960 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
1961 + port->netdev->name, port->tx_buff_tab[n_desc]);
1962 +#endif
1963 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1964 + port->tx_buff_tab[n_desc] = NULL;
1965 +
1966 + start = qmgr_stat_empty(port->plat->txreadyq);
1967 + queue_put_desc(port->plat->txreadyq,
1968 + tx_desc_phys(port, n_desc), desc);
1969 + if (start) {
1970 +#if DEBUG_TX
1971 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
1972 + " ready\n", port->netdev->name);
1973 +#endif
1974 + netif_wake_queue(port->netdev);
1975 + }
1976 + }
1977 +}
1978 +
1979 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
1980 +{
1981 + struct port *port = dev_to_port(dev);
1982 + struct net_device_stats *stats = hdlc_stats(dev);
1983 + unsigned int txreadyq = port->plat->txreadyq;
1984 + int len, offset, bytes, n;
1985 + void *mem;
1986 + u32 phys;
1987 + struct desc *desc;
1988 +
1989 +#if DEBUG_TX
1990 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
1991 +#endif
1992 +
1993 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
1994 + dev_kfree_skb(skb);
1995 + stats->tx_errors++;
1996 + return NETDEV_TX_OK;
1997 + }
1998 +
1999 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
2000 +
2001 + len = skb->len;
2002 +#ifdef __ARMEB__
2003 + offset = 0; /* no need to keep alignment */
2004 + bytes = len;
2005 + mem = skb->data;
2006 +#else
2007 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
2008 + bytes = ALIGN(offset + len, 4);
2009 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
2010 + dev_kfree_skb(skb);
2011 + stats->tx_dropped++;
2012 + return NETDEV_TX_OK;
2013 + }
2014 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
2015 + dev_kfree_skb(skb);
2016 +#endif
2017 +
2018 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
2019 + if (dma_mapping_error(phys)) {
2020 +#ifdef __ARMEB__
2021 + dev_kfree_skb(skb);
2022 +#else
2023 + kfree(mem);
2024 +#endif
2025 + stats->tx_dropped++;
2026 + return NETDEV_TX_OK;
2027 + }
2028 +
2029 + n = queue_get_desc(txreadyq, port, 1);
2030 + BUG_ON(n < 0);
2031 + desc = tx_desc_ptr(port, n);
2032 +
2033 +#ifdef __ARMEB__
2034 + port->tx_buff_tab[n] = skb;
2035 +#else
2036 + port->tx_buff_tab[n] = mem;
2037 +#endif
2038 + desc->data = phys + offset;
2039 + desc->buf_len = desc->pkt_len = len;
2040 +
2041 + wmb();
2042 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
2043 + dev->trans_start = jiffies;
2044 +
2045 + if (qmgr_stat_empty(txreadyq)) {
2046 +#if DEBUG_TX
2047 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
2048 +#endif
2049 + netif_stop_queue(dev);
2050 + /* we could miss TX ready interrupt */
2051 + if (!qmgr_stat_empty(txreadyq)) {
2052 +#if DEBUG_TX
2053 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
2054 + dev->name);
2055 +#endif
2056 + netif_wake_queue(dev);
2057 + }
2058 + }
2059 +
2060 +#if DEBUG_TX
2061 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
2062 +#endif
2063 + return NETDEV_TX_OK;
2064 +}
2065 +
2066 +
2067 +static int request_hdlc_queues(struct port *port)
2068 +{
2069 + int err;
2070 +
2071 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
2072 + if (err)
2073 + return err;
2074 +
2075 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
2076 + if (err)
2077 + goto rel_rxfree;
2078 +
2079 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
2080 + if (err)
2081 + goto rel_rx;
2082 +
2083 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
2084 + if (err)
2085 + goto rel_tx;
2086 +
2087 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
2088 + if (err)
2089 + goto rel_txready;
2090 + return 0;
2091 +
2092 +rel_txready:
2093 + qmgr_release_queue(port->plat->txreadyq);
2094 +rel_tx:
2095 + qmgr_release_queue(queue_ids[port->id].tx);
2096 +rel_rx:
2097 + qmgr_release_queue(queue_ids[port->id].rx);
2098 +rel_rxfree:
2099 + qmgr_release_queue(queue_ids[port->id].rxfree);
2100 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
2101 + port->netdev->name);
2102 + return err;
2103 +}
2104 +
2105 +static void release_hdlc_queues(struct port *port)
2106 +{
2107 + qmgr_release_queue(queue_ids[port->id].rxfree);
2108 + qmgr_release_queue(queue_ids[port->id].rx);
2109 + qmgr_release_queue(queue_ids[port->id].txdone);
2110 + qmgr_release_queue(queue_ids[port->id].tx);
2111 + qmgr_release_queue(port->plat->txreadyq);
2112 +}
2113 +
2114 +static int init_hdlc_queues(struct port *port)
2115 +{
2116 + int i;
2117 +
2118 + if (!ports_open)
2119 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
2120 + POOL_ALLOC_SIZE, 32, 0)))
2121 + return -ENOMEM;
2122 +
2123 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
2124 + &port->desc_tab_phys)))
2125 + return -ENOMEM;
2126 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2127 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2128 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2129 +
2130 + /* Setup RX buffers */
2131 + for (i = 0; i < RX_DESCS; i++) {
2132 + struct desc *desc = rx_desc_ptr(port, i);
2133 + buffer_t *buff;
2134 + void *data;
2135 +#ifdef __ARMEB__
2136 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
2137 + return -ENOMEM;
2138 + data = buff->data;
2139 +#else
2140 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
2141 + return -ENOMEM;
2142 + data = buff;
2143 +#endif
2144 + desc->buf_len = RX_SIZE;
2145 + desc->data = dma_map_single(&port->netdev->dev, data,
2146 + RX_SIZE, DMA_FROM_DEVICE);
2147 + if (dma_mapping_error(desc->data)) {
2148 + free_buffer(buff);
2149 + return -EIO;
2150 + }
2151 + port->rx_buff_tab[i] = buff;
2152 + }
2153 +
2154 + return 0;
2155 +}
2156 +
2157 +static void destroy_hdlc_queues(struct port *port)
2158 +{
2159 + int i;
2160 +
2161 + if (port->desc_tab) {
2162 + for (i = 0; i < RX_DESCS; i++) {
2163 + struct desc *desc = rx_desc_ptr(port, i);
2164 + buffer_t *buff = port->rx_buff_tab[i];
2165 + if (buff) {
2166 + dma_unmap_single(&port->netdev->dev,
2167 + desc->data, RX_SIZE,
2168 + DMA_FROM_DEVICE);
2169 + free_buffer(buff);
2170 + }
2171 + }
2172 + for (i = 0; i < TX_DESCS; i++) {
2173 + struct desc *desc = tx_desc_ptr(port, i);
2174 + buffer_t *buff = port->tx_buff_tab[i];
2175 + if (buff) {
2176 + dma_unmap_tx(port, desc);
2177 + free_buffer(buff);
2178 + }
2179 + }
2180 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2181 + port->desc_tab = NULL;
2182 + }
2183 +
2184 + if (!ports_open && dma_pool) {
2185 + dma_pool_destroy(dma_pool);
2186 + dma_pool = NULL;
2187 + }
2188 +}
2189 +
2190 +static int hss_hdlc_open(struct net_device *dev)
2191 +{
2192 + struct port *port = dev_to_port(dev);
2193 + struct npe *npe = port->npe;
2194 + struct msg msg;
2195 + int i, err;
2196 +
2197 + if (!npe_running(npe)) {
2198 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2199 + if (err)
2200 + return err;
2201 + }
2202 +
2203 + if ((err = hdlc_open(dev)) != 0)
2204 + return err;
2205 +
2206 + if (port->plat->open)
2207 + if ((err = port->plat->open(port->id, port->netdev,
2208 + hss_hdlc_set_carrier)) != 0)
2209 + goto err_hdlc_close;
2210 +
2211 + /* HSS main configuration */
2212 + memset(&msg, 0, sizeof(msg));
2213 + msg.cmd = PORT_CONFIG_WRITE;
2214 + msg.hss_port = port->id;
2215 + msg.index = 0; /* offset in HSS config */
2216 +
2217 + msg.data32 = PCR_FRM_PULSE_DISABLED |
2218 + PCR_SOF_NO_FBIT |
2219 + PCR_MSB_ENDIAN |
2220 + PCR_TX_DATA_ENABLE;
2221 +
2222 + if (port->clock_type == CLOCK_INT)
2223 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
2224 +
2225 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
2226 + goto err_plat_close; /* 0: TX PCR */
2227 +
2228 + msg.index = 4;
2229 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
2230 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
2231 + goto err_plat_close; /* 4: RX PCR */
2232 +
2233 + msg.index = 8;
2234 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
2235 + (port->id ? CCR_SECOND_HSS : 0);
2236 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
2237 + goto err_plat_close; /* 8: Core CR */
2238 +
2239 + msg.index = 12;
2240 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
2241 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
2242 + goto err_plat_close; /* 12: CLK CR */
2243 +
2244 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
2245 + msg.index = 16;
2246 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
2247 + goto err_plat_close; /* 16: TX FCR */
2248 +
2249 + msg.index = 20;
2250 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
2251 + goto err_plat_close; /* 20: RX FCR */
2252 +
2253 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
2254 + for (i = 0; i < 32 / LUT_BITS; i++)
2255 + msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i);
2256 +
2257 + for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) {
2258 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
2259 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
2260 + goto err_plat_close;
2261 + }
2262 +
2263 + /* HDLC mode configuration */
2264 + memset(&msg, 0, sizeof(msg));
2265 + msg.cmd = PKT_NUM_PIPES_WRITE;
2266 + msg.hss_port = port->id;
2267 + msg.data8a = PKT_NUM_PIPES;
2268 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
2269 + goto err_plat_close;
2270 +
2271 + memset(&msg, 0, sizeof(msg));
2272 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
2273 + msg.hss_port = port->id;
2274 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
2275 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
2276 + goto err_plat_close;
2277 +
2278 + memset(&msg, 0, sizeof(msg));
2279 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
2280 + msg.hss_port = port->id;
2281 + msg.data32 = 0x7F7F7F7F;
2282 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
2283 + goto err_plat_close;
2284 +
2285 + memset(&msg, 0, sizeof(msg));
2286 + msg.cmd = PORT_CONFIG_LOAD;
2287 + msg.hss_port = port->id;
2288 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
2289 + goto err_plat_close;
2290 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
2291 + goto err_plat_close;
2292 +
2293 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
2294 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
2295 + printk(KERN_DEBUG "%s: unexpected message received in"
2296 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
2297 + err = EIO;
2298 + goto err_plat_close;
2299 + }
2300 +
2301 + memset(&msg, 0, sizeof(msg));
2302 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
2303 + msg.hss_port = port->id;
2304 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
2305 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
2306 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
2307 + goto err_plat_close;
2308 +
2309 + memset(&msg, 0, sizeof(msg));
2310 + msg.cmd = PKT_PIPE_MODE_WRITE;
2311 + msg.hss_port = port->id;
2312 + msg.data8a = NPE_PKT_MODE_HDLC;
2313 + /* msg.data8b = inv_mask */
2314 + /* msg.data8c = or_mask */
2315 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
2316 + goto err_plat_close;
2317 +
2318 + memset(&msg, 0, sizeof(msg));
2319 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
2320 + msg.hss_port = port->id;
2321 + msg.data16a = HDLC_MAX_MRU;
2322 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
2323 + goto err_plat_close;
2324 +
2325 + if ((err = request_hdlc_queues(port)) != 0)
2326 + goto err_plat_close;
2327 +
2328 + if ((err = init_hdlc_queues(port)) != 0)
2329 + goto err_destroy_queues;
2330 +
2331 + memset(&msg, 0, sizeof(msg));
2332 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
2333 + msg.hss_port = port->id;
2334 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
2335 + goto err_destroy_queues;
2336 +
2337 + /* Populate queues with buffers, no failure after this point */
2338 + for (i = 0; i < TX_DESCS; i++)
2339 + queue_put_desc(port->plat->txreadyq,
2340 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2341 +
2342 + for (i = 0; i < RX_DESCS; i++)
2343 + queue_put_desc(queue_ids[port->id].rxfree,
2344 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2345 +
2346 + netif_start_queue(dev);
2347 +
2348 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
2349 + hss_hdlc_rx_irq, dev);
2350 +
2351 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
2352 + hss_hdlc_txdone_irq, dev);
2353 + qmgr_enable_irq(queue_ids[port->id].txdone);
2354 +
2355 + ports_open++;
2356 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2357 + return 0;
2358 +
2359 +err_destroy_queues:
2360 + destroy_hdlc_queues(port);
2361 + release_hdlc_queues(port);
2362 +err_plat_close:
2363 + if (port->plat->close)
2364 + port->plat->close(port->id, port->netdev);
2365 +err_hdlc_close:
2366 + hdlc_close(dev);
2367 + return err;
2368 +}
2369 +
2370 +static int hss_hdlc_close(struct net_device *dev)
2371 +{
2372 + struct port *port = dev_to_port(dev);
2373 + struct npe *npe = port->npe;
2374 + struct msg msg;
2375 + int buffs = RX_DESCS; /* allocated RX buffers */
2376 + int i;
2377 +
2378 + ports_open--;
2379 + qmgr_disable_irq(queue_ids[port->id].rx);
2380 + netif_stop_queue(dev);
2381 +
2382 + memset(&msg, 0, sizeof(msg));
2383 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
2384 + msg.hss_port = port->id;
2385 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
2386 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
2387 + port->id);
2388 + /* The upper level would ignore the error anyway */
2389 + }
2390 +
2391 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
2392 + buffs--;
2393 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
2394 + buffs--;
2395 +
2396 + if (buffs)
2397 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2398 + " left in NPE\n", dev->name, buffs);
2399 +
2400 + buffs = TX_DESCS;
2401 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
2402 + buffs--; /* cancel TX */
2403 +
2404 + i = 0;
2405 + do {
2406 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2407 + buffs--;
2408 + if (!buffs)
2409 + break;
2410 + } while (++i < MAX_CLOSE_WAIT);
2411 +
2412 + if (buffs)
2413 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2414 + "left in NPE\n", dev->name, buffs);
2415 +#if DEBUG_CLOSE
2416 + if (!buffs)
2417 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2418 +#endif
2419 + qmgr_disable_irq(queue_ids[port->id].txdone);
2420 + destroy_hdlc_queues(port);
2421 + release_hdlc_queues(port);
2422 +
2423 + if (port->plat->close)
2424 + port->plat->close(port->id, port->netdev);
2425 + hdlc_close(dev);
2426 + return 0;
2427 +}
2428 +
2429 +
2430 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
2431 + unsigned short parity)
2432 +{
2433 + struct port *port = dev_to_port(dev);
2434 +
2435 + if (encoding != ENCODING_NRZ)
2436 + return -EINVAL;
2437 +
2438 + switch(parity) {
2439 + case PARITY_CRC16_PR1_CCITT:
2440 + port->hdlc_cfg = 0;
2441 + return 0;
2442 +
2443 + case PARITY_CRC32_PR1_CCITT:
2444 + port->hdlc_cfg = PKT_HDLC_CRC_32;
2445 + return 0;
2446 +
2447 + default:
2448 + return -EINVAL;
2449 + }
2450 +}
2451 +
2452 +
2453 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2454 +{
2455 + const size_t size = sizeof(sync_serial_settings);
2456 + sync_serial_settings new_line;
2457 + int clk;
2458 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
2459 + struct port *port = dev_to_port(dev);
2460 +
2461 + if (cmd != SIOCWANDEV)
2462 + return hdlc_ioctl(dev, ifr, cmd);
2463 +
2464 + switch(ifr->ifr_settings.type) {
2465 + case IF_GET_IFACE:
2466 + ifr->ifr_settings.type = IF_IFACE_V35;
2467 + if (ifr->ifr_settings.size < size) {
2468 + ifr->ifr_settings.size = size; /* data size wanted */
2469 + return -ENOBUFS;
2470 + }
2471 + memset(&new_line, 0, sizeof(new_line));
2472 + new_line.clock_type = port->clock_type;
2473 + new_line.clock_rate = port->clock_rate;
2474 + new_line.loopback = port->loopback;
2475 + if (copy_to_user(line, &new_line, size))
2476 + return -EFAULT;
2477 + return 0;
2478 +
2479 + case IF_IFACE_SYNC_SERIAL:
2480 + case IF_IFACE_V35:
2481 + if(!capable(CAP_NET_ADMIN))
2482 + return -EPERM;
2483 + if (dev->flags & IFF_UP)
2484 + return -EBUSY; /* Cannot change parameters when open */
2485 +
2486 + if (copy_from_user(&new_line, line, size))
2487 + return -EFAULT;
2488 +
2489 + clk = new_line.clock_type;
2490 + if (port->plat->set_clock)
2491 + clk = port->plat->set_clock(port->id, clk);
2492 +
2493 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
2494 + return -EINVAL; /* No such clock setting */
2495 +
2496 + if (new_line.loopback != 0 && new_line.loopback != 1)
2497 + return -EINVAL;
2498 +
2499 + port->clock_type = clk; /* Update settings */
2500 + port->clock_rate = new_line.clock_rate;
2501 + port->loopback = new_line.loopback;
2502 + return 0;
2503 +
2504 + default:
2505 + return hdlc_ioctl(dev, ifr, cmd);
2506 + }
2507 +}
2508 +
2509 +
2510 +static int __devinit hss_init_one(struct platform_device *pdev)
2511 +{
2512 + struct port *port;
2513 + struct net_device *dev;
2514 + hdlc_device *hdlc;
2515 + int err;
2516 +
2517 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
2518 + return -ENOMEM;
2519 + platform_set_drvdata(pdev, port);
2520 + port->id = pdev->id;
2521 +
2522 + if ((port->npe = npe_request(0)) == NULL) {
2523 + err = -ENOSYS;
2524 + goto err_free;
2525 + }
2526 +
2527 + port->plat = pdev->dev.platform_data;
2528 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
2529 + err = -ENOMEM;
2530 + goto err_plat;
2531 + }
2532 +
2533 + SET_MODULE_OWNER(net);
2534 + SET_NETDEV_DEV(dev, &pdev->dev);
2535 + hdlc = dev_to_hdlc(dev);
2536 + hdlc->attach = hss_hdlc_attach;
2537 + hdlc->xmit = hss_hdlc_xmit;
2538 + dev->open = hss_hdlc_open;
2539 + dev->poll = hss_hdlc_poll;
2540 + dev->stop = hss_hdlc_close;
2541 + dev->do_ioctl = hss_hdlc_ioctl;
2542 + dev->weight = 16;
2543 + dev->tx_queue_len = 100;
2544 + port->clock_type = CLOCK_EXT;
2545 + port->clock_rate = 2048000;
2546 +
2547 + if (register_hdlc_device(dev)) {
2548 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
2549 + port->id);
2550 + err = -ENOBUFS;
2551 + goto err_free_netdev;
2552 + }
2553 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
2554 + return 0;
2555 +
2556 +err_free_netdev:
2557 + free_netdev(dev);
2558 +err_plat:
2559 + npe_release(port->npe);
2560 + platform_set_drvdata(pdev, NULL);
2561 +err_free:
2562 + kfree(port);
2563 + return err;
2564 +}
2565 +
2566 +static int __devexit hss_remove_one(struct platform_device *pdev)
2567 +{
2568 + struct port *port = platform_get_drvdata(pdev);
2569 +
2570 + unregister_hdlc_device(port->netdev);
2571 + free_netdev(port->netdev);
2572 + npe_release(port->npe);
2573 + platform_set_drvdata(pdev, NULL);
2574 + kfree(port);
2575 + return 0;
2576 +}
2577 +
2578 +static struct platform_driver drv = {
2579 + .driver.name = DRV_NAME,
2580 + .probe = hss_init_one,
2581 + .remove = hss_remove_one,
2582 +};
2583 +
2584 +static int __init hss_init_module(void)
2585 +{
2586 + if ((ixp4xx_read_feature_bits() &
2587 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
2588 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
2589 + return -ENOSYS;
2590 + return platform_driver_register(&drv);
2591 +}
2592 +
2593 +static void __exit hss_cleanup_module(void)
2594 +{
2595 + platform_driver_unregister(&drv);
2596 +}
2597 +
2598 +MODULE_AUTHOR("Krzysztof Halasa");
2599 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
2600 +MODULE_LICENSE("GPL v2");
2601 +module_init(hss_init_module);
2602 +module_exit(hss_cleanup_module);
2603 From: Krzysztof Halasa <khc@pm.waw.pl>
2604 Subject: Adds functions to read and write IXP4xx "feature" bits
2605
2606 Adds functions to read and write IXP4xx "feature" (aka "fuse")
2607 bits, containing information about available/enabled CPU features.
2608
2609 The uncompress.h included by boot/compressed/misc.c resides in
2610 a different space than rest of the kernel and thus can't use
2611 asm/hardware.h (including asm/arch/cpu.h - which, in turn, may use
2612 EXPORTed symbol "processor_id").
2613
2614 Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
2615 --
2616 PATCH FOLLOWS
2617 KernelVersion: 2.6.23
2618
2619 diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2620 index 5d949d7..c704fe8 100644
2621 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2622 +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
2623 @@ -15,10 +15,6 @@
2624 *
2625 */
2626
2627 -#ifndef __ASM_ARCH_HARDWARE_H__
2628 -#error "Do not include this directly, instead #include <asm/hardware.h>"
2629 -#endif
2630 -
2631 #ifndef _ASM_ARM_IXP4XX_H_
2632 #define _ASM_ARM_IXP4XX_H_
2633
2634 @@ -607,4 +603,36 @@
2635
2636 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
2637
2638 +/* "fuse" bits of IXP_EXP_CFG2 */
2639 +#define IXP4XX_FEATURE_RCOMP (1 << 0)
2640 +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
2641 +#define IXP4XX_FEATURE_HASH (1 << 2)
2642 +#define IXP4XX_FEATURE_AES (1 << 3)
2643 +#define IXP4XX_FEATURE_DES (1 << 4)
2644 +#define IXP4XX_FEATURE_HDLC (1 << 5)
2645 +#define IXP4XX_FEATURE_AAL (1 << 6)
2646 +#define IXP4XX_FEATURE_HSS (1 << 7)
2647 +#define IXP4XX_FEATURE_UTOPIA (1 << 8)
2648 +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
2649 +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
2650 +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
2651 +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
2652 +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
2653 +#define IXP4XX_FEATURE_PCI (1 << 14)
2654 +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
2655 +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
2656 +#define IXP4XX_FEATURE_USB_HOST (1 << 18)
2657 +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
2658 +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
2659 +#define IXP4XX_FEATURE_RSA (1 << 21)
2660 +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
2661 +#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
2662 +
2663 +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
2664 + IXP4XX_FEATURE_USB_HOST | \
2665 + IXP4XX_FEATURE_NPEA_ETH | \
2666 + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
2667 + IXP4XX_FEATURE_RSA | \
2668 + IXP4XX_FEATURE_XSCALE_MAX_FREQ)
2669 +
2670 #endif
2671 diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
2672 index d2523b3..2fa3d6b 100644
2673 --- a/include/asm-arm/arch-ixp4xx/cpu.h
2674 +++ b/include/asm-arm/arch-ixp4xx/cpu.h
2675 @@ -28,4 +28,19 @@ extern unsigned int processor_id;
2676 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
2677 IXP465_PROCESSOR_ID_VALUE)
2678
2679 +static inline u32 ixp4xx_read_feature_bits(void)
2680 +{
2681 + unsigned int val = ~*IXP4XX_EXP_CFG2;
2682 + val &= ~IXP4XX_FEATURE_RESERVED;
2683 + if (!cpu_is_ixp46x())
2684 + val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
2685 +
2686 + return val;
2687 +}
2688 +
2689 +static inline void ixp4xx_write_feature_bits(u32 value)
2690 +{
2691 + *IXP4XX_EXP_CFG2 = ~value;
2692 +}
2693 +
2694 #endif /* _ASM_ARCH_CPU_H */
2695 diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
2696 index 297ceda..73e8dc3 100644
2697 --- a/include/asm-arm/arch-ixp4xx/hardware.h
2698 +++ b/include/asm-arm/arch-ixp4xx/hardware.h
2699 @@ -27,13 +27,13 @@
2700
2701 #define pcibios_assign_all_busses() 1
2702
2703 +/* Register locations and bits */
2704 +#include "ixp4xx-regs.h"
2705 +
2706 #ifndef __ASSEMBLER__
2707 #include <asm/arch/cpu.h>
2708 #endif
2709
2710 -/* Register locations and bits */
2711 -#include "ixp4xx-regs.h"
2712 -
2713 /* Platform helper functions and definitions */
2714 #include "platform.h"
2715
2716 diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
2717 index f7a35b7..34ef48f 100644
2718 --- a/include/asm-arm/arch-ixp4xx/uncompress.h
2719 +++ b/include/asm-arm/arch-ixp4xx/uncompress.h
2720 @@ -13,7 +13,7 @@
2721 #ifndef _ARCH_UNCOMPRESS_H_
2722 #define _ARCH_UNCOMPRESS_H_
2723
2724 -#include <asm/hardware.h>
2725 +#include "ixp4xx-regs.h"
2726 #include <asm/mach-types.h>
2727 #include <linux/serial_reg.h>
2728
2729 diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
2730 index 4de432e..c4c810b 100644
2731 --- a/arch/arm/kernel/setup.c
2732 +++ b/arch/arm/kernel/setup.c
2733 @@ -61,6 +61,7 @@ extern int root_mountflags;
2734 extern void _stext, _text, _etext, __data_start, _edata, _end;
2735
2736 unsigned int processor_id;
2737 +EXPORT_SYMBOL(processor_id);
2738 unsigned int __machine_arch_type;
2739 EXPORT_SYMBOL(__machine_arch_type);
2740
2741
2742
2743 From: Krzysztof Halasa <khc@pm.waw.pl>
2744 Subject: Adds drivers for IXP4xx QMgr and NPE features
2745
2746 This patch adds drivers for IXP4xx hardware Queue Manager and for
2747 Network Processor Engines. Requires patch #4712 (reading/writing
2748 CPU feature (aka fuse) bits).
2749
2750 Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
2751 --
2752 PATCH FOLLOWS
2753 KernelVersion: 2.6.23
2754
2755 diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
2756 index 61b2dfc..e774447 100644
2757 --- a/arch/arm/mach-ixp4xx/Kconfig
2758 +++ b/arch/arm/mach-ixp4xx/Kconfig
2759 @@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI
2760 need to use the indirect method instead. If you don't know
2761 what you need, leave this option unselected.
2762
2763 +config IXP4XX_QMGR
2764 + tristate "IXP4xx Queue Manager support"
2765 + help
2766 + This driver supports IXP4xx built-in hardware queue manager
2767 + and is automatically selected by Ethernet and HSS drivers.
2768 +
2769 +config IXP4XX_NPE
2770 + tristate "IXP4xx Network Processor Engine support"
2771 + select HOTPLUG
2772 + select FW_LOADER
2773 + help
2774 + This driver supports IXP4xx built-in network coprocessors
2775 + and is automatically selected by Ethernet and HSS drivers.
2776 +
2777 endmenu
2778
2779 endif
2780 diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
2781 index 77e00ad..4bb97e1 100644
2782 --- a/arch/arm/mach-ixp4xx/Makefile
2783 +++ b/arch/arm/mach-ixp4xx/Makefile
2784 @@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
2785 obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
2786
2787 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
2788 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
2789 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
2790 diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h
2791 new file mode 100644
2792 index 0000000..1e52b95
2793 --- /dev/null
2794 +++ b/include/asm-arm/arch-ixp4xx/qmgr.h
2795 @@ -0,0 +1,126 @@
2796 +/*
2797 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2798 + *
2799 + * This program is free software; you can redistribute it and/or modify it
2800 + * under the terms of version 2 of the GNU General Public License
2801 + * as published by the Free Software Foundation.
2802 + */
2803 +
2804 +#ifndef IXP4XX_QMGR_H
2805 +#define IXP4XX_QMGR_H
2806 +
2807 +#include <linux/io.h>
2808 +#include <linux/kernel.h>
2809 +
2810 +#define HALF_QUEUES 32
2811 +#define QUEUES 64 /* only 32 lower queues currently supported */
2812 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
2813 +
2814 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
2815 +#define QUEUE_STAT1_NEARLY_EMPTY 2
2816 +#define QUEUE_STAT1_NEARLY_FULL 4
2817 +#define QUEUE_STAT1_FULL 8
2818 +#define QUEUE_STAT2_UNDERFLOW 1
2819 +#define QUEUE_STAT2_OVERFLOW 2
2820 +
2821 +#define QUEUE_WATERMARK_0_ENTRIES 0
2822 +#define QUEUE_WATERMARK_1_ENTRY 1
2823 +#define QUEUE_WATERMARK_2_ENTRIES 2
2824 +#define QUEUE_WATERMARK_4_ENTRIES 3
2825 +#define QUEUE_WATERMARK_8_ENTRIES 4
2826 +#define QUEUE_WATERMARK_16_ENTRIES 5
2827 +#define QUEUE_WATERMARK_32_ENTRIES 6
2828 +#define QUEUE_WATERMARK_64_ENTRIES 7
2829 +
2830 +/* queue interrupt request conditions */
2831 +#define QUEUE_IRQ_SRC_EMPTY 0
2832 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
2833 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
2834 +#define QUEUE_IRQ_SRC_FULL 3
2835 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
2836 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
2837 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
2838 +#define QUEUE_IRQ_SRC_NOT_FULL 7
2839 +
2840 +struct qmgr_regs {
2841 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
2842 + u32 stat1[4]; /* 0x400 - 0x40F */
2843 + u32 stat2[2]; /* 0x410 - 0x417 */
2844 + u32 statne_h; /* 0x418 - queue nearly empty */
2845 + u32 statf_h; /* 0x41C - queue full */
2846 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
2847 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
2848 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
2849 + u32 reserved[1776];
2850 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
2851 +};
2852 +
2853 +void qmgr_set_irq(unsigned int queue, int src,
2854 + void (*handler)(void *pdev), void *pdev);
2855 +void qmgr_enable_irq(unsigned int queue);
2856 +void qmgr_disable_irq(unsigned int queue);
2857 +
2858 +/* request_ and release_queue() must be called from non-IRQ context */
2859 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
2860 + unsigned int nearly_empty_watermark,
2861 + unsigned int nearly_full_watermark);
2862 +void qmgr_release_queue(unsigned int queue);
2863 +
2864 +
2865 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
2866 +{
2867 + extern struct qmgr_regs __iomem *qmgr_regs;
2868 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
2869 +}
2870 +
2871 +static inline u32 qmgr_get_entry(unsigned int queue)
2872 +{
2873 + extern struct qmgr_regs __iomem *qmgr_regs;
2874 + return __raw_readl(&qmgr_regs->acc[queue][0]);
2875 +}
2876 +
2877 +static inline int qmgr_get_stat1(unsigned int queue)
2878 +{
2879 + extern struct qmgr_regs __iomem *qmgr_regs;
2880 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
2881 + >> ((queue & 7) << 2)) & 0xF;
2882 +}
2883 +
2884 +static inline int qmgr_get_stat2(unsigned int queue)
2885 +{
2886 + extern struct qmgr_regs __iomem *qmgr_regs;
2887 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
2888 + >> ((queue & 0xF) << 1)) & 0x3;
2889 +}
2890 +
2891 +static inline int qmgr_stat_empty(unsigned int queue)
2892 +{
2893 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
2894 +}
2895 +
2896 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
2897 +{
2898 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
2899 +}
2900 +
2901 +static inline int qmgr_stat_nearly_full(unsigned int queue)
2902 +{
2903 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
2904 +}
2905 +
2906 +static inline int qmgr_stat_full(unsigned int queue)
2907 +{
2908 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
2909 +}
2910 +
2911 +static inline int qmgr_stat_underflow(unsigned int queue)
2912 +{
2913 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
2914 +}
2915 +
2916 +static inline int qmgr_stat_overflow(unsigned int queue)
2917 +{
2918 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
2919 +}
2920 +
2921 +#endif
2922 diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h
2923 new file mode 100644
2924 index 0000000..37d0511
2925 --- /dev/null
2926 +++ b/include/asm-arm/arch-ixp4xx/npe.h
2927 @@ -0,0 +1,39 @@
2928 +#ifndef __IXP4XX_NPE_H
2929 +#define __IXP4XX_NPE_H
2930 +
2931 +#include <linux/kernel.h>
2932 +
2933 +extern const char *npe_names[];
2934 +
2935 +struct npe_regs {
2936 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
2937 + u32 action_points[4];
2938 + u32 watchpoint_fifo, watch_count;
2939 + u32 profile_count;
2940 + u32 messaging_status, messaging_control;
2941 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
2942 +};
2943 +
2944 +struct npe {
2945 + struct resource *mem_res;
2946 + struct npe_regs __iomem *regs;
2947 + u32 regs_phys;
2948 + int id;
2949 + int valid;
2950 +};
2951 +
2952 +
2953 +static inline const char *npe_name(struct npe *npe)
2954 +{
2955 + return npe_names[npe->id];
2956 +}
2957 +
2958 +int npe_running(struct npe *npe);
2959 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
2960 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
2961 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
2962 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
2963 +struct npe *npe_request(int id);
2964 +void npe_release(struct npe *npe);
2965 +
2966 +#endif /* __IXP4XX_NPE_H */
2967 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
2968 new file mode 100644
2969 index 0000000..e833013
2970 --- /dev/null
2971 +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
2972 @@ -0,0 +1,274 @@
2973 +/*
2974 + * Intel IXP4xx Queue Manager driver for Linux
2975 + *
2976 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2977 + *
2978 + * This program is free software; you can redistribute it and/or modify it
2979 + * under the terms of version 2 of the GNU General Public License
2980 + * as published by the Free Software Foundation.
2981 + */
2982 +
2983 +#include <linux/ioport.h>
2984 +#include <linux/interrupt.h>
2985 +#include <linux/kernel.h>
2986 +#include <linux/module.h>
2987 +#include <asm/arch/qmgr.h>
2988 +
2989 +#define DEBUG 0
2990 +
2991 +struct qmgr_regs __iomem *qmgr_regs;
2992 +static struct resource *mem_res;
2993 +static spinlock_t qmgr_lock;
2994 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
2995 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
2996 +static void *irq_pdevs[HALF_QUEUES];
2997 +
2998 +void qmgr_set_irq(unsigned int queue, int src,
2999 + void (*handler)(void *pdev), void *pdev)
3000 +{
3001 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
3002 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
3003 + unsigned long flags;
3004 +
3005 + src &= 7;
3006 + spin_lock_irqsave(&qmgr_lock, flags);
3007 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
3008 + irq_handlers[queue] = handler;
3009 + irq_pdevs[queue] = pdev;
3010 + spin_unlock_irqrestore(&qmgr_lock, flags);
3011 +}
3012 +
3013 +
3014 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
3015 +{
3016 + int i;
3017 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
3018 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
3019 +
3020 + for (i = 0; i < HALF_QUEUES; i++)
3021 + if (val & (1 << i))
3022 + irq_handlers[i](irq_pdevs[i]);
3023 +
3024 + return val ? IRQ_HANDLED : 0;
3025 +}
3026 +
3027 +
3028 +void qmgr_enable_irq(unsigned int queue)
3029 +{
3030 + unsigned long flags;
3031 +
3032 + spin_lock_irqsave(&qmgr_lock, flags);
3033 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
3034 + &qmgr_regs->irqen[0]);
3035 + spin_unlock_irqrestore(&qmgr_lock, flags);
3036 +}
3037 +
3038 +void qmgr_disable_irq(unsigned int queue)
3039 +{
3040 + unsigned long flags;
3041 +
3042 + spin_lock_irqsave(&qmgr_lock, flags);
3043 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
3044 + &qmgr_regs->irqen[0]);
3045 + spin_unlock_irqrestore(&qmgr_lock, flags);
3046 +}
3047 +
3048 +static inline void shift_mask(u32 *mask)
3049 +{
3050 + mask[3] = mask[3] << 1 | mask[2] >> 31;
3051 + mask[2] = mask[2] << 1 | mask[1] >> 31;
3052 + mask[1] = mask[1] << 1 | mask[0] >> 31;
3053 + mask[0] <<= 1;
3054 +}
3055 +
3056 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3057 + unsigned int nearly_empty_watermark,
3058 + unsigned int nearly_full_watermark)
3059 +{
3060 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
3061 + int err;
3062 +
3063 + if (queue >= HALF_QUEUES)
3064 + return -ERANGE;
3065 +
3066 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
3067 + return -EINVAL;
3068 +
3069 + switch (len) {
3070 + case 16:
3071 + cfg = 0 << 24;
3072 + mask[0] = 0x1;
3073 + break;
3074 + case 32:
3075 + cfg = 1 << 24;
3076 + mask[0] = 0x3;
3077 + break;
3078 + case 64:
3079 + cfg = 2 << 24;
3080 + mask[0] = 0xF;
3081 + break;
3082 + case 128:
3083 + cfg = 3 << 24;
3084 + mask[0] = 0xFF;
3085 + break;
3086 + default:
3087 + return -EINVAL;
3088 + }
3089 +
3090 + cfg |= nearly_empty_watermark << 26;
3091 + cfg |= nearly_full_watermark << 29;
3092 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
3093 + mask[1] = mask[2] = mask[3] = 0;
3094 +
3095 + if (!try_module_get(THIS_MODULE))
3096 + return -ENODEV;
3097 +
3098 + spin_lock_irq(&qmgr_lock);
3099 + if (__raw_readl(&qmgr_regs->sram[queue])) {
3100 + err = -EBUSY;
3101 + goto err;
3102 + }
3103 +
3104 + while (1) {
3105 + if (!(used_sram_bitmap[0] & mask[0]) &&
3106 + !(used_sram_bitmap[1] & mask[1]) &&
3107 + !(used_sram_bitmap[2] & mask[2]) &&
3108 + !(used_sram_bitmap[3] & mask[3]))
3109 + break; /* found free space */
3110 +
3111 + addr++;
3112 + shift_mask(mask);
3113 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
3114 + printk(KERN_ERR "qmgr: no free SRAM space for"
3115 + " queue %i\n", queue);
3116 + err = -ENOMEM;
3117 + goto err;
3118 + }
3119 + }
3120 +
3121 + used_sram_bitmap[0] |= mask[0];
3122 + used_sram_bitmap[1] |= mask[1];
3123 + used_sram_bitmap[2] |= mask[2];
3124 + used_sram_bitmap[3] |= mask[3];
3125 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
3126 + spin_unlock_irq(&qmgr_lock);
3127 +
3128 +#if DEBUG
3129 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
3130 + queue, addr);
3131 +#endif
3132 + return 0;
3133 +
3134 +err:
3135 + spin_unlock_irq(&qmgr_lock);
3136 + module_put(THIS_MODULE);
3137 + return err;
3138 +}
3139 +
3140 +void qmgr_release_queue(unsigned int queue)
3141 +{
3142 + u32 cfg, addr, mask[4];
3143 +
3144 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
3145 +
3146 + spin_lock_irq(&qmgr_lock);
3147 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
3148 + addr = (cfg >> 14) & 0xFF;
3149 +
3150 + BUG_ON(!addr); /* not requested */
3151 +
3152 + switch ((cfg >> 24) & 3) {
3153 + case 0: mask[0] = 0x1; break;
3154 + case 1: mask[0] = 0x3; break;
3155 + case 2: mask[0] = 0xF; break;
3156 + case 3: mask[0] = 0xFF; break;
3157 + }
3158 +
3159 + while (addr--)
3160 + shift_mask(mask);
3161 +
3162 + __raw_writel(0, &qmgr_regs->sram[queue]);
3163 +
3164 + used_sram_bitmap[0] &= ~mask[0];
3165 + used_sram_bitmap[1] &= ~mask[1];
3166 + used_sram_bitmap[2] &= ~mask[2];
3167 + used_sram_bitmap[3] &= ~mask[3];
3168 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
3169 + spin_unlock_irq(&qmgr_lock);
3170 +
3171 + module_put(THIS_MODULE);
3172 +#if DEBUG
3173 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
3174 +#endif
3175 +}
3176 +
3177 +static int qmgr_init(void)
3178 +{
3179 + int i, err;
3180 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
3181 + IXP4XX_QMGR_REGION_SIZE,
3182 + "IXP4xx Queue Manager");
3183 + if (mem_res == NULL)
3184 + return -EBUSY;
3185 +
3186 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3187 + if (qmgr_regs == NULL) {
3188 + err = -ENOMEM;
3189 + goto error_map;
3190 + }
3191 +
3192 + /* reset qmgr registers */
3193 + for (i = 0; i < 4; i++) {
3194 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
3195 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
3196 + }
3197 + for (i = 0; i < 2; i++) {
3198 + __raw_writel(0, &qmgr_regs->stat2[i]);
3199 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
3200 + __raw_writel(0, &qmgr_regs->irqen[i]);
3201 + }
3202 +
3203 + for (i = 0; i < QUEUES; i++)
3204 + __raw_writel(0, &qmgr_regs->sram[i]);
3205 +
3206 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
3207 + "IXP4xx Queue Manager", NULL);
3208 + if (err) {
3209 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
3210 + IRQ_IXP4XX_QM1);
3211 + goto error_irq;
3212 + }
3213 +
3214 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
3215 + spin_lock_init(&qmgr_lock);
3216 +
3217 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
3218 + return 0;
3219 +
3220 +error_irq:
3221 + iounmap(qmgr_regs);
3222 +error_map:
3223 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3224 + return err;
3225 +}
3226 +
3227 +static void qmgr_remove(void)
3228 +{
3229 + free_irq(IRQ_IXP4XX_QM1, NULL);
3230 + synchronize_irq(IRQ_IXP4XX_QM1);
3231 + iounmap(qmgr_regs);
3232 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
3233 +}
3234 +
3235 +module_init(qmgr_init);
3236 +module_exit(qmgr_remove);
3237 +
3238 +MODULE_LICENSE("GPL v2");
3239 +MODULE_AUTHOR("Krzysztof Halasa");
3240 +
3241 +EXPORT_SYMBOL(qmgr_regs);
3242 +EXPORT_SYMBOL(qmgr_set_irq);
3243 +EXPORT_SYMBOL(qmgr_enable_irq);
3244 +EXPORT_SYMBOL(qmgr_disable_irq);
3245 +EXPORT_SYMBOL(qmgr_request_queue);
3246 +EXPORT_SYMBOL(qmgr_release_queue);
3247 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
3248 new file mode 100644
3249 index 0000000..83c137e
3250 --- /dev/null
3251 +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
3252 @@ -0,0 +1,741 @@
3253 +/*
3254 + * Intel IXP4xx Network Processor Engine driver for Linux
3255 + *
3256 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3257 + *
3258 + * This program is free software; you can redistribute it and/or modify it
3259 + * under the terms of version 2 of the GNU General Public License
3260 + * as published by the Free Software Foundation.
3261 + *
3262 + * The code is based on publicly available information:
3263 + * - Intel IXP4xx Developer's Manual and other e-papers
3264 + * - Intel IXP400 Access Library Software (BSD license)
3265 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
3266 + * Thanks, Christian.
3267 + */
3268 +
3269 +#include <linux/delay.h>
3270 +#include <linux/dma-mapping.h>
3271 +#include <linux/firmware.h>
3272 +#include <linux/io.h>
3273 +#include <linux/kernel.h>
3274 +#include <linux/module.h>
3275 +#include <linux/slab.h>
3276 +#include <asm/arch/npe.h>
3277 +
3278 +#define DEBUG_MSG 0
3279 +#define DEBUG_FW 0
3280 +
3281 +#define NPE_COUNT 3
3282 +#define MAX_RETRIES 1000 /* microseconds */
3283 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
3284 +#define NPE_46X_DATA_SIZE 0x1000
3285 +#define NPE_A_42X_INSTR_SIZE 0x1000
3286 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
3287 +#define NPE_46X_INSTR_SIZE 0x1000
3288 +#define REGS_SIZE 0x1000
3289 +
3290 +#define NPE_PHYS_REG 32
3291 +
3292 +#define FW_MAGIC 0xFEEDF00D
3293 +#define FW_BLOCK_TYPE_INSTR 0x0
3294 +#define FW_BLOCK_TYPE_DATA 0x1
3295 +#define FW_BLOCK_TYPE_EOF 0xF
3296 +
3297 +/* NPE exec status (read) and command (write) */
3298 +#define CMD_NPE_STEP 0x01
3299 +#define CMD_NPE_START 0x02
3300 +#define CMD_NPE_STOP 0x03
3301 +#define CMD_NPE_CLR_PIPE 0x04
3302 +#define CMD_CLR_PROFILE_CNT 0x0C
3303 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
3304 +#define CMD_WR_INS_MEM 0x11
3305 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
3306 +#define CMD_WR_DATA_MEM 0x13
3307 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
3308 +#define CMD_WR_ECS_REG 0x15
3309 +
3310 +#define STAT_RUN 0x80000000
3311 +#define STAT_STOP 0x40000000
3312 +#define STAT_CLEAR 0x20000000
3313 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
3314 +
3315 +#define NPE_STEVT 0x1B
3316 +#define NPE_STARTPC 0x1C
3317 +#define NPE_REGMAP 0x1E
3318 +#define NPE_CINDEX 0x1F
3319 +
3320 +#define INSTR_WR_REG_SHORT 0x0000C000
3321 +#define INSTR_WR_REG_BYTE 0x00004000
3322 +#define INSTR_RD_FIFO 0x0F888220
3323 +#define INSTR_RESET_MBOX 0x0FAC8210
3324 +
3325 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
3326 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
3327 +#define ECS_BG_CTXT_REG_2 0x02
3328 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
3329 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
3330 +#define ECS_PRI_1_CTXT_REG_2 0x06
3331 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
3332 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
3333 +#define ECS_PRI_2_CTXT_REG_2 0x0A
3334 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
3335 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
3336 +#define ECS_DBG_CTXT_REG_2 0x0E
3337 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
3338 +
3339 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
3340 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
3341 +#define ECS_REG_0_LDUR_BITS 8
3342 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
3343 +#define ECS_REG_1_CCTXT_BITS 16
3344 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
3345 +#define ECS_REG_1_SELCTXT_BITS 0
3346 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
3347 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
3348 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
3349 +
3350 +/* NPE watchpoint_fifo register bit */
3351 +#define WFIFO_VALID 0x80000000
3352 +
3353 +/* NPE messaging_status register bit definitions */
3354 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
3355 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
3356 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
3357 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
3358 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
3359 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
3360 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
3361 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
3362 +
3363 +/* NPE messaging_control register bit definitions */
3364 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
3365 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
3366 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
3367 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
3368 +
3369 +/* NPE mailbox_status value for reset */
3370 +#define RESET_MBOX_STAT 0x0000F0F0
3371 +
3372 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
3373 +
3374 +#define print_npe(pri, npe, fmt, ...) \
3375 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
3376 +
3377 +#if DEBUG_MSG
3378 +#define debug_msg(npe, fmt, ...) \
3379 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
3380 +#else
3381 +#define debug_msg(npe, fmt, ...)
3382 +#endif
3383 +
3384 +static struct {
3385 + u32 reg, val;
3386 +} ecs_reset[] = {
3387 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
3388 + { ECS_BG_CTXT_REG_1, 0x01000000 },
3389 + { ECS_BG_CTXT_REG_2, 0x00008000 },
3390 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
3391 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
3392 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
3393 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
3394 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
3395 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
3396 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
3397 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
3398 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
3399 + { ECS_INSTRUCT_REG, 0x1003C00F },
3400 +};
3401 +
3402 +static struct npe npe_tab[NPE_COUNT] = {
3403 + {
3404 + .id = 0,
3405 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
3406 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
3407 + }, {
3408 + .id = 1,
3409 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
3410 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
3411 + }, {
3412 + .id = 2,
3413 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
3414 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
3415 + }
3416 +};
3417 +
3418 +int npe_running(struct npe *npe)
3419 +{
3420 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
3421 +}
3422 +
3423 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
3424 +{
3425 + __raw_writel(data, &npe->regs->exec_data);
3426 + __raw_writel(addr, &npe->regs->exec_addr);
3427 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
3428 +}
3429 +
3430 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
3431 +{
3432 + __raw_writel(addr, &npe->regs->exec_addr);
3433 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
3434 + /* Iintroduce extra read cycles after issuing read command to NPE
3435 + so that we read the register after the NPE has updated it.
3436 + This is to overcome race condition between XScale and NPE */
3437 + __raw_readl(&npe->regs->exec_data);
3438 + __raw_readl(&npe->regs->exec_data);
3439 + return __raw_readl(&npe->regs->exec_data);
3440 +}
3441 +
3442 +static void npe_clear_active(struct npe *npe, u32 reg)
3443 +{
3444 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
3445 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
3446 +}
3447 +
3448 +static void npe_start(struct npe *npe)
3449 +{
3450 + /* ensure only Background Context Stack Level is active */
3451 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
3452 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
3453 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
3454 +
3455 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3456 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
3457 +}
3458 +
3459 +static void npe_stop(struct npe *npe)
3460 +{
3461 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
3462 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
3463 +}
3464 +
3465 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
3466 + u32 ldur)
3467 +{
3468 + u32 wc;
3469 + int i;
3470 +
3471 + /* set the Active bit, and the LDUR, in the debug level */
3472 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
3473 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
3474 +
3475 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
3476 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
3477 + which context store to access.
3478 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
3479 + */
3480 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
3481 + (ctx << ECS_REG_1_CCTXT_BITS) |
3482 + (ctx << ECS_REG_1_SELCTXT_BITS));
3483 +
3484 + /* clear the pipeline */
3485 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3486 +
3487 + /* load NPE instruction into the instruction register */
3488 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
3489 +
3490 + /* we need this value later to wait for completion of NPE execution
3491 + step */
3492 + wc = __raw_readl(&npe->regs->watch_count);
3493 +
3494 + /* issue a Step One command via the Execution Control register */
3495 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
3496 +
3497 + /* Watch Count register increments when NPE completes an instruction */
3498 + for (i = 0; i < MAX_RETRIES; i++) {
3499 + if (wc != __raw_readl(&npe->regs->watch_count))
3500 + return 0;
3501 + udelay(1);
3502 + }
3503 +
3504 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
3505 + return -ETIMEDOUT;
3506 +}
3507 +
3508 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
3509 + u8 val, u32 ctx)
3510 +{
3511 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
3512 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
3513 + addr << 9 | /* base Operand */
3514 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
3515 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
3516 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
3517 +}
3518 +
3519 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
3520 + u16 val, u32 ctx)
3521 +{
3522 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
3523 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
3524 + addr << 9 | /* base Operand */
3525 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
3526 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
3527 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
3528 +}
3529 +
3530 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
3531 + u32 val, u32 ctx)
3532 +{
3533 + /* write in 16 bit steps first the high and then the low value */
3534 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
3535 + return -ETIMEDOUT;
3536 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
3537 +}
3538 +
3539 +static int npe_reset(struct npe *npe)
3540 +{
3541 + u32 val, ctl, exec_count, ctx_reg2;
3542 + int i;
3543 +
3544 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
3545 + 0x3F3FFFFF;
3546 +
3547 + /* disable parity interrupt */
3548 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
3549 +
3550 + /* pre exec - debug instruction */
3551 + /* turn off the halt bit by clearing Execution Count register. */
3552 + exec_count = __raw_readl(&npe->regs->exec_count);
3553 + __raw_writel(0, &npe->regs->exec_count);
3554 + /* ensure that IF and IE are on (temporarily), so that we don't end up
3555 + stepping forever */
3556 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
3557 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
3558 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
3559 +
3560 + /* clear the FIFOs */
3561 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
3562 + ;
3563 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
3564 + /* read from the outFIFO until empty */
3565 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
3566 + __raw_readl(&npe->regs->in_out_fifo));
3567 +
3568 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
3569 + /* step execution of the NPE intruction to read inFIFO using
3570 + the Debug Executing Context stack */
3571 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
3572 + return -ETIMEDOUT;
3573 +
3574 + /* reset the mailbox reg from the XScale side */
3575 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
3576 + /* from NPE side */
3577 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
3578 + return -ETIMEDOUT;
3579 +
3580 + /* Reset the physical registers in the NPE register file */
3581 + for (val = 0; val < NPE_PHYS_REG; val++) {
3582 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
3583 + return -ETIMEDOUT;
3584 + /* address is either 0 or 4 */
3585 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
3586 + return -ETIMEDOUT;
3587 + }
3588 +
3589 + /* Reset the context store = each context's Context Store registers */
3590 +
3591 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
3592 + for Background ECS, to set where NPE starts executing code */
3593 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
3594 + val &= ~ECS_REG_0_NEXTPC_MASK;
3595 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
3596 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
3597 +
3598 + for (i = 0; i < 16; i++) {
3599 + if (i) { /* Context 0 has no STEVT nor STARTPC */
3600 + /* STEVT = off, 0x80 */
3601 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
3602 + return -ETIMEDOUT;
3603 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
3604 + return -ETIMEDOUT;
3605 + }
3606 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
3607 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
3608 + return -ETIMEDOUT;
3609 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
3610 + return -ETIMEDOUT;
3611 + }
3612 +
3613 + /* post exec */
3614 + /* clear active bit in debug level */
3615 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
3616 + /* clear the pipeline */
3617 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
3618 + /* restore previous values */
3619 + __raw_writel(exec_count, &npe->regs->exec_count);
3620 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
3621 +
3622 + /* write reset values to Execution Context Stack registers */
3623 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
3624 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
3625 + ecs_reset[val].val);
3626 +
3627 + /* clear the profile counter */
3628 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
3629 +
3630 + __raw_writel(0, &npe->regs->exec_count);
3631 + __raw_writel(0, &npe->regs->action_points[0]);
3632 + __raw_writel(0, &npe->regs->action_points[1]);
3633 + __raw_writel(0, &npe->regs->action_points[2]);
3634 + __raw_writel(0, &npe->regs->action_points[3]);
3635 + __raw_writel(0, &npe->regs->watch_count);
3636 +
3637 + val = ixp4xx_read_feature_bits();
3638 + /* reset the NPE */
3639 + ixp4xx_write_feature_bits(val &
3640 + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
3641 + for (i = 0; i < MAX_RETRIES; i++) {
3642 + if (!(ixp4xx_read_feature_bits() &
3643 + (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
3644 + break; /* reset completed */
3645 + udelay(1);
3646 + }
3647 + if (i == MAX_RETRIES)
3648 + return -ETIMEDOUT;
3649 +
3650 + /* deassert reset */
3651 + ixp4xx_write_feature_bits(val |
3652 + (IXP4XX_FEATURE_RESET_NPEA << npe->id));
3653 + for (i = 0; i < MAX_RETRIES; i++) {
3654 + if (ixp4xx_read_feature_bits() &
3655 + (IXP4XX_FEATURE_RESET_NPEA << npe->id))
3656 + break; /* NPE is back alive */
3657 + udelay(1);
3658 + }
3659 + if (i == MAX_RETRIES)
3660 + return -ETIMEDOUT;
3661 +
3662 + npe_stop(npe);
3663 +
3664 + /* restore NPE configuration bus Control Register - parity settings */
3665 + __raw_writel(ctl, &npe->regs->messaging_control);
3666 + return 0;
3667 +}
3668 +
3669 +
3670 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
3671 +{
3672 + const u32 *send = msg;
3673 + int cycles = 0;
3674 +
3675 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
3676 + what, send[0], send[1]);
3677 +
3678 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
3679 + debug_msg(npe, "NPE input FIFO not empty\n");
3680 + return -EIO;
3681 + }
3682 +
3683 + __raw_writel(send[0], &npe->regs->in_out_fifo);
3684 +
3685 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
3686 + debug_msg(npe, "NPE input FIFO full\n");
3687 + return -EIO;
3688 + }
3689 +
3690 + __raw_writel(send[1], &npe->regs->in_out_fifo);
3691 +
3692 + while ((cycles < MAX_RETRIES) &&
3693 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
3694 + udelay(1);
3695 + cycles++;
3696 + }
3697 +
3698 + if (cycles == MAX_RETRIES) {
3699 + debug_msg(npe, "Timeout sending message\n");
3700 + return -ETIMEDOUT;
3701 + }
3702 +
3703 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
3704 + return 0;
3705 +}
3706 +
3707 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
3708 +{
3709 + u32 *recv = msg;
3710 + int cycles = 0, cnt = 0;
3711 +
3712 + debug_msg(npe, "Trying to receive message %s\n", what);
3713 +
3714 + while (cycles < MAX_RETRIES) {
3715 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
3716 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
3717 + if (cnt == 2)
3718 + break;
3719 + } else {
3720 + udelay(1);
3721 + cycles++;
3722 + }
3723 + }
3724 +
3725 + switch(cnt) {
3726 + case 1:
3727 + debug_msg(npe, "Received [%08X]\n", recv[0]);
3728 + break;
3729 + case 2:
3730 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
3731 + break;
3732 + }
3733 +
3734 + if (cycles == MAX_RETRIES) {
3735 + debug_msg(npe, "Timeout waiting for message\n");
3736 + return -ETIMEDOUT;
3737 + }
3738 +
3739 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
3740 + return 0;
3741 +}
3742 +
3743 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
3744 +{
3745 + int result;
3746 + u32 *send = msg, recv[2];
3747 +
3748 + if ((result = npe_send_message(npe, msg, what)) != 0)
3749 + return result;
3750 + if ((result = npe_recv_message(npe, recv, what)) != 0)
3751 + return result;
3752 +
3753 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
3754 + debug_msg(npe, "Message %s: unexpected message received\n",
3755 + what);
3756 + return -EIO;
3757 + }
3758 + return 0;
3759 +}
3760 +
3761 +
3762 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
3763 +{
3764 + const struct firmware *fw_entry;
3765 +
3766 + struct dl_block {
3767 + u32 type;
3768 + u32 offset;
3769 + } *blk;
3770 +
3771 + struct dl_image {
3772 + u32 magic;
3773 + u32 id;
3774 + u32 size;
3775 + union {
3776 + u32 data[0];
3777 + struct dl_block blocks[0];
3778 + };
3779 + } *image;
3780 +
3781 + struct dl_codeblock {
3782 + u32 npe_addr;
3783 + u32 size;
3784 + u32 data[0];
3785 + } *cb;
3786 +
3787 + int i, j, err, data_size, instr_size, blocks, table_end;
3788 + u32 cmd;
3789 +
3790 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
3791 + return err;
3792 +
3793 + err = -EINVAL;
3794 + if (fw_entry->size < sizeof(struct dl_image)) {
3795 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
3796 + goto err;
3797 + }
3798 + image = (struct dl_image*)fw_entry->data;
3799 +
3800 +#if DEBUG_FW
3801 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
3802 + image->magic, image->id, image->size, image->size * 4);
3803 +#endif
3804 +
3805 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
3806 + image->id = swab32(image->id);
3807 + image->size = swab32(image->size);
3808 + } else if (image->magic != FW_MAGIC) {
3809 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
3810 + image->magic);
3811 + goto err;
3812 + }
3813 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
3814 + print_npe(KERN_ERR, npe,
3815 + "inconsistent size of firmware file\n");
3816 + goto err;
3817 + }
3818 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
3819 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
3820 + goto err;
3821 + }
3822 + if (image->magic == swab32(FW_MAGIC))
3823 + for (i = 0; i < image->size; i++)
3824 + image->data[i] = swab32(image->data[i]);
3825 +
3826 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
3827 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
3828 + "IXP42x\n");
3829 + goto err;
3830 + }
3831 +
3832 + if (npe_running(npe)) {
3833 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
3834 + "already running\n");
3835 + err = -EBUSY;
3836 + goto err;
3837 + }
3838 +#if 0
3839 + npe_stop(npe);
3840 + npe_reset(npe);
3841 +#endif
3842 +
3843 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
3844 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
3845 + (image->id >> 8) & 0xFF, image->id & 0xFF);
3846 +
3847 + if (!cpu_is_ixp46x()) {
3848 + if (!npe->id)
3849 + instr_size = NPE_A_42X_INSTR_SIZE;
3850 + else
3851 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
3852 + data_size = NPE_42X_DATA_SIZE;
3853 + } else {
3854 + instr_size = NPE_46X_INSTR_SIZE;
3855 + data_size = NPE_46X_DATA_SIZE;
3856 + }
3857 +
3858 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
3859 + blocks++)
3860 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
3861 + break;
3862 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
3863 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
3864 + "found\n");
3865 + goto err;
3866 + }
3867 +
3868 +#if DEBUG_FW
3869 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
3870 +#endif
3871 +
3872 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
3873 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
3874 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
3875 + || blk->offset < table_end) {
3876 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
3877 + "firmware block #%i\n", blk->offset, i);
3878 + goto err;
3879 + }
3880 +
3881 + cb = (struct dl_codeblock*)&image->data[blk->offset];
3882 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
3883 + if (cb->npe_addr + cb->size > instr_size)
3884 + goto too_big;
3885 + cmd = CMD_WR_INS_MEM;
3886 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
3887 + if (cb->npe_addr + cb->size > data_size)
3888 + goto too_big;
3889 + cmd = CMD_WR_DATA_MEM;
3890 + } else {
3891 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
3892 + "type 0x%X\n", i, blk->type);
3893 + goto err;
3894 + }
3895 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
3896 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
3897 + "fit in firmware image: type %c, start 0x%X,"
3898 + " length 0x%X\n", i,
3899 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
3900 + cb->npe_addr, cb->size);
3901 + goto err;
3902 + }
3903 +
3904 + for (j = 0; j < cb->size; j++)
3905 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
3906 + }
3907 +
3908 + npe_start(npe);
3909 + if (!npe_running(npe))
3910 + print_npe(KERN_ERR, npe, "unable to start\n");
3911 + release_firmware(fw_entry);
3912 + return 0;
3913 +
3914 +too_big:
3915 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
3916 + "memory: type %c, start 0x%X, length 0x%X\n", i,
3917 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
3918 + cb->npe_addr, cb->size);
3919 +err:
3920 + release_firmware(fw_entry);
3921 + return err;
3922 +}
3923 +
3924 +
3925 +struct npe *npe_request(int id)
3926 +{
3927 + if (id < NPE_COUNT)
3928 + if (npe_tab[id].valid)
3929 + if (try_module_get(THIS_MODULE))
3930 + return &npe_tab[id];
3931 + return NULL;
3932 +}
3933 +
3934 +void npe_release(struct npe *npe)
3935 +{
3936 + module_put(THIS_MODULE);
3937 +}
3938 +
3939 +
3940 +static int __init npe_init_module(void)
3941 +{
3942 +
3943 + int i, found = 0;
3944 +
3945 + for (i = 0; i < NPE_COUNT; i++) {
3946 + struct npe *npe = &npe_tab[i];
3947 + if (!(ixp4xx_read_feature_bits() &
3948 + (IXP4XX_FEATURE_RESET_NPEA << i)))
3949 + continue; /* NPE already disabled or not present */
3950 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
3951 + REGS_SIZE,
3952 + npe_name(npe)))) {
3953 + print_npe(KERN_ERR, npe,
3954 + "failed to request memory region\n");
3955 + continue;
3956 + }
3957 +
3958 + if (npe_reset(npe))
3959 + continue;
3960 + npe->valid = 1;
3961 + found++;
3962 + }
3963 +
3964 + if (!found)
3965 + return -ENOSYS;
3966 + return 0;
3967 +}
3968 +
3969 +static void __exit npe_cleanup_module(void)
3970 +{
3971 + int i;
3972 +
3973 + for (i = 0; i < NPE_COUNT; i++)
3974 + if (npe_tab[i].mem_res) {
3975 + npe_reset(&npe_tab[i]);
3976 + release_resource(npe_tab[i].mem_res);
3977 + }
3978 +}
3979 +
3980 +module_init(npe_init_module);
3981 +module_exit(npe_cleanup_module);
3982 +
3983 +MODULE_AUTHOR("Krzysztof Halasa");
3984 +MODULE_LICENSE("GPL v2");
3985 +
3986 +EXPORT_SYMBOL(npe_names);
3987 +EXPORT_SYMBOL(npe_running);
3988 +EXPORT_SYMBOL(npe_request);
3989 +EXPORT_SYMBOL(npe_release);
3990 +EXPORT_SYMBOL(npe_load_firmware);
3991 +EXPORT_SYMBOL(npe_send_message);
3992 +EXPORT_SYMBOL(npe_recv_message);
3993 +EXPORT_SYMBOL(npe_send_recv_message);
3994
3995
3996 From 35acb53f356e80efad803b9460986d9786dc9b96 Mon Sep 17 00:00:00 2001
3997 From: Krzysztof Halasa <khc@pm.waw.pl>
3998 Date: Tue, 29 Jan 2008 10:25:57 +1030
3999 Subject: Headers for IXP4xx built-in Ethernet and WAN drivers (Patch #4714)
4000
4001 Adds platform structs and #defines required by drivers for
4002 IXP4xx built-in Ethernet and WAN (sync serial) ports.
4003
4004 The actual drivers will reside in drivers/net/arm and
4005 drivers/net/wan and will be submitted separately.
4006
4007 Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
4008 Signed-off-by: Rod Whitby <rod@whitby.id.au>
4009
4010 PATCH FOLLOWS
4011 KernelVersion: 2.6.24-git5
4012
4013 diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
4014 index 2ce28e3..a1f2b54 100644
4015 --- a/include/asm-arm/arch-ixp4xx/platform.h
4016 +++ b/include/asm-arm/arch-ixp4xx/platform.h
4017 @@ -91,6 +91,27 @@ struct ixp4xx_pata_data {
4018
4019 struct sys_timer;
4020
4021 +#define IXP4XX_ETH_NPEA 0x00
4022 +#define IXP4XX_ETH_NPEB 0x10
4023 +#define IXP4XX_ETH_NPEC 0x20
4024 +
4025 +/* Information about built-in Ethernet MAC interfaces */
4026 +struct eth_plat_info {
4027 + u8 phy; /* MII PHY ID, 0 - 31 */
4028 + u8 rxq; /* configurable, currently 0 - 31 only */
4029 + u8 txreadyq;
4030 + u8 hwaddr[6];
4031 +};
4032 +
4033 +/* Information about built-in HSS (synchronous serial) interfaces */
4034 +struct hss_plat_info {
4035 + int (*set_clock)(int port, unsigned int clock_type);
4036 + int (*open)(int port, void *pdev,
4037 + void (*set_carrier_cb)(void *pdev, int carrier));
4038 + void (*close)(int port, void *pdev);
4039 + u8 txreadyq;
4040 +};
4041 +
4042 /*
4043 * Frequency of clock used for primary clocksource
4044 */
4045 --
4046 1.5.2.5
4047
4048 From 5a5be39c6411f2d6d8cead614f3f71af9fa4b4b4 Mon Sep 17 00:00:00 2001
4049 From: Krzysztof Halasa <khc@pm.waw.pl>
4050 Date: Fri, 1 Feb 2008 11:37:47 +1030
4051 Subject: Ethernet support for IXDP425 boards (Patch #4715)
4052
4053 Adds IXDP425 platform support for two built-in 10/100 Ethernet ports.
4054
4055 This patch will do nothing until the actual Ethernet driver is
4056 also included.
4057
4058 Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl>
4059 --
4060 PATCH FOLLOWS
4061 KernelVersion: 2.6.23
4062
4063 diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
4064 index e89070d..44584af 100644
4065 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
4066 +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
4067 @@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = {
4068 .resource = ixdp425_uart_resources
4069 };
4070
4071 +/* Built-in 10/100 Ethernet MAC interfaces */
4072 +static struct eth_plat_info ixdp425_plat_eth[] = {
4073 + {
4074 + .phy = 0,
4075 + .rxq = 3,
4076 + .txreadyq = 20,
4077 + }, {
4078 + .phy = 1,
4079 + .rxq = 4,
4080 + .txreadyq = 21,
4081 + }
4082 +};
4083 +
4084 +static struct platform_device ixdp425_eth[] = {
4085 + {
4086 + .name = "ixp4xx_eth",
4087 + .id = IXP4XX_ETH_NPEB,
4088 + .dev.platform_data = ixdp425_plat_eth,
4089 + }, {
4090 + .name = "ixp4xx_eth",
4091 + .id = IXP4XX_ETH_NPEC,
4092 + .dev.platform_data = ixdp425_plat_eth + 1,
4093 + }
4094 +};
4095 +
4096 static struct platform_device *ixdp425_devices[] __initdata = {
4097 &ixdp425_i2c_gpio,
4098 &ixdp425_flash,
4099 @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = {
4100 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
4101 &ixdp425_flash_nand,
4102 #endif
4103 - &ixdp425_uart
4104 + &ixdp425_uart,
4105 + &ixdp425_eth[0],
4106 + &ixdp425_eth[1],
4107 };
4108
4109 static void __init ixdp425_init(void)
4110 --
4111 1.5.2.5
4112
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