1 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/init.h>
5 #include <linux/delay.h>
7 #include <asm/danube/danube.h>
8 #include <asm/danube/danube_irq.h>
9 #include <asm/addrspace.h>
10 #include <linux/vmalloc.h>
12 #define IFXMIPS_PCI_MEM_BASE 0x18000000
13 #define IFXMIPS_PCI_MEM_SIZE 0x02000000
14 #define IFXMIPS_PCI_IO_BASE 0x1AE00000
15 #define IFXMIPS_PCI_IO_SIZE 0x00200000
17 #define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
18 #define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
19 #define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
21 #define PCI_ACCESS_READ 0
22 #define PCI_ACCESS_WRITE 1
24 static int danube_pci_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
);
25 static int danube_pci_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
);
27 struct pci_ops danube_pci_ops
= {
28 .read
= danube_pci_read_config_dword
,
29 .write
= danube_pci_write_config_dword
32 static struct resource pci_io_resource
= {
33 .name
= "io pci IO space",
34 .start
= IFXMIPS_PCI_IO_BASE
,
35 .end
= IFXMIPS_PCI_IO_BASE
+ IFXMIPS_PCI_IO_SIZE
- 1,
36 .flags
= IORESOURCE_IO
39 static struct resource pci_mem_resource
= {
40 .name
= "ext pci memory space",
41 .start
= IFXMIPS_PCI_MEM_BASE
,
42 .end
= IFXMIPS_PCI_MEM_BASE
+ IFXMIPS_PCI_MEM_SIZE
- 1,
43 .flags
= IORESOURCE_MEM
46 static struct pci_controller danube_pci_controller
= {
47 .pci_ops
= &danube_pci_ops
,
48 .mem_resource
= &pci_mem_resource
,
49 .mem_offset
= 0x00000000UL
,
50 .io_resource
= &pci_io_resource
,
51 .io_offset
= 0x00000000UL
,
54 static u32 danube_pci_mapped_cfg
;
57 danube_pci_config_access(unsigned char access_type
,
58 struct pci_bus
*bus
, unsigned int devfn
, unsigned int where
, u32
*data
)
60 unsigned long cfg_base
;
65 /* Danube support slot from 0 to 15 */
66 /* dev_fn 0&0x68 (AD29) is danube itself */
67 if ((bus
->number
!= 0) || ((devfn
& 0xf8) > 0x78)
68 || ((devfn
& 0xf8) == 0) || ((devfn
& 0xf8) == 0x68))
71 local_irq_save(flags
);
73 cfg_base
= danube_pci_mapped_cfg
;
74 cfg_base
|= (bus
->number
<< IFXMIPS_PCI_CFG_BUSNUM_SHF
) | (devfn
<<
75 IFXMIPS_PCI_CFG_FUNNUM_SHF
) | (where
& ~0x3);
78 if (access_type
== PCI_ACCESS_WRITE
)
80 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
81 writel(swab32(*data
), ((u32
*)cfg_base
));
83 writel(*data
, ((u32
*)cfg_base
));
86 *data
= readl(((u32
*)(cfg_base
)));
87 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
88 *data
= swab32(*data
);
93 /* clean possible Master abort */
94 cfg_base
= (danube_pci_mapped_cfg
| (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF
)) + 4;
95 temp
= readl(((u32
*)(cfg_base
)));
96 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
99 cfg_base
= (danube_pci_mapped_cfg
| (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF
)) + 4;
100 writel(temp
, ((u32
*)cfg_base
));
102 local_irq_restore(flags
);
104 if (((*data
) == 0xffffffff) && (access_type
== PCI_ACCESS_READ
))
110 static int danube_pci_read_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
111 int where
, int size
, u32
* val
)
115 if (danube_pci_config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
))
116 return PCIBIOS_DEVICE_NOT_FOUND
;
119 *val
= (data
>> ((where
& 3) << 3)) & 0xff;
121 *val
= (data
>> ((where
& 3) << 3)) & 0xffff;
125 return PCIBIOS_SUCCESSFUL
;
128 static int danube_pci_write_config_dword(struct pci_bus
*bus
, unsigned int devfn
,
129 int where
, int size
, u32 val
)
137 if (danube_pci_config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
))
138 return PCIBIOS_DEVICE_NOT_FOUND
;
141 data
= (data
& ~(0xff << ((where
& 3) << 3))) |
142 (val
<< ((where
& 3) << 3));
144 data
= (data
& ~(0xffff << ((where
& 3) << 3))) |
145 (val
<< ((where
& 3) << 3));
148 if (danube_pci_config_access(PCI_ACCESS_WRITE
, bus
, devfn
, where
, &data
))
149 return PCIBIOS_DEVICE_NOT_FOUND
;
151 return PCIBIOS_SUCCESSFUL
;
155 int pcibios_plat_dev_init(struct pci_dev
*dev
){
158 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
164 //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
165 printk("%s:%s[%d] %08X \n", __FILE__
, __func__
, __LINE__
, dev
->irq
);
166 writel(readl(IFXMIPS_EBU_PCC_CON
) | 0xc, IFXMIPS_EBU_PCC_CON
);
167 writel(readl(IFXMIPS_EBU_PCC_IEN
) | 0x10, IFXMIPS_EBU_PCC_IEN
);
172 printk ("WARNING: interrupt pin %d not supported yet!\n", pin
);
174 printk ("WARNING: invalid interrupt pin %d\n", pin
);
181 static void __init
danube_pci_startup (void){
182 /*initialize the first PCI device--danube itself */
184 /*TODO: trigger reset */
185 writel(readl(IFXMIPS_CGU_IFCCR
) & ~0xf00000, IFXMIPS_CGU_IFCCR
);
186 writel(readl(IFXMIPS_CGU_IFCCR
) | 0x800000, IFXMIPS_CGU_IFCCR
);
187 /* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
189 PADsel of PCI_CR of CGU : 1 =>From CGU
192 writel(readl(IFXMIPS_CGU_IFCCR
) | (1 << 16), IFXMIPS_CGU_IFCCR
);
193 writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR
);
196 /* PCI_RST: P1.5 ALT 01 */
197 //pliu20060613: start
198 writel(readl(IFXMIPS_GPIO_P1_OUT
) | (1 << 5), IFXMIPS_GPIO_P1_OUT
);
199 writel(readl(IFXMIPS_GPIO_P1_OD
) | (1 << 5), IFXMIPS_GPIO_P1_OD
);
200 writel(readl(IFXMIPS_GPIO_P1_DIR
) | (1 << 5), IFXMIPS_GPIO_P1_DIR
);
201 writel(readl(IFXMIPS_GPIO_P1_ALTSEL1
) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1
);
202 writel(readl(IFXMIPS_GPIO_P1_ALTSEL0
) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0
);
204 /* PCI_REQ1: P1.13 ALT 01 */
205 /* PCI_GNT1: P1.14 ALT 01 */
206 writel(readl(IFXMIPS_GPIO_P1_DIR
) & ~0x2000, IFXMIPS_GPIO_P1_DIR
);
207 writel(readl(IFXMIPS_GPIO_P1_DIR
) | 0x4000, IFXMIPS_GPIO_P1_DIR
);
208 writel(readl(IFXMIPS_GPIO_P1_ALTSEL1
) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1
);
209 writel(readl(IFXMIPS_GPIO_P1_ALTSEL0
) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0
);
210 /* PCI_REQ2: P1.15 ALT 10 */
211 /* PCI_GNT2: P1.7 ALT 10 */
214 /* enable auto-switching between PCI and EBU */
215 writel(0xa, PCI_CR_CLK_CTRL
);
216 /* busy, i.e. configuration is not done, PCI access has to be retried */
217 writel(readl(PCI_CR_PCI_MOD
) & ~(1 << 24), PCI_CR_PCI_MOD
);
219 /* BUS Master/IO/MEM access */
220 writel(readl(PCI_CS_STS_CMD
) | 7, PCI_CS_STS_CMD
);
222 temp_buffer
= readl(PCI_CR_PC_ARB
);
223 /* enable external 2 PCI masters */
224 temp_buffer
&= (~(0xf << 16));
225 /* enable internal arbiter */
226 temp_buffer
|= (1 << INTERNAL_ARB_ENABLE_BIT
);
227 /* enable internal PCI master reqest */
228 temp_buffer
&= (~(3 << PCI_MASTER0_REQ_MASK_2BITS
));
230 /* enable EBU reqest */
231 temp_buffer
&= (~(3 << PCI_MASTER1_REQ_MASK_2BITS
));
233 /* enable all external masters request */
234 temp_buffer
&= (~(3 << PCI_MASTER2_REQ_MASK_2BITS
));
235 writel(temp_buffer
, PCI_CR_PC_ARB
);
239 /* FPI ==> PCI MEM address mapping */
240 /* base: 0xb8000000 == > 0x18000000 */
241 /* size: 8x4M = 32M */
242 writel(0x18000000, PCI_CR_FCI_ADDR_MAP0
);
243 writel(0x18400000, PCI_CR_FCI_ADDR_MAP1
);
244 writel(0x18800000, PCI_CR_FCI_ADDR_MAP2
);
245 writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3
);
246 writel(0x19000000, PCI_CR_FCI_ADDR_MAP4
);
247 writel(0x19400000, PCI_CR_FCI_ADDR_MAP5
);
248 writel(0x19800000, PCI_CR_FCI_ADDR_MAP6
);
249 writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7
);
251 /* FPI ==> PCI IO address mapping */
252 /* base: 0xbAE00000 == > 0xbAE00000 */
254 writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg
);
256 /* PCI ==> FPI address mapping */
257 /* base: 0x0 ==> 0x0 */
259 /* BAR1 32M map to SDR address */
260 writel(0x0e000008, PCI_CR_BAR11MASK
);
261 writel(0, PCI_CR_PCI_ADDR_MAP11
);
262 writel(0, PCI_CS_BASE_ADDR1
);
263 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
264 /* both TX and RX endian swap are enabled */
265 IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG
) |= 3;
268 /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
269 writel(readl(PCI_CR_BAR12MASK
) | 0x80000000, PCI_CR_BAR12MASK
);
270 writel(readl(PCI_CR_BAR13MASK
) | 0x80000000, PCI_CR_BAR13MASK
);
271 /*use 8 dw burse length */
272 writel(0x303, PCI_CR_FCI_BURST_LENGTH
);
274 writel(readl(PCI_CR_PCI_MOD
) | (1 << 24), PCI_CR_PCI_MOD
);
276 writel(readl(IFXMIPS_GPIO_P1_OUT
) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT
);
279 writel(readl(IFXMIPS_GPIO_P1_OUT
) | (1 << 5), IFXMIPS_GPIO_P1_OUT
);
282 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
){
283 printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__
, __func__
, __LINE__
, slot
, pin
);
286 /* IDSEL = AD29 --> USB Host Controller */
287 return (INT_NUM_IM1_IRL0
+ 17);
289 /* IDSEL = AD30 --> mini PCI connector */
290 //return (INT_NUM_IM1_IRL0 + 14);
291 return (INT_NUM_IM0_IRL0
+ 22);
293 printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot
, pin
);
298 int pcibios_init(void){
299 extern int pci_probe_only
;
302 printk ("PCI: Probing PCI hardware on host bus 0.\n");
304 danube_pci_startup ();
306 // IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
307 danube_pci_mapped_cfg
= ioremap_nocache(0x17000000, 0x800 * 16);
308 printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg
);
310 danube_pci_controller
.io_map_base
= (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE
, IFXMIPS_PCI_IO_SIZE
- 1);
312 printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller
.io_map_base
);
314 register_pci_controller(&danube_pci_controller
);
319 arch_initcall(pcibios_init
);