target/linux/brcm47xx/patches-3.2/220-bcm5354.patch

   1 From 6d174f732e198aae8583cc5414b11b988bfd37a9 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Mon, 30 Jan 2012 22:44:15 +0100
   4 Subject: [PATCH 4/4] ssb: add support for bcm5354
   5
   6 This patch adds support the the BCM5354 SoC.
   7 It has a PMU and a constant not configurable clock.
   8
   9 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  10 ---
  11  drivers/ssb/driver_chipcommon_pmu.c |   48 +++++++++++++++++++++++++++++++---
  12  drivers/ssb/driver_mipscore.c       |    3 ++
  13  drivers/ssb/main.c                  |    3 ++
  14  drivers/ssb/ssb_private.h           |    4 +++
  15  4 files changed, 53 insertions(+), 5 deletions(-)
  16
  17 diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
  18 index e5a2e0e..b58fef7 100644
  19 --- a/drivers/ssb/driver_chipcommon_pmu.c
  20 +++ b/drivers/ssb/driver_chipcommon_pmu.c
  21 @@ -13,6 +13,9 @@
  22  #include <linux/ssb/ssb_driver_chipcommon.h>
  23  #include <linux/delay.h>
  24  #include <linux/export.h>
  25 +#ifdef CONFIG_BCM47XX
  26 +#include <asm/mach-bcm47xx/nvram.h>
  27 +#endif
  28
  29  #include "ssb_private.h"
  30
  31 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
  32         u32 pmuctl, tmp, pllctl;
  33         unsigned int i;
  34
  35 -       if ((bus->chip_id == 0x5354) && !crystalfreq) {
  36 -               /* The 5354 crystal freq is 25MHz */
  37 -               crystalfreq = 25000;
  38 -       }
  39         if (crystalfreq)
  40                 e = pmu0_plltab_find_entry(crystalfreq);
  41         if (!e)
  42 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
  43         u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
  44
  45         if (bus->bustype == SSB_BUSTYPE_SSB) {
  46 -               /* TODO: The user may override the crystal frequency. */
  47 +#ifdef CONFIG_BCM47XX
  48 +               char buf[20];
  49 +               if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
  50 +                       crystalfreq = simple_strtoul(buf, NULL, 0);
  51 +#endif
  52         }
  53
  54         switch (bus->chip_id) {
  55 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
  56                 ssb_pmu1_pllinit_r0(cc, crystalfreq);
  57                 break;
  58         case 0x4328:
  59 +               ssb_pmu0_pllinit_r0(cc, crystalfreq);
  60 +               break;
  61         case 0x5354:
  62 +               if (crystalfreq == 0)
  63 +                       crystalfreq = 25000;
  64                 ssb_pmu0_pllinit_r0(cc, crystalfreq);
  65                 break;
  66         case 0x4322:
  67 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
  68
  69  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
  70  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
  71 +
  72 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
  73 +{
  74 +       struct ssb_bus *bus = cc->dev->bus;
  75 +
  76 +       switch (bus->chip_id) {
  77 +       case 0x5354:
  78 +               /* 5354 chip uses a non programmable PLL of frequency 240MHz */
  79 +               return 240000000;
  80 +       default:
  81 +               ssb_printk(KERN_ERR PFX
  82 +                          "ERROR: PMU cpu clock unknown for device %04X\n",
  83 +                          bus->chip_id);
  84 +               return 0;
  85 +       }
  86 +}
  87 +
  88 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
  89 +{
  90 +       struct ssb_bus *bus = cc->dev->bus;
  91 +
  92 +       switch (bus->chip_id) {
  93 +       case 0x5354:
  94 +               return 120000000;
  95 +       default:
  96 +               ssb_printk(KERN_ERR PFX
  97 +                          "ERROR: PMU controlclock unknown for device %04X\n",
  98 +                          bus->chip_id);
  99 +               return 0;
 100 +       }
 101 +}
 102 diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
 103 index ced5015..d784ec8 100644
 104 --- a/drivers/ssb/driver_mipscore.c
 105 +++ b/drivers/ssb/driver_mipscore.c
 106 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
 107         struct ssb_bus *bus = mcore->dev->bus;
 108         u32 pll_type, n, m, rate = 0;
 109
 110 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 111 +               return ssb_pmu_get_cpu_clock(&bus->chipco);
 112 +
 113         if (bus->extif.dev) {
 114                 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
 115         } else if (bus->chipco.dev) {
 116 diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
 117 index bb6317f..d109cf0 100644
 118 --- a/drivers/ssb/main.c
 119 +++ b/drivers/ssb/main.c
 120 @@ -1094,6 +1094,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
 121         u32 plltype;
 122         u32 clkctl_n, clkctl_m;
 123
 124 +       if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
 125 +               return ssb_pmu_get_controlclock(&bus->chipco);
 126 +
 127         if (ssb_extif_available(&bus->extif))
 128                 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
 129                                            &clkctl_n, &clkctl_m);
 130 diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
 131 index 7765301..a305550 100644
 132 --- a/drivers/ssb/ssb_private.h
 133 +++ b/drivers/ssb/ssb_private.h
 134 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_exit(void)
 135  }
 136  #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
 137
 138 +/* driver_chipcommon_pmu.c */
 139 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
 140 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
 141 +
 142  #endif /* LINUX_SSB_PRIVATE_H_ */
 143 --
 144 1.7.5.4
 145