3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; see the file COPYING. If not, write to
23 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
24 Boston, MA 02110-1301, USA.
28 #include <linux/delay.h>
29 #include <linux/types.h>
32 #include "bcm43xx_phy.h"
33 #include "bcm43xx_main.h"
34 #include "bcm43xx_tables.h"
35 #include "bcm43xx_power.h"
36 #include "bcm43xx_lo.h"
39 static const s8 bcm43xx_tssi2dbm_b_table
[] = {
40 0x4D, 0x4C, 0x4B, 0x4A,
41 0x4A, 0x49, 0x48, 0x47,
42 0x47, 0x46, 0x45, 0x45,
43 0x44, 0x43, 0x42, 0x42,
44 0x41, 0x40, 0x3F, 0x3E,
45 0x3D, 0x3C, 0x3B, 0x3A,
46 0x39, 0x38, 0x37, 0x36,
47 0x35, 0x34, 0x32, 0x31,
48 0x30, 0x2F, 0x2D, 0x2C,
49 0x2B, 0x29, 0x28, 0x26,
50 0x25, 0x23, 0x21, 0x1F,
51 0x1D, 0x1A, 0x17, 0x14,
52 0x10, 0x0C, 0x06, 0x00,
58 static const s8 bcm43xx_tssi2dbm_g_table
[] = {
77 const u8 bcm43xx_radio_channel_codes_bg
[] = {
85 static void bcm43xx_phy_initg(struct bcm43xx_wldev
*dev
);
87 /* Reverse the bits of a 4bit value.
88 * Example: 1101 is flipped 1011
90 static u16
flip_4bit(u16 value
)
94 assert((value
& ~0x000F) == 0x0000);
96 flipped
|= (value
& 0x0001) << 3;
97 flipped
|= (value
& 0x0002) << 1;
98 flipped
|= (value
& 0x0004) >> 1;
99 flipped
|= (value
& 0x0008) >> 3;
104 static void generate_rfatt_list(struct bcm43xx_wldev
*dev
,
105 struct bcm43xx_rfatt_list
*list
)
107 struct bcm43xx_phy
*phy
= &dev
->phy
;
109 /* APHY.rev < 5 || GPHY.rev < 6 */
110 static const struct bcm43xx_rfatt rfatt_0
[] = {
111 { .att
= 3, .with_padmix
= 0, },
112 { .att
= 1, .with_padmix
= 0, },
113 { .att
= 5, .with_padmix
= 0, },
114 { .att
= 7, .with_padmix
= 0, },
115 { .att
= 9, .with_padmix
= 0, },
116 { .att
= 2, .with_padmix
= 0, },
117 { .att
= 0, .with_padmix
= 0, },
118 { .att
= 4, .with_padmix
= 0, },
119 { .att
= 6, .with_padmix
= 0, },
120 { .att
= 8, .with_padmix
= 0, },
121 { .att
= 1, .with_padmix
= 1, },
122 { .att
= 2, .with_padmix
= 1, },
123 { .att
= 3, .with_padmix
= 1, },
124 { .att
= 4, .with_padmix
= 1, },
126 /* Radio.rev == 8 && Radio.version == 0x2050 */
127 static const struct bcm43xx_rfatt rfatt_1
[] = {
128 { .att
= 2, .with_padmix
= 1, },
129 { .att
= 4, .with_padmix
= 1, },
130 { .att
= 6, .with_padmix
= 1, },
131 { .att
= 8, .with_padmix
= 1, },
132 { .att
= 10, .with_padmix
= 1, },
133 { .att
= 12, .with_padmix
= 1, },
134 { .att
= 14, .with_padmix
= 1, },
137 static const struct bcm43xx_rfatt rfatt_2
[] = {
138 { .att
= 0, .with_padmix
= 1, },
139 { .att
= 2, .with_padmix
= 1, },
140 { .att
= 4, .with_padmix
= 1, },
141 { .att
= 6, .with_padmix
= 1, },
142 { .att
= 8, .with_padmix
= 1, },
143 { .att
= 9, .with_padmix
= 1, },
144 { .att
= 9, .with_padmix
= 1, },
147 if ((phy
->type
== BCM43xx_PHYTYPE_A
&& phy
->rev
< 5) ||
148 (phy
->type
== BCM43xx_PHYTYPE_G
&& phy
->rev
< 6)) {
150 list
->list
= rfatt_0
;
151 list
->len
= ARRAY_SIZE(rfatt_0
);
156 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
158 list
->list
= rfatt_1
;
159 list
->len
= ARRAY_SIZE(rfatt_1
);
165 list
->list
= rfatt_2
;
166 list
->len
= ARRAY_SIZE(rfatt_2
);
171 static void generate_bbatt_list(struct bcm43xx_wldev
*dev
,
172 struct bcm43xx_bbatt_list
*list
)
174 static const struct bcm43xx_bbatt bbatt_0
[] = {
186 list
->list
= bbatt_0
;
187 list
->len
= ARRAY_SIZE(bbatt_0
);
192 static void bcm43xx_shm_clear_tssi(struct bcm43xx_wldev
*dev
)
194 struct bcm43xx_phy
*phy
= &dev
->phy
;
197 case BCM43xx_PHYTYPE_A
:
198 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0068, 0x7F7F);
199 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x006a, 0x7F7F);
201 case BCM43xx_PHYTYPE_B
:
202 case BCM43xx_PHYTYPE_G
:
203 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0058, 0x7F7F);
204 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x005a, 0x7F7F);
205 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0070, 0x7F7F);
206 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0072, 0x7F7F);
211 void bcm43xx_raw_phy_lock(struct bcm43xx_wldev
*dev
)
213 struct bcm43xx_phy
*phy
= &dev
->phy
;
215 assert(irqs_disabled());
216 if (bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
) == 0) {
220 if (dev
->dev
->id
.revision
< 3) {
221 bcm43xx_mac_suspend(dev
);
222 spin_lock(&phy
->lock
);
224 if (!bcm43xx_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
))
225 bcm43xx_power_saving_ctl_bits(dev
, -1, 1);
230 void bcm43xx_raw_phy_unlock(struct bcm43xx_wldev
*dev
)
232 struct bcm43xx_phy
*phy
= &dev
->phy
;
234 assert(irqs_disabled());
235 if (dev
->dev
->id
.revision
< 3) {
237 spin_unlock(&phy
->lock
);
238 bcm43xx_mac_enable(dev
);
241 if (!bcm43xx_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
))
242 bcm43xx_power_saving_ctl_bits(dev
, -1, -1);
247 /* Different PHYs require different register routing flags.
248 * This adjusts (and does sanity checks on) the routing flags.
250 static inline u16
adjust_phyreg_for_phytype(struct bcm43xx_phy
*phy
,
253 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
254 /* OFDM registers are base-registers for the A-PHY. */
255 offset
&= ~BCM43xx_PHYROUTE_OFDM_GPHY
;
257 if (offset
& BCM43xx_PHYROUTE_EXT_GPHY
) {
258 /* Ext-G registers are only available on G-PHYs */
259 if (phy
->type
!= BCM43xx_PHYTYPE_G
) {
260 dprintk(KERN_ERR PFX
"EXT-G PHY access at "
261 "0x%04X on %u type PHY\n",
269 u16
bcm43xx_phy_read(struct bcm43xx_wldev
*dev
, u16 offset
)
271 struct bcm43xx_phy
*phy
= &dev
->phy
;
273 offset
= adjust_phyreg_for_phytype(phy
, offset
);
274 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY_CONTROL
, offset
);
275 return bcm43xx_read16(dev
, BCM43xx_MMIO_PHY_DATA
);
278 void bcm43xx_phy_write(struct bcm43xx_wldev
*dev
, u16 offset
, u16 val
)
280 struct bcm43xx_phy
*phy
= &dev
->phy
;
282 offset
= adjust_phyreg_for_phytype(phy
, offset
);
283 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY_CONTROL
, offset
);
285 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY_DATA
, val
);
288 /* This func is called "PHY calibrate" in the specs... */
289 void bcm43xx_phy_early_init(struct bcm43xx_wldev
*dev
)
291 struct bcm43xx_phy
*phy
= &dev
->phy
;
292 struct bcm43xx_txpower_lo_control
*lo
= phy
->lo_control
;
294 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
); /* Dummy read. */
295 if (phy
->type
== BCM43xx_PHYTYPE_B
||
296 phy
->type
== BCM43xx_PHYTYPE_G
) {
297 generate_rfatt_list(dev
, &lo
->rfatt_list
);
298 generate_bbatt_list(dev
, &lo
->bbatt_list
);
300 if (phy
->type
== BCM43xx_PHYTYPE_G
&& phy
->rev
== 1) {
301 /* Workaround: Temporarly disable gmode through the early init
302 * phase, as the gmode stuff is not needed for phy rev 1 */
304 bcm43xx_wireless_core_reset(dev
, 0);
305 bcm43xx_phy_initg(dev
);
307 bcm43xx_wireless_core_reset(dev
, BCM43xx_TMSLOW_GMODE
);
311 /* GPHY_TSSI_Power_Lookup_Table_Init */
312 static void bcm43xx_gphy_tssi_power_lt_init(struct bcm43xx_wldev
*dev
)
314 struct bcm43xx_phy
*phy
= &dev
->phy
;
318 for (i
= 0; i
< 32; i
++)
319 bcm43xx_ofdmtab_write16(dev
, 0x3C20, i
, phy
->tssi2dbm
[i
]);
320 for (i
= 32; i
< 64; i
++)
321 bcm43xx_ofdmtab_write16(dev
, 0x3C00, i
- 32, phy
->tssi2dbm
[i
]);
322 for (i
= 0; i
< 64; i
+= 2) {
323 value
= (u16
)phy
->tssi2dbm
[i
];
324 value
|= ((u16
)phy
->tssi2dbm
[i
+ 1]) << 8;
325 bcm43xx_phy_write(dev
, 0x380 + (i
/ 2), value
);
329 /* GPHY_Gain_Lookup_Table_Init */
330 static void bcm43xx_gphy_gain_lt_init(struct bcm43xx_wldev
*dev
)
332 struct bcm43xx_phy
*phy
= &dev
->phy
;
333 struct bcm43xx_txpower_lo_control
*lo
= phy
->lo_control
;
338 if (!lo
->lo_measured
) {
339 bcm43xx_phy_write(dev
, 0x3FF, 0);
343 for (rf
= 0; rf
< lo
->rfatt_list
.len
; rf
++) {
344 for (bb
= 0; bb
< lo
->bbatt_list
.len
; bb
++) {
345 if (nr_written
>= 0x40)
347 tmp
= lo
->bbatt_list
.list
[bb
].att
;
349 if (phy
->radio_rev
== 8)
353 tmp
|= lo
->rfatt_list
.list
[rf
].att
;
354 bcm43xx_phy_write(dev
, 0x3C0 + nr_written
,
361 /* GPHY_DC_Lookup_Table */
362 void bcm43xx_gphy_dc_lt_init(struct bcm43xx_wldev
*dev
)
364 struct bcm43xx_phy
*phy
= &dev
->phy
;
365 struct bcm43xx_txpower_lo_control
*lo
= phy
->lo_control
;
366 struct bcm43xx_loctl
*loctl0
;
367 struct bcm43xx_loctl
*loctl1
;
369 int rf_offset
, bb_offset
;
373 i
< lo
->rfatt_list
.len
+ lo
->bbatt_list
.len
;
375 rf_offset
= i
/ lo
->rfatt_list
.len
;
376 bb_offset
= i
% lo
->rfatt_list
.len
;
378 loctl0
= bcm43xx_get_lo_g_ctl(dev
, &lo
->rfatt_list
.list
[rf_offset
],
379 &lo
->bbatt_list
.list
[bb_offset
]);
380 if (i
+ 1 < lo
->rfatt_list
.len
* lo
->bbatt_list
.len
) {
381 rf_offset
= (i
+ 1) / lo
->rfatt_list
.len
;
382 bb_offset
= (i
+ 1) % lo
->rfatt_list
.len
;
384 loctl1
= bcm43xx_get_lo_g_ctl(dev
, &lo
->rfatt_list
.list
[rf_offset
],
385 &lo
->bbatt_list
.list
[bb_offset
]);
389 tmp
= ((u16
)loctl0
->q
& 0xF);
390 tmp
|= ((u16
)loctl0
->i
& 0xF) << 4;
391 tmp
|= ((u16
)loctl1
->q
& 0xF) << 8;
392 tmp
|= ((u16
)loctl1
->i
& 0xF) << 12;//FIXME?
393 bcm43xx_phy_write(dev
, 0x3A0 + (i
/ 2),
398 static void hardware_pctl_init_aphy(struct bcm43xx_wldev
*dev
)
403 static void hardware_pctl_init_gphy(struct bcm43xx_wldev
*dev
)
405 struct bcm43xx_phy
*phy
= &dev
->phy
;
407 bcm43xx_phy_write(dev
, 0x0036,
408 (bcm43xx_phy_read(dev
, 0x0036) & 0xFFC0)
409 | (phy
->tgt_idle_tssi
- phy
->cur_idle_tssi
));
410 bcm43xx_phy_write(dev
, 0x0478,
411 (bcm43xx_phy_read(dev
, 0x0478) & 0xFF00)
412 | (phy
->tgt_idle_tssi
- phy
->cur_idle_tssi
));
413 bcm43xx_gphy_tssi_power_lt_init(dev
);
414 bcm43xx_gphy_gain_lt_init(dev
);
415 bcm43xx_phy_write(dev
, 0x0060,
416 bcm43xx_phy_read(dev
, 0x0060) & 0xFFBF);
417 bcm43xx_phy_write(dev
, 0x0014, 0x0000);
419 assert(phy
->rev
>= 6);
420 bcm43xx_phy_write(dev
, 0x0478,
421 bcm43xx_phy_read(dev
, 0x0478)
423 bcm43xx_phy_write(dev
, 0x0478,
424 bcm43xx_phy_read(dev
, 0x0478)
426 bcm43xx_phy_write(dev
, 0x0801,
427 bcm43xx_phy_read(dev
, 0x0801)
430 bcm43xx_gphy_dc_lt_init(dev
);
433 /* HardwarePowerControl for A and G PHY.
434 * This does nothing, if the card does not have HW PCTL
436 static void bcm43xx_hardware_pctl_init(struct bcm43xx_wldev
*dev
)
438 struct bcm43xx_phy
*phy
= &dev
->phy
;
440 if (!has_hardware_pctl(phy
))
442 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
443 hardware_pctl_init_aphy(dev
);
446 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
447 hardware_pctl_init_gphy(dev
);
453 static void bcm43xx_hardware_pctl_early_init(struct bcm43xx_wldev
*dev
)
455 struct bcm43xx_phy
*phy
= &dev
->phy
;
457 if (!has_hardware_pctl(phy
)) {
458 bcm43xx_phy_write(dev
, 0x047A, 0xC111);
462 bcm43xx_phy_write(dev
, 0x0036,
463 bcm43xx_phy_read(dev
, 0x0036) & 0xFEFF);
464 bcm43xx_phy_write(dev
, 0x002F, 0x0202);
465 bcm43xx_phy_write(dev
, 0x047C,
466 bcm43xx_phy_read(dev
, 0x047C) | 0x0002);
467 bcm43xx_phy_write(dev
, 0x047A,
468 bcm43xx_phy_read(dev
, 0x047A) | 0xF000);
469 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
470 bcm43xx_phy_write(dev
, 0x047A,
471 (bcm43xx_phy_read(dev
, 0x047A)
473 bcm43xx_phy_write(dev
, 0x005D,
474 bcm43xx_phy_read(dev
, 0x005D)
476 bcm43xx_phy_write(dev
, 0x004E,
477 (bcm43xx_phy_read(dev
, 0x004E)
479 bcm43xx_phy_write(dev
, 0x002E, 0xC07F);
480 bcm43xx_phy_write(dev
, 0x0036,
481 bcm43xx_phy_read(dev
, 0x0036)
484 bcm43xx_phy_write(dev
, 0x0036,
485 bcm43xx_phy_read(dev
, 0x0036)
487 bcm43xx_phy_write(dev
, 0x0036,
488 bcm43xx_phy_read(dev
, 0x0036)
490 bcm43xx_phy_write(dev
, 0x005D,
491 bcm43xx_phy_read(dev
, 0x005D)
493 bcm43xx_phy_write(dev
, 0x004F,
494 bcm43xx_phy_read(dev
, 0x004F)
496 bcm43xx_phy_write(dev
, 0x004E,
497 (bcm43xx_phy_read(dev
, 0x004E)
499 bcm43xx_phy_write(dev
, 0x002E, 0xC07F);
500 bcm43xx_phy_write(dev
, 0x047A,
501 (bcm43xx_phy_read(dev
, 0x047A)
506 /* Intialize B/G PHY power control
507 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
509 static void bcm43xx_phy_init_pctl(struct bcm43xx_wldev
*dev
)
511 struct ssb_bus
*bus
= dev
->dev
->bus
;
512 struct bcm43xx_phy
*phy
= &dev
->phy
;
514 if ((bus
->board_vendor
== SSB_BOARDVENDOR_BCM
) &&
515 (bus
->board_type
== SSB_BOARD_BU4306
))
518 bcm43xx_phy_write(dev
, 0x0028, 0x8018);
520 /* This does something with the Analog... */
521 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY0
,
522 bcm43xx_read16(dev
, BCM43xx_MMIO_PHY0
)
525 if (phy
->type
== BCM43xx_PHYTYPE_G
&& !phy
->gmode
)
527 bcm43xx_hardware_pctl_early_init(dev
);
528 if (phy
->cur_idle_tssi
== 0) {
529 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
530 bcm43xx_radio_write16(dev
, 0x0076,
531 (bcm43xx_radio_read16(dev
, 0x0076)
534 if (phy
->radio_rev
== 8)
535 bcm43xx_radio_set_txpower_bg(dev
, 0xB, 0x1F, 0);
537 bcm43xx_radio_set_txpower_bg(dev
, 0xB, 9, 0);
539 bcm43xx_dummy_transmission(dev
);
540 phy
->cur_idle_tssi
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ITSSI
);
542 /* Current-Idle-TSSI sanity check. */
543 if (abs(phy
->cur_idle_tssi
- phy
->tgt_idle_tssi
) >= 20) {
544 dprintk(KERN_ERR PFX
"!WARNING! Idle-TSSI phy->cur_idle_tssi "
545 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
546 "adjustment.\n", phy
->cur_idle_tssi
, phy
->tgt_idle_tssi
);
547 phy
->cur_idle_tssi
= 0;
551 if (phy
->radio_ver
== 0x2050 && phy
->analog
== 0) {
552 bcm43xx_radio_write16(dev
, 0x0076,
553 bcm43xx_radio_read16(dev
, 0x0076)
556 bcm43xx_radio_set_txpower_bg(dev
, -1, -1, -1);
558 bcm43xx_hardware_pctl_init(dev
);
559 bcm43xx_shm_clear_tssi(dev
);
562 static void bcm43xx_phy_agcsetup(struct bcm43xx_wldev
*dev
)
564 struct bcm43xx_phy
*phy
= &dev
->phy
;
570 bcm43xx_ofdmtab_write16(dev
, offset
, 0, 0x00FE);
571 bcm43xx_ofdmtab_write16(dev
, offset
, 1, 0x000D);
572 bcm43xx_ofdmtab_write16(dev
, offset
, 2, 0x0013);
573 bcm43xx_ofdmtab_write16(dev
, offset
, 3, 0x0019);
576 bcm43xx_ofdmtab_write16(dev
, 0x1800, 0, 0x2710);
577 bcm43xx_ofdmtab_write16(dev
, 0x1801, 0, 0x9B83);
578 bcm43xx_ofdmtab_write16(dev
, 0x1802, 0, 0x9B83);
579 bcm43xx_ofdmtab_write16(dev
, 0x1803, 0, 0x0F8D);
580 bcm43xx_phy_write(dev
, 0x0455, 0x0004);
583 bcm43xx_phy_write(dev
, 0x04A5,
584 (bcm43xx_phy_read(dev
, 0x04A5)
586 bcm43xx_phy_write(dev
, 0x041A,
587 (bcm43xx_phy_read(dev
, 0x041A)
589 bcm43xx_phy_write(dev
, 0x041A,
590 (bcm43xx_phy_read(dev
, 0x041A)
592 bcm43xx_phy_write(dev
, 0x048C,
593 (bcm43xx_phy_read(dev
, 0x048C)
596 bcm43xx_radio_write16(dev
, 0x007A,
597 bcm43xx_radio_read16(dev
, 0x007A)
600 bcm43xx_phy_write(dev
, 0x04A0,
601 (bcm43xx_phy_read(dev
, 0x04A0)
603 bcm43xx_phy_write(dev
, 0x04A1,
604 (bcm43xx_phy_read(dev
, 0x04A1)
606 bcm43xx_phy_write(dev
, 0x04A2,
607 (bcm43xx_phy_read(dev
, 0x04A2)
609 bcm43xx_phy_write(dev
, 0x04A0,
610 (bcm43xx_phy_read(dev
, 0x04A0)
614 bcm43xx_phy_write(dev
, 0x04A2,
615 (bcm43xx_phy_read(dev
, 0x04A2)
619 bcm43xx_phy_write(dev
, 0x0488,
620 (bcm43xx_phy_read(dev
, 0x0488)
622 bcm43xx_phy_write(dev
, 0x0488,
623 (bcm43xx_phy_read(dev
, 0x0488)
625 bcm43xx_phy_write(dev
, 0x0496,
626 (bcm43xx_phy_read(dev
, 0x0496)
628 bcm43xx_phy_write(dev
, 0x0489,
629 (bcm43xx_phy_read(dev
, 0x0489)
631 bcm43xx_phy_write(dev
, 0x0489,
632 (bcm43xx_phy_read(dev
, 0x0489)
634 bcm43xx_phy_write(dev
, 0x0482,
635 (bcm43xx_phy_read(dev
, 0x0482)
637 bcm43xx_phy_write(dev
, 0x0496,
638 (bcm43xx_phy_read(dev
, 0x0496)
640 bcm43xx_phy_write(dev
, 0x0481,
641 (bcm43xx_phy_read(dev
, 0x0481)
643 bcm43xx_phy_write(dev
, 0x0481,
644 (bcm43xx_phy_read(dev
, 0x0481)
648 bcm43xx_phy_write(dev
, 0x0430, 0x092B);
649 bcm43xx_phy_write(dev
, 0x041B,
650 (bcm43xx_phy_read(dev
, 0x041B)
653 bcm43xx_phy_write(dev
, 0x041B,
654 bcm43xx_phy_read(dev
, 0x041B)
656 bcm43xx_phy_write(dev
, 0x041F, 0x287A);
657 bcm43xx_phy_write(dev
, 0x0420,
658 (bcm43xx_phy_read(dev
, 0x0420)
663 bcm43xx_phy_write(dev
, 0x0422, 0x287A);
664 bcm43xx_phy_write(dev
, 0x0420,
665 (bcm43xx_phy_read(dev
, 0x0420)
669 bcm43xx_phy_write(dev
, 0x04A8,
670 (bcm43xx_phy_read(dev
, 0x04A8)
672 bcm43xx_phy_write(dev
, 0x048E, 0x1C00);
677 bcm43xx_phy_write(dev
, 0x04AB,
678 (bcm43xx_phy_read(dev
, 0x04AB)
680 bcm43xx_phy_write(dev
, 0x048B, 0x005E);
681 bcm43xx_phy_write(dev
, 0x048C,
682 (bcm43xx_phy_read(dev
, 0x048C)
684 bcm43xx_phy_write(dev
, 0x048D, 0x0002);
686 bcm43xx_ofdmtab_write16(dev
, offset
, 0, 0x00);
687 bcm43xx_ofdmtab_write16(dev
, offset
, 1, 0x07);
688 bcm43xx_ofdmtab_write16(dev
, offset
, 2, 0x10);
689 bcm43xx_ofdmtab_write16(dev
, offset
, 3, 0x1C);
692 bcm43xx_phy_write(dev
, 0x0426,
693 bcm43xx_phy_read(dev
, 0x0426)
695 bcm43xx_phy_write(dev
, 0x0426,
696 bcm43xx_phy_read(dev
, 0x0426)
701 static void bcm43xx_phy_setupg(struct bcm43xx_wldev
*dev
)
703 struct ssb_bus
*bus
= dev
->dev
->bus
;
704 struct bcm43xx_phy
*phy
= &dev
->phy
;
707 assert(phy
->type
== BCM43xx_PHYTYPE_G
);
709 bcm43xx_phy_write(dev
, 0x0406, 0x4F19);
710 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
711 (bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) & 0xFC3F) | 0x0340);
712 bcm43xx_phy_write(dev
, 0x042C, 0x005A);
713 bcm43xx_phy_write(dev
, 0x0427, 0x001A);
715 for (i
= 0; i
< BCM43xx_TAB_FINEFREQG_SIZE
; i
++)
716 bcm43xx_ofdmtab_write16(dev
, 0x5800, i
, bcm43xx_tab_finefreqg
[i
]);
717 for (i
= 0; i
< BCM43xx_TAB_NOISEG1_SIZE
; i
++)
718 bcm43xx_ofdmtab_write16(dev
, 0x1800, i
, bcm43xx_tab_noiseg1
[i
]);
719 for (i
= 0; i
< BCM43xx_TAB_ROTOR_SIZE
; i
++)
720 bcm43xx_ofdmtab_write16(dev
, 0x2000, i
, bcm43xx_tab_rotor
[i
]);
722 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
723 bcm43xx_nrssi_hw_write(dev
, 0xBA98, (s16
)0x7654);
726 bcm43xx_phy_write(dev
, 0x04C0, 0x1861);
727 bcm43xx_phy_write(dev
, 0x04C1, 0x0271);
728 } else if (phy
->rev
> 2) {
729 bcm43xx_phy_write(dev
, 0x04C0, 0x0098);
730 bcm43xx_phy_write(dev
, 0x04C1, 0x0070);
731 bcm43xx_phy_write(dev
, 0x04C9, 0x0080);
733 bcm43xx_phy_write(dev
, 0x042B, bcm43xx_phy_read(dev
, 0x042B) | 0x800);
735 for (i
= 0; i
< 64; i
++)
736 bcm43xx_ofdmtab_write16(dev
, 0x4000, i
, i
);
737 for (i
= 0; i
< BCM43xx_TAB_NOISEG2_SIZE
; i
++)
738 bcm43xx_ofdmtab_write16(dev
, 0x1800, i
, bcm43xx_tab_noiseg2
[i
]);
742 for (i
= 0; i
< BCM43xx_TAB_NOISESCALEG_SIZE
; i
++)
743 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, bcm43xx_tab_noisescaleg1
[i
]);
744 else if ((phy
->rev
>= 7) && (bcm43xx_phy_read(dev
, 0x0449) & 0x0200))
745 for (i
= 0; i
< BCM43xx_TAB_NOISESCALEG_SIZE
; i
++)
746 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, bcm43xx_tab_noisescaleg3
[i
]);
748 for (i
= 0; i
< BCM43xx_TAB_NOISESCALEG_SIZE
; i
++)
749 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, bcm43xx_tab_noisescaleg2
[i
]);
752 for (i
= 0; i
< BCM43xx_TAB_SIGMASQR_SIZE
; i
++)
753 bcm43xx_ofdmtab_write16(dev
, 0x5000, i
, bcm43xx_tab_sigmasqr1
[i
]);
754 else if ((phy
->rev
> 2) && (phy
->rev
<= 8))
755 for (i
= 0; i
< BCM43xx_TAB_SIGMASQR_SIZE
; i
++)
756 bcm43xx_ofdmtab_write16(dev
, 0x5000, i
, bcm43xx_tab_sigmasqr2
[i
]);
759 for (i
= 0; i
< BCM43xx_TAB_RETARD_SIZE
; i
++)
760 bcm43xx_ofdmtab_write32(dev
, 0x2400, i
, bcm43xx_tab_retard
[i
]);
761 for (i
= 0; i
< 4; i
++) {
762 bcm43xx_ofdmtab_write16(dev
, 0x5404, i
, 0x0020);
763 bcm43xx_ofdmtab_write16(dev
, 0x5408, i
, 0x0020);
764 bcm43xx_ofdmtab_write16(dev
, 0x540C, i
, 0x0020);
765 bcm43xx_ofdmtab_write16(dev
, 0x5410, i
, 0x0020);
767 bcm43xx_phy_agcsetup(dev
);
769 if ((bus
->board_vendor
== SSB_BOARDVENDOR_BCM
) &&
770 (bus
->board_type
== SSB_BOARD_BU4306
) &&
771 (bus
->board_rev
== 0x17))
774 bcm43xx_ofdmtab_write16(dev
, 0x5001, 0, 0x0002);
775 bcm43xx_ofdmtab_write16(dev
, 0x5002, 0, 0x0001);
777 for (i
= 0; i
<= 0x2F; i
++)
778 bcm43xx_ofdmtab_write16(dev
, 0x1000, i
, 0x0820);
779 bcm43xx_phy_agcsetup(dev
);
780 bcm43xx_phy_read(dev
, 0x0400); /* dummy read */
781 bcm43xx_phy_write(dev
, 0x0403, 0x1000);
782 bcm43xx_ofdmtab_write16(dev
, 0x3C02, 0, 0x000F);
783 bcm43xx_ofdmtab_write16(dev
, 0x3C03, 0, 0x0014);
785 if ((bus
->board_vendor
== SSB_BOARDVENDOR_BCM
) &&
786 (bus
->board_type
== SSB_BOARD_BU4306
) &&
787 (bus
->board_rev
== 0x17))
790 bcm43xx_ofdmtab_write16(dev
, 0x0401, 0, 0x0002);
791 bcm43xx_ofdmtab_write16(dev
, 0x0402, 0, 0x0001);
795 /* Initialize the noisescaletable for APHY */
796 static void bcm43xx_phy_init_noisescaletbl(struct bcm43xx_wldev
*dev
)
798 struct bcm43xx_phy
*phy
= &dev
->phy
;
801 for (i
= 0; i
< 12; i
++) {
803 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x6767);
805 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x2323);
808 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x6700);
810 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x2300);
811 for (i
= 0; i
< 11; i
++) {
813 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x6767);
815 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x2323);
818 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x0067);
820 bcm43xx_ofdmtab_write16(dev
, 0x1400, i
, 0x0023);
823 static void bcm43xx_phy_setupa(struct bcm43xx_wldev
*dev
)
825 struct bcm43xx_phy
*phy
= &dev
->phy
;
828 assert(phy
->type
== BCM43xx_PHYTYPE_A
);
831 bcm43xx_phy_write(dev
, 0x008E, 0x3800);
832 bcm43xx_phy_write(dev
, 0x0035, 0x03FF);
833 bcm43xx_phy_write(dev
, 0x0036, 0x0400);
835 bcm43xx_ofdmtab_write16(dev
, 0x3807, 0, 0x0051);
837 bcm43xx_phy_write(dev
, 0x001C, 0x0FF9);
838 bcm43xx_phy_write(dev
, 0x0020, bcm43xx_phy_read(dev
, 0x0020) & 0xFF0F);
839 bcm43xx_ofdmtab_write16(dev
, 0x3C0C, 0, 0x07BF);
840 bcm43xx_radio_write16(dev
, 0x0002, 0x07BF);
842 bcm43xx_phy_write(dev
, 0x0024, 0x4680);
843 bcm43xx_phy_write(dev
, 0x0020, 0x0003);
844 bcm43xx_phy_write(dev
, 0x001D, 0x0F40);
845 bcm43xx_phy_write(dev
, 0x001F, 0x1C00);
847 bcm43xx_phy_write(dev
, 0x002A,
848 (bcm43xx_phy_read(dev
, 0x002A)
850 bcm43xx_phy_write(dev
, 0x002B,
851 bcm43xx_phy_read(dev
, 0x002B)
853 bcm43xx_phy_write(dev
, 0x008E, 0x58C1);
855 bcm43xx_ofdmtab_write16(dev
, 0x0803, 0, 0x000F);
856 bcm43xx_ofdmtab_write16(dev
, 0x0804, 0, 0x001F);
857 bcm43xx_ofdmtab_write16(dev
, 0x0805, 0, 0x002A);
858 bcm43xx_ofdmtab_write16(dev
, 0x0805, 0, 0x0030);
859 bcm43xx_ofdmtab_write16(dev
, 0x0807, 0, 0x003A);
861 bcm43xx_ofdmtab_write16(dev
, 0x0000, 0, 0x0013);
862 bcm43xx_ofdmtab_write16(dev
, 0x0000, 1, 0x0013);
863 bcm43xx_ofdmtab_write16(dev
, 0x0000, 2, 0x0013);
864 bcm43xx_ofdmtab_write16(dev
, 0x0000, 3, 0x0013);
865 bcm43xx_ofdmtab_write16(dev
, 0x0000, 4, 0x0015);
866 bcm43xx_ofdmtab_write16(dev
, 0x0000, 5, 0x0015);
867 bcm43xx_ofdmtab_write16(dev
, 0x0000, 6, 0x0019);
869 bcm43xx_ofdmtab_write16(dev
, 0x0404, 0, 0x0003);
870 bcm43xx_ofdmtab_write16(dev
, 0x0405, 0, 0x0003);
871 bcm43xx_ofdmtab_write16(dev
, 0x0406, 0, 0x0007);
873 for (i
= 0; i
< 16; i
++)
874 bcm43xx_ofdmtab_write16(dev
, 0x4000, i
, (0x8 + i
) & 0x000F);
876 bcm43xx_ofdmtab_write16(dev
, 0x3003, 0, 0x1044);
877 bcm43xx_ofdmtab_write16(dev
, 0x3004, 0, 0x7201);
878 bcm43xx_ofdmtab_write16(dev
, 0x3006, 0, 0x0040);
879 bcm43xx_ofdmtab_write16(dev
, 0x3001, 0, (bcm43xx_ofdmtab_read16(dev
, 0x3001, 0) & 0x0010) | 0x0008);
881 for (i
= 0; i
< BCM43xx_TAB_FINEFREQA_SIZE
; i
++)
882 bcm43xx_ofdmtab_write16(dev
, 0x5800, i
, bcm43xx_tab_finefreqa
[i
]);
883 for (i
= 0; i
< BCM43xx_TAB_NOISEA2_SIZE
; i
++)
884 bcm43xx_ofdmtab_write16(dev
, 0x1800, i
, bcm43xx_tab_noisea2
[i
]);
885 for (i
= 0; i
< BCM43xx_TAB_ROTOR_SIZE
; i
++)
886 bcm43xx_ofdmtab_write32(dev
, 0x2000, i
, bcm43xx_tab_rotor
[i
]);
887 bcm43xx_phy_init_noisescaletbl(dev
);
888 for (i
= 0; i
< BCM43xx_TAB_RETARD_SIZE
; i
++)
889 bcm43xx_ofdmtab_write32(dev
, 0x2400, i
, bcm43xx_tab_retard
[i
]);
892 for (i
= 0; i
< 64; i
++)
893 bcm43xx_ofdmtab_write16(dev
, 0x4000, i
, i
);
895 bcm43xx_ofdmtab_write16(dev
, 0x3807, 0, 0x0051);
897 bcm43xx_phy_write(dev
, 0x001C, 0x0FF9);
898 bcm43xx_phy_write(dev
, 0x0020,
899 bcm43xx_phy_read(dev
, 0x0020) & 0xFF0F);
900 bcm43xx_radio_write16(dev
, 0x0002, 0x07BF);
902 bcm43xx_phy_write(dev
, 0x0024, 0x4680);
903 bcm43xx_phy_write(dev
, 0x0020, 0x0003);
904 bcm43xx_phy_write(dev
, 0x001D, 0x0F40);
905 bcm43xx_phy_write(dev
, 0x001F, 0x1C00);
906 bcm43xx_phy_write(dev
, 0x002A,
907 (bcm43xx_phy_read(dev
, 0x002A)
910 bcm43xx_ofdmtab_write16(dev
, 0x3000, 1,
911 (bcm43xx_ofdmtab_read16(dev
, 0x3000, 1)
913 for (i
= 0; i
< BCM43xx_TAB_NOISEA3_SIZE
; i
++) {
914 bcm43xx_ofdmtab_write16(dev
, 0x1800, i
,
915 bcm43xx_tab_noisea3
[i
]);
917 bcm43xx_phy_init_noisescaletbl(dev
);
918 for (i
= 0; i
< BCM43xx_TAB_SIGMASQR_SIZE
; i
++) {
919 bcm43xx_ofdmtab_write16(dev
, 0x5000, i
,
920 bcm43xx_tab_sigmasqr1
[i
]);
923 bcm43xx_phy_write(dev
, 0x0003, 0x1808);
925 bcm43xx_ofdmtab_write16(dev
, 0x0803, 0, 0x000F);
926 bcm43xx_ofdmtab_write16(dev
, 0x0804, 0, 0x001F);
927 bcm43xx_ofdmtab_write16(dev
, 0x0805, 0, 0x002A);
928 bcm43xx_ofdmtab_write16(dev
, 0x0805, 0, 0x0030);
929 bcm43xx_ofdmtab_write16(dev
, 0x0807, 0, 0x003A);
931 bcm43xx_ofdmtab_write16(dev
, 0x0000, 0, 0x0013);
932 bcm43xx_ofdmtab_write16(dev
, 0x0001, 0, 0x0013);
933 bcm43xx_ofdmtab_write16(dev
, 0x0002, 0, 0x0013);
934 bcm43xx_ofdmtab_write16(dev
, 0x0003, 0, 0x0013);
935 bcm43xx_ofdmtab_write16(dev
, 0x0004, 0, 0x0015);
936 bcm43xx_ofdmtab_write16(dev
, 0x0005, 0, 0x0015);
937 bcm43xx_ofdmtab_write16(dev
, 0x0006, 0, 0x0019);
939 bcm43xx_ofdmtab_write16(dev
, 0x0404, 0, 0x0003);
940 bcm43xx_ofdmtab_write16(dev
, 0x0405, 0, 0x0003);
941 bcm43xx_ofdmtab_write16(dev
, 0x0406, 0, 0x0007);
943 bcm43xx_ofdmtab_write16(dev
, 0x3C02, 0, 0x000F);
944 bcm43xx_ofdmtab_write16(dev
, 0x3C03, 0, 0x0014);
951 /* Initialize APHY. This is also called for the GPHY in some cases. */
952 static void bcm43xx_phy_inita(struct bcm43xx_wldev
*dev
)
954 struct ssb_bus
*bus
= dev
->dev
->bus
;
955 struct bcm43xx_phy
*phy
= &dev
->phy
;
958 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
959 bcm43xx_phy_setupa(dev
);
961 bcm43xx_phy_setupg(dev
);
963 (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
))
964 bcm43xx_phy_write(dev
, 0x046E, 0x03CF);
968 bcm43xx_phy_write(dev
, BCM43xx_PHY_A_CRS
,
969 (bcm43xx_phy_read(dev
, BCM43xx_PHY_A_CRS
) & 0xF83C) | 0x0340);
970 bcm43xx_phy_write(dev
, 0x0034, 0x0001);
972 TODO();//TODO: RSSI AGC
973 bcm43xx_phy_write(dev
, BCM43xx_PHY_A_CRS
,
974 bcm43xx_phy_read(dev
, BCM43xx_PHY_A_CRS
) | (1 << 14));
975 bcm43xx_radio_init2060(dev
);
977 if ((bus
->board_vendor
== SSB_BOARDVENDOR_BCM
) &&
978 ((bus
->board_type
== SSB_BOARD_BU4306
) ||
979 (bus
->board_type
== SSB_BOARD_BU4309
))) {
980 if (phy
->lofcal
== 0xFFFF) {
981 TODO();//TODO: LOF Cal
982 bcm43xx_radio_set_tx_iq(dev
);
984 bcm43xx_radio_write16(dev
, 0x001E, phy
->lofcal
);
987 bcm43xx_phy_write(dev
, 0x007A, 0xF111);
989 if (phy
->cur_idle_tssi
== 0) {
990 bcm43xx_radio_write16(dev
, 0x0019, 0x0000);
991 bcm43xx_radio_write16(dev
, 0x0017, 0x0020);
993 tval
= bcm43xx_ofdmtab_read16(dev
, 0x3001, 0);
995 bcm43xx_ofdmtab_write16(dev
, 0x3001, 0,
996 (bcm43xx_ofdmtab_read16(dev
, 0x3001, 0) & 0xFF87)
999 bcm43xx_ofdmtab_write16(dev
, 0x3001, 0,
1000 (bcm43xx_ofdmtab_read16(dev
, 0x3001, 0) & 0xFFC3)
1003 bcm43xx_dummy_transmission(dev
);
1004 phy
->cur_idle_tssi
= bcm43xx_phy_read(dev
, BCM43xx_PHY_A_PCTL
);
1005 bcm43xx_ofdmtab_write16(dev
, 0x3001, 0, tval
);
1007 bcm43xx_radio_set_txpower_a(dev
, 0x0018);
1009 bcm43xx_shm_clear_tssi(dev
);
1012 static void bcm43xx_phy_initb2(struct bcm43xx_wldev
*dev
)
1014 struct bcm43xx_phy
*phy
= &dev
->phy
;
1017 bcm43xx_write16(dev
, 0x03EC, 0x3F22);
1018 bcm43xx_phy_write(dev
, 0x0020, 0x301C);
1019 bcm43xx_phy_write(dev
, 0x0026, 0x0000);
1020 bcm43xx_phy_write(dev
, 0x0030, 0x00C6);
1021 bcm43xx_phy_write(dev
, 0x0088, 0x3E00);
1023 for (offset
= 0x0089; offset
< 0x00A7; offset
++) {
1024 bcm43xx_phy_write(dev
, offset
, val
);
1027 bcm43xx_phy_write(dev
, 0x03E4, 0x3000);
1028 if (phy
->channel
== 0xFF)
1029 bcm43xx_radio_selectchannel(dev
, BCM43xx_DEFAULT_CHANNEL_BG
, 0);
1031 bcm43xx_radio_selectchannel(dev
, phy
->channel
, 0);
1032 if (phy
->radio_ver
!= 0x2050) {
1033 bcm43xx_radio_write16(dev
, 0x0075, 0x0080);
1034 bcm43xx_radio_write16(dev
, 0x0079, 0x0081);
1036 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1037 bcm43xx_radio_write16(dev
, 0x0050, 0x0023);
1038 if (phy
->radio_ver
== 0x2050) {
1039 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1040 bcm43xx_radio_write16(dev
, 0x005A, 0x0070);
1041 bcm43xx_radio_write16(dev
, 0x005B, 0x007B);
1042 bcm43xx_radio_write16(dev
, 0x005C, 0x00B0);
1043 bcm43xx_radio_write16(dev
, 0x007A, 0x000F);
1044 bcm43xx_phy_write(dev
, 0x0038, 0x0677);
1045 bcm43xx_radio_init2050(dev
);
1047 bcm43xx_phy_write(dev
, 0x0014, 0x0080);
1048 bcm43xx_phy_write(dev
, 0x0032, 0x00CA);
1049 bcm43xx_phy_write(dev
, 0x0032, 0x00CC);
1050 bcm43xx_phy_write(dev
, 0x0035, 0x07C2);
1051 bcm43xx_lo_b_measure(dev
);
1052 bcm43xx_phy_write(dev
, 0x0026, 0xCC00);
1053 if (phy
->radio_ver
!= 0x2050)
1054 bcm43xx_phy_write(dev
, 0x0026, 0xCE00);
1055 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
, 0x1000);
1056 bcm43xx_phy_write(dev
, 0x002A, 0x88A3);
1057 if (phy
->radio_ver
!= 0x2050)
1058 bcm43xx_phy_write(dev
, 0x002A, 0x88C2);
1059 bcm43xx_radio_set_txpower_bg(dev
, -1, -1, -1);
1060 bcm43xx_phy_init_pctl(dev
);
1063 static void bcm43xx_phy_initb4(struct bcm43xx_wldev
*dev
)
1065 struct bcm43xx_phy
*phy
= &dev
->phy
;
1068 bcm43xx_write16(dev
, 0x03EC, 0x3F22);
1069 bcm43xx_phy_write(dev
, 0x0020, 0x301C);
1070 bcm43xx_phy_write(dev
, 0x0026, 0x0000);
1071 bcm43xx_phy_write(dev
, 0x0030, 0x00C6);
1072 bcm43xx_phy_write(dev
, 0x0088, 0x3E00);
1074 for (offset
= 0x0089; offset
< 0x00A7; offset
++) {
1075 bcm43xx_phy_write(dev
, offset
, val
);
1078 bcm43xx_phy_write(dev
, 0x03E4, 0x3000);
1079 if (phy
->channel
== 0xFF)
1080 bcm43xx_radio_selectchannel(dev
, BCM43xx_DEFAULT_CHANNEL_BG
, 0);
1082 bcm43xx_radio_selectchannel(dev
, phy
->channel
, 0);
1083 if (phy
->radio_ver
!= 0x2050) {
1084 bcm43xx_radio_write16(dev
, 0x0075, 0x0080);
1085 bcm43xx_radio_write16(dev
, 0x0079, 0x0081);
1087 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1088 bcm43xx_radio_write16(dev
, 0x0050, 0x0023);
1089 if (phy
->radio_ver
== 0x2050) {
1090 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1091 bcm43xx_radio_write16(dev
, 0x005A, 0x0070);
1092 bcm43xx_radio_write16(dev
, 0x005B, 0x007B);
1093 bcm43xx_radio_write16(dev
, 0x005C, 0x00B0);
1094 bcm43xx_radio_write16(dev
, 0x007A, 0x000F);
1095 bcm43xx_phy_write(dev
, 0x0038, 0x0677);
1096 bcm43xx_radio_init2050(dev
);
1098 bcm43xx_phy_write(dev
, 0x0014, 0x0080);
1099 bcm43xx_phy_write(dev
, 0x0032, 0x00CA);
1100 if (phy
->radio_ver
== 0x2050)
1101 bcm43xx_phy_write(dev
, 0x0032, 0x00E0);
1102 bcm43xx_phy_write(dev
, 0x0035, 0x07C2);
1104 bcm43xx_lo_b_measure(dev
);
1106 bcm43xx_phy_write(dev
, 0x0026, 0xCC00);
1107 if (phy
->radio_ver
== 0x2050)
1108 bcm43xx_phy_write(dev
, 0x0026, 0xCE00);
1109 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
, 0x1100);
1110 bcm43xx_phy_write(dev
, 0x002A, 0x88A3);
1111 if (phy
->radio_ver
== 0x2050)
1112 bcm43xx_phy_write(dev
, 0x002A, 0x88C2);
1113 bcm43xx_radio_set_txpower_bg(dev
, 0xFFFF, 0xFFFF, 0xFFFF);
1114 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
) {
1115 bcm43xx_calc_nrssi_slope(dev
);
1116 bcm43xx_calc_nrssi_threshold(dev
);
1118 bcm43xx_phy_init_pctl(dev
);
1121 static void bcm43xx_phy_initb5(struct bcm43xx_wldev
*dev
)
1123 struct ssb_bus
*bus
= dev
->dev
->bus
;
1124 struct bcm43xx_phy
*phy
= &dev
->phy
;
1128 if (phy
->analog
== 1) {
1129 bcm43xx_radio_write16(dev
, 0x007A,
1130 bcm43xx_radio_read16(dev
, 0x007A)
1133 if ((bus
->board_vendor
!= SSB_BOARDVENDOR_BCM
) &&
1134 (bus
->board_type
!= SSB_BOARD_BU4306
)) {
1136 for (offset
= 0x00A8 ; offset
< 0x00C7; offset
++) {
1137 bcm43xx_phy_write(dev
, offset
, value
);
1141 bcm43xx_phy_write(dev
, 0x0035,
1142 (bcm43xx_phy_read(dev
, 0x0035) & 0xF0FF)
1144 if (phy
->radio_ver
== 0x2050)
1145 bcm43xx_phy_write(dev
, 0x0038, 0x0667);
1147 if (phy
->gmode
|| phy
->rev
>= 2) {
1148 if (phy
->radio_ver
== 0x2050) {
1149 bcm43xx_radio_write16(dev
, 0x007A,
1150 bcm43xx_radio_read16(dev
, 0x007A)
1152 bcm43xx_radio_write16(dev
, 0x0051,
1153 bcm43xx_radio_read16(dev
, 0x0051)
1156 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY_RADIO
, 0x0000);
1158 bcm43xx_phy_write(dev
, 0x0802, bcm43xx_phy_read(dev
, 0x0802) | 0x0100);
1159 bcm43xx_phy_write(dev
, 0x042B, bcm43xx_phy_read(dev
, 0x042B) | 0x2000);
1161 bcm43xx_phy_write(dev
, 0x001C, 0x186A);
1163 bcm43xx_phy_write(dev
, 0x0013, (bcm43xx_phy_read(dev
, 0x0013) & 0x00FF) | 0x1900);
1164 bcm43xx_phy_write(dev
, 0x0035, (bcm43xx_phy_read(dev
, 0x0035) & 0xFFC0) | 0x0064);
1165 bcm43xx_phy_write(dev
, 0x005D, (bcm43xx_phy_read(dev
, 0x005D) & 0xFF80) | 0x000A);
1168 if (dev
->bad_frames_preempt
) {
1169 bcm43xx_phy_write(dev
, BCM43xx_PHY_RADIO_BITFIELD
,
1170 bcm43xx_phy_read(dev
, BCM43xx_PHY_RADIO_BITFIELD
) | (1 << 11));
1173 if (phy
->analog
== 1) {
1174 bcm43xx_phy_write(dev
, 0x0026, 0xCE00);
1175 bcm43xx_phy_write(dev
, 0x0021, 0x3763);
1176 bcm43xx_phy_write(dev
, 0x0022, 0x1BC3);
1177 bcm43xx_phy_write(dev
, 0x0023, 0x06F9);
1178 bcm43xx_phy_write(dev
, 0x0024, 0x037E);
1180 bcm43xx_phy_write(dev
, 0x0026, 0xCC00);
1181 bcm43xx_phy_write(dev
, 0x0030, 0x00C6);
1182 bcm43xx_write16(dev
, 0x03EC, 0x3F22);
1184 if (phy
->analog
== 1)
1185 bcm43xx_phy_write(dev
, 0x0020, 0x3E1C);
1187 bcm43xx_phy_write(dev
, 0x0020, 0x301C);
1189 if (phy
->analog
== 0)
1190 bcm43xx_write16(dev
, 0x03E4, 0x3000);
1192 old_channel
= phy
->channel
;
1193 /* Force to channel 7, even if not supported. */
1194 bcm43xx_radio_selectchannel(dev
, 7, 0);
1196 if (phy
->radio_ver
!= 0x2050) {
1197 bcm43xx_radio_write16(dev
, 0x0075, 0x0080);
1198 bcm43xx_radio_write16(dev
, 0x0079, 0x0081);
1201 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1202 bcm43xx_radio_write16(dev
, 0x0050, 0x0023);
1204 if (phy
->radio_ver
== 0x2050) {
1205 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1206 bcm43xx_radio_write16(dev
, 0x005A, 0x0070);
1209 bcm43xx_radio_write16(dev
, 0x005B, 0x007B);
1210 bcm43xx_radio_write16(dev
, 0x005C, 0x00B0);
1212 bcm43xx_radio_write16(dev
, 0x007A, bcm43xx_radio_read16(dev
, 0x007A) | 0x0007);
1214 bcm43xx_radio_selectchannel(dev
, old_channel
, 0);
1216 bcm43xx_phy_write(dev
, 0x0014, 0x0080);
1217 bcm43xx_phy_write(dev
, 0x0032, 0x00CA);
1218 bcm43xx_phy_write(dev
, 0x002A, 0x88A3);
1220 bcm43xx_radio_set_txpower_bg(dev
, -1, -1, -1);
1222 if (phy
->radio_ver
== 0x2050)
1223 bcm43xx_radio_write16(dev
, 0x005D, 0x000D);
1225 bcm43xx_write16(dev
, 0x03E4, (bcm43xx_read16(dev
, 0x03E4) & 0xFFC0) | 0x0004);
1228 static void bcm43xx_phy_initb6(struct bcm43xx_wldev
*dev
)
1230 struct bcm43xx_phy
*phy
= &dev
->phy
;
1234 bcm43xx_phy_write(dev
, 0x003E, 0x817A);
1235 bcm43xx_radio_write16(dev
, 0x007A,
1236 (bcm43xx_radio_read16(dev
, 0x007A) | 0x0058));
1237 if (phy
->radio_rev
== 4 || phy
->radio_rev
== 5) {
1238 bcm43xx_radio_write16(dev
, 0x51, 0x37);
1239 bcm43xx_radio_write16(dev
, 0x52, 0x70);
1240 bcm43xx_radio_write16(dev
, 0x53, 0xB3);
1241 bcm43xx_radio_write16(dev
, 0x54, 0x9B);
1242 bcm43xx_radio_write16(dev
, 0x5A, 0x88);
1243 bcm43xx_radio_write16(dev
, 0x5B, 0x88);
1244 bcm43xx_radio_write16(dev
, 0x5D, 0x88);
1245 bcm43xx_radio_write16(dev
, 0x5E, 0x88);
1246 bcm43xx_radio_write16(dev
, 0x7D, 0x88);
1247 bcm43xx_hf_write(dev
, bcm43xx_hf_read(dev
)
1248 | BCM43xx_HF_TSSIRPSMW
);
1250 assert(phy
->radio_rev
!= 6 && phy
->radio_rev
!= 7); /* We had code for these revs here...*/
1251 if (phy
->radio_rev
== 8) {
1252 bcm43xx_radio_write16(dev
, 0x51, 0);
1253 bcm43xx_radio_write16(dev
, 0x52, 0x40);
1254 bcm43xx_radio_write16(dev
, 0x53, 0xB7);
1255 bcm43xx_radio_write16(dev
, 0x54, 0x98);
1256 bcm43xx_radio_write16(dev
, 0x5A, 0x88);
1257 bcm43xx_radio_write16(dev
, 0x5B, 0x6B);
1258 bcm43xx_radio_write16(dev
, 0x5C, 0x0F);
1259 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_ALTIQ
) {
1260 bcm43xx_radio_write16(dev
, 0x5D, 0xFA);
1261 bcm43xx_radio_write16(dev
, 0x5E, 0xD8);
1263 bcm43xx_radio_write16(dev
, 0x5D, 0xF5);
1264 bcm43xx_radio_write16(dev
, 0x5E, 0xB8);
1266 bcm43xx_radio_write16(dev
, 0x0073, 0x0003);
1267 bcm43xx_radio_write16(dev
, 0x007D, 0x00A8);
1268 bcm43xx_radio_write16(dev
, 0x007C, 0x0001);
1269 bcm43xx_radio_write16(dev
, 0x007E, 0x0008);
1272 for (offset
= 0x0088; offset
< 0x0098; offset
++) {
1273 bcm43xx_phy_write(dev
, offset
, val
);
1277 for (offset
= 0x0098; offset
< 0x00A8; offset
++) {
1278 bcm43xx_phy_write(dev
, offset
, val
);
1282 for (offset
= 0x00A8; offset
< 0x00C8; offset
++) {
1283 bcm43xx_phy_write(dev
, offset
, (val
& 0x3F3F));
1286 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
1287 bcm43xx_radio_write16(dev
, 0x007A,
1288 bcm43xx_radio_read16(dev
, 0x007A) | 0x0020);
1289 bcm43xx_radio_write16(dev
, 0x0051,
1290 bcm43xx_radio_read16(dev
, 0x0051) | 0x0004);
1291 bcm43xx_phy_write(dev
, 0x0802,
1292 bcm43xx_phy_read(dev
, 0x0802) | 0x0100);
1293 bcm43xx_phy_write(dev
, 0x042B,
1294 bcm43xx_phy_read(dev
, 0x042B) | 0x2000);
1295 bcm43xx_phy_write(dev
, 0x5B, 0);
1296 bcm43xx_phy_write(dev
, 0x5C, 0);
1299 old_channel
= phy
->channel
;
1300 if (old_channel
>= 8)
1301 bcm43xx_radio_selectchannel(dev
, 1, 0);
1303 bcm43xx_radio_selectchannel(dev
, 13, 0);
1305 bcm43xx_radio_write16(dev
, 0x0050, 0x0020);
1306 bcm43xx_radio_write16(dev
, 0x0050, 0x0023);
1308 if (phy
->radio_rev
< 6 || phy
->radio_rev
== 8) {
1309 bcm43xx_radio_write16(dev
, 0x7C,
1310 (bcm43xx_radio_read16(dev
, 0x7C)
1312 bcm43xx_radio_write16(dev
, 0x50, 0x20);
1314 if (phy
->radio_rev
<= 2) {
1315 bcm43xx_radio_write16(dev
, 0x7C, 0x20);
1316 bcm43xx_radio_write16(dev
, 0x5A, 0x70);
1317 bcm43xx_radio_write16(dev
, 0x5B, 0x7B);
1318 bcm43xx_radio_write16(dev
, 0x5C, 0xB0);
1320 bcm43xx_radio_write16(dev
, 0x007A,
1321 (bcm43xx_radio_read16(dev
, 0x007A) & 0x00F8) | 0x0007);
1323 bcm43xx_radio_selectchannel(dev
, old_channel
, 0);
1325 bcm43xx_phy_write(dev
, 0x0014, 0x0200);
1326 if (phy
->radio_rev
>= 6)
1327 bcm43xx_phy_write(dev
, 0x2A, 0x88C2);
1329 bcm43xx_phy_write(dev
, 0x2A, 0x8AC0);
1330 bcm43xx_phy_write(dev
, 0x0038, 0x0668);
1331 bcm43xx_radio_set_txpower_bg(dev
, -1, -1, -1);
1332 if (phy
->radio_rev
<= 5) {
1333 bcm43xx_phy_write(dev
, 0x5D,
1334 (bcm43xx_phy_read(dev
, 0x5D)
1335 & 0xFF80) | 0x0003);
1337 if (phy
->radio_rev
<= 2)
1338 bcm43xx_radio_write16(dev
, 0x005D, 0x000D);
1340 if (phy
->analog
== 4) {
1341 bcm43xx_write16(dev
, 0x3E4, 9);
1342 bcm43xx_phy_write(dev
, 0x61,
1343 bcm43xx_phy_read(dev
, 0x61)
1346 bcm43xx_phy_write(dev
, 0x0002,
1347 (bcm43xx_phy_read(dev
, 0x0002) & 0xFFC0)
1350 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
1351 bcm43xx_write16(dev
, 0x03E6, 0x8140);
1352 bcm43xx_phy_write(dev
, 0x0016, 0x0410);
1353 bcm43xx_phy_write(dev
, 0x0017, 0x0820);
1354 bcm43xx_phy_write(dev
, 0x0062, 0x0007);
1355 bcm43xx_radio_init2050(dev
);
1356 bcm43xx_lo_g_measure(dev
);
1357 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
) {
1358 bcm43xx_calc_nrssi_slope(dev
);
1359 bcm43xx_calc_nrssi_threshold(dev
);
1361 bcm43xx_phy_init_pctl(dev
);
1362 } else if (phy
->type
== BCM43xx_PHYTYPE_G
)
1363 bcm43xx_write16(dev
, 0x03E6, 0x0);
1366 static void bcm43xx_calc_loopback_gain(struct bcm43xx_wldev
*dev
)
1368 struct bcm43xx_phy
*phy
= &dev
->phy
;
1369 u16 backup_phy
[16] = {0};
1370 u16 backup_radio
[3];
1372 u16 i
, j
, loop_i_max
;
1374 u16 loop1_outer_done
, loop1_inner_done
;
1376 backup_phy
[0] = bcm43xx_phy_read(dev
, BCM43xx_PHY_CRS0
);
1377 backup_phy
[1] = bcm43xx_phy_read(dev
, BCM43xx_PHY_CCKBBANDCFG
);
1378 backup_phy
[2] = bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
);
1379 backup_phy
[3] = bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
);
1380 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1381 backup_phy
[4] = bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
);
1382 backup_phy
[5] = bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
);
1384 backup_phy
[6] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x5A));
1385 backup_phy
[7] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x59));
1386 backup_phy
[8] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x58));
1387 backup_phy
[9] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x0A));
1388 backup_phy
[10] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x03));
1389 backup_phy
[11] = bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_MASK
);
1390 backup_phy
[12] = bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_CTL
);
1391 backup_phy
[13] = bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x2B));
1392 backup_phy
[14] = bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
);
1393 backup_phy
[15] = bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_LEAKAGE
);
1394 backup_bband
= phy
->bbatt
;
1395 backup_radio
[0] = bcm43xx_radio_read16(dev
, 0x52);
1396 backup_radio
[1] = bcm43xx_radio_read16(dev
, 0x43);
1397 backup_radio
[2] = bcm43xx_radio_read16(dev
, 0x7A);
1399 bcm43xx_phy_write(dev
, BCM43xx_PHY_CRS0
,
1400 bcm43xx_phy_read(dev
, BCM43xx_PHY_CRS0
) & 0x3FFF);
1401 bcm43xx_phy_write(dev
, BCM43xx_PHY_CCKBBANDCFG
,
1402 bcm43xx_phy_read(dev
, BCM43xx_PHY_CCKBBANDCFG
) | 0x8000);
1403 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1404 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
) | 0x0002);
1405 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1406 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
) & 0xFFFD);
1407 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1408 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
) | 0x0001);
1409 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1410 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
) & 0xFFFE);
1411 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1412 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
,
1413 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
) | 0x0001);
1414 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
,
1415 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
) & 0xFFFE);
1416 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
,
1417 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
) | 0x0002);
1418 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
,
1419 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
) & 0xFFFD);
1421 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1422 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
) | 0x000C);
1423 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1424 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
) | 0x000C);
1425 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1426 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
) | 0x0030);
1427 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1428 (bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
)
1431 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x5A), 0x0780);
1432 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x59), 0xC810);
1433 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0x000D);
1435 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x0A),
1436 bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x0A)) | 0x2000);
1437 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1438 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
,
1439 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
) | 0x0004);
1440 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
,
1441 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
) & 0xFFFB);
1443 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x03),
1444 (bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x03))
1447 if (phy
->radio_rev
== 8) {
1448 bcm43xx_radio_write16(dev
, 0x43, 0x000F);
1450 bcm43xx_radio_write16(dev
, 0x52, 0);
1451 bcm43xx_radio_write16(dev
, 0x43,
1452 (bcm43xx_radio_read16(dev
, 0x43)
1455 bcm43xx_phy_set_baseband_attenuation(dev
, 11);
1458 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, 0xC020);
1460 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, 0x8020);
1461 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_CTL
, 0);
1463 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2B),
1464 (bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x2B))
1466 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2B),
1467 (bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x2B))
1470 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1471 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
) | 0x0100);
1472 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1473 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
) & 0xCFFF);
1475 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_EXTLNA
) {
1476 if (phy
->rev
>= 7) {
1477 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
1478 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
)
1480 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1481 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
)
1485 bcm43xx_radio_write16(dev
, 0x7A,
1486 bcm43xx_radio_read16(dev
, 0x7A)
1490 loop_i_max
= (phy
->radio_rev
== 8) ? 15 : 9;
1491 for (i
= 0; i
< loop_i_max
; i
++) {
1492 for (j
= 0; j
< 16; j
++) {
1493 bcm43xx_radio_write16(dev
, 0x43, i
);
1494 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1495 (bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
)
1496 & 0xF0FF) | (j
<< 8));
1497 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
,
1498 (bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
)
1499 & 0x0FFF) | 0xA000);
1500 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
,
1501 bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
)
1504 if (bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_LEAKAGE
) >= 0xDFC)
1509 loop1_outer_done
= i
;
1510 loop1_inner_done
= j
;
1512 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1513 bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
)
1516 for (j
= j
- 8; j
< 16; j
++) {
1517 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
1518 (bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
)
1519 & 0xF0FF) | (j
<< 8));
1520 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
,
1521 (bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
)
1522 & 0x0FFF) | 0xA000);
1523 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
,
1524 bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
)
1528 if (bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_LEAKAGE
) >= 0xDFC)
1535 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
1536 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
, backup_phy
[4]);
1537 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
, backup_phy
[5]);
1539 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x5A), backup_phy
[6]);
1540 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x59), backup_phy
[7]);
1541 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), backup_phy
[8]);
1542 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x0A), backup_phy
[9]);
1543 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x03), backup_phy
[10]);
1544 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, backup_phy
[11]);
1545 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_CTL
, backup_phy
[12]);
1546 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2B), backup_phy
[13]);
1547 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, backup_phy
[14]);
1549 bcm43xx_phy_set_baseband_attenuation(dev
, backup_bband
);
1551 bcm43xx_radio_write16(dev
, 0x52, backup_radio
[0]);
1552 bcm43xx_radio_write16(dev
, 0x43, backup_radio
[1]);
1553 bcm43xx_radio_write16(dev
, 0x7A, backup_radio
[2]);
1555 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
, backup_phy
[2] | 0x0003);
1557 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
, backup_phy
[2]);
1558 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
, backup_phy
[3]);
1559 bcm43xx_phy_write(dev
, BCM43xx_PHY_CRS0
, backup_phy
[0]);
1560 bcm43xx_phy_write(dev
, BCM43xx_PHY_CCKBBANDCFG
, backup_phy
[1]);
1562 phy
->max_lb_gain
= ((loop1_inner_done
* 6) - (loop1_outer_done
* 4)) - 11;
1563 phy
->trsw_rx_gain
= trsw_rx
* 2;
1566 static void bcm43xx_phy_initg(struct bcm43xx_wldev
*dev
)
1568 struct bcm43xx_phy
*phy
= &dev
->phy
;
1572 bcm43xx_phy_initb5(dev
);
1574 bcm43xx_phy_initb6(dev
);
1576 if (phy
->rev
>= 2 || phy
->gmode
)
1577 bcm43xx_phy_inita(dev
);
1579 if (phy
->rev
>= 2) {
1580 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
, 0);
1581 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
, 0);
1583 if (phy
->rev
== 2) {
1584 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
, 0);
1585 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xC0);
1588 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
, 0x400);
1589 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xC0);
1591 if (phy
->gmode
|| phy
->rev
>= 2) {
1592 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_VERSION_OFDM
);
1593 tmp
&= BCM43xx_PHYVER_VERSION
;
1594 if (tmp
== 3 || tmp
== 5) {
1595 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0xC2), 0x1816);
1596 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0xC3), 0x8006);
1599 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0xCC),
1600 (bcm43xx_phy_read(dev
, BCM43xx_PHY_OFDM(0xCC))
1601 & 0x00FF) | 0x1F00);
1604 if ((phy
->rev
<= 2 && phy
->gmode
) || phy
->rev
>= 2)
1605 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0x7E), 0x78);
1606 if (phy
->radio_rev
== 8) {
1607 bcm43xx_phy_write(dev
, BCM43xx_PHY_EXTG(0x01),
1608 bcm43xx_phy_read(dev
, BCM43xx_PHY_EXTG(0x01))
1610 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0x3E),
1611 bcm43xx_phy_read(dev
, BCM43xx_PHY_OFDM(0x3E))
1614 if (has_loopback_gain(phy
))
1615 bcm43xx_calc_loopback_gain(dev
);
1617 if (phy
->radio_rev
!= 8) {
1618 if (phy
->initval
== 0xFFFF)
1619 phy
->initval
= bcm43xx_radio_init2050(dev
);
1621 bcm43xx_radio_write16(dev
, 0x0078, phy
->initval
);
1623 if (phy
->lo_control
->tx_bias
== 0xFF) {
1624 bcm43xx_lo_g_measure(dev
);
1626 if (has_tx_magnification(phy
)) {
1627 bcm43xx_radio_write16(dev
, 0x52,
1628 (bcm43xx_radio_read16(dev
, 0x52) & 0xFF00) |
1629 phy
->lo_control
->tx_bias
|
1630 phy
->lo_control
->tx_magn
);
1632 bcm43xx_radio_write16(dev
, 0x52,
1633 (bcm43xx_radio_read16(dev
, 0x52) & 0xFFF0) |
1634 phy
->lo_control
->tx_bias
);
1636 if (phy
->rev
>= 6) {
1637 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x36),
1638 (bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x36))
1639 & 0x0FFF) | (phy
->lo_control
->tx_bias
<< 12));
1641 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
)
1642 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2E), 0x8075);
1644 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2E), 0x807F);
1646 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2F), 0x101);
1648 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2F), 0x202);
1650 if (phy
->gmode
|| phy
->rev
>= 2) {
1651 bcm43xx_lo_g_adjust(dev
);
1652 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, 0x8078);
1655 if (!(dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
)) {
1656 /* The specs state to update the NRSSI LT with
1657 * the value 0x7FFFFFFF here. I think that is some weird
1658 * compiler optimization in the original driver.
1659 * Essentially, what we do here is resetting all NRSSI LT
1660 * entries to -32 (see the limit_value() in nrssi_hw_update())
1662 bcm43xx_nrssi_hw_update(dev
, 0xFFFF);//FIXME?
1663 bcm43xx_calc_nrssi_threshold(dev
);
1664 } else if (phy
->gmode
|| phy
->rev
>= 2) {
1665 if (phy
->nrssi
[0] == -1000) {
1666 assert(phy
->nrssi
[1] == -1000);
1667 bcm43xx_calc_nrssi_slope(dev
);
1669 bcm43xx_calc_nrssi_threshold(dev
);
1671 if (phy
->radio_rev
== 8)
1672 bcm43xx_phy_write(dev
, BCM43xx_PHY_EXTG(0x05), 0x3230);
1673 bcm43xx_phy_init_pctl(dev
);
1674 /* FIXME: The spec says in the following if, the 0 should be replaced
1675 'if OFDM may not be used in the current locale'
1676 but OFDM is legal everywhere */
1677 if ((dev
->dev
->bus
->chip_id
== 0x4306 && dev
->dev
->bus
->chip_package
== 2) || 0) {
1678 bcm43xx_phy_write(dev
, BCM43xx_PHY_CRS0
,
1679 bcm43xx_phy_read(dev
, BCM43xx_PHY_CRS0
)
1681 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM(0xC3),
1682 bcm43xx_phy_read(dev
, BCM43xx_PHY_OFDM(0xC3))
1687 /* Set the baseband attenuation value on chip. */
1688 void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_wldev
*dev
,
1689 u16 baseband_attenuation
)
1691 struct bcm43xx_phy
*phy
= &dev
->phy
;
1694 if (phy
->analog
== 0) {
1695 value
= (bcm43xx_read16(dev
, 0x03E6) & 0xFFF0);
1696 value
|= (baseband_attenuation
& 0x000F);
1697 bcm43xx_write16(dev
, 0x03E6, value
);
1701 if (phy
->analog
> 1) {
1702 value
= bcm43xx_phy_read(dev
, 0x0060) & ~0x003C;
1703 value
|= (baseband_attenuation
<< 2) & 0x003C;
1705 value
= bcm43xx_phy_read(dev
, 0x0060) & ~0x0078;
1706 value
|= (baseband_attenuation
<< 3) & 0x0078;
1708 bcm43xx_phy_write(dev
, 0x0060, value
);
1711 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1712 * This function converts a TSSI value to dBm in Q5.2
1714 static s8
bcm43xx_phy_estimate_power_out(struct bcm43xx_wldev
*dev
, s8 tssi
)
1716 struct bcm43xx_phy
*phy
= &dev
->phy
;
1720 tmp
= (phy
->tgt_idle_tssi
- phy
->cur_idle_tssi
+ tssi
);
1722 switch (phy
->type
) {
1723 case BCM43xx_PHYTYPE_A
:
1725 tmp
= limit_value(tmp
, 0x00, 0xFF);
1726 dbm
= phy
->tssi2dbm
[tmp
];
1727 TODO(); //TODO: There's a FIXME on the specs
1729 case BCM43xx_PHYTYPE_B
:
1730 case BCM43xx_PHYTYPE_G
:
1731 tmp
= limit_value(tmp
, 0x00, 0x3F);
1732 dbm
= phy
->tssi2dbm
[tmp
];
1741 static void put_attenuation_into_ranges(struct bcm43xx_wldev
*dev
,
1742 int *_rfatt
, int *_bbatt
)
1744 int rfatt
= *_rfatt
;
1745 int bbatt
= *_bbatt
;
1747 /* Get baseband and radio attenuation values into their permitted ranges.
1748 * Radio attenuation affects power level 4 times as much as baseband. */
1750 /* Range constants */
1751 const int rf_min
= 0;
1752 const int rf_max
= 9;
1753 const int bb_min
= 0;
1754 const int bb_max
= 11;
1757 if (rfatt
> rf_max
&&
1759 break; /* Can not get it into ranges */
1760 if (rfatt
< rf_min
&&
1762 break; /* Can not get it into ranges */
1763 if (bbatt
> bb_max
&&
1765 break; /* Can not get it into ranges */
1766 if (bbatt
< bb_min
&&
1768 break; /* Can not get it into ranges */
1770 if (bbatt
> bb_max
) {
1775 if (bbatt
< bb_min
) {
1780 if (rfatt
> rf_max
) {
1785 if (rfatt
< rf_min
) {
1793 *_rfatt
= limit_value(rfatt
, rf_min
, rf_max
);
1794 *_bbatt
= limit_value(bbatt
, bb_min
, bb_max
);
1797 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1798 void bcm43xx_phy_xmitpower(struct bcm43xx_wldev
*dev
)
1800 struct ssb_bus
*bus
= dev
->dev
->bus
;
1801 struct bcm43xx_phy
*phy
= &dev
->phy
;
1803 if (phy
->cur_idle_tssi
== 0)
1805 if ((bus
->board_vendor
== SSB_BOARDVENDOR_BCM
) &&
1806 (bus
->board_type
== SSB_BOARD_BU4306
))
1809 switch (phy
->type
) {
1810 case BCM43xx_PHYTYPE_A
: {
1812 TODO(); //TODO: Nothing for A PHYs yet :-/
1816 case BCM43xx_PHYTYPE_B
:
1817 case BCM43xx_PHYTYPE_G
: {
1823 s16 desired_pwr
, estimated_pwr
, pwr_adjust
;
1824 int radio_att_delta
, baseband_att_delta
;
1825 int radio_attenuation
, baseband_attenuation
;
1826 unsigned long phylock_flags
;
1828 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x0058);
1829 v0
= (s8
)(tmp
& 0x00FF);
1830 v1
= (s8
)((tmp
& 0xFF00) >> 8);
1831 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x005A);
1832 v2
= (s8
)(tmp
& 0x00FF);
1833 v3
= (s8
)((tmp
& 0xFF00) >> 8);
1836 if (v0
== 0x7F || v1
== 0x7F || v2
== 0x7F || v3
== 0x7F) {
1837 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x0070);
1838 v0
= (s8
)(tmp
& 0x00FF);
1839 v1
= (s8
)((tmp
& 0xFF00) >> 8);
1840 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x0072);
1841 v2
= (s8
)(tmp
& 0x00FF);
1842 v3
= (s8
)((tmp
& 0xFF00) >> 8);
1843 if (v0
== 0x7F || v1
== 0x7F || v2
== 0x7F || v3
== 0x7F)
1845 v0
= (v0
+ 0x20) & 0x3F;
1846 v1
= (v1
+ 0x20) & 0x3F;
1847 v2
= (v2
+ 0x20) & 0x3F;
1848 v3
= (v3
+ 0x20) & 0x3F;
1851 bcm43xx_shm_clear_tssi(dev
);
1853 average
= (v0
+ v1
+ v2
+ v3
+ 2) / 4;
1855 if (tmp
&& (bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x005E) & 0x8))
1858 estimated_pwr
= bcm43xx_phy_estimate_power_out(dev
, average
);
1860 max_pwr
= dev
->dev
->bus
->sprom
.r1
.maxpwr_bg
;
1862 if ((dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
) &&
1863 (phy
->type
== BCM43xx_PHYTYPE_G
))
1867 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
1868 where REG is the max power as per the regulatory domain
1871 desired_pwr
= phy
->power_level
;
1872 /* Convert the desired_pwr to Q5.2 and limit it. */
1873 desired_pwr
= limit_value((desired_pwr
<< 2), 0, max_pwr
);
1875 pwr_adjust
= desired_pwr
- estimated_pwr
;
1876 radio_att_delta
= -((pwr_adjust
+ 7) >> 3);
1877 baseband_att_delta
= (-(pwr_adjust
>> 1)) - (4 * radio_att_delta
);
1878 if ((radio_att_delta
== 0) && (baseband_att_delta
== 0)) {
1879 bcm43xx_lo_g_ctl_mark_cur_used(dev
);
1883 /* Calculate the new attenuation values. */
1884 baseband_attenuation
= phy
->bbatt
;
1885 baseband_attenuation
+= baseband_att_delta
;
1886 radio_attenuation
= phy
->rfatt
;
1887 radio_attenuation
+= radio_att_delta
;
1888 put_attenuation_into_ranges(dev
, &radio_attenuation
,
1889 &baseband_attenuation
);
1891 txpower
= phy
->txctl1
;
1892 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 2)) {
1893 if (radio_attenuation
<= 1) {
1896 radio_attenuation
+= 2;
1897 baseband_attenuation
+= 2;
1898 } else if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
) {
1899 baseband_attenuation
+= 4 * (radio_attenuation
- 2);
1900 radio_attenuation
= 2;
1902 } else if (radio_attenuation
> 4 && txpower
!= 0) {
1904 if (baseband_attenuation
< 3) {
1905 radio_attenuation
-= 3;
1906 baseband_attenuation
+= 2;
1908 radio_attenuation
-= 2;
1909 baseband_attenuation
-= 2;
1913 phy
->txctl1
= txpower
;
1914 baseband_attenuation
= limit_value(baseband_attenuation
, 0, 11);
1915 radio_attenuation
= limit_value(radio_attenuation
, 0, 9);
1917 bcm43xx_phy_lock(dev
, phylock_flags
);
1918 bcm43xx_radio_lock(dev
);
1919 bcm43xx_radio_set_txpower_bg(dev
, baseband_attenuation
,
1920 radio_attenuation
, txpower
);
1921 bcm43xx_lo_g_ctl_mark_cur_used(dev
);
1922 bcm43xx_radio_unlock(dev
);
1923 bcm43xx_phy_unlock(dev
, phylock_flags
);
1932 s32
bcm43xx_tssi2dbm_ad(s32 num
, s32 den
)
1937 return (num
+den
/2)/den
;
1941 s8
bcm43xx_tssi2dbm_entry(s8 entry
[], u8 index
, s16 pab0
, s16 pab1
, s16 pab2
)
1943 s32 m1
, m2
, f
= 256, q
, delta
;
1946 m1
= bcm43xx_tssi2dbm_ad(16 * pab0
+ index
* pab1
, 32);
1947 m2
= max(bcm43xx_tssi2dbm_ad(32768 + index
* pab2
, 256), 1);
1951 q
= bcm43xx_tssi2dbm_ad(f
* 4096 -
1952 bcm43xx_tssi2dbm_ad(m2
* f
, 16) * f
, 2048);
1956 } while (delta
>= 2);
1957 entry
[index
] = limit_value(bcm43xx_tssi2dbm_ad(m1
* f
, 8192), -127, 128);
1961 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1962 int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_wldev
*dev
)
1964 struct bcm43xx_phy
*phy
= &dev
->phy
;
1965 s16 pab0
, pab1
, pab2
;
1969 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
1970 pab0
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa1b0
);
1971 pab1
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa1b1
);
1972 pab2
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa1b2
);
1974 pab0
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa0b0
);
1975 pab1
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa0b1
);
1976 pab2
= (s16
)(dev
->dev
->bus
->sprom
.r1
.pa0b2
);
1979 if ((dev
->dev
->bus
->chip_id
== 0x4301) && (phy
->radio_ver
!= 0x2050)) {
1980 phy
->tgt_idle_tssi
= 0x34;
1981 phy
->tssi2dbm
= bcm43xx_tssi2dbm_b_table
;
1985 if (pab0
!= 0 && pab1
!= 0 && pab2
!= 0 &&
1986 pab0
!= -1 && pab1
!= -1 && pab2
!= -1) {
1987 /* The pabX values are set in SPROM. Use them. */
1988 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
1989 if ((s8
)dev
->dev
->bus
->sprom
.r1
.itssi_a
!= 0 &&
1990 (s8
)dev
->dev
->bus
->sprom
.r1
.itssi_a
!= -1)
1991 phy
->tgt_idle_tssi
= (s8
)(dev
->dev
->bus
->sprom
.r1
.itssi_a
);
1993 phy
->tgt_idle_tssi
= 62;
1995 if ((s8
)dev
->dev
->bus
->sprom
.r1
.itssi_bg
!= 0 &&
1996 (s8
)dev
->dev
->bus
->sprom
.r1
.itssi_bg
!= -1)
1997 phy
->tgt_idle_tssi
= (s8
)(dev
->dev
->bus
->sprom
.r1
.itssi_bg
);
1999 phy
->tgt_idle_tssi
= 62;
2001 dyn_tssi2dbm
= kmalloc(64, GFP_KERNEL
);
2002 if (dyn_tssi2dbm
== NULL
) {
2003 printk(KERN_ERR PFX
"Could not allocate memory"
2004 "for tssi2dbm table\n");
2007 for (idx
= 0; idx
< 64; idx
++)
2008 if (bcm43xx_tssi2dbm_entry(dyn_tssi2dbm
, idx
, pab0
, pab1
, pab2
)) {
2009 phy
->tssi2dbm
= NULL
;
2010 printk(KERN_ERR PFX
"Could not generate "
2011 "tssi2dBm table\n");
2012 kfree(dyn_tssi2dbm
);
2015 phy
->tssi2dbm
= dyn_tssi2dbm
;
2016 phy
->dyn_tssi_tbl
= 1;
2018 /* pabX values not set in SPROM. */
2019 switch (phy
->type
) {
2020 case BCM43xx_PHYTYPE_A
:
2021 /* APHY needs a generated table. */
2022 phy
->tssi2dbm
= NULL
;
2023 printk(KERN_ERR PFX
"Could not generate tssi2dBm "
2024 "table (wrong SPROM info)!\n");
2026 case BCM43xx_PHYTYPE_B
:
2027 phy
->tgt_idle_tssi
= 0x34;
2028 phy
->tssi2dbm
= bcm43xx_tssi2dbm_b_table
;
2030 case BCM43xx_PHYTYPE_G
:
2031 phy
->tgt_idle_tssi
= 0x34;
2032 phy
->tssi2dbm
= bcm43xx_tssi2dbm_g_table
;
2040 int bcm43xx_phy_init(struct bcm43xx_wldev
*dev
)
2042 struct bcm43xx_phy
*phy
= &dev
->phy
;
2045 switch (phy
->type
) {
2046 case BCM43xx_PHYTYPE_A
:
2047 if (phy
->rev
== 2 || phy
->rev
== 3) {
2048 bcm43xx_phy_inita(dev
);
2052 case BCM43xx_PHYTYPE_B
:
2055 bcm43xx_phy_initb2(dev
);
2059 bcm43xx_phy_initb4(dev
);
2063 bcm43xx_phy_initb5(dev
);
2067 bcm43xx_phy_initb6(dev
);
2072 case BCM43xx_PHYTYPE_G
:
2073 bcm43xx_phy_initg(dev
);
2078 printk(KERN_WARNING PFX
"Unknown PHYTYPE found!\n");
2083 void bcm43xx_set_rx_antenna(struct bcm43xx_wldev
*dev
, int antenna
)
2085 struct bcm43xx_phy
*phy
= &dev
->phy
;
2090 if (antenna
== BCM43xx_ANTENNA_AUTO0
||
2091 antenna
== BCM43xx_ANTENNA_AUTO1
)
2094 hf
= bcm43xx_hf_read(dev
);
2095 hf
&= ~BCM43xx_HF_ANTDIVHELP
;
2096 bcm43xx_hf_write(dev
, hf
);
2098 switch (phy
->type
) {
2099 case BCM43xx_PHYTYPE_A
:
2100 case BCM43xx_PHYTYPE_G
:
2101 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_BBANDCFG
);
2102 tmp
&= ~BCM43xx_PHY_BBANDCFG_RXANT
;
2103 tmp
|= (autodiv
? BCM43xx_ANTENNA_AUTO0
: antenna
)
2104 << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT
;
2105 bcm43xx_phy_write(dev
, BCM43xx_PHY_BBANDCFG
, tmp
);
2108 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ANTDWELL
);
2109 if (antenna
== BCM43xx_ANTENNA_AUTO0
)
2110 tmp
&= ~BCM43xx_PHY_ANTDWELL_AUTODIV1
;
2112 tmp
|= BCM43xx_PHY_ANTDWELL_AUTODIV1
;
2113 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANTDWELL
, tmp
);
2115 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
2116 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ANTWRSETT
);
2118 tmp
|= BCM43xx_PHY_ANTWRSETT_ARXDIV
;
2120 tmp
&= ~BCM43xx_PHY_ANTWRSETT_ARXDIV
;
2121 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANTWRSETT
, tmp
);
2122 if (phy
->rev
>= 2) {
2123 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_OFDM61
);
2124 tmp
|= BCM43xx_PHY_OFDM61_10
;
2125 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM61
, tmp
);
2127 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_DIVSRCHGAINBACK
);
2128 tmp
= (tmp
& 0xFF00) | 0x15;
2129 bcm43xx_phy_write(dev
, BCM43xx_PHY_DIVSRCHGAINBACK
, tmp
);
2131 if (phy
->rev
== 2) {
2132 bcm43xx_phy_write(dev
, BCM43xx_PHY_ADIVRELATED
, 8);
2134 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ADIVRELATED
);
2135 tmp
= (tmp
& 0xFF00) | 8;
2136 bcm43xx_phy_write(dev
, BCM43xx_PHY_ADIVRELATED
, tmp
);
2140 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM9B
, 0xDC);
2143 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ANTDWELL
);
2144 tmp
= (tmp
& 0xFF00) | 0x24;
2145 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANTDWELL
, tmp
);
2147 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_OFDM61
);
2149 bcm43xx_phy_write(dev
, BCM43xx_PHY_OFDM61
, tmp
);
2150 if (phy
->analog
== 3) {
2151 bcm43xx_phy_write(dev
, BCM43xx_PHY_CLIPPWRDOWNT
, 0x1D);
2152 bcm43xx_phy_write(dev
, BCM43xx_PHY_ADIVRELATED
, 8);
2154 bcm43xx_phy_write(dev
, BCM43xx_PHY_CLIPPWRDOWNT
, 0x3A);
2155 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ADIVRELATED
);
2156 tmp
= (tmp
& 0xFF00) | 8;
2157 bcm43xx_phy_write(dev
, BCM43xx_PHY_ADIVRELATED
, tmp
);
2162 case BCM43xx_PHYTYPE_B
:
2163 tmp
= bcm43xx_phy_read(dev
, BCM43xx_PHY_CCKBBANDCFG
);
2164 tmp
&= ~BCM43xx_PHY_BBANDCFG_RXANT
;
2165 tmp
|= (autodiv
? BCM43xx_ANTENNA_AUTO0
: antenna
)
2166 << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT
;
2167 bcm43xx_phy_write(dev
, BCM43xx_PHY_CCKBBANDCFG
, tmp
);
2173 hf
|= BCM43xx_HF_ANTDIVHELP
;
2174 bcm43xx_hf_write(dev
, hf
);
2177 /* Get the freq, as it has to be written to the device. */
2179 u16
channel2freq_bg(u8 channel
)
2181 assert(channel
>= 1 && channel
<= 14);
2183 return bcm43xx_radio_channel_codes_bg
[channel
- 1];
2186 /* Get the freq, as it has to be written to the device. */
2188 u16
channel2freq_a(u8 channel
)
2190 assert(channel
<= 200);
2192 return (5000 + 5 * channel
);
2195 void bcm43xx_radio_lock(struct bcm43xx_wldev
*dev
)
2199 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
2200 status
|= BCM43xx_SBF_RADIOREG_LOCK
;
2201 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
2206 void bcm43xx_radio_unlock(struct bcm43xx_wldev
*dev
)
2210 bcm43xx_read16(dev
, BCM43xx_MMIO_PHY_VER
); /* dummy read */
2211 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
2212 status
&= ~BCM43xx_SBF_RADIOREG_LOCK
;
2213 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
2217 u16
bcm43xx_radio_read16(struct bcm43xx_wldev
*dev
, u16 offset
)
2219 struct bcm43xx_phy
*phy
= &dev
->phy
;
2221 switch (phy
->type
) {
2222 case BCM43xx_PHYTYPE_A
:
2225 case BCM43xx_PHYTYPE_B
:
2226 if (phy
->radio_ver
== 0x2053) {
2229 else if (offset
< 0x80)
2231 } else if (phy
->radio_ver
== 0x2050) {
2236 case BCM43xx_PHYTYPE_G
:
2241 bcm43xx_write16(dev
, BCM43xx_MMIO_RADIO_CONTROL
, offset
);
2242 return bcm43xx_read16(dev
, BCM43xx_MMIO_RADIO_DATA_LOW
);
2245 void bcm43xx_radio_write16(struct bcm43xx_wldev
*dev
, u16 offset
, u16 val
)
2247 bcm43xx_write16(dev
, BCM43xx_MMIO_RADIO_CONTROL
, offset
);
2249 bcm43xx_write16(dev
, BCM43xx_MMIO_RADIO_DATA_LOW
, val
);
2252 static void bcm43xx_set_all_gains(struct bcm43xx_wldev
*dev
,
2253 s16 first
, s16 second
, s16 third
)
2255 struct bcm43xx_phy
*phy
= &dev
->phy
;
2257 u16 start
= 0x08, end
= 0x18;
2261 if (phy
->rev
<= 1) {
2266 table
= BCM43xx_OFDMTAB_GAINX
;
2268 table
= BCM43xx_OFDMTAB_GAINX_R1
;
2269 for (i
= 0; i
< 4; i
++)
2270 bcm43xx_ofdmtab_write16(dev
, table
, i
, first
);
2272 for (i
= start
; i
< end
; i
++)
2273 bcm43xx_ofdmtab_write16(dev
, table
, i
, second
);
2276 tmp
= ((u16
)third
<< 14) | ((u16
)third
<< 6);
2277 bcm43xx_phy_write(dev
, 0x04A0,
2278 (bcm43xx_phy_read(dev
, 0x04A0) & 0xBFBF) | tmp
);
2279 bcm43xx_phy_write(dev
, 0x04A1,
2280 (bcm43xx_phy_read(dev
, 0x04A1) & 0xBFBF) | tmp
);
2281 bcm43xx_phy_write(dev
, 0x04A2,
2282 (bcm43xx_phy_read(dev
, 0x04A2) & 0xBFBF) | tmp
);
2284 bcm43xx_dummy_transmission(dev
);
2287 static void bcm43xx_set_original_gains(struct bcm43xx_wldev
*dev
)
2289 struct bcm43xx_phy
*phy
= &dev
->phy
;
2292 u16 start
= 0x0008, end
= 0x0018;
2294 if (phy
->rev
<= 1) {
2299 table
= BCM43xx_OFDMTAB_GAINX
;
2301 table
= BCM43xx_OFDMTAB_GAINX_R1
;
2302 for (i
= 0; i
< 4; i
++) {
2304 tmp
|= (i
& 0x0001) << 1;
2305 tmp
|= (i
& 0x0002) >> 1;
2307 bcm43xx_ofdmtab_write16(dev
, table
, i
, tmp
);
2310 for (i
= start
; i
< end
; i
++)
2311 bcm43xx_ofdmtab_write16(dev
, table
, i
, i
- start
);
2313 bcm43xx_phy_write(dev
, 0x04A0,
2314 (bcm43xx_phy_read(dev
, 0x04A0) & 0xBFBF) | 0x4040);
2315 bcm43xx_phy_write(dev
, 0x04A1,
2316 (bcm43xx_phy_read(dev
, 0x04A1) & 0xBFBF) | 0x4040);
2317 bcm43xx_phy_write(dev
, 0x04A2,
2318 (bcm43xx_phy_read(dev
, 0x04A2) & 0xBFBF) | 0x4000);
2319 bcm43xx_dummy_transmission(dev
);
2322 /* Synthetic PU workaround */
2323 static void bcm43xx_synth_pu_workaround(struct bcm43xx_wldev
*dev
, u8 channel
)
2325 struct bcm43xx_phy
*phy
= &dev
->phy
;
2327 if (phy
->radio_ver
!= 0x2050 || phy
->radio_rev
>= 6) {
2328 /* We do not need the workaround. */
2332 if (channel
<= 10) {
2333 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL
,
2334 channel2freq_bg(channel
+ 4));
2336 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL
,
2337 channel2freq_bg(1));
2340 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL
,
2341 channel2freq_bg(channel
));
2344 u8
bcm43xx_radio_aci_detect(struct bcm43xx_wldev
*dev
, u8 channel
)
2346 struct bcm43xx_phy
*phy
= &dev
->phy
;
2348 u16 saved
, rssi
, temp
;
2351 saved
= bcm43xx_phy_read(dev
, 0x0403);
2352 bcm43xx_radio_selectchannel(dev
, channel
, 0);
2353 bcm43xx_phy_write(dev
, 0x0403, (saved
& 0xFFF8) | 5);
2354 if (phy
->aci_hw_rssi
)
2355 rssi
= bcm43xx_phy_read(dev
, 0x048A) & 0x3F;
2357 rssi
= saved
& 0x3F;
2358 /* clamp temp to signed 5bit */
2361 for (i
= 0;i
< 100; i
++) {
2362 temp
= (bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x3F;
2370 bcm43xx_phy_write(dev
, 0x0403, saved
);
2375 u8
bcm43xx_radio_aci_scan(struct bcm43xx_wldev
*dev
)
2377 struct bcm43xx_phy
*phy
= &dev
->phy
;
2379 unsigned int channel
= phy
->channel
;
2380 unsigned int i
, j
, start
, end
;
2381 unsigned long phylock_flags
;
2383 if (!((phy
->type
== BCM43xx_PHYTYPE_G
) && (phy
->rev
> 0)))
2386 bcm43xx_phy_lock(dev
, phylock_flags
);
2387 bcm43xx_radio_lock(dev
);
2388 bcm43xx_phy_write(dev
, 0x0802,
2389 bcm43xx_phy_read(dev
, 0x0802) & 0xFFFC);
2390 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
2391 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) & 0x7FFF);
2392 bcm43xx_set_all_gains(dev
, 3, 8, 1);
2394 start
= (channel
- 5 > 0) ? channel
- 5 : 1;
2395 end
= (channel
+ 5 < 14) ? channel
+ 5 : 13;
2397 for (i
= start
; i
<= end
; i
++) {
2398 if (abs(channel
- i
) > 2)
2399 ret
[i
-1] = bcm43xx_radio_aci_detect(dev
, i
);
2401 bcm43xx_radio_selectchannel(dev
, channel
, 0);
2402 bcm43xx_phy_write(dev
, 0x0802,
2403 (bcm43xx_phy_read(dev
, 0x0802) & 0xFFFC) | 0x0003);
2404 bcm43xx_phy_write(dev
, 0x0403,
2405 bcm43xx_phy_read(dev
, 0x0403) & 0xFFF8);
2406 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
2407 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) | 0x8000);
2408 bcm43xx_set_original_gains(dev
);
2409 for (i
= 0; i
< 13; i
++) {
2412 end
= (i
+ 5 < 13) ? i
+ 5 : 13;
2413 for (j
= i
; j
< end
; j
++)
2416 bcm43xx_radio_unlock(dev
);
2417 bcm43xx_phy_unlock(dev
, phylock_flags
);
2419 return ret
[channel
- 1];
2422 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2423 void bcm43xx_nrssi_hw_write(struct bcm43xx_wldev
*dev
, u16 offset
, s16 val
)
2425 bcm43xx_phy_write(dev
, BCM43xx_PHY_NRSSILT_CTRL
, offset
);
2427 bcm43xx_phy_write(dev
, BCM43xx_PHY_NRSSILT_DATA
, (u16
)val
);
2430 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2431 s16
bcm43xx_nrssi_hw_read(struct bcm43xx_wldev
*dev
, u16 offset
)
2435 bcm43xx_phy_write(dev
, BCM43xx_PHY_NRSSILT_CTRL
, offset
);
2436 val
= bcm43xx_phy_read(dev
, BCM43xx_PHY_NRSSILT_DATA
);
2441 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2442 void bcm43xx_nrssi_hw_update(struct bcm43xx_wldev
*dev
, u16 val
)
2447 for (i
= 0; i
< 64; i
++) {
2448 tmp
= bcm43xx_nrssi_hw_read(dev
, i
);
2450 tmp
= limit_value(tmp
, -32, 31);
2451 bcm43xx_nrssi_hw_write(dev
, i
, tmp
);
2455 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2456 void bcm43xx_nrssi_mem_update(struct bcm43xx_wldev
*dev
)
2458 struct bcm43xx_phy
*phy
= &dev
->phy
;
2462 delta
= 0x1F - phy
->nrssi
[0];
2463 for (i
= 0; i
< 64; i
++) {
2464 tmp
= (i
- delta
) * phy
->nrssislope
;
2467 tmp
= limit_value(tmp
, 0, 0x3F);
2468 phy
->nrssi_lt
[i
] = tmp
;
2472 static void bcm43xx_calc_nrssi_offset(struct bcm43xx_wldev
*dev
)
2474 struct bcm43xx_phy
*phy
= &dev
->phy
;
2475 u16 backup
[20] = { 0 };
2480 backup
[0] = bcm43xx_phy_read(dev
, 0x0001);
2481 backup
[1] = bcm43xx_phy_read(dev
, 0x0811);
2482 backup
[2] = bcm43xx_phy_read(dev
, 0x0812);
2483 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2484 backup
[3] = bcm43xx_phy_read(dev
, 0x0814);
2485 backup
[4] = bcm43xx_phy_read(dev
, 0x0815);
2487 backup
[5] = bcm43xx_phy_read(dev
, 0x005A);
2488 backup
[6] = bcm43xx_phy_read(dev
, 0x0059);
2489 backup
[7] = bcm43xx_phy_read(dev
, 0x0058);
2490 backup
[8] = bcm43xx_phy_read(dev
, 0x000A);
2491 backup
[9] = bcm43xx_phy_read(dev
, 0x0003);
2492 backup
[10] = bcm43xx_radio_read16(dev
, 0x007A);
2493 backup
[11] = bcm43xx_radio_read16(dev
, 0x0043);
2495 bcm43xx_phy_write(dev
, 0x0429,
2496 bcm43xx_phy_read(dev
, 0x0429) & 0x7FFF);
2497 bcm43xx_phy_write(dev
, 0x0001,
2498 (bcm43xx_phy_read(dev
, 0x0001) & 0x3FFF) | 0x4000);
2499 bcm43xx_phy_write(dev
, 0x0811,
2500 bcm43xx_phy_read(dev
, 0x0811) | 0x000C);
2501 bcm43xx_phy_write(dev
, 0x0812,
2502 (bcm43xx_phy_read(dev
, 0x0812) & 0xFFF3) | 0x0004);
2503 bcm43xx_phy_write(dev
, 0x0802,
2504 bcm43xx_phy_read(dev
, 0x0802) & ~(0x1 | 0x2));
2505 if (phy
->rev
>= 6) {
2506 backup
[12] = bcm43xx_phy_read(dev
, 0x002E);
2507 backup
[13] = bcm43xx_phy_read(dev
, 0x002F);
2508 backup
[14] = bcm43xx_phy_read(dev
, 0x080F);
2509 backup
[15] = bcm43xx_phy_read(dev
, 0x0810);
2510 backup
[16] = bcm43xx_phy_read(dev
, 0x0801);
2511 backup
[17] = bcm43xx_phy_read(dev
, 0x0060);
2512 backup
[18] = bcm43xx_phy_read(dev
, 0x0014);
2513 backup
[19] = bcm43xx_phy_read(dev
, 0x0478);
2515 bcm43xx_phy_write(dev
, 0x002E, 0);
2516 bcm43xx_phy_write(dev
, 0x002F, 0);
2517 bcm43xx_phy_write(dev
, 0x080F, 0);
2518 bcm43xx_phy_write(dev
, 0x0810, 0);
2519 bcm43xx_phy_write(dev
, 0x0478,
2520 bcm43xx_phy_read(dev
, 0x0478) | 0x0100);
2521 bcm43xx_phy_write(dev
, 0x0801,
2522 bcm43xx_phy_read(dev
, 0x0801) | 0x0040);
2523 bcm43xx_phy_write(dev
, 0x0060,
2524 bcm43xx_phy_read(dev
, 0x0060) | 0x0040);
2525 bcm43xx_phy_write(dev
, 0x0014,
2526 bcm43xx_phy_read(dev
, 0x0014) | 0x0200);
2528 bcm43xx_radio_write16(dev
, 0x007A,
2529 bcm43xx_radio_read16(dev
, 0x007A) | 0x0070);
2530 bcm43xx_radio_write16(dev
, 0x007A,
2531 bcm43xx_radio_read16(dev
, 0x007A) | 0x0080);
2534 v47F
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2538 for (i
= 7; i
>= 4; i
--) {
2539 bcm43xx_radio_write16(dev
, 0x007B, i
);
2541 v47F
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2544 if (v47F
< 31 && saved
== 0xFFFF)
2547 if (saved
== 0xFFFF)
2550 bcm43xx_radio_write16(dev
, 0x007A,
2551 bcm43xx_radio_read16(dev
, 0x007A) & 0x007F);
2552 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2553 bcm43xx_phy_write(dev
, 0x0814,
2554 bcm43xx_phy_read(dev
, 0x0814) | 0x0001);
2555 bcm43xx_phy_write(dev
, 0x0815,
2556 bcm43xx_phy_read(dev
, 0x0815) & 0xFFFE);
2558 bcm43xx_phy_write(dev
, 0x0811,
2559 bcm43xx_phy_read(dev
, 0x0811) | 0x000C);
2560 bcm43xx_phy_write(dev
, 0x0812,
2561 bcm43xx_phy_read(dev
, 0x0812) | 0x000C);
2562 bcm43xx_phy_write(dev
, 0x0811,
2563 bcm43xx_phy_read(dev
, 0x0811) | 0x0030);
2564 bcm43xx_phy_write(dev
, 0x0812,
2565 bcm43xx_phy_read(dev
, 0x0812) | 0x0030);
2566 bcm43xx_phy_write(dev
, 0x005A, 0x0480);
2567 bcm43xx_phy_write(dev
, 0x0059, 0x0810);
2568 bcm43xx_phy_write(dev
, 0x0058, 0x000D);
2569 if (phy
->rev
== 0) {
2570 bcm43xx_phy_write(dev
, 0x0003, 0x0122);
2572 bcm43xx_phy_write(dev
, 0x000A,
2573 bcm43xx_phy_read(dev
, 0x000A)
2576 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2577 bcm43xx_phy_write(dev
, 0x0814,
2578 bcm43xx_phy_read(dev
, 0x0814) | 0x0004);
2579 bcm43xx_phy_write(dev
, 0x0815,
2580 bcm43xx_phy_read(dev
, 0x0815) & 0xFFFB);
2582 bcm43xx_phy_write(dev
, 0x0003,
2583 (bcm43xx_phy_read(dev
, 0x0003) & 0xFF9F)
2585 bcm43xx_radio_write16(dev
, 0x007A,
2586 bcm43xx_radio_read16(dev
, 0x007A) | 0x000F);
2587 bcm43xx_set_all_gains(dev
, 3, 0, 1);
2588 bcm43xx_radio_write16(dev
, 0x0043,
2589 (bcm43xx_radio_read16(dev
, 0x0043)
2590 & 0x00F0) | 0x000F);
2592 v47F
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2596 for (i
= 0; i
< 4; i
++) {
2597 bcm43xx_radio_write16(dev
, 0x007B, i
);
2599 v47F
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2602 if (v47F
> -31 && saved
== 0xFFFF)
2605 if (saved
== 0xFFFF)
2610 bcm43xx_radio_write16(dev
, 0x007B, saved
);
2612 if (phy
->rev
>= 6) {
2613 bcm43xx_phy_write(dev
, 0x002E, backup
[12]);
2614 bcm43xx_phy_write(dev
, 0x002F, backup
[13]);
2615 bcm43xx_phy_write(dev
, 0x080F, backup
[14]);
2616 bcm43xx_phy_write(dev
, 0x0810, backup
[15]);
2618 if (phy
->rev
!= 1) { /* Not in specs, but needed to prevent PPC machine check */
2619 bcm43xx_phy_write(dev
, 0x0814, backup
[3]);
2620 bcm43xx_phy_write(dev
, 0x0815, backup
[4]);
2622 bcm43xx_phy_write(dev
, 0x005A, backup
[5]);
2623 bcm43xx_phy_write(dev
, 0x0059, backup
[6]);
2624 bcm43xx_phy_write(dev
, 0x0058, backup
[7]);
2625 bcm43xx_phy_write(dev
, 0x000A, backup
[8]);
2626 bcm43xx_phy_write(dev
, 0x0003, backup
[9]);
2627 bcm43xx_radio_write16(dev
, 0x0043, backup
[11]);
2628 bcm43xx_radio_write16(dev
, 0x007A, backup
[10]);
2629 bcm43xx_phy_write(dev
, 0x0802,
2630 bcm43xx_phy_read(dev
, 0x0802) | 0x1 | 0x2);
2631 bcm43xx_phy_write(dev
, 0x0429,
2632 bcm43xx_phy_read(dev
, 0x0429) | 0x8000);
2633 bcm43xx_set_original_gains(dev
);
2634 if (phy
->rev
>= 6) {
2635 bcm43xx_phy_write(dev
, 0x0801, backup
[16]);
2636 bcm43xx_phy_write(dev
, 0x0060, backup
[17]);
2637 bcm43xx_phy_write(dev
, 0x0014, backup
[18]);
2638 bcm43xx_phy_write(dev
, 0x0478, backup
[19]);
2640 bcm43xx_phy_write(dev
, 0x0001, backup
[0]);
2641 bcm43xx_phy_write(dev
, 0x0812, backup
[2]);
2642 bcm43xx_phy_write(dev
, 0x0811, backup
[1]);
2645 void bcm43xx_calc_nrssi_slope(struct bcm43xx_wldev
*dev
)
2647 struct bcm43xx_phy
*phy
= &dev
->phy
;
2648 u16 backup
[18] = { 0 };
2652 switch (phy
->type
) {
2653 case BCM43xx_PHYTYPE_B
:
2654 backup
[0] = bcm43xx_radio_read16(dev
, 0x007A);
2655 backup
[1] = bcm43xx_radio_read16(dev
, 0x0052);
2656 backup
[2] = bcm43xx_radio_read16(dev
, 0x0043);
2657 backup
[3] = bcm43xx_phy_read(dev
, 0x0030);
2658 backup
[4] = bcm43xx_phy_read(dev
, 0x0026);
2659 backup
[5] = bcm43xx_phy_read(dev
, 0x0015);
2660 backup
[6] = bcm43xx_phy_read(dev
, 0x002A);
2661 backup
[7] = bcm43xx_phy_read(dev
, 0x0020);
2662 backup
[8] = bcm43xx_phy_read(dev
, 0x005A);
2663 backup
[9] = bcm43xx_phy_read(dev
, 0x0059);
2664 backup
[10] = bcm43xx_phy_read(dev
, 0x0058);
2665 backup
[11] = bcm43xx_read16(dev
, 0x03E2);
2666 backup
[12] = bcm43xx_read16(dev
, 0x03E6);
2667 backup
[13] = bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
);
2669 tmp
= bcm43xx_radio_read16(dev
, 0x007A);
2670 tmp
&= (phy
->rev
>= 5) ? 0x007F : 0x000F;
2671 bcm43xx_radio_write16(dev
, 0x007A, tmp
);
2672 bcm43xx_phy_write(dev
, 0x0030, 0x00FF);
2673 bcm43xx_write16(dev
, 0x03EC, 0x7F7F);
2674 bcm43xx_phy_write(dev
, 0x0026, 0x0000);
2675 bcm43xx_phy_write(dev
, 0x0015,
2676 bcm43xx_phy_read(dev
, 0x0015) | 0x0020);
2677 bcm43xx_phy_write(dev
, 0x002A, 0x08A3);
2678 bcm43xx_radio_write16(dev
, 0x007A,
2679 bcm43xx_radio_read16(dev
, 0x007A) | 0x0080);
2681 nrssi0
= (s16
)bcm43xx_phy_read(dev
, 0x0027);
2682 bcm43xx_radio_write16(dev
, 0x007A,
2683 bcm43xx_radio_read16(dev
, 0x007A) & 0x007F);
2684 if (phy
->rev
>= 2) {
2685 bcm43xx_write16(dev
, 0x03E6, 0x0040);
2686 } else if (phy
->rev
== 0) {
2687 bcm43xx_write16(dev
, 0x03E6, 0x0122);
2689 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
,
2690 bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
) & 0x2000);
2692 bcm43xx_phy_write(dev
, 0x0020, 0x3F3F);
2693 bcm43xx_phy_write(dev
, 0x0015, 0xF330);
2694 bcm43xx_radio_write16(dev
, 0x005A, 0x0060);
2695 bcm43xx_radio_write16(dev
, 0x0043,
2696 bcm43xx_radio_read16(dev
, 0x0043) & 0x00F0);
2697 bcm43xx_phy_write(dev
, 0x005A, 0x0480);
2698 bcm43xx_phy_write(dev
, 0x0059, 0x0810);
2699 bcm43xx_phy_write(dev
, 0x0058, 0x000D);
2702 nrssi1
= (s16
)bcm43xx_phy_read(dev
, 0x0027);
2703 bcm43xx_phy_write(dev
, 0x0030, backup
[3]);
2704 bcm43xx_radio_write16(dev
, 0x007A, backup
[0]);
2705 bcm43xx_write16(dev
, 0x03E2, backup
[11]);
2706 bcm43xx_phy_write(dev
, 0x0026, backup
[4]);
2707 bcm43xx_phy_write(dev
, 0x0015, backup
[5]);
2708 bcm43xx_phy_write(dev
, 0x002A, backup
[6]);
2709 bcm43xx_synth_pu_workaround(dev
, phy
->channel
);
2711 bcm43xx_write16(dev
, 0x03F4, backup
[13]);
2713 bcm43xx_phy_write(dev
, 0x0020, backup
[7]);
2714 bcm43xx_phy_write(dev
, 0x005A, backup
[8]);
2715 bcm43xx_phy_write(dev
, 0x0059, backup
[9]);
2716 bcm43xx_phy_write(dev
, 0x0058, backup
[10]);
2717 bcm43xx_radio_write16(dev
, 0x0052, backup
[1]);
2718 bcm43xx_radio_write16(dev
, 0x0043, backup
[2]);
2720 if (nrssi0
== nrssi1
)
2721 phy
->nrssislope
= 0x00010000;
2723 phy
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
2726 phy
->nrssi
[0] = nrssi0
;
2727 phy
->nrssi
[1] = nrssi1
;
2730 case BCM43xx_PHYTYPE_G
:
2731 if (phy
->radio_rev
>= 9)
2733 if (phy
->radio_rev
== 8)
2734 bcm43xx_calc_nrssi_offset(dev
);
2736 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
2737 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) & 0x7FFF);
2738 bcm43xx_phy_write(dev
, 0x0802,
2739 bcm43xx_phy_read(dev
, 0x0802) & 0xFFFC);
2740 backup
[7] = bcm43xx_read16(dev
, 0x03E2);
2741 bcm43xx_write16(dev
, 0x03E2,
2742 bcm43xx_read16(dev
, 0x03E2) | 0x8000);
2743 backup
[0] = bcm43xx_radio_read16(dev
, 0x007A);
2744 backup
[1] = bcm43xx_radio_read16(dev
, 0x0052);
2745 backup
[2] = bcm43xx_radio_read16(dev
, 0x0043);
2746 backup
[3] = bcm43xx_phy_read(dev
, 0x0015);
2747 backup
[4] = bcm43xx_phy_read(dev
, 0x005A);
2748 backup
[5] = bcm43xx_phy_read(dev
, 0x0059);
2749 backup
[6] = bcm43xx_phy_read(dev
, 0x0058);
2750 backup
[8] = bcm43xx_read16(dev
, 0x03E6);
2751 backup
[9] = bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
);
2752 if (phy
->rev
>= 3) {
2753 backup
[10] = bcm43xx_phy_read(dev
, 0x002E);
2754 backup
[11] = bcm43xx_phy_read(dev
, 0x002F);
2755 backup
[12] = bcm43xx_phy_read(dev
, 0x080F);
2756 backup
[13] = bcm43xx_phy_read(dev
, BCM43xx_PHY_G_LO_CONTROL
);
2757 backup
[14] = bcm43xx_phy_read(dev
, 0x0801);
2758 backup
[15] = bcm43xx_phy_read(dev
, 0x0060);
2759 backup
[16] = bcm43xx_phy_read(dev
, 0x0014);
2760 backup
[17] = bcm43xx_phy_read(dev
, 0x0478);
2761 bcm43xx_phy_write(dev
, 0x002E, 0);
2762 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_LO_CONTROL
, 0);
2764 case 4: case 6: case 7:
2765 bcm43xx_phy_write(dev
, 0x0478,
2766 bcm43xx_phy_read(dev
, 0x0478)
2768 bcm43xx_phy_write(dev
, 0x0801,
2769 bcm43xx_phy_read(dev
, 0x0801)
2773 bcm43xx_phy_write(dev
, 0x0801,
2774 bcm43xx_phy_read(dev
, 0x0801)
2778 bcm43xx_phy_write(dev
, 0x0060,
2779 bcm43xx_phy_read(dev
, 0x0060)
2781 bcm43xx_phy_write(dev
, 0x0014,
2782 bcm43xx_phy_read(dev
, 0x0014)
2785 bcm43xx_radio_write16(dev
, 0x007A,
2786 bcm43xx_radio_read16(dev
, 0x007A) | 0x0070);
2787 bcm43xx_set_all_gains(dev
, 0, 8, 0);
2788 bcm43xx_radio_write16(dev
, 0x007A,
2789 bcm43xx_radio_read16(dev
, 0x007A) & 0x00F7);
2790 if (phy
->rev
>= 2) {
2791 bcm43xx_phy_write(dev
, 0x0811,
2792 (bcm43xx_phy_read(dev
, 0x0811) & 0xFFCF) | 0x0030);
2793 bcm43xx_phy_write(dev
, 0x0812,
2794 (bcm43xx_phy_read(dev
, 0x0812) & 0xFFCF) | 0x0010);
2796 bcm43xx_radio_write16(dev
, 0x007A,
2797 bcm43xx_radio_read16(dev
, 0x007A) | 0x0080);
2800 nrssi0
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2801 if (nrssi0
>= 0x0020)
2804 bcm43xx_radio_write16(dev
, 0x007A,
2805 bcm43xx_radio_read16(dev
, 0x007A) & 0x007F);
2806 if (phy
->rev
>= 2) {
2807 bcm43xx_phy_write(dev
, 0x0003,
2808 (bcm43xx_phy_read(dev
, 0x0003)
2809 & 0xFF9F) | 0x0040);
2812 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
,
2813 bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
)
2815 bcm43xx_radio_write16(dev
, 0x007A,
2816 bcm43xx_radio_read16(dev
, 0x007A) | 0x000F);
2817 bcm43xx_phy_write(dev
, 0x0015, 0xF330);
2818 if (phy
->rev
>= 2) {
2819 bcm43xx_phy_write(dev
, 0x0812,
2820 (bcm43xx_phy_read(dev
, 0x0812) & 0xFFCF) | 0x0020);
2821 bcm43xx_phy_write(dev
, 0x0811,
2822 (bcm43xx_phy_read(dev
, 0x0811) & 0xFFCF) | 0x0020);
2825 bcm43xx_set_all_gains(dev
, 3, 0, 1);
2826 if (phy
->radio_rev
== 8) {
2827 bcm43xx_radio_write16(dev
, 0x0043, 0x001F);
2829 tmp
= bcm43xx_radio_read16(dev
, 0x0052) & 0xFF0F;
2830 bcm43xx_radio_write16(dev
, 0x0052, tmp
| 0x0060);
2831 tmp
= bcm43xx_radio_read16(dev
, 0x0043) & 0xFFF0;
2832 bcm43xx_radio_write16(dev
, 0x0043, tmp
| 0x0009);
2834 bcm43xx_phy_write(dev
, 0x005A, 0x0480);
2835 bcm43xx_phy_write(dev
, 0x0059, 0x0810);
2836 bcm43xx_phy_write(dev
, 0x0058, 0x000D);
2838 nrssi1
= (s16
)((bcm43xx_phy_read(dev
, 0x047F) >> 8) & 0x003F);
2839 if (nrssi1
>= 0x0020)
2841 if (nrssi0
== nrssi1
)
2842 phy
->nrssislope
= 0x00010000;
2844 phy
->nrssislope
= 0x00400000 / (nrssi0
- nrssi1
);
2846 phy
->nrssi
[0] = nrssi1
;
2847 phy
->nrssi
[1] = nrssi0
;
2849 if (phy
->rev
>= 3) {
2850 bcm43xx_phy_write(dev
, 0x002E, backup
[10]);
2851 bcm43xx_phy_write(dev
, 0x002F, backup
[11]);
2852 bcm43xx_phy_write(dev
, 0x080F, backup
[12]);
2853 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_LO_CONTROL
, backup
[13]);
2855 if (phy
->rev
>= 2) {
2856 bcm43xx_phy_write(dev
, 0x0812,
2857 bcm43xx_phy_read(dev
, 0x0812) & 0xFFCF);
2858 bcm43xx_phy_write(dev
, 0x0811,
2859 bcm43xx_phy_read(dev
, 0x0811) & 0xFFCF);
2862 bcm43xx_radio_write16(dev
, 0x007A, backup
[0]);
2863 bcm43xx_radio_write16(dev
, 0x0052, backup
[1]);
2864 bcm43xx_radio_write16(dev
, 0x0043, backup
[2]);
2865 bcm43xx_write16(dev
, 0x03E2, backup
[7]);
2866 bcm43xx_write16(dev
, 0x03E6, backup
[8]);
2867 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
, backup
[9]);
2868 bcm43xx_phy_write(dev
, 0x0015, backup
[3]);
2869 bcm43xx_phy_write(dev
, 0x005A, backup
[4]);
2870 bcm43xx_phy_write(dev
, 0x0059, backup
[5]);
2871 bcm43xx_phy_write(dev
, 0x0058, backup
[6]);
2872 bcm43xx_synth_pu_workaround(dev
, phy
->channel
);
2873 bcm43xx_phy_write(dev
, 0x0802,
2874 bcm43xx_phy_read(dev
, 0x0802) | (0x0001 | 0x0002));
2875 bcm43xx_set_original_gains(dev
);
2876 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
2877 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) | 0x8000);
2878 if (phy
->rev
>= 3) {
2879 bcm43xx_phy_write(dev
, 0x0801, backup
[14]);
2880 bcm43xx_phy_write(dev
, 0x0060, backup
[15]);
2881 bcm43xx_phy_write(dev
, 0x0014, backup
[16]);
2882 bcm43xx_phy_write(dev
, 0x0478, backup
[17]);
2884 bcm43xx_nrssi_mem_update(dev
);
2885 bcm43xx_calc_nrssi_threshold(dev
);
2892 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_wldev
*dev
)
2894 struct bcm43xx_phy
*phy
= &dev
->phy
;
2900 switch (phy
->type
) {
2901 case BCM43xx_PHYTYPE_B
: {
2902 if (phy
->radio_ver
!= 0x2050)
2904 if (!(dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
))
2907 if (phy
->radio_rev
>= 6) {
2908 threshold
= (phy
->nrssi
[1] - phy
->nrssi
[0]) * 32;
2909 threshold
+= 20 * (phy
->nrssi
[0] + 1);
2912 threshold
= phy
->nrssi
[1] - 5;
2914 threshold
= limit_value(threshold
, 0, 0x3E);
2915 bcm43xx_phy_read(dev
, 0x0020); /* dummy read */
2916 bcm43xx_phy_write(dev
, 0x0020, (((u16
)threshold
) << 8) | 0x001C);
2918 if (phy
->radio_rev
>= 6) {
2919 bcm43xx_phy_write(dev
, 0x0087, 0x0E0D);
2920 bcm43xx_phy_write(dev
, 0x0086, 0x0C0B);
2921 bcm43xx_phy_write(dev
, 0x0085, 0x0A09);
2922 bcm43xx_phy_write(dev
, 0x0084, 0x0808);
2923 bcm43xx_phy_write(dev
, 0x0083, 0x0808);
2924 bcm43xx_phy_write(dev
, 0x0082, 0x0604);
2925 bcm43xx_phy_write(dev
, 0x0081, 0x0302);
2926 bcm43xx_phy_write(dev
, 0x0080, 0x0100);
2930 case BCM43xx_PHYTYPE_G
:
2932 !(dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
)) {
2933 tmp16
= bcm43xx_nrssi_hw_read(dev
, 0x20);
2937 bcm43xx_phy_write(dev
, 0x048A,
2938 (bcm43xx_phy_read(dev
, 0x048A)
2939 & 0xF000) | 0x09EB);
2941 bcm43xx_phy_write(dev
, 0x048A,
2942 (bcm43xx_phy_read(dev
, 0x048A)
2943 & 0xF000) | 0x0AED);
2946 if (phy
->interfmode
== BCM43xx_INTERFMODE_NONWLAN
) {
2949 } else if (!phy
->aci_wlan_automatic
&& phy
->aci_enable
) {
2957 a
= a
* (phy
->nrssi
[1] - phy
->nrssi
[0]);
2958 a
+= (phy
->nrssi
[0] << 6);
2964 a
= limit_value(a
, -31, 31);
2966 b
= b
* (phy
->nrssi
[1] - phy
->nrssi
[0]);
2967 b
+= (phy
->nrssi
[0] << 6);
2973 b
= limit_value(b
, -31, 31);
2975 tmp_u16
= bcm43xx_phy_read(dev
, 0x048A) & 0xF000;
2976 tmp_u16
|= ((u32
)b
& 0x0000003F);
2977 tmp_u16
|= (((u32
)a
& 0x0000003F) << 6);
2978 bcm43xx_phy_write(dev
, 0x048A, tmp_u16
);
2986 /* Stack implementation to save/restore values from the
2987 * interference mitigation code.
2988 * It is save to restore values in random order.
2990 static void _stack_save(u32
*_stackptr
, size_t *stackidx
,
2991 u8 id
, u16 offset
, u16 value
)
2993 u32
*stackptr
= &(_stackptr
[*stackidx
]);
2995 assert((offset
& 0xF000) == 0x0000);
2996 assert((id
& 0xF0) == 0x00);
2998 *stackptr
|= ((u32
)id
) << 12;
2999 *stackptr
|= ((u32
)value
) << 16;
3001 assert(*stackidx
< BCM43xx_INTERFSTACK_SIZE
);
3004 static u16
_stack_restore(u32
*stackptr
,
3009 assert((offset
& 0xF000) == 0x0000);
3010 assert((id
& 0xF0) == 0x00);
3011 for (i
= 0; i
< BCM43xx_INTERFSTACK_SIZE
; i
++, stackptr
++) {
3012 if ((*stackptr
& 0x00000FFF) != offset
)
3014 if (((*stackptr
& 0x0000F000) >> 12) != id
)
3016 return ((*stackptr
& 0xFFFF0000) >> 16);
3023 #define phy_stacksave(offset) \
3025 _stack_save(stack, &stackidx, 0x1, (offset), \
3026 bcm43xx_phy_read(dev, (offset))); \
3028 #define phy_stackrestore(offset) \
3030 bcm43xx_phy_write(dev, (offset), \
3031 _stack_restore(stack, 0x1, \
3034 #define radio_stacksave(offset) \
3036 _stack_save(stack, &stackidx, 0x2, (offset), \
3037 bcm43xx_radio_read16(dev, (offset))); \
3039 #define radio_stackrestore(offset) \
3041 bcm43xx_radio_write16(dev, (offset), \
3042 _stack_restore(stack, 0x2, \
3045 #define ofdmtab_stacksave(table, offset) \
3047 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
3048 bcm43xx_ofdmtab_read16(dev, (table), (offset))); \
3050 #define ofdmtab_stackrestore(table, offset) \
3052 bcm43xx_ofdmtab_write16(dev, (table), (offset), \
3053 _stack_restore(stack, 0x3, \
3054 (offset)|(table))); \
3058 bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_wldev
*dev
,
3061 struct bcm43xx_phy
*phy
= &dev
->phy
;
3063 size_t stackidx
= 0;
3064 u32
*stack
= phy
->interfstack
;
3067 case BCM43xx_INTERFMODE_NONWLAN
:
3068 if (phy
->rev
!= 1) {
3069 bcm43xx_phy_write(dev
, 0x042B,
3070 bcm43xx_phy_read(dev
, 0x042B) | 0x0800);
3071 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
3072 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) & ~0x4000);
3075 radio_stacksave(0x0078);
3076 tmp
= (bcm43xx_radio_read16(dev
, 0x0078) & 0x001E);
3077 flipped
= flip_4bit(tmp
);
3078 if (flipped
< 10 && flipped
>= 8)
3080 else if (flipped
>= 10)
3082 flipped
= flip_4bit(flipped
);
3083 flipped
= (flipped
<< 1) | 0x0020;
3084 bcm43xx_radio_write16(dev
, 0x0078, flipped
);
3086 bcm43xx_calc_nrssi_threshold(dev
);
3088 phy_stacksave(0x0406);
3089 bcm43xx_phy_write(dev
, 0x0406, 0x7E28);
3091 bcm43xx_phy_write(dev
, 0x042B,
3092 bcm43xx_phy_read(dev
, 0x042B) | 0x0800);
3093 bcm43xx_phy_write(dev
, BCM43xx_PHY_RADIO_BITFIELD
,
3094 bcm43xx_phy_read(dev
, BCM43xx_PHY_RADIO_BITFIELD
) | 0x1000);
3096 phy_stacksave(0x04A0);
3097 bcm43xx_phy_write(dev
, 0x04A0,
3098 (bcm43xx_phy_read(dev
, 0x04A0) & 0xC0C0) | 0x0008);
3099 phy_stacksave(0x04A1);
3100 bcm43xx_phy_write(dev
, 0x04A1,
3101 (bcm43xx_phy_read(dev
, 0x04A1) & 0xC0C0) | 0x0605);
3102 phy_stacksave(0x04A2);
3103 bcm43xx_phy_write(dev
, 0x04A2,
3104 (bcm43xx_phy_read(dev
, 0x04A2) & 0xC0C0) | 0x0204);
3105 phy_stacksave(0x04A8);
3106 bcm43xx_phy_write(dev
, 0x04A8,
3107 (bcm43xx_phy_read(dev
, 0x04A8) & 0xC0C0) | 0x0803);
3108 phy_stacksave(0x04AB);
3109 bcm43xx_phy_write(dev
, 0x04AB,
3110 (bcm43xx_phy_read(dev
, 0x04AB) & 0xC0C0) | 0x0605);
3112 phy_stacksave(0x04A7);
3113 bcm43xx_phy_write(dev
, 0x04A7, 0x0002);
3114 phy_stacksave(0x04A3);
3115 bcm43xx_phy_write(dev
, 0x04A3, 0x287A);
3116 phy_stacksave(0x04A9);
3117 bcm43xx_phy_write(dev
, 0x04A9, 0x2027);
3118 phy_stacksave(0x0493);
3119 bcm43xx_phy_write(dev
, 0x0493, 0x32F5);
3120 phy_stacksave(0x04AA);
3121 bcm43xx_phy_write(dev
, 0x04AA, 0x2027);
3122 phy_stacksave(0x04AC);
3123 bcm43xx_phy_write(dev
, 0x04AC, 0x32F5);
3125 case BCM43xx_INTERFMODE_MANUALWLAN
:
3126 if (bcm43xx_phy_read(dev
, 0x0033) & 0x0800)
3129 phy
->aci_enable
= 1;
3131 phy_stacksave(BCM43xx_PHY_RADIO_BITFIELD
);
3132 phy_stacksave(BCM43xx_PHY_G_CRS
);
3134 phy_stacksave(0x0406);
3136 phy_stacksave(0x04C0);
3137 phy_stacksave(0x04C1);
3139 phy_stacksave(0x0033);
3140 phy_stacksave(0x04A7);
3141 phy_stacksave(0x04A3);
3142 phy_stacksave(0x04A9);
3143 phy_stacksave(0x04AA);
3144 phy_stacksave(0x04AC);
3145 phy_stacksave(0x0493);
3146 phy_stacksave(0x04A1);
3147 phy_stacksave(0x04A0);
3148 phy_stacksave(0x04A2);
3149 phy_stacksave(0x048A);
3150 phy_stacksave(0x04A8);
3151 phy_stacksave(0x04AB);
3152 if (phy
->rev
== 2) {
3153 phy_stacksave(0x04AD);
3154 phy_stacksave(0x04AE);
3155 } else if (phy
->rev
>= 3) {
3156 phy_stacksave(0x04AD);
3157 phy_stacksave(0x0415);
3158 phy_stacksave(0x0416);
3159 phy_stacksave(0x0417);
3160 ofdmtab_stacksave(0x1A00, 0x2);
3161 ofdmtab_stacksave(0x1A00, 0x3);
3163 phy_stacksave(0x042B);
3164 phy_stacksave(0x048C);
3166 bcm43xx_phy_write(dev
, BCM43xx_PHY_RADIO_BITFIELD
,
3167 bcm43xx_phy_read(dev
, BCM43xx_PHY_RADIO_BITFIELD
)
3169 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
3170 (bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
)
3171 & 0xFFFC) | 0x0002);
3173 bcm43xx_phy_write(dev
, 0x0033, 0x0800);
3174 bcm43xx_phy_write(dev
, 0x04A3, 0x2027);
3175 bcm43xx_phy_write(dev
, 0x04A9, 0x1CA8);
3176 bcm43xx_phy_write(dev
, 0x0493, 0x287A);
3177 bcm43xx_phy_write(dev
, 0x04AA, 0x1CA8);
3178 bcm43xx_phy_write(dev
, 0x04AC, 0x287A);
3180 bcm43xx_phy_write(dev
, 0x04A0,
3181 (bcm43xx_phy_read(dev
, 0x04A0)
3182 & 0xFFC0) | 0x001A);
3183 bcm43xx_phy_write(dev
, 0x04A7, 0x000D);
3186 bcm43xx_phy_write(dev
, 0x0406, 0xFF0D);
3187 } else if (phy
->rev
== 2) {
3188 bcm43xx_phy_write(dev
, 0x04C0, 0xFFFF);
3189 bcm43xx_phy_write(dev
, 0x04C1, 0x00A9);
3191 bcm43xx_phy_write(dev
, 0x04C0, 0x00C1);
3192 bcm43xx_phy_write(dev
, 0x04C1, 0x0059);
3195 bcm43xx_phy_write(dev
, 0x04A1,
3196 (bcm43xx_phy_read(dev
, 0x04A1)
3197 & 0xC0FF) | 0x1800);
3198 bcm43xx_phy_write(dev
, 0x04A1,
3199 (bcm43xx_phy_read(dev
, 0x04A1)
3200 & 0xFFC0) | 0x0015);
3201 bcm43xx_phy_write(dev
, 0x04A8,
3202 (bcm43xx_phy_read(dev
, 0x04A8)
3203 & 0xCFFF) | 0x1000);
3204 bcm43xx_phy_write(dev
, 0x04A8,
3205 (bcm43xx_phy_read(dev
, 0x04A8)
3206 & 0xF0FF) | 0x0A00);
3207 bcm43xx_phy_write(dev
, 0x04AB,
3208 (bcm43xx_phy_read(dev
, 0x04AB)
3209 & 0xCFFF) | 0x1000);
3210 bcm43xx_phy_write(dev
, 0x04AB,
3211 (bcm43xx_phy_read(dev
, 0x04AB)
3212 & 0xF0FF) | 0x0800);
3213 bcm43xx_phy_write(dev
, 0x04AB,
3214 (bcm43xx_phy_read(dev
, 0x04AB)
3215 & 0xFFCF) | 0x0010);
3216 bcm43xx_phy_write(dev
, 0x04AB,
3217 (bcm43xx_phy_read(dev
, 0x04AB)
3218 & 0xFFF0) | 0x0005);
3219 bcm43xx_phy_write(dev
, 0x04A8,
3220 (bcm43xx_phy_read(dev
, 0x04A8)
3221 & 0xFFCF) | 0x0010);
3222 bcm43xx_phy_write(dev
, 0x04A8,
3223 (bcm43xx_phy_read(dev
, 0x04A8)
3224 & 0xFFF0) | 0x0006);
3225 bcm43xx_phy_write(dev
, 0x04A2,
3226 (bcm43xx_phy_read(dev
, 0x04A2)
3227 & 0xF0FF) | 0x0800);
3228 bcm43xx_phy_write(dev
, 0x04A0,
3229 (bcm43xx_phy_read(dev
, 0x04A0)
3230 & 0xF0FF) | 0x0500);
3231 bcm43xx_phy_write(dev
, 0x04A2,
3232 (bcm43xx_phy_read(dev
, 0x04A2)
3233 & 0xFFF0) | 0x000B);
3235 if (phy
->rev
>= 3) {
3236 bcm43xx_phy_write(dev
, 0x048A,
3237 bcm43xx_phy_read(dev
, 0x048A)
3239 bcm43xx_phy_write(dev
, 0x0415,
3240 (bcm43xx_phy_read(dev
, 0x0415)
3241 & 0x8000) | 0x36D8);
3242 bcm43xx_phy_write(dev
, 0x0416,
3243 (bcm43xx_phy_read(dev
, 0x0416)
3244 & 0x8000) | 0x36D8);
3245 bcm43xx_phy_write(dev
, 0x0417,
3246 (bcm43xx_phy_read(dev
, 0x0417)
3247 & 0xFE00) | 0x016D);
3249 bcm43xx_phy_write(dev
, 0x048A,
3250 bcm43xx_phy_read(dev
, 0x048A)
3252 bcm43xx_phy_write(dev
, 0x048A,
3253 (bcm43xx_phy_read(dev
, 0x048A)
3254 & 0x9FFF) | 0x2000);
3255 bcm43xx_hf_write(dev
, bcm43xx_hf_read(dev
) | BCM43xx_HF_ACIW
);
3257 if (phy
->rev
>= 2) {
3258 bcm43xx_phy_write(dev
, 0x042B,
3259 bcm43xx_phy_read(dev
, 0x042B)
3262 bcm43xx_phy_write(dev
, 0x048C,
3263 (bcm43xx_phy_read(dev
, 0x048C)
3264 & 0xF0FF) | 0x0200);
3265 if (phy
->rev
== 2) {
3266 bcm43xx_phy_write(dev
, 0x04AE,
3267 (bcm43xx_phy_read(dev
, 0x04AE)
3268 & 0xFF00) | 0x007F);
3269 bcm43xx_phy_write(dev
, 0x04AD,
3270 (bcm43xx_phy_read(dev
, 0x04AD)
3271 & 0x00FF) | 0x1300);
3272 } else if (phy
->rev
>= 6) {
3273 bcm43xx_ofdmtab_write16(dev
, 0x1A00, 0x3, 0x007F);
3274 bcm43xx_ofdmtab_write16(dev
, 0x1A00, 0x2, 0x007F);
3275 bcm43xx_phy_write(dev
, 0x04AD,
3276 bcm43xx_phy_read(dev
, 0x04AD)
3279 bcm43xx_calc_nrssi_slope(dev
);
3287 bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_wldev
*dev
,
3290 struct bcm43xx_phy
*phy
= &dev
->phy
;
3291 u32
*stack
= phy
->interfstack
;
3294 case BCM43xx_INTERFMODE_NONWLAN
:
3295 if (phy
->rev
!= 1) {
3296 bcm43xx_phy_write(dev
, 0x042B,
3297 bcm43xx_phy_read(dev
, 0x042B) & ~0x0800);
3298 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
3299 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) | 0x4000);
3302 radio_stackrestore(0x0078);
3303 bcm43xx_calc_nrssi_threshold(dev
);
3304 phy_stackrestore(0x0406);
3305 bcm43xx_phy_write(dev
, 0x042B,
3306 bcm43xx_phy_read(dev
, 0x042B) & ~0x0800);
3307 if (!dev
->bad_frames_preempt
) {
3308 bcm43xx_phy_write(dev
, BCM43xx_PHY_RADIO_BITFIELD
,
3309 bcm43xx_phy_read(dev
, BCM43xx_PHY_RADIO_BITFIELD
)
3312 bcm43xx_phy_write(dev
, BCM43xx_PHY_G_CRS
,
3313 bcm43xx_phy_read(dev
, BCM43xx_PHY_G_CRS
) | 0x4000);
3314 phy_stackrestore(0x04A0);
3315 phy_stackrestore(0x04A1);
3316 phy_stackrestore(0x04A2);
3317 phy_stackrestore(0x04A8);
3318 phy_stackrestore(0x04AB);
3319 phy_stackrestore(0x04A7);
3320 phy_stackrestore(0x04A3);
3321 phy_stackrestore(0x04A9);
3322 phy_stackrestore(0x0493);
3323 phy_stackrestore(0x04AA);
3324 phy_stackrestore(0x04AC);
3326 case BCM43xx_INTERFMODE_MANUALWLAN
:
3327 if (!(bcm43xx_phy_read(dev
, 0x0033) & 0x0800))
3330 phy
->aci_enable
= 0;
3332 phy_stackrestore(BCM43xx_PHY_RADIO_BITFIELD
);
3333 phy_stackrestore(BCM43xx_PHY_G_CRS
);
3334 phy_stackrestore(0x0033);
3335 phy_stackrestore(0x04A3);
3336 phy_stackrestore(0x04A9);
3337 phy_stackrestore(0x0493);
3338 phy_stackrestore(0x04AA);
3339 phy_stackrestore(0x04AC);
3340 phy_stackrestore(0x04A0);
3341 phy_stackrestore(0x04A7);
3342 if (phy
->rev
>= 2) {
3343 phy_stackrestore(0x04C0);
3344 phy_stackrestore(0x04C1);
3346 phy_stackrestore(0x0406);
3347 phy_stackrestore(0x04A1);
3348 phy_stackrestore(0x04AB);
3349 phy_stackrestore(0x04A8);
3350 if (phy
->rev
== 2) {
3351 phy_stackrestore(0x04AD);
3352 phy_stackrestore(0x04AE);
3353 } else if (phy
->rev
>= 3) {
3354 phy_stackrestore(0x04AD);
3355 phy_stackrestore(0x0415);
3356 phy_stackrestore(0x0416);
3357 phy_stackrestore(0x0417);
3358 ofdmtab_stackrestore(0x1A00, 0x2);
3359 ofdmtab_stackrestore(0x1A00, 0x3);
3361 phy_stackrestore(0x04A2);
3362 phy_stackrestore(0x048A);
3363 phy_stackrestore(0x042B);
3364 phy_stackrestore(0x048C);
3365 bcm43xx_hf_write(dev
, bcm43xx_hf_read(dev
) & ~BCM43xx_HF_ACIW
);
3366 bcm43xx_calc_nrssi_slope(dev
);
3373 #undef phy_stacksave
3374 #undef phy_stackrestore
3375 #undef radio_stacksave
3376 #undef radio_stackrestore
3377 #undef ofdmtab_stacksave
3378 #undef ofdmtab_stackrestore
3380 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_wldev
*dev
,
3383 struct bcm43xx_phy
*phy
= &dev
->phy
;
3386 if ((phy
->type
!= BCM43xx_PHYTYPE_G
) ||
3391 phy
->aci_wlan_automatic
= 0;
3393 case BCM43xx_INTERFMODE_AUTOWLAN
:
3394 phy
->aci_wlan_automatic
= 1;
3395 if (phy
->aci_enable
)
3396 mode
= BCM43xx_INTERFMODE_MANUALWLAN
;
3398 mode
= BCM43xx_INTERFMODE_NONE
;
3400 case BCM43xx_INTERFMODE_NONE
:
3401 case BCM43xx_INTERFMODE_NONWLAN
:
3402 case BCM43xx_INTERFMODE_MANUALWLAN
:
3408 currentmode
= phy
->interfmode
;
3409 if (currentmode
== mode
)
3411 if (currentmode
!= BCM43xx_INTERFMODE_NONE
)
3412 bcm43xx_radio_interference_mitigation_disable(dev
, currentmode
);
3414 if (mode
== BCM43xx_INTERFMODE_NONE
) {
3415 phy
->aci_enable
= 0;
3416 phy
->aci_hw_rssi
= 0;
3418 bcm43xx_radio_interference_mitigation_enable(dev
, mode
);
3419 phy
->interfmode
= mode
;
3424 static u16
bcm43xx_radio_core_calibration_value(struct bcm43xx_wldev
*dev
)
3426 u16 reg
, index
, ret
;
3428 static const u8 rcc_table
[] = {
3429 0x02, 0x03, 0x01, 0x0F,
3430 0x06, 0x07, 0x05, 0x0F,
3431 0x0A, 0x0B, 0x09, 0x0F,
3432 0x0E, 0x0F, 0x0D, 0x0F,
3435 reg
= bcm43xx_radio_read16(dev
, 0x60);
3436 index
= (reg
& 0x001E) >> 1;
3437 ret
= rcc_table
[index
] << 1;
3438 ret
|= (reg
& 0x0001);
3444 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3445 static u16
radio2050_rfover_val(struct bcm43xx_wldev
*dev
,
3449 struct bcm43xx_phy
*phy
= &dev
->phy
;
3450 struct ssb_sprom
*sprom
= &(dev
->dev
->bus
->sprom
);
3455 if (has_loopback_gain(phy
)) {
3456 int max_lb_gain
= phy
->max_lb_gain
;
3460 if (phy
->radio_rev
== 8)
3461 max_lb_gain
+= 0x3E;
3463 max_lb_gain
+= 0x26;
3464 if (max_lb_gain
>= 0x46) {
3466 max_lb_gain
-= 0x46;
3467 } else if (max_lb_gain
>= 0x3A) {
3469 max_lb_gain
-= 0x3A;
3470 } else if (max_lb_gain
>= 0x2E) {
3472 max_lb_gain
-= 0x2E;
3475 max_lb_gain
-= 0x10;
3478 for (i
= 0; i
< 16; i
++) {
3479 max_lb_gain
-= (i
* 6);
3480 if (max_lb_gain
< 6)
3484 if ((phy
->rev
< 7) ||
3485 !(sprom
->r1
.boardflags_lo
& BCM43xx_BFL_EXTLNA
)) {
3486 if (phy_register
== BCM43xx_PHY_RFOVER
) {
3488 } else if (phy_register
== BCM43xx_PHY_RFOVERVAL
) {
3495 return (0x0092 | extlna
);
3497 return (0x0093 | extlna
);
3503 if (phy_register
== BCM43xx_PHY_RFOVER
) {
3505 } else if (phy_register
== BCM43xx_PHY_RFOVERVAL
) {
3513 return (0x8092 | extlna
);
3515 return (0x2092 | extlna
);
3517 return (0x2093 | extlna
);
3524 if ((phy
->rev
< 7) ||
3525 !(sprom
->r1
.boardflags_lo
& BCM43xx_BFL_EXTLNA
)) {
3526 if (phy_register
== BCM43xx_PHY_RFOVER
) {
3528 } else if (phy_register
== BCM43xx_PHY_RFOVERVAL
) {
3543 if (phy_register
== BCM43xx_PHY_RFOVER
) {
3545 } else if (phy_register
== BCM43xx_PHY_RFOVERVAL
) {
3564 struct init2050_saved_values
{
3565 /* Core registers */
3569 /* Radio registers */
3582 u16 phy_analogoverval
;
3590 u16
bcm43xx_radio_init2050(struct bcm43xx_wldev
*dev
)
3592 struct bcm43xx_phy
*phy
= &dev
->phy
;
3593 struct init2050_saved_values sav
;
3598 u32 tmp1
= 0, tmp2
= 0;
3600 memset(&sav
, 0, sizeof(sav
)); /* get rid of "may be used uninitialized..." */
3602 sav
.radio_43
= bcm43xx_radio_read16(dev
, 0x43);
3603 sav
.radio_51
= bcm43xx_radio_read16(dev
, 0x51);
3604 sav
.radio_52
= bcm43xx_radio_read16(dev
, 0x52);
3605 sav
.phy_pgactl
= bcm43xx_phy_read(dev
, BCM43xx_PHY_PGACTL
);
3606 sav
.phy_base_5A
= bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x5A));
3607 sav
.phy_base_59
= bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x59));
3608 sav
.phy_base_58
= bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x58));
3610 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
3611 sav
.phy_base_30
= bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x30));
3612 sav
.reg_3EC
= bcm43xx_read16(dev
, 0x3EC);
3614 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x30), 0xFF);
3615 bcm43xx_write16(dev
, 0x3EC, 0x3F3F);
3616 } else if (phy
->gmode
|| phy
->rev
>= 2) {
3617 sav
.phy_rfover
= bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVER
);
3618 sav
.phy_rfoverval
= bcm43xx_phy_read(dev
, BCM43xx_PHY_RFOVERVAL
);
3619 sav
.phy_analogover
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
);
3620 sav
.phy_analogoverval
= bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
);
3621 sav
.phy_crs0
= bcm43xx_phy_read(dev
, BCM43xx_PHY_CRS0
);
3622 sav
.phy_classctl
= bcm43xx_phy_read(dev
, BCM43xx_PHY_CLASSCTL
);
3624 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
,
3625 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVER
)
3627 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
,
3628 bcm43xx_phy_read(dev
, BCM43xx_PHY_ANALOGOVERVAL
)
3630 bcm43xx_phy_write(dev
, BCM43xx_PHY_CRS0
,
3631 bcm43xx_phy_read(dev
, BCM43xx_PHY_CRS0
)
3633 bcm43xx_phy_write(dev
, BCM43xx_PHY_CLASSCTL
,
3634 bcm43xx_phy_read(dev
, BCM43xx_PHY_CLASSCTL
)
3636 if (has_loopback_gain(phy
)) {
3637 sav
.phy_lo_mask
= bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_MASK
);
3638 sav
.phy_lo_ctl
= bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_CTL
);
3641 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, 0xC020);
3643 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, 0x8020);
3644 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_CTL
, 0);
3647 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3648 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3650 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
,
3651 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVER
, 0));
3653 bcm43xx_write16(dev
, 0x3E2, bcm43xx_read16(dev
, 0x3E2) | 0x8000);
3655 sav
.phy_syncctl
= bcm43xx_phy_read(dev
, BCM43xx_PHY_SYNCCTL
);
3656 bcm43xx_phy_write(dev
, BCM43xx_PHY_SYNCCTL
,
3657 bcm43xx_phy_read(dev
, BCM43xx_PHY_SYNCCTL
)
3659 sav
.reg_3E6
= bcm43xx_read16(dev
, 0x3E6);
3660 sav
.reg_3F4
= bcm43xx_read16(dev
, 0x3F4);
3662 if (phy
->analog
== 0) {
3663 bcm43xx_write16(dev
, 0x03E6, 0x0122);
3665 if (phy
->analog
>= 2) {
3666 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x03),
3667 (bcm43xx_phy_read(dev
, BCM43xx_PHY_BASE(0x03))
3670 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
,
3671 (bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
) | 0x2000));
3674 rcc
= bcm43xx_radio_core_calibration_value(dev
);
3676 if (phy
->type
== BCM43xx_PHYTYPE_B
)
3677 bcm43xx_radio_write16(dev
, 0x78, 0x26);
3678 if (phy
->gmode
|| phy
->rev
>= 2) {
3679 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3680 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3683 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xBFAF);
3684 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x2B), 0x1403);
3685 if (phy
->gmode
|| phy
->rev
>= 2) {
3686 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3687 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3690 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xBFA0);
3691 bcm43xx_radio_write16(dev
, 0x51,
3692 bcm43xx_radio_read16(dev
, 0x51)
3694 if (phy
->radio_rev
== 8) {
3695 bcm43xx_radio_write16(dev
, 0x43, 0x1F);
3697 bcm43xx_radio_write16(dev
, 0x52, 0);
3698 bcm43xx_radio_write16(dev
, 0x43,
3699 (bcm43xx_radio_read16(dev
, 0x43)
3700 & 0xFFF0) | 0x0009);
3702 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0);
3704 for (i
= 0; i
< 16; i
++) {
3705 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x5A), 0x0480);
3706 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x59), 0xC810);
3707 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0x000D);
3708 if (phy
->gmode
|| phy
->rev
>= 2) {
3709 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3710 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3713 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xAFB0);
3715 if (phy
->gmode
|| phy
->rev
>= 2) {
3716 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3717 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3720 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xEFB0);
3722 if (phy
->gmode
|| phy
->rev
>= 2) {
3723 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3724 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3727 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xFFF0);
3729 tmp1
+= bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_LEAKAGE
);
3730 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0);
3731 if (phy
->gmode
|| phy
->rev
>= 2) {
3732 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3733 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3736 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xAFB0);
3740 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0);
3744 for (i
= 0; i
< 16; i
++) {
3745 radio78
= ((flip_4bit(i
) << 1) | 0x20);
3746 bcm43xx_radio_write16(dev
, 0x78, radio78
);
3748 for (j
= 0; j
< 16; j
++) {
3749 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x5A), 0x0D80);
3750 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x59), 0xC810);
3751 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0x000D);
3752 if (phy
->gmode
|| phy
->rev
>= 2) {
3753 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3754 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3757 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xAFB0);
3759 if (phy
->gmode
|| phy
->rev
>= 2) {
3760 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3761 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3764 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xEFB0);
3766 if (phy
->gmode
|| phy
->rev
>= 2) {
3767 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3768 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3771 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xFFF0);
3773 tmp2
+= bcm43xx_phy_read(dev
, BCM43xx_PHY_LO_LEAKAGE
);
3774 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), 0);
3775 if (phy
->gmode
|| phy
->rev
>= 2) {
3776 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
,
3777 radio2050_rfover_val(dev
, BCM43xx_PHY_RFOVERVAL
,
3780 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, 0xAFB0);
3788 /* Restore the registers */
3789 bcm43xx_phy_write(dev
, BCM43xx_PHY_PGACTL
, sav
.phy_pgactl
);
3790 bcm43xx_radio_write16(dev
, 0x51, sav
.radio_51
);
3791 bcm43xx_radio_write16(dev
, 0x52, sav
.radio_52
);
3792 bcm43xx_radio_write16(dev
, 0x43, sav
.radio_43
);
3793 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x5A), sav
.phy_base_5A
);
3794 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x59), sav
.phy_base_59
);
3795 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x58), sav
.phy_base_58
);
3796 bcm43xx_write16(dev
, 0x3E6, sav
.reg_3E6
);
3797 if (phy
->analog
!= 0)
3798 bcm43xx_write16(dev
, 0x3F4, sav
.reg_3F4
);
3799 bcm43xx_phy_write(dev
, BCM43xx_PHY_SYNCCTL
, sav
.phy_syncctl
);
3800 bcm43xx_synth_pu_workaround(dev
, phy
->channel
);
3801 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
3802 bcm43xx_phy_write(dev
, BCM43xx_PHY_BASE(0x30), sav
.phy_base_30
);
3803 bcm43xx_write16(dev
, 0x3EC, sav
.reg_3EC
);
3804 } else if (phy
->gmode
) {
3805 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY_RADIO
,
3806 bcm43xx_read16(dev
, BCM43xx_MMIO_PHY_RADIO
)
3808 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVER
, sav
.phy_rfover
);
3809 bcm43xx_phy_write(dev
, BCM43xx_PHY_RFOVERVAL
, sav
.phy_rfoverval
);
3810 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVER
, sav
.phy_analogover
);
3811 bcm43xx_phy_write(dev
, BCM43xx_PHY_ANALOGOVERVAL
, sav
.phy_analogoverval
);
3812 bcm43xx_phy_write(dev
, BCM43xx_PHY_CRS0
, sav
.phy_crs0
);
3813 bcm43xx_phy_write(dev
, BCM43xx_PHY_CLASSCTL
, sav
.phy_classctl
);
3814 if (has_loopback_gain(phy
)) {
3815 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_MASK
, sav
.phy_lo_mask
);
3816 bcm43xx_phy_write(dev
, BCM43xx_PHY_LO_CTL
, sav
.phy_lo_ctl
);
3827 void bcm43xx_radio_init2060(struct bcm43xx_wldev
*dev
)
3831 bcm43xx_radio_write16(dev
, 0x0004, 0x00C0);
3832 bcm43xx_radio_write16(dev
, 0x0005, 0x0008);
3833 bcm43xx_radio_write16(dev
, 0x0009, 0x0040);
3834 bcm43xx_radio_write16(dev
, 0x0005, 0x00AA);
3835 bcm43xx_radio_write16(dev
, 0x0032, 0x008F);
3836 bcm43xx_radio_write16(dev
, 0x0006, 0x008F);
3837 bcm43xx_radio_write16(dev
, 0x0034, 0x008F);
3838 bcm43xx_radio_write16(dev
, 0x002C, 0x0007);
3839 bcm43xx_radio_write16(dev
, 0x0082, 0x0080);
3840 bcm43xx_radio_write16(dev
, 0x0080, 0x0000);
3841 bcm43xx_radio_write16(dev
, 0x003F, 0x00DA);
3842 bcm43xx_radio_write16(dev
, 0x0005, bcm43xx_radio_read16(dev
, 0x0005) & ~0x0008);
3843 bcm43xx_radio_write16(dev
, 0x0081, bcm43xx_radio_read16(dev
, 0x0081) & ~0x0010);
3844 bcm43xx_radio_write16(dev
, 0x0081, bcm43xx_radio_read16(dev
, 0x0081) & ~0x0020);
3845 bcm43xx_radio_write16(dev
, 0x0081, bcm43xx_radio_read16(dev
, 0x0081) & ~0x0020);
3848 bcm43xx_radio_write16(dev
, 0x0081, (bcm43xx_radio_read16(dev
, 0x0081) & ~0x0020) | 0x0010);
3851 bcm43xx_radio_write16(dev
, 0x0005, (bcm43xx_radio_read16(dev
, 0x0005) & ~0x0008) | 0x0008);
3852 bcm43xx_radio_write16(dev
, 0x0085, bcm43xx_radio_read16(dev
, 0x0085) & ~0x0010);
3853 bcm43xx_radio_write16(dev
, 0x0005, bcm43xx_radio_read16(dev
, 0x0005) & ~0x0008);
3854 bcm43xx_radio_write16(dev
, 0x0081, bcm43xx_radio_read16(dev
, 0x0081) & ~0x0040);
3855 bcm43xx_radio_write16(dev
, 0x0081, (bcm43xx_radio_read16(dev
, 0x0081) & ~0x0040) | 0x0040);
3856 bcm43xx_radio_write16(dev
, 0x0005, (bcm43xx_radio_read16(dev
, 0x0081) & ~0x0008) | 0x0008);
3857 bcm43xx_phy_write(dev
, 0x0063, 0xDDC6);
3858 bcm43xx_phy_write(dev
, 0x0069, 0x07BE);
3859 bcm43xx_phy_write(dev
, 0x006A, 0x0000);
3861 err
= bcm43xx_radio_selectchannel(dev
, BCM43xx_DEFAULT_CHANNEL_A
, 0);
3867 u16
freq_r3A_value(u16 frequency
)
3871 if (frequency
< 5091)
3873 else if (frequency
< 5321)
3875 else if (frequency
< 5806)
3883 void bcm43xx_radio_set_tx_iq(struct bcm43xx_wldev
*dev
)
3885 static const u8 data_high
[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
3886 static const u8 data_low
[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
3887 u16 tmp
= bcm43xx_radio_read16(dev
, 0x001E);
3890 for (i
= 0; i
< 5; i
++) {
3891 for (j
= 0; j
< 5; j
++) {
3892 if (tmp
== (data_high
[i
] << 4 | data_low
[j
])) {
3893 bcm43xx_phy_write(dev
, 0x0069, (i
- j
) << 8 | 0x00C0);
3900 int bcm43xx_radio_selectchannel(struct bcm43xx_wldev
*dev
,
3902 int synthetic_pu_workaround
)
3904 struct bcm43xx_phy
*phy
= &dev
->phy
;
3909 /* First we set the channel radio code to prevent the
3910 * firmware from sending ghost packets.
3912 channelcookie
= channel
;
3913 if (phy
->type
== BCM43xx_PHYTYPE_A
)
3914 channelcookie
|= 0x100;
3915 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
3916 BCM43xx_SHM_SH_CHAN
, channelcookie
);
3918 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
3921 freq
= channel2freq_a(channel
);
3923 r8
= bcm43xx_radio_read16(dev
, 0x0008);
3924 bcm43xx_write16(dev
, 0x03F0, freq
);
3925 bcm43xx_radio_write16(dev
, 0x0008, r8
);
3927 TODO();//TODO: write max channel TX power? to Radio 0x2D
3928 tmp
= bcm43xx_radio_read16(dev
, 0x002E);
3930 TODO();//TODO: OR tmp with the Power out estimation for this channel?
3931 bcm43xx_radio_write16(dev
, 0x002E, tmp
);
3933 if (freq
>= 4920 && freq
<= 5500) {
3935 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
3936 * = (freq * 0.025862069
3938 r8
= 3 * freq
/ 116; /* is equal to r8 = freq * 0.025862 */
3940 bcm43xx_radio_write16(dev
, 0x0007, (r8
<< 4) | r8
);
3941 bcm43xx_radio_write16(dev
, 0x0020, (r8
<< 4) | r8
);
3942 bcm43xx_radio_write16(dev
, 0x0021, (r8
<< 4) | r8
);
3943 bcm43xx_radio_write16(dev
, 0x0022,
3944 (bcm43xx_radio_read16(dev
, 0x0022)
3945 & 0x000F) | (r8
<< 4));
3946 bcm43xx_radio_write16(dev
, 0x002A, (r8
<< 4));
3947 bcm43xx_radio_write16(dev
, 0x002B, (r8
<< 4));
3948 bcm43xx_radio_write16(dev
, 0x0008,
3949 (bcm43xx_radio_read16(dev
, 0x0008)
3950 & 0x00F0) | (r8
<< 4));
3951 bcm43xx_radio_write16(dev
, 0x0029,
3952 (bcm43xx_radio_read16(dev
, 0x0029)
3953 & 0xFF0F) | 0x00B0);
3954 bcm43xx_radio_write16(dev
, 0x0035, 0x00AA);
3955 bcm43xx_radio_write16(dev
, 0x0036, 0x0085);
3956 bcm43xx_radio_write16(dev
, 0x003A,
3957 (bcm43xx_radio_read16(dev
, 0x003A)
3958 & 0xFF20) | freq_r3A_value(freq
));
3959 bcm43xx_radio_write16(dev
, 0x003D,
3960 bcm43xx_radio_read16(dev
, 0x003D) & 0x00FF);
3961 bcm43xx_radio_write16(dev
, 0x0081,
3962 (bcm43xx_radio_read16(dev
, 0x0081)
3963 & 0xFF7F) | 0x0080);
3964 bcm43xx_radio_write16(dev
, 0x0035,
3965 bcm43xx_radio_read16(dev
, 0x0035) & 0xFFEF);
3966 bcm43xx_radio_write16(dev
, 0x0035,
3967 (bcm43xx_radio_read16(dev
, 0x0035)
3968 & 0xFFEF) | 0x0010);
3969 bcm43xx_radio_set_tx_iq(dev
);
3970 TODO(); //TODO: TSSI2dbm workaround
3971 bcm43xx_phy_xmitpower(dev
);//FIXME correct?
3973 if ((channel
< 1) || (channel
> 14))
3976 if (synthetic_pu_workaround
)
3977 bcm43xx_synth_pu_workaround(dev
, channel
);
3979 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL
,
3980 channel2freq_bg(channel
));
3982 if (channel
== 14) {
3983 if (dev
->dev
->bus
->sprom
.r1
.country_code
== SSB_SPROM1CCODE_JAPAN
)
3984 bcm43xx_hf_write(dev
, bcm43xx_hf_read(dev
) & ~BCM43xx_HF_ACPR
);
3986 bcm43xx_hf_write(dev
, bcm43xx_hf_read(dev
) | BCM43xx_HF_ACPR
);
3987 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
,
3988 bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
)
3991 bcm43xx_write16(dev
, BCM43xx_MMIO_CHANNEL_EXT
,
3992 bcm43xx_read16(dev
, BCM43xx_MMIO_CHANNEL_EXT
)
3997 phy
->channel
= channel
;
3998 //XXX: Using the longer of 2 timeouts (8000 vs 2000 usecs). Specs states
3999 // that 2000 usecs might suffice.
4005 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
4006 static u16
bcm43xx_get_txgain_base_band(u16 txpower
)
4010 assert(txpower
<= 63);
4014 else if (txpower
>= 49)
4016 else if (txpower
>= 44)
4024 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
4025 static u16
bcm43xx_get_txgain_freq_power_amp(u16 txpower
)
4029 assert(txpower
<= 63);
4033 else if (txpower
>= 25)
4035 else if (txpower
>= 20)
4037 else if (txpower
>= 12)
4045 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
4046 static u16
bcm43xx_get_txgain_dac(u16 txpower
)
4050 assert(txpower
<= 63);
4054 else if (txpower
>= 49)
4056 else if (txpower
>= 44)
4058 else if (txpower
>= 32)
4060 else if (txpower
>= 25)
4062 else if (txpower
>= 20)
4064 else if (txpower
>= 12)
4072 void bcm43xx_radio_set_txpower_a(struct bcm43xx_wldev
*dev
, u16 txpower
)
4074 struct bcm43xx_phy
*phy
= &dev
->phy
;
4075 u16 pamp
, base
, dac
, t
;
4077 txpower
= limit_value(txpower
, 0, 63);
4079 pamp
= bcm43xx_get_txgain_freq_power_amp(txpower
);
4082 bcm43xx_phy_write(dev
, 0x0019, pamp
);
4084 base
= bcm43xx_get_txgain_base_band(txpower
);
4086 bcm43xx_phy_write(dev
, 0x0017, base
| 0x0020);
4088 t
= bcm43xx_ofdmtab_read16(dev
, 0x3000, 1);
4091 dac
= bcm43xx_get_txgain_dac(txpower
);
4095 bcm43xx_ofdmtab_write16(dev
, 0x3000, 1, dac
);
4097 phy
->txpwr_offset
= txpower
;
4100 //TODO: FuncPlaceholder (Adjust BB loft cancel)
4103 void bcm43xx_radio_set_txpower_bg(struct bcm43xx_wldev
*dev
,
4104 s16 baseband_attenuation
,
4105 s16 radio_attenuation
,
4108 struct bcm43xx_phy
*phy
= &dev
->phy
;
4109 u8 tx_bias
= phy
->lo_control
->tx_bias
;
4112 if (baseband_attenuation
< 0)
4113 baseband_attenuation
= phy
->bbatt
;
4114 if (radio_attenuation
< 0)
4115 radio_attenuation
= phy
->rfatt
;
4117 _tx_magn
= phy
->lo_control
->tx_magn
;
4119 phy
->bbatt
= baseband_attenuation
;
4120 phy
->rfatt
= radio_attenuation
;
4122 /* Set Baseband Attenuation on device. */
4123 bcm43xx_phy_set_baseband_attenuation(dev
, baseband_attenuation
);
4125 /* Set Radio Attenuation on device. */
4126 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
4127 0x0064, radio_attenuation
);
4128 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
== 8) {
4129 bcm43xx_phy_write(dev
, 0x0043, radio_attenuation
);
4131 bcm43xx_radio_write16(dev
, 0x0043,
4132 (bcm43xx_radio_read16(dev
, 0x0043)
4133 & 0xFFF0) | radio_attenuation
);
4136 if (phy
->radio_ver
== 0x2050) {//FIXME: It seems like tx_magn and tx_bias are swapped in this func.
4137 if (phy
->radio_rev
< 6) {
4138 bcm43xx_radio_write16(dev
, 0x0043,
4139 (bcm43xx_radio_read16(dev
, 0x0043)
4140 & 0xFF8F) | tx_magn
);
4141 } else if (phy
->radio_rev
!= 8) {
4142 bcm43xx_radio_write16(dev
, 0x0052,
4143 (bcm43xx_radio_read16(dev
, 0x0052)
4144 & 0xFF8F) | tx_magn
);
4146 bcm43xx_radio_write16(dev
, 0x52,
4147 (bcm43xx_radio_read16(dev
, 0x52) & 0xFF00) |
4151 if (phy
->radio_rev
!= 8) {
4152 bcm43xx_radio_write16(dev
, 0x0052,
4153 (bcm43xx_radio_read16(dev
, 0x0052)
4154 & 0xFFF0) | tx_bias
);
4156 if (phy
->type
== BCM43xx_PHYTYPE_G
)
4157 bcm43xx_lo_g_adjust(dev
);
4160 u16
bcm43xx_default_baseband_attenuation(struct bcm43xx_wldev
*dev
)
4162 struct bcm43xx_phy
*phy
= &dev
->phy
;
4164 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
< 6)
4169 u16
bcm43xx_default_radio_attenuation(struct bcm43xx_wldev
*dev
)
4171 struct ssb_bus
*bus
= dev
->dev
->bus
;
4172 struct bcm43xx_phy
*phy
= &dev
->phy
;
4175 if (phy
->type
== BCM43xx_PHYTYPE_A
)
4178 switch (phy
->radio_ver
) {
4180 switch (phy
->radio_rev
) {
4187 switch (phy
->radio_rev
) {
4192 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
4193 if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4194 bus
->board_type
== SSB_BOARD_BCM4309G
&&
4195 bus
->board_rev
>= 30)
4197 else if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4198 bus
->board_type
== SSB_BOARD_BU4306
)
4203 if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4204 bus
->board_type
== SSB_BOARD_BCM4309G
&&
4205 bus
->board_rev
>= 30)
4212 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
4213 if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4214 bus
->board_type
== SSB_BOARD_BCM4309G
&&
4215 bus
->board_rev
>= 30)
4217 else if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4218 bus
->board_type
== SSB_BOARD_BU4306
)
4220 else if (bus
->chip_id
== 0x4320)
4246 if (bus
->board_vendor
== SSB_BOARDVENDOR_BCM
&&
4247 bus
->board_type
== SSB_BOARD_BCM4309G
) {
4248 if (bus
->board_rev
< 0x43)
4250 else if (bus
->board_rev
< 0x51)
4259 u16
bcm43xx_default_txctl1(struct bcm43xx_wldev
*dev
)
4261 struct bcm43xx_phy
*phy
= &dev
->phy
;
4263 if (phy
->radio_ver
!= 0x2050)
4265 if (phy
->radio_rev
== 1)
4267 if (phy
->radio_rev
< 6)
4269 if (phy
->radio_rev
== 8)
4274 void bcm43xx_radio_turn_on(struct bcm43xx_wldev
*dev
)
4276 struct bcm43xx_phy
*phy
= &dev
->phy
;
4282 switch (phy
->type
) {
4283 case BCM43xx_PHYTYPE_A
:
4284 bcm43xx_radio_write16(dev
, 0x0004, 0x00C0);
4285 bcm43xx_radio_write16(dev
, 0x0005, 0x0008);
4286 bcm43xx_phy_write(dev
, 0x0010, bcm43xx_phy_read(dev
, 0x0010) & 0xFFF7);
4287 bcm43xx_phy_write(dev
, 0x0011, bcm43xx_phy_read(dev
, 0x0011) & 0xFFF7);
4288 bcm43xx_radio_init2060(dev
);
4290 case BCM43xx_PHYTYPE_B
:
4291 case BCM43xx_PHYTYPE_G
:
4292 bcm43xx_phy_write(dev
, 0x0015, 0x8000);
4293 bcm43xx_phy_write(dev
, 0x0015, 0xCC00);
4294 bcm43xx_phy_write(dev
, 0x0015, (phy
->gmode
? 0x00C0 : 0x0000));
4295 err
= bcm43xx_radio_selectchannel(dev
, BCM43xx_DEFAULT_CHANNEL_BG
, 1);
4302 dprintk(KERN_INFO PFX
"Radio turned on\n");
4305 void bcm43xx_radio_turn_off(struct bcm43xx_wldev
*dev
)
4307 struct bcm43xx_phy
*phy
= &dev
->phy
;
4309 if (phy
->type
== BCM43xx_PHYTYPE_A
) {
4310 bcm43xx_radio_write16(dev
, 0x0004, 0x00FF);
4311 bcm43xx_radio_write16(dev
, 0x0005, 0x00FB);
4312 bcm43xx_phy_write(dev
, 0x0010, bcm43xx_phy_read(dev
, 0x0010) | 0x0008);
4313 bcm43xx_phy_write(dev
, 0x0011, bcm43xx_phy_read(dev
, 0x0011) | 0x0008);
4315 if (phy
->type
== BCM43xx_PHYTYPE_G
&& dev
->dev
->id
.revision
>= 5) {
4316 bcm43xx_phy_write(dev
, 0x0811, bcm43xx_phy_read(dev
, 0x0811) | 0x008C);
4317 bcm43xx_phy_write(dev
, 0x0812, bcm43xx_phy_read(dev
, 0x0812) & 0xFF73);
4319 bcm43xx_phy_write(dev
, 0x0015, 0xAA00);
4321 dprintk(KERN_INFO PFX
"Radio turned off\n");