add acx-mac80211 (thanks to Matteo Croce)
[openwrt.git] / package / acx-mac80211 / patches / 003-endianness_fixes.patch
1 --- acx-mac80211-20070610/pci.c 2007-06-10 20:23:27.000000000 +0200
2 +++ acx-mac80211-20070610/pci.c 2007-07-23 16:49:06.000000000 +0200
3 @@ -104,6 +104,11 @@
4 ** Register access
5 */
6
7 +#define acx_readl(v) le32_to_cpu(readl((v)))
8 +#define acx_readw(v) le16_to_cpu(readw((v)))
9 +#define acx_writew(v,r) writew(le16_to_cpu((v)), r)
10 +#define acx_writel(v,r) writel(le32_to_cpu((v)), r)
11 +
12 /* Pick one */
13 /* #define INLINE_IO static */
14 #define INLINE_IO static inline
15 @@ -111,16 +116,16 @@
16 INLINE_IO u32 read_reg32(acx_device_t * adev, unsigned int offset)
17 {
18 #if ACX_IO_WIDTH == 32
19 - return readl((u8 *) adev->iobase + adev->io[offset]);
20 + return acx_readl((u8 *) adev->iobase + adev->io[offset]);
21 #else
22 - return readw((u8 *) adev->iobase + adev->io[offset])
23 - + (readw((u8 *) adev->iobase + adev->io[offset] + 2) << 16);
24 + return acx_readw((u8 *) adev->iobase + adev->io[offset])
25 + + (acx_readw((u8 *) adev->iobase + adev->io[offset] + 2) << 16);
26 #endif
27 }
28
29 INLINE_IO u16 read_reg16(acx_device_t * adev, unsigned int offset)
30 {
31 - return readw((u8 *) adev->iobase + adev->io[offset]);
32 + return acx_readw((u8 *) adev->iobase + adev->io[offset]);
33 }
34
35 INLINE_IO u8 read_reg8(acx_device_t * adev, unsigned int offset)
36 @@ -131,16 +136,16 @@
37 INLINE_IO void write_reg32(acx_device_t * adev, unsigned int offset, u32 val)
38 {
39 #if ACX_IO_WIDTH == 32
40 - writel(val, (u8 *) adev->iobase + adev->io[offset]);
41 + acx_writel(val, (u8 *) adev->iobase + adev->io[offset]);
42 #else
43 - writew(val & 0xffff, (u8 *) adev->iobase + adev->io[offset]);
44 - writew(val >> 16, (u8 *) adev->iobase + adev->io[offset] + 2);
45 + acx_writew(val & 0xffff, (u8 *) adev->iobase + adev->io[offset]);
46 + acx_writew(val >> 16, (u8 *) adev->iobase + adev->io[offset] + 2);
47 #endif
48 }
49
50 INLINE_IO void write_reg16(acx_device_t * adev, unsigned int offset, u16 val)
51 {
52 - writew(val, (u8 *) adev->iobase + adev->io[offset]);
53 + acx_writew(val, (u8 *) adev->iobase + adev->io[offset]);
54 }
55
56 INLINE_IO void write_reg8(acx_device_t * adev, unsigned int offset, u8 val)
57 @@ -165,7 +170,7 @@
58 {
59 /* fast version (accesses the first register, IO_ACX_SOFT_RESET,
60 * which should be safe): */
61 - return readl(adev->iobase) != 0xffffffff;
62 + return acx_readl(adev->iobase) != 0xffffffff;
63 }
64
65
66 @@ -821,7 +826,7 @@
67 static inline void
68 acxpci_write_cmd_type_status(acx_device_t * adev, u16 type, u16 status)
69 {
70 - writel(type | (status << 16), adev->cmd_area);
71 + acx_writel(type | (status << 16), adev->cmd_area);
72 write_flush(adev);
73 }
74
75 @@ -833,7 +838,7 @@
76 {
77 u32 cmd_type, cmd_status;
78
79 - cmd_type = readl(adev->cmd_area);
80 + cmd_type = acx_readl(adev->cmd_area);
81 cmd_status = (cmd_type >> 16);
82 cmd_type = (u16) cmd_type;
83
84 @@ -2421,12 +2426,12 @@
85 #endif
86 u32 info_type, info_status;
87
88 - info_type = readl(adev->info_area);
89 + info_type = acx_readl(adev->info_area);
90 info_status = (info_type >> 16);
91 info_type = (u16) info_type;
92
93 /* inform fw that we have read this info message */
94 - writel(info_type | 0x00010000, adev->info_area);
95 + acx_writel(info_type | 0x00010000, adev->info_area);
96 write_reg16(adev, IO_ACX_INT_TRIG, INT_TRIG_INFOACK);
97 write_flush(adev);
98
99 @@ -4304,8 +4309,8 @@
100 #define ENDIANNESS_STRING "running on a BIG-ENDIAN CPU\n"
101 #endif
102 log(L_INIT,
103 - ENDIANNESS_STRING
104 - "PCI module " ACX_RELEASE " initialized, "
105 + "acx: " ENDIANNESS_STRING
106 + "acx: PCI module " ACX_RELEASE " initialized, "
107 "waiting for cards to probe...\n");
108
109 res = pci_register_driver(&acxpci_drv_id);
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