target/linux/linux-2.6/patches/generic/003-net-b44.patch

   1 diff -Nur linux-2.6.12.5/drivers/net/b44.c linux-2.6.12.5-b44/drivers/net/b44.c
   2 --- linux-2.6.12.5/drivers/net/b44.c    2005-08-15 02:20:18.000000000 +0200
   3 +++ linux-2.6.12.5-b44/drivers/net/b44.c        2005-09-16 10:33:56.284312840 +0200
   4 @@ -1,7 +1,8 @@
   5 -/* b44.c: Broadcom 4400 device driver.
   6 +/* b44.c: Broadcom 4400/47xx device driver.
   7   *
   8   * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
  11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  12   *
  13   * Distribute under GPL.
  14   */
  15 @@ -78,7 +79,7 @@
  16         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  17
  18  MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  19 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  20 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
  21  MODULE_LICENSE("GPL");
  22  MODULE_VERSION(DRV_MODULE_VERSION);
  23
  24 @@ -93,6 +94,8 @@
  25           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  26         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  27           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  28 +       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
  29 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  30         { }     /* terminate list with empty entry */
  31  };
  32
  33 @@ -106,24 +109,13 @@
  34  static void b44_poll_controller(struct net_device *dev);
  35  #endif
  36
  37 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
  38 -{
  39 -       return readl(bp->regs + reg);
  40 -}
  41 -
  42 -static inline void bw32(const struct b44 *bp,
  43 -                       unsigned long reg, unsigned long val)
  44 -{
  45 -       writel(val, bp->regs + reg);
  46 -}
  47 -
  48  static int b44_wait_bit(struct b44 *bp, unsigned long reg,
  49                         u32 bit, unsigned long timeout, const int clear)
  50  {
  51         unsigned long i;
  52
  53         for (i = 0; i < timeout; i++) {
  54 -               u32 val = br32(bp, reg);
  55 +               u32 val = br32(reg);
  56
  57                 if (clear && !(val & bit))
  58                         break;
  59 @@ -154,7 +146,7 @@
  60
  61  static u32 ssb_get_core_rev(struct b44 *bp)
  62  {
  63 -       return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
  64 +       return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
  65  }
  66
  67  static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
  68 @@ -165,13 +157,13 @@
  69         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
  70         pci_rev = ssb_get_core_rev(bp);
  71
  72 -       val = br32(bp, B44_SBINTVEC);
  73 +       val = br32(B44_SBINTVEC);
  74         val |= cores;
  75 -       bw32(bp, B44_SBINTVEC, val);
  76 +       bw32(B44_SBINTVEC, val);
  77
  78 -       val = br32(bp, SSB_PCI_TRANS_2);
  79 +       val = br32(SSB_PCI_TRANS_2);
  80         val |= SSB_PCI_PREF | SSB_PCI_BURST;
  81 -       bw32(bp, SSB_PCI_TRANS_2, val);
  82 +       bw32(SSB_PCI_TRANS_2, val);
  83
  84         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
  85
  86 @@ -180,18 +172,18 @@
  87
  88  static void ssb_core_disable(struct b44 *bp)
  89  {
  90 -       if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
  91 +       if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
  92                 return;
  93
  94 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
  95 +       bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
  96         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
  97         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
  98 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
  99 +       bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 100                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 101 -       br32(bp, B44_SBTMSLOW);
 102 +       br32(B44_SBTMSLOW);
 103         udelay(1);
 104 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 105 -       br32(bp, B44_SBTMSLOW);
 106 +       bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 107 +       br32(B44_SBTMSLOW);
 108         udelay(1);
 109  }
 110
 111 @@ -200,58 +192,65 @@
 112         u32 val;
 113
 114         ssb_core_disable(bp);
 115 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 116 -       br32(bp, B44_SBTMSLOW);
 117 +       bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 118 +       br32(B44_SBTMSLOW);
 119         udelay(1);
 120
 121         /* Clear SERR if set, this is a hw bug workaround.  */
 122 -       if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 123 -               bw32(bp, B44_SBTMSHIGH, 0);
 124 +       if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 125 +               bw32(B44_SBTMSHIGH, 0);
 126
 127 -       val = br32(bp, B44_SBIMSTATE);
 128 +       val = br32(B44_SBIMSTATE);
 129         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 130 -               bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 131 +               bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 132
 133 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 134 -       br32(bp, B44_SBTMSLOW);
 135 +       bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 136 +       br32(B44_SBTMSLOW);
 137         udelay(1);
 138
 139 -       bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 140 -       br32(bp, B44_SBTMSLOW);
 141 +       bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 142 +       br32(B44_SBTMSLOW);
 143         udelay(1);
 144  }
 145
 146 +static int b44_4713_instance;
 147 +
 148  static int ssb_core_unit(struct b44 *bp)
 149  {
 150 -#if 0
 151 -       u32 val = br32(bp, B44_SBADMATCH0);
 152 -       u32 base;
 153 -
 154 -       type = val & SBADMATCH0_TYPE_MASK;
 155 -       switch (type) {
 156 -       case 0:
 157 -               base = val & SBADMATCH0_BS0_MASK;
 158 -               break;
 159 -
 160 -       case 1:
 161 -               base = val & SBADMATCH0_BS1_MASK;
 162 -               break;
 163 -
 164 -       case 2:
 165 -       default:
 166 -               base = val & SBADMATCH0_BS2_MASK;
 167 -               break;
 168 -       };
 169 -#endif
 170 -       return 0;
 171 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 172 +               return b44_4713_instance++;
 173 +       else
 174 +               return 0;
 175  }
 176
 177  static int ssb_is_core_up(struct b44 *bp)
 178  {
 179 -       return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 180 +       return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 181                 == SBTMSLOW_CLOCK);
 182  }
 183
 184 +static void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 185 +{
 186 +       u32 val;
 187 +
 188 +       bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
 189 +                           (index << CAM_CTRL_INDEX_SHIFT)));
 190 +
 191 +       b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 192 +
 193 +       val = br32(B44_CAM_DATA_LO);
 194 +
 195 +       data[2] = (val >> 24) & 0xFF;
 196 +       data[3] = (val >> 16) & 0xFF;
 197 +       data[4] = (val >> 8) & 0xFF;
 198 +       data[5] = (val >> 0) & 0xFF;
 199 +
 200 +       val = br32(B44_CAM_DATA_HI);
 201 +
 202 +       data[0] = (val >> 8) & 0xFF;
 203 +       data[1] = (val >> 0) & 0xFF;
 204 +}
 205 +
 206  static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 207  {
 208         u32 val;
 209 @@ -260,19 +259,19 @@
 210         val |= ((u32) data[3]) << 16;
 211         val |= ((u32) data[4]) <<  8;
 212         val |= ((u32) data[5]) <<  0;
 213 -       bw32(bp, B44_CAM_DATA_LO, val);
 214 +       bw32(B44_CAM_DATA_LO, val);
 215         val = (CAM_DATA_HI_VALID |
 216                (((u32) data[0]) << 8) |
 217                (((u32) data[1]) << 0));
 218 -       bw32(bp, B44_CAM_DATA_HI, val);
 219 -       bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 220 +       bw32(B44_CAM_DATA_HI, val);
 221 +       bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
 222                             (index << CAM_CTRL_INDEX_SHIFT)));
 223         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 224  }
 225
 226  static inline void __b44_disable_ints(struct b44 *bp)
 227  {
 228 -       bw32(bp, B44_IMASK, 0);
 229 +       bw32(B44_IMASK, 0);
 230  }
 231
 232  static void b44_disable_ints(struct b44 *bp)
 233 @@ -280,34 +279,40 @@
 234         __b44_disable_ints(bp);
 235
 236         /* Flush posted writes. */
 237 -       br32(bp, B44_IMASK);
 238 +       br32(B44_IMASK);
 239  }
 240
 241  static void b44_enable_ints(struct b44 *bp)
 242  {
 243 -       bw32(bp, B44_IMASK, bp->imask);
 244 +       bw32(B44_IMASK, bp->imask);
 245  }
 246
 247  static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 248  {
 249         int err;
 250
 251 -       bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 252 -       bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 253 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 254 +               return 0;
 255 +
 256 +       bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 257 +       bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 258                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 259                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 260                              (reg << MDIO_DATA_RA_SHIFT) |
 261                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 262         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 263 -       *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 264 +       *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
 265
 266         return err;
 267  }
 268
 269  static int b44_writephy(struct b44 *bp, int reg, u32 val)
 270  {
 271 -       bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 272 -       bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 273 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 274 +               return 0;
 275 +
 276 +       bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 277 +       bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 278                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 279                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 280                              (reg << MDIO_DATA_RA_SHIFT) |
 281 @@ -344,6 +349,9 @@
 282         u32 val;
 283         int err;
 284
 285 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 286 +               return 0;
 287 +
 288         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 289         if (err)
 290                 return err;
 291 @@ -367,20 +375,20 @@
 292         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 293         bp->flags |= pause_flags;
 294
 295 -       val = br32(bp, B44_RXCONFIG);
 296 +       val = br32(B44_RXCONFIG);
 297         if (pause_flags & B44_FLAG_RX_PAUSE)
 298                 val |= RXCONFIG_FLOW;
 299         else
 300                 val &= ~RXCONFIG_FLOW;
 301 -       bw32(bp, B44_RXCONFIG, val);
 302 +       bw32(B44_RXCONFIG, val);
 303
 304 -       val = br32(bp, B44_MAC_FLOW);
 305 +       val = br32(B44_MAC_FLOW);
 306         if (pause_flags & B44_FLAG_TX_PAUSE)
 307                 val |= (MAC_FLOW_PAUSE_ENAB |
 308                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 309         else
 310                 val &= ~MAC_FLOW_PAUSE_ENAB;
 311 -       bw32(bp, B44_MAC_FLOW, val);
 312 +       bw32(B44_MAC_FLOW, val);
 313  }
 314
 315  static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 316 @@ -414,6 +422,9 @@
 317         u32 val;
 318         int err;
 319
 320 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 321 +               return 0;
 322 +
 323         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 324                 goto out;
 325         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 326 @@ -476,11 +487,11 @@
 327
 328         val = &bp->hw_stats.tx_good_octets;
 329         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 330 -               *val++ += br32(bp, reg);
 331 +               *val++ += br32(reg);
 332         }
 333         val = &bp->hw_stats.rx_good_octets;
 334         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 335 -               *val++ += br32(bp, reg);
 336 +               *val++ += br32(reg);
 337         }
 338  }
 339
 340 @@ -506,6 +517,19 @@
 341  {
 342         u32 bmsr, aux;
 343
 344 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 345 +               bp->flags |= B44_FLAG_100_BASE_T;
 346 +               bp->flags |= B44_FLAG_FULL_DUPLEX;
 347 +               if (!netif_carrier_ok(bp->dev)) {
 348 +                       u32 val = br32(B44_TX_CTRL);
 349 +                       val |= TX_CTRL_DUPLEX;
 350 +                       bw32(B44_TX_CTRL, val);
 351 +                       netif_carrier_on(bp->dev);
 352 +                       b44_link_report(bp);
 353 +               }
 354 +               return;
 355 +       }
 356 +
 357         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 358             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 359             (bmsr != 0xffff)) {
 360 @@ -520,14 +544,14 @@
 361
 362                 if (!netif_carrier_ok(bp->dev) &&
 363                     (bmsr & BMSR_LSTATUS)) {
 364 -                       u32 val = br32(bp, B44_TX_CTRL);
 365 +                       u32 val = br32(B44_TX_CTRL);
 366                         u32 local_adv, remote_adv;
 367
 368                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 369                                 val |= TX_CTRL_DUPLEX;
 370                         else
 371                                 val &= ~TX_CTRL_DUPLEX;
 372 -                       bw32(bp, B44_TX_CTRL, val);
 373 +                       bw32(B44_TX_CTRL, val);
 374
 375                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 376                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 377 @@ -572,7 +596,7 @@
 378  {
 379         u32 cur, cons;
 380
 381 -       cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 382 +       cur  = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 383         cur /= sizeof(struct dma_desc);
 384
 385         /* XXX needs updating when NETIF_F_SG is supported */
 386 @@ -596,7 +620,7 @@
 387             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 388                 netif_wake_queue(bp->dev);
 389
 390 -       bw32(bp, B44_GPTIMER, 0);
 391 +       bw32(B44_GPTIMER, 0);
 392  }
 393
 394  /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 395 @@ -713,7 +737,7 @@
 396         u32 cons, prod;
 397
 398         received = 0;
 399 -       prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 400 +       prod  = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 401         prod /= sizeof(struct dma_desc);
 402         cons = bp->rx_cons;
 403
 404 @@ -792,7 +816,7 @@
 405         }
 406
 407         bp->rx_cons = cons;
 408 -       bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 409 +       bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 410
 411         return received;
 412  }
 413 @@ -856,8 +880,8 @@
 414
 415         spin_lock_irqsave(&bp->lock, flags);
 416
 417 -       istat = br32(bp, B44_ISTAT);
 418 -       imask = br32(bp, B44_IMASK);
 419 +       istat = br32(B44_ISTAT);
 420 +       imask = br32(B44_IMASK);
 421
 422         /* ??? What the fuck is the purpose of the interrupt mask
 423          * ??? register if we have to mask it out by hand anyways?
 424 @@ -877,8 +901,8 @@
 425                                dev->name);
 426                 }
 427
 428 -               bw32(bp, B44_ISTAT, istat);
 429 -               br32(bp, B44_ISTAT);
 430 +               bw32(B44_ISTAT, istat);
 431 +               br32(B44_ISTAT);
 432         }
 433         spin_unlock_irqrestore(&bp->lock, flags);
 434         return IRQ_RETVAL(handled);
 435 @@ -965,11 +989,11 @@
 436
 437         wmb();
 438
 439 -       bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 440 +       bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 441         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
 442 -               bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 443 +               bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 444         if (bp->flags & B44_FLAG_REORDER_BUG)
 445 -               br32(bp, B44_DMATX_PTR);
 446 +               br32(B44_DMATX_PTR);
 447
 448         if (TX_BUFFS_AVAIL(bp) < 1)
 449                 netif_stop_queue(dev);
 450 @@ -1137,32 +1161,35 @@
 451  {
 452         unsigned long reg;
 453
 454 -       bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 455 +       bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 456         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
 457 -               br32(bp, reg);
 458 +               br32(reg);
 459         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
 460 -               br32(bp, reg);
 461 +               br32(reg);
 462  }
 463
 464  /* bp->lock is held. */
 465  static void b44_chip_reset(struct b44 *bp)
 466  {
 467 +       unsigned int sb_clock;
 468 +
 469         if (ssb_is_core_up(bp)) {
 470 -               bw32(bp, B44_RCV_LAZY, 0);
 471 -               bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
 472 +               bw32(B44_RCV_LAZY, 0);
 473 +               bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
 474                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
 475 -               bw32(bp, B44_DMATX_CTRL, 0);
 476 +               bw32(B44_DMATX_CTRL, 0);
 477                 bp->tx_prod = bp->tx_cons = 0;
 478 -               if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
 479 +               if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
 480                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
 481                                      100, 0);
 482                 }
 483 -               bw32(bp, B44_DMARX_CTRL, 0);
 484 +               bw32(B44_DMARX_CTRL, 0);
 485                 bp->rx_prod = bp->rx_cons = 0;
 486         } else {
 487 -               ssb_pci_setup(bp, (bp->core_unit == 0 ?
 488 -                                  SBINTVEC_ENET0 :
 489 -                                  SBINTVEC_ENET1));
 490 +               if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
 491 +                       ssb_pci_setup(bp, (bp->core_unit == 0 ?
 492 +                                          SBINTVEC_ENET0 :
 493 +                                          SBINTVEC_ENET1));
 494         }
 495
 496         ssb_core_reset(bp);
 497 @@ -1170,20 +1197,26 @@
 498         b44_clear_stats(bp);
 499
 500         /* Make PHY accessible. */
 501 -       bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 502 -                            (0x0d & MDIO_CTRL_MAXF_MASK)));
 503 -       br32(bp, B44_MDIO_CTRL);
 504 -
 505 -       if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
 506 -               bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
 507 -               br32(bp, B44_ENET_CTRL);
 508 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 509 +               sb_clock = 100000000; /* 100 MHz */
 510 +       else
 511 +               sb_clock = 62500000; /* 62.5 MHz */
 512 +
 513 +       bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 514 +                            (((sb_clock + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
 515 +                            & MDIO_CTRL_MAXF_MASK)));
 516 +       br32(B44_MDIO_CTRL);
 517 +
 518 +       if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
 519 +               bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
 520 +               br32(B44_ENET_CTRL);
 521                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
 522         } else {
 523 -               u32 val = br32(bp, B44_DEVCTRL);
 524 +               u32 val = br32(B44_DEVCTRL);
 525
 526                 if (val & DEVCTRL_EPR) {
 527 -                       bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
 528 -                       br32(bp, B44_DEVCTRL);
 529 +                       bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
 530 +                       br32(B44_DEVCTRL);
 531                         udelay(100);
 532                 }
 533                 bp->flags |= B44_FLAG_INTERNAL_PHY;
 534 @@ -1200,13 +1233,13 @@
 535  /* bp->lock is held. */
 536  static void __b44_set_mac_addr(struct b44 *bp)
 537  {
 538 -       bw32(bp, B44_CAM_CTRL, 0);
 539 +       bw32(B44_CAM_CTRL, 0);
 540         if (!(bp->dev->flags & IFF_PROMISC)) {
 541                 u32 val;
 542
 543                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
 544 -               val = br32(bp, B44_CAM_CTRL);
 545 -               bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 546 +               val = br32(B44_CAM_CTRL);
 547 +               bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 548         }
 549  }
 550
 551 @@ -1240,30 +1273,30 @@
 552         b44_setup_phy(bp);
 553
 554         /* Enable CRC32, set proper LED modes and power on PHY */
 555 -       bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
 556 -       bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
 557 +       bw32(B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
 558 +       bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
 559
 560         /* This sets the MAC address too.  */
 561         __b44_set_rx_mode(bp->dev);
 562
 563         /* MTU + eth header + possible VLAN tag + struct rx_header */
 564 -       bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 565 -       bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 566 +       bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 567 +       bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
 568
 569 -       bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
 570 -       bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
 571 -       bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
 572 -       bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
 573 +       bw32(B44_TX_WMARK, 56); /* XXX magic */
 574 +       bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
 575 +       bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
 576 +       bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
 577                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
 578 -       bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
 579 +       bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
 580
 581 -       bw32(bp, B44_DMARX_PTR, bp->rx_pending);
 582 +       bw32(B44_DMARX_PTR, bp->rx_pending);
 583         bp->rx_prod = bp->rx_pending;
 584
 585 -       bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 586 +       bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
 587
 588 -       val = br32(bp, B44_ENET_CTRL);
 589 -       bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
 590 +       val = br32(B44_ENET_CTRL);
 591 +       bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
 592  }
 593
 594  static int b44_open(struct net_device *dev)
 595 @@ -1416,11 +1449,11 @@
 596         int i=0;
 597         unsigned char zero[6] = {0,0,0,0,0,0};
 598
 599 -       val = br32(bp, B44_RXCONFIG);
 600 +       val = br32(B44_RXCONFIG);
 601         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
 602         if (dev->flags & IFF_PROMISC) {
 603                 val |= RXCONFIG_PROMISC;
 604 -               bw32(bp, B44_RXCONFIG, val);
 605 +               bw32(B44_RXCONFIG, val);
 606         } else {
 607                 __b44_set_mac_addr(bp);
 608
 609 @@ -1432,9 +1465,9 @@
 610                 for(;i<64;i++) {
 611                         __b44_cam_write(bp, zero, i);
 612                 }
 613 -               bw32(bp, B44_RXCONFIG, val);
 614 -               val = br32(bp, B44_CAM_CTRL);
 615 -               bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 616 +               bw32(B44_RXCONFIG, val);
 617 +               val = br32(B44_CAM_CTRL);
 618 +               bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
 619         }
 620  }
 621
 622 @@ -1704,19 +1737,41 @@
 623  {
 624         u8 eeprom[128];
 625         int err;
 626 +       unsigned long flags;
 627
 628 -       err = b44_read_eeprom(bp, &eeprom[0]);
 629 -       if (err)
 630 -               goto out;
 631 -
 632 -       bp->dev->dev_addr[0] = eeprom[79];
 633 -       bp->dev->dev_addr[1] = eeprom[78];
 634 -       bp->dev->dev_addr[2] = eeprom[81];
 635 -       bp->dev->dev_addr[3] = eeprom[80];
 636 -       bp->dev->dev_addr[4] = eeprom[83];
 637 -       bp->dev->dev_addr[5] = eeprom[82];
 638 -
 639 -       bp->phy_addr = eeprom[90] & 0x1f;
 640 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
 641 +               /*
 642 +                * BCM47xx boards don't have a EEPROM. The MAC is stored in
 643 +                * a NVRAM area somewhere in the flash memory. As we don't
 644 +                * know the location and/or the format of the NVRAM area
 645 +                * here, we simply rely on the bootloader to write the
 646 +                * MAC into the CAM.
 647 +                */
 648 +               spin_lock_irqsave(&bp->lock, flags);
 649 +               __b44_cam_read(bp, bp->dev->dev_addr, 0);
 650 +               spin_unlock_irqrestore(&bp->lock, flags);
 651 +
 652 +               /*
 653 +                * BCM47xx boards don't have a PHY. Usually there is a switch
 654 +                * chip with multiple PHYs connected to the PHY port.
 655 +                */
 656 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 657 +               bp->dma_offset = 0;
 658 +       } else {
 659 +               err = b44_read_eeprom(bp, &eeprom[0]);
 660 +               if (err)
 661 +                       return err;
 662 +
 663 +               bp->dev->dev_addr[0] = eeprom[79];
 664 +               bp->dev->dev_addr[1] = eeprom[78];
 665 +               bp->dev->dev_addr[2] = eeprom[81];
 666 +               bp->dev->dev_addr[3] = eeprom[80];
 667 +               bp->dev->dev_addr[4] = eeprom[83];
 668 +               bp->dev->dev_addr[5] = eeprom[82];
 669 +
 670 +               bp->phy_addr = eeprom[90] & 0x1f;
 671 +               bp->dma_offset = SB_PCI_DMA;
 672 +       }
 673
 674         /* With this, plus the rx_header prepended to the data by the
 675          * hardware, we'll land the ethernet header on a 2-byte boundary.
 676 @@ -1726,13 +1781,12 @@
 677         bp->imask = IMASK_DEF;
 678
 679         bp->core_unit = ssb_core_unit(bp);
 680 -       bp->dma_offset = SB_PCI_DMA;
 681
 682         /* XXX - really required?
 683            bp->flags |= B44_FLAG_BUGGY_TXPTR;
 684           */
 685 -out:
 686 -       return err;
 687 +
 688 +       return 0;
 689  }
 690
 691  static int __devinit b44_init_one(struct pci_dev *pdev,
 692 @@ -1810,7 +1864,7 @@
 693
 694         spin_lock_init(&bp->lock);
 695
 696 -       bp->regs = ioremap(b44reg_base, b44reg_len);
 697 +       bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
 698         if (bp->regs == 0UL) {
 699                 printk(KERN_ERR PFX "Cannot map device registers, "
 700                        "aborting.\n");
 701 @@ -1871,7 +1925,8 @@
 702
 703         pci_save_state(bp->pdev);
 704
 705 -       printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
 706 +       printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
 707 +               (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
 708         for (i = 0; i < 6; i++)
 709                 printk("%2.2x%c", dev->dev_addr[i],
 710                        i == 5 ? '\n' : ':');
 711 @@ -1879,7 +1934,7 @@
 712         return 0;
 713
 714  err_out_iounmap:
 715 -       iounmap(bp->regs);
 716 +       iounmap((void *) bp->regs);
 717
 718  err_out_free_dev:
 719         free_netdev(dev);
 720 @@ -1901,7 +1956,7 @@
 721                 struct b44 *bp = netdev_priv(dev);
 722
 723                 unregister_netdev(dev);
 724 -               iounmap(bp->regs);
 725 +               iounmap((void *) bp->regs);
 726                 free_netdev(dev);
 727                 pci_release_regions(pdev);
 728                 pci_disable_device(pdev);
 729 diff -Nur linux-2.6.12.5/drivers/net/b44.h linux-2.6.12.5-b44/drivers/net/b44.h
 730 --- linux-2.6.12.5/drivers/net/b44.h    2005-08-15 02:20:18.000000000 +0200
 731 +++ linux-2.6.12.5-b44/drivers/net/b44.h        2005-09-16 11:06:16.393533960 +0200
 732 @@ -292,6 +292,9 @@
 733  #define SSB_PCI_MASK1          0xfc000000
 734  #define SSB_PCI_MASK2          0xc0000000
 735
 736 +#define br32(REG)      readl((void *)bp->regs + (REG))
 737 +#define bw32(REG,VAL)  writel((VAL), (void *)bp->regs + (REG))
 738 +
 739  /* 4400 PHY registers */
 740  #define B44_MII_AUXCTRL                24      /* Auxiliary Control */
 741  #define  MII_AUXCTRL_DUPLEX    0x0001  /* Full Duplex */
 742 @@ -345,6 +348,8 @@
 743  };
 744
 745  #define B44_MCAST_TABLE_SIZE   32
 746 +#define B44_PHY_ADDR_NO_PHY    30
 747 +#define B44_MDC_RATIO          5000000
 748
 749  /* SW copy of device statistics, kept up to date by periodic timer
 750   * which probes HW values.  Must have same relative layout as HW
 751 @@ -410,7 +415,7 @@
 752         struct net_device_stats stats;
 753         struct b44_hw_stats     hw_stats;
 754
 755 -       void __iomem            *regs;
 756 +       unsigned long           regs;
 757         struct pci_dev          *pdev;
 758         struct net_device       *dev;
 759