target/linux/lantiq/patches/260-pci.patch

   1 --- a/arch/mips/pci/Makefile
   2 +++ b/arch/mips/pci/Makefile
   3 @@ -55,6 +55,7 @@
   4  obj-$(CONFIG_WR_PPMC)          += fixup-wrppmc.o
   5  obj-$(CONFIG_MIKROTIK_RB532)   += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
   6  obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += pci-octeon.o pcie-octeon.o
   7 +obj-$(CONFIG_LANTIQ)                   += pci-lantiq.o ops-lantiq.o
   8
   9  ifdef CONFIG_PCI_MSI
  10  obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += msi-octeon.o
  11 --- /dev/null
  12 +++ b/arch/mips/pci/ops-lantiq.c
  13 @@ -0,0 +1,127 @@
  14 +/*
  15 + *  This program is free software; you can redistribute it and/or modify it
  16 + *  under the terms of the GNU General Public License version 2 as published
  17 + *  by the Free Software Foundation.
  18 + *
  19 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  20 + */
  21 +
  22 +#include <linux/types.h>
  23 +#include <linux/pci.h>
  24 +#include <linux/kernel.h>
  25 +#include <linux/init.h>
  26 +#include <linux/delay.h>
  27 +#include <linux/mm.h>
  28 +#include <asm/addrspace.h>
  29 +#include <linux/vmalloc.h>
  30 +
  31 +#include <xway.h>
  32 +
  33 +#define LQ_PCI_CFG_BUSNUM_SHF 16
  34 +#define LQ_PCI_CFG_DEVNUM_SHF 11
  35 +#define LQ_PCI_CFG_FUNNUM_SHF 8
  36 +
  37 +#define PCI_ACCESS_READ  0
  38 +#define PCI_ACCESS_WRITE 1
  39 +
  40 +extern u32 lq_pci_mapped_cfg;
  41 +
  42 +static int
  43 +lq_pci_config_access(unsigned char access_type,
  44 +               struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
  45 +{
  46 +       unsigned long cfg_base;
  47 +       unsigned long flags;
  48 +
  49 +       u32 temp;
  50 +
  51 +       /* we support slot from 0 to 15 */
  52 +       /* dev_fn 0&0x68 (AD29) is ifxmips itself */
  53 +       if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
  54 +                       || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
  55 +               return 1;
  56 +
  57 +       spin_lock_irqsave(&ebu_lock, flags);
  58 +
  59 +       cfg_base = lq_pci_mapped_cfg;
  60 +       cfg_base |= (bus->number << LQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
  61 +                       LQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
  62 +
  63 +       /* Perform access */
  64 +       if (access_type == PCI_ACCESS_WRITE)
  65 +       {
  66 +#ifdef CONFIG_SWAP_IO_SPACE
  67 +               lq_w32(swab32(*data), ((u32*)cfg_base));
  68 +#else
  69 +               lq_w32(*data, ((u32*)cfg_base));
  70 +#endif
  71 +       } else {
  72 +               *data = lq_r32(((u32*)(cfg_base)));
  73 +#ifdef CONFIG_SWAP_IO_SPACE
  74 +               *data = swab32(*data);
  75 +#endif
  76 +       }
  77 +       wmb();
  78 +
  79 +       /* clean possible Master abort */
  80 +       cfg_base = (lq_pci_mapped_cfg | (0x0 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
  81 +       temp = lq_r32(((u32*)(cfg_base)));
  82 +#ifdef CONFIG_SWAP_IO_SPACE
  83 +       temp = swab32 (temp);
  84 +#endif
  85 +       cfg_base = (lq_pci_mapped_cfg | (0x68 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
  86 +       lq_w32(temp, ((u32*)cfg_base));
  87 +
  88 +       spin_unlock_irqrestore(&ebu_lock, flags);
  89 +
  90 +       if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
  91 +               return 1;
  92 +
  93 +       return 0;
  94 +}
  95 +
  96 +int
  97 +lq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
  98 +               int where, int size, u32 * val)
  99 +{
 100 +       u32 data = 0;
 101 +
 102 +       if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 103 +               return PCIBIOS_DEVICE_NOT_FOUND;
 104 +
 105 +       if (size == 1)
 106 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 107 +       else if (size == 2)
 108 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 109 +       else
 110 +               *val = data;
 111 +
 112 +       return PCIBIOS_SUCCESSFUL;
 113 +}
 114 +
 115 +int
 116 +lq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
 117 +               int where, int size, u32 val)
 118 +{
 119 +       u32 data = 0;
 120 +
 121 +       if (size == 4)
 122 +       {
 123 +               data = val;
 124 +       } else {
 125 +               if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 126 +                       return PCIBIOS_DEVICE_NOT_FOUND;
 127 +
 128 +               if (size == 1)
 129 +                       data = (data & ~(0xff << ((where & 3) << 3))) |
 130 +                               (val << ((where & 3) << 3));
 131 +               else if (size == 2)
 132 +                       data = (data & ~(0xffff << ((where & 3) << 3))) |
 133 +                               (val << ((where & 3) << 3));
 134 +       }
 135 +
 136 +       if (lq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 137 +               return PCIBIOS_DEVICE_NOT_FOUND;
 138 +
 139 +       return PCIBIOS_SUCCESSFUL;
 140 +}
 141 --- /dev/null
 142 +++ b/arch/mips/pci/pci-lantiq.c
 143 @@ -0,0 +1,303 @@
 144 +/*
 145 + *  This program is free software; you can redistribute it and/or modify it
 146 + *  under the terms of the GNU General Public License version 2 as published
 147 + *  by the Free Software Foundation.
 148 + *
 149 + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 150 + */
 151 +
 152 +#include <linux/types.h>
 153 +#include <linux/pci.h>
 154 +#include <linux/kernel.h>
 155 +#include <linux/init.h>
 156 +#include <linux/delay.h>
 157 +#include <linux/mm.h>
 158 +#include <linux/vmalloc.h>
 159 +#include <linux/platform_device.h>
 160 +
 161 +#include <asm/gpio.h>
 162 +#include <asm/addrspace.h>
 163 +
 164 +#include <xway.h>
 165 +#include <xway_irq.h>
 166 +#include <lantiq_platform.h>
 167 +
 168 +#define LQ_PCI_CFG_BASE                0x17000000
 169 +#define LQ_PCI_CFG_SIZE                0x00008000
 170 +#define LQ_PCI_MEM_BASE                0x18000000
 171 +#define LQ_PCI_MEM_SIZE                0x02000000
 172 +#define LQ_PCI_IO_BASE         0x1AE00000
 173 +#define LQ_PCI_IO_SIZE         0x00200000
 174 +
 175 +#define PCI_CR_FCI_ADDR_MAP0           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
 176 +#define PCI_CR_FCI_ADDR_MAP1           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
 177 +#define PCI_CR_FCI_ADDR_MAP2           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
 178 +#define PCI_CR_FCI_ADDR_MAP3           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
 179 +#define PCI_CR_FCI_ADDR_MAP4           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
 180 +#define PCI_CR_FCI_ADDR_MAP5           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
 181 +#define PCI_CR_FCI_ADDR_MAP6           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
 182 +#define PCI_CR_FCI_ADDR_MAP7           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
 183 +#define PCI_CR_CLK_CTRL                        ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
 184 +#define PCI_CR_PCI_IRM                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0028))
 185 +#define PCI_CR_PCI_MOD                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
 186 +#define PCI_CR_PC_ARB                  ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
 187 +#define PCI_CR_FCI_ADDR_MAP11hg                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
 188 +#define PCI_CR_BAR11MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
 189 +#define PCI_CR_BAR12MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
 190 +#define PCI_CR_BAR13MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
 191 +#define PCI_CR_PCI_ADDR_MAP11          ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
 192 +#define PCI_CR_FCI_BURST_LENGTH                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
 193 +#define PCI_CR_PCI_EOI                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
 194 +
 195 +#define PCI_CS_STS_CMD                 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
 196 +#define PCI_CS_BASE_ADDR1              ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
 197 +
 198 +#define PCI_MASTER0_REQ_MASK_2BITS     8
 199 +#define PCI_MASTER1_REQ_MASK_2BITS     10
 200 +#define PCI_MASTER2_REQ_MASK_2BITS     12
 201 +#define INTERNAL_ARB_ENABLE_BIT                0
 202 +
 203 +#define LQ_CGU_IFCCR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
 204 +#define LQ_CGU_PCICR           ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
 205 +
 206 +extern int lq_pci_read_config_dword(struct pci_bus *bus,
 207 +       unsigned int devfn, int where, int size, u32 *val);
 208 +extern int lq_pci_write_config_dword(struct pci_bus *bus,
 209 +       unsigned int devfn, int where, int size, u32 val);
 210 +
 211 +u32 lq_pci_mapped_cfg;
 212 +
 213 +int (*lqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
 214 +
 215 +/* Since the PCI REQ pins can be reused for other functionality, make it possible
 216 +   to exclude those from interpretation by the PCI controller */
 217 +static int lq_pci_req_mask = 0xf;
 218 +
 219 +static int *lq_pci_irq_map;
 220 +
 221 +struct pci_ops lq_pci_ops =
 222 +{
 223 +       .read = lq_pci_read_config_dword,
 224 +       .write = lq_pci_write_config_dword
 225 +};
 226 +
 227 +static struct resource pci_io_resource =
 228 +{
 229 +       .name = "pci io space",
 230 +       .start = LQ_PCI_IO_BASE,
 231 +       .end = LQ_PCI_IO_BASE + LQ_PCI_IO_SIZE - 1,
 232 +       .flags = IORESOURCE_IO
 233 +};
 234 +
 235 +static struct resource pci_mem_resource =
 236 +{
 237 +       .name = "pci memory space",
 238 +       .start = LQ_PCI_MEM_BASE,
 239 +       .end = LQ_PCI_MEM_BASE + LQ_PCI_MEM_SIZE - 1,
 240 +       .flags = IORESOURCE_MEM
 241 +};
 242 +
 243 +static struct pci_controller lq_pci_controller =
 244 +{
 245 +       .pci_ops = &lq_pci_ops,
 246 +       .mem_resource = &pci_mem_resource,
 247 +       .mem_offset     = 0x00000000UL,
 248 +       .io_resource = &pci_io_resource,
 249 +       .io_offset      = 0x00000000UL,
 250 +};
 251 +
 252 +int
 253 +pcibios_plat_dev_init(struct pci_dev *dev)
 254 +{
 255 +       if (lqpci_plat_dev_init)
 256 +               return lqpci_plat_dev_init(dev);
 257 +
 258 +       return 0;
 259 +}
 260 +
 261 +static u32
 262 +lq_calc_bar11mask(void)
 263 +{
 264 +       u32 mem, bar11mask;
 265 +
 266 +       /* BAR11MASK value depends on available memory on system. */
 267 +       mem = num_physpages * PAGE_SIZE;
 268 +       bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
 269 +
 270 +       return bar11mask;
 271 +}
 272 +
 273 +struct ltq_pci_gpio_map {
 274 +       int pin;
 275 +       int alt0;
 276 +       int alt1;
 277 +       int dir;
 278 +       char *name;
 279 +};
 280 +
 281 +static struct ltq_pci_gpio_map gmap[] = {
 282 +       { 0, 1, 0, 0, "pci-exin0" },
 283 +       { 1, 1, 0, 0, "pci-exin1" },
 284 +       { 2, 1, 0, 0, "pci-exin2" },
 285 +       { 30, 1, 0, 1, "pci-gnt1" },
 286 +       { 23, 1, 0, 1, "pci-gnt2" },
 287 +       { 19, 1, 0, 1, "pci-gnt3" },
 288 +       { 29, 1, 0, 0, "pci-req1" },
 289 +       { 31, 1, 0, 0, "pci-req2" },
 290 +       { 3, 1, 0, 0, "pci-req3" },
 291 +};
 292 +
 293 +static void
 294 +lq_pci_setup_gpio(int gpio)
 295 +{
 296 +       int i;
 297 +       for (i = 0; i < ARRAY_SIZE(gmap); i++)
 298 +       {
 299 +               if(gpio & (1 << i))
 300 +               {
 301 +                       lq_gpio_request(gmap[i].pin, gmap[i].alt0,
 302 +                               gmap[i].alt1, gmap[i].dir, gmap[i].name);
 303 +               }
 304 +       }
 305 +       for(i = 0; i < 3; i++)
 306 +       {
 307 +               if(gpio & (1 << i))
 308 +               {
 309 +                       lq_w32(lq_r32((u32*)0xBF101000) | (0x6 << (i * 4)), (u32*)0xBF101000);
 310 +                       lq_w32(lq_r32((u32*)0xBF101004) & ~(1 << i), (u32*)0xBF101004);
 311 +                       lq_w32(lq_r32((u32*)0xBF10100C) | (1 << i), (u32*)0xBF10100C);
 312 +               }
 313 +       }
 314 +       lq_gpio_request(21, 0, 0, 1, "pci-reset");
 315 +       lq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & 0x7;
 316 +}
 317 +
 318 +static int __init
 319 +lq_pci_startup(struct lq_pci_data *conf)
 320 +{
 321 +       u32 temp_buffer;
 322 +
 323 +       /* set clock to 33Mhz */
 324 +       lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
 325 +       lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR);
 326 +       if (conf->clock == PCI_CLOCK_EXT)
 327 +       {
 328 +               lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
 329 +               lq_w32((1 << 30), LQ_CGU_PCICR);
 330 +       } else {
 331 +               lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
 332 +               lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
 333 +       }
 334 +
 335 +       /* setup pci clock and gpis used by pci */
 336 +       lq_pci_setup_gpio(conf->gpio);
 337 +
 338 +       /* enable auto-switching between PCI and EBU */
 339 +       lq_w32(0xa, PCI_CR_CLK_CTRL);
 340 +
 341 +       /* busy, i.e. configuration is not done, PCI access has to be retried */
 342 +       lq_w32(lq_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 343 +       wmb ();
 344 +       /* BUS Master/IO/MEM access */
 345 +       lq_w32(lq_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 346 +
 347 +       /* enable external 2 PCI masters */
 348 +       temp_buffer = lq_r32(PCI_CR_PC_ARB);
 349 +       temp_buffer &= (~((lq_pci_req_mask & 0xf) << 16));
 350 +
 351 +       /* enable internal arbiter */
 352 +       temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 353 +       /* enable internal PCI master reqest */
 354 +       temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 355 +
 356 +       /* enable EBU request */
 357 +       temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 358 +
 359 +       /* enable all external masters request */
 360 +       temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 361 +       lq_w32(temp_buffer, PCI_CR_PC_ARB);
 362 +       wmb ();
 363 +
 364 +       /* setup BAR memory regions */
 365 +       lq_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 366 +       lq_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 367 +       lq_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 368 +       lq_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 369 +       lq_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 370 +       lq_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 371 +       lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 372 +       lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 373 +       lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 374 +
 375 +       lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
 376 +       lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
 377 +       lq_w32(0, PCI_CS_BASE_ADDR1);
 378 +
 379 +       /* both TX and RX endian swap are enabled */
 380 +       lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 381 +       wmb ();
 382 +
 383 +       /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
 384 +       lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
 385 +       lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
 386 +
 387 +       /* use 8 dw burst length */
 388 +       lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 389 +       lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 390 +       wmb();
 391 +
 392 +       /* setup irq line */
 393 +       lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
 394 +       lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
 395 +
 396 +       /* toggle reset pin */
 397 +       gpio_set_value(21, 0);
 398 +       wmb();
 399 +       mdelay(1);
 400 +       gpio_set_value(21, 1);
 401 +       return 0;
 402 +}
 403 +
 404 +int __init
 405 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
 406 +       printk("%s:%s[%d]%d %d\n", __FILE__, __func__, __LINE__, slot, pin);
 407 +       if(lq_pci_irq_map[slot])
 408 +               return lq_pci_irq_map[slot];
 409 +       printk("lq_pci: trying to map irq for unknown slot %d\n", slot);
 410 +       return 0;
 411 +}
 412 +
 413 +static int
 414 +lq_pci_probe(struct platform_device *pdev)
 415 +{
 416 +       struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
 417 +       extern int pci_probe_only;
 418 +       pci_probe_only = 0;
 419 +       lq_pci_irq_map = lq_pci_data->irq;
 420 +       lq_pci_startup(lq_pci_data);
 421 +       lq_pci_mapped_cfg =
 422 +               (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_SIZE);
 423 +       lq_pci_controller.io_map_base = mips_io_port_base + LQ_PCI_IO_BASE;
 424 +       register_pci_controller(&lq_pci_controller);
 425 +       return 0;
 426 +}
 427 +
 428 +static struct platform_driver
 429 +lq_pci_driver = {
 430 +       .probe = lq_pci_probe,
 431 +       .driver = {
 432 +               .name = "lq_pci",
 433 +               .owner = THIS_MODULE,
 434 +       },
 435 +};
 436 +
 437 +int __init
 438 +pcibios_init(void)
 439 +{
 440 +       int ret = platform_driver_register(&lq_pci_driver);
 441 +       if(ret)
 442 +               printk(KERN_INFO "lq_pci: Error registering platfom driver!");
 443 +       return ret;
 444 +}
 445 +
 446 +arch_initcall(pcibios_init);