1 diff -urN linux-2.6.22/arch/mips/Kconfig linux-2.6.22.new/arch/mips/Kconfig
2 --- linux-2.6.22/arch/mips/Kconfig 2007-07-09 01:32:17.000000000 +0200
3 +++ linux-2.6.22.new/arch/mips/Kconfig 2007-07-11 02:34:51.000000000 +0200
9 + bool "Texas Instruments AR7"
11 + select DMA_NONCOHERENT
14 + select SWAP_IO_SPACE
15 + select SYS_HAS_CPU_MIPS32_R1
16 + select SYS_HAS_EARLY_PRINTK
17 + select SYS_SUPPORTS_32BIT_KERNEL
18 + select SYS_SUPPORTS_KGDB
19 + select SYS_SUPPORTS_LITTLE_ENDIAN
23 bool "Alchemy processor based machines"
25 diff -urN linux-2.6.22/arch/mips/kernel/traps.c linux-2.6.22.new/arch/mips/kernel/traps.c
26 --- linux-2.6.22/arch/mips/kernel/traps.c 2007-07-09 01:32:17.000000000 +0200
27 +++ linux-2.6.22.new/arch/mips/kernel/traps.c 2007-07-11 02:32:39.000000000 +0200
28 @@ -1051,11 +1051,6 @@
29 unsigned long exception_handlers[32];
30 unsigned long vi_handlers[64];
33 - * As a side effect of the way this is implemented we're limited
34 - * to interrupt handlers in the address range from
35 - * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
37 void *set_except_vector(int n, void *addr)
39 unsigned long handler = (unsigned long) addr;
40 @@ -1063,9 +1058,15 @@
42 exception_handlers[n] = handler;
43 if (n == 0 && cpu_has_divec) {
44 - *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
45 - (0x03ffffff & (handler >> 2));
46 - flush_icache_range(ebase + 0x200, ebase + 0x204);
47 + /* lui k0, 0x0000 */
48 + *(volatile u32 *)(CAC_BASE+0x200) = 0x3c1a0000 | (handler >> 16);
49 + /* ori k0, 0x0000 */
50 + *(volatile u32 *)(CAC_BASE+0x204) = 0x375a0000 | (handler & 0xffff);
52 + *(volatile u32 *)(CAC_BASE+0x208) = 0x03400008;
54 + *(volatile u32 *)(CAC_BASE+0x20C) = 0x00000000;
55 + flush_icache_range(CAC_BASE+0x200, CAC_BASE+0x210);
57 return (void *)old_handler;
59 diff -urN linux-2.6.22/arch/mips/Makefile linux-2.6.22.new/arch/mips/Makefile
60 --- linux-2.6.22/arch/mips/Makefile 2007-07-09 01:32:17.000000000 +0200
61 +++ linux-2.6.22.new/arch/mips/Makefile 2007-07-11 02:32:39.000000000 +0200
66 +# Texas Instruments AR7
68 +core-$(CONFIG_AR7) += arch/mips/ar7/
69 +cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
70 +load-$(CONFIG_AR7) += 0xffffffff94100000
73 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
75 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/