Upgrade rt2x00 to a more recent snapshot, master mode now working, thanks to Daniel...
[openwrt.git] / package / acx / patches / 003-endianness-fixes.patch
1 Index: acx-20070101/pci.c
2 ===================================================================
3 --- acx-20070101.orig/pci.c 2007-06-04 13:22:42.557385576 +0200
4 +++ acx-20070101/pci.c 2007-06-04 13:22:42.946326448 +0200
5 @@ -123,6 +123,11 @@
6 ** Register access
7 */
8
9 +#define acx_readl(v) le32_to_cpu(readl((v)))
10 +#define acx_readw(v) le16_to_cpu(readw((v)))
11 +#define acx_writew(v,r) writew(le16_to_cpu((v)), r)
12 +#define acx_writel(v,r) writel(le32_to_cpu((v)), r)
13 +
14 /* Pick one */
15 /* #define INLINE_IO static */
16 #define INLINE_IO static inline
17 @@ -131,17 +136,17 @@
18 read_reg32(acx_device_t *adev, unsigned int offset)
19 {
20 #if ACX_IO_WIDTH == 32
21 - return readl((u8 *)adev->iobase + adev->io[offset]);
22 + return acx_readl((u8 *)adev->iobase + adev->io[offset]);
23 #else
24 - return readw((u8 *)adev->iobase + adev->io[offset])
25 - + (readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
26 + return acx_readw((u8 *)adev->iobase + adev->io[offset])
27 + + (acx_readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
28 #endif
29 }
30
31 INLINE_IO u16
32 read_reg16(acx_device_t *adev, unsigned int offset)
33 {
34 - return readw((u8 *)adev->iobase + adev->io[offset]);
35 + return acx_readw((u8 *)adev->iobase + adev->io[offset]);
36 }
37
38 INLINE_IO u8
39 @@ -154,17 +159,17 @@
40 write_reg32(acx_device_t *adev, unsigned int offset, u32 val)
41 {
42 #if ACX_IO_WIDTH == 32
43 - writel(val, (u8 *)adev->iobase + adev->io[offset]);
44 + acx_writel(val, (u8 *)adev->iobase + adev->io[offset]);
45 #else
46 - writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
47 - writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
48 + acx_writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
49 + acx_writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
50 #endif
51 }
52
53 INLINE_IO void
54 write_reg16(acx_device_t *adev, unsigned int offset, u16 val)
55 {
56 - writew(val, (u8 *)adev->iobase + adev->io[offset]);
57 + acx_writew(val, (u8 *)adev->iobase + adev->io[offset]);
58 }
59
60 INLINE_IO void
61 @@ -192,7 +197,7 @@
62 {
63 /* fast version (accesses the first register, IO_ACX_SOFT_RESET,
64 * which should be safe): */
65 - return readl(adev->iobase) != 0xffffffff;
66 + return acx_readl(adev->iobase) != 0xffffffff;
67 }
68
69
70 @@ -835,7 +840,7 @@
71 static inline void
72 acxpci_write_cmd_type_status(acx_device_t *adev, u16 type, u16 status)
73 {
74 - writel(type | (status << 16), adev->cmd_area);
75 + acx_writel(type | (status << 16), adev->cmd_area);
76 write_flush(adev);
77 }
78
79 @@ -848,7 +853,7 @@
80 {
81 u32 cmd_type, cmd_status;
82
83 - cmd_type = readl(adev->cmd_area);
84 + cmd_type = acx_readl(adev->cmd_area);
85 cmd_status = (cmd_type >> 16);
86 cmd_type = (u16)cmd_type;
87
88 @@ -2415,12 +2420,12 @@
89 #endif
90 u32 info_type, info_status;
91
92 - info_type = readl(adev->info_area);
93 + info_type = acx_readl(adev->info_area);
94 info_status = (info_type >> 16);
95 info_type = (u16)info_type;
96
97 /* inform fw that we have read this info message */
98 - writel(info_type | 0x00010000, adev->info_area);
99 + acx_writel(info_type | 0x00010000, adev->info_area);
100 write_reg16(adev, IO_ACX_INT_TRIG, INT_TRIG_INFOACK);
101 write_flush(adev);
102
103 @@ -4209,8 +4214,8 @@
104 #define ENDIANNESS_STRING "running on a BIG-ENDIAN CPU\n"
105 #endif
106 log(L_INIT,
107 - ENDIANNESS_STRING
108 - "PCI module " ACX_RELEASE " initialized, "
109 + "acx: " ENDIANNESS_STRING
110 + "acx: PCI module " ACX_RELEASE " initialized, "
111 "waiting for cards to probe...\n"
112 );
113
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